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repo_name stringlengths 6 79	path stringlengths 5 236	copies stringclasses 54 values	size stringlengths 1 8	content stringlengths 0 1.04M ⌀	license stringclasses 15 values
Bjay1435/capstone	Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd	5	74551	------------------------------------------------------------------------------- -- axi_datamover.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover.vhd -- -- Description: -- Top level VHDL wrapper for the AXI DataMover -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_11; use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ; use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ; use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap; use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ; use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ; use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap; ------------------------------------------------------------------------------- entity axi_datamover is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 2; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Basic MM2S functionality C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit MM2S Store and Forward -- 1 = Include MM2S Store and Forward C_INCLUDE_S2MM : Integer range 0 to 4 := 2; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Basic S2MM functionality C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) Store and Forward function -- 0 = Omit S2MM Store and Forward -- 1 = Include S2MM Store and Forward C_ENABLE_CACHE_USER : integer range 0 to 1 := 0; C_ENABLE_SKID_BUF : string := "11111"; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0; C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_CMD_WIDTH : integer range 72 to 112 := 72; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input ---------------------------------- m_axi_mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- m_axi_mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- MM2S Halt request input control -------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------- -- Error discrete output ------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------- -- Memory Map to Stream Command FIFO and Status FIFO I/O --------- m_axis_mm2s_cmdsts_aclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ------------------------------------------------- s_axis_mm2s_cmd_tvalid : in std_logic; -- s_axis_mm2s_cmd_tready : out std_logic; -- s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- ---------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------------ m_axis_mm2s_sts_tvalid : out std_logic; -- m_axis_mm2s_sts_tready : in std_logic; -- m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); -- m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); -- m_axis_mm2s_sts_tlast : out std_logic; -- -------------------------------------------------------------------- -- Address Posting contols ----------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- -------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------------------- m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); -- -- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); -- -- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); -- -- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------ m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); -- m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); -- m_axi_mm2s_rlast : In std_logic; -- m_axi_mm2s_rvalid : In std_logic; -- m_axi_mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------------- m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tlast : Out std_logic; -- m_axis_mm2s_tvalid : Out std_logic; -- m_axis_mm2s_tready : In std_logic; -- ---------------------------------------------------------------------------------------------- -- Testing Support I/O -------------------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) ; -- ------------------------------------------------------------------------------- -- S2MM Primary Clock input --------------------------------- m_axi_s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- S2MM Primary Reset input -- m_axi_s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- S2MM Halt request input control ------------------ s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : out std_logic; -- -- Active high soft shutdown complete status -- ----------------------------------------------------- -- S2MM Error discrete output ------------------ s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------ -- Memory Map to Stream Command FIFO and Status FIFO I/O ----------------- m_axis_s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) -------------------------------------------------- s_axis_s2mm_cmd_tvalid : in std_logic; -- s_axis_s2mm_cmd_tready : out std_logic; -- s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- ----------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ----------------------------------------------------------- m_axis_s2mm_sts_tvalid : out std_logic; -- m_axis_s2mm_sts_tready : in std_logic; -- m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT24)+8)-1 downto 0); -- m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0); -- m_axis_s2mm_sts_tlast : out std_logic; -- ------------------------------------------------------------------------------------------------------- -- Address posting controls ----------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- --------------------------------------------------------------------- -- S2MM AXI Address Channel I/O ---------------------------------------------------- m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); -- -- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); -- -- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); -- -- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O -------------------------------------------------- m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); -- m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); -- m_axi_s2mm_wlast : Out std_logic; -- m_axi_s2mm_wvalid : Out std_logic; -- m_axi_s2mm_wready : In std_logic; -- ------------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ------------------------- m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); -- m_axi_s2mm_bvalid : In std_logic; -- m_axi_s2mm_bready : Out std_logic; -- ---------------------------------------------------------------------- -- S2MM AXI Slave Stream Channel I/O ------------------------------------------------------- s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_tlast : In std_logic; -- s_axis_s2mm_tvalid : In std_logic; -- s_axis_s2mm_tready : Out std_logic; -- --------------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------------ ); end entity axi_datamover; architecture implementation of axi_datamover is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ------------------------------------------------------------------- -- Function -- -- Function Name: funct_clip_brst_len -- -- Function Description: -- This function is used to limit the parameterized max burst -- databeats when the tranfer data width is 256 bits or greater. -- This is required to keep from crossing the 4K byte xfer -- boundary required by AXI. This process is further complicated -- by the inclusion/omission of upsizers or downsizers in the -- data path. -- ------------------------------------------------------------------- function funct_clip_brst_len (param_burst_beats : integer; mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0); Variable fvar_max_burst_dbeats : Integer; begin if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc If (mmap_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (mmap_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (mmap_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit mmap width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; else -- use stream dwidth for calc If (stream_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (stream_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (stream_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit stream width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; end if; Return (fvar_max_burst_dbeats); end function funct_clip_brst_len; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_depth_16 -- -- Function Description: -- This function is used to fix the Command and Status FIFO depths to -- 16 entries when Async clocking mode is enabled. This is required -- due to the way the async_fifo_fg.vhd design in proc_common is -- implemented. ------------------------------------------------------------------- function funct_fix_depth_16 (async_clocking_mode : integer; requested_depth : integer) return integer is Variable fvar_depth_2_use : Integer; begin If (async_clocking_mode = 1) Then -- async mode so fix at 16 fvar_depth_2_use := 16; Elsif (requested_depth > 16) Then -- limit at 16 fvar_depth_2_use := 16; Else -- use requested depth fvar_depth_2_use := requested_depth; End if; Return (fvar_depth_2_use); end function funct_fix_depth_16; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_min_btt_width -- -- Function Description: -- This function calculates the minimum required value -- for the used width of the command BTT field. -- ------------------------------------------------------------------- function funct_get_min_btt_width (max_burst_beats : integer; bytes_per_beat : integer ) return integer is Variable var_min_btt_needed : Integer; Variable var_max_bytes_per_burst : Integer; begin var_max_bytes_per_burst := max_burst_beatsbytes_per_beat; if (var_max_bytes_per_burst <= 16) then var_min_btt_needed := 5; elsif (var_max_bytes_per_burst <= 32) then var_min_btt_needed := 6; elsif (var_max_bytes_per_burst <= 64) then var_min_btt_needed := 7; elsif (var_max_bytes_per_burst <= 128) then var_min_btt_needed := 8; elsif (var_max_bytes_per_burst <= 256) then var_min_btt_needed := 9; elsif (var_max_bytes_per_burst <= 512) then var_min_btt_needed := 10; elsif (var_max_bytes_per_burst <= 1024) then var_min_btt_needed := 11; elsif (var_max_bytes_per_burst <= 2048) then var_min_btt_needed := 12; elsif (var_max_bytes_per_burst <= 4096) then var_min_btt_needed := 13; else -- 8K byte range var_min_btt_needed := 14; end if; Return (var_min_btt_needed); end function funct_get_min_btt_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_xfer_bytes_per_dbeat -- -- Function Description: -- Calculates the nuber of bytes that will transfered per databeat -- on the AXI4 MMap Bus. -- ------------------------------------------------------------------- function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is Variable temp_bytes_per_dbeat : Integer := 4; begin if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth temp_bytes_per_dbeat := mmap_transfer_bit_width/8; else -- No down/up sizers so use Stream data width temp_bytes_per_dbeat := stream_transfer_bit_width/8; end if; Return (temp_bytes_per_dbeat); end function funct_get_xfer_bytes_per_dbeat; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_btt_used -- -- Function Description: -- THis function makes sure the BTT width used is at least the -- minimum needed. -- ------------------------------------------------------------------- function funct_fix_btt_used (requested_btt_width : integer; min_btt_width : integer) return integer is Variable var_corrected_btt_width : Integer; begin If (requested_btt_width < min_btt_width) Then var_corrected_btt_width := min_btt_width; else var_corrected_btt_width := requested_btt_width; End if; Return (var_corrected_btt_width); end function funct_fix_btt_used; function funct_fix_addr (in_addr_width : integer) return integer is Variable new_addr_width : Integer; begin If (in_addr_width <= 32) Then new_addr_width := 32; elsif (in_addr_width > 32 and in_addr_width <= 40) Then new_addr_width := 40; elsif (in_addr_width > 40 and in_addr_width <= 48) Then new_addr_width := 48; elsif (in_addr_width > 48 and in_addr_width <= 56) Then new_addr_width := 56; else new_addr_width := 64; End if; Return (new_addr_width); end function funct_fix_addr; ------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------- Constant MM2S_TAG_WIDTH : integer := 4; Constant S2MM_TAG_WIDTH : integer := 4; Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF; Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT; Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE, C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE, C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC, C_MM2S_STSCMD_FIFO_DEPTH); Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC, C_S2MM_STSCMD_FIFO_DEPTH); Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS, MM2S_BYTES_PER_BEAT); Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED, MM2S_MIN_BTT_NEEDED); Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS, S2MM_BYTES_PER_BEAT); Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED, S2MM_MIN_BTT_NEEDED); constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH); constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH); -- Signals signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0'); signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT24)+8)/8)-1 downto 0) := (others => '0'); signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ; signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ; begin --(architecture implementation) ------------------------------------------------------------- -- Conversion to tkeep for external stream connnections ------------------------------------------------------------- -- MM2S Status Stream Output m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ; GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate begin -- MM2S Stream Output m_axis_mm2s_tkeep <= sig_mm2s_tstrb ; end generate GEN_MM2S_TKEEP_ENABLE1; GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate begin m_axis_mm2s_tkeep <= (others => '1'); end generate GEN_MM2S_TKEEP_DISABLE1; GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- S2MM Stream Input sig_s2mm_tstrb <= s_axis_s2mm_tkeep ; end generate GEN_S2MM_TKEEP_ENABLE1; GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate begin sig_s2mm_tstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE1; -- S2MM Status Stream Output m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_OMIT -- -- If Generate Description: -- Instantiate the MM2S OMIT Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_OMIT_WRAPPER -- -- Description: -- Read omit Wrapper Instance -- ------------------------------------------------------------ I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr_int , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_FULL -- -- If Generate Description: -- Instantiate the MM2S Full Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_FULL_WRAPPER -- -- Description: -- Read Full Wrapper Instance -- ------------------------------------------------------------ I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr_int , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_BASIC -- -- If Generate Description: -- Instantiate the MM2S Basic Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_BASIC_WRAPPER -- -- Description: -- Read Basic Wrapper Instance -- ------------------------------------------------------------ I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr_int , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_BASIC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_OMIT -- -- If Generate Description: -- Instantiate the S2MM OMIT Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_OMIT_WRAPPER -- -- Description: -- Write Omit Wrapper Instance -- ------------------------------------------------------------ I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr_int , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_FULL -- -- If Generate Description: -- Instantiate the S2MM FULL Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_FULL_WRAPPER -- -- Description: -- Write Full Wrapper Instance -- ------------------------------------------------------------ I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr_int , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_BASIC -- -- If Generate Description: -- Instantiate the S2MM Basic Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_BASIC_WRAPPER -- -- Description: -- Write Basic Wrapper Instance -- ------------------------------------------------------------ I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr_int , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_BASIC; m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); end implementation;	mit
Bjay1435/capstone	Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mssai_skid_buf.vhd	5	24689	------------------------------------------------------------------------------- -- axi_datamover_mssai_skid_buf.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mssai_skid_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode that -- also incorporates the MS Strobe Asserted detection function needed by the -- module. This provides a register isolation of the MS asserted strobe index -- Scatter needed to improve Fmax. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_11; Use axi_datamover_v5_1_11.axi_datamover_ms_strb_set; ------------------------------------------------------------------------------- entity axi_datamover_mssai_skid_buf is generic ( C_WDATA_WIDTH : INTEGER range 8 to 1024 := 32 ; -- Width of the Stream Data bus (in bits) C_INDEX_WIDTH : Integer range 1 to 8 := 2 -- Sets the width of the MS asserted strobe index output value ); port ( -- Clock and Reset Ports ----------------------- aclk : In std_logic ; -- arst : In std_logic ; -- ------------------------------------------------ -- Shutdown control (assert for 1 clk pulse) --- skid_stop : In std_logic ; -- ------------------------------------------------ -- Slave Side (Stream Data Input) ------------------------------------ s_valid : In std_logic ; -- s_ready : Out std_logic ; -- s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- s_last : In std_logic ; -- ---------------------------------------------------------------------- -- Master Side (Stream Data Output ----------------------------------- m_valid : Out std_logic ; -- m_ready : In std_logic ; -- m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- m_last : Out std_logic ; -- -- m_mssa_index : Out std_logic_vector(C_INDEX_WIDTH-1 downto 0); -- m_strb_error : Out std_logic -- ---------------------------------------------------------------------- ); end entity axi_datamover_mssai_skid_buf; architecture implementation of axi_datamover_mssai_skid_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant declarations ------------------------- Constant STROBE_WIDTH : integer := C_WDATA_WIDTH/8; -- Signals declarations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_stop_request : std_logic := '0'; signal sig_stopped : std_logic := '0'; signal sig_sready_stop : std_logic := '0'; signal sig_sready_early_stop : std_logic := '0'; signal sig_sready_stop_set : std_logic := '0'; signal sig_sready_stop_reg : std_logic := '0'; signal sig_mvalid_stop_reg : std_logic := '0'; signal sig_mvalid_stop : std_logic := '0'; signal sig_mvalid_early_stop : std_logic := '0'; signal sig_mvalid_stop_set : std_logic := '0'; signal sig_slast_with_stop : std_logic := '0'; signal sig_sstrb_stop_mask : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_sstrb_with_stop : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_reg_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_error : std_logic := '0'; signal sig_strb_error_reg_out : std_logic := '0'; -- Fmax improvements signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_dup2 : std_logic := '0'; signal sig_s_ready_dup3 : std_logic := '0'; signal sig_s_ready_dup4 : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_skid_mux_sel2 : std_logic := '0'; signal sig_skid_mux_sel3 : std_logic := '0'; signal sig_skid_mux_sel4 : std_logic := '0'; -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup2 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup3 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup4 : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup2 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup3 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup4 : signal is "no"; begin --(architecture implementation) m_valid <= sig_m_valid_out; s_ready <= sig_s_ready_out; m_strb <= sig_strb_reg_out; m_last <= sig_last_reg_out; m_data <= sig_data_reg_out; m_mssa_index <= sig_mssa_index_reg_out; m_strb_error <= sig_strb_error_reg_out; -- Special shutdown logic version of Slast. -- A halt request forces a tlast through the skig buffer sig_slast_with_stop <= s_last or sig_stop_request; sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask; -- Assign the special s_ready FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup); -- Generate the skid input register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel2 <= not(sig_s_ready_dup2); sig_skid_mux_sel3 <= not(sig_s_ready_dup3); sig_skid_mux_sel4 <= not(sig_s_ready_dup4); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel2 = '1') Else s_data; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel3 = '1') Else sig_sstrb_with_stop; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel4 = '1') Else sig_slast_with_stop; -- m_valid combinational logic sig_m_valid_comb <= s_valid or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(m_ready))); -- s_ready combinational logic sig_s_ready_comb <= m_ready or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(s_valid))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (aclk) begin if (aclk'event and aclk = '1') then sig_reset_reg <= arst; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers s_ready handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_sready_stop = '1' or sig_sready_early_stop = '1') then -- Special stop condition sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; sig_s_ready_dup2 <= '0'; sig_s_ready_dup3 <= '0'; sig_s_ready_dup4 <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; sig_s_ready_dup2 <= '1'; sig_s_ready_dup3 <= '1'; sig_s_ready_dup4 <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; sig_s_ready_dup2 <= sig_s_ready_comb; sig_s_ready_dup3 <= sig_s_ready_comb; sig_s_ready_dup4 <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers m_valid handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA sig_mvalid_stop = '1' or sig_mvalid_stop_set = '1') then -- Special stop condition sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_DATA_REG -- -- Process Description: -- This process implements the skid register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- SKID_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_skid_reg_en = '1') then sig_data_skid_reg <= s_data; else null; -- hold current state end if; end if; end process SKID_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_CNTL_REG -- -- Process Description: -- This process implements the skid registers for the -- Skid Buffer control signals -- ------------------------------------------------------------- SKID_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_strb_skid_reg <= sig_sstrb_with_stop; sig_last_skid_reg <= sig_slast_with_stop; else null; -- hold current state end if; end if; end process SKID_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_DATA_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- OUTPUT_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_CNTL_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Control signals. -- ------------------------------------------------------------- OUTPUT_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_CNTL_REG; -------- Special Stop Logic -------------------------------------- sig_sready_stop <= sig_sready_stop_reg; sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately sig_sready_stop_set <= sig_sready_early_stop; sig_mvalid_stop <= sig_mvalid_stop_reg; sig_mvalid_early_stop <= sig_m_valid_dup and m_ready and skid_stop; sig_mvalid_stop_set <= sig_mvalid_early_stop or (sig_stop_request and not(sig_m_valid_dup)) or (sig_m_valid_dup and m_ready and sig_stop_request); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STOP_REQ_FLOP -- -- Process Description: -- This process implements the Stop request flop. It is a -- sample and hold register that can only be cleared by reset. -- ------------------------------------------------------------- IMP_STOP_REQ_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_stop_request <= '0'; sig_sstrb_stop_mask <= (others => '0'); elsif (skid_stop = '1') then sig_stop_request <= '1'; sig_sstrb_stop_mask <= (others => '1'); else null; -- hold current state end if; end if; end process IMP_STOP_REQ_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_SREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the s_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_SREADY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_sready_stop_reg <= '0'; elsif (sig_sready_stop_set = '1') then sig_sready_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_SREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_MVALID_FLOP -- -- Process Description: -- This process implements the flag to clear the m_valid -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_MVALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_mvalid_stop_reg <= '0'; elsif (sig_mvalid_stop_set = '1') then sig_mvalid_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_MVALID_FLOP; ---------------------------------------------------------------------------- -- Logic for the detection of the most significant asserted strobe bit and -- the formulation of the index of that strobe bit. ---------------------------------------------------------------------------- ------------------------------------------------------------ -- Instance: I_MSSAI_DETECTION -- -- Description: -- This module detects the most significant asserted strobe -- and outputs the bit index of the strobe. -- ------------------------------------------------------------ I_MSSAI_DETECTION : entity axi_datamover_v5_1_11.axi_datamover_ms_strb_set generic map ( C_STRB_WIDTH => STROBE_WIDTH , C_INDEX_WIDTH => C_INDEX_WIDTH ) port map ( -- Input Stream Strobes strbs_in => sig_strb_skid_mux_out , -- Index of the most significant strobe asserted ms_strb_index => sig_mssa_index_out , -- Output flag for a detected error associated Strobe assertions strb_error => sig_strb_error ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSSAI_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer's MSSAI value and the strobe error bit -- that is needed by the Scatter module. -- ------------------------------------------------------------- IMP_MSSAI_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_mssa_index_reg_out <= (others => '0'); sig_strb_error_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_mssa_index_reg_out <= sig_mssa_index_out; sig_strb_error_reg_out <= sig_strb_error; else null; -- hold current state end if; end if; end process IMP_MSSAI_REG; end implementation;	mit
Bjay1435/capstone	Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd	18	75691	------------------------------------------------------------------------------- -- axi_datamover_wr_demux.vhd ------------------------------------------------------------------------------- -- -- *********************************************************************** -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- *********************************************************************** -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_demux.vhd -- -- Description: -- This file implements the DataMover Master Write Strobe De-Multiplexer. -- This is needed when the native data width of the DataMover is narrower -- than the AXI4 Write Data Channel. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_wr_demux is generic ( C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the select control bus C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the width of the AXI4 Write Data Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32 -- Indicates the native data width of the DataMover S2MM. If -- S2MM Store and Forward with upsizer is enabled, the width is -- the AXi4 Write Data Channel, else it is the S2MM Stream data width. ); port ( -- AXI MMap Data Channel Input -------------------------------------------- -- wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- data input -- ---------------------------------------------------------------------------- -- AXI Master Stream ------------------------------------------------------ -- demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); -- --De-Mux strb output -- ---------------------------------------------------------------------------- -- Command Calculator Interface -------------------------------------------- -- debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap Data -- -- Width). -- ---------------------------------------------------------------------------- ); end entity axi_datamover_wr_demux; architecture implementation of axi_datamover_wr_demux is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Decalarations ------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_mux_sel_width -- -- Function Description: -- Calculates the number of needed bits for the Mux Select control -- based on the number of input channels to the mux. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_mux_sel_width (num_channels : integer) return integer is Variable var_sel_width : integer := 0; begin case num_channels is --when 2 => -- var_sel_width := 1; when 4 => var_sel_width := 2; when 8 => var_sel_width := 3; when 16 => var_sel_width := 4; when 32 => var_sel_width := 5; when 64 => var_sel_width := 6; when 128 => var_sel_width := 7; when others => var_sel_width := 1; end case; Return (var_sel_width); end function func_mux_sel_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_sel_ls_index -- -- Function Description: -- Calculates the LS index of the select field to rip from the -- input select bus. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_sel_ls_index (stream_width : integer) return integer is Variable var_sel_ls_index : integer := 0; begin case stream_width is when 8 => var_sel_ls_index := 0; when 16 => var_sel_ls_index := 1; when 32 => var_sel_ls_index := 2; when 64 => var_sel_ls_index := 3; when 128 => var_sel_ls_index := 4; when 256 => var_sel_ls_index := 5; when 512 => var_sel_ls_index := 6; when others => -- assume 1024 bit width var_sel_ls_index := 7; end case; Return (var_sel_ls_index); end function func_sel_ls_index; -- Constant Decalarations ------------------------------------------------- Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH); Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX); Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8; Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH; Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS); Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH); -- Signal Declarations -------------------------------------------- signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) -- Assign the Output data port demux_wstrb_out <= sig_demux_wstrb_out; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_STRM_EQ_MMAP -- -- If Generate Description: -- This IfGen implements the case where the Stream Data Width is -- the same as the Memeory Map read Data width. -- -- ------------------------------------------------------------ GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate begin sig_demux_wstrb_out <= wstrb_in; end generate GEN_STRM_EQ_MMAP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2XN -- -- If Generate Description: -- 2 channel demux case -- -- ------------------------------------------------------------ GEN_2XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 2) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_2XN_DEMUX -- -- Process Description: -- Implement the 2XN DeMux -- ------------------------------------------------------------- DO_2XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when others => -- 1 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH2)-1 downto STREAM_WSTB_WIDTH1) <= wstrb_in; end case; end process DO_2XN_DEMUX; end generate GEN_2XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4XN -- -- If Generate Description: -- 4 channel demux case -- -- ------------------------------------------------------------ GEN_4XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 4) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_4XN_DEMUX -- -- Process Description: -- Implement the 4XN DeMux -- ------------------------------------------------------------- DO_4XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH2)-1 downto STREAM_WSTB_WIDTH1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH3)-1 downto STREAM_WSTB_WIDTH2) <= wstrb_in; when others => -- 3 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH4)-1 downto STREAM_WSTB_WIDTH3) <= wstrb_in; end case; end process DO_4XN_DEMUX; end generate GEN_4XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8XN -- -- If Generate Description: -- 8 channel demux case -- -- ------------------------------------------------------------ GEN_8XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 8) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_8XN_DEMUX -- -- Process Description: -- Implement the 8XN DeMux -- ------------------------------------------------------------- DO_8XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH2)-1 downto STREAM_WSTB_WIDTH1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH3)-1 downto STREAM_WSTB_WIDTH2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH4)-1 downto STREAM_WSTB_WIDTH3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH5)-1 downto STREAM_WSTB_WIDTH4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH6)-1 downto STREAM_WSTB_WIDTH5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH7)-1 downto STREAM_WSTB_WIDTH6) <= wstrb_in; when others => -- 7 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH8)-1 downto STREAM_WSTB_WIDTH7) <= wstrb_in; end case; end process DO_8XN_DEMUX; end generate GEN_8XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16XN -- -- If Generate Description: -- 16 channel demux case -- -- ------------------------------------------------------------ GEN_16XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 16) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_16XN_DEMUX -- -- Process Description: -- Implement the 16XN DeMux -- ------------------------------------------------------------- DO_16XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH2)-1 downto STREAM_WSTB_WIDTH1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH3)-1 downto STREAM_WSTB_WIDTH2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH4)-1 downto STREAM_WSTB_WIDTH3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH5)-1 downto STREAM_WSTB_WIDTH4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH6)-1 downto STREAM_WSTB_WIDTH5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH7)-1 downto STREAM_WSTB_WIDTH6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH8)-1 downto STREAM_WSTB_WIDTH7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH9)-1 downto STREAM_WSTB_WIDTH8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH10)-1 downto STREAM_WSTB_WIDTH9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH11)-1 downto STREAM_WSTB_WIDTH10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH12)-1 downto STREAM_WSTB_WIDTH11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH13)-1 downto STREAM_WSTB_WIDTH12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH14)-1 downto STREAM_WSTB_WIDTH13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH15)-1 downto STREAM_WSTB_WIDTH14) <= wstrb_in; when others => -- 15 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH16)-1 downto STREAM_WSTB_WIDTH15) <= wstrb_in; end case; end process DO_16XN_DEMUX; end generate GEN_16XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32XN -- -- If Generate Description: -- 32 channel demux case -- -- ------------------------------------------------------------ GEN_32XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 32) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_32XN_DEMUX -- -- Process Description: -- Implement the 32XN DeMux -- ------------------------------------------------------------- DO_32XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH2)-1 downto STREAM_WSTB_WIDTH1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH3)-1 downto STREAM_WSTB_WIDTH2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH4)-1 downto STREAM_WSTB_WIDTH3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH5)-1 downto STREAM_WSTB_WIDTH4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH6)-1 downto STREAM_WSTB_WIDTH5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH7)-1 downto STREAM_WSTB_WIDTH6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH8)-1 downto STREAM_WSTB_WIDTH7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH9)-1 downto STREAM_WSTB_WIDTH8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH10)-1 downto STREAM_WSTB_WIDTH9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH11)-1 downto STREAM_WSTB_WIDTH10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH12)-1 downto STREAM_WSTB_WIDTH11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH13)-1 downto STREAM_WSTB_WIDTH12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH14)-1 downto STREAM_WSTB_WIDTH13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH15)-1 downto STREAM_WSTB_WIDTH14) <= wstrb_in; when 15 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH16)-1 downto STREAM_WSTB_WIDTH15) <= wstrb_in; when 16 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH17)-1 downto STREAM_WSTB_WIDTH16) <= wstrb_in; when 17 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH18)-1 downto STREAM_WSTB_WIDTH17) <= wstrb_in; when 18 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH19)-1 downto STREAM_WSTB_WIDTH18) <= wstrb_in; when 19 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH20)-1 downto STREAM_WSTB_WIDTH19) <= wstrb_in; when 20 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH21)-1 downto STREAM_WSTB_WIDTH20) <= wstrb_in; when 21 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH22)-1 downto STREAM_WSTB_WIDTH21) <= wstrb_in; when 22 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH23)-1 downto STREAM_WSTB_WIDTH22) <= wstrb_in; when 23 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH24)-1 downto STREAM_WSTB_WIDTH23) <= wstrb_in; when 24 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH25)-1 downto STREAM_WSTB_WIDTH24) <= wstrb_in; when 25 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH26)-1 downto STREAM_WSTB_WIDTH25) <= wstrb_in; when 26 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH27)-1 downto STREAM_WSTB_WIDTH26) <= wstrb_in; when 27 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH28)-1 downto STREAM_WSTB_WIDTH27) <= wstrb_in; when 28 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH29)-1 downto STREAM_WSTB_WIDTH28) <= wstrb_in; when 29 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH30)-1 downto STREAM_WSTB_WIDTH29) <= wstrb_in; when 30 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH31)-1 downto STREAM_WSTB_WIDTH30) <= wstrb_in; when others => -- 31 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH32)-1 downto STREAM_WSTB_WIDTH31) <= wstrb_in; end case; end process DO_32XN_DEMUX; end generate GEN_32XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64XN -- -- If Generate Description: -- 64 channel demux case -- -- ------------------------------------------------------------ GEN_64XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 64) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_64XN_DEMUX -- -- Process Description: -- Implement the 32XN DeMux -- ------------------------------------------------------------- DO_64XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH2)-1 downto STREAM_WSTB_WIDTH1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH3)-1 downto STREAM_WSTB_WIDTH2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH4)-1 downto STREAM_WSTB_WIDTH3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH5)-1 downto STREAM_WSTB_WIDTH4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH6)-1 downto STREAM_WSTB_WIDTH5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH7)-1 downto STREAM_WSTB_WIDTH6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH8)-1 downto STREAM_WSTB_WIDTH7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH9)-1 downto STREAM_WSTB_WIDTH8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH10)-1 downto STREAM_WSTB_WIDTH9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH11)-1 downto STREAM_WSTB_WIDTH10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH12)-1 downto STREAM_WSTB_WIDTH11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH13)-1 downto STREAM_WSTB_WIDTH12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH14)-1 downto STREAM_WSTB_WIDTH13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH15)-1 downto STREAM_WSTB_WIDTH14) <= wstrb_in; when 15 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH16)-1 downto STREAM_WSTB_WIDTH15) <= wstrb_in; when 16 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH17)-1 downto STREAM_WSTB_WIDTH16) <= wstrb_in; when 17 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH18)-1 downto STREAM_WSTB_WIDTH17) <= wstrb_in; when 18 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH19)-1 downto STREAM_WSTB_WIDTH18) <= wstrb_in; when 19 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH20)-1 downto STREAM_WSTB_WIDTH19) <= wstrb_in; when 20 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH21)-1 downto STREAM_WSTB_WIDTH20) <= wstrb_in; when 21 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH22)-1 downto STREAM_WSTB_WIDTH21) <= wstrb_in; when 22 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH23)-1 downto STREAM_WSTB_WIDTH22) <= wstrb_in; when 23 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH24)-1 downto STREAM_WSTB_WIDTH23) <= wstrb_in; when 24 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH25)-1 downto STREAM_WSTB_WIDTH24) <= wstrb_in; when 25 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH26)-1 downto STREAM_WSTB_WIDTH25) <= wstrb_in; when 26 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH27)-1 downto STREAM_WSTB_WIDTH26) <= wstrb_in; when 27 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH28)-1 downto STREAM_WSTB_WIDTH27) <= wstrb_in; when 28 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH29)-1 downto STREAM_WSTB_WIDTH28) <= wstrb_in; when 29 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH30)-1 downto STREAM_WSTB_WIDTH29) <= wstrb_in; when 30 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH31)-1 downto STREAM_WSTB_WIDTH30) <= wstrb_in; when 31 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH32)-1 downto STREAM_WSTB_WIDTH31) <= wstrb_in; when 32 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH33)-1 downto STREAM_WSTB_WIDTH32) <= wstrb_in; when 33 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH34)-1 downto STREAM_WSTB_WIDTH33) <= wstrb_in; when 34 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH35)-1 downto STREAM_WSTB_WIDTH34) <= wstrb_in; when 35 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH36)-1 downto STREAM_WSTB_WIDTH35) <= wstrb_in; when 36 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH37)-1 downto STREAM_WSTB_WIDTH36) <= wstrb_in; when 37 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH38)-1 downto STREAM_WSTB_WIDTH37) <= wstrb_in; when 38 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH39)-1 downto STREAM_WSTB_WIDTH38) <= wstrb_in; when 39 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH40)-1 downto STREAM_WSTB_WIDTH39) <= wstrb_in; when 40 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH41)-1 downto STREAM_WSTB_WIDTH40) <= wstrb_in; when 41 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH42)-1 downto STREAM_WSTB_WIDTH41) <= wstrb_in; when 42 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH43)-1 downto STREAM_WSTB_WIDTH42) <= wstrb_in; when 43 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH44)-1 downto STREAM_WSTB_WIDTH43) <= wstrb_in; when 44 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH45)-1 downto STREAM_WSTB_WIDTH44) <= wstrb_in; when 45 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH46)-1 downto STREAM_WSTB_WIDTH45) <= wstrb_in; when 46 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH47)-1 downto STREAM_WSTB_WIDTH46) <= wstrb_in; when 47 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH48)-1 downto STREAM_WSTB_WIDTH47) <= wstrb_in; when 48 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH49)-1 downto STREAM_WSTB_WIDTH48) <= wstrb_in; when 49 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH50)-1 downto STREAM_WSTB_WIDTH49) <= wstrb_in; when 50 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH51)-1 downto STREAM_WSTB_WIDTH50) <= wstrb_in; when 51 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH52)-1 downto STREAM_WSTB_WIDTH51) <= wstrb_in; when 52 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH53)-1 downto STREAM_WSTB_WIDTH52) <= wstrb_in; when 53 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH54)-1 downto STREAM_WSTB_WIDTH53) <= wstrb_in; when 54 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH55)-1 downto STREAM_WSTB_WIDTH54) <= wstrb_in; when 55 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH56)-1 downto STREAM_WSTB_WIDTH55) <= wstrb_in; when 56 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH57)-1 downto STREAM_WSTB_WIDTH56) <= wstrb_in; when 57 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH58)-1 downto STREAM_WSTB_WIDTH57) <= wstrb_in; when 58 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH59)-1 downto STREAM_WSTB_WIDTH58) <= wstrb_in; when 59 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH60)-1 downto STREAM_WSTB_WIDTH59) <= wstrb_in; when 60 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH61)-1 downto STREAM_WSTB_WIDTH60) <= wstrb_in; when 61 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH62)-1 downto STREAM_WSTB_WIDTH61) <= wstrb_in; when 62 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH63)-1 downto STREAM_WSTB_WIDTH62) <= wstrb_in; when others => -- 63 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH64)-1 downto STREAM_WSTB_WIDTH63) <= wstrb_in; end case; end process DO_64XN_DEMUX; end generate GEN_64XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128XN -- -- If Generate Description: -- 128 channel demux case -- -- ------------------------------------------------------------ GEN_128XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 128) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_128XN_DEMUX -- -- Process Description: -- Implement the 32XN DeMux -- ------------------------------------------------------------- DO_128XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH2)-1 downto STREAM_WSTB_WIDTH1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH3)-1 downto STREAM_WSTB_WIDTH2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH4)-1 downto STREAM_WSTB_WIDTH3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH5)-1 downto STREAM_WSTB_WIDTH4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH6)-1 downto STREAM_WSTB_WIDTH5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH7)-1 downto STREAM_WSTB_WIDTH6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH8)-1 downto STREAM_WSTB_WIDTH7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH9)-1 downto STREAM_WSTB_WIDTH8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH10)-1 downto STREAM_WSTB_WIDTH9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH11)-1 downto STREAM_WSTB_WIDTH10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH12)-1 downto STREAM_WSTB_WIDTH11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH13)-1 downto STREAM_WSTB_WIDTH12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH14)-1 downto STREAM_WSTB_WIDTH13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH15)-1 downto STREAM_WSTB_WIDTH14) <= wstrb_in; when 15 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH16)-1 downto STREAM_WSTB_WIDTH15) <= wstrb_in; when 16 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH17)-1 downto STREAM_WSTB_WIDTH16) <= wstrb_in; when 17 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH18)-1 downto STREAM_WSTB_WIDTH17) <= wstrb_in; when 18 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH19)-1 downto STREAM_WSTB_WIDTH18) <= wstrb_in; when 19 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH20)-1 downto STREAM_WSTB_WIDTH19) <= wstrb_in; when 20 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH21)-1 downto STREAM_WSTB_WIDTH20) <= wstrb_in; when 21 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH22)-1 downto STREAM_WSTB_WIDTH21) <= wstrb_in; when 22 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH23)-1 downto STREAM_WSTB_WIDTH22) <= wstrb_in; when 23 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH24)-1 downto STREAM_WSTB_WIDTH23) <= wstrb_in; when 24 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH25)-1 downto STREAM_WSTB_WIDTH24) <= wstrb_in; when 25 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH26)-1 downto STREAM_WSTB_WIDTH25) <= wstrb_in; when 26 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH27)-1 downto STREAM_WSTB_WIDTH26) <= wstrb_in; when 27 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH28)-1 downto STREAM_WSTB_WIDTH27) <= wstrb_in; when 28 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH29)-1 downto STREAM_WSTB_WIDTH28) <= wstrb_in; when 29 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH30)-1 downto STREAM_WSTB_WIDTH29) <= wstrb_in; when 30 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH31)-1 downto STREAM_WSTB_WIDTH30) <= wstrb_in; when 31 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH32)-1 downto STREAM_WSTB_WIDTH31) <= wstrb_in; when 32 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH33)-1 downto STREAM_WSTB_WIDTH32) <= wstrb_in; when 33 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH34)-1 downto STREAM_WSTB_WIDTH33) <= wstrb_in; when 34 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH35)-1 downto STREAM_WSTB_WIDTH34) <= wstrb_in; when 35 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH36)-1 downto STREAM_WSTB_WIDTH35) <= wstrb_in; when 36 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH37)-1 downto STREAM_WSTB_WIDTH36) <= wstrb_in; when 37 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH38)-1 downto STREAM_WSTB_WIDTH37) <= wstrb_in; when 38 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH39)-1 downto STREAM_WSTB_WIDTH38) <= wstrb_in; when 39 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH40)-1 downto STREAM_WSTB_WIDTH39) <= wstrb_in; when 40 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH41)-1 downto STREAM_WSTB_WIDTH40) <= wstrb_in; when 41 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH42)-1 downto STREAM_WSTB_WIDTH41) <= wstrb_in; when 42 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH43)-1 downto STREAM_WSTB_WIDTH42) <= wstrb_in; when 43 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH44)-1 downto STREAM_WSTB_WIDTH43) <= wstrb_in; when 44 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH45)-1 downto STREAM_WSTB_WIDTH44) <= wstrb_in; when 45 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH46)-1 downto STREAM_WSTB_WIDTH45) <= wstrb_in; when 46 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH47)-1 downto STREAM_WSTB_WIDTH46) <= wstrb_in; when 47 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH48)-1 downto STREAM_WSTB_WIDTH47) <= wstrb_in; when 48 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH49)-1 downto STREAM_WSTB_WIDTH48) <= wstrb_in; when 49 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH50)-1 downto STREAM_WSTB_WIDTH49) <= wstrb_in; when 50 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH51)-1 downto STREAM_WSTB_WIDTH50) <= wstrb_in; when 51 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH52)-1 downto STREAM_WSTB_WIDTH51) <= wstrb_in; when 52 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH53)-1 downto STREAM_WSTB_WIDTH52) <= wstrb_in; when 53 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH54)-1 downto STREAM_WSTB_WIDTH53) <= wstrb_in; when 54 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH55)-1 downto STREAM_WSTB_WIDTH54) <= wstrb_in; when 55 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH56)-1 downto STREAM_WSTB_WIDTH55) <= wstrb_in; when 56 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH57)-1 downto STREAM_WSTB_WIDTH56) <= wstrb_in; when 57 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH58)-1 downto STREAM_WSTB_WIDTH57) <= wstrb_in; when 58 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH59)-1 downto STREAM_WSTB_WIDTH58) <= wstrb_in; when 59 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH60)-1 downto STREAM_WSTB_WIDTH59) <= wstrb_in; when 60 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH61)-1 downto STREAM_WSTB_WIDTH60) <= wstrb_in; when 61 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH62)-1 downto STREAM_WSTB_WIDTH61) <= wstrb_in; when 62 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH63)-1 downto STREAM_WSTB_WIDTH62) <= wstrb_in; when 63 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH64)-1 downto STREAM_WSTB_WIDTH63) <= wstrb_in; when 64 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH65)-1 downto STREAM_WSTB_WIDTH64) <= wstrb_in; when 65 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH66)-1 downto STREAM_WSTB_WIDTH65) <= wstrb_in; when 66 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH67)-1 downto STREAM_WSTB_WIDTH66) <= wstrb_in; when 67 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH68)-1 downto STREAM_WSTB_WIDTH67) <= wstrb_in; when 68 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH69)-1 downto STREAM_WSTB_WIDTH68) <= wstrb_in; when 69 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH70)-1 downto STREAM_WSTB_WIDTH69) <= wstrb_in; when 70 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH71)-1 downto STREAM_WSTB_WIDTH70) <= wstrb_in; when 71 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH72)-1 downto STREAM_WSTB_WIDTH71) <= wstrb_in; when 72 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH73)-1 downto STREAM_WSTB_WIDTH72) <= wstrb_in; when 73 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH74)-1 downto STREAM_WSTB_WIDTH73) <= wstrb_in; when 74 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH75)-1 downto STREAM_WSTB_WIDTH74) <= wstrb_in; when 75 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH76)-1 downto STREAM_WSTB_WIDTH75) <= wstrb_in; when 76 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH77)-1 downto STREAM_WSTB_WIDTH76) <= wstrb_in; when 77 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH78)-1 downto STREAM_WSTB_WIDTH77) <= wstrb_in; when 78 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH79)-1 downto STREAM_WSTB_WIDTH78) <= wstrb_in; when 79 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH80)-1 downto STREAM_WSTB_WIDTH79) <= wstrb_in; when 80 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH81)-1 downto STREAM_WSTB_WIDTH80) <= wstrb_in; when 81 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH82)-1 downto STREAM_WSTB_WIDTH81) <= wstrb_in; when 82 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH83)-1 downto STREAM_WSTB_WIDTH82) <= wstrb_in; when 83 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH84)-1 downto STREAM_WSTB_WIDTH83) <= wstrb_in; when 84 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH85)-1 downto STREAM_WSTB_WIDTH84) <= wstrb_in; when 85 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH86)-1 downto STREAM_WSTB_WIDTH85) <= wstrb_in; when 86 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH87)-1 downto STREAM_WSTB_WIDTH86) <= wstrb_in; when 87 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH88)-1 downto STREAM_WSTB_WIDTH87) <= wstrb_in; when 88 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH89)-1 downto STREAM_WSTB_WIDTH88) <= wstrb_in; when 89 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH90)-1 downto STREAM_WSTB_WIDTH89) <= wstrb_in; when 90 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH91)-1 downto STREAM_WSTB_WIDTH90) <= wstrb_in; when 91 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH92)-1 downto STREAM_WSTB_WIDTH91) <= wstrb_in; when 92 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH93)-1 downto STREAM_WSTB_WIDTH92) <= wstrb_in; when 93 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH94)-1 downto STREAM_WSTB_WIDTH93) <= wstrb_in; when 94 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH95)-1 downto STREAM_WSTB_WIDTH94) <= wstrb_in; when 95 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH96)-1 downto STREAM_WSTB_WIDTH95) <= wstrb_in; when 96 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH97 )-1 downto STREAM_WSTB_WIDTH96 ) <= wstrb_in; when 97 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH98 )-1 downto STREAM_WSTB_WIDTH97 ) <= wstrb_in; when 98 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH99 )-1 downto STREAM_WSTB_WIDTH98 ) <= wstrb_in; when 99 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH100)-1 downto STREAM_WSTB_WIDTH99 ) <= wstrb_in; when 100 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH101)-1 downto STREAM_WSTB_WIDTH100) <= wstrb_in; when 101 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH102)-1 downto STREAM_WSTB_WIDTH101) <= wstrb_in; when 102 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH103)-1 downto STREAM_WSTB_WIDTH102) <= wstrb_in; when 103 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH104)-1 downto STREAM_WSTB_WIDTH103) <= wstrb_in; when 104 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH105)-1 downto STREAM_WSTB_WIDTH104) <= wstrb_in; when 105 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH106)-1 downto STREAM_WSTB_WIDTH105) <= wstrb_in; when 106 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH107)-1 downto STREAM_WSTB_WIDTH106) <= wstrb_in; when 107 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH108)-1 downto STREAM_WSTB_WIDTH107) <= wstrb_in; when 108 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH109)-1 downto STREAM_WSTB_WIDTH108) <= wstrb_in; when 109 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH110)-1 downto STREAM_WSTB_WIDTH109) <= wstrb_in; when 110 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH111)-1 downto STREAM_WSTB_WIDTH110) <= wstrb_in; when 111 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH112)-1 downto STREAM_WSTB_WIDTH111) <= wstrb_in; when 112 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH113)-1 downto STREAM_WSTB_WIDTH112) <= wstrb_in; when 113 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH114)-1 downto STREAM_WSTB_WIDTH113) <= wstrb_in; when 114 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH115)-1 downto STREAM_WSTB_WIDTH114) <= wstrb_in; when 115 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH116)-1 downto STREAM_WSTB_WIDTH115) <= wstrb_in; when 116 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH117)-1 downto STREAM_WSTB_WIDTH116) <= wstrb_in; when 117 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH118)-1 downto STREAM_WSTB_WIDTH117) <= wstrb_in; when 118 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH119)-1 downto STREAM_WSTB_WIDTH118) <= wstrb_in; when 119 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH120)-1 downto STREAM_WSTB_WIDTH119) <= wstrb_in; when 120 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH121)-1 downto STREAM_WSTB_WIDTH120) <= wstrb_in; when 121 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH122)-1 downto STREAM_WSTB_WIDTH121) <= wstrb_in; when 122 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH123)-1 downto STREAM_WSTB_WIDTH122) <= wstrb_in; when 123 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH124)-1 downto STREAM_WSTB_WIDTH123) <= wstrb_in; when 124 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH125)-1 downto STREAM_WSTB_WIDTH124) <= wstrb_in; when 125 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH126)-1 downto STREAM_WSTB_WIDTH125) <= wstrb_in; when 126 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH127)-1 downto STREAM_WSTB_WIDTH126) <= wstrb_in; when others => -- 127 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH128)-1 downto STREAM_WSTB_WIDTH127) <= wstrb_in; end case; end process DO_128XN_DEMUX; end generate GEN_128XN; end implementation;	mit
Bjay1435/capstone	Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_rst_module.vhd	1	24263	-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_rst_module.vhd -- Description: This entity is the top level reset module entity for the -- AXI VDMA core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_10; use axi_dma_v7_1_10.axi_dma_pkg.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- entity axi_dma_rst_module is generic( C_INCLUDE_MM2S : integer range 0 to 1 := 1; -- Include or exclude MM2S primary data path -- 0 = Exclude MM2S primary data path -- 1 = Include MM2S primary data path C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_INCLUDE_SG : integer range 0 to 1 := 1; -- Include or Exclude the Scatter Gather Engine -- 0 = Exclude SG Engine - Enables Simple DMA Mode -- 1 = Include SG Engine - Enables Scatter Gather Mode C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000; -- Primary clock frequency in hertz C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000; -- Primary clock frequency in hertz C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000 -- Scatter Gather clock frequency in hertz ); port ( ----------------------------------------------------------------------- -- Clock Sources ----------------------------------------------------------------------- s_axi_lite_aclk : in std_logic ; m_axi_sg_aclk : in std_logic ; -- m_axi_mm2s_aclk : in std_logic ; -- m_axi_s2mm_aclk : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- Hard Reset -- ----------------------------------------------------------------------- -- axi_resetn : in std_logic ; -- ----------------------------------------------------------------------- -- -- Soft Reset -- ----------------------------------------------------------------------- -- soft_reset : in std_logic ; -- soft_reset_clr : out std_logic := '0' ; -- -- ----------------------------------------------------------------------- -- -- MM2S Soft Reset Support -- ----------------------------------------------------------------------- -- mm2s_all_idle : in std_logic ; -- mm2s_stop : in std_logic ; -- mm2s_halt : out std_logic := '0' ; -- mm2s_halt_cmplt : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- S2MM Soft Reset Support -- ----------------------------------------------------------------------- -- s2mm_all_idle : in std_logic ; -- s2mm_stop : in std_logic ; -- s2mm_halt : out std_logic := '0' ; -- s2mm_halt_cmplt : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- MM2S Distributed Reset Out -- ----------------------------------------------------------------------- -- -- AXI DataMover Primary Reset (Raw) -- dm_mm2s_prmry_resetn : out std_logic := '1' ; -- -- AXI DataMover Secondary Reset (Raw) -- dm_mm2s_scndry_resetn : out std_logic := '1' ; -- AXI Stream Primary Reset Outputs -- mm2s_prmry_reset_out_n : out std_logic := '1' ; -- -- AXI Stream Control Reset Outputs -- mm2s_cntrl_reset_out_n : out std_logic := '1' ; -- -- AXI Secondary reset mm2s_scndry_resetn : out std_logic := '1' ; -- -- AXI Upsizer and Line Buffer -- mm2s_prmry_resetn : out std_logic := '1' ; -- -- -- ----------------------------------------------------------------------- -- -- S2MM Distributed Reset Out -- ----------------------------------------------------------------------- -- -- AXI DataMover Primary Reset (Raw) -- dm_s2mm_prmry_resetn : out std_logic := '1' ; -- -- AXI DataMover Secondary Reset (Raw) -- dm_s2mm_scndry_resetn : out std_logic := '1' ; -- AXI Stream Primary Reset Outputs -- s2mm_prmry_reset_out_n : out std_logic := '1' ; -- -- AXI Stream Control Reset Outputs -- s2mm_sts_reset_out_n : out std_logic := '1' ; -- -- AXI Secondary reset s2mm_scndry_resetn : out std_logic := '1' ; -- -- AXI Upsizer and Line Buffer -- s2mm_prmry_resetn : out std_logic := '1' ; -- ----------------------------------------------------------------------- -- -- Scatter Gather Distributed Reset Out ----------------------------------------------------------------------- -- -- AXI Scatter Gather Reset Out m_axi_sg_aresetn : out std_logic := '1' ; -- -- AXI Scatter Gather Datamover Reset Out dm_m_axi_sg_aresetn : out std_logic := '1' ; -- ----------------------------------------------------------------------- -- -- Hard Reset Out -- ----------------------------------------------------------------------- -- m_axi_sg_hrdresetn : out std_logic := '1' ; -- s_axi_lite_resetn : out std_logic := '1' -- ); Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of s_axi_lite_resetn : signal is "TRUE"; Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE"; Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no"; end axi_dma_rst_module; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_rst_module is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- ATTRIBUTE async_reg : STRING; signal hrd_resetn_i_cdc_tig : std_logic := '1'; signal hrd_resetn_i_d1_cdc_tig : std_logic := '1'; --ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true"; -- Soft reset support signal mm2s_soft_reset_clr : std_logic := '0'; signal s2mm_soft_reset_clr : std_logic := '0'; signal soft_reset_clr_i : std_logic := '0'; signal mm2s_soft_reset_done : std_logic := '0'; signal s2mm_soft_reset_done : std_logic := '0'; signal mm2s_scndry_resetn_i : std_logic := '0'; signal s2mm_scndry_resetn_i : std_logic := '0'; signal dm_mm2s_scndry_resetn_i : std_logic := '0'; signal dm_s2mm_scndry_resetn_i : std_logic := '0'; signal sg_hard_reset : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Register hard reset in REG_HRD_RST : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => axi_resetn, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => sg_hard_reset, scndry_vect_out => open ); m_axi_sg_hrdresetn <= sg_hard_reset; --REG_HRD_RST : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- hrd_resetn_i_cdc_tig <= axi_resetn; -- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig; -- end if; -- end process REG_HRD_RST; -- Regsiter hard reset out for axi lite interface REG_HRD_RST_OUT : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => axi_resetn, prmry_vect_in => (others => '0'), scndry_aclk => s_axi_lite_aclk, scndry_resetn => '0', scndry_out => s_axi_lite_resetn, scndry_vect_out => open ); --REG_HRD_RST_OUT : process(s_axi_lite_aclk) -- begin -- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then -- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig; -- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig; -- end if; -- end process REG_HRD_RST_OUT; dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i; dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i; -- mm2s channel included therefore map secondary resets to -- from mm2s reset module to scatter gather interface (default) MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate begin -- both must be low before sg reset is asserted. m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i; end generate MAP_SG_FOR_BOTH; -- Only s2mm channel included therefore map secondary resets to -- from s2mm reset module to scatter gather interface MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate begin m_axi_sg_aresetn <= s2mm_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i; end generate MAP_SG_FOR_S2MM; -- Only mm2s channel included therefore map secondary resets to -- from mm2s reset module to scatter gather interface MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate begin m_axi_sg_aresetn <= mm2s_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i; end generate MAP_SG_FOR_MM2S; -- Invalid configuration for axi dma - simply here for completeness MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate begin m_axi_sg_aresetn <= '1'; dm_m_axi_sg_aresetn <= '1'; end generate MAP_NO_SG; s2mm_scndry_resetn <= s2mm_scndry_resetn_i; mm2s_scndry_resetn <= mm2s_scndry_resetn_i; -- Generate MM2S reset signals GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate begin RESET_I : entity axi_dma_v7_1_10.axi_dma_reset generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ , C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_INCLUDE_SG => C_INCLUDE_SG ) port map( -- Clock Sources m_axi_sg_aclk => m_axi_sg_aclk , axi_prmry_aclk => m_axi_mm2s_aclk , -- Hard Reset axi_resetn => sg_hard_reset , -- Soft Reset soft_reset => soft_reset , soft_reset_clr => mm2s_soft_reset_clr , soft_reset_done => soft_reset_clr_i , all_idle => mm2s_all_idle , stop => mm2s_stop , halt => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , -- Secondary Reset scndry_resetn => mm2s_scndry_resetn_i , -- AXI Upsizer and Line Buffer prmry_resetn => mm2s_prmry_resetn , -- AXI DataMover Primary Reset (Raw) dm_prmry_resetn => dm_mm2s_prmry_resetn , -- AXI DataMover Secondary Reset (Raw) dm_scndry_resetn => dm_mm2s_scndry_resetn_i , -- AXI Stream Primary Reset Outputs prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Alternate Reset Outputs altrnt_reset_out_n => mm2s_cntrl_reset_out_n ); -- Sample an hold mm2s soft reset done to use in -- combined reset done to DMACR MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then mm2s_soft_reset_done <= '0'; elsif(mm2s_soft_reset_clr = '1')then mm2s_soft_reset_done <= '1'; end if; end if; end process MM2S_SOFT_RST_DONE; end generate GEN_RESET_FOR_MM2S; -- No MM2S therefore tie off mm2s reset signals GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate begin mm2s_prmry_reset_out_n <= '1'; mm2s_cntrl_reset_out_n <= '1'; dm_mm2s_scndry_resetn_i <= '1'; dm_mm2s_prmry_resetn <= '1'; mm2s_prmry_resetn <= '1'; mm2s_scndry_resetn_i <= '1'; mm2s_halt <= '0'; mm2s_soft_reset_clr <= '0'; mm2s_soft_reset_done <= '1'; end generate GEN_NO_RESET_FOR_MM2S; -- Generate S2MM reset signals GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate begin RESET_I : entity axi_dma_v7_1_10.axi_dma_reset generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ , C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_INCLUDE_SG => C_INCLUDE_SG ) port map( -- Clock Sources m_axi_sg_aclk => m_axi_sg_aclk , axi_prmry_aclk => m_axi_s2mm_aclk , -- Hard Reset axi_resetn => sg_hard_reset , -- Soft Reset soft_reset => soft_reset , soft_reset_clr => s2mm_soft_reset_clr , soft_reset_done => soft_reset_clr_i , all_idle => s2mm_all_idle , stop => s2mm_stop , halt => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , -- Secondary Reset scndry_resetn => s2mm_scndry_resetn_i , -- AXI Upsizer and Line Buffer prmry_resetn => s2mm_prmry_resetn , -- AXI DataMover Primary Reset (Raw) dm_prmry_resetn => dm_s2mm_prmry_resetn , -- AXI DataMover Secondary Reset (Raw) dm_scndry_resetn => dm_s2mm_scndry_resetn_i , -- AXI Stream Primary Reset Outputs prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Alternate Reset Outputs altrnt_reset_out_n => s2mm_sts_reset_out_n ); -- Sample an hold s2mm soft reset done to use in -- combined reset done to DMACR S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then s2mm_soft_reset_done <= '0'; elsif(s2mm_soft_reset_clr = '1')then s2mm_soft_reset_done <= '1'; end if; end if; end process S2MM_SOFT_RST_DONE; end generate GEN_RESET_FOR_S2MM; -- No SsMM therefore tie off mm2s reset signals GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate begin s2mm_prmry_reset_out_n <= '1'; dm_s2mm_scndry_resetn_i <= '1'; dm_s2mm_prmry_resetn <= '1'; s2mm_prmry_resetn <= '1'; s2mm_scndry_resetn_i <= '1'; s2mm_halt <= '0'; s2mm_soft_reset_clr <= '0'; s2mm_soft_reset_done <= '1'; end generate GEN_NO_RESET_FOR_S2MM; -- When both mm2s and s2mm are done then drive soft reset clear and -- also clear s_h registers above soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done; soft_reset_clr <= soft_reset_clr_i; end implementation;	mit
xiadz/oscilloscope	src/screen_position_gen.vhd	1	4551	library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity screen_position_gen is port ( -- inputs nrst : in std_logic; clk108 : in std_logic; vblank : in std_logic; in_line_change : in std_logic; in_page_change : in std_logic; in_column : in integer range 0 to 1279; in_column_change : in std_logic; -- outputs segment : out integer range 0 to 15; segment_change : out std_logic; subsegment : out integer range 0 to 3; subsegment_change : out std_logic; line : out integer range 0 to 15; out_line_change : out std_logic; out_column : out integer range 0 to 1279; out_column_mod_8 : out integer range 0 to 7; out_column_div_8 : out integer range 0 to 159; out_column_change : out std_logic; out_page_change : out std_logic; active_pixgen_source : out PIXGEN_SOURCE_T ); end screen_position_gen; architecture behavioral of screen_position_gen is signal internal_segment : integer range 0 to 15; signal internal_subsegment : integer range 0 to 3; signal internal_line : integer range 0 to 15; signal next_segment : integer range 0 to 15; signal next_subsegment : integer range 0 to 3; signal next_line : integer range 0 to 15; begin segment <= internal_segment; subsegment <= internal_subsegment; line <= internal_line; -- This process calculates next_line, next_subsegment, next_segment signals process (in_line_change, in_page_change, internal_segment, internal_subsegment, internal_line) is begin if in_page_change = '1' then next_line <= 0; next_subsegment <= 0; next_segment <= 0; else if in_line_change = '1' then if internal_line = 15 then next_line <= 0; if internal_subsegment = 3 then next_subsegment <= 0; if internal_segment = 15 then next_segment <= 0; else next_segment <= internal_segment + 1; end if; else next_subsegment <= internal_subsegment + 1; next_segment <= internal_segment; end if; else next_line <= internal_line + 1; next_subsegment <= internal_subsegment; next_segment <= internal_segment; end if; else next_line <= internal_line; next_subsegment <= internal_subsegment; next_segment <= internal_segment; end if; end if; end process; -- This proces generates all output signals process (clk108, nrst) is begin if nrst = '0' then elsif rising_edge (clk108) then internal_line <= next_line; internal_subsegment <= next_subsegment; internal_segment <= next_segment; out_line_change <= in_line_change; if internal_subsegment /= next_subsegment then subsegment_change <= '1'; else subsegment_change <= '0'; end if; if internal_segment /= next_segment then segment_change <= '1'; else segment_change <= '0'; end if; out_column <= in_column; out_column_mod_8 <= in_column mod 8; out_column_div_8 <= in_column / 8; out_column_change <= in_column_change; out_page_change <= in_page_change; if vblank = '1' then active_pixgen_source <= BLANK_PIXGEN_T; elsif next_segment < 14 then if next_subsegment /= 3 then active_pixgen_source <= TRACE_PIXGEN_T; else active_pixgen_source <= TIME_BASE_PIXGEN_T; end if; else active_pixgen_source <= SETTINGS_PIXGEN_T; end if; end if; end process; end architecture behavioral;	mit
xiadz/oscilloscope	src/clock_divider.vhd	1	965	-- A simple frequency divider library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity divider is -- 1 -- f_out = f_in ----- -- 2 * n generic (n: natural range 1 to 2147483647); port ( clk_in : in std_logic; nrst : in std_logic; clk_out : out std_logic ); end entity divider; architecture counter of divider is signal cnt : integer range 0 to n - 1; signal internal_clk_out : std_logic := '0'; begin clk_out <= internal_clk_out; process (clk_in, nrst) begin if nrst = '0' then cnt <= 0; internal_clk_out <= '0'; elsif rising_edge (clk_in) then if cnt = n - 1 then cnt <= 0; internal_clk_out <= not internal_clk_out; else cnt <= cnt + 1; end if; end if; end process; end architecture counter;	mit
xiadz/oscilloscope	src/bits_aggregator.vhd	1	3657	---------------------------------------------------------------------------------- -- Author: Osowski Marcin -- Create Date: 19:43:33 05/27/2011 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bits_aggregator is port ( -- Inputs nrst : in std_logic; clk108 : in std_logic; flush_and_return_to_zero : in std_logic; write_enable : in std_logic; red_value : in std_logic; green_value : in std_logic; blue_value : in std_logic; -- Outputs wea : out std_logic; addra : out std_logic_vector (12 downto 0); dina : out std_logic_vector (8 downto 0) ); end bits_aggregator; architecture behavioral of bits_aggregator is signal mod3 : integer range 0 to 2 := 0; signal next_mod3 : integer range 0 to 2; signal mod3_overflow : std_logic := '0'; signal address : std_logic_vector (12 downto 0) := (others => '0'); signal next_address : std_logic_vector (12 downto 0); signal row_buffer : std_logic_vector (5 downto 0) := (others => '0'); signal next_row : std_logic_vector (8 downto 0) := (others => '0'); begin -- Process calculates next_mod3, mod3_overflow, next_address process (mod3, address) is begin if mod3 = 2 then next_mod3 <= 0; mod3_overflow <= '1'; next_address <= address + 1; else next_mod3 <= mod3 + 1; mod3_overflow <= '0'; next_address <= address; end if; end process; -- Process calculates next_row process (mod3, row_buffer, red_value, green_value, blue_value) is begin if mod3 = 0 then next_row (0) <= red_value; next_row (1) <= green_value; next_row (2) <= blue_value; next_row (8 downto 3) <= (others => '0'); elsif mod3 = 1 then next_row (2 downto 0) <= row_buffer (2 downto 0); next_row (3) <= red_value; next_row (4) <= green_value; next_row (5) <= blue_value; next_row (8 downto 6) <= (others => '0'); else next_row (5 downto 0) <= row_buffer (5 downto 0); next_row (6) <= red_value; next_row (7) <= green_value; next_row (8) <= blue_value; end if; end process; process (nrst, clk108) is begin if nrst = '0' then mod3 <= 0; address <= (others => '0'); wea <= '0'; addra <= (others => '0'); dina <= (others => '0'); elsif rising_edge (clk108) then if flush_and_return_to_zero = '1' then mod3 <= 0; address <= (others => '0'); row_buffer <= (others => '0'); addra <= address; dina <= next_row; wea <= '1'; elsif write_enable = '1' then mod3 <= next_mod3; address <= next_address; row_buffer <= next_row (5 downto 0); if mod3_overflow = '1' then addra <= address; dina <= next_row; wea <= '1'; else wea <= '0'; end if; else wea <= '0'; end if; end if; end process; end behavioral;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_arccospi_s5.vhd	10	713163	----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_arccospi_s5 -- VHDL created on Thu Feb 28 17:21:22 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_arccospi_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_arccospi_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstBiasM2_uid6_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal ooPi_uid9_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstBias_uid22_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q : std_logic_vector (12 downto 0); signal pi_uid94_acosX_uid8_fpArccosPiTest_q : std_logic_vector (27 downto 0); signal path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal pi2_uid111_acosX_uid8_fpArccosPiTest_q : std_logic_vector (26 downto 0); signal fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (9 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (10 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector (23 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (47 downto 0); signal roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (15 downto 0); signal rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (3 downto 0); signal rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (11 downto 0); signal rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (1 downto 0); signal rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (10 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector (23 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (47 downto 0); signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b : std_logic_vector (23 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr : SIGNED (39 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q : std_logic_vector (38 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_reset0 : std_logic; signal memoryC0_uid550_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_reset0 : std_logic; signal memoryC1_uid551_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_reset0 : std_logic; signal memoryC2_uid552_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid566_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid567_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid568_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0); signal reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (2 downto 0); signal reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (36 downto 0); signal reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (36 downto 0); signal reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (36 downto 0); signal reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q : std_logic_vector (36 downto 0); signal reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (35 downto 0); signal reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (31 downto 0); signal reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (15 downto 0); signal reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (3 downto 0); signal reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0); signal reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (0 downto 0); signal reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (5 downto 0); signal reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (22 downto 0); signal reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0); signal reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (3 downto 0); signal reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0); signal reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0); signal reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0); signal reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (7 downto 0); signal reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0); signal reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q : std_logic_vector (23 downto 0); signal reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0); signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0); signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0); signal reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0); signal reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (23 downto 0); signal reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (11 downto 0); signal reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (2 downto 0); signal reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (22 downto 0); signal reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0); signal reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (26 downto 0); signal reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0); signal reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0); signal reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (27 downto 0); signal reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (26 downto 0); signal reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (22 downto 0); signal reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (22 downto 0); signal reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (7 downto 0); signal reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (23 downto 0); signal reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (11 downto 0); signal reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (2 downto 0); signal reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q : std_logic_vector (22 downto 0); signal reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q : std_logic_vector (7 downto 0); signal ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (23 downto 0); signal ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (31 downto 0); signal ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (22 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (1 downto 0); signal ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (7 downto 0); signal ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (8 downto 0); signal ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q : std_logic_vector (22 downto 0); signal ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (5 downto 0); signal ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (22 downto 0); signal ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (1 downto 0); signal ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (8 downto 0); signal ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q : std_logic_vector (22 downto 0); signal ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q : std_logic_vector (22 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q : std_logic_vector (7 downto 0); signal ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q : std_logic_vector (0 downto 0); signal ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0); signal ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q : std_logic_vector (0 downto 0); signal ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q : std_logic_vector (7 downto 0); signal ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 : std_logic; signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq : std_logic; signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : signal is true; signal ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q : std_logic_vector (31 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic; signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i : unsigned(5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq : std_logic; signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q : std_logic_vector (6 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true; signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0 : std_logic; signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q : signal is true; signal ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : signal is true; signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq : std_logic; signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true; signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true; signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q : signal is true; signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true; signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0); signal ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 : std_logic; signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq : std_logic; signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : signal is true; signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 : std_logic; signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : signal is true; signal pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q : std_logic_vector (35 downto 0); signal pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q : std_logic_vector (27 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c : std_logic_vector (0 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal excSelBits_uid137_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal expX_uid15_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid15_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid16_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid16_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal singX_uid17_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal singX_uid17_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid38_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid38_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid38_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_a : std_logic_vector(10 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_b : std_logic_vector(10 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_o : std_logic_vector (10 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_c : std_logic_vector (0 downto 0); signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_a : std_logic_vector(36 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_b : std_logic_vector(36 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_o : std_logic_vector (36 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a : std_logic_vector(28 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b : std_logic_vector(28 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o : std_logic_vector (28 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q : std_logic_vector (28 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_a : std_logic_vector(28 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_b : std_logic_vector(28 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_o : std_logic_vector (28 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_q : std_logic_vector (28 downto 0); signal expRCalc_uid134_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRCalc_uid134_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (35 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (35 downto 0); signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q : std_logic_vector(0 downto 0); signal fracOOPi_uid10_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracOOPi_uid10_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal piF_uid128_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal piF_uid128_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0); signal prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0); signal prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b : std_logic_vector (24 downto 0); signal prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in : std_logic_vector (15 downto 0); signal sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b : std_logic_vector (14 downto 0); signal fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal R_uid242_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (15 downto 0); signal FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a : std_logic_vector(6 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b : std_logic_vector(6 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a : std_logic_vector(5 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b : std_logic_vector(5 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q : std_logic_vector(0 downto 0); signal oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in : std_logic_vector (5 downto 0); signal fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b : std_logic_vector (5 downto 0); signal l_uid65_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal l_uid65_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0); signal expLRange_uid69_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal expLRange_uid69_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal srValRange_uid77_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal srValRange_uid77_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0); signal path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in : std_logic_vector (27 downto 0); signal path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0); signal path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal normBit_uid114_acosX_uid8_fpArccosPiTest_in : std_logic_vector (27 downto 0); signal normBit_uid114_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0); signal path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal sR_uid141_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (11 downto 0); signal InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (35 downto 0); signal RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0); signal RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (33 downto 0); signal rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (18 downto 0); signal vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (18 downto 0); signal rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (26 downto 0); signal rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (32 downto 0); signal vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (32 downto 0); signal InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (8 downto 0); signal expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (8 downto 0); signal expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (11 downto 0); signal RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (19 downto 0); signal RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (17 downto 0); signal fpOOPi_uid11_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal lowRangeB_uid411_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid411_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid412_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid412_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid417_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid417_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid418_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0); signal highBBits_uid418_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0); signal lowRangeB_uid555_arccosXO2PolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid555_arccosXO2PolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid556_arccosXO2PolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid556_arccosXO2PolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid561_arccosXO2PolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid561_arccosXO2PolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid562_arccosXO2PolyEval_in : std_logic_vector (24 downto 0); signal highBBits_uid562_arccosXO2PolyEval_b : std_logic_vector (22 downto 0); signal lowRangeB_uid571_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid571_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid572_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal highBBits_uid572_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal lowRangeB_uid577_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid577_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid578_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal highBBits_uid578_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0); signal yT1_uid409_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid409_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal yT1_uid569_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0); signal yT1_uid569_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal exc_N_uid40_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid40_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid40_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal shiftValue_uid56_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal shiftValue_uid56_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0); signal vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (2 downto 0); signal fpL_uid70_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal expX_uid143_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid143_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signX_uid145_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signX_uid145_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal expY_uid144_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expY_uid144_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signY_uid146_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signY_uid146_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_a : std_logic_vector(22 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_b : std_logic_vector(22 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_o : std_logic_vector (22 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_q : std_logic_vector (22 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0); signal oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (20 downto 0); signal X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0); signal InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (5 downto 0); signal rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (3 downto 0); signal rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (1 downto 0); signal rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal s1_uid411_uid414_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0); signal s2_uid417_uid420_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0); signal s1_uid555_uid558_arccosXO2PolyEval_q : std_logic_vector (23 downto 0); signal s2_uid561_uid564_arccosXO2PolyEval_q : std_logic_vector (32 downto 0); signal s1_uid571_uid574_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0); signal s2_uid577_uid580_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0); signal X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0); signal rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0); signal expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (19 downto 0); signal RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (17 downto 0); signal Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal y_uid61_acosX_uid8_fpArccosPiTest_in : std_logic_vector (35 downto 0); signal y_uid61_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0); signal rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (30 downto 0); signal rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (33 downto 0); signal vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (33 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sAddr_uid80_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal sAddr_uid80_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b : std_logic_vector (25 downto 0); signal fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b : std_logic_vector (26 downto 0); signal fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (28 downto 0); signal fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (32 downto 0); signal RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (28 downto 0); signal RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (24 downto 0); signal expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal firstPath_uid62_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal firstPath_uid62_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal mAddr_uid107_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal mAddr_uid107_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b : std_logic_vector (14 downto 0); signal cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in : std_logic_vector (24 downto 0); signal fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0); signal path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal yT1_uid553_arccosXO2PolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid553_arccosXO2PolyEval_b : std_logic_vector (11 downto 0); signal vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in : std_logic_vector (33 downto 0); signal fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q : std_logic_vector (26 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (25 downto 0); signal roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (25 downto 0); signal expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (3 downto 0); signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); begin --xIn(GPIN,3)@0 --cstAllZWF_uid19_acosX_uid8_fpArccosPiTest(CONSTANT,18) cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000000"; --GND(CONSTANT,0) GND_q <= "0"; --cstAllOWE_uid18_acosX_uid8_fpArccosPiTest(CONSTANT,17) cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q <= "11111111"; --cstBiasP1_uid26_acosX_uid8_fpArccosPiTest(CONSTANT,25) cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q <= "10000000"; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable(LOGICAL,1457) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a <= en; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q <= not ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor(LOGICAL,1626) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q <= not (ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a or ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top(CONSTANT,1609) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q <= "011001"; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp(LOGICAL,1610) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q); ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q <= "1" when ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a = ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b else "0"; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg(REG,1611) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q; END IF; END IF; END PROCESS; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena(REG,1627) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q = "1") THEN ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd(LOGICAL,1628) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b <= en; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a and ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b; --rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,271) rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "000"; --RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,270)@1 RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 3); --rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,272)@1 rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,268) rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "00"; --RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,267)@1 RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 2); --rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,269)@1 rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,264)@1 RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 1); --rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,266)@1 rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,260) rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "000000000000"; --rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,250) rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000000000000000000000000000000000000"; --rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,248) rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000000000000000"; --X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,247)@0 X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q; X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 32); --rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,249)@0 rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,245) rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000000000000000"; --X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,244)@0 X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q; X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 16); --rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,246)@0 rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --fracX_uid16_acosX_uid8_fpArccosPiTest(BITSELECT,15)@0 fracX_uid16_acosX_uid8_fpArccosPiTest_in <= a(22 downto 0); fracX_uid16_acosX_uid8_fpArccosPiTest_b <= fracX_uid16_acosX_uid8_fpArccosPiTest_in(22 downto 0); --oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest(BITJOIN,50)@0 oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q <= VCC_q & fracX_uid16_acosX_uid8_fpArccosPiTest_b; --cst01pWShift_uid57_acosX_uid8_fpArccosPiTest(CONSTANT,56) cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q <= "0000000000000"; --oFracXExt_uid58_acosX_uid8_fpArccosPiTest(BITJOIN,57)@0 oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q <= oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q & cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q; --shiftOutVal_uid54_acosX_uid8_fpArccosPiTest(CONSTANT,53) shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q <= "100100"; --expX_uid15_acosX_uid8_fpArccosPiTest(BITSELECT,14)@0 expX_uid15_acosX_uid8_fpArccosPiTest_in <= a(30 downto 0); expX_uid15_acosX_uid8_fpArccosPiTest_b <= expX_uid15_acosX_uid8_fpArccosPiTest_in(30 downto 23); --cstBias_uid22_acosX_uid8_fpArccosPiTest(CONSTANT,21) cstBias_uid22_acosX_uid8_fpArccosPiTest_q <= "01111111"; --shiftValuePre_uid53_acosX_uid8_fpArccosPiTest(SUB,52)@0 shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_acosX_uid8_fpArccosPiTest_b); shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b)); shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q <= shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o(8 downto 0); --fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest(BITSELECT,54)@0 fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in <= shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q(5 downto 0); fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b <= fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in(5 downto 0); --cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest(CONSTANT,23) cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q <= "001011100"; --shiftValue_uid52_acosX_uid8_fpArccosPiTest(COMPARE,51)@0 shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin <= GND_q; shiftValue_uid52_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q(8)) & cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q) & '0'; shiftValue_uid52_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid15_acosX_uid8_fpArccosPiTest_b) & shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin(0); shiftValue_uid52_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid52_acosX_uid8_fpArccosPiTest_a) - SIGNED(shiftValue_uid52_acosX_uid8_fpArccosPiTest_b)); shiftValue_uid52_acosX_uid8_fpArccosPiTest_n(0) <= not shiftValue_uid52_acosX_uid8_fpArccosPiTest_o(11); --shiftValue_uid56_acosX_uid8_fpArccosPiTest(MUX,55)@0 shiftValue_uid56_acosX_uid8_fpArccosPiTest_s <= shiftValue_uid52_acosX_uid8_fpArccosPiTest_n; shiftValue_uid56_acosX_uid8_fpArccosPiTest: PROCESS (shiftValue_uid56_acosX_uid8_fpArccosPiTest_s, en, fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b, shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q) BEGIN CASE shiftValue_uid56_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b; WHEN "1" => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,251)@0 rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q; rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(5 downto 4); --rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,252)@0 rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q; WHEN "01" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "10" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "11" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,259)@0 RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 12); --rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,261)@0 rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5(REG,613)@0 reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q <= rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,256)@0 RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 8); --rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,258)@0 rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4(REG,612)@0 reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,254) rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000"; --RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,253)@0 RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 4); --rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,255)@0 rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3(REG,611)@0 reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2(REG,610)@0 reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,262)@0 rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q(3 downto 0); rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(3 downto 2); --reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1(REG,609)@0 reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,263)@1 rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q, reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q) BEGIN CASE rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q; WHEN OTHERS => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,273)@0 rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q(1 downto 0); rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(1 downto 0); --reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1(REG,614)@0 reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,274)@1 rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "01" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "10" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "11" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid61_acosX_uid8_fpArccosPiTest(BITSELECT,60)@1 y_uid61_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q(35 downto 0); y_uid61_acosX_uid8_fpArccosPiTest_b <= y_uid61_acosX_uid8_fpArccosPiTest_in(35 downto 1); --mAddr_uid107_acosX_uid8_fpArccosPiTest(BITSELECT,106)@1 mAddr_uid107_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b; mAddr_uid107_acosX_uid8_fpArccosPiTest_b <= mAddr_uid107_acosX_uid8_fpArccosPiTest_in(34 downto 27); --reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0(REG,688)@1 reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q <= mAddr_uid107_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid552_arccosXO2TabGen_lutmem(DUALMEM,604)@2 memoryC2_uid552_arccosXO2TabGen_lutmem_reset0 <= areset; memoryC2_uid552_arccosXO2TabGen_lutmem_ia <= (others => '0'); memoryC2_uid552_arccosXO2TabGen_lutmem_aa <= (others => '0'); memoryC2_uid552_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q; memoryC2_uid552_arccosXO2TabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC2_uid552_arccosXO2TabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid552_arccosXO2TabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid552_arccosXO2TabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid552_arccosXO2TabGen_lutmem_iq, address_a => memoryC2_uid552_arccosXO2TabGen_lutmem_aa, data_a => memoryC2_uid552_arccosXO2TabGen_lutmem_ia ); memoryC2_uid552_arccosXO2TabGen_lutmem_q <= memoryC2_uid552_arccosXO2TabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1(REG,690)@4 reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q <= memoryC2_uid552_arccosXO2TabGen_lutmem_q; END IF; END IF; END PROCESS; --mPPolyEval_uid108_acosX_uid8_fpArccosPiTest(BITSELECT,107)@1 mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b(26 downto 0); mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in(26 downto 12); --yT1_uid553_arccosXO2PolyEval(BITSELECT,552)@1 yT1_uid553_arccosXO2PolyEval_in <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b; yT1_uid553_arccosXO2PolyEval_b <= yT1_uid553_arccosXO2PolyEval_in(14 downto 3); --ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg(DELAY,1601) ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 12, depth => 1 ) PORT MAP ( xin => yT1_uid553_arccosXO2PolyEval_b, xout => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a(DELAY,1420)@1 ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a : dspba_delay GENERIC MAP ( width => 12, depth => 2 ) PORT MAP ( xin => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0(REG,689)@4 reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q <= ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q; END IF; END IF; END PROCESS; --prodXY_uid588_pT1_uid554_arccosXO2PolyEval(MULT,587)@5 prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b); prodXY_uid588_pT1_uid554_arccosXO2PolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a <= (others => '0'); prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b <= (others => '0'); prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a <= reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q; prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b <= reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q; prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid588_pT1_uid554_arccosXO2PolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q <= prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval(BITSELECT,588)@8 prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in <= prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q; prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in(23 downto 11); --highBBits_uid556_arccosXO2PolyEval(BITSELECT,555)@8 highBBits_uid556_arccosXO2PolyEval_in <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b; highBBits_uid556_arccosXO2PolyEval_b <= highBBits_uid556_arccosXO2PolyEval_in(12 downto 1); --ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1602) ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => mAddr_uid107_acosX_uid8_fpArccosPiTest_b, xout => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a(DELAY,1422)@1 ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q, xout => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0(REG,691)@5 reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid551_arccosXO2TabGen_lutmem(DUALMEM,603)@6 memoryC1_uid551_arccosXO2TabGen_lutmem_reset0 <= areset; memoryC1_uid551_arccosXO2TabGen_lutmem_ia <= (others => '0'); memoryC1_uid551_arccosXO2TabGen_lutmem_aa <= (others => '0'); memoryC1_uid551_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q; memoryC1_uid551_arccosXO2TabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 22, widthad_a => 8, numwords_a => 256, width_b => 22, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC1_uid551_arccosXO2TabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid551_arccosXO2TabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid551_arccosXO2TabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid551_arccosXO2TabGen_lutmem_iq, address_a => memoryC1_uid551_arccosXO2TabGen_lutmem_aa, data_a => memoryC1_uid551_arccosXO2TabGen_lutmem_ia ); memoryC1_uid551_arccosXO2TabGen_lutmem_q <= memoryC1_uid551_arccosXO2TabGen_lutmem_iq(21 downto 0); --sumAHighB_uid557_arccosXO2PolyEval(ADD,556)@8 sumAHighB_uid557_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid551_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid551_arccosXO2TabGen_lutmem_q); sumAHighB_uid557_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid556_arccosXO2PolyEval_b(11)) & highBBits_uid556_arccosXO2PolyEval_b); sumAHighB_uid557_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid557_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid557_arccosXO2PolyEval_b)); sumAHighB_uid557_arccosXO2PolyEval_q <= sumAHighB_uid557_arccosXO2PolyEval_o(22 downto 0); --lowRangeB_uid555_arccosXO2PolyEval(BITSELECT,554)@8 lowRangeB_uid555_arccosXO2PolyEval_in <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b(0 downto 0); lowRangeB_uid555_arccosXO2PolyEval_b <= lowRangeB_uid555_arccosXO2PolyEval_in(0 downto 0); --s1_uid555_uid558_arccosXO2PolyEval(BITJOIN,557)@8 s1_uid555_uid558_arccosXO2PolyEval_q <= sumAHighB_uid557_arccosXO2PolyEval_q & lowRangeB_uid555_arccosXO2PolyEval_b; --reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1(REG,693)@8 reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q <= s1_uid555_uid558_arccosXO2PolyEval_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor(LOGICAL,1535) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q <= not (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a or ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b); --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top(CONSTANT,1531) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q <= "0101"; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp(LOGICAL,1532) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q); ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q <= "1" when ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a = ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b else "0"; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg(REG,1533) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena(REG,1536) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q = "1") THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd(LOGICAL,1537) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b <= en; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a and ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b; --reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0(REG,692)@1 reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt(COUNTER,1527) -- every=1, low=0, high=5, step=1, init=1 ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i = 4 THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i - 5; ELSE ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i,3)); --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg(REG,1528) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux(MUX,1529) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s <= en; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux: PROCESS (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s, ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q, ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem(DUALMEM,1526) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0 <= areset; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia <= reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 3, numwords_a => 6, width_b => 15, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq, address_a => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa, data_a => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia ); ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq(14 downto 0); --prodXY_uid591_pT2_uid560_arccosXO2PolyEval(MULT,590)@9 prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b); prodXY_uid591_pT2_uid560_arccosXO2PolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a <= (others => '0'); prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b <= (others => '0'); prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q; prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b <= reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q; prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr,39)); END IF; END IF; END PROCESS; prodXY_uid591_pT2_uid560_arccosXO2PolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q <= prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval(BITSELECT,591)@12 prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in <= prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q; prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in(38 downto 14); --highBBits_uid562_arccosXO2PolyEval(BITSELECT,561)@12 highBBits_uid562_arccosXO2PolyEval_in <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b; highBBits_uid562_arccosXO2PolyEval_b <= highBBits_uid562_arccosXO2PolyEval_in(24 downto 2); --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor(LOGICAL,1548) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q <= not (ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a or ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b); --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena(REG,1549) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q = "1") THEN ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd(LOGICAL,1550) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b <= en; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a and ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b; --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem(DUALMEM,1539) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia ); ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq(7 downto 0); --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1538) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q, xout => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC0_uid550_arccosXO2TabGen_lutmem(DUALMEM,602)@10 memoryC0_uid550_arccosXO2TabGen_lutmem_reset0 <= areset; memoryC0_uid550_arccosXO2TabGen_lutmem_ia <= (others => '0'); memoryC0_uid550_arccosXO2TabGen_lutmem_aa <= (others => '0'); memoryC0_uid550_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q; memoryC0_uid550_arccosXO2TabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC0_uid550_arccosXO2TabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid550_arccosXO2TabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid550_arccosXO2TabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid550_arccosXO2TabGen_lutmem_iq, address_a => memoryC0_uid550_arccosXO2TabGen_lutmem_aa, data_a => memoryC0_uid550_arccosXO2TabGen_lutmem_ia ); memoryC0_uid550_arccosXO2TabGen_lutmem_q <= memoryC0_uid550_arccosXO2TabGen_lutmem_iq(29 downto 0); --sumAHighB_uid563_arccosXO2PolyEval(ADD,562)@12 sumAHighB_uid563_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid550_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid550_arccosXO2TabGen_lutmem_q); sumAHighB_uid563_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid562_arccosXO2PolyEval_b(22)) & highBBits_uid562_arccosXO2PolyEval_b); sumAHighB_uid563_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid563_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid563_arccosXO2PolyEval_b)); sumAHighB_uid563_arccosXO2PolyEval_q <= sumAHighB_uid563_arccosXO2PolyEval_o(30 downto 0); --lowRangeB_uid561_arccosXO2PolyEval(BITSELECT,560)@12 lowRangeB_uid561_arccosXO2PolyEval_in <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b(1 downto 0); lowRangeB_uid561_arccosXO2PolyEval_b <= lowRangeB_uid561_arccosXO2PolyEval_in(1 downto 0); --s2_uid561_uid564_arccosXO2PolyEval(BITJOIN,563)@12 s2_uid561_uid564_arccosXO2PolyEval_q <= sumAHighB_uid563_arccosXO2PolyEval_q & lowRangeB_uid561_arccosXO2PolyEval_b; --fxpArccosX_uid110_acosX_uid8_fpArccosPiTest(BITSELECT,109)@12 fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in <= s2_uid561_uid564_arccosXO2PolyEval_q(30 downto 0); fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in(30 downto 4); --reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1(REG,696)@12 reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --pi2_uid111_acosX_uid8_fpArccosPiTest(CONSTANT,110) pi2_uid111_acosX_uid8_fpArccosPiTest_q <= "110010010000111111011010101"; --pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest(BITJOIN,111)@12 pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q <= pi2_uid111_acosX_uid8_fpArccosPiTest_q & GND_q; --reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0(REG,695)@12 reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q <= "0000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q <= pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --path2Diff_uid112_acosX_uid8_fpArccosPiTest(SUB,112)@13 path2Diff_uid112_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q); path2Diff_uid112_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q); path2Diff_uid112_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid112_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(path2Diff_uid112_acosX_uid8_fpArccosPiTest_b)); path2Diff_uid112_acosX_uid8_fpArccosPiTest_q <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_o(28 downto 0); --path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest(BITSELECT,114)@13 path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(26 downto 0); path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b <= path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in(26 downto 4); --path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest(BITJOIN,115)@13 path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q & path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b; --path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest(BITSELECT,117)@13 path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(25 downto 0); path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b <= path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in(25 downto 3); --path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest(BITJOIN,118)@13 path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBias_uid22_acosX_uid8_fpArccosPiTest_q & path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b; --normBit_uid114_acosX_uid8_fpArccosPiTest(BITSELECT,113)@13 normBit_uid114_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(27 downto 0); normBit_uid114_acosX_uid8_fpArccosPiTest_b <= normBit_uid114_acosX_uid8_fpArccosPiTest_in(27 downto 27); --path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest(MUX,120)@13 path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s <= normBit_uid114_acosX_uid8_fpArccosPiTest_b; path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest: PROCESS (path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s, en, path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q, path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q) BEGIN CASE path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q; WHEN "1" => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest(BITSELECT,121)@12 path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b(25 downto 0); path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b <= path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in(25 downto 3); --ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a(DELAY,806)@12 ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b, xout => ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest(BITJOIN,122)@13 path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBias_uid22_acosX_uid8_fpArccosPiTest_q & ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q; --singX_uid17_acosX_uid8_fpArccosPiTest(BITSELECT,16)@0 singX_uid17_acosX_uid8_fpArccosPiTest_in <= a; singX_uid17_acosX_uid8_fpArccosPiTest_b <= singX_uid17_acosX_uid8_fpArccosPiTest_in(31 downto 31); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b(DELAY,807)@0 ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => singX_uid17_acosX_uid8_fpArccosPiTest_b, xout => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --path2ResFP_uid125_acosX_uid8_fpArccosPiTest(MUX,124)@13 path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q; path2ResFP_uid125_acosX_uid8_fpArccosPiTest: PROCESS (path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s, en, path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q, path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q) BEGIN CASE path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q; WHEN "1" => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest(BITSELECT,131)@13 Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in <= path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q(30 downto 0); Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b <= Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in(30 downto 23); --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg(DELAY,1616) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b, xout => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt(COUNTER,1605) -- every=1, low=0, high=25, step=1, init=1 ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i = 24 THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '1'; ELSE ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i - 25; ELSE ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i,5)); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg(REG,1606) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux(MUX,1607) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s <= en; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux: PROCESS (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s, ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q, ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q) BEGIN CASE ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s IS WHEN "0" => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q; WHEN "1" => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q; WHEN OTHERS => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem(DUALMEM,1617) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 <= areset; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 26, width_b => 8, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0, clock1 => clk, address_b => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq, address_a => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa, data_a => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia ); ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq(7 downto 0); --reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3(REG,700)@41 reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q; END IF; END IF; END PROCESS; --RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,543)@39 RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 1); --rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,545)@39 rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(CONSTANT,395) rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= "000000"; --RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,538)@39 RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 6); --rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,540)@39 rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,535)@39 RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 4); --rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,537)@39 rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,532)@39 RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 2); --rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,534)@39 rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(CONSTANT,385) rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= "000000000000000000000000"; --maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(CONSTANT,319) maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "100011"; --reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1(REG,616)@1 reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q <= y_uid61_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest(BITJOIN,62)@1 pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q); --reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0(REG,615)@1 reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q <= "000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q <= pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --oMy_uid63_acosX_uid8_fpArccosPiTest(SUB,63)@2 oMy_uid63_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q); oMy_uid63_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q); oMy_uid63_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid63_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(oMy_uid63_acosX_uid8_fpArccosPiTest_b)); oMy_uid63_acosX_uid8_fpArccosPiTest_q <= oMy_uid63_acosX_uid8_fpArccosPiTest_o(36 downto 0); --l_uid65_acosX_uid8_fpArccosPiTest(BITSELECT,64)@2 l_uid65_acosX_uid8_fpArccosPiTest_in <= oMy_uid63_acosX_uid8_fpArccosPiTest_q(34 downto 0); l_uid65_acosX_uid8_fpArccosPiTest_b <= l_uid65_acosX_uid8_fpArccosPiTest_in(34 downto 0); --rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,277)@2 rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= l_uid65_acosX_uid8_fpArccosPiTest_b; rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 3); --reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,617)@2 reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,278)@3 vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q; vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f(DELAY,1040)@3 ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,280)@2 vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= l_uid65_acosX_uid8_fpArccosPiTest_b(2 downto 0); vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(2 downto 0); --cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,281)@2 cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,619)@2 reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,618)@2 reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= l_uid65_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,282)@3 vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q) BEGIN CASE vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q; WHEN "1" => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q; WHEN OTHERS => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,284)@3 rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 19); --reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,620)@3 reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,285)@4 vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q; vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e(DELAY,1039)@4 ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,287)@3 vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(18 downto 0); vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(18 downto 0); --cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,288)@3 cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,622)@3 reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,621)@3 reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,289)@4 vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q) BEGIN CASE vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q; WHEN "1" => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q; WHEN OTHERS => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,291)@4 rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 27); --vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,292)@4 vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,626)@4 reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,294)@4 vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(26 downto 0); vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(26 downto 0); --cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,295)@4 cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; --vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,296)@4 vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) BEGIN CASE vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN "1" => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,298)@4 rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 31); --reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,623)@4 reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,299)@5 vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q; vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,301)@4 vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(30 downto 0); vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(30 downto 0); --cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,302)@4 cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,625)@4 reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,624)@4 reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,303)@5 vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q) BEGIN CASE vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q; WHEN "1" => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q; WHEN OTHERS => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,305)@5 rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 33); --vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,306)@5 vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,308)@5 vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(32 downto 0); vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(32 downto 0); --cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,309)@5 cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,310)@5 vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) BEGIN CASE vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN "1" => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,312)@5 rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 34); --vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,313)@5 vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= GND_q; vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,318)@5 vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q & ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q & reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q & vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q & vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q & vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; --ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c(DELAY,1043)@5 ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 6, depth => 1 ) PORT MAP ( xin => vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,627)@5 reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(COMPARE,320)@6 vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin <= GND_q; vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) & '0'; vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q) & vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin(0); vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b)); vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c(0) <= vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o(8); --vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,322)@6 vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c; vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q; WHEN "1" => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --cstBiasM2_uid6_fpArccosPiTest(CONSTANT,5) cstBiasM2_uid6_fpArccosPiTest_q <= "01111101"; --expL_uid67_acosX_uid8_fpArccosPiTest(SUB,66)@7 expL_uid67_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid6_fpArccosPiTest_q); expL_uid67_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q); expL_uid67_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid67_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(expL_uid67_acosX_uid8_fpArccosPiTest_b)); expL_uid67_acosX_uid8_fpArccosPiTest_q <= expL_uid67_acosX_uid8_fpArccosPiTest_o(8 downto 0); --expLRange_uid69_acosX_uid8_fpArccosPiTest(BITSELECT,68)@7 expLRange_uid69_acosX_uid8_fpArccosPiTest_in <= expL_uid67_acosX_uid8_fpArccosPiTest_q(7 downto 0); expLRange_uid69_acosX_uid8_fpArccosPiTest_b <= expLRange_uid69_acosX_uid8_fpArccosPiTest_in(7 downto 0); --vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,315)@5 vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(33 downto 0); vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(33 downto 0); --cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,316)@5 cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & GND_q; --vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,317)@5 vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) BEGIN CASE vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN "1" => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest(BITSELECT,67)@5 fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in <= vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(33 downto 0); fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b <= fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in(33 downto 11); --ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a(DELAY,1359)@5 ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b, xout => ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0(REG,628)@6 reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q <= ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q; END IF; END IF; END PROCESS; --fpL_uid70_acosX_uid8_fpArccosPiTest(BITJOIN,69)@7 fpL_uid70_acosX_uid8_fpArccosPiTest_q <= GND_q & expLRange_uid69_acosX_uid8_fpArccosPiTest_b & reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q; --signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,327)@7 signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q; signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(31 downto 31); --expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,325)@7 expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q(30 downto 0); expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(30 downto 23); --expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,332)@7 expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b else "0"; --negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,375)@7 negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; END IF; END PROCESS; --ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c(DELAY,1099)@8 ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor(LOGICAL,1499) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q <= not (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a or ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top(CONSTANT,1495) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q <= "0110"; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp(LOGICAL,1496) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q); ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a = ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b else "0"; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg(REG,1497) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena(REG,1500) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q = "1") THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd(LOGICAL,1501) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b <= en; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a and ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b; --cstBiasM1_uid23_acosX_uid8_fpArccosPiTest(CONSTANT,22) cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q <= "01111110"; --reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0(REG,638)@7 reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(ADD,348)@8 expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q); expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q); expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b)); expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o(8 downto 0); --expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,349)@8 expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(8 downto 1); --expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(ADD,345)@8 expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q); expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b)); expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o(8 downto 0); --expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,346)@8 expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(8 downto 1); --expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,350)@7 expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(0 downto 0); expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(0 downto 0); --expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,351)@7 expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1067)@7 ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,352)@8 expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; WHEN "1" => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1079)@7 ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,340)@8 InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,326)@7 fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q(22 downto 0); fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1(REG,629)@7 reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,336)@8 fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q; fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b else "0"; --expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,334)@7 expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN IF (expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b) THEN expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1"; ELSE expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "0"; END IF; END IF; END PROCESS; --exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,337)@8 exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,341)@8 InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,342)@7 InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; END IF; END PROCESS; --exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,343)@8 exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b and exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c; --minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,361)@8 minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,362)@8 minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,338)@8 InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,339)@8 exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,363)@8 excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c <= minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a or excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b or excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c; --InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,359)@7 InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1077)@7 ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,360)@8 inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a(DELAY,1085)@7 ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,364)@8 join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q; --fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,365)@8 fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q & join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; --reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0(REG,630)@8 reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOOKUP,366)@9 fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q) IS WHEN "0000" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "0001" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "0010" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "0011" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "0100" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "0101" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "0110" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "0111" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "1000" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1001" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "1010" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1011" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1100" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1101" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1110" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1111" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN OTHERS => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,370)@9 expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; WHEN "10" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg(DELAY,1489) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt(COUNTER,1491) -- every=1, low=0, high=6, step=1, init=1 ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i = 5 THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i - 6; ELSE ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i,3)); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg(REG,1492) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux(MUX,1493) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s <= en; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s, ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q, ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; WHEN "1" => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem(DUALMEM,1490) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 7, width_b => 8, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia ); ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq(7 downto 0); --cstNaNWF_uid20_acosX_uid8_fpArccosPiTest(CONSTANT,19) cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000001"; --fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,354)@7 fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(22 downto 16); --addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,355)@7 addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0(REG,631)@7 reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q <= addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --memoryC2_uid568_sqrtTableGenerator_lutmem(DUALMEM,607)@8 memoryC2_uid568_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid568_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid568_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid568_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q; memoryC2_uid568_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC2_uid568_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid568_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid568_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid568_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid568_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid568_sqrtTableGenerator_lutmem_ia ); memoryC2_uid568_sqrtTableGenerator_lutmem_q <= memoryC2_uid568_sqrtTableGenerator_lutmem_iq(11 downto 0); --reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1(REG,633)@10 reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q <= memoryC2_uid568_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1488) ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a(DELAY,1073)@7 ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q, xout => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,356)@10 FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q(15 downto 0); FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(15 downto 0); --yT1_uid569_sqrtPolynomialEvaluator(BITSELECT,568)@10 yT1_uid569_sqrtPolynomialEvaluator_in <= FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; yT1_uid569_sqrtPolynomialEvaluator_b <= yT1_uid569_sqrtPolynomialEvaluator_in(15 downto 4); --reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0(REG,632)@10 reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q <= yT1_uid569_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator(MULT,593)@11 prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b); prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a <= reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q; prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q; prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr,24)); END IF; END IF; END PROCESS; prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q <= prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator(BITSELECT,594)@14 prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in <= prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in(23 downto 11); --highBBits_uid572_sqrtPolynomialEvaluator(BITSELECT,571)@14 highBBits_uid572_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b; highBBits_uid572_sqrtPolynomialEvaluator_b <= highBBits_uid572_sqrtPolynomialEvaluator_in(12 downto 1); --ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a(DELAY,1337)@8 ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1551) ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q, xout => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid567_sqrtTableGenerator_lutmem(DUALMEM,606)@12 memoryC1_uid567_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid567_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid567_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid567_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q; memoryC1_uid567_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC1_uid567_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid567_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid567_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid567_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid567_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid567_sqrtTableGenerator_lutmem_ia ); memoryC1_uid567_sqrtTableGenerator_lutmem_q <= memoryC1_uid567_sqrtTableGenerator_lutmem_iq(20 downto 0); --sumAHighB_uid573_sqrtPolynomialEvaluator(ADD,572)@14 sumAHighB_uid573_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid567_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid567_sqrtTableGenerator_lutmem_q); sumAHighB_uid573_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid572_sqrtPolynomialEvaluator_b(11)) & highBBits_uid572_sqrtPolynomialEvaluator_b); sumAHighB_uid573_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid573_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid573_sqrtPolynomialEvaluator_b)); sumAHighB_uid573_sqrtPolynomialEvaluator_q <= sumAHighB_uid573_sqrtPolynomialEvaluator_o(21 downto 0); --lowRangeB_uid571_sqrtPolynomialEvaluator(BITSELECT,570)@14 lowRangeB_uid571_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid571_sqrtPolynomialEvaluator_b <= lowRangeB_uid571_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid571_uid574_sqrtPolynomialEvaluator(BITJOIN,573)@14 s1_uid571_uid574_sqrtPolynomialEvaluator_q <= sumAHighB_uid573_sqrtPolynomialEvaluator_q & lowRangeB_uid571_sqrtPolynomialEvaluator_b; --reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1(REG,636)@14 reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q <= s1_uid571_uid574_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,1560) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a or ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b); --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg(REG,1558) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,1561) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,1562) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,1552) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,1554) -- every=1, low=0, high=1, step=1, init=1 ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,1)); --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,1555) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,1556) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,1553) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 16, widthad_a => 1, numwords_a => 2, width_b => 16, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq(15 downto 0); --reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0(REG,635)@14 reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator(MULT,596)@15 prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b); prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a <= reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q; prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b <= reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q; prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr,39)); END IF; END IF; END PROCESS; prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q <= prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator(BITSELECT,597)@18 prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in <= prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in(38 downto 15); --highBBits_uid578_sqrtPolynomialEvaluator(BITSELECT,577)@18 highBBits_uid578_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b; highBBits_uid578_sqrtPolynomialEvaluator_b <= highBBits_uid578_sqrtPolynomialEvaluator_in(23 downto 2); --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,1573) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,1574) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1575) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1563) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1564) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0(REG,637)@15 reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid566_sqrtTableGenerator_lutmem(DUALMEM,605)@16 memoryC0_uid566_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid566_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid566_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid566_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q; memoryC0_uid566_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 29, widthad_a => 8, numwords_a => 256, width_b => 29, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC0_uid566_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid566_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid566_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid566_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid566_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid566_sqrtTableGenerator_lutmem_ia ); memoryC0_uid566_sqrtTableGenerator_lutmem_q <= memoryC0_uid566_sqrtTableGenerator_lutmem_iq(28 downto 0); --sumAHighB_uid579_sqrtPolynomialEvaluator(ADD,578)@18 sumAHighB_uid579_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid566_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid566_sqrtTableGenerator_lutmem_q); sumAHighB_uid579_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid578_sqrtPolynomialEvaluator_b(21)) & highBBits_uid578_sqrtPolynomialEvaluator_b); sumAHighB_uid579_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid579_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid579_sqrtPolynomialEvaluator_b)); sumAHighB_uid579_sqrtPolynomialEvaluator_q <= sumAHighB_uid579_sqrtPolynomialEvaluator_o(29 downto 0); --lowRangeB_uid577_sqrtPolynomialEvaluator(BITSELECT,576)@18 lowRangeB_uid577_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid577_sqrtPolynomialEvaluator_b <= lowRangeB_uid577_sqrtPolynomialEvaluator_in(1 downto 0); --s2_uid577_uid580_sqrtPolynomialEvaluator(BITJOIN,579)@18 s2_uid577_uid580_sqrtPolynomialEvaluator_q <= sumAHighB_uid579_sqrtPolynomialEvaluator_q & lowRangeB_uid577_sqrtPolynomialEvaluator_b; --fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,358)@18 fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= s2_uid577_uid580_sqrtPolynomialEvaluator_q(28 downto 0); fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(28 downto 6); --ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1093)@9 ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 9 ) PORT MAP ( xin => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,374)@18 fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; WHEN "10" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,376)@18 RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q & ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q & fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; --SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest(BITSELECT,72)@18 SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q(22 downto 0); SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b <= SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,662)@18 reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,437)@19 fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1149)@19 ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest(BITSELECT,74)@18 SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q(30 downto 0); SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b <= SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in(30 downto 23); --reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,640)@18 reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,435)@19 expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1148)@19 ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,438)@31 exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,675)@31 reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,399)@20 RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 1); --rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,401)@20 rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest(BITJOIN,73)@18 oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q <= VCC_q & SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b; --X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,382)@18 X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q; X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 16); --rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,384)@18 rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4(REG,644)@18 reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,379)@18 X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q; X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 8); --rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,381)@18 rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3(REG,643)@18 reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2(REG,642)@18 reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --srVal_uid76_acosX_uid8_fpArccosPiTest(SUB,75)@19 srVal_uid76_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q); srVal_uid76_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q); srVal_uid76_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid76_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(srVal_uid76_acosX_uid8_fpArccosPiTest_b)); srVal_uid76_acosX_uid8_fpArccosPiTest_q <= srVal_uid76_acosX_uid8_fpArccosPiTest_o(8 downto 0); --srValRange_uid77_acosX_uid8_fpArccosPiTest(BITSELECT,76)@19 srValRange_uid77_acosX_uid8_fpArccosPiTest_in <= srVal_uid76_acosX_uid8_fpArccosPiTest_q(4 downto 0); srValRange_uid77_acosX_uid8_fpArccosPiTest_b <= srValRange_uid77_acosX_uid8_fpArccosPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,386)@19 rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b; rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(4 downto 3); --rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,387)@19 rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q, rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,394)@19 RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 6); --rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,396)@19 rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5(REG,649)@19 reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q <= rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,391)@19 RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 4); --rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,393)@19 rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4(REG,648)@19 reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,388)@19 RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 2); --rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,390)@19 rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3(REG,647)@19 reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2(REG,646)@19 reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,397)@19 rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(2 downto 1); --reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1(REG,645)@19 reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,398)@20 rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q, reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q) BEGIN CASE rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q; WHEN OTHERS => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,402)@19 rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1(REG,650)@19 reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,403)@20 rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN "1" => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --sAddr_uid80_acosX_uid8_fpArccosPiTest(BITSELECT,79)@20 sAddr_uid80_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; sAddr_uid80_acosX_uid8_fpArccosPiTest_b <= sAddr_uid80_acosX_uid8_fpArccosPiTest_in(23 downto 16); --reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0(REG,651)@20 reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid80_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid408_arcsinXO2XTabGen_lutmem(DUALMEM,601)@21 memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q; memoryC2_uid408_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC2_uid408_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia ); memoryC2_uid408_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1(REG,653)@23 reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q <= memoryC2_uid408_arcsinXO2XTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1448) ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q, xout => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a(DELAY,768)@20 ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 24, depth => 2 ) PORT MAP ( xin => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q, xout => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --sPPolyEval_uid81_acosX_uid8_fpArccosPiTest(BITSELECT,80)@23 sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in <= ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q(15 downto 0); sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b <= sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in(15 downto 1); --yT1_uid409_arcsinXO2XPolyEval(BITSELECT,408)@23 yT1_uid409_arcsinXO2XPolyEval_in <= sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b; yT1_uid409_arcsinXO2XPolyEval_b <= yT1_uid409_arcsinXO2XPolyEval_in(14 downto 3); --reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0(REG,652)@23 reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q <= yT1_uid409_arcsinXO2XPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval(MULT,581)@24 prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b); prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a <= reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q; prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b <= reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q; prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q <= prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval(BITSELECT,582)@27 prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in <= prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q; prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in(23 downto 11); --highBBits_uid412_arcsinXO2XPolyEval(BITSELECT,411)@27 highBBits_uid412_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b; highBBits_uid412_arcsinXO2XPolyEval_b <= highBBits_uid412_arcsinXO2XPolyEval_in(12 downto 1); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1576) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => sAddr_uid80_acosX_uid8_fpArccosPiTest_b, xout => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a(DELAY,1385)@20 ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, xout => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0(REG,654)@24 reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid407_arcsinXO2XTabGen_lutmem(DUALMEM,600)@25 memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q; memoryC1_uid407_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 19, widthad_a => 8, numwords_a => 256, width_b => 19, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC1_uid407_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia ); memoryC1_uid407_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq(18 downto 0); --sumAHighB_uid413_arcsinXO2XPolyEval(ADD,412)@27 sumAHighB_uid413_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid407_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid407_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid413_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid412_arcsinXO2XPolyEval_b(11)) & highBBits_uid412_arcsinXO2XPolyEval_b); sumAHighB_uid413_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid413_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid413_arcsinXO2XPolyEval_b)); sumAHighB_uid413_arcsinXO2XPolyEval_q <= sumAHighB_uid413_arcsinXO2XPolyEval_o(19 downto 0); --lowRangeB_uid411_arcsinXO2XPolyEval(BITSELECT,410)@27 lowRangeB_uid411_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b(0 downto 0); lowRangeB_uid411_arcsinXO2XPolyEval_b <= lowRangeB_uid411_arcsinXO2XPolyEval_in(0 downto 0); --s1_uid411_uid414_arcsinXO2XPolyEval(BITJOIN,413)@27 s1_uid411_uid414_arcsinXO2XPolyEval_q <= sumAHighB_uid413_arcsinXO2XPolyEval_q & lowRangeB_uid411_arcsinXO2XPolyEval_b; --reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1(REG,656)@27 reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q <= s1_uid411_uid414_arcsinXO2XPolyEval_q; END IF; END IF; END PROCESS; --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1585) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b); --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1586) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1587) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b <= en; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b; --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1577) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b, xout => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1578) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 1, numwords_a => 2, width_b => 15, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq, address_a => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa, data_a => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia ); ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0); --reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0(REG,655)@27 reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval(MULT,584)@28 prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b); prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q; prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b <= reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q; prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr,36)); END IF; END IF; END PROCESS; prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q <= prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval(BITSELECT,585)@31 prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in <= prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q; prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in(35 downto 14); --highBBits_uid418_arcsinXO2XPolyEval(BITSELECT,417)@31 highBBits_uid418_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b; highBBits_uid418_arcsinXO2XPolyEval_b <= highBBits_uid418_arcsinXO2XPolyEval_in(21 downto 2); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1598) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1599) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1600) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b; --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1589) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq, address_a => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa, data_a => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia ); ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0(REG,657)@28 reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid406_arcsinXO2XTabGen_lutmem(DUALMEM,599)@29 memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q; memoryC0_uid406_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC0_uid406_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia ); memoryC0_uid406_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq(29 downto 0); --sumAHighB_uid419_arcsinXO2XPolyEval(ADD,418)@31 sumAHighB_uid419_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid406_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid406_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid419_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid418_arcsinXO2XPolyEval_b(19)) & highBBits_uid418_arcsinXO2XPolyEval_b); sumAHighB_uid419_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid419_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid419_arcsinXO2XPolyEval_b)); sumAHighB_uid419_arcsinXO2XPolyEval_q <= sumAHighB_uid419_arcsinXO2XPolyEval_o(30 downto 0); --lowRangeB_uid417_arcsinXO2XPolyEval(BITSELECT,416)@31 lowRangeB_uid417_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b(1 downto 0); lowRangeB_uid417_arcsinXO2XPolyEval_b <= lowRangeB_uid417_arcsinXO2XPolyEval_in(1 downto 0); --s2_uid417_uid420_arcsinXO2XPolyEval(BITJOIN,419)@31 s2_uid417_uid420_arcsinXO2XPolyEval_q <= sumAHighB_uid419_arcsinXO2XPolyEval_q & lowRangeB_uid417_arcsinXO2XPolyEval_b; --fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest(BITSELECT,82)@31 fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in <= s2_uid417_uid420_arcsinXO2XPolyEval_q(30 downto 0); fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b <= fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in(30 downto 5); --fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest(BITSELECT,83)@31 fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in <= fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b(24 downto 0); fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b <= fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in(24 downto 2); --fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest(BITJOIN,84)@31 fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q & fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b; --expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,422)@31 expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q(30 downto 0); expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(30 downto 23); --expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,449)@31 expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,659)@31 reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,503)@32 excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,427)@31 fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q(22 downto 0); fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,660)@31 reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,453)@32 fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,451)@31 expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN IF (expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b) THEN expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1"; ELSE expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "0"; END IF; END IF; END PROCESS; --exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,454)@32 exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,433)@19 expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1212)@19 ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,504)@32 excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,505)@32 ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,455)@32 InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,456)@32 exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,439)@19 InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,440)@19 exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1242)@19 ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,506)@32 excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,518)@32 InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; END IF; END PROCESS; --signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,424)@31 signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q; signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(31 downto 31); --signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,423)@18 signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(31 downto 31); --ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a(DELAY,1410)@18 ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, xout => ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,679)@30 reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q; END IF; END IF; END PROCESS; --signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,489)@31 signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a xor signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END PROCESS; --ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1254)@32 ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,519)@33 signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1258)@33 ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,428)@31 add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= VCC_q & fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,666)@31 reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1523) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b); --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top(CONSTANT,1507) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q <= "01011"; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp(LOGICAL,1508) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q); ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b else "0"; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg(REG,1509) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1524) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1525) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt(COUNTER,1503) -- every=1, low=0, high=11, step=1, init=1 ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i = 10 THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i - 11; ELSE ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i,4)); --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg(REG,1504) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux(MUX,1505) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s <= en; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q) BEGIN CASE ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s IS WHEN "0" => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; WHEN "1" => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1514) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 4, numwords_a => 12, width_b => 24, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq, address_a => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa, data_a => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia ); ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(23 downto 0); --prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MULT,464)@32 prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr <= UNSIGNED(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) * UNSIGNED(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b); prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= (others => '0'); prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= (others => '0'); prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q; prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr); END IF; END IF; END PROCESS; prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,465)@35 normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(47 downto 47); --roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest(CONSTANT,200) roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q <= "010"; --fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,467)@35 fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(46 downto 0); fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(46 downto 23); --fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,468)@35 fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(45 downto 0); fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(45 downto 22); --fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,469)@35 fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b) BEGIN CASE fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; WHEN "1" => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,477)@35 FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(1 downto 0); FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(1 downto 0); --Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,471)@35 Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(22 downto 0); Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(22 downto 22); --extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,472)@35 extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, GND_q, Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b) BEGIN CASE extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,470)@35 stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(21 downto 0); stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(21 downto 0); --stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,473)@35 stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,475)@35 stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,476)@35 sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,478)@35 lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b & sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,480)@35 roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q; roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,481)@35 roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,484)@35 roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= GND_q & normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b & cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q & roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,670)@35 reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --biasInc_uid184_rAcosPi_uid13_fpArccosPiTest(CONSTANT,183) biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q <= "0001111111"; --reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,668)@31 reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1511) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b); --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1512) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1513) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1502) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 12, width_b => 8, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq, address_a => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa, data_a => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia ); ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(7 downto 0); --expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest(ADD,461)@32 expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q); expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q); expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(8 downto 0); --ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1175)@33 ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest(SUB,463)@34 expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q); expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q(9)) & biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q); expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(10 downto 0); --expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,482)@35 expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0(REG,669)@35 reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest(ADD,485)@36 expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q(34)) & reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q); expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q); expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) + SIGNED(expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(35 downto 0); --expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,487)@36 expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(35 downto 24); --expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,488)@36 expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(7 downto 0); expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(7 downto 0); --ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a(DELAY,1409)@36 ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, xout => ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3(REG,678)@37 reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1247)@32 ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,671)@36 reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest(COMPARE,492)@37 expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin <= GND_q; expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q) & '0'; expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) & expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin(0); expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n(0) <= not expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(14); --InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,457)@32 InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,458)@32 InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,459)@31 InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; END IF; END PROCESS; --exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,460)@32 exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1217)@32 ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1153)@19 ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,441)@31 InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,442)@31 InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,443)@19 InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1156)@19 ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,444)@31 exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1216)@31 ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 6 ) PORT MAP ( xin => exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,501)@37 ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n; ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1223)@31 ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,500)@32 excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1234)@32 ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,664)@31 reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,499)@32 excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1233)@32 ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,498)@32 excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1232)@32 ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,502)@37 excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d <= ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d; --expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest(COMPARE,490)@37 expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin <= GND_q; expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q) & expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin(0); expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n(0) <= not expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(14); --excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,496)@37 excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n; excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,495)@32 excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1221)@32 ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,494)@32 excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1220)@32 ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,658)@19 reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1210)@20 ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q, xout => ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,493)@32 excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1219)@32 ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,497)@37 excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d <= excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d; --concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,507)@37 concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q & excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0(REG,676)@37 reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOOKUP,508)@38 excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q) IS WHEN "000" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "001" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "010" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "011" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "100" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "101" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "110" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "111" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN OTHERS => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,517)@38 expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,486)@36 fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(23 downto 0); fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(23 downto 1); --reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3(REG,677)@36 reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d(DELAY,1250)@37 ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q, xout => ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,512)@38 fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q; WHEN "10" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,520)@38 R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q & expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest(BITSELECT,87)@38 ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in <= R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(22 downto 0); ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b <= ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in(22 downto 0); --oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest(BITJOIN,88)@38 oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q <= VCC_q & ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b; --X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,526)@38 X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q; X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 16); --rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,528)@38 rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4(REG,683)@38 reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,523)@38 X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q; X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 8); --rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,525)@38 rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3(REG,682)@38 reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2(REG,681)@38 reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest(BITSELECT,89)@38 ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in <= R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(30 downto 0); ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b <= ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in(30 downto 23); --srValArcsinL_uid91_acosX_uid8_fpArccosPiTest(SUB,90)@38 srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b); srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b)); srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q <= srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o(8 downto 0); --srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest(BITSELECT,91)@38 srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in <= srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q(4 downto 0); srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,530)@38 rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b; rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(4 downto 3); --reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,680)@38 reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,531)@39 rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q, rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,541)@38 rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(2 downto 1); --reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,684)@38 reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,542)@39 rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "01" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "10" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "11" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,546)@38 rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,685)@38 reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,547)@39 rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "1" => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest(BITJOIN,94)@39 pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q); --reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1(REG,686)@39 reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q <= pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --pi_uid94_acosX_uid8_fpArccosPiTest(CONSTANT,93) pi_uid94_acosX_uid8_fpArccosPiTest_q <= "1100100100001111110110101010"; --path1NegCase_uid95_acosX_uid8_fpArccosPiTest(SUB,95)@40 path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & pi_uid94_acosX_uid8_fpArccosPiTest_q); path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q); path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b)); path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o(28 downto 0); --path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest(BITSELECT,96)@40 path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(27 downto 0); path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in(27 downto 27); --reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1(REG,687)@40 reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest(ADD,100)@41 path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q); path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b)); path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q <= path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o(8 downto 0); --path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest(BITSELECT,101)@41 path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in <= path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q(7 downto 0); path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b <= path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in(7 downto 0); --path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest(BITSELECT,97)@40 path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(26 downto 0); path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b <= path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in(26 downto 4); --path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest(BITSELECT,98)@40 path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(25 downto 0); path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b <= path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in(25 downto 3); --path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest(MUX,99)@40 path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b; path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b; WHEN "1" => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest(BITJOIN,102)@41 path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q <= GND_q & path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b & path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q; --ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg(DELAY,1461) ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c(DELAY,790)@38 ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 2 ) PORT MAP ( xin => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q, xout => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor(LOGICAL,1458) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q <= not (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a or ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top(CONSTANT,1454) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q <= "0100111"; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp(LOGICAL,1455) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q); ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q <= "1" when ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a = ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b else "0"; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg(REG,1456) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena(REG,1459) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q = "1") THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd(LOGICAL,1460) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b <= en; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a and ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt(COUNTER,1450) -- every=1, low=0, high=39, step=1, init=1 ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i = 38 THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i - 39; ELSE ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i,6)); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg(REG,1451) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux(MUX,1452) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s <= en; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux: PROCESS (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s, ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q, ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; WHEN "1" => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem(DUALMEM,1449) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 <= areset; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia <= singX_uid17_acosX_uid8_fpArccosPiTest_b; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq, address_a => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa, data_a => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia ); ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq(0 downto 0); --path1ResFP_uid105_acosX_uid8_fpArccosPiTest(MUX,104)@41 path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q; path1ResFP_uid105_acosX_uid8_fpArccosPiTest: PROCESS (path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s, en, ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q, path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q) BEGIN CASE path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q; WHEN "1" => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest(BITSELECT,132)@41 Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in <= path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q(30 downto 0); Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b <= Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in(30 downto 23); --reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2(REG,699)@41 reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q <= Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1472) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a or ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b); --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top(CONSTANT,1468) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q <= "0100101"; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp(LOGICAL,1469) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q); ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q <= "1" when ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a = ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b else "0"; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg(REG,1470) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1473) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1474) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c(DELAY,812)@0 ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => singX_uid17_acosX_uid8_fpArccosPiTest_b, xout => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --inputIsMax_uid60_acosX_uid8_fpArccosPiTest(BITSELECT,59)@1 inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b <= inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in(36 downto 36); --firstPath_uid62_acosX_uid8_fpArccosPiTest(BITSELECT,61)@1 firstPath_uid62_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b; firstPath_uid62_acosX_uid8_fpArccosPiTest_b <= firstPath_uid62_acosX_uid8_fpArccosPiTest_in(34 downto 34); --pathSelBits_uid126_acosX_uid8_fpArccosPiTest(BITJOIN,125)@1 pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q & inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b & firstPath_uid62_acosX_uid8_fpArccosPiTest_b; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1462) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q, xout => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt(COUNTER,1464) -- every=1, low=0, high=37, step=1, init=1 ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i = 36 THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i - 37; ELSE ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i,6)); --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg(REG,1465) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux(MUX,1466) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s <= en; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s, ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q, ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q) BEGIN CASE ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s IS WHEN "0" => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; WHEN "1" => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1463) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 6, numwords_a => 38, width_b => 3, widthad_b => 6, numwords_b => 38, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq, address_a => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa, data_a => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia ); ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(2 downto 0); --fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest(LOOKUP,126)@41 fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q) IS WHEN "000" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "001" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "010" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "011" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "100" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "101" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "110" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "111" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN OTHERS => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; END IF; END PROCESS; --expRCalc_uid134_acosX_uid8_fpArccosPiTest(MUX,133)@42 expRCalc_uid134_acosX_uid8_fpArccosPiTest_s <= fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q; expRCalc_uid134_acosX_uid8_fpArccosPiTest: PROCESS (expRCalc_uid134_acosX_uid8_fpArccosPiTest_s, en, reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q, reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q, cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRCalc_uid134_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --cstAllZWE_uid21_acosX_uid8_fpArccosPiTest(CONSTANT,20) cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q <= "00000000"; --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor(LOGICAL,1485) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q <= not (ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a or ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b); --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena(REG,1486) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q = "1") THEN ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd(LOGICAL,1487) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b <= en; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a and ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b; --fracXIsZero_uid47_acosX_uid8_fpArccosPiTest(LOGICAL,46)@0 fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a <= fracX_uid16_acosX_uid8_fpArccosPiTest_b; fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q); fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b else "0"; --InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest(LOGICAL,47)@0 InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a; --expEQ0_uid46_acosX_uid8_fpArccosPiTest(LOGICAL,45)@0 expEQ0_uid46_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b; expEQ0_uid46_acosX_uid8_fpArccosPiTest_b <= cstBias_uid22_acosX_uid8_fpArccosPiTest_q; expEQ0_uid46_acosX_uid8_fpArccosPiTest_q <= "1" when expEQ0_uid46_acosX_uid8_fpArccosPiTest_a = expEQ0_uid46_acosX_uid8_fpArccosPiTest_b else "0"; --expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest(LOGICAL,48)@0 expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a <= expEQ0_uid46_acosX_uid8_fpArccosPiTest_q; expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q; expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q <= expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a and expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b; --expGT0_uid45_acosX_uid8_fpArccosPiTest(COMPARE,44)@0 expGT0_uid45_acosX_uid8_fpArccosPiTest_cin <= GND_q; expGT0_uid45_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q) & '0'; expGT0_uid45_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_acosX_uid8_fpArccosPiTest_b) & expGT0_uid45_acosX_uid8_fpArccosPiTest_cin(0); expGT0_uid45_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid45_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(expGT0_uid45_acosX_uid8_fpArccosPiTest_b)); expGT0_uid45_acosX_uid8_fpArccosPiTest_c(0) <= expGT0_uid45_acosX_uid8_fpArccosPiTest_o(10); --inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest(LOGICAL,49)@0 inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a <= expGT0_uid45_acosX_uid8_fpArccosPiTest_c; inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b <= expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q; inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q <= inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a or inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b; --InvExc_N_uid41_acosX_uid8_fpArccosPiTest(LOGICAL,40)@0 InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a <= exc_N_uid40_acosX_uid8_fpArccosPiTest_q; InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a; --InvExc_I_uid42_acosX_uid8_fpArccosPiTest(LOGICAL,41)@0 InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a <= exc_I_uid38_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a; --expXIsZero_uid33_acosX_uid8_fpArccosPiTest(LOGICAL,32)@0 expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b; expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b else "0"; --InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest(LOGICAL,42)@0 InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a; --exc_R_uid44_acosX_uid8_fpArccosPiTest(LOGICAL,43)@0 exc_R_uid44_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q; exc_R_uid44_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q; exc_R_uid44_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q; exc_R_uid44_acosX_uid8_fpArccosPiTest_q <= exc_R_uid44_acosX_uid8_fpArccosPiTest_a and exc_R_uid44_acosX_uid8_fpArccosPiTest_b and exc_R_uid44_acosX_uid8_fpArccosPiTest_c; --xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest(LOGICAL,134)@0 xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a <= exc_R_uid44_acosX_uid8_fpArccosPiTest_q; xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b <= inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q; xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q <= xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a and xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b; --fracXIsZero_uid37_acosX_uid8_fpArccosPiTest(LOGICAL,36)@0 fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a <= fracX_uid16_acosX_uid8_fpArccosPiTest_b; fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b else "0"; --expXIsMax_uid35_acosX_uid8_fpArccosPiTest(LOGICAL,34)@0 expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b; expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b else "0"; --exc_I_uid38_acosX_uid8_fpArccosPiTest(LOGICAL,37)@0 exc_I_uid38_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q; exc_I_uid38_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q; exc_I_uid38_acosX_uid8_fpArccosPiTest_q <= exc_I_uid38_acosX_uid8_fpArccosPiTest_a and exc_I_uid38_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest(LOGICAL,38)@0 InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a; --exc_N_uid40_acosX_uid8_fpArccosPiTest(LOGICAL,39)@0 exc_N_uid40_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q; exc_N_uid40_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q; exc_N_uid40_acosX_uid8_fpArccosPiTest_q <= exc_N_uid40_acosX_uid8_fpArccosPiTest_a and exc_N_uid40_acosX_uid8_fpArccosPiTest_b; --excRNaN_uid136_acosX_uid8_fpArccosPiTest(LOGICAL,135)@0 excRNaN_uid136_acosX_uid8_fpArccosPiTest_a <= exc_N_uid40_acosX_uid8_fpArccosPiTest_q; excRNaN_uid136_acosX_uid8_fpArccosPiTest_b <= exc_I_uid38_acosX_uid8_fpArccosPiTest_q; excRNaN_uid136_acosX_uid8_fpArccosPiTest_c <= xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q; excRNaN_uid136_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid136_acosX_uid8_fpArccosPiTest_a or excRNaN_uid136_acosX_uid8_fpArccosPiTest_b or excRNaN_uid136_acosX_uid8_fpArccosPiTest_c; --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg(DELAY,1475) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => excRNaN_uid136_acosX_uid8_fpArccosPiTest_q, xout => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem(DUALMEM,1476) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0 <= areset; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 38, width_b => 1, widthad_b => 6, numwords_b => 38, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq, address_a => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa, data_a => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia ); ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq(0 downto 0); --excSelBits_uid137_acosX_uid8_fpArccosPiTest(BITJOIN,136)@40 excSelBits_uid137_acosX_uid8_fpArccosPiTest_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q & GND_q & GND_q; --reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0(REG,608)@40 reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q <= excSelBits_uid137_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest(LOOKUP,137)@41 outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest: PROCESS (reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1(REG,701)@41 reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q <= outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --expRPostExc_uid140_acosX_uid8_fpArccosPiTest(MUX,139)@42 expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s <= reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q; expRPostExc_uid140_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, expRCalc_uid134_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= expRCalc_uid134_acosX_uid8_fpArccosPiTest_q; WHEN "10" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --piF_uid128_acosX_uid8_fpArccosPiTest(BITSELECT,127)@42 piF_uid128_acosX_uid8_fpArccosPiTest_in <= pi_uid94_acosX_uid8_fpArccosPiTest_q(26 downto 0); piF_uid128_acosX_uid8_fpArccosPiTest_b <= piF_uid128_acosX_uid8_fpArccosPiTest_in(26 downto 4); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor(LOGICAL,1613) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a or ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena(REG,1614) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q = "1") THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd(LOGICAL,1615) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b <= en; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b; --Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest(BITSELECT,128)@13 Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in <= path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q(22 downto 0); Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b <= Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in(22 downto 0); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg(DELAY,1603) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b, xout => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem(DUALMEM,1604) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 <= areset; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 5, numwords_a => 26, width_b => 23, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0, clock1 => clk, address_b => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq, address_a => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa, data_a => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia ); ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq(22 downto 0); --reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3(REG,698)@41 reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q; END IF; END IF; END PROCESS; --Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest(BITSELECT,129)@41 Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in <= path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q(22 downto 0); Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b <= Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2(REG,697)@41 reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q <= Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracRCalc_uid131_acosX_uid8_fpArccosPiTest(MUX,130)@42 fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s <= fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q; fracRCalc_uid131_acosX_uid8_fpArccosPiTest: PROCESS (fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s, en, reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q, reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q, piF_uid128_acosX_uid8_fpArccosPiTest_b, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= piF_uid128_acosX_uid8_fpArccosPiTest_b; WHEN "11" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b(DELAY,832)@41 ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q, xout => ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid139_acosX_uid8_fpArccosPiTest(MUX,138)@42 fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s <= ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q; fracRPostExc_uid139_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q; WHEN "10" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --sR_uid141_acosX_uid8_fpArccosPiTest(BITJOIN,140)@42 sR_uid141_acosX_uid8_fpArccosPiTest_q <= GND_q & expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q & fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q; --fracX_uid147_rAcosPi_uid13_fpArccosPiTest(BITSELECT,146)@42 fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q(22 downto 0); fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b <= fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in(22 downto 0); --fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest(LOGICAL,158)@42 fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a <= fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b; fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q <= "1" when fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a = fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b else "0"; --expX_uid143_rAcosPi_uid13_fpArccosPiTest(BITSELECT,142)@42 expX_uid143_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q(30 downto 0); expX_uid143_rAcosPi_uid13_fpArccosPiTest_b <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_in(30 downto 23); --expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest(LOGICAL,156)@42 expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_b; expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a = expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b else "0"; --exc_I_uid160_rAcosPi_uid13_fpArccosPiTest(LOGICAL,159)@42 exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b <= fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a and exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b; --ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a(DELAY,1442)@42 ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2(REG,711)@43 reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q <= ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q; END IF; END IF; END PROCESS; --ooPi_uid9_fpArccosPiTest(CONSTANT,8) ooPi_uid9_fpArccosPiTest_q <= "101000101111100110000011"; --fracOOPi_uid10_fpArccosPiTest(BITSELECT,9)@43 fracOOPi_uid10_fpArccosPiTest_in <= ooPi_uid9_fpArccosPiTest_q(22 downto 0); fracOOPi_uid10_fpArccosPiTest_b <= fracOOPi_uid10_fpArccosPiTest_in(22 downto 0); --fpOOPi_uid11_fpArccosPiTest(BITJOIN,10)@43 fpOOPi_uid11_fpArccosPiTest_q <= GND_q & cstBiasM2_uid6_fpArccosPiTest_q & fracOOPi_uid10_fpArccosPiTest_b; --expY_uid144_rAcosPi_uid13_fpArccosPiTest(BITSELECT,143)@43 expY_uid144_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q(30 downto 0); expY_uid144_rAcosPi_uid13_fpArccosPiTest_b <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_in(30 downto 23); --expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest(LOGICAL,170)@43 expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_b; expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a = expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b else "0"; --reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1(REG,710)@43 reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest(LOGICAL,224)@44 excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a <= reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q; excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b <= reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q; excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q <= excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a and excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b; --fracY_uid149_rAcosPi_uid13_fpArccosPiTest(BITSELECT,148)@43 fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q(22 downto 0); fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b <= fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in(22 downto 0); --fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest(LOGICAL,174)@43 fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a <= fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b; fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q <= "1" when fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a = fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b else "0"; --expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest(LOGICAL,172)@43 expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_b; expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a = expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b else "0"; --exc_I_uid176_rAcosPi_uid13_fpArccosPiTest(LOGICAL,175)@43 exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b <= fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a and exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b; --expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest(LOGICAL,154)@42 expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_b; expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a = expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b else "0"; --ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a(DELAY,911)@42 ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest(LOGICAL,225)@43 excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q; excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b; END IF; END PROCESS; --ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest(LOGICAL,226)@44 ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a <= excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q; ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b <= excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q; ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q <= ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a or ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b; --InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest(LOGICAL,176)@43 InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a <= fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q; InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q <= not InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a; --exc_N_uid178_rAcosPi_uid13_fpArccosPiTest(LOGICAL,177)@43 exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b <= InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a and exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b; --reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2(REG,713)@43 reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest(LOGICAL,160)@42 InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a <= fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q; InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q <= not InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a; --exc_N_uid162_rAcosPi_uid13_fpArccosPiTest(LOGICAL,161)@42 exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b <= InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a and exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b; --reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1(REG,712)@42 reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a(DELAY,943)@43 ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q, xout => ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest(LOGICAL,227)@44 excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a <= ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q; excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b <= reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q; excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c <= ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q; excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q <= excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a or excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b or excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c; --VCC(CONSTANT,1) VCC_q <= "1"; --InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest(LOGICAL,239)@44 InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a <= excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q; InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q <= not InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a; --signY_uid146_rAcosPi_uid13_fpArccosPiTest(BITSELECT,145)@43 signY_uid146_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q; signY_uid146_rAcosPi_uid13_fpArccosPiTest_b <= signY_uid146_rAcosPi_uid13_fpArccosPiTest_in(31 downto 31); --signX_uid145_rAcosPi_uid13_fpArccosPiTest(BITSELECT,144)@42 signX_uid145_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q; signX_uid145_rAcosPi_uid13_fpArccosPiTest_b <= signX_uid145_rAcosPi_uid13_fpArccosPiTest_in(31 downto 31); --ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a(DELAY,907)@42 ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid145_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signR_uid211_rAcosPi_uid13_fpArccosPiTest(LOGICAL,210)@43 signR_uid211_rAcosPi_uid13_fpArccosPiTest_a <= ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q; signR_uid211_rAcosPi_uid13_fpArccosPiTest_b <= signY_uid146_rAcosPi_uid13_fpArccosPiTest_b; signR_uid211_rAcosPi_uid13_fpArccosPiTest_q <= signR_uid211_rAcosPi_uid13_fpArccosPiTest_a xor signR_uid211_rAcosPi_uid13_fpArccosPiTest_b; --ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a(DELAY,955)@43 ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid211_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest(LOGICAL,240)@44 signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a <= ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q; signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b <= InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q; signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q <= signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a and signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b; END IF; END PROCESS; --ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c(DELAY,959)@45 ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest(BITJOIN,149)@43 add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q <= VCC_q & fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b; --add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest(BITJOIN,147)@42 add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q <= VCC_q & fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b; --reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0(REG,702)@42 reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q <= add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --prod_uid186_rAcosPi_uid13_fpArccosPiTest(MULT,185)@43 prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr <= UNSIGNED(prod_uid186_rAcosPi_uid13_fpArccosPiTest_a) * UNSIGNED(prod_uid186_rAcosPi_uid13_fpArccosPiTest_b); prod_uid186_rAcosPi_uid13_fpArccosPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_a <= (others => '0'); prod_uid186_rAcosPi_uid13_fpArccosPiTest_b <= (others => '0'); prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_a <= reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q; prod_uid186_rAcosPi_uid13_fpArccosPiTest_b <= add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q; prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr); END IF; END IF; END PROCESS; prod_uid186_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_q <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest(BITSELECT,186)@46 normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q; normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in(47 downto 47); --fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest(BITSELECT,188)@46 fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(46 downto 0); fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b <= fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in(46 downto 23); --fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest(BITSELECT,189)@46 fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(45 downto 0); fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b <= fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in(45 downto 22); --fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest(MUX,190)@46 fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b; fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest: PROCESS (fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s, en, fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b, fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b) BEGIN CASE fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "0" => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b; WHEN "1" => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b; WHEN OTHERS => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest(BITSELECT,198)@46 FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in <= fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q(1 downto 0); FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b <= FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in(1 downto 0); --Prod22_uid193_rAcosPi_uid13_fpArccosPiTest(BITSELECT,192)@46 Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(22 downto 0); Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b <= Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in(22 downto 22); --extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest(MUX,193)@46 extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b; extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest: PROCESS (extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s, en, GND_q, Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b) BEGIN CASE extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "0" => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b; WHEN OTHERS => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest(BITSELECT,191)@46 stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(21 downto 0); stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b <= stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in(21 downto 0); --stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest(BITJOIN,194)@46 stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q <= extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q & stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b; --stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest(LOGICAL,196)@46 stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a <= stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q; stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q <= "1" when stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a = stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b else "0"; --sticky_uid198_rAcosPi_uid13_fpArccosPiTest(LOGICAL,197)@46 sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a <= stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q; sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q <= not sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a; --lrs_uid200_rAcosPi_uid13_fpArccosPiTest(BITJOIN,199)@46 lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q <= FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b & sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q; --roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest(LOGICAL,201)@46 roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a <= lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q; roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b <= roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q; roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q <= "1" when roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a = roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b else "0"; --roundBit_uid203_rAcosPi_uid13_fpArccosPiTest(LOGICAL,202)@46 roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a <= roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q; roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q <= not roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a; --roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest(BITJOIN,205)@46 roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q <= GND_q & normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b & cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q & roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q; --reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1(REG,704)@46 reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q <= roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a(DELAY,874)@42 ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expX_uid143_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSum_uid183_rAcosPi_uid13_fpArccosPiTest(ADD,182)@43 expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q); expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & expY_uid144_rAcosPi_uid13_fpArccosPiTest_b); expSum_uid183_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a) + UNSIGNED(expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q <= expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o(8 downto 0); --ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a(DELAY,876)@44 ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest(SUB,184)@45 expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q); expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q(9)) & biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q); expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q <= expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o(10 downto 0); --expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest(BITJOIN,203)@46 expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q <= expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q & fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q; --reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0(REG,703)@46 reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q <= expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest(ADD,206)@47 expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q(34)) & reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q); expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q); expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a) + SIGNED(expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b)); expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o(35 downto 0); --expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest(BITSELECT,208)@47 expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q; expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in(35 downto 24); --expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest(BITSELECT,209)@47 expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b(7 downto 0); expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b <= expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in(7 downto 0); --ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a(DELAY,1447)@47 ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3(REG,716)@48 reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q <= ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c(DELAY,948)@44 ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1(REG,705)@47 reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid214_rAcosPi_uid13_fpArccosPiTest(COMPARE,213)@48 expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin <= GND_q; expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q) & '0'; expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) & expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin(0); expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b)); expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n(0) <= not expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o(14); --InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest(LOGICAL,178)@43 InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q; InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a; --InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest(LOGICAL,179)@43 InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a; --InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest(LOGICAL,180)@43 InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q <= not InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a; --exc_R_uid182_rAcosPi_uid13_fpArccosPiTest(LOGICAL,181)@43 exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a <= InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b <= InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c <= InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a and exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b and exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c; --ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b(DELAY,918)@43 ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest(LOGICAL,162)@42 InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q; InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a; END IF; END PROCESS; --InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest(LOGICAL,163)@42 InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q; InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a; END IF; END PROCESS; --InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest(LOGICAL,164)@42 InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q; InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q <= not InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a; END IF; END PROCESS; --exc_R_uid166_rAcosPi_uid13_fpArccosPiTest(LOGICAL,165)@43 exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a <= InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b <= InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c <= InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a and exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b and exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c; --ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a(DELAY,917)@43 ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest(LOGICAL,222)@48 ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a <= ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q; ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b <= ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q; ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c <= expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n; ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q <= ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a and ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b and ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c; --reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1(REG,706)@42 reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b(DELAY,929)@43 ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q, xout => ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1(REG,707)@43 reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest(LOGICAL,221)@44 excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a <= reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q; excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b <= ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q; excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q <= excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a and excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b; --ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c(DELAY,935)@44 ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest(LOGICAL,220)@43 excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q; excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q <= excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a and excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b(DELAY,934)@43 ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest(LOGICAL,219)@43 excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a <= reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q; excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q <= excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a and excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a(DELAY,933)@43 ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid224_rAcosPi_uid13_fpArccosPiTest(LOGICAL,223)@48 excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a <= ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b <= ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c <= ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d <= ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q <= excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d; --expUdf_uid212_rAcosPi_uid13_fpArccosPiTest(COMPARE,211)@48 expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin <= GND_q; expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q) & expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin(0); expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b)); expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n(0) <= not expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o(14); --excZC3_uid218_rAcosPi_uid13_fpArccosPiTest(LOGICAL,217)@48 excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a <= ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q; excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b <= ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q; excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c <= expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n; excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q <= excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a and excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b and excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c; --excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest(LOGICAL,216)@43 excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q; excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q <= excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a and excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b; --ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c(DELAY,922)@43 ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest(LOGICAL,215)@43 excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q; excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q; excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b(DELAY,921)@43 ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest(LOGICAL,214)@43 excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q; excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a(DELAY,920)@43 ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid219_rAcosPi_uid13_fpArccosPiTest(LOGICAL,218)@48 excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a <= ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b <= ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c <= ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d <= excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q <= excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d; --concExc_uid229_rAcosPi_uid13_fpArccosPiTest(BITJOIN,228)@48 concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q <= ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q & excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q & excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q; --reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0(REG,714)@48 reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q <= concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid230_rAcosPi_uid13_fpArccosPiTest(LOOKUP,229)@49 excREnc_uid230_rAcosPi_uid13_fpArccosPiTest: PROCESS (reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q) IS WHEN "000" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "01"; WHEN "001" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "010" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "10"; WHEN "011" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "100" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "11"; WHEN "101" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "110" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "111" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN OTHERS => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest(MUX,238)@49 expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s <= excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q; expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest: PROCESS (expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q; WHEN "10" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest(BITSELECT,207)@47 fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q(23 downto 0); fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b <= fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in(23 downto 1); --reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3(REG,715)@47 reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q <= fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d(DELAY,951)@48 ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q, xout => ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest(MUX,233)@49 fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s <= excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q; fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest: PROCESS (fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q; WHEN "10" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid242_rAcosPi_uid13_fpArccosPiTest(BITJOIN,241)@49 R_uid242_rAcosPi_uid13_fpArccosPiTest_q <= ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q & expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q & fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q; --xOut(GPOUT,4)@49 q <= R_uid242_rAcosPi_uid13_fpArccosPiTest_q; end normal;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_lsft36.vhd	10	4582	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_LSFT36.VHD * --* * --* Function: 36 bit Left Shift * --* * --* 22/12/09 ML * --* * --* (c) 2009 Altera Corporation * --* * --* Change History * --* * --* * --* * --************************************************* ENTITY fp_lsft36 IS PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); END fp_lsft36; ARCHITECTURE sft OF fp_lsft36 IS signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1); BEGIN levzip <= inbus; -- shift by 0,1,2,3 levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1))); levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(1) AND NOT(shift(2)) AND shift(1)); levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(2) AND NOT(shift(2)) AND shift(1)) OR (levzip(1) AND shift(2) AND NOT(shift(1))); gaa: FOR k IN 4 TO 36 GENERATE levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR (levzip(k-2) AND shift(2) AND NOT(shift(1))) OR (levzip(k-3) AND shift(2) AND shift(1)); END GENERATE; -- shift by 0,4,8,12 gba: FOR k IN 1 TO 4 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))); END GENERATE; gbb: FOR k IN 5 TO 8 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k-4) AND NOT(shift(4)) AND shift(3)); END GENERATE; gbc: FOR k IN 9 TO 12 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k-4) AND NOT(shift(4)) AND shift(3)) OR (levone(k-8) AND shift(4) AND NOT(shift(3))); END GENERATE; gbd: FOR k IN 13 TO 36 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k-4) AND NOT(shift(4)) AND shift(3)) OR (levone(k-8) AND shift(4) AND NOT(shift(3))) OR (levone(k-12) AND shift(4) AND shift(3)); END GENERATE; -- shift by 0,16,32 gca: FOR k IN 1 TO 16 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))); END GENERATE; gcb: FOR k IN 17 TO 32 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k-16) AND NOT(shift(6)) AND shift(5)); END GENERATE; gcc: FOR k IN 33 TO 36 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(k-32) AND shift(6) AND NOT(shift(5))); END GENERATE; outbus <= levthr; END sft;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_ln_core.vhd	10	16472	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* SINGLE PRECISION LOG(e) - CORE * --* * --* FP_LN_CORE.VHD * --* * --* Function: Single Precision LOG (LN) Core * --* * --* 22/02/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --*********************************************** --*********************************************** --* Notes: * --* Latency = 19 * --*********************************************** ENTITY fp_ln_core IS GENERIC (synthesize : integer := 0); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1); aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); ccsgn : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); END fp_ln_core; ARCHITECTURE rtl OF fp_ln_core IS signal zerovec : STD_LOGIC_VECTOR (32 DOWNTO 1); -- input signal aamanff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal aaexpff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal aaexppos, aaexpneg : STD_LOGIC_VECTOR (9 DOWNTO 1); signal aaexpabs, aaexpabsff : STD_LOGIC_VECTOR (7 DOWNTO 1); -- range reduction signal lutpowaddff : STD_LOGIC_VECTOR (7 DOWNTO 1); signal lutoneaddff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal lutpowmanff, lutonemanff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal lutpowexpff, lutoneexpff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal lutoneinvff : STD_LOGIC_VECTOR (11 DOWNTO 1); signal lutpowmannode, lutonemannode : STD_LOGIC_VECTOR (23 DOWNTO 1); signal lutpowexpnode, lutoneexpnode : STD_LOGIC_VECTOR (8 DOWNTO 1); signal lutoneinvnode : STD_LOGIC_VECTOR (11 DOWNTO 1); signal aanum, aanumdel : STD_LOGIC_VECTOR (24 DOWNTO 1); signal mulonenode : STD_LOGIC_VECTOR (35 DOWNTO 1); signal mulonenormff : STD_LOGIC_VECTOR (34 DOWNTO 1); -- series signal squared : STD_LOGIC_VECTOR (36 DOWNTO 1); signal cubed : STD_LOGIC_VECTOR (36 DOWNTO 1); signal scaled : STD_LOGIC_VECTOR (36 DOWNTO 1); signal onethird : STD_LOGIC_VECTOR (18 DOWNTO 1); signal mulonedel : STD_LOGIC_VECTOR (26 DOWNTO 1); signal oneterm, twoterm, thrterm : STD_LOGIC_VECTOR (32 DOWNTO 1); signal seriesoneff, seriesonedelff, seriestwoff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numtwo : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exptwo : STD_LOGIC_VECTOR (8 DOWNTO 1); -- addition signal zeroone, zeropow : STD_LOGIC; signal numberone, numberonedel : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numpow, numone : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numpowsigned : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exppow, expone : STD_LOGIC_VECTOR (8 DOWNTO 1); signal numpowone, numpowonedel : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exppowone, exppowonedel : STD_LOGIC_VECTOR (8 DOWNTO 1); signal numsum : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numsumabs : STD_LOGIC_VECTOR (32 DOWNTO 1); signal expsum : STD_LOGIC_VECTOR (8 DOWNTO 1); signal ccmannode : STD_LOGIC_VECTOR (24 DOWNTO 1); signal ccexpnode : STD_LOGIC_VECTOR (8 DOWNTO 1); signal signff : STD_LOGIC_VECTOR (18 DOWNTO 1); component fp_lnlutpow PORT ( add : IN STD_LOGIC_VECTOR (7 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); end component; component fp_lnlut8 PORT ( add : IN STD_LOGIC_VECTOR (8 DOWNTO 1); inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); end component; component fp_del GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_fxmul GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_lnadd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aaman : IN STD_LOGIC_VECTOR (32 DOWNTO 1); aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); bbman : IN STD_LOGIC_VECTOR (32 DOWNTO 1); bbexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); ccman : OUT STD_LOGIC_VECTOR (32 DOWNTO 1); ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); end component; component fp_lnnorm PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inman : IN STD_LOGIC_VECTOR (32 DOWNTO 1); inexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); outman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); outexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); zero : OUT STD_LOGIC ); end component; BEGIN gza: FOR k IN 1 TO 32 GENERATE zerovec(k) <= '0'; END GENERATE; --*************** --* INPUT BLOCK * --*************** ppin: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 23 LOOP aamanff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP aaexpff(k) <= '0'; END LOOP; FOR k IN 1 TO 7 LOOP aaexpabsff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aamanff <= aaman; -- level 1 aaexpff <= aaexp; -- level 1 aaexpabsff <= aaexpabs; -- level 2 END IF; END IF; END PROCESS; aaexppos <= ('0' & aaexpff) - "001111111"; aaexpneg <= "001111111" - ('0' & aaexpff); gaba: FOR k IN 1 TO 7 GENERATE aaexpabs(k) <= (aaexppos(k) AND NOT(aaexppos(9))) OR (aaexpneg(k) AND aaexppos(9)); END GENERATE; --************************************** --* RANGE REDUCTION THROUGH LUT SERIES * --**************************************** plut: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 7 LOOP lutpowaddff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP lutoneaddff(k) <= '0'; END LOOP; FOR k IN 1 TO 23 LOOP lutpowmanff(k) <= '0'; lutonemanff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP lutpowexpff(k) <= '0'; lutoneexpff(k) <= '0'; END LOOP; FOR k IN 1 TO 11 LOOP lutoneinvff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN lutpowaddff <= aaexpabsff; -- level 3 lutoneaddff <= aamanff(23 DOWNTO 16); -- level 2 lutpowmanff <= lutpowmannode; -- level 4 lutpowexpff <= lutpowexpnode; -- level 4 lutoneinvff <= lutoneinvnode; -- level 3 lutonemanff <= lutonemannode; -- level 3 lutoneexpff <= lutoneexpnode; -- level 3 END IF; END IF; END PROCESS; lutpow: fp_lnlutpow PORT MAP (add=>lutpowaddff, logman=>lutpowmannode,logexp=>lutpowexpnode); lutone: fp_lnlut8 PORT MAP (add=>lutoneaddff, inv=>lutoneinvnode,logman=>lutonemannode,logexp=>lutoneexpnode); aanum <= '1' & aamanff; -- level 1 in, level 3 out delone: fp_del GENERIC MAP (width=>24,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aanum,cc=>aanumdel); --mulone <= aanum * invone; -- 2411 = 35 -- level 3 in, level 6 out mulone: fp_fxmul GENERIC MAP (widthaa=>24,widthbb=>11,widthcc=>35, pipes=>3,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>aanumdel,databb=>lutoneinvff, result=>mulonenode); pmna: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 34 LOOP mulonenormff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN -- normalize in case input is 1.000000 and inv is 0.5 -- level 7 FOR k IN 1 TO 34 LOOP mulonenormff(k) <= (mulonenode(k+1) AND mulonenode(35)) OR (mulonenode(k) AND NOT(mulonenode(35))); END LOOP; END IF; END IF; END PROCESS; --******************************************************** --* taylor series expansion of subrange (15 bits) * --* x - xx/2 --* 7 leading bits, so xx 7 bits down, +1 bit for 1/2 --********************************************************* --square <= mulonenorm(25 DOWNTO 8) * mulonenorm(25 DOWNTO 8); --cubed <= square(36 DOWNTO 19) * mulonenorm(25 DOWNTO 8); --cubedscale <= cubed(36 DOWNTO 19) * onethird; onethird <= "010101010101010101"; -- level 7 in, level 9 out multwo: fp_fxmul GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36, pipes=>2,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>mulonenormff(26 DOWNTO 9),databb=>mulonenormff(26 DOWNTO 9), result=>squared); -- level 7 in, level 9 out multhr: fp_fxmul GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36, pipes=>2,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>mulonenormff(26 DOWNTO 9),databb=>onethird, result=>scaled); -- level 9 in, level 11 out mulfor: fp_fxmul GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36, pipes=>2,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>squared(36 DOWNTO 19),databb=>scaled(36 DOWNTO 19), result=>cubed); oneterm <= mulonenormff(26 DOWNTO 1) & zerovec(6 DOWNTO 1); twoterm <= zerovec(7 DOWNTO 1) & squared(36 DOWNTO 12); thrterm <= zerovec(14 DOWNTO 1) & cubed(36 DOWNTO 19); --numtwo <= '0' & ((mulonenorm(25 DOWNTO 1) & zerovec(6 DOWNTO 1)) - -- (zerovec(9 DOWNTO 1) & square(36 DOWNTO 15)) + -- (zerovec(16 DOWNTO 1) & cubedscale(36 DOWNTO 22))); -- level 7 in, level 9 out deltwo: fp_del GENERIC MAP (width=>26,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>mulonenormff(26 DOWNTO 1),cc=>mulonedel); ptay: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP seriesoneff(k) <= '0'; seriesonedelff(k) <= '0'; seriestwoff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN -- level 10 seriesoneff <= (mulonedel & zerovec(6 DOWNTO 1)) - (zerovec(8 DOWNTO 1) & squared(36 DOWNTO 13)); seriesonedelff <= seriesoneff; -- level 12 seriestwoff <= seriesonedelff + (zerovec(14 DOWNTO 1) & cubed(36 DOWNTO 19)); END IF; END IF; END PROCESS; numtwo <= '0' & seriestwoff(32 DOWNTO 2); -- exponent for subrange 127-8 = 119 exptwo <= "01110111"; --********************************************************* --* add logarithm values * --********************************************************* zeroone <= lutoneexpff(8) OR lutoneexpff(7) OR lutoneexpff(6) OR lutoneexpff(5) OR lutoneexpff(4) OR lutoneexpff(3) OR lutoneexpff(2) OR lutoneexpff(1); numberone <= zeroone & lutonemanff & lutoneexpff; -- level 3 in, level 4 out delthr: fp_del GENERIC MAP (width=>32,pipes=>1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>numberone,cc=>numberonedel); numone <= '0' & numberonedel(32 DOWNTO 9) & zerovec(7 DOWNTO 1); expone <= numberonedel(8 DOWNTO 1); zeropow <= lutpowexpff(8) OR lutpowexpff(7) OR lutpowexpff(6) OR lutpowexpff(5) OR lutpowexpff(4) OR lutpowexpff(3) OR lutpowexpff(2) OR lutpowexpff(1); numpow <= '0' & zeropow & lutpowmanff & zerovec(7 DOWNTO 1); exppow <= lutpowexpff; gmpz: FOR k IN 1 TO 32 GENERATE numpowsigned(k) <= numpow(k) XOR signff(3); END GENERATE; -- level 4 in, level 8 out addone: fp_lnadd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aaman=>numpowsigned,aaexp=>exppow, bbman=>numone,bbexp=>expone, ccman=>numpowone,ccexp=>exppowone); -- level 8 in, level 12 out delfor: fp_del GENERIC MAP (width=>32,pipes=>4) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>numpowone,cc=>numpowonedel); delfiv: fp_del GENERIC MAP (width=>8,pipes=>4) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>exppowone,cc=>exppowonedel); -- level 12 in, level 16 out addtwo: fp_lnadd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aaman=>numpowonedel,aaexp=>exppowonedel, bbman=>numtwo,bbexp=>exptwo, ccman=>numsum,ccexp=>expsum); gmsa: FOR k IN 1 TO 32 GENERATE numsumabs(k) <= numsum(k) XOR signff(15); END GENERATE; -- level 16 in, level 19 out norm: fp_lnnorm PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inman=>numsumabs,inexp=>expsum, outman=>ccmannode,outexp=>ccexpnode, zero=>zeroout); psgna: PROCESS (sysclk) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 18 LOOP signff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN signff(1) <= aaexppos(9); FOR k IN 2 TO 18 LOOP signff(k) <= signff(k-1); END LOOP; END IF; END PROCESS; ccsgn <= signff(18); ccman <= ccmannode; ccexp <= ccexpnode; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/dp_inv.vhd	10	12634	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* DOUBLE PRECISION INVERSE - TOP LEVEL * --* * --* DP_INV.VHD * --* * --* Function: IEEE754 DP Inverse * --* (multiplicative iterative algorithm) * --* * --* 12/08/09 ML * --* * --* (c) 2009 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --*********************************************** --*********************************************** --* Notes: * --* * --* Stratix II * --* Latency = 20 + 2DoubleSpeed + --* RoundConvert(1+DoubleSpeed) --* DoubleSpeed = 0, Roundconvert = 0 : 20 * --* DoubleSpeed = 1, Roundconvert = 0 : 22 * --* DoubleSpeed = 0, Roundconvert = 1 : 21 * --* DoubleSpeed = 1, Roundconvert = 1 : 24 * --* * --* Stratix III/IV * --* Latency = 19 + DoubleSpeed + * --* Roundconvert(1+DoubleSpeed) --* DoubleSpeed = 0, Roundconvert = 0 : 19 * --* DoubleSpeed = 1, Roundconvert = 0 : 20 * --* DoubleSpeed = 0, Roundconvert = 1 : 20 * --* DoubleSpeed = 1, Roundconvert = 1 : 22 * --* * --************************************************* ENTITY dp_inv IS GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); END dp_inv; ARCHITECTURE rtl OF dp_inv IS constant expwidth : positive := 11; constant manwidth : positive := 52; -- SII Latency = 19 + 2speed -- SIII Latency = 18 + speed constant coredepth : positive := 19+2doublespeed - device(1+doublespeed); type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal signinff : STD_LOGIC; signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal invertnum : STD_LOGIC_VECTOR (54 DOWNTO 1); signal quotient : STD_LOGIC_VECTOR (55 DOWNTO 1); signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1); signal expff : expfftype; -- conditions signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zeromaninff : STD_LOGIC; signal zeroexpinff : STD_LOGIC; signal maxexpinff : STD_LOGIC; signal zeroinff : STD_LOGIC; signal infinityinff : STD_LOGIC; signal naninff : STD_LOGIC; signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1); component dp_inv_core GENERIC ( doublespeed : integer := 0; -- 0/1 doubleaccuracy : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1); quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1) ); end component; component dp_divnornd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1); mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; dividebyzeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component dp_divrnd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1); mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; dividebyzeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component dp_divrndpipe PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1); mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; dividebyzeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; BEGIN gzva: FOR k IN 1 TO manwidth GENERATE zerovec(k) <= '0'; END GENERATE; gxa: FOR k IN 1 TO expwidth-1 GENERATE expoffset(k) <= '1'; END GENERATE; expoffset(expwidth+2 DOWNTO expwidth) <= "000"; pma: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO manwidth LOOP manff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP expinff(k) <= '0'; END LOOP; FOR k IN 1 TO coredepth-1 LOOP signff(k) <= '0'; END LOOP; FOR k IN 1 TO coredepth-1 LOOP FOR j IN 1 TO expwidth+2 LOOP expff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN signinff <= signin; manff <= mantissain; expinff <= exponentin; signff(1) <= signinff; FOR k IN 2 TO coredepth-1 LOOP signff(k) <= signff(k-1); END LOOP; expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff); expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset; FOR k IN 3 TO coredepth-2 LOOP expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1); END LOOP; -- quotient always <1, so decrement exponent expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) - (zerovec(expwidth+1 DOWNTO 1) & '1'); END IF; END IF; END PROCESS; --***************** --* CHECK INPUTS * --**************** zeroman(1) <= manff(1); gca: FOR k IN 2 TO manwidth GENERATE zeroman(k) <= zeroman(k-1) OR manff(k); END GENERATE; zeroexp(1) <= expinff(1); gcb: FOR k IN 2 TO expwidth GENERATE zeroexp(k) <= zeroexp(k-1) OR expinff(k); END GENERATE; maxexp(1) <= expinff(1); gcc: FOR k IN 2 TO expwidth GENERATE maxexp(k) <= maxexp(k-1) AND expinff(k); END GENERATE; pcc: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN zeromaninff <= '0'; zeroexpinff <= '0'; maxexpinff <= '0'; zeroinff <= '0'; infinityinff <= '0'; naninff <= '0'; FOR k IN 1 TO coredepth-3 LOOP dividebyzeroff(k) <= '0'; nanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN zeromaninff <= zeroman(manwidth); zeroexpinff <= zeroexp(expwidth); maxexpinff <= maxexp(expwidth); -- zero when man = 0, exp = 0 -- infinity when man = 0, exp = max -- nan when man != 0, exp = max -- all ffs '1' when condition true zeroinff <= NOT(zeromaninff OR zeroexpinff); infinityinff <= NOT(zeromaninff) AND maxexpinff; naninff <= zeromaninff AND maxexpinff; -- nan output when nan input nanff(1) <= naninff; FOR k IN 2 TO coredepth-3 LOOP nanff(k) <= nanff(k-1); END LOOP; dividebyzeroff(1) <= zeroinff; FOR k IN 2 TO coredepth-3 LOOP dividebyzeroff(k) <= dividebyzeroff(k-1); END LOOP; END IF; END IF; END PROCESS; --*************** --* DIVIDE CORE * --*************** invertnum <= '1' & mantissain & '0'; invcore: dp_inv_core GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy, device=>device,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>invertnum, quotient=>quotient); -- quotient always <1 --******************** --* ROUND AND OUTPUT * --********************** -- in depth coredepth+1 (core + normalff) gra: IF (roundconvert = 0) GENERATE norndout: dp_divnornd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signff(coredepth-1), exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1), mantissadiv=>quotient(53 DOWNTO 1), nanin=>nanff(coredepth-3), dividebyzeroin=>dividebyzeroff(coredepth-3), signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout, nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout); END GENERATE; grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE rndout: dp_divrnd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signff(coredepth-1), exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1), mantissadiv=>quotient(53 DOWNTO 1), nanin=>nanff(coredepth-3), dividebyzeroin=>dividebyzeroff(coredepth-3), signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout, nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout); END GENERATE; grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE rndoutpipe: dp_divrndpipe PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signff(coredepth-1), exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1), mantissadiv=>quotient(53 DOWNTO 1), nanin=>nanff(coredepth-3), dividebyzeroin=>dividebyzeroff(coredepth-3), signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout, nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout); END GENERATE; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/dp_exprnd.vhd	10	6808	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* DP_EXPRND.VHD * --* * --* Function: DP Exponent Output Block - * --* Rounded * --* * --* 18/02/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --*********************************************** ENTITY dp_exprnd IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit nanin : IN STD_LOGIC; rangeerror : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); END dp_exprnd; ARCHITECTURE rtl OF dp_exprnd IS constant expwidth : positive := 11; constant manwidth : positive := 52; type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1); signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal rangeerrorff : STD_LOGIC; signal overflownode, underflownode : STD_LOGIC; signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal manoverflowbitff : STD_LOGIC; signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1); signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal setmanzero, setmanmax : STD_LOGIC; signal setexpzero, setexpmax : STD_LOGIC; BEGIN gzv: FOR k IN 1 TO manwidth-1 GENERATE zerovec(k) <= '0'; END GENERATE; pra: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN nanff <= "00"; rangeerrorff <= '0'; overflowff <= "00"; underflowff <= "00"; manoverflowbitff <= '0'; FOR k IN 1 TO manwidth LOOP roundmantissaff(k) <= '0'; mantissaff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth+2 LOOP exponentoneff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF(enable = '1') THEN nanff(1) <= nanin; nanff(2) <= nanff(1); rangeerrorff <= rangeerror; overflowff(1) <= overflownode; overflowff(2) <= overflowff(1); underflowff(1) <= underflownode; underflowff(2) <= underflowff(1); manoverflowbitff <= manoverflow(manwidth+1); roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1)); -- nan takes precedence (set max) -- nan takes precedence (set max) FOR k IN 1 TO manwidth LOOP mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax; END LOOP; exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax; END LOOP; END IF; END IF; END PROCESS; exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) + (zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff); --***************************** --* PREDICT MANTISSA OVERFLOW * --***************************** manoverflow(1) <= mantissaexp(1); gmoa: FOR k IN 2 TO manwidth+1 GENERATE manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k); END GENERATE; --****************************** --* CHECK GENERATED CONDITIONS * --****************************** -- infinity if exponent == 255 infinitygen(1) <= exponentnode(1); gia: FOR k IN 2 TO expwidth GENERATE infinitygen(k) <= infinitygen(k-1) AND exponentnode(k); END GENERATE; infinitygen(expwidth+1) <= infinitygen(expwidth) OR (exponentnode(expwidth+1) AND NOT(exponentnode(expwidth+2))); -- '1' if infinity -- zero if exponent == 0 zerogen(1) <= exponentnode(1); gza: FOR k IN 2 TO expwidth GENERATE zerogen(k) <= zerogen(k-1) OR exponentnode(k); END GENERATE; zerogen(expwidth+1) <= zerogen(expwidth) AND NOT(exponentnode(expwidth+2)); -- '0' if zero -- trap any other overflow errors -- when sign = 0 and rangeerror = 1, overflow -- when sign = 1 and rangeerror = 1, underflow overflownode <= NOT(signin) AND rangeerror; underflownode <= signin AND rangeerror; -- set mantissa to 0 when infinity or zero condition setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff); -- setmantissa to "11..11" when nan setmanmax <= nanff(1); -- set exponent to 0 when zero condition setexpzero <= zerogen(expwidth+1); -- set exponent to "11..11" when nan, infinity, or divide by 0 setexpmax <= nanff(1) OR infinitygen(expwidth+1) OR rangeerrorff; --*********** --* OUTPUTS * --************* signout <= '0'; mantissaout <= mantissaff; exponentout <= exponenttwoff; ----------------------------------------------- nanout <= nanff(2); overflowout <= overflowff(2); underflowout <= underflowff(2); END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/dp_fxsub.vhd	10	2876	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_FXSUB.VHD * --* * --* Function: Generic Fixed Point Subtractor * --* * --* 31/01/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY dp_fxsub IS GENERIC ( width : positive := 64; pipes : positive := 1; synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END dp_fxsub; ARCHITECTURE rtl OF dp_fxsub IS component dp_subb IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component dp_subs IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gaa: IF (synthesize = 0) GENERATE addone: dp_subb GENERIC MAP (width=>width,pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,bb=>bb,borrowin=>borrowin, cc=>cc); END GENERATE; gab: IF (synthesize = 1) GENERATE addtwo: dp_subs GENERIC MAP (width=>width,pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,bb=>bb,borrowin=>borrowin, cc=>cc); END GENERATE; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_atanpi_s5.vhd	10	525003	----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_atanpi_s5 -- VHDL created on Tue Mar 12 11:23:23 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_atanpi_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_atanpi_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0); signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0); signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0); signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0); signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0); signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0); signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0); signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0); signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0); signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0); signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0); signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0); signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0); signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0); signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0); signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0); signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0); signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0); signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0); signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0); signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0); signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0); signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0); signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0); signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0); signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0); signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0); signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0); signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0); signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0); signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0); signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0); signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0); signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0); signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0); signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0); signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0); signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0); signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0); signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0); signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0); signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0); signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0); signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0); signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0); signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0); signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0); signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0); signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0); signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0); signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0); signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0); signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0); signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0); signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0); signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0); signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0); signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0); signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0); signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic; signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic; signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true; signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic; signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic; signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic; signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic; signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true; signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true; signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true; signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true; signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true; signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic; signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true; signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0); signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0); signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0); signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0); signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0); signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0); signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0); signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0); signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0); signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0); signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0); signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0); signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0); signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0); signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0); signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0); signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0); signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0); signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0); signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0); signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0); signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0); signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0); signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0); signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0); signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0); signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0); signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0); signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0); signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0); signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0); signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0); signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0); signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0); signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0); signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0); signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0); signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0); signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0); signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0); signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0); signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0); signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0); signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0); signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0); signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0); signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0); signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0); signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0); signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0); signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0); signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0); signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0); signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0); signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0); signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0); signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0); signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0); signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0); signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0); signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0); signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0); signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0); signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0); signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0); signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0); signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0); signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0); begin --xIn(GPIN,3)@0 --cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18) cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000"; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001"; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q); ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0"; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0 fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0); fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0); --fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0 fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b; fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0"; --InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0 InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q; InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a; --cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17) cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111"; --expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0 expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0); expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23); --expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0 expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b; expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0"; --exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0 exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q; exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q; exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b; --InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0 InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q; InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a; --singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0 singX_uid17_atanX_uid8_fpArctanPiTest_in <= a; singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31); --signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0 signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b; signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q; signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000) -- every=1, low=0, high=33, step=1, init=1 ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33; ELSE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000"; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q); ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0"; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871) -- every=1, low=0, high=32, step=1, init=1 ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32; ELSE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6)); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q) BEGIN CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0); --cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21) cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111"; --piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45) piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011"; --cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35 cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0); cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2); --fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35 fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b; --cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22) cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110"; --piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46) piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011"; --cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35 cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0); cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0); --fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35 fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b; --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b); --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b; --exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0 exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q; exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q; exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b; --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq, address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa, data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia ); ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0); --constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35 constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q; constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q) BEGIN CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q; WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35 expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0); expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23); --reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35 reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68) cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000"; --reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0 reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1 ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 11 ) PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111"; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q); ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0"; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b; --cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230) cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110"; --expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0 expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q); expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b); expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b)); expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0); --expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0 expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0); expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0); --cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229) cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101"; --expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0 expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q); expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b); expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b)); expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0); --expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0 expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0); expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0 fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b; fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q); fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0"; --expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0 expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q; expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b; WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b; WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0 expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b; expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0"; --udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0 udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q); udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9); --InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0 InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q; InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a; --InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0 InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q; InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a; --exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0 exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q; exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q; exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q; exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c; --xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0 xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q; xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b; xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b; --xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0 xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q; xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q; xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b; --excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0 excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q; --reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0 reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1 outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1 expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q; expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q; WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014) -- every=1, low=0, high=7, step=1, init=1 ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3)); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q; WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 8, width_b => 8, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia ); ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0); --cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19) cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001"; --oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0 oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b; --y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0 y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0); y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0); --yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0 yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b; yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15); --reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0 reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1 memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0'); memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0'); memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q; memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid346_invTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid346_invTabGen_lutmem_iq, address_a => memoryC2_uid346_invTabGen_lutmem_aa, data_a => memoryC2_uid346_invTabGen_lutmem_ia ); memoryC2_uid346_invTabGen_lutmem_reset0 <= areset; memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3 reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011) ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0 ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3 yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0); yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0); --yT1_uid347_invPolyEval(BITSELECT,346)@3 yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b; yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3); --reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3 reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4 prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b); prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0'); prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0'); prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q; prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q; prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7 prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q; prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11); --highBBits_uid350_invPolyEval(BITSELECT,349)@7 highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b; highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1); --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1 ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4 memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0'); memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0'); memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q; memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 20, widthad_a => 8, numwords_a => 256, width_b => 20, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid345_invTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid345_invTabGen_lutmem_iq, address_a => memoryC1_uid345_invTabGen_lutmem_aa, data_a => memoryC1_uid345_invTabGen_lutmem_ia ); memoryC1_uid345_invTabGen_lutmem_reset0 <= areset; memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0); --reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6 reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid351_invPolyEval(ADD,350)@7 sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q); sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b); sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b)); sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0); --lowRangeB_uid349_invPolyEval(BITSELECT,348)@7 lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0); lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0); --s1_uid349_uid352_invPolyEval(BITJOIN,351)@7 s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b; --reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7 reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q; END IF; END IF; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q; END IF; END IF; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962) -- every=1, low=0, high=1, step=1, init=1 ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1)); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q) BEGIN CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q; WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q; WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 1, numwords_a => 2, width_b => 15, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq, address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa, data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia ); ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0); --reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7 reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8 prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b); prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0'); prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0'); prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q; prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q; prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37)); END IF; END IF; END PROCESS; prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11 prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q; prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14); --highBBits_uid356_invPolyEval(BITSELECT,355)@11 highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b; highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2); --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100"; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q); ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0"; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027) -- every=1, low=0, high=4, step=1, init=1 ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4; ELSE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3)); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia ); ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8 memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0'); memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0'); memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q; memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 29, widthad_a => 8, numwords_a => 256, width_b => 29, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid344_invTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid344_invTabGen_lutmem_iq, address_a => memoryC0_uid344_invTabGen_lutmem_aa, data_a => memoryC0_uid344_invTabGen_lutmem_ia ); memoryC0_uid344_invTabGen_lutmem_reset0 <= areset; memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0); --reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10 reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid357_invPolyEval(ADD,356)@11 sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q); sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b); sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b)); sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0); --lowRangeB_uid355_invPolyEval(BITSELECT,354)@11 lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0); lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0); --s2_uid355_uid358_invPolyEval(BITJOIN,357)@11 s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b; --fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11 fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0); fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5); --fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11 fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0); fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0); --ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0 ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 11 ) PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11 fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q; fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b; WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1 reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2 ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 10 ) PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12 fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q; fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q) BEGIN CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q; WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12 R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001"; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q); ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0"; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897) -- every=1, low=0, high=9, step=1, init=1 ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9; ELSE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4)); --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q) BEGIN CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 32, widthad_a => 4, numwords_a => 10, width_b => 32, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0); --path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0 path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q; path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0'; path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0); path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b)); path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10); --reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0 reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n; END IF; END IF; END PROCESS; --ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1 ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 11 ) PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12 u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q; u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q) BEGIN CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q; WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12 fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0); fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0); --ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12 ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13 oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q; --oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13 oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q; --X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13 X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0); X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0); --leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281) leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000"; --leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13 leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13 reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13 X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0); X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0); --leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13 leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; --reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13 reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13 X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0); X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0); --leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275) leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000"; --leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13 leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13 reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13 reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66) zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000"; --shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63) shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010"; --expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12 expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0); expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23); --reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12 reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13 shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q); shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q); shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b)); shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0); --ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13 ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q; ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8); --shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13 shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b; shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q) BEGIN CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q; WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13 fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0); fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0); --leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13 leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b; leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2); --reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13 reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14 leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q; leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q) BEGIN CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q; WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q; WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q; WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14 LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0); LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0); --ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14 ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 34, depth => 1 ) PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292) leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000"; --leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15 leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14 LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0); LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0); --ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14 ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 35, depth => 1 ) PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289) leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00"; --leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15 leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14 LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0); LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0); --ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14 ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 36, depth => 1 ) PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15 leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q; --reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14 reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13 leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0); leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0); --ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13 ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14 reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15 leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q; leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q) BEGIN CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15 y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0); y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1); --yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15 yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b; yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27); --reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15 reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16 memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0'); memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0'); memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q; memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 8, numwords_a => 256, width_b => 13, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq, address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa, data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia ); memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset; memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0); --reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18 reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q; END IF; END IF; END PROCESS; --yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15 yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0); yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9); --yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15 yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b; yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5); --ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062) ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 13, depth => 1 ) PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15 ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay GENERIC MAP ( width => 13, depth => 2 ) PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18 reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q; END IF; END IF; END PROCESS; --prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19 prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b); prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0'); prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0'); prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q; prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q; prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22 prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q; prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12); --highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22 highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b; highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15 ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18 reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19 memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0'); memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0'); memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q; memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq, address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa, data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia ); memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset; memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0); --reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21 reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22 sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q); sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b); sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b)); sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0); --lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22 lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0); lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0); --s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22 s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b; --reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22 reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b; --reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15 reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 3, numwords_a => 5, width_b => 18, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq, address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa, data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia ); ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0); --prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23 prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b); prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0'); prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0'); prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q; prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q; prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41)); END IF; END IF; END PROCESS; prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26 prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q; prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17); --highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26 highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b; highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b; --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq, address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa, data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia ); ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22 reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23 memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0'); memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0'); memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q; memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 31, widthad_a => 8, numwords_a => 256, width_b => 31, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq, address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa, data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia ); memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset; memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0); --reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25 reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26 sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q); sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b); sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b)); sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0); --lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26 lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0); lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0); --s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26 s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b; --fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26 fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0); fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5); --reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26 reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010"; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q); ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0"; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13 reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910) -- every=1, low=0, high=10, step=1, init=1 ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10; ELSE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4)); --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q) BEGIN CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 4, numwords_a => 11, width_b => 24, widthad_b => 4, numwords_b => 11, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0); --mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27 mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b); mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0'); mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0'); mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q; mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q; mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr); END IF; END IF; END PROCESS; mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1; END IF; END IF; END PROCESS; --normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30 normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0); normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49); --InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30 InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b; InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111"; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q); ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0"; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923) -- every=1, low=0, high=15, step=1, init=1 ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4)); --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 16, width_b => 8, widthad_b => 4, numwords_b => 16, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0); --expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30 expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q); expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q); expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b)); expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0); --fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30 fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0); fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25); --fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30 fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0); fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24); --fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30 fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b; fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b) BEGIN CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b; WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b; WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30 expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q; --reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30 reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31 expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q); expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q); expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b)); expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0); --expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31 expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0); expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24); --reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31 reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971) ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32 ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33 RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1); --rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33 rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333) rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000"; --rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322) rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000"; --X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32 X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24); --rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32 rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319) rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000"; --X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32 X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16); --rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32 rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32 X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8); --rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32 rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30 ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 24, depth => 2 ) PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32 oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q; --cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24) cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001"; --reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30 reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31 shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q); shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q); shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b)); shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0); --shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31 shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0); shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0); --cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23) cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000"; --shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13 shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q; shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0'; shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0); shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b)); shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10); --ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13 ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 18 ) PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31 sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q; sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q) BEGIN CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b; WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31 sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0); sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31 rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b; rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3); --reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31 reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32 rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q; rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q) BEGIN CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32 RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6); --ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32 ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 19, depth => 1 ) PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33 rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q; --RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32 RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4); --ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32 ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 21, depth => 1 ) PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33 rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q; --RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32 RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2); --ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32 ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33 rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q; --reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32 reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31 rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1); --ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31 ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32 reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q; END IF; END IF; END PROCESS; --rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33 rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q; rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q) BEGIN CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31 rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31 reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32 ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33 rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q; rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q) BEGIN CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33 pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q; --reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33 reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34 path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q); path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q); path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b)); path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0); --normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34 normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0); normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25); --expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34 expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b; expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q) BEGIN CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q; WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34 path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0); path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1); --path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34 path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0); path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0); --fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34 fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b; fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b) BEGIN CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b; WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b; WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34 expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q; --reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34 reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35 expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q); expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q); expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b)); expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0); --expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35 expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0); expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24); --reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35 reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b); --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b; --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 33, width_b => 8, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq, address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa, data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia ); ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0); --reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35 reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010"; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q); ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0"; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0 expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b; expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q; expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0"; --inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0 inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q; inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q; inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b; --arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0 arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q; arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q; arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1 ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61) biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011"; --atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13 atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q; atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0'; atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0); atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b)); atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10); --ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0 ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13 pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q; --reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13 reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936) -- every=1, low=0, high=18, step=1, init=1 ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18; ELSE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5)); --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q) BEGIN CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 5, numwords_a => 19, width_b => 3, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0); --fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35 fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10"; WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00"; WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN OTHERS => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36 expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q; expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q) BEGIN CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q; WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q; WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q; WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20) cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000"; --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0); --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0); --excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35 excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q; --reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35 reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36 outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36 expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q; expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) BEGIN CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q; WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35 fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0); fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0); --reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35 reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b; --fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31 fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0); fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1); --reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31 reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 1, numwords_a => 2, width_b => 23, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0, clock1 => clk, address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq, address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa, data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia ); ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0); --fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35 fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0); fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1); --reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35 reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0 reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 6, numwords_a => 33, width_b => 23, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0); --fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36 fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q; fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q) BEGIN CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q; WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q; WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q; WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q; WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36 fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q; fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q) BEGIN CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q; WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36 R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q; --fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36 fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0); fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0); --reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36 reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37 fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q; fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0"; --expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36 expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0); expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23); --reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36 reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37 expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q; expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0"; --exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37 exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q; exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q; exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b; --cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5) cstBiasM2_uid6_fpArctanPiTest_q <= "01111101"; --ooPi_uid9_fpArctanPiTest(CONSTANT,8) ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011"; --fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36 fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0); fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0); --fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36 fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b; --expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36 expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0); expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23); --expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36 expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b; expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0"; --ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36 ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37 excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b; --fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36 fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0); fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0); --fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36 fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b; fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0"; --ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36 ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36 expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b; expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0"; --ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36 ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37 exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q; exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q; exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b; --expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37 expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q; expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0"; --excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37 excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b; --ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37 ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q; ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q; ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b; --InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36 InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q; InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a; --exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36 exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b; --ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36 ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37 InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q; InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a; --exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37 exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b; --excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37 excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q; excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q; excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q; excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c; --VCC(CONSTANT,1) VCC_q <= "1"; --InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37 InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q; InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a; END IF; END PROCESS; --signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36 signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q; signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31); --signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36 signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q; signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31); --signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36 signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b; signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b; signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37 ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38 signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q; signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q; signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b; --ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38 ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36 add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b; --reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36 reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36 add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b; --reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36 reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37 prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b); prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0'); prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0'); prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q; prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q; prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr); END IF; END IF; END PROCESS; prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40 normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q; normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47); --roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179) roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010"; --fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40 fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0); fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23); --fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40 fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0); fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22); --fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40 fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b; fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b) BEGIN CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b; WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b; WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40 FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0); FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0); --Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40 Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0); Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22); --extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40 extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b; extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b) BEGIN CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b; WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40 stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0); stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0); --stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40 stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b; --stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40 stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q; stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0"; --sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40 sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q; sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a; --lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40 lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q; --roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40 roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q; roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q; roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0"; --roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40 roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q; roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a; --roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40 roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q; --reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40 reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162) biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111"; --ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36 ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37 expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q); expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q); expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b)); END IF; END IF; END PROCESS; expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0); --ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38 ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39 expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q); expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q); expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0); --expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40 expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q; --reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40 reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41 expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q); expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q); expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b)); expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0); --expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41 expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q; expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24); --expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41 expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0); expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0); --ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41 ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay GENERIC MAP ( width => 8, depth => 2 ) PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37 ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41 reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42 expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q; expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0'; expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0); expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b)); expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14); --InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37 InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q; InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a; --InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37 InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a; --InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37 InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a; --exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37 exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c; --ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37 ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37 InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q; InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a; --InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37 InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a; --InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37 InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a; --exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37 exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c; --ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37 ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42 ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q; ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q; ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n; ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c; --excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37 excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q; excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b; --ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37 ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37 excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q; excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37 ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37 excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37 ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42 excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d; --expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42 expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q; expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0); expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b)); expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14); --excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42 excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q; excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q; excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n; excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c; --excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37 excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q; excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b; --ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37 ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37 excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37 ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37 excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37 ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42 excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d; --concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42 concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q; --reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42 reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43 excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01"; WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10"; WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11"; WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN OTHERS => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43 expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q; expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) BEGIN CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q; WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41 fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0); fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1); --ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41 ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43 fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q; fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q) BEGIN CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q; WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43 R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q; --xOut(GPOUT,4)@43 q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q; end normal;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/dp_explut10.vhd	10	174445	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* DP_EXPLUT10.VHD * --* * --* Function: Look Up Table - EXP() * --* * --* Generated by MATLAB Utility * --* * --* 18/02/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY dp_explut10 IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC ); END dp_explut10; ARCHITECTURE rtl OF dp_explut10 IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= '0'; WHEN "0000000001" => manhi <= conv_std_logic_vector(16392,24); manlo <= conv_std_logic_vector(699221,28); exponent <= '0'; WHEN "0000000010" => manhi <= conv_std_logic_vector(32800,24); manlo <= conv_std_logic_vector(5595137,28); exponent <= '0'; WHEN "0000000011" => manhi <= conv_std_logic_vector(49224,24); manlo <= conv_std_logic_vector(18888200,28); exponent <= '0'; WHEN "0000000100" => manhi <= conv_std_logic_vector(65664,24); manlo <= conv_std_logic_vector(44782967,28); exponent <= '0'; WHEN "0000000101" => manhi <= conv_std_logic_vector(82120,24); manlo <= conv_std_logic_vector(87488104,28); exponent <= '0'; WHEN "0000000110" => manhi <= conv_std_logic_vector(98592,24); manlo <= conv_std_logic_vector(151216387,28); exponent <= '0'; WHEN "0000000111" => manhi <= conv_std_logic_vector(115080,24); manlo <= conv_std_logic_vector(240184710,28); exponent <= '0'; WHEN "0000001000" => manhi <= conv_std_logic_vector(131585,24); manlo <= conv_std_logic_vector(90178630,28); exponent <= '0'; WHEN "0000001001" => manhi <= conv_std_logic_vector(148105,24); manlo <= conv_std_logic_vector(242294195,28); exponent <= '0'; WHEN "0000001010" => manhi <= conv_std_logic_vector(164642,24); manlo <= conv_std_logic_vector(163889760,28); exponent <= '0'; WHEN "0000001011" => manhi <= conv_std_logic_vector(181195,24); manlo <= conv_std_logic_vector(127634178,28); exponent <= '0'; WHEN "0000001100" => manhi <= conv_std_logic_vector(197764,24); manlo <= conv_std_logic_vector(137764983,28); exponent <= '0'; WHEN "0000001101" => manhi <= conv_std_logic_vector(214349,24); manlo <= conv_std_logic_vector(198523848,28); exponent <= '0'; WHEN "0000001110" => manhi <= conv_std_logic_vector(230951,24); manlo <= conv_std_logic_vector(45721136,28); exponent <= '0'; WHEN "0000001111" => manhi <= conv_std_logic_vector(247568,24); manlo <= conv_std_logic_vector(220477726,28); exponent <= '0'; WHEN "0000010000" => manhi <= conv_std_logic_vector(264202,24); manlo <= conv_std_logic_vector(190176825,28); exponent <= '0'; WHEN "0000010001" => manhi <= conv_std_logic_vector(280852,24); manlo <= conv_std_logic_vector(227512164,28); exponent <= '0'; WHEN "0000010010" => manhi <= conv_std_logic_vector(297519,24); manlo <= conv_std_logic_vector(68310723,28); exponent <= '0'; WHEN "0000010011" => manhi <= conv_std_logic_vector(314201,24); manlo <= conv_std_logic_vector(253710014,28); exponent <= '0'; WHEN "0000010100" => manhi <= conv_std_logic_vector(330900,24); manlo <= conv_std_logic_vector(251109895,28); exponent <= '0'; WHEN "0000010101" => manhi <= conv_std_logic_vector(347616,24); manlo <= conv_std_logic_vector(64785307,28); exponent <= '0'; WHEN "0000010110" => manhi <= conv_std_logic_vector(364347,24); manlo <= conv_std_logic_vector(235886282,28); exponent <= '0'; WHEN "0000010111" => manhi <= conv_std_logic_vector(381095,24); manlo <= conv_std_logic_vector(231825206,28); exponent <= '0'; WHEN "0000011000" => manhi <= conv_std_logic_vector(397860,24); manlo <= conv_std_logic_vector(56889565,28); exponent <= '0'; WHEN "0000011001" => manhi <= conv_std_logic_vector(414640,24); manlo <= conv_std_logic_vector(252241943,28); exponent <= '0'; WHEN "0000011010" => manhi <= conv_std_logic_vector(431438,24); manlo <= conv_std_logic_vector(16871840,28); exponent <= '0'; WHEN "0000011011" => manhi <= conv_std_logic_vector(448251,24); manlo <= conv_std_logic_vector(160385687,28); exponent <= '0'; WHEN "0000011100" => manhi <= conv_std_logic_vector(465081,24); manlo <= conv_std_logic_vector(150216837,28); exponent <= '0'; WHEN "0000011101" => manhi <= conv_std_logic_vector(481927,24); manlo <= conv_std_logic_vector(259109217,28); exponent <= '0'; WHEN "0000011110" => manhi <= conv_std_logic_vector(498790,24); manlo <= conv_std_logic_vector(222940052,28); exponent <= '0'; WHEN "0000011111" => manhi <= conv_std_logic_vector(515670,24); manlo <= conv_std_logic_vector(46026234,28); exponent <= '0'; WHEN "0000100000" => manhi <= conv_std_logic_vector(532566,24); manlo <= conv_std_logic_vector(1124333,28); exponent <= '0'; WHEN "0000100001" => manhi <= conv_std_logic_vector(549478,24); manlo <= conv_std_logic_vector(92559680,28); exponent <= '0'; WHEN "0000100010" => manhi <= conv_std_logic_vector(566407,24); manlo <= conv_std_logic_vector(56226380,28); exponent <= '0'; WHEN "0000100011" => manhi <= conv_std_logic_vector(583352,24); manlo <= conv_std_logic_vector(164893679,28); exponent <= '0'; WHEN "0000100100" => manhi <= conv_std_logic_vector(600314,24); manlo <= conv_std_logic_vector(154464145,28); exponent <= '0'; WHEN "0000100101" => manhi <= conv_std_logic_vector(617293,24); manlo <= conv_std_logic_vector(29280039,28); exponent <= '0'; WHEN "0000100110" => manhi <= conv_std_logic_vector(634288,24); manlo <= conv_std_logic_vector(62123323,28); exponent <= '0'; WHEN "0000100111" => manhi <= conv_std_logic_vector(651299,24); manlo <= conv_std_logic_vector(257344748,28); exponent <= '0'; WHEN "0000101000" => manhi <= conv_std_logic_vector(668328,24); manlo <= conv_std_logic_vector(82428406,28); exponent <= '0'; WHEN "0000101001" => manhi <= conv_std_logic_vector(685373,24); manlo <= conv_std_logic_vector(78604464,28); exponent <= '0'; WHEN "0000101010" => manhi <= conv_std_logic_vector(702434,24); manlo <= conv_std_logic_vector(250236442,28); exponent <= '0'; WHEN "0000101011" => manhi <= conv_std_logic_vector(719513,24); manlo <= conv_std_logic_vector(64821205,28); exponent <= '0'; WHEN "0000101100" => manhi <= conv_std_logic_vector(736608,24); manlo <= conv_std_logic_vector(63601714,28); exponent <= '0'; WHEN "0000101101" => manhi <= conv_std_logic_vector(753719,24); manlo <= conv_std_logic_vector(250954289,28); exponent <= '0'; WHEN "0000101110" => manhi <= conv_std_logic_vector(770848,24); manlo <= conv_std_logic_vector(94388611,28); exponent <= '0'; WHEN "0000101111" => manhi <= conv_std_logic_vector(787993,24); manlo <= conv_std_logic_vector(135160468,28); exponent <= '0'; WHEN "0000110000" => manhi <= conv_std_logic_vector(805155,24); manlo <= conv_std_logic_vector(109223564,28); exponent <= '0'; WHEN "0000110001" => manhi <= conv_std_logic_vector(822334,24); manlo <= conv_std_logic_vector(20971345,28); exponent <= '0'; WHEN "0000110010" => manhi <= conv_std_logic_vector(839529,24); manlo <= conv_std_logic_vector(143237009,28); exponent <= '0'; WHEN "0000110011" => manhi <= conv_std_logic_vector(856741,24); manlo <= conv_std_logic_vector(211987135,28); exponent <= '0'; WHEN "0000110100" => manhi <= conv_std_logic_vector(873970,24); manlo <= conv_std_logic_vector(231628063,28); exponent <= '0'; WHEN "0000110101" => manhi <= conv_std_logic_vector(891216,24); manlo <= conv_std_logic_vector(206570434,28); exponent <= '0'; WHEN "0000110110" => manhi <= conv_std_logic_vector(908479,24); manlo <= conv_std_logic_vector(141229202,28); exponent <= '0'; WHEN "0000110111" => manhi <= conv_std_logic_vector(925759,24); manlo <= conv_std_logic_vector(40023632,28); exponent <= '0'; WHEN "0000111000" => manhi <= conv_std_logic_vector(943055,24); manlo <= conv_std_logic_vector(175812765,28); exponent <= '0'; WHEN "0000111001" => manhi <= conv_std_logic_vector(960369,24); manlo <= conv_std_logic_vector(16153594,28); exponent <= '0'; WHEN "0000111010" => manhi <= conv_std_logic_vector(977699,24); manlo <= conv_std_logic_vector(102349263,28); exponent <= '0'; WHEN "0000111011" => manhi <= conv_std_logic_vector(995046,24); manlo <= conv_std_logic_vector(170400879,28); exponent <= '0'; WHEN "0000111100" => manhi <= conv_std_logic_vector(1012410,24); manlo <= conv_std_logic_vector(224749339,28); exponent <= '0'; WHEN "0000111101" => manhi <= conv_std_logic_vector(1029792,24); manlo <= conv_std_logic_vector(1404424,28); exponent <= '0'; WHEN "0000111110" => manhi <= conv_std_logic_vector(1047190,24); manlo <= conv_std_logic_vector(41686624,28); exponent <= '0'; WHEN "0000111111" => manhi <= conv_std_logic_vector(1064605,24); manlo <= conv_std_logic_vector(81614410,28); exponent <= '0'; WHEN "0001000000" => manhi <= conv_std_logic_vector(1082037,24); manlo <= conv_std_logic_vector(125646062,28); exponent <= '0'; WHEN "0001000001" => manhi <= conv_std_logic_vector(1099486,24); manlo <= conv_std_logic_vector(178244212,28); exponent <= '0'; WHEN "0001000010" => manhi <= conv_std_logic_vector(1116952,24); manlo <= conv_std_logic_vector(243875856,28); exponent <= '0'; WHEN "0001000011" => manhi <= conv_std_logic_vector(1134436,24); manlo <= conv_std_logic_vector(58576897,28); exponent <= '0'; WHEN "0001000100" => manhi <= conv_std_logic_vector(1151936,24); manlo <= conv_std_logic_vector(163693974,28); exponent <= '0'; WHEN "0001000101" => manhi <= conv_std_logic_vector(1169454,24); manlo <= conv_std_logic_vector(26836276,28); exponent <= '0'; WHEN "0001000110" => manhi <= conv_std_logic_vector(1186988,24); manlo <= conv_std_logic_vector(189359192,28); exponent <= '0'; WHEN "0001000111" => manhi <= conv_std_logic_vector(1204540,24); manlo <= conv_std_logic_vector(118880671,28); exponent <= '0'; WHEN "0001001000" => manhi <= conv_std_logic_vector(1222109,24); manlo <= conv_std_logic_vector(88329413,28); exponent <= '0'; WHEN "0001001001" => manhi <= conv_std_logic_vector(1239695,24); manlo <= conv_std_logic_vector(102203053,28); exponent <= '0'; WHEN "0001001010" => manhi <= conv_std_logic_vector(1257298,24); manlo <= conv_std_logic_vector(165003622,28); exponent <= '0'; WHEN "0001001011" => manhi <= conv_std_logic_vector(1274919,24); manlo <= conv_std_logic_vector(12802090,28); exponent <= '0'; WHEN "0001001100" => manhi <= conv_std_logic_vector(1292556,24); manlo <= conv_std_logic_vector(186980202,28); exponent <= '0'; WHEN "0001001101" => manhi <= conv_std_logic_vector(1310211,24); manlo <= conv_std_logic_vector(155182284,28); exponent <= '0'; WHEN "0001001110" => manhi <= conv_std_logic_vector(1327883,24); manlo <= conv_std_logic_vector(190363442,28); exponent <= '0'; WHEN "0001001111" => manhi <= conv_std_logic_vector(1345573,24); manlo <= conv_std_logic_vector(28612286,28); exponent <= '0'; WHEN "0001010000" => manhi <= conv_std_logic_vector(1363279,24); manlo <= conv_std_logic_vector(211328214,28); exponent <= '0'; WHEN "0001010001" => manhi <= conv_std_logic_vector(1381003,24); manlo <= conv_std_logic_vector(206173225,28); exponent <= '0'; WHEN "0001010010" => manhi <= conv_std_logic_vector(1398745,24); manlo <= conv_std_logic_vector(17684657,28); exponent <= '0'; WHEN "0001010011" => manhi <= conv_std_logic_vector(1416503,24); manlo <= conv_std_logic_vector(187275197,28); exponent <= '0'; WHEN "0001010100" => manhi <= conv_std_logic_vector(1434279,24); manlo <= conv_std_logic_vector(182620141,28); exponent <= '0'; WHEN "0001010101" => manhi <= conv_std_logic_vector(1452073,24); manlo <= conv_std_logic_vector(8270141,28); exponent <= '0'; WHEN "0001010110" => manhi <= conv_std_logic_vector(1469883,24); manlo <= conv_std_logic_vector(205651209,28); exponent <= '0'; WHEN "0001010111" => manhi <= conv_std_logic_vector(1487711,24); manlo <= conv_std_logic_vector(242451980,28); exponent <= '0'; WHEN "0001011000" => manhi <= conv_std_logic_vector(1505557,24); manlo <= conv_std_logic_vector(123236457,28); exponent <= '0'; WHEN "0001011001" => manhi <= conv_std_logic_vector(1523420,24); manlo <= conv_std_logic_vector(121008560,28); exponent <= '0'; WHEN "0001011010" => manhi <= conv_std_logic_vector(1541300,24); manlo <= conv_std_logic_vector(240341215,28); exponent <= '0'; WHEN "0001011011" => manhi <= conv_std_logic_vector(1559198,24); manlo <= conv_std_logic_vector(217376360,28); exponent <= '0'; WHEN "0001011100" => manhi <= conv_std_logic_vector(1577114,24); manlo <= conv_std_logic_vector(56695861,28); exponent <= '0'; WHEN "0001011101" => manhi <= conv_std_logic_vector(1595047,24); manlo <= conv_std_logic_vector(31321518,28); exponent <= '0'; WHEN "0001011110" => manhi <= conv_std_logic_vector(1612997,24); manlo <= conv_std_logic_vector(145844154,28); exponent <= '0'; WHEN "0001011111" => manhi <= conv_std_logic_vector(1630965,24); manlo <= conv_std_logic_vector(136423623,28); exponent <= '0'; WHEN "0001100000" => manhi <= conv_std_logic_vector(1648951,24); manlo <= conv_std_logic_vector(7659725,28); exponent <= '0'; WHEN "0001100001" => manhi <= conv_std_logic_vector(1666954,24); manlo <= conv_std_logic_vector(32592210,28); exponent <= '0'; WHEN "0001100010" => manhi <= conv_std_logic_vector(1684974,24); manlo <= conv_std_logic_vector(215829868,28); exponent <= '0'; WHEN "0001100011" => manhi <= conv_std_logic_vector(1703013,24); manlo <= conv_std_logic_vector(25115084,28); exponent <= '0'; WHEN "0001100100" => manhi <= conv_std_logic_vector(1721069,24); manlo <= conv_std_logic_vector(1936572,28); exponent <= '0'; WHEN "0001100101" => manhi <= conv_std_logic_vector(1739142,24); manlo <= conv_std_logic_vector(150916647,28); exponent <= '0'; WHEN "0001100110" => manhi <= conv_std_logic_vector(1757233,24); manlo <= conv_std_logic_vector(208246681,28); exponent <= '0'; WHEN "0001100111" => manhi <= conv_std_logic_vector(1775342,24); manlo <= conv_std_logic_vector(178558028,28); exponent <= '0'; WHEN "0001101000" => manhi <= conv_std_logic_vector(1793469,24); manlo <= conv_std_logic_vector(66486562,28); exponent <= '0'; WHEN "0001101001" => manhi <= conv_std_logic_vector(1811613,24); manlo <= conv_std_logic_vector(145108146,28); exponent <= '0'; WHEN "0001101010" => manhi <= conv_std_logic_vector(1829775,24); manlo <= conv_std_logic_vector(150632262,28); exponent <= '0'; WHEN "0001101011" => manhi <= conv_std_logic_vector(1847955,24); manlo <= conv_std_logic_vector(87708388,28); exponent <= '0'; WHEN "0001101100" => manhi <= conv_std_logic_vector(1866152,24); manlo <= conv_std_logic_vector(229426001,28); exponent <= '0'; WHEN "0001101101" => manhi <= conv_std_logic_vector(1884368,24); manlo <= conv_std_logic_vector(43572756,28); exponent <= '0'; WHEN "0001101110" => manhi <= conv_std_logic_vector(1902601,24); manlo <= conv_std_logic_vector(71682684,28); exponent <= '0'; WHEN "0001101111" => manhi <= conv_std_logic_vector(1920852,24); manlo <= conv_std_logic_vector(49988005,28); exponent <= '0'; WHEN "0001110000" => manhi <= conv_std_logic_vector(1939120,24); manlo <= conv_std_logic_vector(251596409,28); exponent <= '0'; WHEN "0001110001" => manhi <= conv_std_logic_vector(1957407,24); manlo <= conv_std_logic_vector(144313787,28); exponent <= '0'; WHEN "0001110010" => manhi <= conv_std_logic_vector(1975712,24); manlo <= conv_std_logic_vector(1256963,28); exponent <= '0'; WHEN "0001110011" => manhi <= conv_std_logic_vector(1994034,24); manlo <= conv_std_logic_vector(95547338,28); exponent <= '0'; WHEN "0001110100" => manhi <= conv_std_logic_vector(2012374,24); manlo <= conv_std_logic_vector(163439978,28); exponent <= '0'; WHEN "0001110101" => manhi <= conv_std_logic_vector(2030732,24); manlo <= conv_std_logic_vector(209629988,28); exponent <= '0'; WHEN "0001110110" => manhi <= conv_std_logic_vector(2049108,24); manlo <= conv_std_logic_vector(238817060,28); exponent <= '0'; WHEN "0001110111" => manhi <= conv_std_logic_vector(2067502,24); manlo <= conv_std_logic_vector(255705480,28); exponent <= '0'; WHEN "0001111000" => manhi <= conv_std_logic_vector(2085914,24); manlo <= conv_std_logic_vector(265004126,28); exponent <= '0'; WHEN "0001111001" => manhi <= conv_std_logic_vector(2104345,24); manlo <= conv_std_logic_vector(2991026,28); exponent <= '0'; WHEN "0001111010" => manhi <= conv_std_logic_vector(2122793,24); manlo <= conv_std_logic_vector(11255176,28); exponent <= '0'; WHEN "0001111011" => manhi <= conv_std_logic_vector(2141259,24); manlo <= conv_std_logic_vector(26083817,28); exponent <= '0'; WHEN "0001111100" => manhi <= conv_std_logic_vector(2159743,24); manlo <= conv_std_logic_vector(52204260,28); exponent <= '0'; WHEN "0001111101" => manhi <= conv_std_logic_vector(2178245,24); manlo <= conv_std_logic_vector(94348435,28); exponent <= '0'; WHEN "0001111110" => manhi <= conv_std_logic_vector(2196765,24); manlo <= conv_std_logic_vector(157252892,28); exponent <= '0'; WHEN "0001111111" => manhi <= conv_std_logic_vector(2215303,24); manlo <= conv_std_logic_vector(245658814,28); exponent <= '0'; WHEN "0010000000" => manhi <= conv_std_logic_vector(2233860,24); manlo <= conv_std_logic_vector(95876557,28); exponent <= '0'; WHEN "0010000001" => manhi <= conv_std_logic_vector(2252434,24); manlo <= conv_std_logic_vector(249527482,28); exponent <= '0'; WHEN "0010000010" => manhi <= conv_std_logic_vector(2271027,24); manlo <= conv_std_logic_vector(174495768,28); exponent <= '0'; WHEN "0010000011" => manhi <= conv_std_logic_vector(2289638,24); manlo <= conv_std_logic_vector(143976608,28); exponent <= '0'; WHEN "0010000100" => manhi <= conv_std_logic_vector(2308267,24); manlo <= conv_std_logic_vector(162734389,28); exponent <= '0'; WHEN "0010000101" => manhi <= conv_std_logic_vector(2326914,24); manlo <= conv_std_logic_vector(235538153,28); exponent <= '0'; WHEN "0010000110" => manhi <= conv_std_logic_vector(2345580,24); manlo <= conv_std_logic_vector(98726147,28); exponent <= '0'; WHEN "0010000111" => manhi <= conv_std_logic_vector(2364264,24); manlo <= conv_std_logic_vector(25512192,28); exponent <= '0'; WHEN "0010001000" => manhi <= conv_std_logic_vector(2382966,24); manlo <= conv_std_logic_vector(20679323,28); exponent <= '0'; WHEN "0010001001" => manhi <= conv_std_logic_vector(2401686,24); manlo <= conv_std_logic_vector(89015247,28); exponent <= '0'; WHEN "0010001010" => manhi <= conv_std_logic_vector(2420424,24); manlo <= conv_std_logic_vector(235312351,28); exponent <= '0'; WHEN "0010001011" => manhi <= conv_std_logic_vector(2439181,24); manlo <= conv_std_logic_vector(195932245,28); exponent <= '0'; WHEN "0010001100" => manhi <= conv_std_logic_vector(2457956,24); manlo <= conv_std_logic_vector(244112142,28); exponent <= '0'; WHEN "0010001101" => manhi <= conv_std_logic_vector(2476750,24); manlo <= conv_std_logic_vector(116223030,28); exponent <= '0'; WHEN "0010001110" => manhi <= conv_std_logic_vector(2495562,24); manlo <= conv_std_logic_vector(85511509,28); exponent <= '0'; WHEN "0010001111" => manhi <= conv_std_logic_vector(2514392,24); manlo <= conv_std_logic_vector(156793422,28); exponent <= '0'; WHEN "0010010000" => manhi <= conv_std_logic_vector(2533241,24); manlo <= conv_std_logic_vector(66453860,28); exponent <= '0'; WHEN "0010010001" => manhi <= conv_std_logic_vector(2552108,24); manlo <= conv_std_logic_vector(87753539,28); exponent <= '0'; WHEN "0010010010" => manhi <= conv_std_logic_vector(2570993,24); manlo <= conv_std_logic_vector(225522431,28); exponent <= '0'; WHEN "0010010011" => manhi <= conv_std_logic_vector(2589897,24); manlo <= conv_std_logic_vector(216159772,28); exponent <= '0'; WHEN "0010010100" => manhi <= conv_std_logic_vector(2608820,24); manlo <= conv_std_logic_vector(64504976,28); exponent <= '0'; WHEN "0010010101" => manhi <= conv_std_logic_vector(2627761,24); manlo <= conv_std_logic_vector(43837645,28); exponent <= '0'; WHEN "0010010110" => manhi <= conv_std_logic_vector(2646720,24); manlo <= conv_std_logic_vector(159006654,28); exponent <= '0'; WHEN "0010010111" => manhi <= conv_std_logic_vector(2665698,24); manlo <= conv_std_logic_vector(146430162,28); exponent <= '0'; WHEN "0010011000" => manhi <= conv_std_logic_vector(2684695,24); manlo <= conv_std_logic_vector(10966526,28); exponent <= '0'; WHEN "0010011001" => manhi <= conv_std_logic_vector(2703710,24); manlo <= conv_std_logic_vector(25914303,28); exponent <= '0'; WHEN "0010011010" => manhi <= conv_std_logic_vector(2722743,24); manlo <= conv_std_logic_vector(196141350,28); exponent <= '0'; WHEN "0010011011" => manhi <= conv_std_logic_vector(2741795,24); manlo <= conv_std_logic_vector(258084820,28); exponent <= '0'; WHEN "0010011100" => manhi <= conv_std_logic_vector(2760866,24); manlo <= conv_std_logic_vector(216622086,28); exponent <= '0'; WHEN "0010011101" => manhi <= conv_std_logic_vector(2779956,24); manlo <= conv_std_logic_vector(76635284,28); exponent <= '0'; WHEN "0010011110" => manhi <= conv_std_logic_vector(2799064,24); manlo <= conv_std_logic_vector(111446777,28); exponent <= '0'; WHEN "0010011111" => manhi <= conv_std_logic_vector(2818191,24); manlo <= conv_std_logic_vector(57512790,28); exponent <= '0'; WHEN "0010100000" => manhi <= conv_std_logic_vector(2837336,24); manlo <= conv_std_logic_vector(188165241,28); exponent <= '0'; WHEN "0010100001" => manhi <= conv_std_logic_vector(2856500,24); manlo <= conv_std_logic_vector(239869919,28); exponent <= '0'; WHEN "0010100010" => manhi <= conv_std_logic_vector(2875683,24); manlo <= conv_std_logic_vector(217532856,28); exponent <= '0'; WHEN "0010100011" => manhi <= conv_std_logic_vector(2894885,24); manlo <= conv_std_logic_vector(126064881,28); exponent <= '0'; WHEN "0010100100" => manhi <= conv_std_logic_vector(2914105,24); manlo <= conv_std_logic_vector(238817075,28); exponent <= '0'; WHEN "0010100101" => manhi <= conv_std_logic_vector(2933345,24); manlo <= conv_std_logic_vector(23838952,28); exponent <= '0'; WHEN "0010100110" => manhi <= conv_std_logic_vector(2952603,24); manlo <= conv_std_logic_vector(22926662,28); exponent <= '0'; WHEN "0010100111" => manhi <= conv_std_logic_vector(2971879,24); manlo <= conv_std_logic_vector(241010251,28); exponent <= '0'; WHEN "0010101000" => manhi <= conv_std_logic_vector(2991175,24); manlo <= conv_std_logic_vector(146153671,28); exponent <= '0'; WHEN "0010101001" => manhi <= conv_std_logic_vector(3010490,24); manlo <= conv_std_logic_vector(11732065,28); exponent <= '0'; WHEN "0010101010" => manhi <= conv_std_logic_vector(3029823,24); manlo <= conv_std_logic_vector(111125401,28); exponent <= '0'; WHEN "0010101011" => manhi <= conv_std_logic_vector(3049175,24); manlo <= conv_std_logic_vector(180847566,28); exponent <= '0'; WHEN "0010101100" => manhi <= conv_std_logic_vector(3068546,24); manlo <= conv_std_logic_vector(225852738,28); exponent <= '0'; WHEN "0010101101" => manhi <= conv_std_logic_vector(3087936,24); manlo <= conv_std_logic_vector(251099938,28); exponent <= '0'; WHEN "0010101110" => manhi <= conv_std_logic_vector(3107345,24); manlo <= conv_std_logic_vector(261553029,28); exponent <= '0'; WHEN "0010101111" => manhi <= conv_std_logic_vector(3126773,24); manlo <= conv_std_logic_vector(262180727,28); exponent <= '0'; WHEN "0010110000" => manhi <= conv_std_logic_vector(3146220,24); manlo <= conv_std_logic_vector(257956599,28); exponent <= '0'; WHEN "0010110001" => manhi <= conv_std_logic_vector(3165686,24); manlo <= conv_std_logic_vector(253859075,28); exponent <= '0'; WHEN "0010110010" => manhi <= conv_std_logic_vector(3185171,24); manlo <= conv_std_logic_vector(254871446,28); exponent <= '0'; WHEN "0010110011" => manhi <= conv_std_logic_vector(3204675,24); manlo <= conv_std_logic_vector(265981875,28); exponent <= '0'; WHEN "0010110100" => manhi <= conv_std_logic_vector(3224199,24); manlo <= conv_std_logic_vector(23747940,28); exponent <= '0'; WHEN "0010110101" => manhi <= conv_std_logic_vector(3243741,24); manlo <= conv_std_logic_vector(70038466,28); exponent <= '0'; WHEN "0010110110" => manhi <= conv_std_logic_vector(3263302,24); manlo <= conv_std_logic_vector(141420795,28); exponent <= '0'; WHEN "0010110111" => manhi <= conv_std_logic_vector(3282882,24); manlo <= conv_std_logic_vector(242902610,28); exponent <= '0'; WHEN "0010111000" => manhi <= conv_std_logic_vector(3302482,24); manlo <= conv_std_logic_vector(111061033,28); exponent <= '0'; WHEN "0010111001" => manhi <= conv_std_logic_vector(3322101,24); manlo <= conv_std_logic_vector(19348994,28); exponent <= '0'; WHEN "0010111010" => manhi <= conv_std_logic_vector(3341738,24); manlo <= conv_std_logic_vector(241224327,28); exponent <= '0'; WHEN "0010111011" => manhi <= conv_std_logic_vector(3361395,24); manlo <= conv_std_logic_vector(244843403,28); exponent <= '0'; WHEN "0010111100" => manhi <= conv_std_logic_vector(3381072,24); manlo <= conv_std_logic_vector(35238419,28); exponent <= '0'; WHEN "0010111101" => manhi <= conv_std_logic_vector(3400767,24); manlo <= conv_std_logic_vector(154317398,28); exponent <= '0'; WHEN "0010111110" => manhi <= conv_std_logic_vector(3420482,24); manlo <= conv_std_logic_vector(70251462,28); exponent <= '0'; WHEN "0010111111" => manhi <= conv_std_logic_vector(3440216,24); manlo <= conv_std_logic_vector(56523029,28); exponent <= '0'; WHEN "0011000000" => manhi <= conv_std_logic_vector(3459969,24); manlo <= conv_std_logic_vector(118183989,28); exponent <= '0'; WHEN "0011000001" => manhi <= conv_std_logic_vector(3479741,24); manlo <= conv_std_logic_vector(260291170,28); exponent <= '0'; WHEN "0011000010" => manhi <= conv_std_logic_vector(3499533,24); manlo <= conv_std_logic_vector(219470882,28); exponent <= '0'; WHEN "0011000011" => manhi <= conv_std_logic_vector(3519345,24); manlo <= conv_std_logic_vector(789841,28); exponent <= '0'; WHEN "0011000100" => manhi <= conv_std_logic_vector(3539175,24); manlo <= conv_std_logic_vector(146190621,28); exponent <= '0'; WHEN "0011000101" => manhi <= conv_std_logic_vector(3559025,24); manlo <= conv_std_logic_vector(123878930,28); exponent <= '0'; WHEN "0011000110" => manhi <= conv_std_logic_vector(3578894,24); manlo <= conv_std_logic_vector(207371803,28); exponent <= '0'; WHEN "0011000111" => manhi <= conv_std_logic_vector(3598783,24); manlo <= conv_std_logic_vector(133320328,28); exponent <= '0'; WHEN "0011001000" => manhi <= conv_std_logic_vector(3618691,24); manlo <= conv_std_logic_vector(175251474,28); exponent <= '0'; WHEN "0011001001" => manhi <= conv_std_logic_vector(3638619,24); manlo <= conv_std_logic_vector(69826275,28); exponent <= '0'; WHEN "0011001010" => manhi <= conv_std_logic_vector(3658566,24); manlo <= conv_std_logic_vector(90581653,28); exponent <= '0'; WHEN "0011001011" => manhi <= conv_std_logic_vector(3678532,24); manlo <= conv_std_logic_vector(242624062,28); exponent <= '0'; WHEN "0011001100" => manhi <= conv_std_logic_vector(3698518,24); manlo <= conv_std_logic_vector(262629486,28); exponent <= '0'; WHEN "0011001101" => manhi <= conv_std_logic_vector(3718524,24); manlo <= conv_std_logic_vector(155714362,28); exponent <= '0'; WHEN "0011001110" => manhi <= conv_std_logic_vector(3738549,24); manlo <= conv_std_logic_vector(195435578,28); exponent <= '0'; WHEN "0011001111" => manhi <= conv_std_logic_vector(3758594,24); manlo <= conv_std_logic_vector(118484119,28); exponent <= '0'; WHEN "0011010000" => manhi <= conv_std_logic_vector(3778658,24); manlo <= conv_std_logic_vector(198426886,28); exponent <= '0'; WHEN "0011010001" => manhi <= conv_std_logic_vector(3798742,24); manlo <= conv_std_logic_vector(171964885,28); exponent <= '0'; WHEN "0011010010" => manhi <= conv_std_logic_vector(3818846,24); manlo <= conv_std_logic_vector(44239595,28); exponent <= '0'; WHEN "0011010011" => manhi <= conv_std_logic_vector(3838969,24); manlo <= conv_std_logic_vector(88832973,28); exponent <= '0'; WHEN "0011010100" => manhi <= conv_std_logic_vector(3859112,24); manlo <= conv_std_logic_vector(42461096,28); exponent <= '0'; WHEN "0011010101" => manhi <= conv_std_logic_vector(3879274,24); manlo <= conv_std_logic_vector(178715983,28); exponent <= '0'; WHEN "0011010110" => manhi <= conv_std_logic_vector(3899456,24); manlo <= conv_std_logic_vector(234323781,28); exponent <= '0'; WHEN "0011010111" => manhi <= conv_std_logic_vector(3919658,24); manlo <= conv_std_logic_vector(214451135,28); exponent <= '0'; WHEN "0011011000" => manhi <= conv_std_logic_vector(3939880,24); manlo <= conv_std_logic_vector(124269738,28); exponent <= '0'; WHEN "0011011001" => manhi <= conv_std_logic_vector(3960121,24); manlo <= conv_std_logic_vector(237391794,28); exponent <= '0'; WHEN "0011011010" => manhi <= conv_std_logic_vector(3980383,24); manlo <= conv_std_logic_vector(22128194,28); exponent <= '0'; WHEN "0011011011" => manhi <= conv_std_logic_vector(4000664,24); manlo <= conv_std_logic_vector(20536717,28); exponent <= '0'; WHEN "0011011100" => manhi <= conv_std_logic_vector(4020964,24); manlo <= conv_std_logic_vector(237809299,28); exponent <= '0'; WHEN "0011011101" => manhi <= conv_std_logic_vector(4041285,24); manlo <= conv_std_logic_vector(142272034,28); exponent <= '0'; WHEN "0011011110" => manhi <= conv_std_logic_vector(4061626,24); manlo <= conv_std_logic_vector(7562465,28); exponent <= '0'; WHEN "0011011111" => manhi <= conv_std_logic_vector(4081986,24); manlo <= conv_std_logic_vector(107323215,28); exponent <= '0'; WHEN "0011100000" => manhi <= conv_std_logic_vector(4102366,24); manlo <= conv_std_logic_vector(178331084,28); exponent <= '0'; WHEN "0011100001" => manhi <= conv_std_logic_vector(4122766,24); manlo <= conv_std_logic_vector(225803419,28); exponent <= '0'; WHEN "0011100010" => manhi <= conv_std_logic_vector(4143186,24); manlo <= conv_std_logic_vector(254962667,28); exponent <= '0'; WHEN "0011100011" => manhi <= conv_std_logic_vector(4163627,24); manlo <= conv_std_logic_vector(2600920,28); exponent <= '0'; WHEN "0011100100" => manhi <= conv_std_logic_vector(4184087,24); manlo <= conv_std_logic_vector(10821746,28); exponent <= '0'; WHEN "0011100101" => manhi <= conv_std_logic_vector(4204567,24); manlo <= conv_std_logic_vector(16427456,28); exponent <= '0'; WHEN "0011100110" => manhi <= conv_std_logic_vector(4225067,24); manlo <= conv_std_logic_vector(24660936,28); exponent <= '0'; WHEN "0011100111" => manhi <= conv_std_logic_vector(4245587,24); manlo <= conv_std_logic_vector(40770196,28); exponent <= '0'; WHEN "0011101000" => manhi <= conv_std_logic_vector(4266127,24); manlo <= conv_std_logic_vector(70008370,28); exponent <= '0'; WHEN "0011101001" => manhi <= conv_std_logic_vector(4286687,24); manlo <= conv_std_logic_vector(117633727,28); exponent <= '0'; WHEN "0011101010" => manhi <= conv_std_logic_vector(4307267,24); manlo <= conv_std_logic_vector(188909673,28); exponent <= '0'; WHEN "0011101011" => manhi <= conv_std_logic_vector(4327868,24); manlo <= conv_std_logic_vector(20669300,28); exponent <= '0'; WHEN "0011101100" => manhi <= conv_std_logic_vector(4348488,24); manlo <= conv_std_logic_vector(155057216,28); exponent <= '0'; WHEN "0011101101" => manhi <= conv_std_logic_vector(4369129,24); manlo <= conv_std_logic_vector(60481357,28); exponent <= '0'; WHEN "0011101110" => manhi <= conv_std_logic_vector(4389790,24); manlo <= conv_std_logic_vector(10661187,28); exponent <= '0'; WHEN "0011101111" => manhi <= conv_std_logic_vector(4410471,24); manlo <= conv_std_logic_vector(10885873,28); exponent <= '0'; WHEN "0011110000" => manhi <= conv_std_logic_vector(4431172,24); manlo <= conv_std_logic_vector(66449753,28); exponent <= '0'; WHEN "0011110001" => manhi <= conv_std_logic_vector(4451893,24); manlo <= conv_std_logic_vector(182652336,28); exponent <= '0'; WHEN "0011110010" => manhi <= conv_std_logic_vector(4472635,24); manlo <= conv_std_logic_vector(96362852,28); exponent <= '0'; WHEN "0011110011" => manhi <= conv_std_logic_vector(4493397,24); manlo <= conv_std_logic_vector(81326629,28); exponent <= '0'; WHEN "0011110100" => manhi <= conv_std_logic_vector(4514179,24); manlo <= conv_std_logic_vector(142858724,28); exponent <= '0'; WHEN "0011110101" => manhi <= conv_std_logic_vector(4534982,24); manlo <= conv_std_logic_vector(17843933,28); exponent <= '0'; WHEN "0011110110" => manhi <= conv_std_logic_vector(4555804,24); manlo <= conv_std_logic_vector(248478616,28); exponent <= '0'; WHEN "0011110111" => manhi <= conv_std_logic_vector(4576648,24); manlo <= conv_std_logic_vector(34787059,28); exponent <= '0'; WHEN "0011111000" => manhi <= conv_std_logic_vector(4597511,24); manlo <= conv_std_logic_vector(187411489,28); exponent <= '0'; WHEN "0011111001" => manhi <= conv_std_logic_vector(4618395,24); manlo <= conv_std_logic_vector(174822068,28); exponent <= '0'; WHEN "0011111010" => manhi <= conv_std_logic_vector(4639300,24); manlo <= conv_std_logic_vector(2365090,28); exponent <= '0'; WHEN "0011111011" => manhi <= conv_std_logic_vector(4660224,24); manlo <= conv_std_logic_vector(212262982,28); exponent <= '0'; WHEN "0011111100" => manhi <= conv_std_logic_vector(4681170,24); manlo <= conv_std_logic_vector(4566120,28); exponent <= '0'; WHEN "0011111101" => manhi <= conv_std_logic_vector(4702135,24); manlo <= conv_std_logic_vector(189942850,28); exponent <= '0'; WHEN "0011111110" => manhi <= conv_std_logic_vector(4723121,24); manlo <= conv_std_logic_vector(236889480,28); exponent <= '0'; WHEN "0011111111" => manhi <= conv_std_logic_vector(4744128,24); manlo <= conv_std_logic_vector(150778468,28); exponent <= '0'; WHEN "0100000000" => manhi <= conv_std_logic_vector(4765155,24); manlo <= conv_std_logic_vector(205422982,28); exponent <= '0'; WHEN "0100000001" => manhi <= conv_std_logic_vector(4786203,24); manlo <= conv_std_logic_vector(137770531,28); exponent <= '0'; WHEN "0100000010" => manhi <= conv_std_logic_vector(4807271,24); manlo <= conv_std_logic_vector(221644793,28); exponent <= '0'; WHEN "0100000011" => manhi <= conv_std_logic_vector(4828360,24); manlo <= conv_std_logic_vector(194003802,28); exponent <= '0'; WHEN "0100000100" => manhi <= conv_std_logic_vector(4849470,24); manlo <= conv_std_logic_vector(60246316,28); exponent <= '0'; WHEN "0100000101" => manhi <= conv_std_logic_vector(4870600,24); manlo <= conv_std_logic_vector(94211823,28); exponent <= '0'; WHEN "0100000110" => manhi <= conv_std_logic_vector(4891751,24); manlo <= conv_std_logic_vector(32874180,28); exponent <= '0'; WHEN "0100000111" => manhi <= conv_std_logic_vector(4912922,24); manlo <= conv_std_logic_vector(150083442,28); exponent <= '0'; WHEN "0100001000" => manhi <= conv_std_logic_vector(4934114,24); manlo <= conv_std_logic_vector(182824039,28); exponent <= '0'; WHEN "0100001001" => manhi <= conv_std_logic_vector(4955327,24); manlo <= conv_std_logic_vector(136521157,28); exponent <= '0'; WHEN "0100001010" => manhi <= conv_std_logic_vector(4976561,24); manlo <= conv_std_logic_vector(16605280,28); exponent <= '0'; WHEN "0100001011" => manhi <= conv_std_logic_vector(4997815,24); manlo <= conv_std_logic_vector(96947652,28); exponent <= '0'; WHEN "0100001100" => manhi <= conv_std_logic_vector(5019090,24); manlo <= conv_std_logic_vector(114553920,28); exponent <= '0'; WHEN "0100001101" => manhi <= conv_std_logic_vector(5040386,24); manlo <= conv_std_logic_vector(74870501,28); exponent <= '0'; WHEN "0100001110" => manhi <= conv_std_logic_vector(5061702,24); manlo <= conv_std_logic_vector(251784590,28); exponent <= '0'; WHEN "0100001111" => manhi <= conv_std_logic_vector(5083040,24); manlo <= conv_std_logic_vector(113882338,28); exponent <= '0'; WHEN "0100010000" => manhi <= conv_std_logic_vector(5104398,24); manlo <= conv_std_logic_vector(203497056,28); exponent <= '0'; WHEN "0100010001" => manhi <= conv_std_logic_vector(5125777,24); manlo <= conv_std_logic_vector(257661021,28); exponent <= '0'; WHEN "0100010010" => manhi <= conv_std_logic_vector(5147178,24); manlo <= conv_std_logic_vector(13411854,28); exponent <= '0'; WHEN "0100010011" => manhi <= conv_std_logic_vector(5168599,24); manlo <= conv_std_logic_vector(13098889,28); exponent <= '0'; WHEN "0100010100" => manhi <= conv_std_logic_vector(5190040,24); manlo <= conv_std_logic_vector(262205904,28); exponent <= '0'; WHEN "0100010101" => manhi <= conv_std_logic_vector(5211503,24); manlo <= conv_std_logic_vector(229351119,28); exponent <= '0'; WHEN "0100010110" => manhi <= conv_std_logic_vector(5232987,24); manlo <= conv_std_logic_vector(188464488,28); exponent <= '0'; WHEN "0100010111" => manhi <= conv_std_logic_vector(5254492,24); manlo <= conv_std_logic_vector(145045878,28); exponent <= '0'; WHEN "0100011000" => manhi <= conv_std_logic_vector(5276018,24); manlo <= conv_std_logic_vector(104600525,28); exponent <= '0'; WHEN "0100011001" => manhi <= conv_std_logic_vector(5297565,24); manlo <= conv_std_logic_vector(72639049,28); exponent <= '0'; WHEN "0100011010" => manhi <= conv_std_logic_vector(5319133,24); manlo <= conv_std_logic_vector(54677451,28); exponent <= '0'; WHEN "0100011011" => manhi <= conv_std_logic_vector(5340722,24); manlo <= conv_std_logic_vector(56237123,28); exponent <= '0'; WHEN "0100011100" => manhi <= conv_std_logic_vector(5362332,24); manlo <= conv_std_logic_vector(82844851,28); exponent <= '0'; WHEN "0100011101" => manhi <= conv_std_logic_vector(5383963,24); manlo <= conv_std_logic_vector(140032820,28); exponent <= '0'; WHEN "0100011110" => manhi <= conv_std_logic_vector(5405615,24); manlo <= conv_std_logic_vector(233338622,28); exponent <= '0'; WHEN "0100011111" => manhi <= conv_std_logic_vector(5427289,24); manlo <= conv_std_logic_vector(99869801,28); exponent <= '0'; WHEN "0100100000" => manhi <= conv_std_logic_vector(5448984,24); manlo <= conv_std_logic_vector(13610232,28); exponent <= '0'; WHEN "0100100001" => manhi <= conv_std_logic_vector(5470699,24); manlo <= conv_std_logic_vector(248549207,28); exponent <= '0'; WHEN "0100100010" => manhi <= conv_std_logic_vector(5492437,24); manlo <= conv_std_logic_vector(4939624,28); exponent <= '0'; WHEN "0100100011" => manhi <= conv_std_logic_vector(5514195,24); manlo <= conv_std_logic_vector(93652547,28); exponent <= '0'; WHEN "0100100100" => manhi <= conv_std_logic_vector(5535974,24); manlo <= conv_std_logic_vector(251822653,28); exponent <= '0'; WHEN "0100100101" => manhi <= conv_std_logic_vector(5557775,24); manlo <= conv_std_logic_vector(216590061,28); exponent <= '0'; WHEN "0100100110" => manhi <= conv_std_logic_vector(5579597,24); manlo <= conv_std_logic_vector(261971250,28); exponent <= '0'; WHEN "0100100111" => manhi <= conv_std_logic_vector(5601441,24); manlo <= conv_std_logic_vector(125117240,28); exponent <= '0'; WHEN "0100101000" => manhi <= conv_std_logic_vector(5623306,24); manlo <= conv_std_logic_vector(80055420,28); exponent <= '0'; WHEN "0100101001" => manhi <= conv_std_logic_vector(5645192,24); manlo <= conv_std_logic_vector(132383188,28); exponent <= '0'; WHEN "0100101010" => manhi <= conv_std_logic_vector(5667100,24); manlo <= conv_std_logic_vector(19267955,28); exponent <= '0'; WHEN "0100101011" => manhi <= conv_std_logic_vector(5689029,24); manlo <= conv_std_logic_vector(14753516,28); exponent <= '0'; WHEN "0100101100" => manhi <= conv_std_logic_vector(5710979,24); manlo <= conv_std_logic_vector(124453694,28); exponent <= '0'; WHEN "0100101101" => manhi <= conv_std_logic_vector(5732951,24); manlo <= conv_std_logic_vector(85552334,28); exponent <= '0'; WHEN "0100101110" => manhi <= conv_std_logic_vector(5754944,24); manlo <= conv_std_logic_vector(172109691,28); exponent <= '0'; WHEN "0100101111" => manhi <= conv_std_logic_vector(5776959,24); manlo <= conv_std_logic_vector(121320598,28); exponent <= '0'; WHEN "0100110000" => manhi <= conv_std_logic_vector(5798995,24); manlo <= conv_std_logic_vector(207256304,28); exponent <= '0'; WHEN "0100110001" => manhi <= conv_std_logic_vector(5821053,24); manlo <= conv_std_logic_vector(167122651,28); exponent <= '0'; WHEN "0100110010" => manhi <= conv_std_logic_vector(5843133,24); manlo <= conv_std_logic_vector(6566449,28); exponent <= '0'; WHEN "0100110011" => manhi <= conv_std_logic_vector(5865233,24); manlo <= conv_std_logic_vector(268110937,28); exponent <= '0'; WHEN "0100110100" => manhi <= conv_std_logic_vector(5887356,24); manlo <= conv_std_logic_vector(152107598,28); exponent <= '0'; WHEN "0100110101" => manhi <= conv_std_logic_vector(5909500,24); manlo <= conv_std_logic_vector(201090721,28); exponent <= '0'; WHEN "0100110110" => manhi <= conv_std_logic_vector(5931666,24); manlo <= conv_std_logic_vector(152293761,28); exponent <= '0'; WHEN "0100110111" => manhi <= conv_std_logic_vector(5953854,24); manlo <= conv_std_logic_vector(11391168,28); exponent <= '0'; WHEN "0100111000" => manhi <= conv_std_logic_vector(5976063,24); manlo <= conv_std_logic_vector(52498394,28); exponent <= '0'; WHEN "0100111001" => manhi <= conv_std_logic_vector(5998294,24); manlo <= conv_std_logic_vector(12865523,28); exponent <= '0'; WHEN "0100111010" => manhi <= conv_std_logic_vector(6020546,24); manlo <= conv_std_logic_vector(166619112,28); exponent <= '0'; WHEN "0100111011" => manhi <= conv_std_logic_vector(6042820,24); manlo <= conv_std_logic_vector(251020365,28); exponent <= '0'; WHEN "0100111100" => manhi <= conv_std_logic_vector(6065117,24); manlo <= conv_std_logic_vector(3336048,28); exponent <= '0'; WHEN "0100111101" => manhi <= conv_std_logic_vector(6087434,24); manlo <= conv_std_logic_vector(234580328,28); exponent <= '0'; WHEN "0100111110" => manhi <= conv_std_logic_vector(6109774,24); manlo <= conv_std_logic_vector(145160209,28); exponent <= '0'; WHEN "0100111111" => manhi <= conv_std_logic_vector(6132136,24); manlo <= conv_std_logic_vector(9230102,28); exponent <= '0'; WHEN "0101000000" => manhi <= conv_std_logic_vector(6154519,24); manlo <= conv_std_logic_vector(100950005,28); exponent <= '0'; WHEN "0101000001" => manhi <= conv_std_logic_vector(6176924,24); manlo <= conv_std_logic_vector(157614600,28); exponent <= '0'; WHEN "0101000010" => manhi <= conv_std_logic_vector(6199351,24); manlo <= conv_std_logic_vector(184959620,28); exponent <= '0'; WHEN "0101000011" => manhi <= conv_std_logic_vector(6221800,24); manlo <= conv_std_logic_vector(188726403,28); exponent <= '0'; WHEN "0101000100" => manhi <= conv_std_logic_vector(6244271,24); manlo <= conv_std_logic_vector(174661898,28); exponent <= '0'; WHEN "0101000101" => manhi <= conv_std_logic_vector(6266764,24); manlo <= conv_std_logic_vector(148518669,28); exponent <= '0'; WHEN "0101000110" => manhi <= conv_std_logic_vector(6289279,24); manlo <= conv_std_logic_vector(116054898,28); exponent <= '0'; WHEN "0101000111" => manhi <= conv_std_logic_vector(6311816,24); manlo <= conv_std_logic_vector(83034395,28); exponent <= '0'; WHEN "0101001000" => manhi <= conv_std_logic_vector(6334375,24); manlo <= conv_std_logic_vector(55226600,28); exponent <= '0'; WHEN "0101001001" => manhi <= conv_std_logic_vector(6356956,24); manlo <= conv_std_logic_vector(38406593,28); exponent <= '0'; WHEN "0101001010" => manhi <= conv_std_logic_vector(6379559,24); manlo <= conv_std_logic_vector(38355093,28); exponent <= '0'; WHEN "0101001011" => manhi <= conv_std_logic_vector(6402184,24); manlo <= conv_std_logic_vector(60858469,28); exponent <= '0'; WHEN "0101001100" => manhi <= conv_std_logic_vector(6424831,24); manlo <= conv_std_logic_vector(111708742,28); exponent <= '0'; WHEN "0101001101" => manhi <= conv_std_logic_vector(6447500,24); manlo <= conv_std_logic_vector(196703594,28); exponent <= '0'; WHEN "0101001110" => manhi <= conv_std_logic_vector(6470192,24); manlo <= conv_std_logic_vector(53210914,28); exponent <= '0'; WHEN "0101001111" => manhi <= conv_std_logic_vector(6492905,24); manlo <= conv_std_logic_vector(223910630,28); exponent <= '0'; WHEN "0101010000" => manhi <= conv_std_logic_vector(6515641,24); manlo <= conv_std_logic_vector(177746520,28); exponent <= '0'; WHEN "0101010001" => manhi <= conv_std_logic_vector(6538399,24); manlo <= conv_std_logic_vector(188974414,28); exponent <= '0'; WHEN "0101010010" => manhi <= conv_std_logic_vector(6561179,24); manlo <= conv_std_logic_vector(263420371,28); exponent <= '0'; WHEN "0101010011" => manhi <= conv_std_logic_vector(6583982,24); manlo <= conv_std_logic_vector(138480686,28); exponent <= '0'; WHEN "0101010100" => manhi <= conv_std_logic_vector(6606807,24); manlo <= conv_std_logic_vector(88428264,28); exponent <= '0'; WHEN "0101010101" => manhi <= conv_std_logic_vector(6629654,24); manlo <= conv_std_logic_vector(119106258,28); exponent <= '0'; WHEN "0101010110" => manhi <= conv_std_logic_vector(6652523,24); manlo <= conv_std_logic_vector(236363530,28); exponent <= '0'; WHEN "0101010111" => manhi <= conv_std_logic_vector(6675415,24); manlo <= conv_std_logic_vector(177619200,28); exponent <= '0'; WHEN "0101011000" => manhi <= conv_std_logic_vector(6698329,24); manlo <= conv_std_logic_vector(217169020,28); exponent <= '0'; WHEN "0101011001" => manhi <= conv_std_logic_vector(6721266,24); manlo <= conv_std_logic_vector(92443558,28); exponent <= '0'; WHEN "0101011010" => manhi <= conv_std_logic_vector(6744225,24); manlo <= conv_std_logic_vector(77750021,28); exponent <= '0'; WHEN "0101011011" => manhi <= conv_std_logic_vector(6767206,24); manlo <= conv_std_logic_vector(178965902,28); exponent <= '0'; WHEN "0101011100" => manhi <= conv_std_logic_vector(6790210,24); manlo <= conv_std_logic_vector(133538975,28); exponent <= '0'; WHEN "0101011101" => manhi <= conv_std_logic_vector(6813236,24); manlo <= conv_std_logic_vector(215793680,28); exponent <= '0'; WHEN "0101011110" => manhi <= conv_std_logic_vector(6836285,24); manlo <= conv_std_logic_vector(163189294,28); exponent <= '0'; WHEN "0101011111" => manhi <= conv_std_logic_vector(6859356,24); manlo <= conv_std_logic_vector(250061769,28); exponent <= '0'; WHEN "0101100000" => manhi <= conv_std_logic_vector(6882450,24); manlo <= conv_std_logic_vector(213881907,28); exponent <= '0'; WHEN "0101100001" => manhi <= conv_std_logic_vector(6905567,24); manlo <= conv_std_logic_vector(60561738,28); exponent <= '0'; WHEN "0101100010" => manhi <= conv_std_logic_vector(6928706,24); manlo <= conv_std_logic_vector(64454525,28); exponent <= '0'; WHEN "0101100011" => manhi <= conv_std_logic_vector(6951867,24); manlo <= conv_std_logic_vector(231483856,28); exponent <= '0'; WHEN "0101100100" => manhi <= conv_std_logic_vector(6975052,24); manlo <= conv_std_logic_vector(30708194,28); exponent <= '0'; WHEN "0101100101" => manhi <= conv_std_logic_vector(6998259,24); manlo <= conv_std_logic_vector(4933620,28); exponent <= '0'; WHEN "0101100110" => manhi <= conv_std_logic_vector(7021488,24); manlo <= conv_std_logic_vector(160101103,28); exponent <= '0'; WHEN "0101100111" => manhi <= conv_std_logic_vector(7044740,24); manlo <= conv_std_logic_vector(233721959,28); exponent <= '0'; WHEN "0101101000" => manhi <= conv_std_logic_vector(7068015,24); manlo <= conv_std_logic_vector(231748770,28); exponent <= '0'; WHEN "0101101001" => manhi <= conv_std_logic_vector(7091313,24); manlo <= conv_std_logic_vector(160139936,28); exponent <= '0'; WHEN "0101101010" => manhi <= conv_std_logic_vector(7114634,24); manlo <= conv_std_logic_vector(24859676,28); exponent <= '0'; WHEN "0101101011" => manhi <= conv_std_logic_vector(7137977,24); manlo <= conv_std_logic_vector(100313494,28); exponent <= '0'; WHEN "0101101100" => manhi <= conv_std_logic_vector(7161343,24); manlo <= conv_std_logic_vector(124041814,28); exponent <= '0'; WHEN "0101101101" => manhi <= conv_std_logic_vector(7184732,24); manlo <= conv_std_logic_vector(102026355,28); exponent <= '0'; WHEN "0101101110" => manhi <= conv_std_logic_vector(7208144,24); manlo <= conv_std_logic_vector(40254681,28); exponent <= '0'; WHEN "0101101111" => manhi <= conv_std_logic_vector(7231578,24); manlo <= conv_std_logic_vector(213155662,28); exponent <= '0'; WHEN "0101110000" => manhi <= conv_std_logic_vector(7255036,24); manlo <= conv_std_logic_vector(89857654,28); exponent <= '0'; WHEN "0101110001" => manhi <= conv_std_logic_vector(7278516,24); manlo <= conv_std_logic_vector(213236700,28); exponent <= '0'; WHEN "0101110010" => manhi <= conv_std_logic_vector(7302020,24); manlo <= conv_std_logic_vector(52432888,28); exponent <= '0'; WHEN "0101110011" => manhi <= conv_std_logic_vector(7325546,24); manlo <= conv_std_logic_vector(150334000,28); exponent <= '0'; WHEN "0101110100" => manhi <= conv_std_logic_vector(7349095,24); manlo <= conv_std_logic_vector(244527329,28); exponent <= '0'; WHEN "0101110101" => manhi <= conv_std_logic_vector(7372668,24); manlo <= conv_std_logic_vector(72606054,28); exponent <= '0'; WHEN "0101110110" => manhi <= conv_std_logic_vector(7396263,24); manlo <= conv_std_logic_vector(177475612,28); exponent <= '0'; WHEN "0101110111" => manhi <= conv_std_logic_vector(7419882,24); manlo <= conv_std_logic_vector(28305511,28); exponent <= '0'; WHEN "0101111000" => manhi <= conv_std_logic_vector(7443523,24); manlo <= conv_std_logic_vector(168012985,28); exponent <= '0'; WHEN "0101111001" => manhi <= conv_std_logic_vector(7467188,24); manlo <= conv_std_logic_vector(65779352,28); exponent <= '0'; WHEN "0101111010" => manhi <= conv_std_logic_vector(7490875,24); manlo <= conv_std_logic_vector(264533668,28); exponent <= '0'; WHEN "0101111011" => manhi <= conv_std_logic_vector(7514586,24); manlo <= conv_std_logic_vector(233469080,28); exponent <= '0'; WHEN "0101111100" => manhi <= conv_std_logic_vector(7538320,24); manlo <= conv_std_logic_vector(247091035,28); exponent <= '0'; WHEN "0101111101" => manhi <= conv_std_logic_vector(7562078,24); manlo <= conv_std_logic_vector(43039991,28); exponent <= '0'; WHEN "0101111110" => manhi <= conv_std_logic_vector(7585858,24); manlo <= conv_std_logic_vector(164268716,28); exponent <= '0'; WHEN "0101111111" => manhi <= conv_std_logic_vector(7609662,24); manlo <= conv_std_logic_vector(79994093,28); exponent <= '0'; WHEN "0110000000" => manhi <= conv_std_logic_vector(7633489,24); manlo <= conv_std_logic_vector(64745322,28); exponent <= '0'; WHEN "0110000001" => manhi <= conv_std_logic_vector(7657339,24); manlo <= conv_std_logic_vector(124622102,28); exponent <= '0'; WHEN "0110000010" => manhi <= conv_std_logic_vector(7681212,24); manlo <= conv_std_logic_vector(265730090,28); exponent <= '0'; WHEN "0110000011" => manhi <= conv_std_logic_vector(7705109,24); manlo <= conv_std_logic_vector(225745453,28); exponent <= '0'; WHEN "0110000100" => manhi <= conv_std_logic_vector(7729030,24); manlo <= conv_std_logic_vector(10785785,28); exponent <= '0'; WHEN "0110000101" => manhi <= conv_std_logic_vector(7752973,24); manlo <= conv_std_logic_vector(163845570,28); exponent <= '0'; WHEN "0110000110" => manhi <= conv_std_logic_vector(7776940,24); manlo <= conv_std_logic_vector(154183450,28); exponent <= '0'; WHEN "0110000111" => manhi <= conv_std_logic_vector(7800930,24); manlo <= conv_std_logic_vector(256370426,28); exponent <= '0'; WHEN "0110001000" => manhi <= conv_std_logic_vector(7824944,24); manlo <= conv_std_logic_vector(208112577,28); exponent <= '0'; WHEN "0110001001" => manhi <= conv_std_logic_vector(7848982,24); manlo <= conv_std_logic_vector(15557444,28); exponent <= '0'; WHEN "0110001010" => manhi <= conv_std_logic_vector(7873042,24); manlo <= conv_std_logic_vector(221729482,28); exponent <= '0'; WHEN "0110001011" => manhi <= conv_std_logic_vector(7897127,24); manlo <= conv_std_logic_vector(27481881,28); exponent <= '0'; WHEN "0110001100" => manhi <= conv_std_logic_vector(7921234,24); manlo <= conv_std_logic_vector(244286584,28); exponent <= '0'; WHEN "0110001101" => manhi <= conv_std_logic_vector(7945366,24); manlo <= conv_std_logic_vector(73008824,28); exponent <= '0'; WHEN "0110001110" => manhi <= conv_std_logic_vector(7969521,24); manlo <= conv_std_logic_vector(56697140,28); exponent <= '0'; WHEN "0110001111" => manhi <= conv_std_logic_vector(7993699,24); manlo <= conv_std_logic_vector(201535196,28); exponent <= '0'; WHEN "0110010000" => manhi <= conv_std_logic_vector(8017901,24); manlo <= conv_std_logic_vector(245277246,28); exponent <= '0'; WHEN "0110010001" => manhi <= conv_std_logic_vector(8042127,24); manlo <= conv_std_logic_vector(194119042,28); exponent <= '0'; WHEN "0110010010" => manhi <= conv_std_logic_vector(8066377,24); manlo <= conv_std_logic_vector(54262392,28); exponent <= '0'; WHEN "0110010011" => manhi <= conv_std_logic_vector(8090650,24); manlo <= conv_std_logic_vector(100350618,28); exponent <= '0'; WHEN "0110010100" => manhi <= conv_std_logic_vector(8114947,24); manlo <= conv_std_logic_vector(70162199,28); exponent <= '0'; WHEN "0110010101" => manhi <= conv_std_logic_vector(8139267,24); manlo <= conv_std_logic_vector(238352593,28); exponent <= '0'; WHEN "0110010110" => manhi <= conv_std_logic_vector(8163612,24); manlo <= conv_std_logic_vector(74276969,28); exponent <= '0'; WHEN "0110010111" => manhi <= conv_std_logic_vector(8187980,24); manlo <= conv_std_logic_vector(121038404,28); exponent <= '0'; WHEN "0110011000" => manhi <= conv_std_logic_vector(8212372,24); manlo <= conv_std_logic_vector(116439694,28); exponent <= '0'; WHEN "0110011001" => manhi <= conv_std_logic_vector(8236788,24); manlo <= conv_std_logic_vector(66725186,28); exponent <= '0'; WHEN "0110011010" => manhi <= conv_std_logic_vector(8261227,24); manlo <= conv_std_logic_vector(246580788,28); exponent <= '0'; WHEN "0110011011" => manhi <= conv_std_logic_vector(8285691,24); manlo <= conv_std_logic_vector(125392143,28); exponent <= '0'; WHEN "0110011100" => manhi <= conv_std_logic_vector(8310178,24); manlo <= conv_std_logic_vector(246292830,28); exponent <= '0'; WHEN "0110011101" => manhi <= conv_std_logic_vector(8334690,24); manlo <= conv_std_logic_vector(78680728,28); exponent <= '0'; WHEN "0110011110" => manhi <= conv_std_logic_vector(8359225,24); manlo <= conv_std_logic_vector(165701659,28); exponent <= '0'; WHEN "0110011111" => manhi <= conv_std_logic_vector(8383784,24); manlo <= conv_std_logic_vector(245201212,28); exponent <= '0'; WHEN "0110100000" => manhi <= conv_std_logic_vector(8408368,24); manlo <= conv_std_logic_vector(55031110,28); exponent <= '0'; WHEN "0110100001" => manhi <= conv_std_logic_vector(8432975,24); manlo <= conv_std_logic_vector(138355589,28); exponent <= '0'; WHEN "0110100010" => manhi <= conv_std_logic_vector(8457606,24); manlo <= conv_std_logic_vector(233038665,28); exponent <= '0'; WHEN "0110100011" => manhi <= conv_std_logic_vector(8482262,24); manlo <= conv_std_logic_vector(76950508,28); exponent <= '0'; WHEN "0110100100" => manhi <= conv_std_logic_vector(8506941,24); manlo <= conv_std_logic_vector(213273820,28); exponent <= '0'; WHEN "0110100101" => manhi <= conv_std_logic_vector(8531645,24); manlo <= conv_std_logic_vector(111455640,28); exponent <= '0'; WHEN "0110100110" => manhi <= conv_std_logic_vector(8556373,24); manlo <= conv_std_logic_vector(46255554,28); exponent <= '0'; WHEN "0110100111" => manhi <= conv_std_logic_vector(8581125,24); manlo <= conv_std_logic_vector(24003868,28); exponent <= '0'; WHEN "0110101000" => manhi <= conv_std_logic_vector(8605901,24); manlo <= conv_std_logic_vector(51037072,28); exponent <= '0'; WHEN "0110101001" => manhi <= conv_std_logic_vector(8630701,24); manlo <= conv_std_logic_vector(133697849,28); exponent <= '0'; WHEN "0110101010" => manhi <= conv_std_logic_vector(8655526,24); manlo <= conv_std_logic_vector(9899623,28); exponent <= '0'; WHEN "0110101011" => manhi <= conv_std_logic_vector(8680374,24); manlo <= conv_std_logic_vector(222868388,28); exponent <= '0'; WHEN "0110101100" => manhi <= conv_std_logic_vector(8705247,24); manlo <= conv_std_logic_vector(242094523,28); exponent <= '0'; WHEN "0110101101" => manhi <= conv_std_logic_vector(8730145,24); manlo <= conv_std_logic_vector(73945536,28); exponent <= '0'; WHEN "0110101110" => manhi <= conv_std_logic_vector(8755066,24); manlo <= conv_std_logic_vector(261666066,28); exponent <= '0'; WHEN "0110101111" => manhi <= conv_std_logic_vector(8780013,24); manlo <= conv_std_logic_vector(6329700,28); exponent <= '0'; WHEN "0110110000" => manhi <= conv_std_logic_vector(8804983,24); manlo <= conv_std_logic_vector(119628997,28); exponent <= '0'; WHEN "0110110001" => manhi <= conv_std_logic_vector(8829978,24); manlo <= conv_std_logic_vector(71085473,28); exponent <= '0'; WHEN "0110110010" => manhi <= conv_std_logic_vector(8854997,24); manlo <= conv_std_logic_vector(135533257,28); exponent <= '0'; WHEN "0110110011" => manhi <= conv_std_logic_vector(8880041,24); manlo <= conv_std_logic_vector(50941820,28); exponent <= '0'; WHEN "0110110100" => manhi <= conv_std_logic_vector(8905109,24); manlo <= conv_std_logic_vector(92157802,28); exponent <= '0'; WHEN "0110110101" => manhi <= conv_std_logic_vector(8930201,24); manlo <= conv_std_logic_vector(265598650,28); exponent <= '0'; WHEN "0110110110" => manhi <= conv_std_logic_vector(8955319,24); manlo <= conv_std_logic_vector(40817170,28); exponent <= '0'; WHEN "0110110111" => manhi <= conv_std_logic_vector(8980460,24); manlo <= conv_std_logic_vector(229549724,28); exponent <= '0'; WHEN "0110111000" => manhi <= conv_std_logic_vector(9005627,24); manlo <= conv_std_logic_vector(32926222,28); exponent <= '0'; WHEN "0110111001" => manhi <= conv_std_logic_vector(9030817,24); manlo <= conv_std_logic_vector(262695596,28); exponent <= '0'; WHEN "0110111010" => manhi <= conv_std_logic_vector(9056033,24); manlo <= conv_std_logic_vector(120000337,28); exponent <= '0'; WHEN "0110111011" => manhi <= conv_std_logic_vector(9081273,24); manlo <= conv_std_logic_vector(148166518,28); exponent <= '0'; WHEN "0110111100" => manhi <= conv_std_logic_vector(9106538,24); manlo <= conv_std_logic_vector(85220151,28); exponent <= '0'; WHEN "0110111101" => manhi <= conv_std_logic_vector(9131827,24); manlo <= conv_std_logic_vector(206064472,28); exponent <= '0'; WHEN "0110111110" => manhi <= conv_std_logic_vector(9157141,24); manlo <= conv_std_logic_vector(248738124,28); exponent <= '0'; WHEN "0110111111" => manhi <= conv_std_logic_vector(9182480,24); manlo <= conv_std_logic_vector(219721533,28); exponent <= '0'; WHEN "0111000000" => manhi <= conv_std_logic_vector(9207844,24); manlo <= conv_std_logic_vector(125501456,28); exponent <= '0'; WHEN "0111000001" => manhi <= conv_std_logic_vector(9233232,24); manlo <= conv_std_logic_vector(241006443,28); exponent <= '0'; WHEN "0111000010" => manhi <= conv_std_logic_vector(9258646,24); manlo <= conv_std_logic_vector(35865021,28); exponent <= '0'; WHEN "0111000011" => manhi <= conv_std_logic_vector(9284084,24); manlo <= conv_std_logic_vector(53453891,28); exponent <= '0'; WHEN "0111000100" => manhi <= conv_std_logic_vector(9309547,24); manlo <= conv_std_logic_vector(31849742,28); exponent <= '0'; WHEN "0111000101" => manhi <= conv_std_logic_vector(9335034,24); manlo <= conv_std_logic_vector(246006538,28); exponent <= '0'; WHEN "0111000110" => manhi <= conv_std_logic_vector(9360547,24); manlo <= conv_std_logic_vector(165578245,28); exponent <= '0'; WHEN "0111000111" => manhi <= conv_std_logic_vector(9386085,24); manlo <= conv_std_logic_vector(65531569,28); exponent <= '0'; WHEN "0111001000" => manhi <= conv_std_logic_vector(9411647,24); manlo <= conv_std_logic_vector(220839600,28); exponent <= '0'; WHEN "0111001001" => manhi <= conv_std_logic_vector(9437235,24); manlo <= conv_std_logic_vector(101175446,28); exponent <= '0'; WHEN "0111001010" => manhi <= conv_std_logic_vector(9462847,24); manlo <= conv_std_logic_vector(249960434,28); exponent <= '0'; WHEN "0111001011" => manhi <= conv_std_logic_vector(9488485,24); manlo <= conv_std_logic_vector(136880466,28); exponent <= '0'; WHEN "0111001100" => manhi <= conv_std_logic_vector(9514148,24); manlo <= conv_std_logic_vector(36934219,28); exponent <= '0'; WHEN "0111001101" => manhi <= conv_std_logic_vector(9539835,24); manlo <= conv_std_logic_vector(225126782,28); exponent <= '0'; WHEN "0111001110" => manhi <= conv_std_logic_vector(9565548,24); manlo <= conv_std_logic_vector(171163295,28); exponent <= '0'; WHEN "0111001111" => manhi <= conv_std_logic_vector(9591286,24); manlo <= conv_std_logic_vector(150061692,28); exponent <= '0'; WHEN "0111010000" => manhi <= conv_std_logic_vector(9617049,24); manlo <= conv_std_logic_vector(168410880,28); exponent <= '0'; WHEN "0111010001" => manhi <= conv_std_logic_vector(9642837,24); manlo <= conv_std_logic_vector(232806206,28); exponent <= '0'; WHEN "0111010010" => manhi <= conv_std_logic_vector(9668651,24); manlo <= conv_std_logic_vector(81414002,28); exponent <= '0'; WHEN "0111010011" => manhi <= conv_std_logic_vector(9694489,24); manlo <= conv_std_logic_vector(257713424,28); exponent <= '0'; WHEN "0111010100" => manhi <= conv_std_logic_vector(9720353,24); manlo <= conv_std_logic_vector(231448253,28); exponent <= '0'; WHEN "0111010101" => manhi <= conv_std_logic_vector(9746243,24); manlo <= conv_std_logic_vector(9239650,28); exponent <= '0'; WHEN "0111010110" => manhi <= conv_std_logic_vector(9772157,24); manlo <= conv_std_logic_vector(134586155,28); exponent <= '0'; WHEN "0111010111" => manhi <= conv_std_logic_vector(9798097,24); manlo <= conv_std_logic_vector(77250961,28); exponent <= '0'; WHEN "0111011000" => manhi <= conv_std_logic_vector(9824062,24); manlo <= conv_std_logic_vector(112310110,28); exponent <= '0'; WHEN "0111011001" => manhi <= conv_std_logic_vector(9850052,24); manlo <= conv_std_logic_vector(246410674,28); exponent <= '0'; WHEN "0111011010" => manhi <= conv_std_logic_vector(9876068,24); manlo <= conv_std_logic_vector(217770768,28); exponent <= '0'; WHEN "0111011011" => manhi <= conv_std_logic_vector(9902110,24); manlo <= conv_std_logic_vector(33050459,28); exponent <= '0'; WHEN "0111011100" => manhi <= conv_std_logic_vector(9928176,24); manlo <= conv_std_logic_vector(235787236,28); exponent <= '0'; WHEN "0111011101" => manhi <= conv_std_logic_vector(9954269,24); manlo <= conv_std_logic_vector(27347822,28); exponent <= '0'; WHEN "0111011110" => manhi <= conv_std_logic_vector(9980386,24); manlo <= conv_std_logic_vector(219718194,28); exponent <= '0'; WHEN "0111011111" => manhi <= conv_std_logic_vector(10006530,24); manlo <= conv_std_logic_vector(14278120,28); exponent <= '0'; WHEN "0111100000" => manhi <= conv_std_logic_vector(10032698,24); manlo <= conv_std_logic_vector(223026636,28); exponent <= '0'; WHEN "0111100001" => manhi <= conv_std_logic_vector(10058893,24); manlo <= conv_std_logic_vector(47356582,28); exponent <= '0'; WHEN "0111100010" => manhi <= conv_std_logic_vector(10085113,24); manlo <= conv_std_logic_vector(30844624,28); exponent <= '0'; WHEN "0111100011" => manhi <= conv_std_logic_vector(10111358,24); manlo <= conv_std_logic_vector(180203065,28); exponent <= '0'; WHEN "0111100100" => manhi <= conv_std_logic_vector(10137629,24); manlo <= conv_std_logic_vector(233715314,28); exponent <= '0'; WHEN "0111100101" => manhi <= conv_std_logic_vector(10163926,24); manlo <= conv_std_logic_vector(198106796,28); exponent <= '0'; WHEN "0111100110" => manhi <= conv_std_logic_vector(10190249,24); manlo <= conv_std_logic_vector(80109512,28); exponent <= '0'; WHEN "0111100111" => manhi <= conv_std_logic_vector(10216597,24); manlo <= conv_std_logic_vector(154897493,28); exponent <= '0'; WHEN "0111101000" => manhi <= conv_std_logic_vector(10242971,24); manlo <= conv_std_logic_vector(160780443,28); exponent <= '0'; WHEN "0111101001" => manhi <= conv_std_logic_vector(10269371,24); manlo <= conv_std_logic_vector(104510112,28); exponent <= '0'; WHEN "0111101010" => manhi <= conv_std_logic_vector(10295796,24); manlo <= conv_std_logic_vector(261280303,28); exponent <= '0'; WHEN "0111101011" => manhi <= conv_std_logic_vector(10322248,24); manlo <= conv_std_logic_vector(100985054,28); exponent <= '0'; WHEN "0111101100" => manhi <= conv_std_logic_vector(10348725,24); manlo <= conv_std_logic_vector(167266836,28); exponent <= '0'; WHEN "0111101101" => manhi <= conv_std_logic_vector(10375228,24); manlo <= conv_std_logic_vector(198468370,28); exponent <= '0'; WHEN "0111101110" => manhi <= conv_std_logic_vector(10401757,24); manlo <= conv_std_logic_vector(201374454,28); exponent <= '0'; WHEN "0111101111" => manhi <= conv_std_logic_vector(10428312,24); manlo <= conv_std_logic_vector(182776514,28); exponent <= '0'; WHEN "0111110000" => manhi <= conv_std_logic_vector(10454893,24); manlo <= conv_std_logic_vector(149472614,28); exponent <= '0'; WHEN "0111110001" => manhi <= conv_std_logic_vector(10481500,24); manlo <= conv_std_logic_vector(108267459,28); exponent <= '0'; WHEN "0111110010" => manhi <= conv_std_logic_vector(10508133,24); manlo <= conv_std_logic_vector(65972402,28); exponent <= '0'; WHEN "0111110011" => manhi <= conv_std_logic_vector(10534792,24); manlo <= conv_std_logic_vector(29405451,28); exponent <= '0'; WHEN "0111110100" => manhi <= conv_std_logic_vector(10561477,24); manlo <= conv_std_logic_vector(5391275,28); exponent <= '0'; WHEN "0111110101" => manhi <= conv_std_logic_vector(10588188,24); manlo <= conv_std_logic_vector(761213,28); exponent <= '0'; WHEN "0111110110" => manhi <= conv_std_logic_vector(10614925,24); manlo <= conv_std_logic_vector(22353276,28); exponent <= '0'; WHEN "0111110111" => manhi <= conv_std_logic_vector(10641688,24); manlo <= conv_std_logic_vector(77012158,28); exponent <= '0'; WHEN "0111111000" => manhi <= conv_std_logic_vector(10668477,24); manlo <= conv_std_logic_vector(171589240,28); exponent <= '0'; WHEN "0111111001" => manhi <= conv_std_logic_vector(10695293,24); manlo <= conv_std_logic_vector(44507139,28); exponent <= '0'; WHEN "0111111010" => manhi <= conv_std_logic_vector(10722134,24); manlo <= conv_std_logic_vector(239501544,28); exponent <= '0'; WHEN "0111111011" => manhi <= conv_std_logic_vector(10749002,24); manlo <= conv_std_logic_vector(226573024,28); exponent <= '0'; WHEN "0111111100" => manhi <= conv_std_logic_vector(10775897,24); manlo <= conv_std_logic_vector(12599777,28); exponent <= '0'; WHEN "0111111101" => manhi <= conv_std_logic_vector(10802817,24); manlo <= conv_std_logic_vector(141337630,28); exponent <= '0'; WHEN "0111111110" => manhi <= conv_std_logic_vector(10829764,24); manlo <= conv_std_logic_vector(82807315,28); exponent <= '0'; WHEN "0111111111" => manhi <= conv_std_logic_vector(10856737,24); manlo <= conv_std_logic_vector(112342665,28); exponent <= '0'; WHEN "1000000000" => manhi <= conv_std_logic_vector(10883736,24); manlo <= conv_std_logic_vector(236848796,28); exponent <= '0'; WHEN "1000000001" => manhi <= conv_std_logic_vector(10910762,24); manlo <= conv_std_logic_vector(194802116,28); exponent <= '0'; WHEN "1000000010" => manhi <= conv_std_logic_vector(10937814,24); manlo <= conv_std_logic_vector(261556696,28); exponent <= '0'; WHEN "1000000011" => manhi <= conv_std_logic_vector(10964893,24); manlo <= conv_std_logic_vector(175602458,28); exponent <= '0'; WHEN "1000000100" => manhi <= conv_std_logic_vector(10991998,24); manlo <= conv_std_logic_vector(212307000,28); exponent <= '0'; WHEN "1000000101" => manhi <= conv_std_logic_vector(11019130,24); manlo <= conv_std_logic_vector(110173782,28); exponent <= '0'; WHEN "1000000110" => manhi <= conv_std_logic_vector(11046288,24); manlo <= conv_std_logic_vector(144583954,28); exponent <= '0'; WHEN "1000000111" => manhi <= conv_std_logic_vector(11073473,24); manlo <= conv_std_logic_vector(54054542,28); exponent <= '0'; WHEN "1000001000" => manhi <= conv_std_logic_vector(11100684,24); manlo <= conv_std_logic_vector(113980276,28); exponent <= '0'; WHEN "1000001001" => manhi <= conv_std_logic_vector(11127922,24); manlo <= conv_std_logic_vector(62891774,28); exponent <= '0'; WHEN "1000001010" => manhi <= conv_std_logic_vector(11155186,24); manlo <= conv_std_logic_vector(176197372,28); exponent <= '0'; WHEN "1000001011" => manhi <= conv_std_logic_vector(11182477,24); manlo <= conv_std_logic_vector(192441306,28); exponent <= '0'; WHEN "1000001100" => manhi <= conv_std_logic_vector(11209795,24); manlo <= conv_std_logic_vector(118610088,28); exponent <= '0'; WHEN "1000001101" => manhi <= conv_std_logic_vector(11237139,24); manlo <= conv_std_logic_vector(230132514,28); exponent <= '0'; WHEN "1000001110" => manhi <= conv_std_logic_vector(11264510,24); manlo <= conv_std_logic_vector(265573296,28); exponent <= '0'; WHEN "1000001111" => manhi <= conv_std_logic_vector(11291908,24); manlo <= conv_std_logic_vector(231939446,28); exponent <= '0'; WHEN "1000010000" => manhi <= conv_std_logic_vector(11319333,24); manlo <= conv_std_logic_vector(136244820,28); exponent <= '0'; WHEN "1000010001" => manhi <= conv_std_logic_vector(11346784,24); manlo <= conv_std_logic_vector(253945584,28); exponent <= '0'; WHEN "1000010010" => manhi <= conv_std_logic_vector(11374263,24); manlo <= conv_std_logic_vector(55198395,28); exponent <= '0'; WHEN "1000010011" => manhi <= conv_std_logic_vector(11401768,24); manlo <= conv_std_logic_vector(83908598,28); exponent <= '0'; WHEN "1000010100" => manhi <= conv_std_logic_vector(11429300,24); manlo <= conv_std_logic_vector(78682048,28); exponent <= '0'; WHEN "1000010101" => manhi <= conv_std_logic_vector(11456859,24); manlo <= conv_std_logic_vector(46566930,28); exponent <= '0'; WHEN "1000010110" => manhi <= conv_std_logic_vector(11484444,24); manlo <= conv_std_logic_vector(263053774,28); exponent <= '0'; WHEN "1000010111" => manhi <= conv_std_logic_vector(11512057,24); manlo <= conv_std_logic_vector(198333637,28); exponent <= '0'; WHEN "1000011000" => manhi <= conv_std_logic_vector(11539697,24); manlo <= conv_std_logic_vector(127910840,28); exponent <= '0'; WHEN "1000011001" => manhi <= conv_std_logic_vector(11567364,24); manlo <= conv_std_logic_vector(58861158,28); exponent <= '0'; WHEN "1000011010" => manhi <= conv_std_logic_vector(11595057,24); manlo <= conv_std_logic_vector(266702732,28); exponent <= '0'; WHEN "1000011011" => manhi <= conv_std_logic_vector(11622778,24); manlo <= conv_std_logic_vector(221654258,28); exponent <= '0'; WHEN "1000011100" => manhi <= conv_std_logic_vector(11650526,24); manlo <= conv_std_logic_vector(199247725,28); exponent <= '0'; WHEN "1000011101" => manhi <= conv_std_logic_vector(11678301,24); manlo <= conv_std_logic_vector(206586600,28); exponent <= '0'; WHEN "1000011110" => manhi <= conv_std_logic_vector(11706103,24); manlo <= conv_std_logic_vector(250781292,28); exponent <= '0'; WHEN "1000011111" => manhi <= conv_std_logic_vector(11733933,24); manlo <= conv_std_logic_vector(70513697,28); exponent <= '0'; WHEN "1000100000" => manhi <= conv_std_logic_vector(11761789,24); manlo <= conv_std_logic_vector(209779039,28); exponent <= '0'; WHEN "1000100001" => manhi <= conv_std_logic_vector(11789673,24); manlo <= conv_std_logic_vector(138837672,28); exponent <= '0'; WHEN "1000100010" => manhi <= conv_std_logic_vector(11817584,24); manlo <= conv_std_logic_vector(133263292,28); exponent <= '0'; WHEN "1000100011" => manhi <= conv_std_logic_vector(11845522,24); manlo <= conv_std_logic_vector(200201109,28); exponent <= '0'; WHEN "1000100100" => manhi <= conv_std_logic_vector(11873488,24); manlo <= conv_std_logic_vector(78367858,28); exponent <= '0'; WHEN "1000100101" => manhi <= conv_std_logic_vector(11901481,24); manlo <= conv_std_logic_vector(43358178,28); exponent <= '0'; WHEN "1000100110" => manhi <= conv_std_logic_vector(11929501,24); manlo <= conv_std_logic_vector(102338242,28); exponent <= '0'; WHEN "1000100111" => manhi <= conv_std_logic_vector(11957548,24); manlo <= conv_std_logic_vector(262481228,28); exponent <= '0'; WHEN "1000101000" => manhi <= conv_std_logic_vector(11985623,24); manlo <= conv_std_logic_vector(262531864,28); exponent <= '0'; WHEN "1000101001" => manhi <= conv_std_logic_vector(12013726,24); manlo <= conv_std_logic_vector(109677352,28); exponent <= '0'; WHEN "1000101010" => manhi <= conv_std_logic_vector(12041856,24); manlo <= conv_std_logic_vector(79547371,28); exponent <= '0'; WHEN "1000101011" => manhi <= conv_std_logic_vector(12070013,24); manlo <= conv_std_logic_vector(179343172,28); exponent <= '0'; WHEN "1000101100" => manhi <= conv_std_logic_vector(12098198,24); manlo <= conv_std_logic_vector(147837587,28); exponent <= '0'; WHEN "1000101101" => manhi <= conv_std_logic_vector(12126410,24); manlo <= conv_std_logic_vector(260681402,28); exponent <= '0'; WHEN "1000101110" => manhi <= conv_std_logic_vector(12154650,24); manlo <= conv_std_logic_vector(256661542,28); exponent <= '0'; WHEN "1000101111" => manhi <= conv_std_logic_vector(12182918,24); manlo <= conv_std_logic_vector(143007443,28); exponent <= '0'; WHEN "1000110000" => manhi <= conv_std_logic_vector(12211213,24); manlo <= conv_std_logic_vector(195391062,28); exponent <= '0'; WHEN "1000110001" => manhi <= conv_std_logic_vector(12239536,24); manlo <= conv_std_logic_vector(152620513,28); exponent <= '0'; WHEN "1000110010" => manhi <= conv_std_logic_vector(12267887,24); manlo <= conv_std_logic_vector(21946444,28); exponent <= '0'; WHEN "1000110011" => manhi <= conv_std_logic_vector(12296265,24); manlo <= conv_std_logic_vector(79062042,28); exponent <= '0'; WHEN "1000110100" => manhi <= conv_std_logic_vector(12324671,24); manlo <= conv_std_logic_vector(62796676,28); exponent <= '0'; WHEN "1000110101" => manhi <= conv_std_logic_vector(12353104,24); manlo <= conv_std_logic_vector(248857722,28); exponent <= '0'; WHEN "1000110110" => manhi <= conv_std_logic_vector(12381566,24); manlo <= conv_std_logic_vector(107653293,28); exponent <= '0'; WHEN "1000110111" => manhi <= conv_std_logic_vector(12410055,24); manlo <= conv_std_logic_vector(183340440,28); exponent <= '0'; WHEN "1000111000" => manhi <= conv_std_logic_vector(12438572,24); manlo <= conv_std_logic_vector(214776964,28); exponent <= '0'; WHEN "1000111001" => manhi <= conv_std_logic_vector(12467117,24); manlo <= conv_std_logic_vector(209263248,28); exponent <= '0'; WHEN "1000111010" => manhi <= conv_std_logic_vector(12495690,24); manlo <= conv_std_logic_vector(174106806,28); exponent <= '0'; WHEN "1000111011" => manhi <= conv_std_logic_vector(12524291,24); manlo <= conv_std_logic_vector(116622293,28); exponent <= '0'; WHEN "1000111100" => manhi <= conv_std_logic_vector(12552920,24); manlo <= conv_std_logic_vector(44131512,28); exponent <= '0'; WHEN "1000111101" => manhi <= conv_std_logic_vector(12581576,24); manlo <= conv_std_logic_vector(232398874,28); exponent <= '0'; WHEN "1000111110" => manhi <= conv_std_logic_vector(12610261,24); manlo <= conv_std_logic_vector(151889582,28); exponent <= '0'; WHEN "1000111111" => manhi <= conv_std_logic_vector(12638974,24); manlo <= conv_std_logic_vector(78382378,28); exponent <= '0'; WHEN "1001000000" => manhi <= conv_std_logic_vector(12667715,24); manlo <= conv_std_logic_vector(19227718,28); exponent <= '0'; WHEN "1001000001" => manhi <= conv_std_logic_vector(12696483,24); manlo <= conv_std_logic_vector(250218700,28); exponent <= '0'; WHEN "1001000010" => manhi <= conv_std_logic_vector(12725280,24); manlo <= conv_std_logic_vector(241849240,28); exponent <= '0'; WHEN "1001000011" => manhi <= conv_std_logic_vector(12754106,24); manlo <= conv_std_logic_vector(1491364,28); exponent <= '0'; WHEN "1001000100" => manhi <= conv_std_logic_vector(12782959,24); manlo <= conv_std_logic_vector(73395209,28); exponent <= '0'; WHEN "1001000101" => manhi <= conv_std_logic_vector(12811840,24); manlo <= conv_std_logic_vector(196511758,28); exponent <= '0'; WHEN "1001000110" => manhi <= conv_std_logic_vector(12840750,24); manlo <= conv_std_logic_vector(109799208,28); exponent <= '0'; WHEN "1001000111" => manhi <= conv_std_logic_vector(12869688,24); manlo <= conv_std_logic_vector(89093893,28); exponent <= '0'; WHEN "1001001000" => manhi <= conv_std_logic_vector(12898654,24); manlo <= conv_std_logic_vector(141803923,28); exponent <= '0'; WHEN "1001001001" => manhi <= conv_std_logic_vector(12927649,24); manlo <= conv_std_logic_vector(6909187,28); exponent <= '0'; WHEN "1001001010" => manhi <= conv_std_logic_vector(12956671,24); manlo <= conv_std_logic_vector(228703191,28); exponent <= '0'; WHEN "1001001011" => manhi <= conv_std_logic_vector(12985723,24); manlo <= conv_std_logic_vector(9309409,28); exponent <= '0'; WHEN "1001001100" => manhi <= conv_std_logic_vector(13014802,24); manlo <= conv_std_logic_vector(161471314,28); exponent <= '0'; WHEN "1001001101" => manhi <= conv_std_logic_vector(13043910,24); manlo <= conv_std_logic_vector(155762363,28); exponent <= '0'; WHEN "1001001110" => manhi <= conv_std_logic_vector(13073046,24); manlo <= conv_std_logic_vector(268069656,28); exponent <= '0'; WHEN "1001001111" => manhi <= conv_std_logic_vector(13102211,24); manlo <= conv_std_logic_vector(237416659,28); exponent <= '0'; WHEN "1001010000" => manhi <= conv_std_logic_vector(13131405,24); manlo <= conv_std_logic_vector(71269584,28); exponent <= '0'; WHEN "1001010001" => manhi <= conv_std_logic_vector(13160627,24); manlo <= conv_std_logic_vector(45537394,28); exponent <= '0'; WHEN "1001010010" => manhi <= conv_std_logic_vector(13189877,24); manlo <= conv_std_logic_vector(167700897,28); exponent <= '0'; WHEN "1001010011" => manhi <= conv_std_logic_vector(13219156,24); manlo <= conv_std_logic_vector(176812753,28); exponent <= '0'; WHEN "1001010100" => manhi <= conv_std_logic_vector(13248464,24); manlo <= conv_std_logic_vector(80368396,28); exponent <= '0'; WHEN "1001010101" => manhi <= conv_std_logic_vector(13277800,24); manlo <= conv_std_logic_vector(154306039,28); exponent <= '0'; WHEN "1001010110" => manhi <= conv_std_logic_vector(13307165,24); manlo <= conv_std_logic_vector(137700312,28); exponent <= '0'; WHEN "1001010111" => manhi <= conv_std_logic_vector(13336559,24); manlo <= conv_std_logic_vector(38068641,28); exponent <= '0'; WHEN "1001011000" => manhi <= conv_std_logic_vector(13365981,24); manlo <= conv_std_logic_vector(131371250,28); exponent <= '0'; WHEN "1001011001" => manhi <= conv_std_logic_vector(13395432,24); manlo <= conv_std_logic_vector(156704806,28); exponent <= '0'; WHEN "1001011010" => manhi <= conv_std_logic_vector(13424912,24); manlo <= conv_std_logic_vector(121608790,28); exponent <= '0'; WHEN "1001011011" => manhi <= conv_std_logic_vector(13454421,24); manlo <= conv_std_logic_vector(33630048,28); exponent <= '0'; WHEN "1001011100" => manhi <= conv_std_logic_vector(13483958,24); manlo <= conv_std_logic_vector(168758257,28); exponent <= '0'; WHEN "1001011101" => manhi <= conv_std_logic_vector(13513524,24); manlo <= conv_std_logic_vector(266119562,28); exponent <= '0'; WHEN "1001011110" => manhi <= conv_std_logic_vector(13543120,24); manlo <= conv_std_logic_vector(64847498,28); exponent <= '0'; WHEN "1001011111" => manhi <= conv_std_logic_vector(13572744,24); manlo <= conv_std_logic_vector(109389360,28); exponent <= '0'; WHEN "1001100000" => manhi <= conv_std_logic_vector(13602397,24); manlo <= conv_std_logic_vector(138893481,28); exponent <= '0'; WHEN "1001100001" => manhi <= conv_std_logic_vector(13632079,24); manlo <= conv_std_logic_vector(160951056,28); exponent <= '0'; WHEN "1001100010" => manhi <= conv_std_logic_vector(13661790,24); manlo <= conv_std_logic_vector(183160698,28); exponent <= '0'; WHEN "1001100011" => manhi <= conv_std_logic_vector(13691530,24); manlo <= conv_std_logic_vector(213128447,28); exponent <= '0'; WHEN "1001100100" => manhi <= conv_std_logic_vector(13721299,24); manlo <= conv_std_logic_vector(258467771,28); exponent <= '0'; WHEN "1001100101" => manhi <= conv_std_logic_vector(13751098,24); manlo <= conv_std_logic_vector(58364122,28); exponent <= '0'; WHEN "1001100110" => manhi <= conv_std_logic_vector(13780925,24); manlo <= conv_std_logic_vector(157316766,28); exponent <= '0'; WHEN "1001100111" => manhi <= conv_std_logic_vector(13810782,24); manlo <= conv_std_logic_vector(26090597,28); exponent <= '0'; WHEN "1001101000" => manhi <= conv_std_logic_vector(13840667,24); manlo <= conv_std_logic_vector(209199796,28); exponent <= '0'; WHEN "1001101001" => manhi <= conv_std_logic_vector(13870582,24); manlo <= conv_std_logic_vector(177424185,28); exponent <= '0'; WHEN "1001101010" => manhi <= conv_std_logic_vector(13900526,24); manlo <= conv_std_logic_vector(206857431,28); exponent <= '0'; WHEN "1001101011" => manhi <= conv_std_logic_vector(13930500,24); manlo <= conv_std_logic_vector(36729770,28); exponent <= '0'; WHEN "1001101100" => manhi <= conv_std_logic_vector(13960502,24); manlo <= conv_std_logic_vector(211585297,28); exponent <= '0'; WHEN "1001101101" => manhi <= conv_std_logic_vector(13990534,24); manlo <= conv_std_logic_vector(202233780,28); exponent <= '0'; WHEN "1001101110" => manhi <= conv_std_logic_vector(14020596,24); manlo <= conv_std_logic_vector(16363400,28); exponent <= '0'; WHEN "1001101111" => manhi <= conv_std_logic_vector(14050686,24); manlo <= conv_std_logic_vector(198540768,28); exponent <= '0'; WHEN "1001110000" => manhi <= conv_std_logic_vector(14080806,24); manlo <= conv_std_logic_vector(219598184,28); exponent <= '0'; WHEN "1001110001" => manhi <= conv_std_logic_vector(14110956,24); manlo <= conv_std_logic_vector(87246388,28); exponent <= '0'; WHEN "1001110010" => manhi <= conv_std_logic_vector(14141135,24); manlo <= conv_std_logic_vector(77639113,28); exponent <= '0'; WHEN "1001110011" => manhi <= conv_std_logic_vector(14171343,24); manlo <= conv_std_logic_vector(198502173,28); exponent <= '0'; WHEN "1001110100" => manhi <= conv_std_logic_vector(14201581,24); manlo <= conv_std_logic_vector(189133475,28); exponent <= '0'; WHEN "1001110101" => manhi <= conv_std_logic_vector(14231849,24); manlo <= conv_std_logic_vector(57273941,28); exponent <= '0'; WHEN "1001110110" => manhi <= conv_std_logic_vector(14262146,24); manlo <= conv_std_logic_vector(79107508,28); exponent <= '0'; WHEN "1001110111" => manhi <= conv_std_logic_vector(14292472,24); manlo <= conv_std_logic_vector(262390229,28); exponent <= '0'; WHEN "1001111000" => manhi <= conv_std_logic_vector(14322829,24); manlo <= conv_std_logic_vector(78014825,28); exponent <= '0'; WHEN "1001111001" => manhi <= conv_std_logic_vector(14353215,24); manlo <= conv_std_logic_vector(70623424,28); exponent <= '0'; WHEN "1001111010" => manhi <= conv_std_logic_vector(14383630,24); manlo <= conv_std_logic_vector(247994836,28); exponent <= '0'; WHEN "1001111011" => manhi <= conv_std_logic_vector(14414076,24); manlo <= conv_std_logic_vector(81044559,28); exponent <= '0'; WHEN "1001111100" => manhi <= conv_std_logic_vector(14444551,24); manlo <= conv_std_logic_vector(114437521,28); exponent <= '0'; WHEN "1001111101" => manhi <= conv_std_logic_vector(14475056,24); manlo <= conv_std_logic_vector(87539900,28); exponent <= '0'; WHEN "1001111110" => manhi <= conv_std_logic_vector(14505591,24); manlo <= conv_std_logic_vector(8160950,28); exponent <= '0'; WHEN "1001111111" => manhi <= conv_std_logic_vector(14536155,24); manlo <= conv_std_logic_vector(152553012,28); exponent <= '0'; WHEN "1010000000" => manhi <= conv_std_logic_vector(14566749,24); manlo <= conv_std_logic_vector(260105152,28); exponent <= '0'; WHEN "1010000001" => manhi <= conv_std_logic_vector(14597374,24); manlo <= conv_std_logic_vector(70214083,28); exponent <= '0'; WHEN "1010000010" => manhi <= conv_std_logic_vector(14628028,24); manlo <= conv_std_logic_vector(127590534,28); exponent <= '0'; WHEN "1010000011" => manhi <= conv_std_logic_vector(14658712,24); manlo <= conv_std_logic_vector(171646531,28); exponent <= '0'; WHEN "1010000100" => manhi <= conv_std_logic_vector(14689426,24); manlo <= conv_std_logic_vector(210237219,28); exponent <= '0'; WHEN "1010000101" => manhi <= conv_std_logic_vector(14720170,24); manlo <= conv_std_logic_vector(251225419,28); exponent <= '0'; WHEN "1010000110" => manhi <= conv_std_logic_vector(14750945,24); manlo <= conv_std_logic_vector(34046180,28); exponent <= '0'; WHEN "1010000111" => manhi <= conv_std_logic_vector(14781749,24); manlo <= conv_std_logic_vector(103448606,28); exponent <= '0'; WHEN "1010001000" => manhi <= conv_std_logic_vector(14812583,24); manlo <= conv_std_logic_vector(198883134,28); exponent <= '0'; WHEN "1010001001" => manhi <= conv_std_logic_vector(14843448,24); manlo <= conv_std_logic_vector(59807901,28); exponent <= '0'; WHEN "1010001010" => manhi <= conv_std_logic_vector(14874342,24); manlo <= conv_std_logic_vector(230995129,28); exponent <= '0'; WHEN "1010001011" => manhi <= conv_std_logic_vector(14905267,24); manlo <= conv_std_logic_vector(183482934,28); exponent <= '0'; WHEN "1010001100" => manhi <= conv_std_logic_vector(14936222,24); manlo <= conv_std_logic_vector(193623526,28); exponent <= '0'; WHEN "1010001101" => manhi <= conv_std_logic_vector(14967208,24); manlo <= conv_std_logic_vector(905939,28); exponent <= '0'; WHEN "1010001110" => manhi <= conv_std_logic_vector(14998223,24); manlo <= conv_std_logic_vector(150133320,28); exponent <= '0'; WHEN "1010001111" => manhi <= conv_std_logic_vector(15029269,24); manlo <= conv_std_logic_vector(112374738,28); exponent <= '0'; WHEN "1010010000" => manhi <= conv_std_logic_vector(15060345,24); manlo <= conv_std_logic_vector(164013390,28); exponent <= '0'; WHEN "1010010001" => manhi <= conv_std_logic_vector(15091452,24); manlo <= conv_std_logic_vector(44569327,28); exponent <= '0'; WHEN "1010010010" => manhi <= conv_std_logic_vector(15122589,24); manlo <= conv_std_logic_vector(30441282,28); exponent <= '0'; WHEN "1010010011" => manhi <= conv_std_logic_vector(15153756,24); manlo <= conv_std_logic_vector(129600316,28); exponent <= '0'; WHEN "1010010100" => manhi <= conv_std_logic_vector(15184954,24); manlo <= conv_std_logic_vector(81589818,28); exponent <= '0'; WHEN "1010010101" => manhi <= conv_std_logic_vector(15216182,24); manlo <= conv_std_logic_vector(162831889,28); exponent <= '0'; WHEN "1010010110" => manhi <= conv_std_logic_vector(15247441,24); manlo <= conv_std_logic_vector(112885518,28); exponent <= '0'; WHEN "1010010111" => manhi <= conv_std_logic_vector(15278730,24); manlo <= conv_std_logic_vector(208188418,28); exponent <= '0'; WHEN "1010011000" => manhi <= conv_std_logic_vector(15310050,24); manlo <= conv_std_logic_vector(188315209,28); exponent <= '0'; WHEN "1010011001" => manhi <= conv_std_logic_vector(15341401,24); manlo <= conv_std_logic_vector(61283792,28); exponent <= '0'; WHEN "1010011010" => manhi <= conv_std_logic_vector(15372782,24); manlo <= conv_std_logic_vector(103555359,28); exponent <= '0'; WHEN "1010011011" => manhi <= conv_std_logic_vector(15404194,24); manlo <= conv_std_logic_vector(54728032,28); exponent <= '0'; WHEN "1010011100" => manhi <= conv_std_logic_vector(15435636,24); manlo <= conv_std_logic_vector(191278690,28); exponent <= '0'; WHEN "1010011101" => manhi <= conv_std_logic_vector(15467109,24); manlo <= conv_std_logic_vector(252821163,28); exponent <= '0'; WHEN "1010011110" => manhi <= conv_std_logic_vector(15498613,24); manlo <= conv_std_logic_vector(247412597,28); exponent <= '0'; WHEN "1010011111" => manhi <= conv_std_logic_vector(15530148,24); manlo <= conv_std_logic_vector(183118012,28); exponent <= '0'; WHEN "1010100000" => manhi <= conv_std_logic_vector(15561714,24); manlo <= conv_std_logic_vector(68010306,28); exponent <= '0'; WHEN "1010100001" => manhi <= conv_std_logic_vector(15593310,24); manlo <= conv_std_logic_vector(178605723,28); exponent <= '0'; WHEN "1010100010" => manhi <= conv_std_logic_vector(15624937,24); manlo <= conv_std_logic_vector(254557489,28); exponent <= '0'; WHEN "1010100011" => manhi <= conv_std_logic_vector(15656596,24); manlo <= conv_std_logic_vector(35526733,28); exponent <= '0'; WHEN "1010100100" => manhi <= conv_std_logic_vector(15688285,24); manlo <= conv_std_logic_vector(66488863,28); exponent <= '0'; WHEN "1010100101" => manhi <= conv_std_logic_vector(15720005,24); manlo <= conv_std_logic_vector(87120837,28); exponent <= '0'; WHEN "1010100110" => manhi <= conv_std_logic_vector(15751756,24); manlo <= conv_std_logic_vector(105542995,28); exponent <= '0'; WHEN "1010100111" => manhi <= conv_std_logic_vector(15783538,24); manlo <= conv_std_logic_vector(129883612,28); exponent <= '0'; WHEN "1010101000" => manhi <= conv_std_logic_vector(15815351,24); manlo <= conv_std_logic_vector(168278902,28); exponent <= '0'; WHEN "1010101001" => manhi <= conv_std_logic_vector(15847195,24); manlo <= conv_std_logic_vector(228873033,28); exponent <= '0'; WHEN "1010101010" => manhi <= conv_std_logic_vector(15879071,24); manlo <= conv_std_logic_vector(51382669,28); exponent <= '0'; WHEN "1010101011" => manhi <= conv_std_logic_vector(15910977,24); manlo <= conv_std_logic_vector(180838811,28); exponent <= '0'; WHEN "1010101100" => manhi <= conv_std_logic_vector(15942915,24); manlo <= conv_std_logic_vector(88538606,28); exponent <= '0'; WHEN "1010101101" => manhi <= conv_std_logic_vector(15974884,24); manlo <= conv_std_logic_vector(51093552,28); exponent <= '0'; WHEN "1010101110" => manhi <= conv_std_logic_vector(16006884,24); manlo <= conv_std_logic_vector(76687676,28); exponent <= '0'; WHEN "1010101111" => manhi <= conv_std_logic_vector(16038915,24); manlo <= conv_std_logic_vector(173513005,28); exponent <= '0'; WHEN "1010110000" => manhi <= conv_std_logic_vector(16070978,24); manlo <= conv_std_logic_vector(81334110,28); exponent <= '0'; WHEN "1010110001" => manhi <= conv_std_logic_vector(16103072,24); manlo <= conv_std_logic_vector(76794490,28); exponent <= '0'; WHEN "1010110010" => manhi <= conv_std_logic_vector(16135197,24); manlo <= conv_std_logic_vector(168110204,28); exponent <= '0'; WHEN "1010110011" => manhi <= conv_std_logic_vector(16167354,24); manlo <= conv_std_logic_vector(95069884,28); exponent <= '0'; WHEN "1010110100" => manhi <= conv_std_logic_vector(16199542,24); manlo <= conv_std_logic_vector(134341108,28); exponent <= '0'; WHEN "1010110101" => manhi <= conv_std_logic_vector(16231762,24); manlo <= conv_std_logic_vector(25728588,28); exponent <= '0'; WHEN "1010110110" => manhi <= conv_std_logic_vector(16264013,24); manlo <= conv_std_logic_vector(45915996,28); exponent <= '0'; WHEN "1010110111" => manhi <= conv_std_logic_vector(16296295,24); manlo <= conv_std_logic_vector(203159607,28); exponent <= '0'; WHEN "1010111000" => manhi <= conv_std_logic_vector(16328609,24); manlo <= conv_std_logic_vector(237288310,28); exponent <= '0'; WHEN "1010111001" => manhi <= conv_std_logic_vector(16360955,24); manlo <= conv_std_logic_vector(156574520,28); exponent <= '0'; WHEN "1010111010" => manhi <= conv_std_logic_vector(16393332,24); manlo <= conv_std_logic_vector(237734194,28); exponent <= '0'; WHEN "1010111011" => manhi <= conv_std_logic_vector(16425741,24); manlo <= conv_std_logic_vector(220620465,28); exponent <= '0'; WHEN "1010111100" => manhi <= conv_std_logic_vector(16458182,24); manlo <= conv_std_logic_vector(113530022,28); exponent <= '0'; WHEN "1010111101" => manhi <= conv_std_logic_vector(16490654,24); manlo <= conv_std_logic_vector(193203116,28); exponent <= '0'; WHEN "1010111110" => manhi <= conv_std_logic_vector(16523158,24); manlo <= conv_std_logic_vector(199517199,28); exponent <= '0'; WHEN "1010111111" => manhi <= conv_std_logic_vector(16555694,24); manlo <= conv_std_logic_vector(140793302,28); exponent <= '0'; WHEN "1011000000" => manhi <= conv_std_logic_vector(16588262,24); manlo <= conv_std_logic_vector(25360585,28); exponent <= '0'; WHEN "1011000001" => manhi <= conv_std_logic_vector(16620861,24); manlo <= conv_std_logic_vector(129991803,28); exponent <= '0'; WHEN "1011000010" => manhi <= conv_std_logic_vector(16653492,24); manlo <= conv_std_logic_vector(194596944,28); exponent <= '0'; WHEN "1011000011" => manhi <= conv_std_logic_vector(16686155,24); manlo <= conv_std_logic_vector(227529607,28); exponent <= '0'; WHEN "1011000100" => manhi <= conv_std_logic_vector(16718850,24); manlo <= conv_std_logic_vector(237151552,28); exponent <= '0'; WHEN "1011000101" => manhi <= conv_std_logic_vector(16751577,24); manlo <= conv_std_logic_vector(231832709,28); exponent <= '0'; WHEN "1011000110" => manhi <= conv_std_logic_vector(3560,24); manlo <= conv_std_logic_vector(109975592,28); exponent <= '1'; WHEN "1011000111" => manhi <= conv_std_logic_vector(19955,24); manlo <= conv_std_logic_vector(239164365,28); exponent <= '1'; WHEN "1011001000" => manhi <= conv_std_logic_vector(36367,24); manlo <= conv_std_logic_vector(105026731,28); exponent <= '1'; WHEN "1011001001" => manhi <= conv_std_logic_vector(52794,24); manlo <= conv_std_logic_vector(248634947,28); exponent <= '1'; WHEN "1011001010" => manhi <= conv_std_logic_vector(69238,24); manlo <= conv_std_logic_vector(137323551,28); exponent <= '1'; WHEN "1011001011" => manhi <= conv_std_logic_vector(85698,24); manlo <= conv_std_logic_vector(43737556,28); exponent <= '1'; WHEN "1011001100" => manhi <= conv_std_logic_vector(102173,24); manlo <= conv_std_logic_vector(240526091,28); exponent <= '1'; WHEN "1011001101" => manhi <= conv_std_logic_vector(118665,24); manlo <= conv_std_logic_vector(195036030,28); exponent <= '1'; WHEN "1011001110" => manhi <= conv_std_logic_vector(135173,24); manlo <= conv_std_logic_vector(179924739,28); exponent <= '1'; WHEN "1011001111" => manhi <= conv_std_logic_vector(151697,24); manlo <= conv_std_logic_vector(199418251,28); exponent <= '1'; WHEN "1011010000" => manhi <= conv_std_logic_vector(168237,24); manlo <= conv_std_logic_vector(257746730,28); exponent <= '1'; WHEN "1011010001" => manhi <= conv_std_logic_vector(184794,24); manlo <= conv_std_logic_vector(90709016,28); exponent <= '1'; WHEN "1011010010" => manhi <= conv_std_logic_vector(201366,24); manlo <= conv_std_logic_vector(239414453,28); exponent <= '1'; WHEN "1011010011" => manhi <= conv_std_logic_vector(217955,24); manlo <= conv_std_logic_vector(171234704,28); exponent <= '1'; WHEN "1011010100" => manhi <= conv_std_logic_vector(234560,24); manlo <= conv_std_logic_vector(158851944,28); exponent <= '1'; WHEN "1011010101" => manhi <= conv_std_logic_vector(251181,24); manlo <= conv_std_logic_vector(206517042,28); exponent <= '1'; WHEN "1011010110" => manhi <= conv_std_logic_vector(267819,24); manlo <= conv_std_logic_vector(50049563,28); exponent <= '1'; WHEN "1011010111" => manhi <= conv_std_logic_vector(284472,24); manlo <= conv_std_logic_vector(230579599,28); exponent <= '1'; WHEN "1011011000" => manhi <= conv_std_logic_vector(301142,24); manlo <= conv_std_logic_vector(215499577,28); exponent <= '1'; WHEN "1011011001" => manhi <= conv_std_logic_vector(317829,24); manlo <= conv_std_logic_vector(9077005,28); exponent <= '1'; WHEN "1011011010" => manhi <= conv_std_logic_vector(334531,24); manlo <= conv_std_logic_vector(152454469,28); exponent <= '1'; WHEN "1011011011" => manhi <= conv_std_logic_vector(351250,24); manlo <= conv_std_logic_vector(113036907,28); exponent <= '1'; WHEN "1011011100" => manhi <= conv_std_logic_vector(367985,24); manlo <= conv_std_logic_vector(163539801,28); exponent <= '1'; WHEN "1011011101" => manhi <= conv_std_logic_vector(384737,24); manlo <= conv_std_logic_vector(39811903,28); exponent <= '1'; WHEN "1011011110" => manhi <= conv_std_logic_vector(401505,24); manlo <= conv_std_logic_vector(14577065,28); exponent <= '1'; WHEN "1011011111" => manhi <= conv_std_logic_vector(418289,24); manlo <= conv_std_logic_vector(92127870,28); exponent <= '1'; WHEN "1011100000" => manhi <= conv_std_logic_vector(435090,24); manlo <= conv_std_logic_vector(8325641,28); exponent <= '1'; WHEN "1011100001" => manhi <= conv_std_logic_vector(451907,24); manlo <= conv_std_logic_vector(35906810,28); exponent <= '1'; WHEN "1011100010" => manhi <= conv_std_logic_vector(468740,24); manlo <= conv_std_logic_vector(179176556,28); exponent <= '1'; WHEN "1011100011" => manhi <= conv_std_logic_vector(485590,24); manlo <= conv_std_logic_vector(174008808,28); exponent <= '1'; WHEN "1011100100" => manhi <= conv_std_logic_vector(502457,24); manlo <= conv_std_logic_vector(24717160,28); exponent <= '1'; WHEN "1011100101" => manhi <= conv_std_logic_vector(519340,24); manlo <= conv_std_logic_vector(4054880,28); exponent <= '1'; WHEN "1011100110" => manhi <= conv_std_logic_vector(536239,24); manlo <= conv_std_logic_vector(116343996,28); exponent <= '1'; WHEN "1011100111" => manhi <= conv_std_logic_vector(553155,24); manlo <= conv_std_logic_vector(97475302,28); exponent <= '1'; WHEN "1011101000" => manhi <= conv_std_logic_vector(570087,24); manlo <= conv_std_logic_vector(220214735,28); exponent <= '1'; WHEN "1011101001" => manhi <= conv_std_logic_vector(587036,24); manlo <= conv_std_logic_vector(220461546,28); exponent <= '1'; WHEN "1011101010" => manhi <= conv_std_logic_vector(604002,24); manlo <= conv_std_logic_vector(102554681,28); exponent <= '1'; WHEN "1011101011" => manhi <= conv_std_logic_vector(620984,24); manlo <= conv_std_logic_vector(139272779,28); exponent <= '1'; WHEN "1011101100" => manhi <= conv_std_logic_vector(637983,24); manlo <= conv_std_logic_vector(66527812,28); exponent <= '1'; WHEN "1011101101" => manhi <= conv_std_logic_vector(654998,24); manlo <= conv_std_logic_vector(157106911,28); exponent <= '1'; WHEN "1011101110" => manhi <= conv_std_logic_vector(672030,24); manlo <= conv_std_logic_vector(146930546,28); exponent <= '1'; WHEN "1011101111" => manhi <= conv_std_logic_vector(689079,24); manlo <= conv_std_logic_vector(40358901,28); exponent <= '1'; WHEN "1011110000" => manhi <= conv_std_logic_vector(706144,24); manlo <= conv_std_logic_vector(110191873,28); exponent <= '1'; WHEN "1011110001" => manhi <= conv_std_logic_vector(723226,24); manlo <= conv_std_logic_vector(92362714,28); exponent <= '1'; WHEN "1011110010" => manhi <= conv_std_logic_vector(740324,24); manlo <= conv_std_logic_vector(259679855,28); exponent <= '1'; WHEN "1011110011" => manhi <= conv_std_logic_vector(757440,24); manlo <= conv_std_logic_vector(79649632,28); exponent <= '1'; WHEN "1011110100" => manhi <= conv_std_logic_vector(774572,24); manlo <= conv_std_logic_vector(93524482,28); exponent <= '1'; WHEN "1011110101" => manhi <= conv_std_logic_vector(791721,24); manlo <= conv_std_logic_vector(37254754,28); exponent <= '1'; WHEN "1011110110" => manhi <= conv_std_logic_vector(808886,24); manlo <= conv_std_logic_vector(183665996,28); exponent <= '1'; WHEN "1011110111" => manhi <= conv_std_logic_vector(826069,24); manlo <= conv_std_logic_vector(281674,28); exponent <= '1'; WHEN "1011111000" => manhi <= conv_std_logic_vector(843268,24); manlo <= conv_std_logic_vector(28371374,28); exponent <= '1'; WHEN "1011111001" => manhi <= conv_std_logic_vector(860484,24); manlo <= conv_std_logic_vector(3902612,28); exponent <= '1'; WHEN "1011111010" => manhi <= conv_std_logic_vector(877716,24); manlo <= conv_std_logic_vector(199718117,28); exponent <= '1'; WHEN "1011111011" => manhi <= conv_std_logic_vector(894966,24); manlo <= conv_std_logic_vector(83358555,28); exponent <= '1'; WHEN "1011111100" => manhi <= conv_std_logic_vector(912232,24); manlo <= conv_std_logic_vector(196110728,28); exponent <= '1'; WHEN "1011111101" => manhi <= conv_std_logic_vector(929516,24); manlo <= conv_std_logic_vector(5523929,28); exponent <= '1'; WHEN "1011111110" => manhi <= conv_std_logic_vector(946816,24); manlo <= conv_std_logic_vector(52893590,28); exponent <= '1'; WHEN "1011111111" => manhi <= conv_std_logic_vector(964133,24); manlo <= conv_std_logic_vector(74213103,28); exponent <= '1'; WHEN "1100000000" => manhi <= conv_std_logic_vector(981467,24); manlo <= conv_std_logic_vector(73915640,28); exponent <= '1'; WHEN "1100000001" => manhi <= conv_std_logic_vector(998818,24); manlo <= conv_std_logic_vector(56438704,28); exponent <= '1'; WHEN "1100000010" => manhi <= conv_std_logic_vector(1016186,24); manlo <= conv_std_logic_vector(26224136,28); exponent <= '1'; WHEN "1100000011" => manhi <= conv_std_logic_vector(1033570,24); manlo <= conv_std_logic_vector(256153571,28); exponent <= '1'; WHEN "1100000100" => manhi <= conv_std_logic_vector(1050972,24); manlo <= conv_std_logic_vector(213806620,28); exponent <= '1'; WHEN "1100000101" => manhi <= conv_std_logic_vector(1068391,24); manlo <= conv_std_logic_vector(172073612,28); exponent <= '1'; WHEN "1100000110" => manhi <= conv_std_logic_vector(1085827,24); manlo <= conv_std_logic_vector(135413771,28); exponent <= '1'; WHEN "1100000111" => manhi <= conv_std_logic_vector(1103280,24); manlo <= conv_std_logic_vector(108290679,28); exponent <= '1'; WHEN "1100001000" => manhi <= conv_std_logic_vector(1120750,24); manlo <= conv_std_logic_vector(95172278,28); exponent <= '1'; WHEN "1100001001" => manhi <= conv_std_logic_vector(1138237,24); manlo <= conv_std_logic_vector(100530876,28); exponent <= '1'; WHEN "1100001010" => manhi <= conv_std_logic_vector(1155741,24); manlo <= conv_std_logic_vector(128843150,28); exponent <= '1'; WHEN "1100001011" => manhi <= conv_std_logic_vector(1173262,24); manlo <= conv_std_logic_vector(184590152,28); exponent <= '1'; WHEN "1100001100" => manhi <= conv_std_logic_vector(1190801,24); manlo <= conv_std_logic_vector(3821855,28); exponent <= '1'; WHEN "1100001101" => manhi <= conv_std_logic_vector(1208356,24); manlo <= conv_std_logic_vector(127898983,28); exponent <= '1'; WHEN "1100001110" => manhi <= conv_std_logic_vector(1225929,24); manlo <= conv_std_logic_vector(24444823,28); exponent <= '1'; WHEN "1100001111" => manhi <= conv_std_logic_vector(1243518,24); manlo <= conv_std_logic_vector(234828877,28); exponent <= '1'; WHEN "1100010000" => manhi <= conv_std_logic_vector(1261125,24); manlo <= conv_std_logic_vector(226683218,28); exponent <= '1'; WHEN "1100010001" => manhi <= conv_std_logic_vector(1278750,24); manlo <= conv_std_logic_vector(4515229,28); exponent <= '1'; WHEN "1100010010" => manhi <= conv_std_logic_vector(1296391,24); manlo <= conv_std_logic_vector(109707612,28); exponent <= '1'; WHEN "1100010011" => manhi <= conv_std_logic_vector(1314050,24); manlo <= conv_std_logic_vector(9905652,28); exponent <= '1'; WHEN "1100010100" => manhi <= conv_std_logic_vector(1331725,24); manlo <= conv_std_logic_vector(246500869,28); exponent <= '1'; WHEN "1100010101" => manhi <= conv_std_logic_vector(1349419,24); manlo <= conv_std_logic_vector(18711921,28); exponent <= '1'; WHEN "1100010110" => manhi <= conv_std_logic_vector(1367129,24); manlo <= conv_std_logic_vector(136374624,28); exponent <= '1'; WHEN "1100010111" => manhi <= conv_std_logic_vector(1384857,24); manlo <= conv_std_logic_vector(67151939,28); exponent <= '1'; WHEN "1100011000" => manhi <= conv_std_logic_vector(1402602,24); manlo <= conv_std_logic_vector(84017623,28); exponent <= '1'; WHEN "1100011001" => manhi <= conv_std_logic_vector(1420364,24); manlo <= conv_std_logic_vector(191514413,28); exponent <= '1'; WHEN "1100011010" => manhi <= conv_std_logic_vector(1438144,24); manlo <= conv_std_logic_vector(125754028,28); exponent <= '1'; WHEN "1100011011" => manhi <= conv_std_logic_vector(1455941,24); manlo <= conv_std_logic_vector(159723541,28); exponent <= '1'; WHEN "1100011100" => manhi <= conv_std_logic_vector(1473756,24); manlo <= conv_std_logic_vector(29543561,28); exponent <= '1'; WHEN "1100011101" => manhi <= conv_std_logic_vector(1491588,24); manlo <= conv_std_logic_vector(8210062,28); exponent <= '1'; WHEN "1100011110" => manhi <= conv_std_logic_vector(1509437,24); manlo <= conv_std_logic_vector(100288013,28); exponent <= '1'; WHEN "1100011111" => manhi <= conv_std_logic_vector(1527304,24); manlo <= conv_std_logic_vector(41911392,28); exponent <= '1'; WHEN "1100100000" => manhi <= conv_std_logic_vector(1545188,24); manlo <= conv_std_logic_vector(106089552,28); exponent <= '1'; WHEN "1100100001" => manhi <= conv_std_logic_vector(1563090,24); manlo <= conv_std_logic_vector(28965402,28); exponent <= '1'; WHEN "1100100010" => manhi <= conv_std_logic_vector(1581009,24); manlo <= conv_std_logic_vector(83557236,28); exponent <= '1'; WHEN "1100100011" => manhi <= conv_std_logic_vector(1598946,24); manlo <= conv_std_logic_vector(6016916,28); exponent <= '1'; WHEN "1100100100" => manhi <= conv_std_logic_vector(1616900,24); manlo <= conv_std_logic_vector(69371695,28); exponent <= '1'; WHEN "1100100101" => manhi <= conv_std_logic_vector(1634872,24); manlo <= conv_std_logic_vector(9782402,28); exponent <= '1'; WHEN "1100100110" => manhi <= conv_std_logic_vector(1652861,24); manlo <= conv_std_logic_vector(100285270,28); exponent <= '1'; WHEN "1100100111" => manhi <= conv_std_logic_vector(1670868,24); manlo <= conv_std_logic_vector(77050112,28); exponent <= '1'; WHEN "1100101000" => manhi <= conv_std_logic_vector(1688892,24); manlo <= conv_std_logic_vector(213122155,28); exponent <= '1'; WHEN "1100101001" => manhi <= conv_std_logic_vector(1706934,24); manlo <= conv_std_logic_vector(244680216,28); exponent <= '1'; WHEN "1100101010" => manhi <= conv_std_logic_vector(1724994,24); manlo <= conv_std_logic_vector(176343080,28); exponent <= '1'; WHEN "1100101011" => manhi <= conv_std_logic_vector(1743072,24); manlo <= conv_std_logic_vector(12734040,28); exponent <= '1'; WHEN "1100101100" => manhi <= conv_std_logic_vector(1761167,24); manlo <= conv_std_logic_vector(26916364,28); exponent <= '1'; WHEN "1100101101" => manhi <= conv_std_logic_vector(1779279,24); manlo <= conv_std_logic_vector(223522388,28); exponent <= '1'; WHEN "1100101110" => manhi <= conv_std_logic_vector(1797410,24); manlo <= conv_std_logic_vector(70318058,28); exponent <= '1'; WHEN "1100101111" => manhi <= conv_std_logic_vector(1815558,24); manlo <= conv_std_logic_vector(108815677,28); exponent <= '1'; WHEN "1100110000" => manhi <= conv_std_logic_vector(1833724,24); manlo <= conv_std_logic_vector(75225715,28); exponent <= '1'; WHEN "1100110001" => manhi <= conv_std_logic_vector(1851907,24); manlo <= conv_std_logic_vector(242634090,28); exponent <= '1'; WHEN "1100110010" => manhi <= conv_std_logic_vector(1870109,24); manlo <= conv_std_logic_vector(78824900,28); exponent <= '1'; WHEN "1100110011" => manhi <= conv_std_logic_vector(1888328,24); manlo <= conv_std_logic_vector(125328613,28); exponent <= '1'; WHEN "1100110100" => manhi <= conv_std_logic_vector(1906565,24); manlo <= conv_std_logic_vector(118373881,28); exponent <= '1'; WHEN "1100110101" => manhi <= conv_std_logic_vector(1924820,24); manlo <= conv_std_logic_vector(62629370,28); exponent <= '1'; WHEN "1100110110" => manhi <= conv_std_logic_vector(1943092,24); manlo <= conv_std_logic_vector(231203763,28); exponent <= '1'; WHEN "1100110111" => manhi <= conv_std_logic_vector(1961383,24); manlo <= conv_std_logic_vector(91903942,28); exponent <= '1'; WHEN "1100111000" => manhi <= conv_std_logic_vector(1979691,24); manlo <= conv_std_logic_vector(186283181,28); exponent <= '1'; WHEN "1100111001" => manhi <= conv_std_logic_vector(1998017,24); manlo <= conv_std_logic_vector(250592964,28); exponent <= '1'; WHEN "1100111010" => manhi <= conv_std_logic_vector(2016362,24); manlo <= conv_std_logic_vector(21089351,28); exponent <= '1'; WHEN "1100111011" => manhi <= conv_std_logic_vector(2034724,24); manlo <= conv_std_logic_vector(39339357,28); exponent <= '1'; WHEN "1100111100" => manhi <= conv_std_logic_vector(2053104,24); manlo <= conv_std_logic_vector(41608216,28); exponent <= '1'; WHEN "1100111101" => manhi <= conv_std_logic_vector(2071502,24); manlo <= conv_std_logic_vector(32601209,28); exponent <= '1'; WHEN "1100111110" => manhi <= conv_std_logic_vector(2089918,24); manlo <= conv_std_logic_vector(17028217,28); exponent <= '1'; WHEN "1100111111" => manhi <= conv_std_logic_vector(2108351,24); manlo <= conv_std_logic_vector(268039176,28); exponent <= '1'; WHEN "1101000000" => manhi <= conv_std_logic_vector(2126803,24); manlo <= conv_std_logic_vector(253482264,28); exponent <= '1'; WHEN "1101000001" => manhi <= conv_std_logic_vector(2145273,24); manlo <= conv_std_logic_vector(246516634,28); exponent <= '1'; WHEN "1101000010" => manhi <= conv_std_logic_vector(2163761,24); manlo <= conv_std_logic_vector(251870600,28); exponent <= '1'; WHEN "1101000011" => manhi <= conv_std_logic_vector(2182268,24); manlo <= conv_std_logic_vector(5841640,28); exponent <= '1'; WHEN "1101000100" => manhi <= conv_std_logic_vector(2200792,24); manlo <= conv_std_logic_vector(50038222,28); exponent <= '1'; WHEN "1101000101" => manhi <= conv_std_logic_vector(2219334,24); manlo <= conv_std_logic_vector(120767079,28); exponent <= '1'; WHEN "1101000110" => manhi <= conv_std_logic_vector(2237894,24); manlo <= conv_std_logic_vector(222775030,28); exponent <= '1'; WHEN "1101000111" => manhi <= conv_std_logic_vector(2256473,24); manlo <= conv_std_logic_vector(92378075,28); exponent <= '1'; WHEN "1101001000" => manhi <= conv_std_logic_vector(2275070,24); manlo <= conv_std_logic_vector(2767772,28); exponent <= '1'; WHEN "1101001001" => manhi <= conv_std_logic_vector(2293684,24); manlo <= conv_std_logic_vector(227140324,28); exponent <= '1'; WHEN "1101001010" => manhi <= conv_std_logic_vector(2312317,24); manlo <= conv_std_logic_vector(233390216,28); exponent <= '1'; WHEN "1101001011" => manhi <= conv_std_logic_vector(2330969,24); manlo <= conv_std_logic_vector(26287503,28); exponent <= '1'; WHEN "1101001100" => manhi <= conv_std_logic_vector(2349638,24); manlo <= conv_std_logic_vector(147477811,28); exponent <= '1'; WHEN "1101001101" => manhi <= conv_std_logic_vector(2368326,24); manlo <= conv_std_logic_vector(64869610,28); exponent <= '1'; WHEN "1101001110" => manhi <= conv_std_logic_vector(2387032,24); manlo <= conv_std_logic_vector(51682404,28); exponent <= '1'; WHEN "1101001111" => manhi <= conv_std_logic_vector(2405756,24); manlo <= conv_std_logic_vector(112704917,28); exponent <= '1'; WHEN "1101010000" => manhi <= conv_std_logic_vector(2424498,24); manlo <= conv_std_logic_vector(252730552,28); exponent <= '1'; WHEN "1101010001" => manhi <= conv_std_logic_vector(2443259,24); manlo <= conv_std_logic_vector(208121938,28); exponent <= '1'; WHEN "1101010010" => manhi <= conv_std_logic_vector(2462038,24); manlo <= conv_std_logic_vector(252117306,28); exponent <= '1'; WHEN "1101010011" => manhi <= conv_std_logic_vector(2480836,24); manlo <= conv_std_logic_vector(121088666,28); exponent <= '1'; WHEN "1101010100" => manhi <= conv_std_logic_vector(2499652,24); manlo <= conv_std_logic_vector(88283637,28); exponent <= '1'; WHEN "1101010101" => manhi <= conv_std_logic_vector(2518486,24); manlo <= conv_std_logic_vector(158519085,28); exponent <= '1'; WHEN "1101010110" => manhi <= conv_std_logic_vector(2537339,24); manlo <= conv_std_logic_vector(68181124,28); exponent <= '1'; WHEN "1101010111" => manhi <= conv_std_logic_vector(2556210,24); manlo <= conv_std_logic_vector(90531494,28); exponent <= '1'; WHEN "1101011000" => manhi <= conv_std_logic_vector(2575099,24); manlo <= conv_std_logic_vector(230401190,28); exponent <= '1'; WHEN "1101011001" => manhi <= conv_std_logic_vector(2594007,24); manlo <= conv_std_logic_vector(224190477,28); exponent <= '1'; WHEN "1101011010" => manhi <= conv_std_logic_vector(2612934,24); manlo <= conv_std_logic_vector(76739795,28); exponent <= '1'; WHEN "1101011011" => manhi <= conv_std_logic_vector(2631879,24); manlo <= conv_std_logic_vector(61329773,28); exponent <= '1'; WHEN "1101011100" => manhi <= conv_std_logic_vector(2650842,24); manlo <= conv_std_logic_vector(182810317,28); exponent <= '1'; WHEN "1101011101" => manhi <= conv_std_logic_vector(2669824,24); manlo <= conv_std_logic_vector(177600614,28); exponent <= '1'; WHEN "1101011110" => manhi <= conv_std_logic_vector(2688825,24); manlo <= conv_std_logic_vector(50560052,28); exponent <= '1'; WHEN "1101011111" => manhi <= conv_std_logic_vector(2707844,24); manlo <= conv_std_logic_vector(74988222,28); exponent <= '1'; WHEN "1101100000" => manhi <= conv_std_logic_vector(2726881,24); manlo <= conv_std_logic_vector(255754012,28); exponent <= '1'; WHEN "1101100001" => manhi <= conv_std_logic_vector(2745938,24); manlo <= conv_std_logic_vector(60860155,28); exponent <= '1'; WHEN "1101100010" => manhi <= conv_std_logic_vector(2765013,24); manlo <= conv_std_logic_vector(32055969,28); exponent <= '1'; WHEN "1101100011" => manhi <= conv_std_logic_vector(2784106,24); manlo <= conv_std_logic_vector(174224628,28); exponent <= '1'; WHEN "1101100100" => manhi <= conv_std_logic_vector(2803218,24); manlo <= conv_std_logic_vector(223818618,28); exponent <= '1'; WHEN "1101100101" => manhi <= conv_std_logic_vector(2822349,24); manlo <= conv_std_logic_vector(185730660,28); exponent <= '1'; WHEN "1101100110" => manhi <= conv_std_logic_vector(2841499,24); manlo <= conv_std_logic_vector(64858254,28); exponent <= '1'; WHEN "1101100111" => manhi <= conv_std_logic_vector(2860667,24); manlo <= conv_std_logic_vector(134539142,28); exponent <= '1'; WHEN "1101101000" => manhi <= conv_std_logic_vector(2879854,24); manlo <= conv_std_logic_vector(131244940,28); exponent <= '1'; WHEN "1101101001" => manhi <= conv_std_logic_vector(2899060,24); manlo <= conv_std_logic_vector(59887520,28); exponent <= '1'; WHEN "1101101010" => manhi <= conv_std_logic_vector(2918284,24); manlo <= conv_std_logic_vector(193819006,28); exponent <= '1'; WHEN "1101101011" => manhi <= conv_std_logic_vector(2937528,24); manlo <= conv_std_logic_vector(1089957,28); exponent <= '1'; WHEN "1101101100" => manhi <= conv_std_logic_vector(2956790,24); manlo <= conv_std_logic_vector(23497566,28); exponent <= '1'; WHEN "1101101101" => manhi <= conv_std_logic_vector(2976070,24); manlo <= conv_std_logic_vector(265972927,28); exponent <= '1'; WHEN "1101101110" => manhi <= conv_std_logic_vector(2995370,24); manlo <= conv_std_logic_vector(196581040,28); exponent <= '1'; WHEN "1101101111" => manhi <= conv_std_logic_vector(3014689,24); manlo <= conv_std_logic_vector(88698094,28); exponent <= '1'; WHEN "1101110000" => manhi <= conv_std_logic_vector(3034026,24); manlo <= conv_std_logic_vector(215705108,28); exponent <= '1'; WHEN "1101110001" => manhi <= conv_std_logic_vector(3053383,24); manlo <= conv_std_logic_vector(45681562,28); exponent <= '1'; WHEN "1101110010" => manhi <= conv_std_logic_vector(3072758,24); manlo <= conv_std_logic_vector(120453600,28); exponent <= '1'; WHEN "1101110011" => manhi <= conv_std_logic_vector(3092152,24); manlo <= conv_std_logic_vector(176545836,28); exponent <= '1'; WHEN "1101110100" => manhi <= conv_std_logic_vector(3111565,24); manlo <= conv_std_logic_vector(218923189,28); exponent <= '1'; WHEN "1101110101" => manhi <= conv_std_logic_vector(3130997,24); manlo <= conv_std_logic_vector(252555427,28); exponent <= '1'; WHEN "1101110110" => manhi <= conv_std_logic_vector(3150449,24); manlo <= conv_std_logic_vector(13981719,28); exponent <= '1'; WHEN "1101110111" => manhi <= conv_std_logic_vector(3169919,24); manlo <= conv_std_logic_vector(45052462,28); exponent <= '1'; WHEN "1101111000" => manhi <= conv_std_logic_vector(3189408,24); manlo <= conv_std_logic_vector(82316549,28); exponent <= '1'; WHEN "1101111001" => manhi <= conv_std_logic_vector(3208916,24); manlo <= conv_std_logic_vector(130763202,28); exponent <= '1'; WHEN "1101111010" => manhi <= conv_std_logic_vector(3228443,24); manlo <= conv_std_logic_vector(195386513,28); exponent <= '1'; WHEN "1101111011" => manhi <= conv_std_logic_vector(3247990,24); manlo <= conv_std_logic_vector(12750002,28); exponent <= '1'; WHEN "1101111100" => manhi <= conv_std_logic_vector(3267555,24); manlo <= conv_std_logic_vector(124728439,28); exponent <= '1'; WHEN "1101111101" => manhi <= conv_std_logic_vector(3287139,24); manlo <= conv_std_logic_vector(267895114,28); exponent <= '1'; WHEN "1101111110" => manhi <= conv_std_logic_vector(3306743,24); manlo <= conv_std_logic_vector(178828213,28); exponent <= '1'; WHEN "1101111111" => manhi <= conv_std_logic_vector(3326366,24); manlo <= conv_std_logic_vector(130981732,28); exponent <= '1'; WHEN "1110000000" => manhi <= conv_std_logic_vector(3346008,24); manlo <= conv_std_logic_vector(129379112,28); exponent <= '1'; WHEN "1110000001" => manhi <= conv_std_logic_vector(3365669,24); manlo <= conv_std_logic_vector(179048704,28); exponent <= '1'; WHEN "1110000010" => manhi <= conv_std_logic_vector(3385350,24); manlo <= conv_std_logic_vector(16588318,28); exponent <= '1'; WHEN "1110000011" => manhi <= conv_std_logic_vector(3405049,24); manlo <= conv_std_logic_vector(183907046,28); exponent <= '1'; WHEN "1110000100" => manhi <= conv_std_logic_vector(3424768,24); manlo <= conv_std_logic_vector(149177079,28); exponent <= '1'; WHEN "1110000101" => manhi <= conv_std_logic_vector(3444506,24); manlo <= conv_std_logic_vector(185881906,28); exponent <= '1'; WHEN "1110000110" => manhi <= conv_std_logic_vector(3464264,24); manlo <= conv_std_logic_vector(30639033,28); exponent <= '1'; WHEN "1110000111" => manhi <= conv_std_logic_vector(3484040,24); manlo <= conv_std_logic_vector(225377274,28); exponent <= '1'; WHEN "1110001000" => manhi <= conv_std_logic_vector(3503836,24); manlo <= conv_std_logic_vector(238288557,28); exponent <= '1'; WHEN "1110001001" => manhi <= conv_std_logic_vector(3523652,24); manlo <= conv_std_logic_vector(74440673,28); exponent <= '1'; WHEN "1110001010" => manhi <= conv_std_logic_vector(3543487,24); manlo <= conv_std_logic_vector(7341816,28); exponent <= '1'; WHEN "1110001011" => manhi <= conv_std_logic_vector(3563341,24); manlo <= conv_std_logic_vector(42069684,28); exponent <= '1'; WHEN "1110001100" => manhi <= conv_std_logic_vector(3583214,24); manlo <= conv_std_logic_vector(183706934,28); exponent <= '1'; WHEN "1110001101" => manhi <= conv_std_logic_vector(3603107,24); manlo <= conv_std_logic_vector(168905734,28); exponent <= '1'; WHEN "1110001110" => manhi <= conv_std_logic_vector(3623020,24); manlo <= conv_std_logic_vector(2758677,28); exponent <= '1'; WHEN "1110001111" => manhi <= conv_std_logic_vector(3642951,24); manlo <= conv_std_logic_vector(227234245,28); exponent <= '1'; WHEN "1110010000" => manhi <= conv_std_logic_vector(3662903,24); manlo <= conv_std_logic_vector(42128622,28); exponent <= '1'; WHEN "1110010001" => manhi <= conv_std_logic_vector(3682873,24); manlo <= conv_std_logic_vector(257855711,28); exponent <= '1'; WHEN "1110010010" => manhi <= conv_std_logic_vector(3702864,24); manlo <= conv_std_logic_vector(74221670,28); exponent <= '1'; WHEN "1110010011" => manhi <= conv_std_logic_vector(3722874,24); manlo <= conv_std_logic_vector(33214933,28); exponent <= '1'; WHEN "1110010100" => manhi <= conv_std_logic_vector(3742903,24); manlo <= conv_std_logic_vector(139958020,28); exponent <= '1'; WHEN "1110010101" => manhi <= conv_std_logic_vector(3762952,24); manlo <= conv_std_logic_vector(131143002,28); exponent <= '1'; WHEN "1110010110" => manhi <= conv_std_logic_vector(3783021,24); manlo <= conv_std_logic_vector(11902416,28); exponent <= '1'; WHEN "1110010111" => manhi <= conv_std_logic_vector(3803109,24); manlo <= conv_std_logic_vector(55809266,28); exponent <= '1'; WHEN "1110011000" => manhi <= conv_std_logic_vector(3823216,24); manlo <= conv_std_logic_vector(268006125,28); exponent <= '1'; WHEN "1110011001" => manhi <= conv_std_logic_vector(3843344,24); manlo <= conv_std_logic_vector(116769675,28); exponent <= '1'; WHEN "1110011010" => manhi <= conv_std_logic_vector(3863491,24); manlo <= conv_std_logic_vector(144123451,28); exponent <= '1'; WHEN "1110011011" => manhi <= conv_std_logic_vector(3883658,24); manlo <= conv_std_logic_vector(86789657,28); exponent <= '1'; WHEN "1110011100" => manhi <= conv_std_logic_vector(3903844,24); manlo <= conv_std_logic_vector(218366446,28); exponent <= '1'; WHEN "1110011101" => manhi <= conv_std_logic_vector(3924051,24); manlo <= conv_std_logic_vector(7150648,28); exponent <= '1'; WHEN "1110011110" => manhi <= conv_std_logic_vector(3944276,24); manlo <= conv_std_logic_vector(263621422,28); exponent <= '1'; WHEN "1110011111" => manhi <= conv_std_logic_vector(3964522,24); manlo <= conv_std_logic_vector(187650244,28); exponent <= '1'; WHEN "1110100000" => manhi <= conv_std_logic_vector(3984788,24); manlo <= conv_std_logic_vector(52855476,28); exponent <= '1'; WHEN "1110100001" => manhi <= conv_std_logic_vector(4005073,24); manlo <= conv_std_logic_vector(132860541,28); exponent <= '1'; WHEN "1110100010" => manhi <= conv_std_logic_vector(4025378,24); manlo <= conv_std_logic_vector(164423019,28); exponent <= '1'; WHEN "1110100011" => manhi <= conv_std_logic_vector(4045703,24); manlo <= conv_std_logic_vector(152741021,28); exponent <= '1'; WHEN "1110100100" => manhi <= conv_std_logic_vector(4066048,24); manlo <= conv_std_logic_vector(103017737,28); exponent <= '1'; WHEN "1110100101" => manhi <= conv_std_logic_vector(4086413,24); manlo <= conv_std_logic_vector(20461438,28); exponent <= '1'; WHEN "1110100110" => manhi <= conv_std_logic_vector(4106797,24); manlo <= conv_std_logic_vector(178720944,28); exponent <= '1'; WHEN "1110100111" => manhi <= conv_std_logic_vector(4127202,24); manlo <= conv_std_logic_vector(46143798,28); exponent <= '1'; WHEN "1110101000" => manhi <= conv_std_logic_vector(4147626,24); manlo <= conv_std_logic_vector(164824464,28); exponent <= '1'; WHEN "1110101001" => manhi <= conv_std_logic_vector(4168071,24); manlo <= conv_std_logic_vector(3120689,28); exponent <= '1'; WHEN "1110101010" => manhi <= conv_std_logic_vector(4188535,24); manlo <= conv_std_logic_vector(103137152,28); exponent <= '1'; WHEN "1110101011" => manhi <= conv_std_logic_vector(4209019,24); manlo <= conv_std_logic_vector(201677275,28); exponent <= '1'; WHEN "1110101100" => manhi <= conv_std_logic_vector(4229524,24); manlo <= conv_std_logic_vector(35549602,28); exponent <= '1'; WHEN "1110101101" => manhi <= conv_std_logic_vector(4250048,24); manlo <= conv_std_logic_vector(146874166,28); exponent <= '1'; WHEN "1110101110" => manhi <= conv_std_logic_vector(4270593,24); manlo <= conv_std_logic_vector(4034305,28); exponent <= '1'; WHEN "1110101111" => manhi <= conv_std_logic_vector(4291157,24); manlo <= conv_std_logic_vector(149160317,28); exponent <= '1'; WHEN "1110110000" => manhi <= conv_std_logic_vector(4311742,24); manlo <= conv_std_logic_vector(50645812,28); exponent <= '1'; WHEN "1110110001" => manhi <= conv_std_logic_vector(4332346,24); manlo <= conv_std_logic_vector(250631368,28); exponent <= '1'; WHEN "1110110010" => manhi <= conv_std_logic_vector(4352971,24); manlo <= conv_std_logic_vector(217520889,28); exponent <= '1'; WHEN "1110110011" => manhi <= conv_std_logic_vector(4373616,24); manlo <= conv_std_logic_vector(225029798,28); exponent <= '1'; WHEN "1110110100" => manhi <= conv_std_logic_vector(4394282,24); manlo <= conv_std_logic_vector(10007770,28); exponent <= '1'; WHEN "1110110101" => manhi <= conv_std_logic_vector(4414967,24); manlo <= conv_std_logic_vector(114616005,28); exponent <= '1'; WHEN "1110110110" => manhi <= conv_std_logic_vector(4435673,24); manlo <= conv_std_logic_vector(7279052,28); exponent <= '1'; WHEN "1110110111" => manhi <= conv_std_logic_vector(4456398,24); manlo <= conv_std_logic_vector(230168458,28); exponent <= '1'; WHEN "1110111000" => manhi <= conv_std_logic_vector(4477144,24); manlo <= conv_std_logic_vector(251719124,28); exponent <= '1'; WHEN "1110111001" => manhi <= conv_std_logic_vector(4497911,24); manlo <= conv_std_logic_vector(77242046,28); exponent <= '1'; WHEN "1110111010" => manhi <= conv_std_logic_vector(4518697,24); manlo <= conv_std_logic_vector(248924323,28); exponent <= '1'; WHEN "1110111011" => manhi <= conv_std_logic_vector(4539504,24); manlo <= conv_std_logic_vector(235216422,28); exponent <= '1'; WHEN "1110111100" => manhi <= conv_std_logic_vector(4560332,24); manlo <= conv_std_logic_vector(41444923,28); exponent <= '1'; WHEN "1110111101" => manhi <= conv_std_logic_vector(4581179,24); manlo <= conv_std_logic_vector(209812522,28); exponent <= '1'; WHEN "1110111110" => manhi <= conv_std_logic_vector(4602047,24); manlo <= conv_std_logic_vector(208785300,28); exponent <= '1'; WHEN "1110111111" => manhi <= conv_std_logic_vector(4622936,24); manlo <= conv_std_logic_vector(43705464,28); exponent <= '1'; WHEN "1111000000" => manhi <= conv_std_logic_vector(4643844,24); manlo <= conv_std_logic_vector(256791352,28); exponent <= '1'; WHEN "1111000001" => manhi <= conv_std_logic_vector(4664774,24); manlo <= conv_std_logic_vector(48089250,28); exponent <= '1'; WHEN "1111000010" => manhi <= conv_std_logic_vector(4685723,24); manlo <= conv_std_logic_vector(228263405,28); exponent <= '1'; WHEN "1111000011" => manhi <= conv_std_logic_vector(4706693,24); manlo <= conv_std_logic_vector(265806023,28); exponent <= '1'; WHEN "1111000100" => manhi <= conv_std_logic_vector(4727684,24); manlo <= conv_std_logic_vector(166085460,28); exponent <= '1'; WHEN "1111000101" => manhi <= conv_std_logic_vector(4748695,24); manlo <= conv_std_logic_vector(202910772,28); exponent <= '1'; WHEN "1111000110" => manhi <= conv_std_logic_vector(4769727,24); manlo <= conv_std_logic_vector(113225356,28); exponent <= '1'; WHEN "1111000111" => manhi <= conv_std_logic_vector(4790779,24); manlo <= conv_std_logic_vector(170848774,28); exponent <= '1'; WHEN "1111001000" => manhi <= conv_std_logic_vector(4811852,24); manlo <= conv_std_logic_vector(112734938,28); exponent <= '1'; WHEN "1111001001" => manhi <= conv_std_logic_vector(4832945,24); manlo <= conv_std_logic_vector(212713936,28); exponent <= '1'; WHEN "1111001010" => manhi <= conv_std_logic_vector(4854059,24); manlo <= conv_std_logic_vector(207750218,28); exponent <= '1'; WHEN "1111001011" => manhi <= conv_std_logic_vector(4875194,24); manlo <= conv_std_logic_vector(103248961,28); exponent <= '1'; WHEN "1111001100" => manhi <= conv_std_logic_vector(4896349,24); manlo <= conv_std_logic_vector(173056083,28); exponent <= '1'; WHEN "1111001101" => manhi <= conv_std_logic_vector(4917525,24); manlo <= conv_std_logic_vector(154151876,28); exponent <= '1'; WHEN "1111001110" => manhi <= conv_std_logic_vector(4938722,24); manlo <= conv_std_logic_vector(51957376,28); exponent <= '1'; WHEN "1111001111" => manhi <= conv_std_logic_vector(4959939,24); manlo <= conv_std_logic_vector(140334376,28); exponent <= '1'; WHEN "1111010000" => manhi <= conv_std_logic_vector(4981177,24); manlo <= conv_std_logic_vector(156279056,28); exponent <= '1'; WHEN "1111010001" => manhi <= conv_std_logic_vector(5002436,24); manlo <= conv_std_logic_vector(105228360,28); exponent <= '1'; WHEN "1111010010" => manhi <= conv_std_logic_vector(5023715,24); manlo <= conv_std_logic_vector(261060000,28); exponent <= '1'; WHEN "1111010011" => manhi <= conv_std_logic_vector(5045016,24); manlo <= conv_std_logic_vector(92350636,28); exponent <= '1'; WHEN "1111010100" => manhi <= conv_std_logic_vector(5066337,24); manlo <= conv_std_logic_vector(141424076,28); exponent <= '1'; WHEN "1111010101" => manhi <= conv_std_logic_vector(5087679,24); manlo <= conv_std_logic_vector(145303087,28); exponent <= '1'; WHEN "1111010110" => manhi <= conv_std_logic_vector(5109042,24); manlo <= conv_std_logic_vector(109451226,28); exponent <= '1'; WHEN "1111010111" => manhi <= conv_std_logic_vector(5130426,24); manlo <= conv_std_logic_vector(39337386,28); exponent <= '1'; WHEN "1111011000" => manhi <= conv_std_logic_vector(5151830,24); manlo <= conv_std_logic_vector(208871261,28); exponent <= '1'; WHEN "1111011001" => manhi <= conv_std_logic_vector(5173256,24); manlo <= conv_std_logic_vector(86661526,28); exponent <= '1'; WHEN "1111011010" => manhi <= conv_std_logic_vector(5194702,24); manlo <= conv_std_logic_vector(215064032,28); exponent <= '1'; WHEN "1111011011" => manhi <= conv_std_logic_vector(5216170,24); manlo <= conv_std_logic_vector(62698166,28); exponent <= '1'; WHEN "1111011100" => manhi <= conv_std_logic_vector(5237658,24); manlo <= conv_std_logic_vector(171930504,28); exponent <= '1'; WHEN "1111011101" => manhi <= conv_std_logic_vector(5259168,24); manlo <= conv_std_logic_vector(11391165,28); exponent <= '1'; WHEN "1111011110" => manhi <= conv_std_logic_vector(5280698,24); manlo <= conv_std_logic_vector(123457470,28); exponent <= '1'; WHEN "1111011111" => manhi <= conv_std_logic_vector(5302249,24); manlo <= conv_std_logic_vector(245205748,28); exponent <= '1'; WHEN "1111100000" => manhi <= conv_std_logic_vector(5323822,24); manlo <= conv_std_logic_vector(113717718,28); exponent <= '1'; WHEN "1111100001" => manhi <= conv_std_logic_vector(5345416,24); manlo <= conv_std_logic_vector(2951399,28); exponent <= '1'; WHEN "1111100010" => manhi <= conv_std_logic_vector(5367030,24); manlo <= conv_std_logic_vector(186870204,28); exponent <= '1'; WHEN "1111100011" => manhi <= conv_std_logic_vector(5388666,24); manlo <= conv_std_logic_vector(134136582,28); exponent <= '1'; WHEN "1111100100" => manhi <= conv_std_logic_vector(5410323,24); manlo <= conv_std_logic_vector(118724754,28); exponent <= '1'; WHEN "1111100101" => manhi <= conv_std_logic_vector(5432001,24); manlo <= conv_std_logic_vector(146178900,28); exponent <= '1'; WHEN "1111100110" => manhi <= conv_std_logic_vector(5453700,24); manlo <= conv_std_logic_vector(222048612,28); exponent <= '1'; WHEN "1111100111" => manhi <= conv_std_logic_vector(5475421,24); manlo <= conv_std_logic_vector(83453453,28); exponent <= '1'; WHEN "1111101000" => manhi <= conv_std_logic_vector(5497163,24); manlo <= conv_std_logic_vector(4389322,28); exponent <= '1'; WHEN "1111101001" => manhi <= conv_std_logic_vector(5518925,24); manlo <= conv_std_logic_vector(258857552,28); exponent <= '1'; WHEN "1111101010" => manhi <= conv_std_logic_vector(5540710,24); manlo <= conv_std_logic_vector(47123091,28); exponent <= '1'; WHEN "1111101011" => manhi <= conv_std_logic_vector(5562515,24); manlo <= conv_std_logic_vector(180069064,28); exponent <= '1'; WHEN "1111101100" => manhi <= conv_std_logic_vector(5584342,24); manlo <= conv_std_logic_vector(126406768,28); exponent <= '1'; WHEN "1111101101" => manhi <= conv_std_logic_vector(5606190,24); manlo <= conv_std_logic_vector(160159320,28); exponent <= '1'; WHEN "1111101110" => manhi <= conv_std_logic_vector(5628060,24); manlo <= conv_std_logic_vector(18484384,28); exponent <= '1'; WHEN "1111101111" => manhi <= conv_std_logic_vector(5649950,24); manlo <= conv_std_logic_vector(243851457,28); exponent <= '1'; WHEN "1111110000" => manhi <= conv_std_logic_vector(5671863,24); manlo <= conv_std_logic_vector(36558227,28); exponent <= '1'; WHEN "1111110001" => manhi <= conv_std_logic_vector(5693796,24); manlo <= conv_std_logic_vector(207520592,28); exponent <= '1'; WHEN "1111110010" => manhi <= conv_std_logic_vector(5715751,24); manlo <= conv_std_logic_vector(225482653,28); exponent <= '1'; WHEN "1111110011" => manhi <= conv_std_logic_vector(5737728,24); manlo <= conv_std_logic_vector(96064906,28); exponent <= '1'; WHEN "1111110100" => manhi <= conv_std_logic_vector(5759726,24); manlo <= conv_std_logic_vector(93328797,28); exponent <= '1'; WHEN "1111110101" => manhi <= conv_std_logic_vector(5781745,24); manlo <= conv_std_logic_vector(222905812,28); exponent <= '1'; WHEN "1111110110" => manhi <= conv_std_logic_vector(5803786,24); manlo <= conv_std_logic_vector(221997482,28); exponent <= '1'; WHEN "1111110111" => manhi <= conv_std_logic_vector(5825849,24); manlo <= conv_std_logic_vector(96246303,28); exponent <= '1'; WHEN "1111111000" => manhi <= conv_std_logic_vector(5847933,24); manlo <= conv_std_logic_vector(119735740,28); exponent <= '1'; WHEN "1111111001" => manhi <= conv_std_logic_vector(5870039,24); manlo <= conv_std_logic_vector(29683863,28); exponent <= '1'; WHEN "1111111010" => manhi <= conv_std_logic_vector(5892166,24); manlo <= conv_std_logic_vector(100185179,28); exponent <= '1'; WHEN "1111111011" => manhi <= conv_std_logic_vector(5914315,24); manlo <= conv_std_logic_vector(68468812,28); exponent <= '1'; WHEN "1111111100" => manhi <= conv_std_logic_vector(5936485,24); manlo <= conv_std_logic_vector(208640332,28); exponent <= '1'; WHEN "1111111101" => manhi <= conv_std_logic_vector(5958677,24); manlo <= conv_std_logic_vector(257939938,28); exponent <= '1'; WHEN "1111111110" => manhi <= conv_std_logic_vector(5980891,24); manlo <= conv_std_logic_vector(222048827,28); exponent <= '1'; WHEN "1111111111" => manhi <= conv_std_logic_vector(6003127,24); manlo <= conv_std_logic_vector(106653752,28); exponent <= '1'; WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= '0'; END CASE; END PROCESS; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_cos_s5.vhd	10	397588	----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_cos_s5 -- VHDL created on Tue Mar 12 15:57:58 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_cos_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_cos_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0); signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0); signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0); signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0); signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0); signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0); signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0); signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0); signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0); signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0); signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0); signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0); signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0); signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0); signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic; signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic; signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0); signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0); signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0); signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0); signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0); signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0); signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0); signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0); signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0); signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0); signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0); signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0); signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0); signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0); signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0); signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0); signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0); signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0); signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0); signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0); signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0); signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0); signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0); signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0); signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0); signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0); signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0); signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0); signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0); signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0); signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0); signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0); signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0); signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0); signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0); signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0); signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0); signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0); signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0); signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0); signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0); signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0); signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0); signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0); signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0); signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0); signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0); signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0); signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0); signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0); signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0); signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0); signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0); signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0); signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0); signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0); signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0); signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0); signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic; signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true; signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic; signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic; signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true; signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true; signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0); signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0); signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0); signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0); signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true; signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true; signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true; signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0); signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0); signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0); signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0); signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0); signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0); signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0); signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0); signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0); signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0); signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0); signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0); signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0); signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0); signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0); signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0); signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0); signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0); signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0); signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0); signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0); signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0); signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0); signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0); signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0); signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0); signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0); signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0); signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0); signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0); signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0); signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0); signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0); signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0); signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0); signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0); signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0); signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0); signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0); signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0); signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0); signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0); signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0); signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0); signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0); signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0); signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0); signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0); signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0); signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0); signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0); signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0); signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0); signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0); signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0); signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0); signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0); signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0); signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0); signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0); signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0); signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0); signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0); signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0); signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0); signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0); signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0); signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0); signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0); signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0); signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0); signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0); signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0); signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0); signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0); signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0); signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0); signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0); signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0); signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0); signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0); signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0); signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0); signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0); signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0); signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0); signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0); signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0); signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0); signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0); signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0); signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0); signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0); signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0); signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0); signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0); signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0); signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0); signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0); signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0); signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0); signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0); signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0); signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0); signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0); signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0); signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0); signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0); signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0); signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0); signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0); signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0); signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0); signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0); signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0); signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0); signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0); signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0); signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0); signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0); signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0); signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0); signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0); signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0); signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0); signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0); signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0); signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0); signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0); signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0); signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0); signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0); signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0); signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0); signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0); signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0); signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0); signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0); signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0); signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0); signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0); signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0); signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0); signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0); signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0); signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0); signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0); signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0); signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0); signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0); signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0); signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0); signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0); signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0); signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0); signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0); signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0); signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0); signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0); signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0); signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); begin --xIn(GPIN,3)@0 --GND(CONSTANT,0) GND_q <= "0"; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010"; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q); ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0"; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q; END IF; END IF; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b; --expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0 expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0); expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0); --R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0 R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b; --expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0 expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0); expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866) -- every=1, low=0, high=10, step=1, init=1 ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10; ELSE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4)); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q) BEGIN CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q; WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 11, width_b => 8, widthad_b => 4, numwords_b => 11, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq, address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa, data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia ); ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0); --zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184) zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000"; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b); --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842) -- every=1, low=0, high=1, step=1, init=1 ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1)); --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q) BEGIN CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 32, widthad_a => 1, numwords_a => 2, width_b => 32, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq, address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa, data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia ); ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0); --fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4 fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0); fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0); --oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4 oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b; --prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4 prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q); prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0); --reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b; END IF; END IF; END PROCESS; --cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22) cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011"; --expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0 expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b); expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q); expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b)); expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0); --expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0 expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0); expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0); --reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0 reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1 rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0'); rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0'); rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q; rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 38, widthad_a => 8, numwords_a => 140, width_b => 38, widthad_b => 8, numwords_b => 140, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0, clock0 => clk, address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab, -- data_b => (others => '0'), q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq, address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa, data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia ); rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset; rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0); --reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3 reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q; END IF; END IF; END PROCESS; --rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1 rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0'); rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0'); rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q; rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 140, width_b => 40, widthad_b => 8, numwords_b => 140, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0, clock0 => clk, address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab, -- data_b => (others => '0'), q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq, address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa, data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia ); rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset; rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0); --reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3 reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q; END IF; END IF; END PROCESS; --os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4 os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q; --prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4 prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q); prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54); --reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5 prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b); prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q; prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q; prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr); END IF; END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1; END IF; END IF; END PROCESS; --ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8 ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 1 ) PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9 prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4 prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0); prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27); --reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5 prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b); prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q; prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q; prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr); END IF; END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8 prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000"; prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4 prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0); prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0); --reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5 prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b); prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q; prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q; prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr); END IF; END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8 prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q; prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8 prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b)); END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9 prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b)); prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0); --multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9 multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0); multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0); --multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9 multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b; multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46); --rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9 rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b; rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14); --reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9 reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10 vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q; vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q; vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0"; --ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10 ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11 reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q; END IF; END IF; END PROCESS; --cstAllZwE_uid28_fpCosPiTest(CONSTANT,27) cstAllZwE_uid28_fpCosPiTest_q <= "00000000"; --vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9 vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0); vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0); --mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179) mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11"; --cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9 cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q; --reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9 reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10 vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q) BEGIN CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q; WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10 rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8); --vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10 vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q; vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1"; ELSE vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11 ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153) leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000"; --vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10 vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0); vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0); --reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10 reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10 reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11 vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q) BEGIN CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11 rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4); --vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11 vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0"; --reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11 reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167) leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00"; --vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11 vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0); vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0); --vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11 vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b) BEGIN CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b; WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b; WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11 rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2); --vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11 vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1"; ELSE vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11 vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0); vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0); --reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11 reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11 reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12 vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q) BEGIN CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12 rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1); --vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12 vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q; vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0"; --r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12 r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q; --biasM1_uid60_fpCosPiTest(CONSTANT,59) biasM1_uid60_fpCosPiTest_q <= "01111110"; --expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12 expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q); expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q); expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b)); expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0); --expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12 expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0); expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0); --reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12 reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0 xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q; xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0'; xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0); xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b)); END IF; END IF; END PROCESS; xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10); --ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1 ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13 finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q; finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q) BEGIN CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q; WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13 ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111"; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q); ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0"; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816) -- every=1, low=0, high=7, step=1, init=1 ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3)); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q; WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 3, numwords_a => 8, width_b => 23, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq, address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa, data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia ); ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0); --ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146) ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000"; --fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14 fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q; --LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13 LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0); LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0); --leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13 leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q; --X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9 X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0); X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0); --ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923) ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9 ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305) leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000"; --leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12 leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q; --X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9 X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0); X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0); --ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922) ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 60, depth => 1 ) PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9 ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 60, depth => 2 ) PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12 leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q; --X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9 X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0); X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0); --ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921) ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 68, depth => 1 ) PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9 ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 68, depth => 2 ) PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12 leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q; --ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924) ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 76, depth => 1 ) PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9 ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 76, depth => 2 ) PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12 leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q; leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3); --leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12 leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b; leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q) BEGIN CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q; WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12 LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0); LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0); --leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316) leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000"; --leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12 leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q; --reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12 reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12 LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0); LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0); --leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12 leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; --reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12 reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12 LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0); LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0); --leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12 leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; --reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12 reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12 reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12 leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12 reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13 leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q; leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q) BEGIN CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q; WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q; WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q; WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q; WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12 leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12 ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13 leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q; leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q) BEGIN CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13 fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0); fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25); --reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13 reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1 ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14 finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q; finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q) BEGIN CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q; WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14 RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q; --expXRR_uid34_fpCosPiTest(BITSELECT,33)@14 expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0); expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50); --cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23) cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000"; --cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14 cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q; cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0'; cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0); cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b)); cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11); --exp_uid11_fpCosPiTest(BITSELECT,10)@0 exp_uid11_fpCosPiTest_in <= a(30 downto 0); exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23); --cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0 cosXIsOne_uid36_fpCosPiTest_cin <= GND_q; cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0'; cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0); cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b)); cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10); --ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0 ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 14 ) PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14 cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q; cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n; cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b; --ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14 ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --VCC(CONSTANT,1) VCC_q <= "1"; --InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17 InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q; InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvCosXOne_uid92_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a; END IF; END PROCESS; --X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15 X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0); X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0); --leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159) leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000"; --leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15 leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q; --X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15 X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0); X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0); --leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15 leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q; --X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15 X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0); X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0); --leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15 leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; --cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24) cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000"; --fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14 fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0); fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0); --ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14 ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 50, depth => 1 ) PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15 oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q; --extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15 extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q; --fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14 fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b); fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q); fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b)); fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0); --fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14 fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0); fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0); --leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14 leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b; leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2); --reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14 reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15 leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q; leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q) BEGIN CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q; WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q; WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q; WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q; WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15 LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0); LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0); --ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15 ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 62, depth => 1 ) PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170) leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000"; --leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16 leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15 LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0); LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0); --ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15 ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 63, depth => 1 ) PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16 leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15 LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0); LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0); --ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15 ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16 leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q; --reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15 reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14 leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0); leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0); --ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14 ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15 reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16 leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q; leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q) BEGIN CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q; WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q; WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q; WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q; WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid44_fpCosPiTest(BITSELECT,43)@16 y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0); y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1); --ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16 ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 63, depth => 2 ) PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16 reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b; END IF; END IF; END PROCESS; --pad_one_uid49_fpCosPiTest(BITJOIN,48)@16 pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q); --reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16 reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q; END IF; END IF; END PROCESS; --oneMinusY_uid49_fpCosPiTest(SUB,49)@17 oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q); oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q); oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b)); oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0); --reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17 reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q; END IF; END IF; END PROCESS; --cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18 cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q; cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0'; cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0); cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b)); cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67); --InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18 InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c; InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a; --intXParity_uid43_fpCosPiTest(BITSELECT,42)@16 intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q; intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64); --ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16 ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17 yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q; yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0"; --ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17 ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18 InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q; InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a; --signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18 signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q; signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q; signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q; signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q; signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRCond2_uid95_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d; END IF; END IF; END PROCESS; --InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18 InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q; InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a; --signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18 signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q; signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q; signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c; signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q; signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRCond1_uid100_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d; END IF; END IF; END PROCESS; --signR_uid101_fpCosPiTest(LOGICAL,100)@19 signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q; signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q; signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b; --cstAllZWF_uid7_fpCosPiTest(CONSTANT,6) cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000"; --frac_uid13_fpCosPiTest(BITSELECT,12)@0 frac_uid13_fpCosPiTest_in <= a(22 downto 0); frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0); --fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0 fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b; fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q; fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0"; --cstAllOWE_uid6_fpCosPiTest(CONSTANT,5) cstAllOWE_uid6_fpCosPiTest_q <= "11111111"; --expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0 expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b; expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q; expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0"; --exc_I_uid15_fpCosPiTest(LOGICAL,14)@0 exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q; exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q; exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b; --ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0 ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 18 ) PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18 InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q; InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_I_uid102_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a; END IF; END PROCESS; --InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0 InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q; InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a; --exc_N_uid17_fpCosPiTest(LOGICAL,16)@0 exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q; exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q; exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b; --InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0 InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q; InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_N_uid103_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a; END IF; END PROCESS; --ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1 ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 18 ) PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19 signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q; signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q; signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q; signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c; --ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19 ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 16 ) PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --cstBias_uid22_fpCosPiTest(CONSTANT,21) cstBias_uid22_fpCosPiTest_q <= "01111111"; --oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17 oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0); oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0); --reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17 reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18 ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay GENERIC MAP ( width => 62, depth => 1 ) PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --yBottom_uid54_fpCosPiTest(BITSELECT,53)@16 yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0); yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0); --reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16 reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17 ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 62, depth => 2 ) PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18 reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q; END IF; END IF; END PROCESS; --z_uid55_fpCosPiTest(MUX,54)@19 z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q; z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q) BEGIN CASE z_uid55_fpCosPiTest_s IS WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q; WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q; WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid64_fpCosPiTest(BITSELECT,63)@19 zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q; zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54); --reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19 reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20 memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q; memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 8, numwords_a => 256, width_b => 13, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq, address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa, data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia ); memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset; memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0); --reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22 reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19 zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0); zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36); --yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19 yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b; yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5); --reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19 reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b; END IF; END IF; END PROCESS; --ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925) ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay GENERIC MAP ( width => 13, depth => 1 ) PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20 ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 13, depth => 2 ) PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23 prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b); prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0'); prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0'); prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q; prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q; prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26 prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q; prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12); --highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26 highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b; highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1); --ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20 ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23 memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q; memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq, address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa, data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia ); memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset; memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0); --reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25 reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26 sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q); sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b); sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b)); sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0); --lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26 lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0); --s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26 s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b; --reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26 reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b); --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100"; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q); ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0"; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b; --reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19 reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928) -- every=1, low=0, high=4, step=1, init=1 ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4; ELSE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3)); --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 3, numwords_a => 5, width_b => 18, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia ); ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0); --prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27 prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b); prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0'); prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0'); prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q; prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q; prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41)); END IF; END IF; END PROCESS; prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30 prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q; prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17); --highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30 highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b; highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2); --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b); --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b; --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia ); ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26 reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27 memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q; memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq, address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa, data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia ); memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset; memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0); --reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29 reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30 sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q); sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b); sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b)); sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0); --lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30 lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0); lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0); --s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30 s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b; --fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30 fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0); fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5); --reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30 reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010"; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q); ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0"; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b; --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b); --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b; --X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19 X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0); X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0); --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 14, depth => 1 ) PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 14, widthad_a => 1, numwords_a => 2, width_b => 14, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq, address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa, data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia ); ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0); --leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220) leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23 leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q; --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b); --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b; --vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19 vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0); vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0); --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19 ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 30, depth => 1 ) PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 1, numwords_a => 2, width_b => 30, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq, address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa, data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia ); ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0); --zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176) zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23 leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q; --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b); --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b; --X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19 X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0); X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0); --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 46, depth => 1 ) PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 46, widthad_a => 1, numwords_a => 2, width_b => 46, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq, address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa, data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia ); ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0); --leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23 leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q; --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b); --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b; --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 62, depth => 1 ) PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 62, widthad_a => 1, numwords_a => 2, width_b => 62, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq, address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa, data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia ); ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0); --rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19 rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q; rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30); --vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19 vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b; vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q; vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1"; ELSE vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20 ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset ); --cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20 cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q; --ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19 ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20 vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q; vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q) BEGIN CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q; WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q; WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20 rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q; rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16); --vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20 vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b; vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q; vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0"; --reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20 reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21 ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20 vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0); vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0); --vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20 vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q; vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b) BEGIN CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b; WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b; WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20 rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q; rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8); --reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20 reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21 vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q; vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q; vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0"; --ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21 ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20 vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0); vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0); --reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20 reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21 vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q; vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q) BEGIN CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q; WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21 rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q; rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4); --vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21 vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b; vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1"; ELSE vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21 vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0); vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0); --reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21 reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21 reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22 vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q; vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q) BEGIN CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q; WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22 rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q; rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2); --vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22 vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b; vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0"; --vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22 vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0); vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0); --vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22 vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q; vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b) BEGIN CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b; WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b; WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22 rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q; rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1); --vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22 vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b; vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q; vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0"; --r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22 r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q; --leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22 leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q; leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4); --reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22 reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23 leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q; leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q) BEGIN CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q; WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q; WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q; WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q; WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23 LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0); LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0); --ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23 ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 50, depth => 1 ) PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24 leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23 LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0); LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0); --ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23 ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 54, depth => 1 ) PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24 leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q; --LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23 LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0); LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0); --ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23 ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 58, depth => 1 ) PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24 leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; --reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23 reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22 leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0); leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2); --ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22 ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23 reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24 leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q; leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q) BEGIN CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q; WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q; WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q; WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q; WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24 LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0); LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0); --ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24 ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 59, depth => 1 ) PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25 leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24 LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0); LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0); --ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24 ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 60, depth => 1 ) PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25 leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24 LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0); LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0); --ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24 ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 61, depth => 1 ) PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25 leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q; --reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24 reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22 leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0); leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0); --ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22 ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 2 ) PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24 reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25 leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q; leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q) BEGIN CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q; WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q; WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q; WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q; WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --p_uid59_fpCosPiTest(BITSELECT,58)@25 p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q; p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954) -- every=1, low=0, high=2, step=1, init=1 ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2; ELSE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2)); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 2, numwords_a => 3, width_b => 26, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq, address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa, data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia ); ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0); --reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30 reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q; END IF; END IF; END PROCESS; --mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31 mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b); mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0'); mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0'); mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q; mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q; mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr); END IF; END IF; END PROCESS; mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1; END IF; END IF; END PROCESS; --normBit_uid69_fpCosPiTest(BITSELECT,68)@34 normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q; normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51); --rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34 rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b; --reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22 reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 6, depth => 1 ) PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 6, widthad_a => 3, numwords_a => 8, width_b => 6, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq, address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa, data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia ); ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0); --expHardCase_uid61_fpCosPiTest(SUB,60)@33 expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q); expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q); expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b)); expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0); --expP_uid62_fpCosPiTest(BITSELECT,61)@33 expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0); expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0); --reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33 reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b; END IF; END IF; END PROCESS; --highRes_uid70_fpCosPiTest(BITSELECT,69)@34 highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0); highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27); --lowRes_uid71_fpCosPiTest(BITSELECT,70)@34 lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0); lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26); --fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34 fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b; fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b) BEGIN CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b; WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34 expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q; --expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34 expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q); expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q); expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b)); expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0); --expRComp_uid78_fpCosPiTest(BITSELECT,77)@34 expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0); expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24); --reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34 reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b); --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101"; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q); ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0"; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b; --ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0 ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 17 ) PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14 ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16 reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q; END IF; END IF; END PROCESS; --InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16 InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q; InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a; END IF; END PROCESS; --InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0 InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n; InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a; --ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0 ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 17 ) PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45) cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000"; --half_uid47_fpCosPiTest(BITJOIN,46)@17 half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q; --yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17 yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q; yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q; yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0"; --yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17 yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q; yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q; yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q; yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c; --excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0 excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q; excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q; excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b; --ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0 ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 17 ) PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --join_uid86_fpCosPiTest(BITJOIN,85)@17 join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q; --expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17 expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q; --reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17 reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q; END IF; END IF; END PROCESS; --expSelector_uid88_fpCosPiTest(LOOKUP,87)@18 expSelector_uid88_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSelector_uid88_fpCosPiTest_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01"; WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01"; WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01"; WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN OTHERS => expSelector_uid88_fpCosPiTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829) -- every=1, low=0, high=13, step=1, init=1 ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13; ELSE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4)); --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q; WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 4, numwords_a => 14, width_b => 2, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq, address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa, data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia ); ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0); --expRPostExc_uid90_fpCosPiTest(MUX,89)@35 expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q; expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q) BEGIN CASE expRPostExc_uid90_fpCosPiTest_s IS WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q; WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q; WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q; WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q; WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --cstNaNwF_uid30_fpCosPiTest(CONSTANT,29) cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001"; --fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34 fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0); fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1); --reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34 reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b); --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b; --reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17 reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q; END IF; END IF; END PROCESS; --reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14 reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n; END IF; END IF; END PROCESS; --ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15 ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17 reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q; END IF; END IF; END PROCESS; --reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17 reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q; END IF; END IF; END PROCESS; --excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18 excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q; excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q; excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q; excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c; --join_uid84_fpCosPiTest(BITJOIN,83)@18 join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q; --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 4, numwords_a => 14, width_b => 2, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq, address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa, data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia ); ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34 reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q; END IF; END IF; END PROCESS; --fracRPostExc_uid85_fpCosPiTest(MUX,84)@35 fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q; fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q) BEGIN CASE fracRPostExc_uid85_fpCosPiTest_s IS WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q; WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q; WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q; WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q; WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --cosXR_uid105_fpCosPiTest(BITJOIN,104)@35 cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q; --xOut(GPOUT,4)@35 q <= cosXR_uid105_fpCosPiTest_q; end normal;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/dp_floatfix.vhd	10	12529	LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CONVERSION - TOP LEVEL * --* * --* DP_FLOATFIX.VHD * --* * --* Function: Convert Floating Point to Fixed * --* Point Number * --* * --* 07/12/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --*********************************************** --*********************************************** --* LATENCY : * --* speed = 0 : 3 * --* speed = 1 : 5 * --*********************************************** --*********************************************** --* OUTPUT FORMAT - UNSIGNED * --* maximum number is (2^decimal)-1, else * --* saturate. if input negative, zero output * --* OUTPUT FORMAT - SIGNED * --* maximum number is (2^decimal-1)-1, else * --* saturate * --************************************************* ENTITY dp_floatfix IS GENERIC ( unsigned : integer := 1; -- unsigned = 0, signed = 1 decimal : integer := 14; fractional : integer := 6; precision : integer := 0; -- single = 0, double = 1 speed : integer := 0 -- low speed = 0, high speed = 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; sign : IN STD_LOGIC; exponent : IN STD_LOGIC_VECTOR (8+3precision DOWNTO 1); mantissa : IN STD_LOGIC_VECTOR (23+29precision DOWNTO 1); fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1) ); END dp_floatfix; ARCHITECTURE rtl of dp_floatfix IS constant fixed_width : positive := decimal + fractional; constant mantissa_width : positive := 23 + 29precision; constant exponent_width : positive := 8 + 3precision; constant exponent_base_number : positive := 127+896precision; -- input stage signal zerovec : STD_LOGIC_VECTOR (116 DOWNTO 1); signal exponent_base_node : STD_LOGIC_VECTOR (exponent_width+1 DOWNTO 1); signal saturate_check : STD_LOGIC_VECTOR (exponent_width+1 DOWNTO 1); signal saturate_output, zero_output : STD_LOGIC; signal saturate_apply, zero_apply : STD_LOGIC; signal sign_apply : STD_LOGIC; signal signed_mantissa_node : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1); signal signed_mantissa_comp : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1); signal signed_mantissa : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1); signal input_vector : STD_LOGIC_VECTOR (116 DOWNTO 1); signal negexponent : STD_LOGIC_VECTOR (exponent_width DOWNTO 1); signal expbase, negexpbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1); signal leftshift, rightshift : STD_LOGIC_VECTOR (exponent_width DOWNTO 1); -- shift stage signal leftbus, rightbus : STD_LOGIC_VECTOR (116 DOWNTO 1); signal shiftbus, shiftbusff : STD_LOGIC_VECTOR (fixed_width DOWNTO 1); signal select_bit : STD_LOGIC; -- output stage signal fixed_numberff : STD_LOGIC_VECTOR (fixed_width DOWNTO 1); component dp_addpipe IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component dp_lsft64x64 IS PORT ( inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component dp_lsftpipe64x64 IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component dp_rsft64x64 IS PORT ( inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component dp_rsftpipe64x64 IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component fp_delbit IS GENERIC ( pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; BEGIN gera : IF NOT((unsigned = 0) OR (unsigned = 1)) GENERATE assert false report "unsigned must be 0 or 1" severity error; END GENERATE; gerb : IF NOT((precision = 0) OR (precision = 1)) GENERATE assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error; END GENERATE; gerc : IF NOT((speed = 0) OR (speed = 1)) GENERATE assert false report "speed must be 0 or 1" severity error; END GENERATE; gerd : IF (decimal < 2) GENERATE assert false report "decimal must be greater than 2" severity error; END GENERATE; gere : IF (fixed_width > 64) GENERATE assert false report "maximum fixed point precision must be 64 or less" severity error; END GENERATE; gza: FOR k IN 1 TO 116 GENERATE zerovec(k) <= '0'; END GENERATE; -- LEVEL 1-2 * -- level 1 if speed = 0 -- level 2 if speed = 1 -- check for zero and saturate conditions exponent_base_node <= conv_std_logic_vector(exponent_base_number,exponent_width+1); gzsa: IF (unsigned = 0) GENERATE saturate_check <= exponent - exponent_base_node - decimal; -- '1' when condition true saturate_output <= NOT(saturate_check(exponent_width+1)); zero_output <= sign; END GENERATE; gzsb: IF (unsigned = 1) GENERATE saturate_check <= exponent - exponent_base_node - decimal + 1; -- '1' when condition true saturate_output <= NOT(saturate_check(exponent_width+1)); zero_output <= '0'; dss: fp_delbit GENERIC MAP (pipes=>2+2speed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>sign, cc=>sign_apply); END GENERATE; ds: fp_delbit GENERIC MAP (pipes=>2+2speed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>saturate_output, cc=>saturate_apply); dz: fp_delbit GENERIC MAP (pipes=>2+2speed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>zero_output, cc=>zero_apply); signed_mantissa_node <= "01" & mantissa; gsma: FOR k IN 1 TO mantissa_width+2 GENERATE signed_mantissa_comp(k) <= signed_mantissa_node(k) XOR sign; END GENERATE; addtop: dp_addpipe GENERIC MAP (width=>mantissa_width+2,pipes=>speed+1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>signed_mantissa_comp,bb=>zerovec(mantissa_width+2 DOWNTO 1), carryin=>sign, cc=>signed_mantissa); giva: FOR k IN 116-decimal+3 TO 116 GENERATE input_vector(k) <= signed_mantissa(mantissa_width+2); END GENERATE; input_vector(116-decimal+2 DOWNTO 116-decimal-mantissa_width+1) <= signed_mantissa; givb: IF (116-decimal-mantissa_width+1 > 1) GENERATE input_vector(116-decimal-mantissa_width DOWNTO 1) <= zerovec(116-decimal-mantissa_width DOWNTO 1); END GENERATE; gcxa: FOR k IN 1 TO exponent_width GENERATE negexponent(k) <= NOT(exponent(k)); END GENERATE; gcxb: FOR k IN 1 TO exponent_width-1 GENERATE expbase(k) <= '1'; negexpbase(k) <= '0'; END GENERATE; expbase(exponent_width) <= '0'; negexpbase(exponent_width) <= '1'; sublx: dp_addpipe GENERIC MAP (width=>exponent_width,pipes=>speed+1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>exponent,bb=>negexpbase, carryin=>'1', cc=>leftshift); subrx: dp_addpipe GENERIC MAP (width=>exponent_width,pipes=>speed+1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>negexponent,bb=>expbase, carryin=>'1', cc=>rightshift); -- LEVEL 2-4 (shiftbusff) * -- level 2 if speed = 0 -- level 4 if speed = 1 gsfa: IF (speed = 0) GENERATE clsc: dp_lsft64x64 PORT MAP (inbus=>input_vector,shift=>leftshift(6 DOWNTO 1), outbus=>leftbus); crsc: dp_rsft64x64 PORT MAP (inbus=>input_vector,shift=>rightshift(6 DOWNTO 1), outbus=>rightbus); select_bit <= leftshift(exponent_width); END GENERATE; gsfb: IF (speed = 1) GENERATE clsp: dp_lsftpipe64x64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>input_vector,shift=>leftshift(6 DOWNTO 1), outbus=>leftbus); crsp: dp_rsftpipe64x64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>input_vector,shift=>rightshift(6 DOWNTO 1), outbus=>rightbus); db: fp_delbit GENERIC MAP (pipes=>1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>leftshift(exponent_width), cc=>select_bit); END GENERATE; gsba: FOR k IN 1 TO fixed_width GENERATE shiftbus(k) <= (leftbus(116-fixed_width+k) AND NOT(select_bit)) OR (rightbus(116-fixed_width+k) AND select_bit); END GENERATE; psa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO fixed_width LOOP shiftbusff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN shiftbusff <= shiftbus; END IF; END IF; END PROCESS; --* LEVEL 3-5 * -- level 3 if speed = 0 -- level 5 if speed = 1 gou: IF (unsigned = 0) GENERATE poa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO fixed_width LOOP fixed_numberff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO fixed_width LOOP fixed_numberff(k) <= (shiftbusff(k) AND NOT(zero_apply)) OR saturate_apply; END LOOP; END IF; END IF; END PROCESS; END GENERATE; gos: IF (unsigned = 1) GENERATE pos: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO fixed_width LOOP fixed_numberff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO fixed_width-1 LOOP fixed_numberff(k) <= (shiftbusff(k) AND NOT(zero_apply) AND NOT(saturate_apply AND sign_apply)) OR (saturate_apply AND NOT(sign_apply)); END LOOP; fixed_numberff(fixed_width) <= (shiftbusff(fixed_width) AND NOT(zero_apply) AND NOT(saturate_apply AND NOT(sign_apply))) OR (saturate_apply AND sign_apply); END IF; END IF; END PROCESS; END GENERATE; fixed_number <= fixed_numberff; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/dp_explutneg.vhd	10	140760	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* DP_EXPLUTNEG.VHD * --* * --* Function: Look Up Table - EXP() * --* * --* Generated by MATLAB Utility * --* * --* 18/02/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY dp_explutneg IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutneg; ARCHITECTURE rtl OF dp_explutneg IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(7910755,24); manlo <= conv_std_logic_vector(103608120,28); exponent <= conv_std_logic_vector(1021,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(1387178,24); manlo <= conv_std_logic_vector(62882252,28); exponent <= conv_std_logic_vector(1020,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(9952012,24); manlo <= conv_std_logic_vector(214872239,28); exponent <= conv_std_logic_vector(1018,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(2889051,24); manlo <= conv_std_logic_vector(136396020,28); exponent <= conv_std_logic_vector(1017,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(12162046,24); manlo <= conv_std_logic_vector(873334,28); exponent <= conv_std_logic_vector(1015,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(4515103,24); manlo <= conv_std_logic_vector(18076886,28); exponent <= conv_std_logic_vector(1014,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(14554809,24); manlo <= conv_std_logic_vector(203729295,28); exponent <= conv_std_logic_vector(1012,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(6275600,24); manlo <= conv_std_logic_vector(68167597,28); exponent <= conv_std_logic_vector(1011,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(184098,24); manlo <= conv_std_logic_vector(86398042,28); exponent <= conv_std_logic_vector(1010,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(8181659,24); manlo <= conv_std_logic_vector(90471578,28); exponent <= conv_std_logic_vector(1008,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(1586498,24); manlo <= conv_std_logic_vector(59729764,28); exponent <= conv_std_logic_vector(1007,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(10245315,24); manlo <= conv_std_logic_vector(188988555,28); exponent <= conv_std_logic_vector(1005,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(3104851,24); manlo <= conv_std_logic_vector(194518424,28); exponent <= conv_std_logic_vector(1004,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(12479599,24); manlo <= conv_std_logic_vector(229643794,28); exponent <= conv_std_logic_vector(1002,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(4748746,24); manlo <= conv_std_logic_vector(36170808,28); exponent <= conv_std_logic_vector(1001,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(14898619,24); manlo <= conv_std_logic_vector(183403979,28); exponent <= conv_std_logic_vector(999,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(6528561,24); manlo <= conv_std_logic_vector(123365533,28); exponent <= conv_std_logic_vector(998,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(370216,24); manlo <= conv_std_logic_vector(208248737,28); exponent <= conv_std_logic_vector(997,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(8455535,24); manlo <= conv_std_logic_vector(254564210,28); exponent <= conv_std_logic_vector(995,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(1788005,24); manlo <= conv_std_logic_vector(99840615,28); exponent <= conv_std_logic_vector(994,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(10541837,24); manlo <= conv_std_logic_vector(14529516,28); exponent <= conv_std_logic_vector(992,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(3323019,24); manlo <= conv_std_logic_vector(252804514,28); exponent <= conv_std_logic_vector(991,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(12800638,24); manlo <= conv_std_logic_vector(70515377,28); exponent <= conv_std_logic_vector(989,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(4984952,24); manlo <= conv_std_logic_vector(266936970,28); exponent <= conv_std_logic_vector(988,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(15246202,24); manlo <= conv_std_logic_vector(73384750,28); exponent <= conv_std_logic_vector(986,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(6784298,24); manlo <= conv_std_logic_vector(117472834,28); exponent <= conv_std_logic_vector(985,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(558377,24); manlo <= conv_std_logic_vector(141983386,28); exponent <= conv_std_logic_vector(984,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(8732417,24); manlo <= conv_std_logic_vector(225268666,28); exponent <= conv_std_logic_vector(982,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(1991723,24); manlo <= conv_std_logic_vector(183207072,28); exponent <= conv_std_logic_vector(981,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(10841612,24); manlo <= conv_std_logic_vector(44859253,28); exponent <= conv_std_logic_vector(979,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(3543582,24); manlo <= conv_std_logic_vector(38615994,28); exponent <= conv_std_logic_vector(978,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(13125199,24); manlo <= conv_std_logic_vector(123823208,28); exponent <= conv_std_logic_vector(976,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(5223751,24); manlo <= conv_std_logic_vector(209149352,28); exponent <= conv_std_logic_vector(975,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(15597598,24); manlo <= conv_std_logic_vector(248916640,28); exponent <= conv_std_logic_vector(973,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(7042841,24); manlo <= conv_std_logic_vector(173666528,28); exponent <= conv_std_logic_vector(972,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(748602,24); manlo <= conv_std_logic_vector(266199140,28); exponent <= conv_std_logic_vector(971,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(9012337,24); manlo <= conv_std_logic_vector(264921173,28); exponent <= conv_std_logic_vector(969,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(2197677,24); manlo <= conv_std_logic_vector(112079619,28); exponent <= conv_std_logic_vector(968,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(11144676,24); manlo <= conv_std_logic_vector(200497976,28); exponent <= conv_std_logic_vector(966,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(3766564,24); manlo <= conv_std_logic_vector(161159716,28); exponent <= conv_std_logic_vector(965,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(13453322,24); manlo <= conv_std_logic_vector(28788768,28); exponent <= conv_std_logic_vector(963,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(5465170,24); manlo <= conv_std_logic_vector(249755484,28); exponent <= conv_std_logic_vector(962,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(15952851,24); manlo <= conv_std_logic_vector(133443390,28); exponent <= conv_std_logic_vector(960,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(7304221,24); manlo <= conv_std_logic_vector(236407020,28); exponent <= conv_std_logic_vector(959,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(940915,24); manlo <= conv_std_logic_vector(220198205,28); exponent <= conv_std_logic_vector(958,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(9295329,24); manlo <= conv_std_logic_vector(196124030,28); exponent <= conv_std_logic_vector(956,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(2405891,24); manlo <= conv_std_logic_vector(28613594,28); exponent <= conv_std_logic_vector(955,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(11451066,24); manlo <= conv_std_logic_vector(238698933,28); exponent <= conv_std_logic_vector(953,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(3991993,24); manlo <= conv_std_logic_vector(233279365,28); exponent <= conv_std_logic_vector(952,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(13785045,24); manlo <= conv_std_logic_vector(75368511,28); exponent <= conv_std_logic_vector(950,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(5709239,24); manlo <= conv_std_logic_vector(54173026,28); exponent <= conv_std_logic_vector(949,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(16312002,24); manlo <= conv_std_logic_vector(78993710,28); exponent <= conv_std_logic_vector(947,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(7568470,24); manlo <= conv_std_logic_vector(72422582,28); exponent <= conv_std_logic_vector(946,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(1135338,24); manlo <= conv_std_logic_vector(246889480,28); exponent <= conv_std_logic_vector(945,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(9581426,24); manlo <= conv_std_logic_vector(208117876,28); exponent <= conv_std_logic_vector(943,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(2616389,24); manlo <= conv_std_logic_vector(147217980,28); exponent <= conv_std_logic_vector(942,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(11760819,24); manlo <= conv_std_logic_vector(23037889,28); exponent <= conv_std_logic_vector(940,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(4219896,24); manlo <= conv_std_logic_vector(214481816,28); exponent <= conv_std_logic_vector(939,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(14120408,24); manlo <= conv_std_logic_vector(131761485,28); exponent <= conv_std_logic_vector(937,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(5955985,24); manlo <= conv_std_logic_vector(177821786,28); exponent <= conv_std_logic_vector(936,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(16675094,24); manlo <= conv_std_logic_vector(25356748,28); exponent <= conv_std_logic_vector(934,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(7835618,24); manlo <= conv_std_logic_vector(77011020,28); exponent <= conv_std_logic_vector(933,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(1331895,24); manlo <= conv_std_logic_vector(119779026,28); exponent <= conv_std_logic_vector(932,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(9870663,24); manlo <= conv_std_logic_vector(52552908,28); exponent <= conv_std_logic_vector(930,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(2829197,24); manlo <= conv_std_logic_vector(218477336,28); exponent <= conv_std_logic_vector(929,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(12073970,24); manlo <= conv_std_logic_vector(61450731,28); exponent <= conv_std_logic_vector(927,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(4450300,24); manlo <= conv_std_logic_vector(143360086,28); exponent <= conv_std_logic_vector(926,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(14459451,24); manlo <= conv_std_logic_vector(182543396,28); exponent <= conv_std_logic_vector(924,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(6205439,24); manlo <= conv_std_logic_vector(188004913,28); exponent <= conv_std_logic_vector(923,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(132477,24); manlo <= conv_std_logic_vector(19160299,28); exponent <= conv_std_logic_vector(922,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(8105697,24); manlo <= conv_std_logic_vector(201304075,28); exponent <= conv_std_logic_vector(920,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(1530608,24); manlo <= conv_std_logic_vector(217452229,28); exponent <= conv_std_logic_vector(919,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(10163073,24); manlo <= conv_std_logic_vector(118320126,28); exponent <= conv_std_logic_vector(917,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(3044341,24); manlo <= conv_std_logic_vector(66824260,28); exponent <= conv_std_logic_vector(916,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(12390557,24); manlo <= conv_std_logic_vector(165235674,28); exponent <= conv_std_logic_vector(914,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(4683232,24); manlo <= conv_std_logic_vector(138461149,28); exponent <= conv_std_logic_vector(913,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(14802215,24); manlo <= conv_std_logic_vector(61508170,28); exponent <= conv_std_logic_vector(911,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(6457631,24); manlo <= conv_std_logic_vector(7025744,28); exponent <= conv_std_logic_vector(910,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(318029,24); manlo <= conv_std_logic_vector(21309721,28); exponent <= conv_std_logic_vector(909,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(8378740,24); manlo <= conv_std_logic_vector(221720132,28); exponent <= conv_std_logic_vector(907,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(1731502,24); manlo <= conv_std_logic_vector(182144977,28); exponent <= conv_std_logic_vector(906,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(10458692,24); manlo <= conv_std_logic_vector(90475423,28); exponent <= conv_std_logic_vector(904,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(3261845,24); manlo <= conv_std_logic_vector(128220642,28); exponent <= conv_std_logic_vector(903,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(12710618,24); manlo <= conv_std_logic_vector(255552070,28); exponent <= conv_std_logic_vector(901,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(4918720,24); manlo <= conv_std_logic_vector(130727832,28); exponent <= conv_std_logic_vector(900,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(15148739,24); manlo <= conv_std_logic_vector(258265342,28); exponent <= conv_std_logic_vector(898,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(6712589,24); manlo <= conv_std_logic_vector(181573149,28); exponent <= conv_std_logic_vector(897,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(505617,24); manlo <= conv_std_logic_vector(45883390,28); exponent <= conv_std_logic_vector(896,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(8654780,24); manlo <= conv_std_logic_vector(9428106,28); exponent <= conv_std_logic_vector(894,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(1934600,24); manlo <= conv_std_logic_vector(262677610,28); exponent <= conv_std_logic_vector(893,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(10757555,24); manlo <= conv_std_logic_vector(25094861,28); exponent <= conv_std_logic_vector(891,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(3481736,24); manlo <= conv_std_logic_vector(108799619,28); exponent <= conv_std_logic_vector(890,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(13034192,24); manlo <= conv_std_logic_vector(96190464,28); exponent <= conv_std_logic_vector(888,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(5156792,24); manlo <= conv_std_logic_vector(132821234,28); exponent <= conv_std_logic_vector(887,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(15499067,24); manlo <= conv_std_logic_vector(40497064,28); exponent <= conv_std_logic_vector(885,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6970346,24); manlo <= conv_std_logic_vector(4633646,28); exponent <= conv_std_logic_vector(884,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(695263,24); manlo <= conv_std_logic_vector(184734272,28); exponent <= conv_std_logic_vector(883,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(8933848,24); manlo <= conv_std_logic_vector(68258056,28); exponent <= conv_std_logic_vector(881,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(2139927,24); manlo <= conv_std_logic_vector(241478077,28); exponent <= conv_std_logic_vector(880,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(11059697,24); manlo <= conv_std_logic_vector(81964893,28); exponent <= conv_std_logic_vector(878,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(3704040,24); manlo <= conv_std_logic_vector(59435624,28); exponent <= conv_std_logic_vector(877,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(13361316,24); manlo <= conv_std_logic_vector(100097713,28); exponent <= conv_std_logic_vector(875,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(5397476,24); manlo <= conv_std_logic_vector(240017437,28); exponent <= conv_std_logic_vector(874,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(15853238,24); manlo <= conv_std_logic_vector(139632179,28); exponent <= conv_std_logic_vector(872,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(7230930,24); manlo <= conv_std_logic_vector(200816807,28); exponent <= conv_std_logic_vector(871,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(886991,24); manlo <= conv_std_logic_vector(58654941,28); exponent <= conv_std_logic_vector(870,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(9215978,24); manlo <= conv_std_logic_vector(193575030,28); exponent <= conv_std_logic_vector(868,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(2347507,24); manlo <= conv_std_logic_vector(240661664,28); exponent <= conv_std_logic_vector(867,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(11365154,24); manlo <= conv_std_logic_vector(257284930,28); exponent <= conv_std_logic_vector(865,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(3928783,24); manlo <= conv_std_logic_vector(108146246,28); exponent <= conv_std_logic_vector(864,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(13692029,24); manlo <= conv_std_logic_vector(256867284,28); exponent <= conv_std_logic_vector(862,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(5640802,24); manlo <= conv_std_logic_vector(94243132,28); exponent <= conv_std_logic_vector(861,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(16211296,24); manlo <= conv_std_logic_vector(67825654,28); exponent <= conv_std_logic_vector(859,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(7494374,24); manlo <= conv_std_logic_vector(242982196,28); exponent <= conv_std_logic_vector(858,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(1080822,24); manlo <= conv_std_logic_vector(160277009,28); exponent <= conv_std_logic_vector(857,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(9501205,24); manlo <= conv_std_logic_vector(10212621,28); exponent <= conv_std_logic_vector(855,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(2557365,24); manlo <= conv_std_logic_vector(185941944,28); exponent <= conv_std_logic_vector(854,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(11673964,24); manlo <= conv_std_logic_vector(116382402,28); exponent <= conv_std_logic_vector(852,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(4155992,24); manlo <= conv_std_logic_vector(192503267,28); exponent <= conv_std_logic_vector(851,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(14026372,24); manlo <= conv_std_logic_vector(133984890,28); exponent <= conv_std_logic_vector(849,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(5886797,24); manlo <= conv_std_logic_vector(227169396,28); exponent <= conv_std_logic_vector(848,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(16573282,24); manlo <= conv_std_logic_vector(266790864,28); exponent <= conv_std_logic_vector(846,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(7760709,24); manlo <= conv_std_logic_vector(232279832,28); exponent <= conv_std_logic_vector(845,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(1276780,24); manlo <= conv_std_logic_vector(244188460,28); exponent <= conv_std_logic_vector(844,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(9789561,24); manlo <= conv_std_logic_vector(47289108,28); exponent <= conv_std_logic_vector(842,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(2769526,24); manlo <= conv_std_logic_vector(75856665,28); exponent <= conv_std_logic_vector(841,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(11986162,24); manlo <= conv_std_logic_vector(137053172,28); exponent <= conv_std_logic_vector(839,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(4385695,24); manlo <= conv_std_logic_vector(60488459,28); exponent <= conv_std_logic_vector(838,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(14364383,24); manlo <= conv_std_logic_vector(220265084,28); exponent <= conv_std_logic_vector(836,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(6135492,24); manlo <= conv_std_logic_vector(182090040,28); exponent <= conv_std_logic_vector(835,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(81012,24); manlo <= conv_std_logic_vector(249275143,28); exponent <= conv_std_logic_vector(834,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(8029967,24); manlo <= conv_std_logic_vector(93846972,28); exponent <= conv_std_logic_vector(832,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(1474889,24); manlo <= conv_std_logic_vector(132978099,28); exponent <= conv_std_logic_vector(831,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(10081081,24); manlo <= conv_std_logic_vector(128680817,28); exponent <= conv_std_logic_vector(829,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(2984014,24); manlo <= conv_std_logic_vector(251002315,28); exponent <= conv_std_logic_vector(828,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(12301786,24); manlo <= conv_std_logic_vector(100124707,28); exponent <= conv_std_logic_vector(826,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(4617918,24); manlo <= conv_std_logic_vector(76665129,28); exponent <= conv_std_logic_vector(825,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(14706104,24); manlo <= conv_std_logic_vector(48076192,28); exponent <= conv_std_logic_vector(823,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(6386916,24); manlo <= conv_std_logic_vector(125471070,28); exponent <= conv_std_logic_vector(822,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(266000,24); manlo <= conv_std_logic_vector(57624675,28); exponent <= conv_std_logic_vector(821,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(8302179,24); manlo <= conv_std_logic_vector(114693198,28); exponent <= conv_std_logic_vector(819,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(1675171,24); manlo <= conv_std_logic_vector(254852645,28); exponent <= conv_std_logic_vector(818,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(10375800,24); manlo <= conv_std_logic_vector(179426511,28); exponent <= conv_std_logic_vector(816,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(3200857,24); manlo <= conv_std_logic_vector(52664716,28); exponent <= conv_std_logic_vector(815,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(12620873,24); manlo <= conv_std_logic_vector(164386702,28); exponent <= conv_std_logic_vector(813,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(4852689,24); manlo <= conv_std_logic_vector(149310968,28); exponent <= conv_std_logic_vector(812,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(15051574,24); manlo <= conv_std_logic_vector(73675604,28); exponent <= conv_std_logic_vector(810,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(6641099,24); manlo <= conv_std_logic_vector(42591307,28); exponent <= conv_std_logic_vector(809,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(453017,24); manlo <= conv_std_logic_vector(104016801,28); exponent <= conv_std_logic_vector(808,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(8577378,24); manlo <= conv_std_logic_vector(139419332,28); exponent <= conv_std_logic_vector(806,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(1877652,24); manlo <= conv_std_logic_vector(33778363,28); exponent <= conv_std_logic_vector(805,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(10673753,24); manlo <= conv_std_logic_vector(226837452,28); exponent <= conv_std_logic_vector(803,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(3420078,24); manlo <= conv_std_logic_vector(239554874,28); exponent <= conv_std_logic_vector(802,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(12943462,24); manlo <= conv_std_logic_vector(62486566,28); exponent <= conv_std_logic_vector(800,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(5090036,24); manlo <= conv_std_logic_vector(268173235,28); exponent <= conv_std_logic_vector(799,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(15400835,24); manlo <= conv_std_logic_vector(67898261,28); exponent <= conv_std_logic_vector(797,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(6898071,24); manlo <= conv_std_logic_vector(6935226,28); exponent <= conv_std_logic_vector(796,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(642086,24); manlo <= conv_std_logic_vector(193616024,28); exponent <= conv_std_logic_vector(795,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(8855597,24); manlo <= conv_std_logic_vector(108124901,28); exponent <= conv_std_logic_vector(793,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(2082354,24); manlo <= conv_std_logic_vector(37727361,28); exponent <= conv_std_logic_vector(792,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(10974976,24); manlo <= conv_std_logic_vector(133184200,28); exponent <= conv_std_logic_vector(790,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(3641706,24); manlo <= conv_std_logic_vector(35844662,28); exponent <= conv_std_logic_vector(789,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(13269590,24); manlo <= conv_std_logic_vector(175886280,28); exponent <= conv_std_logic_vector(787,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(5329988,24); manlo <= conv_std_logic_vector(236927280,28); exponent <= conv_std_logic_vector(786,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(15753928,24); manlo <= conv_std_logic_vector(191213976,28); exponent <= conv_std_logic_vector(784,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(7157862,24); manlo <= conv_std_logic_vector(181160855,28); exponent <= conv_std_logic_vector(783,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(833230,24); manlo <= conv_std_logic_vector(197197075,28); exponent <= conv_std_logic_vector(782,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(9136869,24); manlo <= conv_std_logic_vector(57456047,28); exponent <= conv_std_logic_vector(780,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(2289302,24); manlo <= conv_std_logic_vector(100400411,28); exponent <= conv_std_logic_vector(779,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(11279504,24); manlo <= conv_std_logic_vector(133702078,28); exponent <= conv_std_logic_vector(777,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(3865765,24); manlo <= conv_std_logic_vector(84791606,28); exponent <= conv_std_logic_vector(776,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(13599297,24); manlo <= conv_std_logic_vector(193913492,28); exponent <= conv_std_logic_vector(774,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(5572573,24); manlo <= conv_std_logic_vector(210951234,28); exponent <= conv_std_logic_vector(773,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(16110896,24); manlo <= conv_std_logic_vector(189751005,28); exponent <= conv_std_logic_vector(771,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(7420505,24); manlo <= conv_std_logic_vector(12771910,28); exponent <= conv_std_logic_vector(770,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(1026472,24); manlo <= conv_std_logic_vector(51864863,28); exponent <= conv_std_logic_vector(769,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(9421227,24); manlo <= conv_std_logic_vector(121664951,28); exponent <= conv_std_logic_vector(767,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(2498521,24); manlo <= conv_std_logic_vector(127312793,28); exponent <= conv_std_logic_vector(766,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(11587374,24); manlo <= conv_std_logic_vector(32431827,28); exponent <= conv_std_logic_vector(764,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(4092283,24); manlo <= conv_std_logic_vector(33663701,28); exponent <= conv_std_logic_vector(763,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(13932622,24); manlo <= conv_std_logic_vector(188745186,28); exponent <= conv_std_logic_vector(761,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(5817820,24); manlo <= conv_std_logic_vector(161368804,28); exponent <= conv_std_logic_vector(760,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(16471781,24); manlo <= conv_std_logic_vector(201946939,28); exponent <= conv_std_logic_vector(758,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(7686029,24); manlo <= conv_std_logic_vector(114155240,28); exponent <= conv_std_logic_vector(757,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(1221834,24); manlo <= conv_std_logic_vector(30217784,28); exponent <= conv_std_logic_vector(756,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(9708705,24); manlo <= conv_std_logic_vector(265245416,28); exponent <= conv_std_logic_vector(754,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(2710036,24); manlo <= conv_std_logic_vector(96582323,28); exponent <= conv_std_logic_vector(753,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(11898622,24); manlo <= conv_std_logic_vector(8685564,28); exponent <= conv_std_logic_vector(751,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(4321286,24); manlo <= conv_std_logic_vector(145205332,28); exponent <= conv_std_logic_vector(750,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(14269605,24); manlo <= conv_std_logic_vector(79792252,28); exponent <= conv_std_logic_vector(748,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(6065758,24); manlo <= conv_std_logic_vector(144408455,28); exponent <= conv_std_logic_vector(747,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(29705,24); manlo <= conv_std_logic_vector(111518540,28); exponent <= conv_std_logic_vector(746,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(7954467,24); manlo <= conv_std_logic_vector(116097284,28); exponent <= conv_std_logic_vector(744,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(1419339,24); manlo <= conv_std_logic_vector(204212637,28); exponent <= conv_std_logic_vector(743,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(9999339,24); manlo <= conv_std_logic_vector(15580207,28); exponent <= conv_std_logic_vector(741,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(2923872,24); manlo <= conv_std_logic_vector(59726033,28); exponent <= conv_std_logic_vector(740,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(12213285,24); manlo <= conv_std_logic_vector(81348195,28); exponent <= conv_std_logic_vector(738,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(4552802,24); manlo <= conv_std_logic_vector(224758002,28); exponent <= conv_std_logic_vector(737,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(14610285,24); manlo <= conv_std_logic_vector(171839647,28); exponent <= conv_std_logic_vector(735,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(6316417,24); manlo <= conv_std_logic_vector(33901818,28); exponent <= conv_std_logic_vector(734,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(214129,24); manlo <= conv_std_logic_vector(187432044,28); exponent <= conv_std_logic_vector(733,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(8225851,24); manlo <= conv_std_logic_vector(10972428,28); exponent <= conv_std_logic_vector(731,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(1619012,24); manlo <= conv_std_logic_vector(177473085,28); exponent <= conv_std_logic_vector(730,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(10293161,24); manlo <= conv_std_logic_vector(74648462,28); exponent <= conv_std_logic_vector(728,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(3140054,24); manlo <= conv_std_logic_vector(142465582,28); exponent <= conv_std_logic_vector(727,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(12531401,24); manlo <= conv_std_logic_vector(110062606,28); exponent <= conv_std_logic_vector(725,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(4786859,24); manlo <= conv_std_logic_vector(158003247,28); exponent <= conv_std_logic_vector(724,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(14954704,24); manlo <= conv_std_logic_vector(82587752,28); exponent <= conv_std_logic_vector(722,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(6569826,24); manlo <= conv_std_logic_vector(59098716,28); exponent <= conv_std_logic_vector(721,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(400577,24); manlo <= conv_std_logic_vector(185198176,28); exponent <= conv_std_logic_vector(720,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(8500212,24); manlo <= conv_std_logic_vector(153765179,28); exponent <= conv_std_logic_vector(718,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(1820876,24); manlo <= conv_std_logic_vector(159783545,28); exponent <= conv_std_logic_vector(717,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(10590207,24); manlo <= conv_std_logic_vector(172648734,28); exponent <= conv_std_logic_vector(715,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(3358609,24); manlo <= conv_std_logic_vector(8670608,28); exponent <= conv_std_logic_vector(714,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(12853008,24); manlo <= conv_std_logic_vector(64863304,28); exponent <= conv_std_logic_vector(712,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(5023484,24); manlo <= conv_std_logic_vector(180279682,28); exponent <= conv_std_logic_vector(711,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(15302902,24); manlo <= conv_std_logic_vector(86126918,28); exponent <= conv_std_logic_vector(709,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(6826016,24); manlo <= conv_std_logic_vector(315265,28); exponent <= conv_std_logic_vector(708,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(589071,24); manlo <= conv_std_logic_vector(160219440,28); exponent <= conv_std_logic_vector(707,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(8777584,24); manlo <= conv_std_logic_vector(189361726,28); exponent <= conv_std_logic_vector(705,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(2024955,24); manlo <= conv_std_logic_vector(162543151,28); exponent <= conv_std_logic_vector(704,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(10890513,24); manlo <= conv_std_logic_vector(142859647,28); exponent <= conv_std_logic_vector(702,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(3579561,24); manlo <= conv_std_logic_vector(203359193,28); exponent <= conv_std_logic_vector(701,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(13178144,24); manlo <= conv_std_logic_vector(27387766,28); exponent <= conv_std_logic_vector(699,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(5262706,24); manlo <= conv_std_logic_vector(72167880,28); exponent <= conv_std_logic_vector(698,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(15654921,24); manlo <= conv_std_logic_vector(40507130,28); exponent <= conv_std_logic_vector(696,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(7085016,24); manlo <= conv_std_logic_vector(263640644,28); exponent <= conv_std_logic_vector(695,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(779633,24); manlo <= conv_std_logic_vector(233308885,28); exponent <= conv_std_logic_vector(694,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(9058000,24); manlo <= conv_std_logic_vector(127336500,28); exponent <= conv_std_logic_vector(692,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(2231273,24); manlo <= conv_std_logic_vector(267969878,28); exponent <= conv_std_logic_vector(691,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(11194114,24); manlo <= conv_std_logic_vector(191206462,28); exponent <= conv_std_logic_vector(689,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(3802939,24); manlo <= conv_std_logic_vector(6046440,28); exponent <= conv_std_logic_vector(688,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(13506847,24); manlo <= conv_std_logic_vector(192101060,28); exponent <= conv_std_logic_vector(686,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(5504552,24); manlo <= conv_std_logic_vector(234133234,28); exponent <= conv_std_logic_vector(685,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(16010802,24); manlo <= conv_std_logic_vector(194370273,28); exponent <= conv_std_logic_vector(683,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(7346860,24); manlo <= conv_std_logic_vector(2864438,28); exponent <= conv_std_logic_vector(682,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(972287,24); manlo <= conv_std_logic_vector(54536955,28); exponent <= conv_std_logic_vector(681,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(9341493,24); manlo <= conv_std_logic_vector(74572905,28); exponent <= conv_std_logic_vector(679,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(2439856,24); manlo <= conv_std_logic_vector(93006730,28); exponent <= conv_std_logic_vector(678,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(11501047,24); manlo <= conv_std_logic_vector(92098230,28); exponent <= conv_std_logic_vector(676,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(4028767,24); manlo <= conv_std_logic_vector(115940390,28); exponent <= conv_std_logic_vector(675,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(13839158,24); manlo <= conv_std_logic_vector(62227559,28); exponent <= conv_std_logic_vector(673,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(5749053,24); manlo <= conv_std_logic_vector(76824142,28); exponent <= conv_std_logic_vector(672,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(16370589,24); manlo <= conv_std_logic_vector(114548734,28); exponent <= conv_std_logic_vector(670,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(7611576,24); manlo <= conv_std_logic_vector(73252889,28); exponent <= conv_std_logic_vector(669,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(1167054,24); manlo <= conv_std_logic_vector(146134399,28); exponent <= conv_std_logic_vector(668,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(9628096,24); manlo <= conv_std_logic_vector(236331104,28); exponent <= conv_std_logic_vector(666,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(2650727,24); manlo <= conv_std_logic_vector(132284651,28); exponent <= conv_std_logic_vector(665,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(11811347,24); manlo <= conv_std_logic_vector(263325685,28); exponent <= conv_std_logic_vector(663,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(4257073,24); manlo <= conv_std_logic_vector(236873507,28); exponent <= conv_std_logic_vector(662,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(14175115,24); manlo <= conv_std_logic_vector(61615323,28); exponent <= conv_std_logic_vector(660,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(5996236,24); manlo <= conv_std_logic_vector(169476567,28); exponent <= conv_std_logic_vector(659,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(16734324,24); manlo <= conv_std_logic_vector(29597837,28); exponent <= conv_std_logic_vector(657,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(7879197,24); manlo <= conv_std_logic_vector(79755942,28); exponent <= conv_std_logic_vector(656,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(1363959,24); manlo <= conv_std_logic_vector(24177677,28); exponent <= conv_std_logic_vector(655,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(9917845,24); manlo <= conv_std_logic_vector(112021148,28); exponent <= conv_std_logic_vector(653,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(2863912,24); manlo <= conv_std_logic_vector(148304045,28); exponent <= conv_std_logic_vector(652,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(12125053,24); manlo <= conv_std_logic_vector(156617262,28); exponent <= conv_std_logic_vector(650,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(4487885,24); manlo <= conv_std_logic_vector(151904422,28); exponent <= conv_std_logic_vector(649,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(14514758,24); manlo <= conv_std_logic_vector(193824214,28); exponent <= conv_std_logic_vector(647,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(6246132,24); manlo <= conv_std_logic_vector(93361418,28); exponent <= conv_std_logic_vector(646,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(162417,24); manlo <= conv_std_logic_vector(12929741,28); exponent <= conv_std_logic_vector(645,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(8149754,24); manlo <= conv_std_logic_vector(257063442,28); exponent <= conv_std_logic_vector(643,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(1563024,24); manlo <= conv_std_logic_vector(78378796,28); exponent <= conv_std_logic_vector(642,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(10210773,24); manlo <= conv_std_logic_vector(106907060,28); exponent <= conv_std_logic_vector(640,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(3079436,24); manlo <= conv_std_logic_vector(245979562,28); exponent <= conv_std_logic_vector(639,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(12442201,24); manlo <= conv_std_logic_vector(137868870,28); exponent <= conv_std_logic_vector(637,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(4721229,24); manlo <= conv_std_logic_vector(261058204,28); exponent <= conv_std_logic_vector(636,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(14858129,24); manlo <= conv_std_logic_vector(43405174,28); exponent <= conv_std_logic_vector(634,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(6498770,24); manlo <= conv_std_logic_vector(53338521,28); exponent <= conv_std_logic_vector(633,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(348297,24); manlo <= conv_std_logic_vector(158641329,28); exponent <= conv_std_logic_vector(632,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(8423281,24); manlo <= conv_std_logic_vector(128446906,28); exponent <= conv_std_logic_vector(630,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(1764273,24); manlo <= conv_std_logic_vector(230657816,28); exponent <= conv_std_logic_vector(629,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(10506915,24); manlo <= conv_std_logic_vector(191032874,28); exponent <= conv_std_logic_vector(627,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(3297326,24); manlo <= conv_std_logic_vector(68145509,28); exponent <= conv_std_logic_vector(626,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(12762829,24); manlo <= conv_std_logic_vector(146161159,28); exponent <= conv_std_logic_vector(624,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(4957134,24); manlo <= conv_std_logic_vector(240027976,28); exponent <= conv_std_logic_vector(623,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(15205267,24); manlo <= conv_std_logic_vector(119370809,28); exponent <= conv_std_logic_vector(621,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(6754180,24); manlo <= conv_std_logic_vector(73501816,28); exponent <= conv_std_logic_vector(620,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(536217,24); manlo <= conv_std_logic_vector(220758658,28); exponent <= conv_std_logic_vector(619,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(8699809,24); manlo <= conv_std_logic_vector(117402516,28); exponent <= conv_std_logic_vector(617,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(1967731,24); manlo <= conv_std_logic_vector(204336317,28); exponent <= conv_std_logic_vector(616,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(10806307,24); manlo <= conv_std_logic_vector(168773516,28); exponent <= conv_std_logic_vector(614,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(3517606,24); manlo <= conv_std_logic_vector(138553816,28); exponent <= conv_std_logic_vector(613,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(13086975,24); manlo <= conv_std_logic_vector(231838082,28); exponent <= conv_std_logic_vector(611,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(5195628,24); manlo <= conv_std_logic_vector(114805284,28); exponent <= conv_std_logic_vector(610,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(15556214,24); manlo <= conv_std_logic_vector(245890169,28); exponent <= conv_std_logic_vector(608,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(7012392,24); manlo <= conv_std_logic_vector(266576824,28); exponent <= conv_std_logic_vector(607,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(726200,24); manlo <= conv_std_logic_vector(33318175,28); exponent <= conv_std_logic_vector(606,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(8979371,24); manlo <= conv_std_logic_vector(206515377,28); exponent <= conv_std_logic_vector(604,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(2173422,24); manlo <= conv_std_logic_vector(61774637,28); exponent <= conv_std_logic_vector(603,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(11108984,24); manlo <= conv_std_logic_vector(216833386,28); exponent <= conv_std_logic_vector(601,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(3740303,24); manlo <= conv_std_logic_vector(252090990,28); exponent <= conv_std_logic_vector(600,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(13414679,24); manlo <= conv_std_logic_vector(20856890,28); exponent <= conv_std_logic_vector(598,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(5436738,24); manlo <= conv_std_logic_vector(262578382,28); exponent <= conv_std_logic_vector(597,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(15911013,24); manlo <= conv_std_logic_vector(100481506,28); exponent <= conv_std_logic_vector(595,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(7273439,24); manlo <= conv_std_logic_vector(29586843,28); exponent <= conv_std_logic_vector(594,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(918267,24); manlo <= conv_std_logic_vector(33154287,28); exponent <= conv_std_logic_vector(593,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(9262001,24); manlo <= conv_std_logic_vector(206947959,28); exponent <= conv_std_logic_vector(591,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(2381369,24); manlo <= conv_std_logic_vector(205146615,28); exponent <= conv_std_logic_vector(590,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(11414983,24); manlo <= conv_std_logic_vector(80080029,28); exponent <= conv_std_logic_vector(588,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(3965445,24); manlo <= conv_std_logic_vector(12487826,28); exponent <= conv_std_logic_vector(587,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(13745978,24); manlo <= conv_std_logic_vector(58199715,28); exponent <= conv_std_logic_vector(585,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(5680495,24); manlo <= conv_std_logic_vector(70463110,28); exponent <= conv_std_logic_vector(584,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(16269705,24); manlo <= conv_std_logic_vector(20654997,28); exponent <= conv_std_logic_vector(582,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(7537349,24); manlo <= conv_std_logic_vector(192319832,28); exponent <= conv_std_logic_vector(581,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(1112441,24); manlo <= conv_std_logic_vector(186880957,28); exponent <= conv_std_logic_vector(580,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(9547733,24); manlo <= conv_std_logic_vector(27940083,28); exponent <= conv_std_logic_vector(578,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(2591599,24); manlo <= conv_std_logic_vector(35045549,28); exponent <= conv_std_logic_vector(577,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(11724339,24); manlo <= conv_std_logic_vector(146438512,28); exponent <= conv_std_logic_vector(575,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(4193056,24); manlo <= conv_std_logic_vector(175344679,28); exponent <= conv_std_logic_vector(574,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(14080912,24); manlo <= conv_std_logic_vector(198508677,28); exponent <= conv_std_logic_vector(572,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(5926926,24); manlo <= conv_std_logic_vector(83904648,28); exponent <= conv_std_logic_vector(571,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(16632332,24); manlo <= conv_std_logic_vector(199957404,28); exponent <= conv_std_logic_vector(569,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(7804156,24); manlo <= conv_std_logic_vector(65532420,28); exponent <= conv_std_logic_vector(568,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(1308746,24); manlo <= conv_std_logic_vector(260058525,28); exponent <= conv_std_logic_vector(567,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(9836599,24); manlo <= conv_std_logic_vector(214756046,28); exponent <= conv_std_logic_vector(565,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(2804135,24); manlo <= conv_std_logic_vector(98759674,28); exponent <= conv_std_logic_vector(564,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(12037090,24); manlo <= conv_std_logic_vector(105879341,28); exponent <= conv_std_logic_vector(562,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(4423165,24); manlo <= conv_std_logic_vector(233069674,28); exponent <= conv_std_logic_vector(561,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(14419522,24); manlo <= conv_std_logic_vector(144218340,28); exponent <= conv_std_logic_vector(559,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(6176061,24); manlo <= conv_std_logic_vector(128557517,28); exponent <= conv_std_logic_vector(558,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(110861,24); manlo <= conv_std_logic_vector(210451229,28); exponent <= conv_std_logic_vector(557,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(8073890,24); manlo <= conv_std_logic_vector(126309403,28); exponent <= conv_std_logic_vector(555,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(1507206,24); manlo <= conv_std_logic_vector(86368556,28); exponent <= conv_std_logic_vector(554,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(10128636,24); manlo <= conv_std_logic_vector(70724454,28); exponent <= conv_std_logic_vector(552,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(3019003,24); manlo <= conv_std_logic_vector(212024500,28); exponent <= conv_std_logic_vector(551,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(12353273,24); manlo <= conv_std_logic_vector(25338267,28); exponent <= conv_std_logic_vector(549,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(4655800,24); manlo <= conv_std_logic_vector(26358145,28); exponent <= conv_std_logic_vector(548,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(14761847,24); manlo <= conv_std_logic_vector(252137457,28); exponent <= conv_std_logic_vector(546,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(6427930,24); manlo <= conv_std_logic_vector(116530320,28); exponent <= conv_std_logic_vector(545,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(296176,24); manlo <= conv_std_logic_vector(162393576,28); exponent <= conv_std_logic_vector(544,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(8346584,24); manlo <= conv_std_logic_vector(140031506,28); exponent <= conv_std_logic_vector(542,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(1707843,24); manlo <= conv_std_logic_vector(105232250,28); exponent <= conv_std_logic_vector(541,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(10423877,24); manlo <= conv_std_logic_vector(74257288,28); exponent <= conv_std_logic_vector(539,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(3236229,24); manlo <= conv_std_logic_vector(265138481,28); exponent <= conv_std_logic_vector(538,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(12672925,24); manlo <= conv_std_logic_vector(81471742,28); exponent <= conv_std_logic_vector(536,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(4890987,24); manlo <= conv_std_logic_vector(13504322,28); exponent <= conv_std_logic_vector(535,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(15107929,24); manlo <= conv_std_logic_vector(192561070,28); exponent <= conv_std_logic_vector(533,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(6682563,24); manlo <= conv_std_logic_vector(47334412,28); exponent <= conv_std_logic_vector(532,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(483524,24); manlo <= conv_std_logic_vector(243414774,28); exponent <= conv_std_logic_vector(531,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(8622270,24); manlo <= conv_std_logic_vector(235144322,28); exponent <= conv_std_logic_vector(529,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(1910682,24); manlo <= conv_std_logic_vector(20388866,28); exponent <= conv_std_logic_vector(528,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(10722358,24); manlo <= conv_std_logic_vector(913747,28); exponent <= conv_std_logic_vector(526,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(3455839,24); manlo <= conv_std_logic_vector(223781205,28); exponent <= conv_std_logic_vector(525,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(12996085,24); manlo <= conv_std_logic_vector(24989984,28); exponent <= conv_std_logic_vector(523,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(5128754,24); manlo <= conv_std_logic_vector(197545335,28); exponent <= conv_std_logic_vector(522,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(15457809,24); manlo <= conv_std_logic_vector(24315860,28); exponent <= conv_std_logic_vector(520,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6939990,24); manlo <= conv_std_logic_vector(8842978,28); exponent <= conv_std_logic_vector(519,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(672929,24); manlo <= conv_std_logic_vector(830489,28); exponent <= conv_std_logic_vector(518,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(8900982,24); manlo <= conv_std_logic_vector(98890321,28); exponent <= conv_std_logic_vector(516,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(2115746,24); manlo <= conv_std_logic_vector(142837003,28); exponent <= conv_std_logic_vector(515,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(11024113,24); manlo <= conv_std_logic_vector(266701758,28); exponent <= conv_std_logic_vector(513,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(3677859,24); manlo <= conv_std_logic_vector(129840563,28); exponent <= conv_std_logic_vector(512,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(13322790,24); manlo <= conv_std_logic_vector(255615990,28); exponent <= conv_std_logic_vector(510,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(5369131,24); manlo <= conv_std_logic_vector(127156783,28); exponent <= conv_std_logic_vector(509,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(15811527,24); manlo <= conv_std_logic_vector(196077973,28); exponent <= conv_std_logic_vector(507,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(7200241,24); manlo <= conv_std_logic_vector(178260644,28); exponent <= conv_std_logic_vector(506,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(864411,24); manlo <= conv_std_logic_vector(121424610,28); exponent <= conv_std_logic_vector(505,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(9182752,24); manlo <= conv_std_logic_vector(52100447,28); exponent <= conv_std_logic_vector(503,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(2323061,24); manlo <= conv_std_logic_vector(49429697,28); exponent <= conv_std_logic_vector(502,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(11329181,24); manlo <= conv_std_logic_vector(50166358,28); exponent <= conv_std_logic_vector(500,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(3902315,24); manlo <= conv_std_logic_vector(102248985,28); exponent <= conv_std_logic_vector(499,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(13653081,24); manlo <= conv_std_logic_vector(212703346,28); exponent <= conv_std_logic_vector(497,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(5612145,24); manlo <= conv_std_logic_vector(239735388,28); exponent <= conv_std_logic_vector(496,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(16169127,24); manlo <= conv_std_logic_vector(205528034,28); exponent <= conv_std_logic_vector(494,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(7463349,24); manlo <= conv_std_logic_vector(17797346,28); exponent <= conv_std_logic_vector(493,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(1057995,24); manlo <= conv_std_logic_vector(16251369,28); exponent <= conv_std_logic_vector(492,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(9467613,24); manlo <= conv_std_logic_vector(244949044,28); exponent <= conv_std_logic_vector(490,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(2532650,24); manlo <= conv_std_logic_vector(194268012,28); exponent <= conv_std_logic_vector(489,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(11637595,24); manlo <= conv_std_logic_vector(246328755,28); exponent <= conv_std_logic_vector(487,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(4129234,24); manlo <= conv_std_logic_vector(69393408,28); exponent <= conv_std_logic_vector(486,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(13986996,24); manlo <= conv_std_logic_vector(255528468,28); exponent <= conv_std_logic_vector(484,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(5857826,24); manlo <= conv_std_logic_vector(251701587,28); exponent <= conv_std_logic_vector(483,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(16530651,24); manlo <= conv_std_logic_vector(211310789,28); exponent <= conv_std_logic_vector(481,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(7729343,24); manlo <= conv_std_logic_vector(154707528,28); exponent <= conv_std_logic_vector(480,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(1253702,24); manlo <= conv_std_logic_vector(237283577,28); exponent <= conv_std_logic_vector(479,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(9755601,24); manlo <= conv_std_logic_vector(121155884,28); exponent <= conv_std_logic_vector(477,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(2744540,24); manlo <= conv_std_logic_vector(30442277,28); exponent <= conv_std_logic_vector(476,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(11949394,24); manlo <= conv_std_logic_vector(246622503,28); exponent <= conv_std_logic_vector(474,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(4358643,24); manlo <= conv_std_logic_vector(38405425,28); exponent <= conv_std_logic_vector(473,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(14324576,24); manlo <= conv_std_logic_vector(53935566,28); exponent <= conv_std_logic_vector(471,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(6106203,24); manlo <= conv_std_logic_vector(233166714,28); exponent <= conv_std_logic_vector(470,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(59463,24); manlo <= conv_std_logic_vector(114545214,28); exponent <= conv_std_logic_vector(469,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(7998256,24); manlo <= conv_std_logic_vector(234808364,28); exponent <= conv_std_logic_vector(467,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(1451558,24); manlo <= conv_std_logic_vector(62230667,28); exponent <= conv_std_logic_vector(466,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(10046749,24); manlo <= conv_std_logic_vector(29683609,28); exponent <= conv_std_logic_vector(464,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(2958754,24); manlo <= conv_std_logic_vector(158313814,28); exponent <= conv_std_logic_vector(463,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(12264615,24); manlo <= conv_std_logic_vector(87551554,28); exponent <= conv_std_logic_vector(461,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(4590569,24); manlo <= conv_std_logic_vector(96025360,28); exponent <= conv_std_logic_vector(460,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(14665859,24); manlo <= conv_std_logic_vector(200220878,28); exponent <= conv_std_logic_vector(458,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(6357306,24); manlo <= conv_std_logic_vector(71997608,28); exponent <= conv_std_logic_vector(457,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(244214,24); manlo <= conv_std_logic_vector(66463607,28); exponent <= conv_std_logic_vector(456,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(8270120,24); manlo <= conv_std_logic_vector(265669912,28); exponent <= conv_std_logic_vector(454,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(1651584,24); manlo <= conv_std_logic_vector(179638473,28); exponent <= conv_std_logic_vector(453,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(10341091,24); manlo <= conv_std_logic_vector(152092530,28); exponent <= conv_std_logic_vector(451,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(3175319,24); manlo <= conv_std_logic_vector(178838140,28); exponent <= conv_std_logic_vector(450,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(12583294,24); manlo <= conv_std_logic_vector(183442082,28); exponent <= conv_std_logic_vector(448,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(4825040,24); manlo <= conv_std_logic_vector(141040370,28); exponent <= conv_std_logic_vector(447,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(15010888,24); manlo <= conv_std_logic_vector(62934477,28); exponent <= conv_std_logic_vector(445,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(6611164,24); manlo <= conv_std_logic_vector(11633311,28); exponent <= conv_std_logic_vector(444,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(430992,24); manlo <= conv_std_logic_vector(96770068,28); exponent <= conv_std_logic_vector(443,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(8544968,24); manlo <= conv_std_logic_vector(80768180,28); exponent <= conv_std_logic_vector(441,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(1853806,24); manlo <= conv_std_logic_vector(5288079,28); exponent <= conv_std_logic_vector(440,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(10638663,24); manlo <= conv_std_logic_vector(235213815,28); exponent <= conv_std_logic_vector(438,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(3394261,24); manlo <= conv_std_logic_vector(36557939,28); exponent <= conv_std_logic_vector(437,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(12905470,24); manlo <= conv_std_logic_vector(253900977,28); exponent <= conv_std_logic_vector(435,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(5062084,24); manlo <= conv_std_logic_vector(153603034,28); exponent <= conv_std_logic_vector(434,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(15359702,24); manlo <= conv_std_logic_vector(204098933,28); exponent <= conv_std_logic_vector(432,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(6867807,24); manlo <= conv_std_logic_vector(115170312,28); exponent <= conv_std_logic_vector(431,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(619820,24); manlo <= conv_std_logic_vector(2986045,28); exponent <= conv_std_logic_vector(430,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(8822831,24); manlo <= conv_std_logic_vector(145826716,28); exponent <= conv_std_logic_vector(428,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(2058246,24); manlo <= conv_std_logic_vector(98876593,28); exponent <= conv_std_logic_vector(427,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(10939501,24); manlo <= conv_std_logic_vector(129141213,28); exponent <= conv_std_logic_vector(425,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(3615605,24); manlo <= conv_std_logic_vector(20427716,28); exponent <= conv_std_logic_vector(424,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(13231182,24); manlo <= conv_std_logic_vector(130335695,28); exponent <= conv_std_logic_vector(422,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(5301729,24); manlo <= conv_std_logic_vector(196124198,28); exponent <= conv_std_logic_vector(421,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(15712344,24); manlo <= conv_std_logic_vector(233039482,28); exponent <= conv_std_logic_vector(419,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(7127266,24); manlo <= conv_std_logic_vector(266329205,28); exponent <= conv_std_logic_vector(418,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(810719,24); manlo <= conv_std_logic_vector(185030259,28); exponent <= conv_std_logic_vector(417,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(9103743,24); manlo <= conv_std_logic_vector(217685905,28); exponent <= conv_std_logic_vector(415,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(2264930,24); manlo <= conv_std_logic_vector(17303531,28); exponent <= conv_std_logic_vector(414,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(11243640,24); manlo <= conv_std_logic_vector(56799625,28); exponent <= conv_std_logic_vector(412,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(3839377,24); manlo <= conv_std_logic_vector(227776580,28); exponent <= conv_std_logic_vector(411,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(13560468,24); manlo <= conv_std_logic_vector(25616516,28); exponent <= conv_std_logic_vector(409,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(5544004,24); manlo <= conv_std_logic_vector(145740137,28); exponent <= conv_std_logic_vector(408,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(16068856,24); manlo <= conv_std_logic_vector(149889545,28); exponent <= conv_std_logic_vector(406,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(7389573,24); manlo <= conv_std_logic_vector(170431948,28); exponent <= conv_std_logic_vector(405,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(1003714,24); manlo <= conv_std_logic_vector(35324999,28); exponent <= conv_std_logic_vector(404,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(9387738,24); manlo <= conv_std_logic_vector(150667400,28); exponent <= conv_std_logic_vector(402,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(2473881,24); manlo <= conv_std_logic_vector(194497484,28); exponent <= conv_std_logic_vector(401,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(11551116,24); manlo <= conv_std_logic_vector(78219737,28); exponent <= conv_std_logic_vector(399,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(4065606,24); manlo <= conv_std_logic_vector(28280174,28); exponent <= conv_std_logic_vector(398,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(13893366,24); manlo <= conv_std_logic_vector(266881350,28); exponent <= conv_std_logic_vector(396,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(5788937,24); manlo <= conv_std_logic_vector(232096008,28); exponent <= conv_std_logic_vector(395,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(16429280,24); manlo <= conv_std_logic_vector(78498076,28); exponent <= conv_std_logic_vector(393,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(7654758,24); manlo <= conv_std_logic_vector(160696217,28); exponent <= conv_std_logic_vector(392,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(1198826,24); manlo <= conv_std_logic_vector(87006684,28); exponent <= conv_std_logic_vector(391,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(9674849,24); manlo <= conv_std_logic_vector(166079254,28); exponent <= conv_std_logic_vector(389,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(2685126,24); manlo <= conv_std_logic_vector(63154951,28); exponent <= conv_std_logic_vector(388,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(11861966,24); manlo <= conv_std_logic_vector(91696135,28); exponent <= conv_std_logic_vector(386,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(4294316,24); manlo <= conv_std_logic_vector(212296424,28); exponent <= conv_std_logic_vector(385,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(14229918,24); manlo <= conv_std_logic_vector(223047784,28); exponent <= conv_std_logic_vector(383,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(6036558,24); manlo <= conv_std_logic_vector(232962025,28); exponent <= conv_std_logic_vector(382,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(8221,24); manlo <= conv_std_logic_vector(133893557,28); exponent <= conv_std_logic_vector(381,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(7922853,24); manlo <= conv_std_logic_vector(125492404,28); exponent <= conv_std_logic_vector(379,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(1396079,24); manlo <= conv_std_logic_vector(135612572,28); exponent <= conv_std_logic_vector(378,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(9965111,24); manlo <= conv_std_logic_vector(47990958,28); exponent <= conv_std_logic_vector(376,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(2898688,24); manlo <= conv_std_logic_vector(203019642,28); exponent <= conv_std_logic_vector(375,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(12176227,24); manlo <= conv_std_logic_vector(103393586,28); exponent <= conv_std_logic_vector(373,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(4525537,24); manlo <= conv_std_logic_vector(38936964,28); exponent <= conv_std_logic_vector(372,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(14570163,24); manlo <= conv_std_logic_vector(185128905,28); exponent <= conv_std_logic_vector(370,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(6286897,24); manlo <= conv_std_logic_vector(12037044,28); exponent <= conv_std_logic_vector(369,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(192410,24); manlo <= conv_std_logic_vector(9691196,28); exponent <= conv_std_logic_vector(368,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(8193890,24); manlo <= conv_std_logic_vector(46224319,28); exponent <= conv_std_logic_vector(366,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(1595497,24); manlo <= conv_std_logic_vector(45130080,28); exponent <= conv_std_logic_vector(365,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(10258557,24); manlo <= conv_std_logic_vector(218068546,28); exponent <= conv_std_logic_vector(363,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(3114594,24); manlo <= conv_std_logic_vector(194203222,28); exponent <= conv_std_logic_vector(362,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(12493936,24); manlo <= conv_std_logic_vector(228530713,28); exponent <= conv_std_logic_vector(360,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(4759294,24); manlo <= conv_std_logic_vector(189728046,28); exponent <= conv_std_logic_vector(359,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(14914142,24); manlo <= conv_std_logic_vector(25337562,28); exponent <= conv_std_logic_vector(357,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(6539982,24); manlo <= conv_std_logic_vector(56762382,28); exponent <= conv_std_logic_vector(356,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(378619,24); manlo <= conv_std_logic_vector(186677702,28); exponent <= conv_std_logic_vector(355,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(8467900,24); manlo <= conv_std_logic_vector(266785510,28); exponent <= conv_std_logic_vector(353,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(1797103,24); manlo <= conv_std_logic_vector(17183357,28); exponent <= conv_std_logic_vector(352,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(10555224,24); manlo <= conv_std_logic_vector(126067134,28); exponent <= conv_std_logic_vector(350,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(3332869,24); manlo <= conv_std_logic_vector(228611260,28); exponent <= conv_std_logic_vector(349,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(12815132,24); manlo <= conv_std_logic_vector(155705738,28); exponent <= conv_std_logic_vector(347,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(4995617,24); manlo <= conv_std_logic_vector(85136440,28); exponent <= conv_std_logic_vector(346,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(15261895,24); manlo <= conv_std_logic_vector(3688335,28); exponent <= conv_std_logic_vector(344,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(6795844,24); manlo <= conv_std_logic_vector(137097782,28); exponent <= conv_std_logic_vector(343,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(566872,24); manlo <= conv_std_logic_vector(175764875,28); exponent <= conv_std_logic_vector(342,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(8744918,24); manlo <= conv_std_logic_vector(152414052,28); exponent <= conv_std_logic_vector(340,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(2000921,24); manlo <= conv_std_logic_vector(54921723,28); exponent <= conv_std_logic_vector(339,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(10855146,24); manlo <= conv_std_logic_vector(129996510,28); exponent <= conv_std_logic_vector(337,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(3553540,24); manlo <= conv_std_logic_vector(37023540,28); exponent <= conv_std_logic_vector(336,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(13139852,24); manlo <= conv_std_logic_vector(221848100,28); exponent <= conv_std_logic_vector(334,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(5234533,24); manlo <= conv_std_logic_vector(32943194,28); exponent <= conv_std_logic_vector(333,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(15613463,24); manlo <= conv_std_logic_vector(232436445,28); exponent <= conv_std_logic_vector(331,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(7054514,24); manlo <= conv_std_logic_vector(111791498,28); exponent <= conv_std_logic_vector(330,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(757191,24); manlo <= conv_std_logic_vector(90062360,28); exponent <= conv_std_logic_vector(329,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(9024975,24); manlo <= conv_std_logic_vector(238219590,28); exponent <= conv_std_logic_vector(327,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(2206975,24); manlo <= conv_std_logic_vector(232222812,28); exponent <= conv_std_logic_vector(326,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(11158359,24); manlo <= conv_std_logic_vector(155073518,28); exponent <= conv_std_logic_vector(324,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(3776631,24); manlo <= conv_std_logic_vector(232102510,28); exponent <= conv_std_logic_vector(323,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(13468136,24); manlo <= conv_std_logic_vector(71264246,28); exponent <= conv_std_logic_vector(321,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(5476070,24); manlo <= conv_std_logic_vector(155401688,28); exponent <= conv_std_logic_vector(320,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(15968890,24); manlo <= conv_std_logic_vector(140531032,28); exponent <= conv_std_logic_vector(318,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(7316022,24); manlo <= conv_std_logic_vector(197790036,28); exponent <= conv_std_logic_vector(317,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(949598,24); manlo <= conv_std_logic_vector(108723575,28); exponent <= conv_std_logic_vector(316,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(9308106,24); manlo <= conv_std_logic_vector(82754530,28); exponent <= conv_std_logic_vector(314,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(2415291,24); manlo <= conv_std_logic_vector(157597766,28); exponent <= conv_std_logic_vector(313,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(11464899,24); manlo <= conv_std_logic_vector(231735034,28); exponent <= conv_std_logic_vector(311,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(4002171,24); manlo <= conv_std_logic_vector(161749904,28); exponent <= conv_std_logic_vector(310,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(13800021,24); manlo <= conv_std_logic_vector(267486845,28); exponent <= conv_std_logic_vector(308,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(5720258,24); manlo <= conv_std_logic_vector(121711942,28); exponent <= conv_std_logic_vector(307,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(16328217,24); manlo <= conv_std_logic_vector(85566619,28); exponent <= conv_std_logic_vector(305,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(7580400,24); manlo <= conv_std_logic_vector(165916765,28); exponent <= conv_std_logic_vector(304,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(1144116,24); manlo <= conv_std_logic_vector(209234965,28); exponent <= conv_std_logic_vector(303,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(9594343,24); manlo <= conv_std_logic_vector(148128653,28); exponent <= conv_std_logic_vector(301,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(2625893,24); manlo <= conv_std_logic_vector(48717694,28); exponent <= conv_std_logic_vector(300,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(11774803,24); manlo <= conv_std_logic_vector(228357100,28); exponent <= conv_std_logic_vector(298,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(4230186,24); manlo <= conv_std_logic_vector(57439900,28); exponent <= conv_std_logic_vector(297,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(14135549,24); manlo <= conv_std_logic_vector(147041206,28); exponent <= conv_std_logic_vector(295,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(5967125,24); manlo <= conv_std_logic_vector(222682176,28); exponent <= conv_std_logic_vector(294,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(16691487,24); manlo <= conv_std_logic_vector(12959237,28); exponent <= conv_std_logic_vector(292,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(7847679,24); manlo <= conv_std_logic_vector(147174066,28); exponent <= conv_std_logic_vector(291,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(1340769,24); manlo <= conv_std_logic_vector(168148656,28); exponent <= conv_std_logic_vector(290,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(9883721,24); manlo <= conv_std_logic_vector(190474495,28); exponent <= conv_std_logic_vector(288,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(2838805,24); manlo <= conv_std_logic_vector(196335986,28); exponent <= conv_std_logic_vector(287,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(12088108,24); manlo <= conv_std_logic_vector(120857634,28); exponent <= conv_std_logic_vector(285,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(4460702,24); manlo <= conv_std_logic_vector(229771569,28); exponent <= conv_std_logic_vector(284,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(14474758,24); manlo <= conv_std_logic_vector(236628147,28); exponent <= conv_std_logic_vector(282,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(6216702,24); manlo <= conv_std_logic_vector(29481361,28); exponent <= conv_std_logic_vector(281,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(140763,24); manlo <= conv_std_logic_vector(131310533,28); exponent <= conv_std_logic_vector(280,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(8117891,24); manlo <= conv_std_logic_vector(96879140,28); exponent <= conv_std_logic_vector(278,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(1539580,24); manlo <= conv_std_logic_vector(98694067,28); exponent <= conv_std_logic_vector(277,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(10176275,24); manlo <= conv_std_logic_vector(66343668,28); exponent <= conv_std_logic_vector(275,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(3054054,24); manlo <= conv_std_logic_vector(159783892,28); exponent <= conv_std_logic_vector(274,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(12404850,24); manlo <= conv_std_logic_vector(262311967,28); exponent <= conv_std_logic_vector(272,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(4693748,24); manlo <= conv_std_logic_vector(264030756,28); exponent <= conv_std_logic_vector(271,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(14817690,24); manlo <= conv_std_logic_vector(106917994,28); exponent <= conv_std_logic_vector(269,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(6469017,24); manlo <= conv_std_logic_vector(5191992,28); exponent <= conv_std_logic_vector(268,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(326406,24); manlo <= conv_std_logic_vector(114083215,28); exponent <= conv_std_logic_vector(267,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(8391068,24); manlo <= conv_std_logic_vector(64117214,28); exponent <= conv_std_logic_vector(265,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(1740572,24); manlo <= conv_std_logic_vector(183091279,28); exponent <= conv_std_logic_vector(264,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(10472039,24); manlo <= conv_std_logic_vector(2244224,28); exponent <= conv_std_logic_vector(262,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(3271665,24); manlo <= conv_std_logic_vector(109958542,28); exponent <= conv_std_logic_vector(261,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(12725069,24); manlo <= conv_std_logic_vector(41968573,28); exponent <= conv_std_logic_vector(259,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(4929352,24); manlo <= conv_std_logic_vector(94809674,28); exponent <= conv_std_logic_vector(258,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(15164384,24); manlo <= conv_std_logic_vector(252890425,28); exponent <= conv_std_logic_vector(256,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(6724100,24); manlo <= conv_std_logic_vector(163583158,28); exponent <= conv_std_logic_vector(255,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(514086,24); manlo <= conv_std_logic_vector(118679222,28); exponent <= conv_std_logic_vector(254,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(8667242,24); manlo <= conv_std_logic_vector(192770478,28); exponent <= conv_std_logic_vector(252,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(1943770,24); manlo <= conv_std_logic_vector(136437165,28); exponent <= conv_std_logic_vector(251,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(10771048,24); manlo <= conv_std_logic_vector(58883744,28); exponent <= conv_std_logic_vector(249,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(3491664,24); manlo <= conv_std_logic_vector(24836209,28); exponent <= conv_std_logic_vector(248,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(13048801,24); manlo <= conv_std_logic_vector(33938829,28); exponent <= conv_std_logic_vector(246,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(5167541,24); manlo <= conv_std_logic_vector(6894318,28); exponent <= conv_std_logic_vector(245,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(15514883,24); manlo <= conv_std_logic_vector(216092120,28); exponent <= conv_std_logic_vector(243,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6981983,24); manlo <= conv_std_logic_vector(70071320,28); exponent <= conv_std_logic_vector(242,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(703825,24); manlo <= conv_std_logic_vector(239890498,28); exponent <= conv_std_logic_vector(241,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(8946447,24); manlo <= conv_std_logic_vector(185687386,28); exponent <= conv_std_logic_vector(239,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(2149198,24); manlo <= conv_std_logic_vector(12777107,28); exponent <= conv_std_logic_vector(238,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(11073338,24); manlo <= conv_std_logic_vector(132295567,28); exponent <= conv_std_logic_vector(236,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(3714076,24); manlo <= conv_std_logic_vector(227171857,28); exponent <= conv_std_logic_vector(235,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(13376085,24); manlo <= conv_std_logic_vector(119368169,28); exponent <= conv_std_logic_vector(233,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(5408343,24); manlo <= conv_std_logic_vector(99290689,28); exponent <= conv_std_logic_vector(232,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(15869228,24); manlo <= conv_std_logic_vector(196569651,28); exponent <= conv_std_logic_vector(230,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(7242695,24); manlo <= conv_std_logic_vector(184868911,28); exponent <= conv_std_logic_vector(229,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(895647,24); manlo <= conv_std_logic_vector(101480846,28); exponent <= conv_std_logic_vector(228,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(9228716,24); manlo <= conv_std_logic_vector(111040654,28); exponent <= conv_std_logic_vector(226,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(2356879,24); manlo <= conv_std_logic_vector(205878747,28); exponent <= conv_std_logic_vector(225,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(11378945,24); manlo <= conv_std_logic_vector(223412824,28); exponent <= conv_std_logic_vector(223,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(3938930,24); manlo <= conv_std_logic_vector(43159582,28); exponent <= conv_std_logic_vector(222,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(13706961,24); manlo <= conv_std_logic_vector(24539717,28); exponent <= conv_std_logic_vector(220,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(5651788,24); manlo <= conv_std_logic_vector(17696328,28); exponent <= conv_std_logic_vector(219,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(16227461,24); manlo <= conv_std_logic_vector(248897772,28); exponent <= conv_std_logic_vector(217,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(7506268,24); manlo <= conv_std_logic_vector(253353585,28); exponent <= conv_std_logic_vector(216,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(1089573,24); manlo <= conv_std_logic_vector(199085712,28); exponent <= conv_std_logic_vector(215,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(9514082,24); manlo <= conv_std_logic_vector(134954983,28); exponent <= conv_std_logic_vector(213,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(2566840,24); manlo <= conv_std_logic_vector(107836942,28); exponent <= conv_std_logic_vector(212,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(11687906,24); manlo <= conv_std_logic_vector(170784064,28); exponent <= conv_std_logic_vector(210,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(4166250,24); manlo <= conv_std_logic_vector(219198631,28); exponent <= conv_std_logic_vector(209,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(14041467,24); manlo <= conv_std_logic_vector(127426909,28); exponent <= conv_std_logic_vector(207,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(5897904,24); manlo <= conv_std_logic_vector(29159081,28); exponent <= conv_std_logic_vector(206,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(16589626,24); manlo <= conv_std_logic_vector(15093248,28); exponent <= conv_std_logic_vector(204,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(7772734,24); manlo <= conv_std_logic_vector(112367334,28); exponent <= conv_std_logic_vector(203,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(1285628,24); manlo <= conv_std_logic_vector(21894417,28); exponent <= conv_std_logic_vector(202,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(9802579,24); manlo <= conv_std_logic_vector(254146435,28); exponent <= conv_std_logic_vector(200,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(2779104,24); manlo <= conv_std_logic_vector(257348234,28); exponent <= conv_std_logic_vector(199,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(12000257,24); manlo <= conv_std_logic_vector(188607876,28); exponent <= conv_std_logic_vector(197,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(4396065,24); manlo <= conv_std_logic_vector(238395052,28); exponent <= conv_std_logic_vector(196,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(14379644,24); manlo <= conv_std_logic_vector(116776141,28); exponent <= conv_std_logic_vector(194,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(6146720,24); manlo <= conv_std_logic_vector(217697734,28); exponent <= conv_std_logic_vector(193,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(89274,24); manlo <= conv_std_logic_vector(34078121,28); exponent <= conv_std_logic_vector(192,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(8042123,24); manlo <= conv_std_logic_vector(228091050,28); exponent <= conv_std_logic_vector(190,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(1483833,24); manlo <= conv_std_logic_vector(200872250,28); exponent <= conv_std_logic_vector(189,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(10094243,24); manlo <= conv_std_logic_vector(28573613,28); exponent <= conv_std_logic_vector(187,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(2993698,24); manlo <= conv_std_logic_vector(193026703,28); exponent <= conv_std_logic_vector(186,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(12316036,24); manlo <= conv_std_logic_vector(62602992,28); exponent <= conv_std_logic_vector(184,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(4628402,24); manlo <= conv_std_logic_vector(200475490,28); exponent <= conv_std_logic_vector(183,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(14721532,24); manlo <= conv_std_logic_vector(67122338,28); exponent <= conv_std_logic_vector(181,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(6398267,24); manlo <= conv_std_logic_vector(216803728,28); exponent <= conv_std_logic_vector(180,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(274352,24); manlo <= conv_std_logic_vector(17200594,28); exponent <= conv_std_logic_vector(179,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(8314469,24); manlo <= conv_std_logic_vector(86446456,28); exponent <= conv_std_logic_vector(177,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(1684214,24); manlo <= conv_std_logic_vector(93587914,28); exponent <= conv_std_logic_vector(176,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(10389106,24); manlo <= conv_std_logic_vector(193148951,28); exponent <= conv_std_logic_vector(174,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(3210647,24); manlo <= conv_std_logic_vector(64824977,28); exponent <= conv_std_logic_vector(173,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(12635279,24); manlo <= conv_std_logic_vector(224939505,28); exponent <= conv_std_logic_vector(171,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(4863289,24); manlo <= conv_std_logic_vector(17355920,28); exponent <= conv_std_logic_vector(170,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(15067171,24); manlo <= conv_std_logic_vector(171641236,28); exponent <= conv_std_logic_vector(168,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(6652575,24); manlo <= conv_std_logic_vector(15694991,28); exponent <= conv_std_logic_vector(167,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(461460,24); manlo <= conv_std_logic_vector(236949593,28); exponent <= conv_std_logic_vector(166,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(8589803,24); manlo <= conv_std_logic_vector(73170085,28); exponent <= conv_std_logic_vector(164,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(1886793,24); manlo <= conv_std_logic_vector(200887360,28); exponent <= conv_std_logic_vector(163,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(10687205,24); manlo <= conv_std_logic_vector(242930225,28); exponent <= conv_std_logic_vector(161,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(3429976,24); manlo <= conv_std_logic_vector(97980458,28); exponent <= conv_std_logic_vector(160,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(12958026,24); manlo <= conv_std_logic_vector(144828568,28); exponent <= conv_std_logic_vector(158,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(5100752,24); manlo <= conv_std_logic_vector(219332721,28); exponent <= conv_std_logic_vector(157,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(15416603,24); manlo <= conv_std_logic_vector(206580322,28); exponent <= conv_std_logic_vector(155,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6909672,24); manlo <= conv_std_logic_vector(228709240,28); exponent <= conv_std_logic_vector(154,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(650622,24); manlo <= conv_std_logic_vector(232984198,28); exponent <= conv_std_logic_vector(153,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(8868158,24); manlo <= conv_std_logic_vector(132673062,28); exponent <= conv_std_logic_vector(151,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(2091596,24); manlo <= conv_std_logic_vector(20173170,28); exponent <= conv_std_logic_vector(150,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(10988576,24); manlo <= conv_std_logic_vector(44856082,28); exponent <= conv_std_logic_vector(148,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(3651712,24); manlo <= conv_std_logic_vector(56970522,28); exponent <= conv_std_logic_vector(147,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(13284314,24); manlo <= conv_std_logic_vector(208786223,28); exponent <= conv_std_logic_vector(145,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(5340822,24); manlo <= conv_std_logic_vector(76928898,28); exponent <= conv_std_logic_vector(144,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(15769870,24); manlo <= conv_std_logic_vector(69445892,28); exponent <= conv_std_logic_vector(142,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(7169591,24); manlo <= conv_std_logic_vector(217224162,28); exponent <= conv_std_logic_vector(141,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(841860,24); manlo <= conv_std_logic_vector(147476782,28); exponent <= conv_std_logic_vector(140,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(9149568,24); manlo <= conv_std_logic_vector(37524984,28); exponent <= conv_std_logic_vector(138,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(2298645,24); manlo <= conv_std_logic_vector(193659590,28); exponent <= conv_std_logic_vector(137,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(11293253,24); manlo <= conv_std_logic_vector(107316618,28); exponent <= conv_std_logic_vector(135,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(3875881,24); manlo <= conv_std_logic_vector(51654059,28); exponent <= conv_std_logic_vector(134,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(13614183,24); manlo <= conv_std_logic_vector(111249634,28); exponent <= conv_std_logic_vector(132,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(5583526,24); manlo <= conv_std_logic_vector(17717412,28); exponent <= conv_std_logic_vector(131,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(16127013,24); manlo <= conv_std_logic_vector(48769099,28); exponent <= conv_std_logic_vector(129,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(7432362,24); manlo <= conv_std_logic_vector(238120049,28); exponent <= conv_std_logic_vector(128,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(1035196,24); manlo <= conv_std_logic_vector(188962402,28); exponent <= conv_std_logic_vector(127,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(9434065,24); manlo <= conv_std_logic_vector(194820226,28); exponent <= conv_std_logic_vector(125,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(2507967,24); manlo <= conv_std_logic_vector(93233285,28); exponent <= conv_std_logic_vector(124,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(11601273,24); manlo <= conv_std_logic_vector(239123672,28); exponent <= conv_std_logic_vector(122,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(4102510,24); manlo <= conv_std_logic_vector(1244898,28); exponent <= conv_std_logic_vector(121,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(13947671,24); manlo <= conv_std_logic_vector(197996828,28); exponent <= conv_std_logic_vector(119,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(5828893,24); manlo <= conv_std_logic_vector(16622593,28); exponent <= conv_std_logic_vector(118,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(16488075,24); manlo <= conv_std_logic_vector(20144764,28); exponent <= conv_std_logic_vector(116,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(7698017,24); manlo <= conv_std_logic_vector(102592250,28); exponent <= conv_std_logic_vector(115,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(1230654,24); manlo <= conv_std_logic_vector(96196092,28); exponent <= conv_std_logic_vector(114,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(9721685,24); manlo <= conv_std_logic_vector(36636777,28); exponent <= conv_std_logic_vector(112,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(2719585,24); manlo <= conv_std_logic_vector(237160861,28); exponent <= conv_std_logic_vector(111,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(11912674,24); manlo <= conv_std_logic_vector(87541902,28); exponent <= conv_std_logic_vector(109,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(4331625,24); manlo <= conv_std_logic_vector(172036325,28); exponent <= conv_std_logic_vector(108,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(14284819,24); manlo <= conv_std_logic_vector(125225503,28); exponent <= conv_std_logic_vector(106,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(6076952,24); manlo <= conv_std_logic_vector(133715238,28); exponent <= conv_std_logic_vector(105,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(37941,24); manlo <= conv_std_logic_vector(126448851,28); exponent <= conv_std_logic_vector(104,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(7966586,24); manlo <= conv_std_logic_vector(250893596,28); exponent <= conv_std_logic_vector(102,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(1428256,24); manlo <= conv_std_logic_vector(212630882,28); exponent <= conv_std_logic_vector(101,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(10012460,24); manlo <= conv_std_logic_vector(168603206,28); exponent <= conv_std_logic_vector(99,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(2933526,24); manlo <= conv_std_logic_vector(143402282,28); exponent <= conv_std_logic_vector(98,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(12227491,24); manlo <= conv_std_logic_vector(213203509,28); exponent <= conv_std_logic_vector(96,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(4563255,24); manlo <= conv_std_logic_vector(104522224,28); exponent <= conv_std_logic_vector(95,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(14625666,24); manlo <= conv_std_logic_vector(203000190,28); exponent <= conv_std_logic_vector(93,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(6327733,24); manlo <= conv_std_logic_vector(246711469,28); exponent <= conv_std_logic_vector(92,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(222456,24); manlo <= conv_std_logic_vector(34640152,28); exponent <= conv_std_logic_vector(91,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(8238103,24); manlo <= conv_std_logic_vector(142733230,28); exponent <= conv_std_logic_vector(89,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(1628027,24); manlo <= conv_std_logic_vector(144984792,28); exponent <= conv_std_logic_vector(88,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(10306426,24); manlo <= conv_std_logic_vector(223510234,28); exponent <= conv_std_logic_vector(86,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(3149814,24); manlo <= conv_std_logic_vector(209464872,28); exponent <= conv_std_logic_vector(85,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(12545763,24); manlo <= conv_std_logic_vector(212245812,28); exponent <= conv_std_logic_vector(83,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(4797426,24); manlo <= conv_std_logic_vector(224882259,28); exponent <= conv_std_logic_vector(82,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(14970254,24); manlo <= conv_std_logic_vector(54358776,28); exponent <= conv_std_logic_vector(80,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(6581267,24); manlo <= conv_std_logic_vector(51917314,28); exponent <= conv_std_logic_vector(79,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(408995,24); manlo <= conv_std_logic_vector(130890803,28); exponent <= conv_std_logic_vector(78,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(8512599,24); manlo <= conv_std_logic_vector(137347476,28); exponent <= conv_std_logic_vector(76,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(1829990,24); manlo <= conv_std_logic_vector(106170554,28); exponent <= conv_std_logic_vector(75,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(10603618,24); manlo <= conv_std_logic_vector(204595238,28); exponent <= conv_std_logic_vector(73,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(3368476,24); manlo <= conv_std_logic_vector(102605239,28); exponent <= conv_std_logic_vector(72,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(12867528,24); manlo <= conv_std_logic_vector(59687307,28); exponent <= conv_std_logic_vector(70,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(5034167,24); manlo <= conv_std_logic_vector(235251142,28); exponent <= conv_std_logic_vector(69,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(15318622,24); manlo <= conv_std_logic_vector(227223140,28); exponent <= conv_std_logic_vector(67,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(6837582,24); manlo <= conv_std_logic_vector(138925467,28); exponent <= conv_std_logic_vector(66,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(597581,24); manlo <= conv_std_logic_vector(205088968,28); exponent <= conv_std_logic_vector(65,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(8790107,24); manlo <= conv_std_logic_vector(152356460,28); exponent <= conv_std_logic_vector(63,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(2034169,24); manlo <= conv_std_logic_vector(110749946,28); exponent <= conv_std_logic_vector(62,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(10904071,24); manlo <= conv_std_logic_vector(218226183,28); exponent <= conv_std_logic_vector(60,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(3589537,24); manlo <= conv_std_logic_vector(102830143,28); exponent <= conv_std_logic_vector(59,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(13192823,24); manlo <= conv_std_logic_vector(110639602,28); exponent <= conv_std_logic_vector(57,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(5273506,24); manlo <= conv_std_logic_vector(188352155,28); exponent <= conv_std_logic_vector(56,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(15670814,24); manlo <= conv_std_logic_vector(48227643,28); exponent <= conv_std_logic_vector(54,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(7096710,24); manlo <= conv_std_logic_vector(112532514,28); exponent <= conv_std_logic_vector(53,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(788237,24); manlo <= conv_std_logic_vector(112565412,28); exponent <= conv_std_logic_vector(52,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(9070660,24); manlo <= conv_std_logic_vector(201680253,28); exponent <= conv_std_logic_vector(50,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(2240588,24); manlo <= conv_std_logic_vector(244138286,28); exponent <= conv_std_logic_vector(49,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(11207821,24); manlo <= conv_std_logic_vector(206597824,28); exponent <= conv_std_logic_vector(47,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(3813024,24); manlo <= conv_std_logic_vector(29987310,28); exponent <= conv_std_logic_vector(46,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(13521688,24); manlo <= conv_std_logic_vector(27790821,28); exponent <= conv_std_logic_vector(44,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(5515471,24); manlo <= conv_std_logic_vector(219963166,28); exponent <= conv_std_logic_vector(43,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(16026870,24); manlo <= conv_std_logic_vector(39964772,28); exponent <= conv_std_logic_vector(41,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(7358681,24); manlo <= conv_std_logic_vector(204327682,28); exponent <= conv_std_logic_vector(40,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(980985,24); manlo <= conv_std_logic_vector(43247066,28); exponent <= conv_std_logic_vector(39,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(9354292,24); manlo <= conv_std_logic_vector(128160132,28); exponent <= conv_std_logic_vector(37,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(2449273,24); manlo <= conv_std_logic_vector(126511008,28); exponent <= conv_std_logic_vector(36,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(11514904,24); manlo <= conv_std_logic_vector(217311246,28); exponent <= conv_std_logic_vector(34,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(4038963,24); manlo <= conv_std_logic_vector(49913566,28); exponent <= conv_std_logic_vector(33,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(13854161,24); manlo <= conv_std_logic_vector(124821568,28); exponent <= conv_std_logic_vector(31,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(5760092,24); manlo <= conv_std_logic_vector(12957085,28); exponent <= conv_std_logic_vector(30,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(16386833,24); manlo <= conv_std_logic_vector(43278038,28); exponent <= conv_std_logic_vector(28,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(7623527,24); manlo <= conv_std_logic_vector(199937734,28); exponent <= conv_std_logic_vector(27,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(1175847,24); manlo <= conv_std_logic_vector(253947561,28); exponent <= conv_std_logic_vector(26,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(9641036,24); manlo <= conv_std_logic_vector(141497796,28); exponent <= conv_std_logic_vector(24,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(2660247,24); manlo <= conv_std_logic_vector(255766959,28); exponent <= conv_std_logic_vector(23,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(11825357,24); manlo <= conv_std_logic_vector(136095046,28); exponent <= conv_std_logic_vector(21,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(4267381,24); manlo <= conv_std_logic_vector(138414926,28); exponent <= conv_std_logic_vector(20,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(14190283,24); manlo <= conv_std_logic_vector(25479908,28); exponent <= conv_std_logic_vector(18,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(6007396,24); manlo <= conv_std_logic_vector(140400514,28); exponent <= conv_std_logic_vector(17,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(16750746,24); manlo <= conv_std_logic_vector(23924155,28); exponent <= conv_std_logic_vector(15,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(7891279,24); manlo <= conv_std_logic_vector(245330892,28); exponent <= conv_std_logic_vector(14,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(1372848,24); manlo <= conv_std_logic_vector(263794815,28); exponent <= conv_std_logic_vector(13,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(9930927,24); manlo <= conv_std_logic_vector(14029030,28); exponent <= conv_std_logic_vector(11,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(2873537,24); manlo <= conv_std_logic_vector(129274844,28); exponent <= conv_std_logic_vector(10,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(12139216,24); manlo <= conv_std_logic_vector(224845565,28); exponent <= conv_std_logic_vector(8,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(4498306,24); manlo <= conv_std_logic_vector(82126943,28); exponent <= conv_std_logic_vector(7,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(14530093,24); manlo <= conv_std_logic_vector(7024665,28); exponent <= conv_std_logic_vector(5,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(6257414,24); manlo <= conv_std_logic_vector(187437029,28); exponent <= conv_std_logic_vector(4,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(170718,24); manlo <= conv_std_logic_vector(36971864,28); exponent <= conv_std_logic_vector(3,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(8161970,24); manlo <= conv_std_logic_vector(42518955,28); exponent <= conv_std_logic_vector(1,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(1572011,24); manlo <= conv_std_logic_vector(197150320,28); exponent <= conv_std_logic_vector(0,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/dp_log.vhd	10	10521	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* DOUBLE PRECISION LOG(LN) - TOP LEVEL * --* * --* DP_LOG.VHD * --* * --* Function: IEEE754 DP LN() * --* * --* 11/08/09 ML * --* * --* (c) 2009 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --*********************************************** --*********************************************** --* Notes: * --* Latency = 27 + 7DoubleSpeed + --* RoundConvert(1+DoubleSpeed) --* DoubleSpeed = 0, RoundConvert = 0 : 27 * --* DoubleSpeed = 1, RoundConvert = 0 : 34 * --* DoubleSpeed = 0, RoundConvert = 1 : 28 * --* DoubleSpeed = 1, RoundConvert = 1 : 36 * --* * --************************************************* ENTITY dp_log IS GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); END dp_log; ARCHITECTURE rtl OF dp_log IS constant expwidth : positive := 11; constant manwidth : positive := 52; constant coredepth : positive := 26 + 7doublespeed; signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal signnode : STD_LOGIC; signal mantissanode : STD_LOGIC_VECTOR (53 DOWNTO 1); signal exponentnode : STD_LOGIC_VECTOR (11 DOWNTO 1); signal zeronode : STD_LOGIC; -- conditions signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zeromaninff : STD_LOGIC; signal zeroexpinff : STD_LOGIC; signal maxexpinff : STD_LOGIC; signal naninff : STD_LOGIC; signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1); signal infinityinff : STD_LOGIC; signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1); component dp_ln_core GENERIC ( doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1); aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1); ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1); ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); ccsgn : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_lnnornd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signln : IN STD_LOGIC; exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; infinityin : IN STD_LOGIC; zeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_lnrnd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signln : IN STD_LOGIC; exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; infinityin : IN STD_LOGIC; zeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_lnrndpipe PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signln : IN STD_LOGIC; exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; infinityin : IN STD_LOGIC; zeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; BEGIN pma: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO manwidth LOOP maninff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP expinff(k) <= '0'; END LOOP; signinff <= "00"; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN maninff <= mantissain; expinff <= exponentin; signinff(1) <= signin; signinff(2) <= signinff(1); END IF; END IF; END PROCESS; --***************** --* CHECK INPUTS * --**************** zeroman(1) <= maninff(1); gca: FOR k IN 2 TO manwidth GENERATE zeroman(k) <= zeroman(k-1) OR maninff(k); END GENERATE; zeroexp(1) <= expinff(1); gcb: FOR k IN 2 TO expwidth GENERATE zeroexp(k) <= zeroexp(k-1) OR expinff(k); END GENERATE; maxexp(1) <= expinff(1); gcc: FOR k IN 2 TO expwidth GENERATE maxexp(k) <= maxexp(k-1) AND expinff(k); END GENERATE; pcc: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN zeromaninff <= '0'; zeroexpinff <= '0'; maxexpinff <= '0'; naninff <= '0'; FOR k IN 1 TO coredepth-3 LOOP nanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN zeromaninff <= NOT(zeroman(manwidth)); zeroexpinff <= NOT(zeroexp(expwidth)); maxexpinff <= maxexp(expwidth); -- infinity when exp = zero -- nan when man != 0, exp = max -- all ffs '1' when condition true naninff <= (zeromaninff AND maxexpinff) OR signinff(2); infinityinff <= zeroexpinff OR maxexpinff; -- nan output when nan input nanff(1) <= naninff; FOR k IN 2 TO coredepth-3 LOOP nanff(k) <= nanff(k-1); END LOOP; infinityff(1) <= infinityinff; FOR k IN 2 TO coredepth-3 LOOP infinityff(k) <= infinityff(k-1); END LOOP; END IF; END IF; END PROCESS; --*********** --* LN CORE * --*********** lncore: dp_ln_core GENERIC MAP (doublespeed=>doublespeed,device=>device,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aaman=>mantissain,aaexp=>exponentin, ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode, zeroout=>zeronode); --******************** --* ROUND AND OUTPUT * --********************** gra: IF (roundconvert = 0) GENERATE norndout: dp_lnnornd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signln=>signnode, exponentln=>exponentnode, mantissaln=>mantissanode, nanin=>nanff(coredepth-3), infinityin=>infinityff(coredepth-3), zeroin=>zeronode, signout=>signout, exponentout=>exponentout, mantissaout=>mantissaout, nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout); END GENERATE; grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE rndout: dp_lnrnd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signln=>signnode, exponentln=>exponentnode, mantissaln=>mantissanode, nanin=>nanff(coredepth-3), infinityin=>infinityff(coredepth-3), zeroin=>zeronode, signout=>signout, exponentout=>exponentout, mantissaout=>mantissaout, nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout); END GENERATE; grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE rndoutpipe: dp_lnrndpipe PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signln=>signnode, exponentln=>exponentnode, mantissaln=>mantissanode, nanin=>nanff(coredepth-3), infinityin=>infinityff(coredepth-3), zeroin=>zeronode, signout=>signout, exponentout=>exponentout, mantissaout=>mantissaout, nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout); END GENERATE; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_scmul3236.vhd	10	4216	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_SCMUL3236.VHD * --* * --* Function: Scale (normalized for overflow * --* only) a 32 or 36 bit mantissa * --* * --* 14/07/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY hcc_scmul3236 IS GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); END hcc_scmul3236; ARCHITECTURE rtl OF hcc_scmul3236 IS signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1); BEGIN -- for single 32 bit mantissa input -- [S ][O....O][1 ][M...M][RGS] -- [32][31..28][27][26..4][321] - NB underflow can run into RGS -- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..]..... -- output -- [S ][1 ][M...M] -- [32][31][30..1], count is shift -- for single 36 bit mantissa -- [S ][O....O][1 ][M...M][O..O][RGS] -- [36][35..32][31][30..8][7..4][321] -- shift 0 if "01XX" or "10XX" scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1))); -- shift 1 if "001XX" or "110XX" scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR (frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2))); -- shift 2 if "0001XX" or "1110XX" scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR (frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3))); -- shift 3 if "00001XX" or "11110XX" scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR (frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND frac(mantissa-3) AND NOT(frac(mantissa-4))); -- shift 4 if "00000XX" or "11111XX" scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR (frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND frac(mantissa-3) AND frac(mantissa-4)); scaled(mantissa) <= frac(mantissa); gsa: FOR k IN 1 TO mantissa-5 GENERATE scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR (frac(mantissa-k-3) AND scale(2)) OR (frac(mantissa-k-2) AND scale(3)) OR (frac(mantissa-k-1) AND scale(4)) OR (frac(mantissa-k) AND scale(5)); END GENERATE; scaled(4) <= (frac(1) AND scale(2)) OR (frac(2) AND scale(3)) OR (frac(3) AND scale(4)) OR (frac(4) AND scale(5)); scaled(3) <= (frac(1) AND scale(3)) OR (frac(2) AND scale(4)) OR (frac(3) AND scale(5)); scaled(2) <= (frac(1) AND scale(4)) OR (frac(2) AND scale(5)); scaled(1) <= (frac(1) AND scale(5)); -- shifts everything to SSSSS1XXXXX -- if '1' is in a position greater than 27,add to exponent count(3) <= scale(5); count(2) <= scale(4) OR scale(3); count(1) <= scale(4) OR scale(2); END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_sqr.vhd	10	9456	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* SINGLE PRECISION SQUARE ROOT - TOP LEVEL * --* * --* FP_SQR.VHD * --* * --* Function: IEEE754 FP Square Root * --* * --* 31/01/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --*********************************************** --*********************************************** --* Notes: * --* Latency = 28 * --* Based on FPROOT1.VHD (12/06) * --*********************************************** ENTITY fp_sqr IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); END fp_sqr; ARCHITECTURE rtl OF fp_sqr IS constant manwidth : positive := 23; constant expwidth : positive := 8; type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal signinff : STD_LOGIC; signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1); signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal expff : expfftype; signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1); signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1); signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal roundbit : STD_LOGIC; signal preadjust : STD_LOGIC; signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1); -- conditions signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1); signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1); signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expzero, expmax, manzero : STD_LOGIC; signal infinitycondition, nancondition : STD_LOGIC; component fp_sqrroot IS GENERIC (width : positive := 52); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1); root : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gzva: FOR k IN 1 TO manwidth GENERATE zerovec(k) <= '0'; END GENERATE; gxoa: FOR k IN 1 TO expwidth-1 GENERATE offset(k) <= '1'; END GENERATE; offset(expwidth) <= '0'; pma: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN signinff <= '0'; FOR k IN 1 TO manwidth LOOP maninff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP expinff(k) <= '0'; END LOOP; FOR k IN 1 TO manwidth+4 LOOP signff(k) <= '0'; END LOOP; FOR k IN 1 TO manwidth+4 LOOP FOR j IN 1 TO expwidth LOOP expff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO manwidth LOOP roundff(k) <= '0'; manff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN signinff <= signin; maninff <= mantissain; expinff <= exponentin; signff(1) <= signinff; FOR k IN 2 TO manwidth+4 LOOP signff(k) <= signff(k-1); END LOOP; expff(1)(expwidth DOWNTO 1) <= expdiv; expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset; FOR k IN 3 TO manwidth+3 LOOP expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1); END LOOP; FOR k IN 1 TO expwidth LOOP expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3); END LOOP; roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit); FOR k IN 1 TO manwidth LOOP manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3); END LOOP; END IF; END PROCESS; --*************** --* CONDITIONS * --*************** pcc: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO manwidth+4 LOOP nanmanff(k) <= '0'; nanexpff(k) <= '0'; END LOOP; FOR k IN 1 TO manwidth+3 LOOP zeroexpff(k) <= '0'; zeromanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN nanmanff(1) <= nancondition; -- level 1 nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity FOR k IN 2 TO manwidth+4 LOOP nanmanff(k) <= nanmanff(k-1); nanexpff(k) <= nanexpff(k-1); END LOOP; zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1 zeroexpff(1) <= expzero; -- level 1 FOR k IN 2 TO manwidth+3 LOOP zeromanff(k) <= zeromanff(k-1); zeroexpff(k) <= zeroexpff(k-1); END LOOP; END IF; END PROCESS; --*************** --* SQUARE ROOT * --*************** -- if exponent is odd, double mantissa and adjust exponent -- core latency manwidth+2 = 25 -- top latency = core + 1 (input) + 2 (output) = 28 sqr: fp_sqrroot GENERIC MAP (width=>manwidth+2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, rad=>radicand, root=>squareroot); radicand(1) <= '0'; radicand(2) <= maninff(1) AND NOT(preadjust); gra: FOR k IN 3 TO manwidth+1 GENERATE radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust); END GENERATE; radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust); radicand(manwidth+3) <= preadjust; --************ --* EXPONENT * --************ -- subtract 1023, divide result/2, if odd - preadjust -- if zero input, zero exponent and mantissa expnode <= expinff - offset; preadjust <= expnode(1); expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2); --********* --* ROUND * --********* -- only need to round up, round to nearest not possible out of root roundbit <= squareroot(1); --***************** --* SPECIAL CASES * --***************** -- 1. if negative input, invalid operation, NAN (unless -0) -- 2. -0 in -0 out -- 3. infinity in, invalid operation, infinity out -- 4. NAN in, invalid operation, NAN -- '0' if 0 expinzero(1) <= expinff(1); gxza: FOR k IN 2 TO expwidth GENERATE expinzero(k) <= expinzero(k-1) OR expinff(k); END GENERATE; expzero <= expinzero(expwidth); -- '0' when zero -- '1' if nan or infinity expinmax(1) <= expinff(1); gxia: FOR k IN 2 TO expwidth GENERATE expinmax(k) <= expinmax(k-1) AND expinff(k); END GENERATE; expmax <= expinmax(expwidth); -- '1' when true -- '1' if not zero or infinity maninzero(1) <= maninff(1); gmza: FOR k IN 2 TO manwidth GENERATE maninzero(k) <= maninzero(k-1) OR maninff(k); END GENERATE; manzero <= maninzero(manwidth); infinitycondition <= NOT(manzero) AND expmax; nancondition <= (signinff AND expzero) OR (expmax AND manzero); --*********** --* OUTPUTS * --************* signout <= signff(manwidth+4); exponentout <= expff(manwidth+4)(expwidth DOWNTO 1); mantissaout <= manff; ----------------------------------------------- nanout <= nanmanff(manwidth+4); invalidout <= nanmanff(manwidth+4); END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_arcsinpi_s5.vhd	10	575341	----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_arcsinpi_s5 -- VHDL created on Thu Feb 28 17:21:04 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_arcsinpi_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_arcsinpi_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstBiasM2_uid6_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal ooPi_uid9_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cstBias_uid22_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(10 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(10 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (10 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n : std_logic_vector (0 downto 0); signal shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (12 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a : std_logic_vector (23 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (25 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 : std_logic_vector (49 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr : UNSIGNED (49 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (49 downto 0); signal z2_uid93_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (1 downto 0); signal piO2_uid101_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (27 downto 0); signal fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (9 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (10 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector (23 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (47 downto 0); signal roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (11 downto 0); signal leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (15 downto 0); signal maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a : std_logic_vector (17 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 : std_logic_vector (38 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr : SIGNED (39 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q : std_logic_vector (38 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_b : std_logic_vector (24 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 : std_logic_vector (41 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr : SIGNED (42 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_q : std_logic_vector (41 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid400_arcsinXTabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid401_arcsinXTabGen_lutmem_ia : std_logic_vector (22 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_iq : std_logic_vector (22 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_q : std_logic_vector (22 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid402_arcsinXTabGen_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_q : std_logic_vector (12 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid422_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid423_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid424_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0); signal reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (2 downto 0); signal reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q : std_logic_vector (36 downto 0); signal reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0); signal reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q : std_logic_vector (17 downto 0); signal reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0); signal reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (23 downto 0); signal reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (25 downto 0); signal reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (31 downto 0); signal reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (15 downto 0); signal reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (3 downto 0); signal reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0); signal reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (0 downto 0); signal reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (5 downto 0); signal reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (22 downto 0); signal reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (22 downto 0); signal reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (3 downto 0); signal reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0); signal reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0); signal reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0); signal reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (7 downto 0); signal reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (25 downto 0); signal reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (25 downto 0); signal reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q : std_logic_vector (25 downto 0); signal reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q : std_logic_vector (25 downto 0); signal reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q : std_logic_vector (24 downto 0); signal reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (27 downto 0); signal reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (11 downto 0); signal reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q : std_logic_vector (2 downto 0); signal reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q : std_logic_vector (22 downto 0); signal reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q : std_logic_vector (7 downto 0); signal ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0); signal ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0); signal ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (25 downto 0); signal ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (8 downto 0); signal ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q : std_logic_vector (5 downto 0); signal ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0); signal ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q : std_logic_vector (11 downto 0); signal ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q : std_logic_vector (0 downto 0); signal ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q : std_logic_vector (22 downto 0); signal ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q : std_logic_vector (4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : signal is true; signal ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (25 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 : std_logic; signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : signal is true; signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 : std_logic; signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q : std_logic_vector (22 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq : std_logic; signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : signal is true; signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 : std_logic; signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : signal is true; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 : std_logic; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : signal is true; signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 : std_logic; signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : signal is true; signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : signal is true; signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 : std_logic; signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : signal is true; signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : signal is true; signal ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : signal is true; signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q : signal is true; signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia : std_logic_vector (16 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq : std_logic_vector (16 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q : std_logic_vector (16 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q : signal is true; signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0); signal ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0 : std_logic; signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq : std_logic; signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q : signal is true; signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q : signal is true; signal pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (35 downto 0); signal excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n : std_logic_vector (0 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c : std_logic_vector (0 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (32 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (32 downto 0); signal InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal expX_uid15_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expX_uid15_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid16_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid16_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal singX_uid17_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal singX_uid17_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(10 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(10 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (10 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_c : std_logic_vector (0 downto 0); signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(28 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(28 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (28 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (28 downto 0); signal fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal signR_uid125_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid125_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid125_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (35 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal fracOOPi_uid10_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracOOPi_uid10_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (49 downto 0); signal normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (48 downto 0); signal fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (47 downto 0); signal fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a : std_logic_vector(2 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b : std_logic_vector(2 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0); signal prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in : std_logic_vector (41 downto 0); signal prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (17 downto 0); signal mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (16 downto 0); signal concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal R_uid227_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (15 downto 0); signal FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (15 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a : std_logic_vector(4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b : std_logic_vector(4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a : std_logic_vector(5 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b : std_logic_vector(5 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a : std_logic_vector(5 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b : std_logic_vector(5 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal R_uid126_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (23 downto 0); signal fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (3 downto 0); signal fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (3 downto 0); signal expLRange_uid84_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (7 downto 0); signal expLRange_uid84_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal srValRange_uid92_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (4 downto 0); signal srValRange_uid92_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (4 downto 0); signal normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (27 downto 0); signal normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (11 downto 0); signal InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (36 downto 0); signal arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal y_uid59_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (35 downto 0); signal y_uid59_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0); signal rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (18 downto 0); signal vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (18 downto 0); signal rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (26 downto 0); signal rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (32 downto 0); signal vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (32 downto 0); signal InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (8 downto 0); signal expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (8 downto 0); signal expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (24 downto 0); signal fpOOPi_uid11_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (24 downto 0); signal X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (17 downto 0); signal X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (9 downto 0); signal X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal lowRangeB_uid258_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid258_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid259_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid259_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid264_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid264_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid265_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0); signal highBBits_uid265_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0); signal lowRangeB_uid405_arcsinXPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid405_arcsinXPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid406_arcsinXPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid406_arcsinXPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid411_arcsinXPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid411_arcsinXPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid412_arcsinXPolyEval_in : std_logic_vector (25 downto 0); signal highBBits_uid412_arcsinXPolyEval_b : std_logic_vector (23 downto 0); signal lowRangeB_uid427_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid427_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid428_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal highBBits_uid428_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal lowRangeB_uid433_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid433_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid434_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal highBBits_uid434_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0); signal yT1_uid403_arcsinXPolyEval_in : std_logic_vector (16 downto 0); signal yT1_uid403_arcsinXPolyEval_b : std_logic_vector (12 downto 0); signal yT1_uid425_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0); signal yT1_uid425_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal fpL_uid85_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal Y34_uid60_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal Y34_uid60_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal yAddr_uid63_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal yAddr_uid63_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (17 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(36 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(36 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (36 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (32 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (32 downto 0); signal rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_a : std_logic_vector(23 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_b : std_logic_vector(23 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_o : std_logic_vector (23 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_q : std_logic_vector (23 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0); signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (32 downto 0); signal X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (32 downto 0); signal X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (28 downto 0); signal X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (28 downto 0); signal X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (24 downto 0); signal X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (24 downto 0); signal InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal path2_uid61_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal path2_uid61_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid256_arcsinXO2XPolyEval_in : std_logic_vector (17 downto 0); signal yT1_uid256_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal l_uid80_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal l_uid80_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0); signal vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (23 downto 0); signal fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal s1_uid258_uid261_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0); signal s2_uid264_uid267_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0); signal s1_uid405_uid408_arcsinXPolyEval_q : std_logic_vector (24 downto 0); signal s2_uid411_uid414_arcsinXPolyEval_q : std_logic_vector (32 downto 0); signal s1_uid427_uid430_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0); signal s2_uid433_uid436_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0); signal InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (0 downto 0); signal expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (6 downto 0); signal RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (21 downto 0); signal RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (19 downto 0); signal pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (2 downto 0); signal vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (2 downto 0); signal rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (30 downto 0); signal rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0); signal vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (33 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal mAddr_uid97_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal mAddr_uid97_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (25 downto 0); signal fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (27 downto 0); signal fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (28 downto 0); signal fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (35 downto 0); signal LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (35 downto 0); signal LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0); signal LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0); signal LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (33 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0); signal fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (3 downto 0); signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); begin --xIn(GPIN,3)@0 --cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest(CONSTANT,18) cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000000"; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable(LOGICAL,1059) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q <= not ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor(LOGICAL,1162) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q <= not (ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a or ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top(CONSTANT,1082) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q <= "011110"; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp(LOGICAL,1083) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q); ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q <= "1" when ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a = ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b else "0"; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg(REG,1084) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q; END IF; END IF; END PROCESS; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena(REG,1163) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q = "1") THEN ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd(LOGICAL,1164) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b <= en; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a and ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b; --fracX_uid16_asinX_uid8_fpArcsinPiTest(BITSELECT,15)@0 fracX_uid16_asinX_uid8_fpArcsinPiTest_in <= a(22 downto 0); fracX_uid16_asinX_uid8_fpArcsinPiTest_b <= fracX_uid16_asinX_uid8_fpArcsinPiTest_in(22 downto 0); --fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest(LOGICAL,34)@0 fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a <= fracX_uid16_asinX_uid8_fpArcsinPiTest_b; fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q <= "1" when fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a = fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b else "0"; --InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest(LOGICAL,36)@0 InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a <= fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q; InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q <= not InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a; --cstBias_uid22_asinX_uid8_fpArcsinPiTest(CONSTANT,21) cstBias_uid22_asinX_uid8_fpArcsinPiTest_q <= "01111111"; --expX_uid15_asinX_uid8_fpArcsinPiTest(BITSELECT,14)@0 expX_uid15_asinX_uid8_fpArcsinPiTest_in <= a(30 downto 0); expX_uid15_asinX_uid8_fpArcsinPiTest_b <= expX_uid15_asinX_uid8_fpArcsinPiTest_in(30 downto 23); --expEQ0_uid45_asinX_uid8_fpArcsinPiTest(LOGICAL,44)@0 expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q; expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q <= "1" when expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a = expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b else "0"; --exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest(LOGICAL,46)@0 exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a <= expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q; exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q; exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q <= exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a and exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b; --GND(CONSTANT,0) GND_q <= "0"; --expGT0_uid44_asinX_uid8_fpArcsinPiTest(COMPARE,43)@0 expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin <= GND_q; expGT0_uid44_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid22_asinX_uid8_fpArcsinPiTest_q) & '0'; expGT0_uid44_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_asinX_uid8_fpArcsinPiTest_b) & expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin(0); expGT0_uid44_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid44_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(expGT0_uid44_asinX_uid8_fpArcsinPiTest_b)); expGT0_uid44_asinX_uid8_fpArcsinPiTest_c(0) <= expGT0_uid44_asinX_uid8_fpArcsinPiTest_o(10); --inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest(LOGICAL,47)@0 inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a <= expGT0_uid44_asinX_uid8_fpArcsinPiTest_c; inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b <= exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q; inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q <= inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a or inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b; --InvExc_N_uid39_asinX_uid8_fpArcsinPiTest(LOGICAL,38)@0 InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_q; InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q <= not InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a; --InvExc_I_uid40_asinX_uid8_fpArcsinPiTest(LOGICAL,39)@0 InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_q; InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q <= not InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a; --cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest(CONSTANT,20) cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q <= "00000000"; --expXIsZero_uid31_asinX_uid8_fpArcsinPiTest(LOGICAL,30)@0 expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a = expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b else "0"; --InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest(LOGICAL,40)@0 InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q; InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q <= not InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a; --exc_R_uid42_asinX_uid8_fpArcsinPiTest(LOGICAL,41)@0 exc_R_uid42_asinX_uid8_fpArcsinPiTest_a <= InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q; exc_R_uid42_asinX_uid8_fpArcsinPiTest_b <= InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q; exc_R_uid42_asinX_uid8_fpArcsinPiTest_c <= InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q; exc_R_uid42_asinX_uid8_fpArcsinPiTest_q <= exc_R_uid42_asinX_uid8_fpArcsinPiTest_a and exc_R_uid42_asinX_uid8_fpArcsinPiTest_b and exc_R_uid42_asinX_uid8_fpArcsinPiTest_c; --xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest(LOGICAL,117)@0 xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a <= exc_R_uid42_asinX_uid8_fpArcsinPiTest_q; xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b <= inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q; xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q <= xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a and xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b; --cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest(CONSTANT,17) cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q <= "11111111"; --expXIsMax_uid33_asinX_uid8_fpArcsinPiTest(LOGICAL,32)@0 expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a = expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b else "0"; --exc_I_uid36_asinX_uid8_fpArcsinPiTest(LOGICAL,35)@0 exc_I_uid36_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q; exc_I_uid36_asinX_uid8_fpArcsinPiTest_b <= fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q; exc_I_uid36_asinX_uid8_fpArcsinPiTest_q <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_a and exc_I_uid36_asinX_uid8_fpArcsinPiTest_b; --exc_N_uid38_asinX_uid8_fpArcsinPiTest(LOGICAL,37)@0 exc_N_uid38_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q; exc_N_uid38_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q; exc_N_uid38_asinX_uid8_fpArcsinPiTest_q <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_a and exc_N_uid38_asinX_uid8_fpArcsinPiTest_b; --excRNaN_uid119_asinX_uid8_fpArcsinPiTest(LOGICAL,118)@0 excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c <= xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a or excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b or excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c; --InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest(LOGICAL,123)@0 InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a <= excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q; InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q <= not InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a; END IF; END PROCESS; --singX_uid17_asinX_uid8_fpArcsinPiTest(BITSELECT,16)@0 singX_uid17_asinX_uid8_fpArcsinPiTest_in <= a; singX_uid17_asinX_uid8_fpArcsinPiTest_b <= singX_uid17_asinX_uid8_fpArcsinPiTest_in(31 downto 31); --reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1(REG,512)@0 reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q <= singX_uid17_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --signR_uid125_asinX_uid8_fpArcsinPiTest(LOGICAL,124)@1 signR_uid125_asinX_uid8_fpArcsinPiTest_a <= reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q; signR_uid125_asinX_uid8_fpArcsinPiTest_b <= InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q; signR_uid125_asinX_uid8_fpArcsinPiTest_q <= signR_uid125_asinX_uid8_fpArcsinPiTest_a and signR_uid125_asinX_uid8_fpArcsinPiTest_b; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt(COUNTER,1078) -- every=1, low=0, high=30, step=1, init=1 ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i = 29 THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '1'; ELSE ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i - 30; ELSE ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i,5)); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg(REG,1079) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux(MUX,1080) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s <= en; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux: PROCESS (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s, ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q, ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; WHEN "1" => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem(DUALMEM,1153) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia <= signR_uid125_asinX_uid8_fpArcsinPiTest_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 31, width_b => 1, widthad_b => 5, numwords_b => 31, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq, address_a => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa, data_a => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia ); ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq(0 downto 0); --cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest(CONSTANT,22) cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q <= "01111110"; --RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,393)@19 RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 1); --rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,395)@19 rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= GND_q & RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(CONSTANT,389) rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= "000000"; --rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(CONSTANT,378) rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= "000000000000000000000000"; --X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,377)@18 X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 24); --rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,379)@18 rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q & X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,275) zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "0000000000000000"; --X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,374)@18 X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 16); --rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,376)@18 rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,371)@18 X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 8); --rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,373)@18 rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q & X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,311) maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "100011"; --zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,268) zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000000000000000"; --X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,236)@0 X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(24 downto 0); X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(24 downto 0); --leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,235) leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "000000000000"; --leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,237)@0 leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,233)@0 X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(28 downto 0); X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(28 downto 0); --leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,234)@0 leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; --X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,230)@0 X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(32 downto 0); X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(32 downto 0); --leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,229) leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "0000"; --leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,231)@0 leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest(CONSTANT,53) cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q <= "0000000000000"; --oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest(BITJOIN,48)@0 oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q <= VCC_q & fracX_uid16_asinX_uid8_fpArcsinPiTest_b; --oFracXExt_uid55_asinX_uid8_fpArcsinPiTest(BITJOIN,54)@0 oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q <= cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q & oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q; --shiftBias_uid52_asinX_uid8_fpArcsinPiTest(CONSTANT,51) shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q <= "01110010"; --shiftValue_uid53_asinX_uid8_fpArcsinPiTest(SUB,52)@0 shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid15_asinX_uid8_fpArcsinPiTest_b); shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q); shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b)); shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q <= shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest(BITSELECT,55)@0 fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in <= shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q(3 downto 0); fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in(3 downto 0); --leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,238)@0 leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b; leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(3 downto 2); --leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest(MUX,239)@0 leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s <= leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b; leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest: PROCESS (leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s, en, oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,247)@0 LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(33 downto 0); LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(33 downto 0); --leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,246) leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "000"; --leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,248)@0 leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5(REG,463)@0 reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q <= leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,244)@0 LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(34 downto 0); LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(34 downto 0); --leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,245)@0 leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & z2_uid93_asinX_uid8_fpArcsinPiTest_q; --reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4(REG,462)@0 reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q <= leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,241)@0 LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(35 downto 0); LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(35 downto 0); --leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,242)@0 leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & GND_q; --reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3(REG,461)@0 reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q <= leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2(REG,460)@0 reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,249)@0 leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b(1 downto 0); leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(1 downto 0); --reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1(REG,459)@0 reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q <= leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest(MUX,250)@1 leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s <= reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q; leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest: PROCESS (leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s, en, reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q, reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q, reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q, reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q) BEGIN CASE leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q; WHEN "01" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q; WHEN "10" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q; WHEN "11" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q; WHEN OTHERS => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid59_asinX_uid8_fpArcsinPiTest(BITSELECT,58)@1 y_uid59_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(35 downto 0); y_uid59_asinX_uid8_fpArcsinPiTest_b <= y_uid59_asinX_uid8_fpArcsinPiTest_in(35 downto 1); --pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest(BITJOIN,77)@1 pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q); --oMy_uid78_asinX_uid8_fpArcsinPiTest(SUB,78)@1 oMy_uid78_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q); oMy_uid78_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & y_uid59_asinX_uid8_fpArcsinPiTest_b); oMy_uid78_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid78_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(oMy_uid78_asinX_uid8_fpArcsinPiTest_b)); oMy_uid78_asinX_uid8_fpArcsinPiTest_q <= oMy_uid78_asinX_uid8_fpArcsinPiTest_o(36 downto 0); --l_uid80_asinX_uid8_fpArcsinPiTest(BITSELECT,79)@1 l_uid80_asinX_uid8_fpArcsinPiTest_in <= oMy_uid78_asinX_uid8_fpArcsinPiTest_q(34 downto 0); l_uid80_asinX_uid8_fpArcsinPiTest_b <= l_uid80_asinX_uid8_fpArcsinPiTest_in(34 downto 0); --rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,269)@1 rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= l_uid80_asinX_uid8_fpArcsinPiTest_b; rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 3); --reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,473)@1 reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,270)@2 vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q; vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f(DELAY,842)@2 ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,272)@1 vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= l_uid80_asinX_uid8_fpArcsinPiTest_b(2 downto 0); vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(2 downto 0); --cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,273)@1 cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; --reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,475)@1 reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,474)@1 reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= l_uid80_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,274)@2 vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q) BEGIN CASE vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q; WHEN "1" => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q; WHEN OTHERS => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,276)@2 rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 19); --reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,476)@2 reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,277)@3 vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q; vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e(DELAY,841)@3 ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,279)@2 vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(18 downto 0); vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(18 downto 0); --cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,280)@2 cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; --reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,478)@2 reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,477)@2 reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,281)@3 vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q) BEGIN CASE vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q; WHEN "1" => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q; WHEN OTHERS => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,283)@3 rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 27); --vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,284)@3 vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,482)@3 reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,286)@3 vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(26 downto 0); vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(26 downto 0); --cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,287)@3 cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; --vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,288)@3 vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,290)@3 rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 31); --reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,479)@3 reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,291)@4 vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q; vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,293)@3 vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(30 downto 0); vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(30 downto 0); --cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,294)@3 cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,481)@3 reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,480)@3 reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,295)@4 vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q) BEGIN CASE vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q; WHEN "1" => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q; WHEN OTHERS => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,297)@4 rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 33); --vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,298)@4 vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= z2_uid93_asinX_uid8_fpArcsinPiTest_q; vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,300)@4 vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(32 downto 0); vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(32 downto 0); --cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,301)@4 cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & z2_uid93_asinX_uid8_fpArcsinPiTest_q; --vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,302)@4 vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,304)@4 rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 34); --vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,305)@4 vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= GND_q; vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,310)@4 vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q & ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q & reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q & vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; --ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c(DELAY,845)@4 ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 6, depth => 1 ) PORT MAP ( xin => vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,483)@4 reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(COMPARE,312)@5 vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin <= GND_q; vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) & '0'; vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q) & vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin(0); vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b)); vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c(0) <= vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o(8); --vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,314)@5 vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c; vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q; WHEN "1" => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --cstBiasM2_uid6_fpArcsinPiTest(CONSTANT,5) cstBiasM2_uid6_fpArcsinPiTest_q <= "01111101"; --expL_uid82_asinX_uid8_fpArcsinPiTest(SUB,81)@6 expL_uid82_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid6_fpArcsinPiTest_q); expL_uid82_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q); expL_uid82_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid82_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(expL_uid82_asinX_uid8_fpArcsinPiTest_b)); expL_uid82_asinX_uid8_fpArcsinPiTest_q <= expL_uid82_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --expLRange_uid84_asinX_uid8_fpArcsinPiTest(BITSELECT,83)@6 expLRange_uid84_asinX_uid8_fpArcsinPiTest_in <= expL_uid82_asinX_uid8_fpArcsinPiTest_q(7 downto 0); expLRange_uid84_asinX_uid8_fpArcsinPiTest_b <= expLRange_uid84_asinX_uid8_fpArcsinPiTest_in(7 downto 0); --vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,307)@4 vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(33 downto 0); vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(33 downto 0); --cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,308)@4 cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & GND_q; --vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,309)@4 vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest(BITSELECT,82)@4 fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(33 downto 0); fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b <= fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in(33 downto 11); --reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0(REG,484)@4 reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q <= fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a(DELAY,581)@5 ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q, xout => ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --fpL_uid85_asinX_uid8_fpArcsinPiTest(BITJOIN,84)@6 fpL_uid85_asinX_uid8_fpArcsinPiTest_q <= GND_q & expLRange_uid84_asinX_uid8_fpArcsinPiTest_b & ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q; --signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,319)@6 signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q; signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(31 downto 31); --expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,317)@6 expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q(30 downto 0); expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(30 downto 23); --expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,324)@6 expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b else "0"; --negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,367)@6 negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; END IF; END PROCESS; --ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c(DELAY,901)@7 ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor(LOGICAL,1176) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q <= not (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a or ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top(CONSTANT,1172) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q <= "0110"; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp(LOGICAL,1173) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q); ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a = ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b else "0"; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg(REG,1174) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena(REG,1177) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q = "1") THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd(LOGICAL,1178) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b <= en; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a and ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b; --reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0(REG,494)@6 reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(ADD,340)@7 expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q); expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q); expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b)); expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,341)@7 expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(8 downto 1); --expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(ADD,337)@7 expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q); expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid22_asinX_uid8_fpArcsinPiTest_q); expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b)); expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,338)@7 expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(8 downto 1); --expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,342)@6 expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(0 downto 0); expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(0 downto 0); --expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,343)@6 expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(DELAY,869)@6 ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,344)@7 expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q; expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; WHEN "1" => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,877)@6 ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,332)@7 InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,318)@6 fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q(22 downto 0); fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(22 downto 0); --reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1(REG,485)@6 reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,328)@7 fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q; fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1" when fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b else "0"; --expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,326)@6 expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN IF (expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b) THEN expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1"; ELSE expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "0"; END IF; END IF; END PROCESS; --exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,329)@7 exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,333)@7 InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,334)@6 InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; END IF; END PROCESS; --exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,335)@7 exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c <= InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b and exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c; --minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,353)@7 minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,354)@7 minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,330)@7 InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,331)@7 exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,355)@7 excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c <= minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a or excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b or excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c; --InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,351)@7 InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,352)@7 inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,887)@6 ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,356)@7 join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; --fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,357)@7 fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q & join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; --reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0(REG,486)@7 reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOOKUP,358)@8 fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q) IS WHEN "0000" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "0001" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "0010" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "0011" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "0100" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "0101" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "0110" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "0111" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "1000" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1001" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "1010" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1011" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1100" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1101" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1110" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1111" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN OTHERS => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,362)@8 expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg(DELAY,1166) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt(COUNTER,1168) -- every=1, low=0, high=6, step=1, init=1 ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i = 5 THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i - 6; ELSE ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i,3)); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg(REG,1169) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux(MUX,1170) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s <= en; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s, ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q, ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem(DUALMEM,1167) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 7, width_b => 8, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia ); ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq(7 downto 0); --cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest(CONSTANT,19) cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000001"; --fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,346)@6 fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(22 downto 16); --addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,347)@6 addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0(REG,487)@6 reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q <= addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --memoryC2_uid424_sqrtTableGenerator_lutmem(DUALMEM,457)@7 memoryC2_uid424_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid424_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid424_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid424_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q; memoryC2_uid424_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC2_uid424_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid424_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid424_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid424_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid424_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid424_sqrtTableGenerator_lutmem_ia ); memoryC2_uid424_sqrtTableGenerator_lutmem_q <= memoryC2_uid424_sqrtTableGenerator_lutmem_iq(11 downto 0); --reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1(REG,489)@9 reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q <= memoryC2_uid424_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1165) ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,875)@6 ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q, xout => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,348)@9 FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q(15 downto 0); FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(15 downto 0); --yT1_uid425_sqrtPolynomialEvaluator(BITSELECT,424)@9 yT1_uid425_sqrtPolynomialEvaluator_in <= FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; yT1_uid425_sqrtPolynomialEvaluator_b <= yT1_uid425_sqrtPolynomialEvaluator_in(15 downto 4); --reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0(REG,488)@9 reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q <= yT1_uid425_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator(MULT,443)@10 prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b); prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a <= reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q; prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q; prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr,24)); END IF; END IF; END PROCESS; prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q <= prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator(BITSELECT,444)@13 prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in <= prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in(23 downto 11); --highBBits_uid428_sqrtPolynomialEvaluator(BITSELECT,427)@13 highBBits_uid428_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b; highBBits_uid428_sqrtPolynomialEvaluator_b <= highBBits_uid428_sqrtPolynomialEvaluator_in(12 downto 1); --ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a(DELAY,983)@7 ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1217) ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q, xout => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid423_sqrtTableGenerator_lutmem(DUALMEM,456)@11 memoryC1_uid423_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid423_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid423_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid423_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q; memoryC1_uid423_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC1_uid423_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid423_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid423_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid423_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid423_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid423_sqrtTableGenerator_lutmem_ia ); memoryC1_uid423_sqrtTableGenerator_lutmem_q <= memoryC1_uid423_sqrtTableGenerator_lutmem_iq(20 downto 0); --sumAHighB_uid429_sqrtPolynomialEvaluator(ADD,428)@13 sumAHighB_uid429_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid423_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid423_sqrtTableGenerator_lutmem_q); sumAHighB_uid429_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid428_sqrtPolynomialEvaluator_b(11)) & highBBits_uid428_sqrtPolynomialEvaluator_b); sumAHighB_uid429_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid429_sqrtPolynomialEvaluator_b)); sumAHighB_uid429_sqrtPolynomialEvaluator_q <= sumAHighB_uid429_sqrtPolynomialEvaluator_o(21 downto 0); --lowRangeB_uid427_sqrtPolynomialEvaluator(BITSELECT,426)@13 lowRangeB_uid427_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid427_sqrtPolynomialEvaluator_b <= lowRangeB_uid427_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid427_uid430_sqrtPolynomialEvaluator(BITJOIN,429)@13 s1_uid427_uid430_sqrtPolynomialEvaluator_q <= sumAHighB_uid429_sqrtPolynomialEvaluator_q & lowRangeB_uid427_sqrtPolynomialEvaluator_b; --reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1(REG,492)@13 reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q <= s1_uid427_uid430_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,1240) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a or ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b); --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg(REG,1238) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,1241) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,1242) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,1232) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,1234) -- every=1, low=0, high=1, step=1, init=1 ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,1)); --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,1235) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,1236) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,1233) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 16, widthad_a => 1, numwords_a => 2, width_b => 16, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq(15 downto 0); --reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0(REG,491)@13 reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator(MULT,446)@14 prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b); prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a <= reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q; prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b <= reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q; prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr,39)); END IF; END IF; END PROCESS; prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q <= prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator(BITSELECT,447)@17 prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in <= prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in(38 downto 15); --highBBits_uid434_sqrtPolynomialEvaluator(BITSELECT,433)@17 highBBits_uid434_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b; highBBits_uid434_sqrtPolynomialEvaluator_b <= highBBits_uid434_sqrtPolynomialEvaluator_in(23 downto 2); --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,1253) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top(CONSTANT,1184) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q <= "0101"; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp(LOGICAL,1185) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q); ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b else "0"; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg(REG,1186) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,1254) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1255) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1243) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt(COUNTER,1180) -- every=1, low=0, high=5, step=1, init=1 ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i = 4 THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i - 5; ELSE ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i,3)); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg(REG,1181) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux(MUX,1182) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s <= en; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1244) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0(REG,493)@14 reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid422_sqrtTableGenerator_lutmem(DUALMEM,455)@15 memoryC0_uid422_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid422_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid422_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid422_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q; memoryC0_uid422_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 29, widthad_a => 8, numwords_a => 256, width_b => 29, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC0_uid422_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid422_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid422_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid422_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid422_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid422_sqrtTableGenerator_lutmem_ia ); memoryC0_uid422_sqrtTableGenerator_lutmem_q <= memoryC0_uid422_sqrtTableGenerator_lutmem_iq(28 downto 0); --sumAHighB_uid435_sqrtPolynomialEvaluator(ADD,434)@17 sumAHighB_uid435_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid422_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid422_sqrtTableGenerator_lutmem_q); sumAHighB_uid435_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid434_sqrtPolynomialEvaluator_b(21)) & highBBits_uid434_sqrtPolynomialEvaluator_b); sumAHighB_uid435_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid435_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid435_sqrtPolynomialEvaluator_b)); sumAHighB_uid435_sqrtPolynomialEvaluator_q <= sumAHighB_uid435_sqrtPolynomialEvaluator_o(29 downto 0); --lowRangeB_uid433_sqrtPolynomialEvaluator(BITSELECT,432)@17 lowRangeB_uid433_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid433_sqrtPolynomialEvaluator_b <= lowRangeB_uid433_sqrtPolynomialEvaluator_in(1 downto 0); --s2_uid433_uid436_sqrtPolynomialEvaluator(BITJOIN,435)@17 s2_uid433_uid436_sqrtPolynomialEvaluator_q <= sumAHighB_uid435_sqrtPolynomialEvaluator_q & lowRangeB_uid433_sqrtPolynomialEvaluator_b; --fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,350)@17 fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= s2_uid433_uid436_sqrtPolynomialEvaluator_q(28 downto 0); fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(28 downto 6); --ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(DELAY,895)@8 ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 9 ) PORT MAP ( xin => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,366)@17 fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q; fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; WHEN "10" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,368)@17 RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q & ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q & fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; --SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest(BITSELECT,89)@17 SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in <= RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q(22 downto 0); SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b <= SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in(22 downto 0); --ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a(DELAY,586)@17 ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b, xout => ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest(BITJOIN,90)@18 oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q <= VCC_q & ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q; --z2_uid93_asinX_uid8_fpArcsinPiTest(CONSTANT,92) z2_uid93_asinX_uid8_fpArcsinPiTest_q <= "00"; --oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest(BITJOIN,93)@18 oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q <= oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q & z2_uid93_asinX_uid8_fpArcsinPiTest_q; --SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest(BITSELECT,87)@17 SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in <= RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q(30 downto 0); SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b <= SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in(30 downto 23); --reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1(REG,496)@17 reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q <= SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --srVal_uid89_asinX_uid8_fpArcsinPiTest(SUB,88)@18 srVal_uid89_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q); srVal_uid89_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q); srVal_uid89_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid89_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(srVal_uid89_asinX_uid8_fpArcsinPiTest_b)); srVal_uid89_asinX_uid8_fpArcsinPiTest_q <= srVal_uid89_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --srValRange_uid92_asinX_uid8_fpArcsinPiTest(BITSELECT,91)@18 srValRange_uid92_asinX_uid8_fpArcsinPiTest_in <= srVal_uid89_asinX_uid8_fpArcsinPiTest_q(4 downto 0); srValRange_uid92_asinX_uid8_fpArcsinPiTest_b <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,380)@18 rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b; rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(4 downto 3); --rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,381)@18 rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,388)@18 RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 6); --rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,390)@18 rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5(REG,501)@18 reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q <= rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,385)@18 RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 4); --rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,387)@18 rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4(REG,500)@18 reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q <= rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,382)@18 RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 2); --rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,384)@18 rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= z2_uid93_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3(REG,499)@18 reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q <= rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2(REG,498)@18 reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,391)@18 rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(2 downto 1); --reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1(REG,497)@18 reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,392)@19 rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q; rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q, reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q, reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q, reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q) BEGIN CASE rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q; WHEN "01" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q; WHEN "10" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q; WHEN "11" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q; WHEN OTHERS => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,396)@18 rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1(REG,502)@18 reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,397)@19 rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q; rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mAddr_uid97_asinX_uid8_fpArcsinPiTest(BITSELECT,96)@19 mAddr_uid97_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; mAddr_uid97_asinX_uid8_fpArcsinPiTest_b <= mAddr_uid97_asinX_uid8_fpArcsinPiTest_in(25 downto 18); --reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0(REG,503)@19 reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q <= mAddr_uid97_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid402_arcsinXTabGen_lutmem(DUALMEM,454)@20 memoryC2_uid402_arcsinXTabGen_lutmem_reset0 <= areset; memoryC2_uid402_arcsinXTabGen_lutmem_ia <= (others => '0'); memoryC2_uid402_arcsinXTabGen_lutmem_aa <= (others => '0'); memoryC2_uid402_arcsinXTabGen_lutmem_ab <= reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q; memoryC2_uid402_arcsinXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 8, numwords_a => 256, width_b => 13, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC2_uid402_arcsinXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid402_arcsinXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid402_arcsinXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid402_arcsinXTabGen_lutmem_iq, address_a => memoryC2_uid402_arcsinXTabGen_lutmem_aa, data_a => memoryC2_uid402_arcsinXTabGen_lutmem_ia ); memoryC2_uid402_arcsinXTabGen_lutmem_q <= memoryC2_uid402_arcsinXTabGen_lutmem_iq(12 downto 0); --reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1(REG,505)@22 reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q <= memoryC2_uid402_arcsinXTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1063) ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, xout => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a(DELAY,590)@19 ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 26, depth => 2 ) PORT MAP ( xin => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q, xout => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest(BITSELECT,97)@22 mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in <= ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q(17 downto 0); mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in(17 downto 1); --yT1_uid403_arcsinXPolyEval(BITSELECT,402)@22 yT1_uid403_arcsinXPolyEval_in <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b; yT1_uid403_arcsinXPolyEval_b <= yT1_uid403_arcsinXPolyEval_in(16 downto 4); --reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0(REG,504)@22 reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q <= yT1_uid403_arcsinXPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid438_pT1_uid404_arcsinXPolyEval(MULT,437)@23 prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid438_pT1_uid404_arcsinXPolyEval_a),14)) * SIGNED(prodXY_uid438_pT1_uid404_arcsinXPolyEval_b); prodXY_uid438_pT1_uid404_arcsinXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_a <= (others => '0'); prodXY_uid438_pT1_uid404_arcsinXPolyEval_b <= (others => '0'); prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_a <= reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q; prodXY_uid438_pT1_uid404_arcsinXPolyEval_b <= reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q; prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid438_pT1_uid404_arcsinXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_q <= prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval(BITSELECT,438)@26 prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in <= prodXY_uid438_pT1_uid404_arcsinXPolyEval_q; prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in(25 downto 12); --highBBits_uid406_arcsinXPolyEval(BITSELECT,405)@26 highBBits_uid406_arcsinXPolyEval_in <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b; highBBits_uid406_arcsinXPolyEval_b <= highBBits_uid406_arcsinXPolyEval_in(13 downto 1); --ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a(DELAY,980)@20 ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q, xout => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg(DELAY,1216) ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q, xout => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid401_arcsinXTabGen_lutmem(DUALMEM,453)@24 memoryC1_uid401_arcsinXTabGen_lutmem_reset0 <= areset; memoryC1_uid401_arcsinXTabGen_lutmem_ia <= (others => '0'); memoryC1_uid401_arcsinXTabGen_lutmem_aa <= (others => '0'); memoryC1_uid401_arcsinXTabGen_lutmem_ab <= ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q; memoryC1_uid401_arcsinXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 8, numwords_a => 256, width_b => 23, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC1_uid401_arcsinXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid401_arcsinXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid401_arcsinXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid401_arcsinXTabGen_lutmem_iq, address_a => memoryC1_uid401_arcsinXTabGen_lutmem_aa, data_a => memoryC1_uid401_arcsinXTabGen_lutmem_ia ); memoryC1_uid401_arcsinXTabGen_lutmem_q <= memoryC1_uid401_arcsinXTabGen_lutmem_iq(22 downto 0); --sumAHighB_uid407_arcsinXPolyEval(ADD,406)@26 sumAHighB_uid407_arcsinXPolyEval_a <= STD_LOGIC_VECTOR((23 downto 23 => memoryC1_uid401_arcsinXTabGen_lutmem_q(22)) & memoryC1_uid401_arcsinXTabGen_lutmem_q); sumAHighB_uid407_arcsinXPolyEval_b <= STD_LOGIC_VECTOR((23 downto 13 => highBBits_uid406_arcsinXPolyEval_b(12)) & highBBits_uid406_arcsinXPolyEval_b); sumAHighB_uid407_arcsinXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid407_arcsinXPolyEval_a) + SIGNED(sumAHighB_uid407_arcsinXPolyEval_b)); sumAHighB_uid407_arcsinXPolyEval_q <= sumAHighB_uid407_arcsinXPolyEval_o(23 downto 0); --lowRangeB_uid405_arcsinXPolyEval(BITSELECT,404)@26 lowRangeB_uid405_arcsinXPolyEval_in <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b(0 downto 0); lowRangeB_uid405_arcsinXPolyEval_b <= lowRangeB_uid405_arcsinXPolyEval_in(0 downto 0); --s1_uid405_uid408_arcsinXPolyEval(BITJOIN,407)@26 s1_uid405_uid408_arcsinXPolyEval_q <= sumAHighB_uid407_arcsinXPolyEval_q & lowRangeB_uid405_arcsinXPolyEval_b; --reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1(REG,508)@26 reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q <= "0000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q <= s1_uid405_uid408_arcsinXPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor(LOGICAL,1200) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q <= not (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a or ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b); --roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest(CONSTANT,185) roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q <= "010"; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp(LOGICAL,1197) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a <= roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q); ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q <= "1" when ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a = ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b else "0"; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg(REG,1198) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena(REG,1201) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q = "1") THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd(LOGICAL,1202) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b <= en; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a and ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b; --reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0(REG,507)@22 reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt(COUNTER,1192) -- every=1, low=0, high=2, step=1, init=1 ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i = 1 THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i - 2; ELSE ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i,2)); --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg(REG,1193) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux(MUX,1194) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s <= en; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux: PROCESS (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s, ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q, ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem(DUALMEM,1191) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0 <= areset; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia <= reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 2, numwords_a => 3, width_b => 17, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq, address_a => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa, data_a => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia ); ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq(16 downto 0); --prodXY_uid441_pT2_uid410_arcsinXPolyEval(MULT,440)@27 prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid441_pT2_uid410_arcsinXPolyEval_a),18)) * SIGNED(prodXY_uid441_pT2_uid410_arcsinXPolyEval_b); prodXY_uid441_pT2_uid410_arcsinXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_a <= (others => '0'); prodXY_uid441_pT2_uid410_arcsinXPolyEval_b <= (others => '0'); prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_a <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q; prodXY_uid441_pT2_uid410_arcsinXPolyEval_b <= reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q; prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr,42)); END IF; END IF; END PROCESS; prodXY_uid441_pT2_uid410_arcsinXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_q <= prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval(BITSELECT,441)@30 prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in <= prodXY_uid441_pT2_uid410_arcsinXPolyEval_q; prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in(41 downto 16); --highBBits_uid412_arcsinXPolyEval(BITSELECT,411)@30 highBBits_uid412_arcsinXPolyEval_in <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b; highBBits_uid412_arcsinXPolyEval_b <= highBBits_uid412_arcsinXPolyEval_in(25 downto 2); --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor(LOGICAL,1266) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a or ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b); --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena(REG,1267) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q = "1") THEN ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd(LOGICAL,1268) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b <= en; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b; --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg(DELAY,1256) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => mAddr_uid97_asinX_uid8_fpArcsinPiTest_b, xout => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem(DUALMEM,1257) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0 <= areset; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq, address_a => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa, data_a => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia ); ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0(REG,509)@27 reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid400_arcsinXTabGen_lutmem(DUALMEM,452)@28 memoryC0_uid400_arcsinXTabGen_lutmem_reset0 <= areset; memoryC0_uid400_arcsinXTabGen_lutmem_ia <= (others => '0'); memoryC0_uid400_arcsinXTabGen_lutmem_aa <= (others => '0'); memoryC0_uid400_arcsinXTabGen_lutmem_ab <= reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q; memoryC0_uid400_arcsinXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC0_uid400_arcsinXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid400_arcsinXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid400_arcsinXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid400_arcsinXTabGen_lutmem_iq, address_a => memoryC0_uid400_arcsinXTabGen_lutmem_aa, data_a => memoryC0_uid400_arcsinXTabGen_lutmem_ia ); memoryC0_uid400_arcsinXTabGen_lutmem_q <= memoryC0_uid400_arcsinXTabGen_lutmem_iq(29 downto 0); --sumAHighB_uid413_arcsinXPolyEval(ADD,412)@30 sumAHighB_uid413_arcsinXPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid400_arcsinXTabGen_lutmem_q(29)) & memoryC0_uid400_arcsinXTabGen_lutmem_q); sumAHighB_uid413_arcsinXPolyEval_b <= STD_LOGIC_VECTOR((30 downto 24 => highBBits_uid412_arcsinXPolyEval_b(23)) & highBBits_uid412_arcsinXPolyEval_b); sumAHighB_uid413_arcsinXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid413_arcsinXPolyEval_a) + SIGNED(sumAHighB_uid413_arcsinXPolyEval_b)); sumAHighB_uid413_arcsinXPolyEval_q <= sumAHighB_uid413_arcsinXPolyEval_o(30 downto 0); --lowRangeB_uid411_arcsinXPolyEval(BITSELECT,410)@30 lowRangeB_uid411_arcsinXPolyEval_in <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b(1 downto 0); lowRangeB_uid411_arcsinXPolyEval_b <= lowRangeB_uid411_arcsinXPolyEval_in(1 downto 0); --s2_uid411_uid414_arcsinXPolyEval(BITJOIN,413)@30 s2_uid411_uid414_arcsinXPolyEval_q <= sumAHighB_uid413_arcsinXPolyEval_q & lowRangeB_uid411_arcsinXPolyEval_b; --fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest(BITSELECT,99)@30 fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in <= s2_uid411_uid414_arcsinXPolyEval_q(30 downto 0); fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b <= fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in(30 downto 3); --reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1(REG,510)@30 reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q <= "0000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q <= fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --piO2_uid101_asinX_uid8_fpArcsinPiTest(CONSTANT,100) piO2_uid101_asinX_uid8_fpArcsinPiTest_q <= "1100100100001111110110101010"; --path3Diff_uid102_asinX_uid8_fpArcsinPiTest(SUB,101)@31 path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid101_asinX_uid8_fpArcsinPiTest_q); path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q); path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b)); path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o(28 downto 0); --normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest(BITSELECT,102)@31 normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(27 downto 0); normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in(27 downto 27); --expRPath3_uid107_asinX_uid8_fpArcsinPiTest(MUX,106)@31 expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b; expRPath3_uid107_asinX_uid8_fpArcsinPiTest: PROCESS (expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s, en, cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q, cstBias_uid22_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest(BITSELECT,103)@31 path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(26 downto 0); path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b <= path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in(26 downto 3); --path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest(BITSELECT,104)@31 path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(25 downto 0); path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b <= path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in(25 downto 2); --fracRPath3_uid106_asinX_uid8_fpArcsinPiTest(MUX,105)@31 fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b; fracRPath3_uid106_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s, en, path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b, path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b) BEGIN CASE fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b; WHEN "1" => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest(BITJOIN,107)@31 expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q <= expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q & fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q; --reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0(REG,511)@31 reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q <= expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest(ADD,108)@32 expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q); expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q); expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b)); expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o(32 downto 0); --expRPath3_uid111_asinX_uid8_fpArcsinPiTest(BITSELECT,110)@32 expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q(31 downto 0); expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b <= expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in(31 downto 24); --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor(LOGICAL,1124) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q <= not (ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a or ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top(CONSTANT,1056) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q <= "01101"; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp(LOGICAL,1057) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q <= "1" when ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a = ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b else "0"; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg(REG,1058) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena(REG,1125) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q = "1") THEN ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd(LOGICAL,1126) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b <= en; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a and ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b; --yAddr_uid63_asinX_uid8_fpArcsinPiTest(BITSELECT,62)@1 yAddr_uid63_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b; yAddr_uid63_asinX_uid8_fpArcsinPiTest_b <= yAddr_uid63_asinX_uid8_fpArcsinPiTest_in(34 downto 27); --reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0(REG,464)@1 reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q <= yAddr_uid63_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid255_arcsinXO2XTabGen_lutmem(DUALMEM,451)@2 memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q; memoryC2_uid255_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC2_uid255_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia ); memoryC2_uid255_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1(REG,466)@4 reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q <= memoryC2_uid255_arcsinXO2XTabGen_lutmem_q; END IF; END IF; END PROCESS; --yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest(BITSELECT,63)@1 yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b(26 downto 0); yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in(26 downto 9); --yT1_uid256_arcsinXO2XPolyEval(BITSELECT,255)@1 yT1_uid256_arcsinXO2XPolyEval_in <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b; yT1_uid256_arcsinXO2XPolyEval_b <= yT1_uid256_arcsinXO2XPolyEval_in(17 downto 6); --ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1218) ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 12, depth => 1 ) PORT MAP ( xin => yT1_uid256_arcsinXO2XPolyEval_b, xout => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a(DELAY,992)@1 ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a : dspba_delay GENERIC MAP ( width => 12, depth => 2 ) PORT MAP ( xin => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q, xout => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0(REG,465)@4 reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q <= ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q; END IF; END IF; END PROCESS; --prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval(MULT,415)@5 prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b); prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a <= reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q; prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b <= reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q; prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q <= prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval(BITSELECT,416)@8 prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in <= prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q; prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in(23 downto 11); --highBBits_uid259_arcsinXO2XPolyEval(BITSELECT,258)@8 highBBits_uid259_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b; highBBits_uid259_arcsinXO2XPolyEval_b <= highBBits_uid259_arcsinXO2XPolyEval_in(12 downto 1); --ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1219) ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => yAddr_uid63_asinX_uid8_fpArcsinPiTest_b, xout => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a(DELAY,994)@1 ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, xout => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0(REG,467)@5 reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q <= ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid254_arcsinXO2XTabGen_lutmem(DUALMEM,450)@6 memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q; memoryC1_uid254_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 19, widthad_a => 8, numwords_a => 256, width_b => 19, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC1_uid254_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia ); memoryC1_uid254_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq(18 downto 0); --sumAHighB_uid260_arcsinXO2XPolyEval(ADD,259)@8 sumAHighB_uid260_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid254_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid254_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid260_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid259_arcsinXO2XPolyEval_b(11)) & highBBits_uid259_arcsinXO2XPolyEval_b); sumAHighB_uid260_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid260_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid260_arcsinXO2XPolyEval_b)); sumAHighB_uid260_arcsinXO2XPolyEval_q <= sumAHighB_uid260_arcsinXO2XPolyEval_o(19 downto 0); --lowRangeB_uid258_arcsinXO2XPolyEval(BITSELECT,257)@8 lowRangeB_uid258_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b(0 downto 0); lowRangeB_uid258_arcsinXO2XPolyEval_b <= lowRangeB_uid258_arcsinXO2XPolyEval_in(0 downto 0); --s1_uid258_uid261_arcsinXO2XPolyEval(BITJOIN,260)@8 s1_uid258_uid261_arcsinXO2XPolyEval_q <= sumAHighB_uid260_arcsinXO2XPolyEval_q & lowRangeB_uid258_arcsinXO2XPolyEval_b; --reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1(REG,469)@8 reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q <= s1_uid258_uid261_arcsinXO2XPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor(LOGICAL,1188) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a or ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena(REG,1189) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q = "1") THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd(LOGICAL,1190) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b <= en; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b; --reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0(REG,468)@1 reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem(DUALMEM,1179) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0 <= areset; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia <= reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 3, numwords_a => 6, width_b => 18, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq, address_a => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa, data_a => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia ); ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq(17 downto 0); --prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval(MULT,418)@9 prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a),19)) * SIGNED(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b); prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q; prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b <= reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q; prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr,39)); END IF; END IF; END PROCESS; prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q <= prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval(BITSELECT,419)@12 prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in <= prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q; prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in(38 downto 17); --highBBits_uid265_arcsinXO2XPolyEval(BITSELECT,264)@12 highBBits_uid265_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b; highBBits_uid265_arcsinXO2XPolyEval_b <= highBBits_uid265_arcsinXO2XPolyEval_in(21 downto 2); --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor(LOGICAL,1213) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b); --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena(REG,1214) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q = "1") THEN ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd(LOGICAL,1215) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b <= en; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b; --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem(DUALMEM,1204) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia ); ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq(7 downto 0); --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1203) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q, xout => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC0_uid253_arcsinXO2XTabGen_lutmem(DUALMEM,449)@10 memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q; memoryC0_uid253_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC0_uid253_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia ); memoryC0_uid253_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq(29 downto 0); --sumAHighB_uid266_arcsinXO2XPolyEval(ADD,265)@12 sumAHighB_uid266_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid253_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid253_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid266_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid265_arcsinXO2XPolyEval_b(19)) & highBBits_uid265_arcsinXO2XPolyEval_b); sumAHighB_uid266_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid266_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid266_arcsinXO2XPolyEval_b)); sumAHighB_uid266_arcsinXO2XPolyEval_q <= sumAHighB_uid266_arcsinXO2XPolyEval_o(30 downto 0); --lowRangeB_uid264_arcsinXO2XPolyEval(BITSELECT,263)@12 lowRangeB_uid264_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b(1 downto 0); lowRangeB_uid264_arcsinXO2XPolyEval_b <= lowRangeB_uid264_arcsinXO2XPolyEval_in(1 downto 0); --s2_uid264_uid267_arcsinXO2XPolyEval(BITJOIN,266)@12 s2_uid264_uid267_arcsinXO2XPolyEval_q <= sumAHighB_uid266_arcsinXO2XPolyEval_q & lowRangeB_uid264_arcsinXO2XPolyEval_b; --fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest(BITSELECT,65)@12 fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in <= s2_uid264_uid267_arcsinXO2XPolyEval_q(30 downto 0); fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b <= fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in(30 downto 5); --reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1(REG,472)@12 reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q <= fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor(LOGICAL,1229) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q <= not (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a or ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b); --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top(CONSTANT,1225) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q <= "01010"; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp(LOGICAL,1226) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q); ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q <= "1" when ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a = ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b else "0"; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg(REG,1227) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena(REG,1230) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q = "1") THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd(LOGICAL,1231) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b <= en; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a and ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt(COUNTER,1221) -- every=1, low=0, high=10, step=1, init=1 ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i = 9 THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '1'; ELSE ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i - 10; ELSE ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i,4)); --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg(REG,1222) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux(MUX,1223) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s <= en; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux: PROCESS (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s, ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q, ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q; WHEN "1" => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem(DUALMEM,1220) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0 <= areset; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia <= oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 4, numwords_a => 11, width_b => 24, widthad_b => 4, numwords_b => 11, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq, address_a => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa, data_a => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia ); ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq(23 downto 0); --reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0(REG,471)@12 reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q; END IF; END IF; END PROCESS; --mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest(MULT,66)@13 mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr <= UNSIGNED(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a) * UNSIGNED(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b); mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a <= (others => '0'); mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b <= (others => '0'); mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a <= reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q; mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b <= reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q; mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 <= STD_LOGIC_VECTOR(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr); END IF; END IF; END PROCESS; mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1; END IF; END IF; END PROCESS; --normBitPath2_uid68_asinX_uid8_fpArcsinPiTest(BITSELECT,67)@16 normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q; normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in(49 downto 49); --add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest(BITJOIN,72)@16 add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b & cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q & VCC_q; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor(LOGICAL,1060) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q <= not (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a or ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena(REG,1061) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd(LOGICAL,1062) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a and ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem(DUALMEM,1051) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 <= areset; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 14, width_b => 8, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq, address_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa, data_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia ); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq(7 downto 0); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg(DELAY,1050) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q, xout => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest(BITSELECT,68)@16 fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q(48 downto 0); fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b <= fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in(48 downto 25); --fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest(BITSELECT,69)@16 fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q(47 downto 0); fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b <= fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in(47 downto 24); --fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest(MUX,70)@16 fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b; fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s, en, fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b, fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b) BEGIN CASE fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b; WHEN "1" => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest(BITJOIN,73)@16 expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q & fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q; --expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest(ADD,74)@16 expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q); expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00000000" & add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q); expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b)); expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o(32 downto 0); --expRPath2_uid77_asinX_uid8_fpArcsinPiTest(BITSELECT,76)@16 expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q(31 downto 0); expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b <= expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in(31 downto 24); --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg(DELAY,1114) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b, xout => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt(COUNTER,1052) -- every=1, low=0, high=13, step=1, init=1 ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i = 12 THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i - 13; ELSE ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i,4)); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg(REG,1053) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux(MUX,1054) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux: PROCESS (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s, ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q, ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem(DUALMEM,1115) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 <= areset; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 14, width_b => 8, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0, clock1 => clk, address_b => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq, address_a => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa, data_a => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia ); ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq(7 downto 0); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor(LOGICAL,1111) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q <= not (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a or ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena(REG,1112) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd(LOGICAL,1113) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a and ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem(DUALMEM,1102) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 <= areset; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 31, width_b => 8, widthad_b => 5, numwords_b => 31, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq, address_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa, data_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia ); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq(7 downto 0); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor(LOGICAL,1074) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q <= not (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a or ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top(CONSTANT,1070) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q <= "011100"; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp(LOGICAL,1071) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q); ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q <= "1" when ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a = ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b else "0"; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg(REG,1072) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena(REG,1075) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q = "1") THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd(LOGICAL,1076) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b <= en; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a and ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b; --arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest(BITSELECT,57)@1 arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b <= arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in(36 downto 36); --biasMwShift_uid50_asinX_uid8_fpArcsinPiTest(CONSTANT,49) biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q <= "01110011"; --arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest(COMPARE,50)@0 arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin <= GND_q; arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q) & '0'; arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_asinX_uid8_fpArcsinPiTest_b) & arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin(0); arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b)); END IF; END IF; END PROCESS; arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n(0) <= not arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o(10); --Y34_uid60_asinX_uid8_fpArcsinPiTest(BITSELECT,59)@1 Y34_uid60_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b; Y34_uid60_asinX_uid8_fpArcsinPiTest_b <= Y34_uid60_asinX_uid8_fpArcsinPiTest_in(34 downto 34); --path2_uid61_asinX_uid8_fpArcsinPiTest(LOGICAL,60)@1 path2_uid61_asinX_uid8_fpArcsinPiTest_a <= Y34_uid60_asinX_uid8_fpArcsinPiTest_b; path2_uid61_asinX_uid8_fpArcsinPiTest_q <= not path2_uid61_asinX_uid8_fpArcsinPiTest_a; --pathSelBits_uid112_asinX_uid8_fpArcsinPiTest(BITJOIN,111)@1 pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q <= arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b & arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n & path2_uid61_asinX_uid8_fpArcsinPiTest_q; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1064) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q, xout => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt(COUNTER,1066) -- every=1, low=0, high=28, step=1, init=1 ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i = 27 THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i - 28; ELSE ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i,5)); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg(REG,1067) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux(MUX,1068) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s <= en; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s, ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q, ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; WHEN "1" => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem(DUALMEM,1065) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 <= areset; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 5, numwords_a => 29, width_b => 3, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq, address_a => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa, data_a => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia ); ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq(2 downto 0); --fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest(LOOKUP,112)@32 fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest: PROCESS (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q) BEGIN -- Begin reserved scope level CASE (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q) IS WHEN "000" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "001" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "010" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "011" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "100" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "101" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "110" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "111" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN OTHERS => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRCalc_uid117_asinX_uid8_fpArcsinPiTest(MUX,116)@32 expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s <= fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q; expRCalc_uid117_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q; WHEN "10" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q; WHEN "11" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor(LOGICAL,1150) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q <= not (ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a or ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b); --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena(REG,1151) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q = "1") THEN ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd(LOGICAL,1152) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b <= en; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a and ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b; --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg(DELAY,1140) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q, xout => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem(DUALMEM,1141) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 <= areset; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 29, width_b => 1, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq, address_a => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa, data_a => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia ); ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq(0 downto 0); --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor(LOGICAL,1137) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q <= not (ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a or ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b); --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena(REG,1138) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q = "1") THEN ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd(LOGICAL,1139) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b <= en; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a and ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b; --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1127) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q, xout => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem(DUALMEM,1128) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 <= areset; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 29, width_b => 1, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq, address_a => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa, data_a => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia ); ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq(0 downto 0); --excSelBits_uid120_asinX_uid8_fpArcsinPiTest(BITJOIN,119)@31 excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q; --reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0(REG,458)@31 reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q <= excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest(LOOKUP,120)@32 outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= (others => '-'); END CASE; END IF; END PROCESS; --expRPostExc_uid123_asinX_uid8_fpArcsinPiTest(MUX,122)@33 expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s <= outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q; expRPostExc_uid123_asinX_uid8_fpArcsinPiTest: PROCESS (expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPath3_uid110_asinX_uid8_fpArcsinPiTest(BITSELECT,109)@32 fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q(23 downto 0); fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b <= fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in(23 downto 1); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor(LOGICAL,1099) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q <= not (ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a or ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena(REG,1100) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q = "1") THEN ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd(LOGICAL,1101) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b <= en; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a and ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b; --fracRPath2_uid76_asinX_uid8_fpArcsinPiTest(BITSELECT,75)@16 fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q(23 downto 0); fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b <= fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in(23 downto 1); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg(DELAY,1089) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b, xout => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem(DUALMEM,1090) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 <= areset; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 4, numwords_a => 14, width_b => 23, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0, clock1 => clk, address_b => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq, address_a => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa, data_a => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia ); ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq(22 downto 0); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor(LOGICAL,1086) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q <= not (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a or ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena(REG,1087) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q = "1") THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd(LOGICAL,1088) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b <= en; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a and ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem(DUALMEM,1077) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 <= areset; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia <= fracX_uid16_asinX_uid8_fpArcsinPiTest_b; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 5, numwords_a => 31, width_b => 23, widthad_b => 5, numwords_b => 31, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq, address_a => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa, data_a => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia ); ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq(22 downto 0); --piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest(BITSELECT,113)@32 piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in <= piO2_uid101_asinX_uid8_fpArcsinPiTest_q(26 downto 0); piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b <= piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in(26 downto 4); --fracRCalc_uid115_asinX_uid8_fpArcsinPiTest(MUX,114)@32 fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s <= fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q; fracRCalc_uid115_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b; WHEN "01" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q; WHEN "10" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q; WHEN "11" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest(MUX,121)@33 fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s <= outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q; fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid126_asinX_uid8_fpArcsinPiTest(BITJOIN,125)@33 R_uid126_asinX_uid8_fpArcsinPiTest_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q & expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q & fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q; --fracX_uid132_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,131)@33 fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q(22 downto 0); fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b <= fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 0); --fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,143)@33 fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a <= fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b; fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a = fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --expX_uid128_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,127)@33 expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q(30 downto 0); expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in(30 downto 23); --expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,141)@33 expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b; expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a = expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,144)@33 exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b <= fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a and exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b; --ooPi_uid9_fpArcsinPiTest(CONSTANT,8) ooPi_uid9_fpArcsinPiTest_q <= "101000101111100110000011"; --fracOOPi_uid10_fpArcsinPiTest(BITSELECT,9)@33 fracOOPi_uid10_fpArcsinPiTest_in <= ooPi_uid9_fpArcsinPiTest_q(22 downto 0); fracOOPi_uid10_fpArcsinPiTest_b <= fracOOPi_uid10_fpArcsinPiTest_in(22 downto 0); --fpOOPi_uid11_fpArcsinPiTest(BITJOIN,10)@33 fpOOPi_uid11_fpArcsinPiTest_q <= GND_q & cstBiasM2_uid6_fpArcsinPiTest_q & fracOOPi_uid10_fpArcsinPiTest_b; --expY_uid129_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,128)@33 expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q(30 downto 0); expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in(30 downto 23); --expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,155)@33 expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b; expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a = expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,209)@33 excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q <= excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a and excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b; --fracY_uid134_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,133)@33 fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q(22 downto 0); fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b <= fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 0); --fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,159)@33 fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a <= fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b; fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a = fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,157)@33 expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b; expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a = expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,160)@33 exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b <= fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a and exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b; --expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,139)@33 expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b; expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a = expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,210)@33 excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b; --ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,211)@33 ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a <= excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q; ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b <= excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q; ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q <= ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a or ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b; END IF; END PROCESS; --InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,161)@33 InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a <= fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q; InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q <= not InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a; --exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,162)@33 exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b <= InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q <= exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a and exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b; --ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,742)@33 ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,145)@33 InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a <= fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q; InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q <= not InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a; --exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,146)@33 exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b <= InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a and exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b; --reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1(REG,519)@33 reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,212)@34 excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a <= reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q; excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q; excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c <= ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q; excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q <= excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a or excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b or excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c; --VCC(CONSTANT,1) VCC_q <= "1"; --InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,224)@34 InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a <= excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q; InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a; --signY_uid131_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,130)@33 signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q; signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b <= signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in(31 downto 31); --signX_uid130_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,129)@33 signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q; signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b <= signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in(31 downto 31); --signR_uid196_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,195)@33 signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a <= signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b; signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b <= signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b; signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q <= signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a xor signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b; --ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,753)@33 ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,225)@34 signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a <= ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q; signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b <= InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q; signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q <= signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a and signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b; --ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,757)@34 ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,134)@33 add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q <= VCC_q & fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b; --add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,132)@33 add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q <= VCC_q & fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b; --prod_uid171_rAsinPi_uid13_fpArcsinPiTest(MULT,170)@33 prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr <= UNSIGNED(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a) * UNSIGNED(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b); prod_uid171_rAsinPi_uid13_fpArcsinPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a <= (others => '0'); prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b <= (others => '0'); prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a <= add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q; prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b <= add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q; prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr); END IF; END IF; END PROCESS; prod_uid171_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,171)@36 normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q; normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in(47 downto 47); --fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,173)@36 fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(46 downto 0); fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in(46 downto 23); --fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,174)@36 fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(45 downto 0); fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in(45 downto 22); --fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest(MUX,175)@36 fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b; fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest: PROCESS (fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s, en, fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b, fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b) BEGIN CASE fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "0" => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b; WHEN "1" => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b; WHEN OTHERS => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,183)@36 FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in <= fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q(1 downto 0); FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b <= FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in(1 downto 0); --Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,177)@36 Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(22 downto 0); Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b <= Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 22); --extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest(MUX,178)@36 extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b; extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest: PROCESS (extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s, en, GND_q, Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b) BEGIN CASE extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "0" => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b; WHEN OTHERS => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,176)@36 stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(21 downto 0); stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b <= stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in(21 downto 0); --stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,179)@36 stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q <= extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q & stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b; --stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,181)@36 stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a <= stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q; stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a = stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --sticky_uid183_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,182)@36 sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a <= stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q; sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q <= not sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a; --lrs_uid185_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,184)@36 lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q <= FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b & sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q; --roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,186)@36 roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a <= lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q; roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b <= roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q; roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a = roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,187)@36 roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a <= roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q; roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q <= not roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a; --roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,190)@36 roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q <= GND_q & normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b & cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q & roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q; --reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1(REG,514)@36 reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q <= roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest(CONSTANT,168) biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q <= "0001111111"; --expSum_uid168_rAsinPi_uid13_fpArcsinPiTest(ADD,167)@33 expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b); expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b); expSum_uid168_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a) + UNSIGNED(expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b)); END IF; END IF; END PROCESS; expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q <= expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o(8 downto 0); --ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,674)@34 ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest(SUB,169)@35 expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q); expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q(9)) & biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q); expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q <= expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o(10 downto 0); --expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,188)@36 expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q <= expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q & fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q; --reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0(REG,513)@36 reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q <= expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest(ADD,191)@37 expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q(34)) & reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q); expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q); expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a) + SIGNED(expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b)); expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o(35 downto 0); --expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,193)@37 expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q; expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in(35 downto 24); --expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,194)@37 expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b(7 downto 0); expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b <= expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in(7 downto 0); --ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a(DELAY,1049)@37 ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b, xout => ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3(REG,522)@38 reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q <= ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,746)@34 ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1(REG,515)@37 reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest(COMPARE,198)@38 expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin <= GND_q; expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q(11)) & reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q) & '0'; expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) & expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin(0); expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b)); expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n(0) <= not expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o(14); --InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,163)@33 InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a <= exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a; --InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,164)@33 InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a; --InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,165)@33 InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a; --exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,166)@33 exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a <= InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b <= InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c <= InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a and exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b and exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c; --ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,716)@33 ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,147)@33 InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a; --InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,148)@33 InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a; --InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,149)@33 InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a; --exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,150)@33 exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a <= InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b <= InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c <= InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a and exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b and exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c; --ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a(DELAY,1045)@33 ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1(REG,518)@37 reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q <= ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q; END IF; END IF; END PROCESS; --ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,207)@38 ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a <= reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q; ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q; ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c <= expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n; ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q <= ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a and ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b and ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c; --excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,206)@33 excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q; excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q <= excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a and excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,733)@33 ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,205)@33 excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q; excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q <= excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a and excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,732)@33 ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,204)@33 excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q <= excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a and excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,731)@33 ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,208)@38 excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a <= ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b <= ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c <= ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d <= ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q <= excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d; --expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest(COMPARE,196)@38 expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin <= GND_q; expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q(11)) & reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q) & expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin(0); expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b)); expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n(0) <= not expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o(14); --reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1(REG,516)@33 reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,715)@34 ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q, xout => ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,202)@38 excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a <= ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q; excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q; excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c <= expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n; excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q <= excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a and excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b and excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c; --excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,201)@33 excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q <= excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a and excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,720)@33 ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,200)@33 excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,719)@33 ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,199)@33 excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,718)@33 ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,203)@38 excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a <= ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b <= ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c <= ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d <= excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q <= excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d; --concExc_uid214_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,213)@38 concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q <= ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q & excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q & excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q; --reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0(REG,520)@38 reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q <= concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest(LOOKUP,214)@39 excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest: PROCESS (reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q) IS WHEN "000" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "01"; WHEN "001" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "010" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "10"; WHEN "011" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "100" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "11"; WHEN "101" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "110" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "111" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN OTHERS => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest(MUX,223)@39 expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s <= excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q; expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest: PROCESS (expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "00" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q; WHEN "10" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,192)@37 fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q(23 downto 0); fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in(23 downto 1); --ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a(DELAY,1048)@37 ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b, xout => ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3(REG,521)@38 reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q <= ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q; END IF; END IF; END PROCESS; --fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest(MUX,218)@39 fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s <= excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q; fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest: PROCESS (fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "00" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q; WHEN "10" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid227_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,226)@39 R_uid227_rAsinPi_uid13_fpArcsinPiTest_q <= ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q & expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q & fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q; --xOut(GPOUT,4)@39 q <= R_uid227_rAsinPi_uid13_fpArcsinPiTest_q; end normal;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_castytol.vhd	10	6849	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_CASTYTOL.VHD * --* * --* Function: Cast Internal Double Format to * --* Long * --* * --* 13/12/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --*********************************************** ENTITY hcc_castytol IS GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aazip, aasat : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytol; ARCHITECTURE rtl OF hcc_castytol IS signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (13 DOWNTO 1); signal midpoint, maxpoint, minpoint : STD_LOGIC_VECTOR (13 DOWNTO 1); signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (13 DOWNTO 1); signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (64 DOWNTO 1); signal selectleftbit, selectleftbitdel : STD_LOGIC; signal satshiftbit, satshiftout : STD_LOGIC; signal zipshiftbit, zipshiftout : STD_LOGIC; signal satout, zipout : STD_LOGIC; signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1); component hcc_delaybit IS GENERIC (delay : positive := 32); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; component hcc_lsftcomb64 PORT ( inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; component hcc_lsftpipe64 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; component hcc_rsftpipe64 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; component hcc_rsftcomb64 PORT ( inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; BEGIN midpoint <= conv_std_logic_vector (1054,13); maxpoint <= conv_std_logic_vector (1118,13); minpoint <= conv_std_logic_vector (1022,13); leftshiftnum <= aa(13 DOWNTO 1) - midpoint; -- 1054 is 1.0 point rightshiftnum <= midpoint - aa(13 DOWNTO 1); -- because of 64 bit Y mantissa > 32 bit long, left shift range > right shift rangre leftshiftmax <= aa(13 DOWNTO 1) - maxpoint; -- 1118 is the max - if +ve, saturate rightshiftmin <= aa(13 DOWNTO 1) - minpoint; -- 1022 is the min - if -ve, zero selectleftbit <= rightshiftnum(13); satshiftbit <= selectleftbit AND NOT(leftshiftmax(13)); zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(13); gsa: IF (normspeed = 1) GENERATE sftlc: hcc_lsftcomb64 PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1), outbus=>leftshiftbus); sftrc: hcc_rsftcomb64 PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1), outbus=>rightshiftbus); END GENERATE; gsb: IF (normspeed > 1) GENERATE sftlp: hcc_lsftpipe64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1), outbus=>leftshiftbus); sftrp: hcc_rsftpipe64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1), outbus=>rightshiftbus); END GENERATE; --* DELAY CONTROL AND CONDITION SIGNALS * dbmux: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>selectleftbit,cc=>selectleftbitdel); dbsat: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aasat,cc=>satout); dbzip: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aazip,cc=>zipout); dbsftsat: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>satshiftbit,cc=>satshiftout); dbsftzip: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>zipshiftbit,cc=>zipshiftout); --* OUTPUT MUX * pao: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP leftshiftbusff(k) <= '0'; rightshiftbusff(k) <= '0'; shiftmuxff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN leftshiftbusff <= leftshiftbus(64 DOWNTO 33); rightshiftbusff <= rightshiftbus(64 DOWNTO 33); FOR k IN 1 TO 32 LOOP shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR (rightshiftbusff(k) AND NOT(selectleftbitdel))) OR (satout OR satshiftout)) AND NOT(zipout OR zipshiftout); END LOOP; END IF; END IF; END PROCESS; --********** --* OUTPUT * --************ cc <= shiftmuxff; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/dp_subs.vhd	10	2556	LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* DOUBLE PRECISION CORE LIBRARY * --* * --* DP_ADDS.VHD * --* * --* Function: Synthesizable Fixed Point * --* Subtractor * --* * --* 31/01/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY dp_subs IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END dp_subs; ARCHITECTURE syn of dp_subs IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "SUB", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => borrowin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;	mit
ou-cse-378/vhdl-tetris	pc.vhd	1	1080	-- ================================================================================= -- // Name: Bryan Mason, James Batcheler, & Brad McMahon -- // File: PC.vhd -- // Date: 12/9/2004 -- // Description: Program Counter -- // Class: CSE 378 -- ================================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PC is port ( d : in STD_LOGIC_VECTOR (15 downto 0); clr : in STD_LOGIC; clk : in STD_LOGIC; inc : in STD_LOGIC; pload : in STD_LOGIC; q : out STD_LOGIC_VECTOR (15 downto 0) ); end PC; architecture PC_arch of PC is signal COUNT: STD_LOGIC_VECTOR (15 downto 0); begin process (clk, clr) begin if clr = '1' then COUNT <= "0000000000000000"; elsif clk'event and clk='1' then if pload = '0' then if inc = '1' then COUNT <= COUNT + 1; end if; else COUNT <= d; end if; end if; q <= COUNT; end process; end PC_arch;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_ln_s5.vhd	10	195654	----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_ln_s5 -- VHDL created on Wed Feb 27 15:13:10 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from /data/tczajkow/polyeval/p4/ip/aion/src/mip_common/hw_model.cpp:1248 entity fp_ln_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_ln_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (22 downto 0); signal cstBias_uid9_fpLogETest_q : std_logic_vector (7 downto 0); signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (7 downto 0); signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (7 downto 0); signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (7 downto 0); signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0); signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0); signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0); signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0); signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0); signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0); signal multTermOne_uid42_fpLogETest_q : std_logic_vector (24 downto 0); signal postPEMul_uid43_fpLogETest_a : std_logic_vector (24 downto 0); signal postPEMul_uid43_fpLogETest_b : std_logic_vector (25 downto 0); signal postPEMul_uid43_fpLogETest_s1 : std_logic_vector (50 downto 0); signal postPEMul_uid43_fpLogETest_pr : SIGNED (50 downto 0); signal postPEMul_uid43_fpLogETest_q : std_logic_vector (50 downto 0); signal wideZero_uid44_fpLogETest_q : std_logic_vector (34 downto 0); signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0); signal addTermOne_uid45_fpLogETest_q : std_logic_vector (34 downto 0); signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(56 downto 0); signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(56 downto 0); signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(56 downto 0); signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (8 downto 0); signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0); signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0); signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0); signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0); signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (22 downto 0); signal p1_uid92_constMult_q : std_logic_vector(36 downto 0); signal p0_uid93_constMult_q : std_logic_vector(33 downto 0); signal zs_uid113_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0); signal mO_uid116_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0); signal zs_uid121_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0); signal zs_uid133_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q : std_logic_vector (47 downto 0); signal leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q : std_logic_vector (11 downto 0); signal leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q : std_logic_vector (2 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_b : std_logic_vector (22 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_s1 : std_logic_vector (37 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_pr : SIGNED (38 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_q : std_logic_vector (37 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (30 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (30 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (30 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid98_natLogTabGen_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid99_natLogTabGen_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_q : std_logic_vector (12 downto 0); signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0); signal reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q : std_logic_vector (8 downto 0); signal reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q : std_logic_vector (22 downto 0); signal reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q : std_logic_vector (25 downto 0); signal reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0); signal reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0); signal reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q : std_logic_vector (3 downto 0); signal reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q : std_logic_vector (3 downto 0); signal reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q : std_logic_vector (0 downto 0); signal reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q : std_logic_vector (57 downto 0); signal reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q : std_logic_vector (57 downto 0); signal reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q : std_logic_vector (57 downto 0); signal reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q : std_logic_vector (57 downto 0); signal reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0); signal reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q : std_logic_vector (5 downto 0); signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (33 downto 0); signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0); signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q : std_logic_vector (22 downto 0); signal ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q : std_logic_vector (0 downto 0); signal ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0); signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0); signal ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q : std_logic_vector (0 downto 0); signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q : std_logic_vector (41 downto 0); signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q : std_logic_vector (25 downto 0); signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q : std_logic_vector (9 downto 0); signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q : std_logic_vector (57 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q : std_logic_vector (8 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true; signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q : std_logic_vector (22 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 : std_logic; signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq : std_logic; signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : signal is true; signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (41 downto 0); signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (25 downto 0); signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (9 downto 0); signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q : std_logic_vector (57 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 : std_logic; signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq : std_logic; signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : signal is true; signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : signal is true; signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (23 downto 0); signal FPOne_uid63_fpLogETest_q : std_logic_vector (31 downto 0); signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(34 downto 0); signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(34 downto 0); signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (34 downto 0); signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (34 downto 0); signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0); signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal expX_uid6_fpLogETest_in : std_logic_vector (30 downto 0); signal expX_uid6_fpLogETest_b : std_logic_vector (7 downto 0); signal signX_uid7_fpLogETest_in : std_logic_vector (31 downto 0); signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0); signal frac_uid19_fpLogETest_in : std_logic_vector (22 downto 0); signal frac_uid19_fpLogETest_b : std_logic_vector (22 downto 0); signal excRZero_uid64_fpLogETest_a : std_logic_vector(31 downto 0); signal excRZero_uid64_fpLogETest_b : std_logic_vector(31 downto 0); signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0); signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0); signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0); signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0); signal e_uid29_fpLogETest_a : std_logic_vector(8 downto 0); signal e_uid29_fpLogETest_b : std_logic_vector(8 downto 0); signal e_uid29_fpLogETest_o : std_logic_vector (8 downto 0); signal e_uid29_fpLogETest_q : std_logic_vector (8 downto 0); signal c_uid31_fpLogETest_a : std_logic_vector(7 downto 0); signal c_uid31_fpLogETest_b : std_logic_vector(7 downto 0); signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0); signal oMz_uid38_fpLogETest_a : std_logic_vector(24 downto 0); signal oMz_uid38_fpLogETest_b : std_logic_vector(24 downto 0); signal oMz_uid38_fpLogETest_o : std_logic_vector (24 downto 0); signal oMz_uid38_fpLogETest_q : std_logic_vector (24 downto 0); signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(57 downto 0); signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(57 downto 0); signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (57 downto 0); signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (57 downto 0); signal expRExt_uid57_fpLogETest_a : std_logic_vector(9 downto 0); signal expRExt_uid57_fpLogETest_b : std_logic_vector(9 downto 0); signal expRExt_uid57_fpLogETest_o : std_logic_vector (9 downto 0); signal expRExt_uid57_fpLogETest_q : std_logic_vector (9 downto 0); signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0); signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0); signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0); signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0); signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0); signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0); signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0); signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0); signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0); signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0); signal lev1_a0_uid94_constMult_a : std_logic_vector(38 downto 0); signal lev1_a0_uid94_constMult_b : std_logic_vector(38 downto 0); signal lev1_a0_uid94_constMult_o : std_logic_vector (38 downto 0); signal lev1_a0_uid94_constMult_q : std_logic_vector (37 downto 0); signal vCount_uid115_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0); signal vCount_uid115_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0); signal vCount_uid115_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid120_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid120_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0); signal vCount_uid123_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0); signal vCount_uid123_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0); signal vCount_uid123_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid126_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid126_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0); signal vCount_uid135_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0); signal vCount_uid135_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0); signal vCount_uid135_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid138_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid138_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0); signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal sEz_uid41_fpLogETest_q : std_logic_vector (24 downto 0); signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (20 downto 0); signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (20 downto 0); signal highBBits_uid47_fpLogETest_in : std_logic_vector (50 downto 0); signal highBBits_uid47_fpLogETest_b : std_logic_vector (29 downto 0); signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(35 downto 0); signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(35 downto 0); signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (35 downto 0); signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (35 downto 0); signal leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in : std_logic_vector (37 downto 0); signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b : std_logic_vector (23 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (14 downto 0); signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (14 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal fracR_uid61_fpLogETest_in : std_logic_vector (23 downto 0); signal fracR_uid61_fpLogETest_b : std_logic_vector (22 downto 0); signal expR_uid62_fpLogETest_in : std_logic_vector (31 downto 0); signal expR_uid62_fpLogETest_b : std_logic_vector (7 downto 0); signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0); signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0); signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (22 downto 0); signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (7 downto 0); signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0); signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0); signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0); signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0); signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0); signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0); signal xv1_uid91_constMult_in : std_logic_vector (8 downto 0); signal xv1_uid91_constMult_b : std_logic_vector (2 downto 0); signal addr_uid34_fpLogETest_q : std_logic_vector (8 downto 0); signal rVStage_uid114_countZ_uid54_fpLogETest_in : std_logic_vector (57 downto 0); signal rVStage_uid114_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0); signal vStage_uid117_countZ_uid54_fpLogETest_in : std_logic_vector (25 downto 0); signal vStage_uid117_countZ_uid54_fpLogETest_b : std_logic_vector (25 downto 0); signal X41dto0_uid152_normVal_uid55_fpLogETest_in : std_logic_vector (41 downto 0); signal X41dto0_uid152_normVal_uid55_fpLogETest_b : std_logic_vector (41 downto 0); signal X9dto0_uid158_normVal_uid55_fpLogETest_in : std_logic_vector (9 downto 0); signal X9dto0_uid158_normVal_uid55_fpLogETest_b : std_logic_vector (9 downto 0); signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (7 downto 0); signal sR_uid95_constMult_in : std_logic_vector (36 downto 0); signal sR_uid95_constMult_b : std_logic_vector (34 downto 0); signal rVStage_uid122_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0); signal rVStage_uid122_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0); signal vStage_uid124_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0); signal vStage_uid124_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0); signal rVStage_uid128_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0); signal rVStage_uid128_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0); signal vStage_uid130_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0); signal vStage_uid130_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0); signal rVStage_uid140_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0); signal rVStage_uid140_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0); signal vStage_uid142_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0); signal vStage_uid142_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0); signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in : std_logic_vector (56 downto 0); signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b : std_logic_vector (56 downto 0); signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in : std_logic_vector (55 downto 0); signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b : std_logic_vector (55 downto 0); signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in : std_logic_vector (54 downto 0); signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b : std_logic_vector (54 downto 0); signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (56 downto 0); signal lowRangeB_uid102_natLogPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid102_natLogPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid103_natLogPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid103_natLogPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid108_natLogPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid108_natLogPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid109_natLogPolyEval_in : std_logic_vector (23 downto 0); signal highBBits_uid109_natLogPolyEval_b : std_logic_vector (21 downto 0); signal yT1_uid100_natLogPolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid100_natLogPolyEval_b : std_logic_vector (12 downto 0); signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0); signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0); signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0); signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0); signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0); signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0); signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0); signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0); signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0); signal cStage_uid118_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0); signal RLn_uid88_fpLogETest_q : std_logic_vector (31 downto 0); signal vCount_uid129_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0); signal vCount_uid129_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0); signal vCount_uid129_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid132_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid132_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0); signal vCount_uid141_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0); signal vCount_uid141_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0); signal vCount_uid141_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid144_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid144_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal FullSumAB56_uid50_fpLogETest_in : std_logic_vector (56 downto 0); signal FullSumAB56_uid50_fpLogETest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid104_natLogPolyEval_a : std_logic_vector(21 downto 0); signal sumAHighB_uid104_natLogPolyEval_b : std_logic_vector(21 downto 0); signal sumAHighB_uid104_natLogPolyEval_o : std_logic_vector (21 downto 0); signal sumAHighB_uid104_natLogPolyEval_q : std_logic_vector (21 downto 0); signal sumAHighB_uid110_natLogPolyEval_a : std_logic_vector(31 downto 0); signal sumAHighB_uid110_natLogPolyEval_b : std_logic_vector(31 downto 0); signal sumAHighB_uid110_natLogPolyEval_o : std_logic_vector (31 downto 0); signal sumAHighB_uid110_natLogPolyEval_q : std_logic_vector (31 downto 0); signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0); signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0); signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0); signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0); signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0); signal rVStage_uid134_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0); signal rVStage_uid134_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0); signal vStage_uid136_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0); signal vStage_uid136_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0); signal rVStage_uid146_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0); signal rVStage_uid146_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0); signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0); signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0); signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0); signal s1_uid102_uid105_natLogPolyEval_q : std_logic_vector (22 downto 0); signal s2_uid108_uid111_natLogPolyEval_q : std_logic_vector (33 downto 0); signal vCount_uid147_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0); signal vCount_uid147_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0); signal vCount_uid147_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal fracR_uid58_fpLogETest_in : std_logic_vector (56 downto 0); signal fracR_uid58_fpLogETest_b : std_logic_vector (23 downto 0); signal peOR_uid37_fpLogETest_in : std_logic_vector (32 downto 0); signal peOR_uid37_fpLogETest_b : std_logic_vector (25 downto 0); signal r_uid148_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0); signal expFracConc_uid59_fpLogETest_q : std_logic_vector (33 downto 0); signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in : std_logic_vector (5 downto 0); signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0); signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in : std_logic_vector (53 downto 0); signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b : std_logic_vector (53 downto 0); signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in : std_logic_vector (49 downto 0); signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b : std_logic_vector (49 downto 0); signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in : std_logic_vector (45 downto 0); signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b : std_logic_vector (45 downto 0); signal leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); begin --xIn(GPIN,3)@0 --cstBiasMO_uid10_fpLogETest(CONSTANT,9) cstBiasMO_uid10_fpLogETest_q <= "01111110"; --expX_uid6_fpLogETest(BITSELECT,5)@0 expX_uid6_fpLogETest_in <= a(30 downto 0); expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(30 downto 23); --c_uid31_fpLogETest(LOGICAL,30)@0 c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b; c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q; c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0"; --frac_uid19_fpLogETest(BITSELECT,18)@0 frac_uid19_fpLogETest_in <= a(22 downto 0); frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(22 downto 0); --zAddrLow_uid33_fpLogETest(BITSELECT,32)@0 zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b; zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(22 downto 15); --addr_uid34_fpLogETest(BITJOIN,33)@0 addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b; --reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0(REG,194)@0 reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q; END IF; END IF; END PROCESS; --memoryC2_uid99_natLogTabGen_lutmem(DUALMEM,192)@1 memoryC2_uid99_natLogTabGen_lutmem_reset0 <= areset; memoryC2_uid99_natLogTabGen_lutmem_ia <= (others => '0'); memoryC2_uid99_natLogTabGen_lutmem_aa <= (others => '0'); memoryC2_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q; memoryC2_uid99_natLogTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 9, numwords_a => 512, width_b => 13, widthad_b => 9, numwords_b => 512, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_ln_s5_memoryC2_uid99_natLogTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid99_natLogTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid99_natLogTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid99_natLogTabGen_lutmem_iq, address_a => memoryC2_uid99_natLogTabGen_lutmem_aa, data_a => memoryC2_uid99_natLogTabGen_lutmem_ia ); memoryC2_uid99_natLogTabGen_lutmem_q <= memoryC2_uid99_natLogTabGen_lutmem_iq(12 downto 0); --reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1(REG,196)@3 reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= memoryC2_uid99_natLogTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a(DELAY,244)@0 ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg(DELAY,451) ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --zPPolyEval_uid35_fpLogETest(BITSELECT,34)@3 zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q(14 downto 0); zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(14 downto 0); --yT1_uid100_natLogPolyEval(BITSELECT,99)@3 yT1_uid100_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b; yT1_uid100_natLogPolyEval_b <= yT1_uid100_natLogPolyEval_in(14 downto 2); --reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0(REG,195)@3 reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= yT1_uid100_natLogPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid185_pT1_uid101_natLogPolyEval(MULT,184)@4 prodXY_uid185_pT1_uid101_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_a),14)) * SIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_b); prodXY_uid185_pT1_uid101_natLogPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid185_pT1_uid101_natLogPolyEval_a <= (others => '0'); prodXY_uid185_pT1_uid101_natLogPolyEval_b <= (others => '0'); prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid185_pT1_uid101_natLogPolyEval_a <= reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q; prodXY_uid185_pT1_uid101_natLogPolyEval_b <= reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q; prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid185_pT1_uid101_natLogPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid185_pT1_uid101_natLogPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid185_pT1_uid101_natLogPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid185_pT1_uid101_natLogPolyEval_q <= prodXY_uid185_pT1_uid101_natLogPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval(BITSELECT,185)@7 prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in <= prodXY_uid185_pT1_uid101_natLogPolyEval_q; prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in(25 downto 12); --highBBits_uid103_natLogPolyEval(BITSELECT,102)@7 highBBits_uid103_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b; highBBits_uid103_natLogPolyEval_b <= highBBits_uid103_natLogPolyEval_in(13 downto 1); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a(DELAY,409)@1 ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a : dspba_delay GENERIC MAP ( width => 9, depth => 3 ) PORT MAP ( xin => reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg(DELAY,482) ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid98_natLogTabGen_lutmem(DUALMEM,191)@5 memoryC1_uid98_natLogTabGen_lutmem_reset0 <= areset; memoryC1_uid98_natLogTabGen_lutmem_ia <= (others => '0'); memoryC1_uid98_natLogTabGen_lutmem_aa <= (others => '0'); memoryC1_uid98_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q; memoryC1_uid98_natLogTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 9, numwords_a => 512, width_b => 21, widthad_b => 9, numwords_b => 512, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_ln_s5_memoryC1_uid98_natLogTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid98_natLogTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid98_natLogTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid98_natLogTabGen_lutmem_iq, address_a => memoryC1_uid98_natLogTabGen_lutmem_aa, data_a => memoryC1_uid98_natLogTabGen_lutmem_ia ); memoryC1_uid98_natLogTabGen_lutmem_q <= memoryC1_uid98_natLogTabGen_lutmem_iq(20 downto 0); --sumAHighB_uid104_natLogPolyEval(ADD,103)@7 sumAHighB_uid104_natLogPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid98_natLogTabGen_lutmem_q(20)) & memoryC1_uid98_natLogTabGen_lutmem_q); sumAHighB_uid104_natLogPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid103_natLogPolyEval_b(12)) & highBBits_uid103_natLogPolyEval_b); sumAHighB_uid104_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid104_natLogPolyEval_a) + SIGNED(sumAHighB_uid104_natLogPolyEval_b)); sumAHighB_uid104_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_o(21 downto 0); --lowRangeB_uid102_natLogPolyEval(BITSELECT,101)@7 lowRangeB_uid102_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b(0 downto 0); lowRangeB_uid102_natLogPolyEval_b <= lowRangeB_uid102_natLogPolyEval_in(0 downto 0); --s1_uid102_uid105_natLogPolyEval(BITJOIN,104)@7 s1_uid102_uid105_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_q & lowRangeB_uid102_natLogPolyEval_b; --reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1(REG,199)@7 reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= s1_uid102_uid105_natLogPolyEval_q; END IF; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,447) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor(LOGICAL,504) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b); --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg(REG,502) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena(REG,505) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd(LOGICAL,506) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b <= en; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg(DELAY,496) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt(COUNTER,498) -- every=1, low=0, high=1, step=1, init=1 ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i,1)); --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg(REG,499) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux(MUX,500) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s <= en; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem(DUALMEM,497) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 1, numwords_a => 2, width_b => 15, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq, address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa, data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia ); ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq(14 downto 0); --reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0(REG,198)@7 reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid188_pT2_uid107_natLogPolyEval(MULT,187)@8 prodXY_uid188_pT2_uid107_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_a),16)) * SIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_b); prodXY_uid188_pT2_uid107_natLogPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid188_pT2_uid107_natLogPolyEval_a <= (others => '0'); prodXY_uid188_pT2_uid107_natLogPolyEval_b <= (others => '0'); prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid188_pT2_uid107_natLogPolyEval_a <= reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q; prodXY_uid188_pT2_uid107_natLogPolyEval_b <= reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q; prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid188_pT2_uid107_natLogPolyEval_pr,38)); END IF; END IF; END PROCESS; prodXY_uid188_pT2_uid107_natLogPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid188_pT2_uid107_natLogPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid188_pT2_uid107_natLogPolyEval_q <= prodXY_uid188_pT2_uid107_natLogPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval(BITSELECT,188)@11 prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in <= prodXY_uid188_pT2_uid107_natLogPolyEval_q; prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in(37 downto 14); --highBBits_uid109_natLogPolyEval(BITSELECT,108)@11 highBBits_uid109_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b; highBBits_uid109_natLogPolyEval_b <= highBBits_uid109_natLogPolyEval_in(23 downto 2); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor(LOGICAL,479) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q <= not (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a or ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top(CONSTANT,475) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q <= "0101"; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp(LOGICAL,476) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q); ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q <= "1" when ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a = ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b else "0"; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg(REG,477) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena(REG,480) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q = "1") THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd(LOGICAL,481) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b <= en; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a and ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt(COUNTER,471) -- every=1, low=0, high=5, step=1, init=1 ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i = 4 THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i - 5; ELSE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg(REG,472) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux(MUX,473) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s <= en; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem(DUALMEM,470) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 3, numwords_a => 6, width_b => 9, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia ); ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq(8 downto 0); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg(DELAY,469) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,190)@9 memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset; memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0'); memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0'); memoryC0_uid97_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q; memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 31, widthad_a => 9, numwords_a => 512, width_b => 31, widthad_b => 9, numwords_b => 512, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_ln_s5_memoryC0_uid97_natLogTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid97_natLogTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid97_natLogTabGen_lutmem_iq, address_a => memoryC0_uid97_natLogTabGen_lutmem_aa, data_a => memoryC0_uid97_natLogTabGen_lutmem_ia ); memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(30 downto 0); --sumAHighB_uid110_natLogPolyEval(ADD,109)@11 sumAHighB_uid110_natLogPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => memoryC0_uid97_natLogTabGen_lutmem_q(30)) & memoryC0_uid97_natLogTabGen_lutmem_q); sumAHighB_uid110_natLogPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid109_natLogPolyEval_b(21)) & highBBits_uid109_natLogPolyEval_b); sumAHighB_uid110_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid110_natLogPolyEval_a) + SIGNED(sumAHighB_uid110_natLogPolyEval_b)); sumAHighB_uid110_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_o(31 downto 0); --lowRangeB_uid108_natLogPolyEval(BITSELECT,107)@11 lowRangeB_uid108_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b(1 downto 0); lowRangeB_uid108_natLogPolyEval_b <= lowRangeB_uid108_natLogPolyEval_in(1 downto 0); --s2_uid108_uid111_natLogPolyEval(BITJOIN,110)@11 s2_uid108_uid111_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_q & lowRangeB_uid108_natLogPolyEval_b; --peOR_uid37_fpLogETest(BITSELECT,36)@11 peOR_uid37_fpLogETest_in <= s2_uid108_uid111_natLogPolyEval_q(32 downto 0); peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(32 downto 7); --reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1(REG,201)@11 reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= peOR_uid37_fpLogETest_b; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor(LOGICAL,462) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q <= not (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a or ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b); --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top(CONSTANT,458) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q <= "01000"; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp(LOGICAL,459) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q); ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q <= "1" when ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a = ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b else "0"; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg(REG,460) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena(REG,463) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q = "1") THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd(LOGICAL,464) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b <= en; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a and ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b; --GND(CONSTANT,0) GND_q <= "0"; --pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@0 pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((22 downto 1 => GND_q(0)) & GND_q); --oMz_uid38_fpLogETest(SUB,38)@0 oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q); oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & frac_uid19_fpLogETest_b); oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b)); oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(24 downto 0); --z2_uid40_fpLogETest(CONSTANT,39) z2_uid40_fpLogETest_q <= "00"; --sEz_uid41_fpLogETest(BITJOIN,40)@0 sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & frac_uid19_fpLogETest_b; --multTermOne_uid42_fpLogETest(MUX,41)@0 multTermOne_uid42_fpLogETest_s <= c_uid31_fpLogETest_q; multTermOne_uid42_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multTermOne_uid42_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE multTermOne_uid42_fpLogETest_s IS WHEN "0" => multTermOne_uid42_fpLogETest_q <= sEz_uid41_fpLogETest_q; WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q; WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt(COUNTER,454) -- every=1, low=0, high=8, step=1, init=1 ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i = 7 THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '1'; ELSE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i - 8; ELSE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i,4)); --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg(REG,455) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux(MUX,456) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s <= en; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux: PROCESS (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q) BEGIN CASE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s IS WHEN "0" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q; WHEN "1" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q; WHEN OTHERS => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem(DUALMEM,453) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 <= areset; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia <= multTermOne_uid42_fpLogETest_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 25, widthad_a => 4, numwords_a => 9, width_b => 25, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0, clock1 => clk, address_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq, address_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa, data_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia ); ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq(24 downto 0); --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg(DELAY,452) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q, xout => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --postPEMul_uid43_fpLogETest(MULT,42)@12 postPEMul_uid43_fpLogETest_pr <= SIGNED(postPEMul_uid43_fpLogETest_a) * SIGNED(postPEMul_uid43_fpLogETest_b); postPEMul_uid43_fpLogETest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN postPEMul_uid43_fpLogETest_a <= (others => '0'); postPEMul_uid43_fpLogETest_b <= (others => '0'); postPEMul_uid43_fpLogETest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN postPEMul_uid43_fpLogETest_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q; postPEMul_uid43_fpLogETest_b <= reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q; postPEMul_uid43_fpLogETest_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_pr); END IF; END IF; END PROCESS; postPEMul_uid43_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN postPEMul_uid43_fpLogETest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN postPEMul_uid43_fpLogETest_q <= postPEMul_uid43_fpLogETest_s1; END IF; END IF; END PROCESS; --highBBits_uid47_fpLogETest(BITSELECT,46)@15 highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_q; highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(50 downto 21); --wideZero_uid44_fpLogETest(CONSTANT,43) wideZero_uid44_fpLogETest_q <= "00000000000000000000000000000000000"; --cstBias_uid9_fpLogETest(CONSTANT,8) cstBias_uid9_fpLogETest_q <= "01111111"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,448) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b); --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,444) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "01011"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,445) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q); ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,446) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,449) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,450) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=11, step=1, init=1 ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 10 THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 11; ELSE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,4)); --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,441) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,442) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,439) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= expX_uid6_fpLogETest_b; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 12, width_b => 8, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq, address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa, data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia ); ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(7 downto 0); --e_uid29_fpLogETest(SUB,28)@13 e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q); e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q); e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b)); e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(8 downto 0); --xv0_uid90_constMult(BITSELECT,89)@13 xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0); xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0); --p0_uid93_constMult(LOOKUP,92)@13 p0_uid93_constMult: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN p0_uid93_constMult_q <= "0000000000000000000000000000000000"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (xv0_uid90_constMult_b) IS WHEN "000000" => p0_uid93_constMult_q <= "0000000000000000000000000000000000"; WHEN "000001" => p0_uid93_constMult_q <= "0000001011000101110010000110000000"; WHEN "000010" => p0_uid93_constMult_q <= "0000010110001011100100001100000000"; WHEN "000011" => p0_uid93_constMult_q <= "0000100001010001010110010010000000"; WHEN "000100" => p0_uid93_constMult_q <= "0000101100010111001000011000000000"; WHEN "000101" => p0_uid93_constMult_q <= "0000110111011100111010011110000000"; WHEN "000110" => p0_uid93_constMult_q <= "0001000010100010101100100100000000"; WHEN "000111" => p0_uid93_constMult_q <= "0001001101101000011110101010000000"; WHEN "001000" => p0_uid93_constMult_q <= "0001011000101110010000110000000000"; WHEN "001001" => p0_uid93_constMult_q <= "0001100011110100000010110110000000"; WHEN "001010" => p0_uid93_constMult_q <= "0001101110111001110100111100000000"; WHEN "001011" => p0_uid93_constMult_q <= "0001111001111111100111000010000000"; WHEN "001100" => p0_uid93_constMult_q <= "0010000101000101011001001000000000"; WHEN "001101" => p0_uid93_constMult_q <= "0010010000001011001011001110000000"; WHEN "001110" => p0_uid93_constMult_q <= "0010011011010000111101010100000000"; WHEN "001111" => p0_uid93_constMult_q <= "0010100110010110101111011010000000"; WHEN "010000" => p0_uid93_constMult_q <= "0010110001011100100001100000000000"; WHEN "010001" => p0_uid93_constMult_q <= "0010111100100010010011100110000000"; WHEN "010010" => p0_uid93_constMult_q <= "0011000111101000000101101100000000"; WHEN "010011" => p0_uid93_constMult_q <= "0011010010101101110111110010000000"; WHEN "010100" => p0_uid93_constMult_q <= "0011011101110011101001111000000000"; WHEN "010101" => p0_uid93_constMult_q <= "0011101000111001011011111110000000"; WHEN "010110" => p0_uid93_constMult_q <= "0011110011111111001110000100000000"; WHEN "010111" => p0_uid93_constMult_q <= "0011111111000101000000001010000000"; WHEN "011000" => p0_uid93_constMult_q <= "0100001010001010110010010000000000"; WHEN "011001" => p0_uid93_constMult_q <= "0100010101010000100100010110000000"; WHEN "011010" => p0_uid93_constMult_q <= "0100100000010110010110011100000000"; WHEN "011011" => p0_uid93_constMult_q <= "0100101011011100001000100010000000"; WHEN "011100" => p0_uid93_constMult_q <= "0100110110100001111010101000000000"; WHEN "011101" => p0_uid93_constMult_q <= "0101000001100111101100101110000000"; WHEN "011110" => p0_uid93_constMult_q <= "0101001100101101011110110100000000"; WHEN "011111" => p0_uid93_constMult_q <= "0101010111110011010000111010000000"; WHEN "100000" => p0_uid93_constMult_q <= "0101100010111001000011000000000000"; WHEN "100001" => p0_uid93_constMult_q <= "0101101101111110110101000110000000"; WHEN "100010" => p0_uid93_constMult_q <= "0101111001000100100111001100000000"; WHEN "100011" => p0_uid93_constMult_q <= "0110000100001010011001010010000000"; WHEN "100100" => p0_uid93_constMult_q <= "0110001111010000001011011000000000"; WHEN "100101" => p0_uid93_constMult_q <= "0110011010010101111101011110000000"; WHEN "100110" => p0_uid93_constMult_q <= "0110100101011011101111100100000000"; WHEN "100111" => p0_uid93_constMult_q <= "0110110000100001100001101010000000"; WHEN "101000" => p0_uid93_constMult_q <= "0110111011100111010011110000000000"; WHEN "101001" => p0_uid93_constMult_q <= "0111000110101101000101110110000000"; WHEN "101010" => p0_uid93_constMult_q <= "0111010001110010110111111100000000"; WHEN "101011" => p0_uid93_constMult_q <= "0111011100111000101010000010000000"; WHEN "101100" => p0_uid93_constMult_q <= "0111100111111110011100001000000000"; WHEN "101101" => p0_uid93_constMult_q <= "0111110011000100001110001110000000"; WHEN "101110" => p0_uid93_constMult_q <= "0111111110001010000000010100000000"; WHEN "101111" => p0_uid93_constMult_q <= "1000001001001111110010011010000000"; WHEN "110000" => p0_uid93_constMult_q <= "1000010100010101100100100000000000"; WHEN "110001" => p0_uid93_constMult_q <= "1000011111011011010110100110000000"; WHEN "110010" => p0_uid93_constMult_q <= "1000101010100001001000101100000000"; WHEN "110011" => p0_uid93_constMult_q <= "1000110101100110111010110010000000"; WHEN "110100" => p0_uid93_constMult_q <= "1001000000101100101100111000000000"; WHEN "110101" => p0_uid93_constMult_q <= "1001001011110010011110111110000000"; WHEN "110110" => p0_uid93_constMult_q <= "1001010110111000010001000100000000"; WHEN "110111" => p0_uid93_constMult_q <= "1001100001111110000011001010000000"; WHEN "111000" => p0_uid93_constMult_q <= "1001101101000011110101010000000000"; WHEN "111001" => p0_uid93_constMult_q <= "1001111000001001100111010110000000"; WHEN "111010" => p0_uid93_constMult_q <= "1010000011001111011001011100000000"; WHEN "111011" => p0_uid93_constMult_q <= "1010001110010101001011100010000000"; WHEN "111100" => p0_uid93_constMult_q <= "1010011001011010111101101000000000"; WHEN "111101" => p0_uid93_constMult_q <= "1010100100100000101111101110000000"; WHEN "111110" => p0_uid93_constMult_q <= "1010101111100110100001110100000000"; WHEN "111111" => p0_uid93_constMult_q <= "1010111010101100010011111010000000"; WHEN OTHERS => p0_uid93_constMult_q <= "0000000000000000000000000000000000"; END CASE; END IF; END PROCESS; --xv1_uid91_constMult(BITSELECT,90)@13 xv1_uid91_constMult_in <= e_uid29_fpLogETest_q; xv1_uid91_constMult_b <= xv1_uid91_constMult_in(8 downto 6); --p1_uid92_constMult(LOOKUP,91)@13 p1_uid92_constMult: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN p1_uid92_constMult_q <= "0000000000000000000000000000000000000"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (xv1_uid91_constMult_b) IS WHEN "000" => p1_uid92_constMult_q <= "0000000000000000000000000000000000000"; WHEN "001" => p1_uid92_constMult_q <= "0001011000101110010000110000000000000"; WHEN "010" => p1_uid92_constMult_q <= "0010110001011100100001100000000000000"; WHEN "011" => p1_uid92_constMult_q <= "0100001010001010110010010000000000000"; WHEN "100" => p1_uid92_constMult_q <= "1010011101000110111101000000000000000"; WHEN "101" => p1_uid92_constMult_q <= "1011110101110101001101110000000000000"; WHEN "110" => p1_uid92_constMult_q <= "1101001110100011011110100000000000000"; WHEN "111" => p1_uid92_constMult_q <= "1110100111010001101111010000000000000"; WHEN OTHERS => p1_uid92_constMult_q <= "0000000000000000000000000000000000000"; END CASE; END IF; END PROCESS; --lev1_a0_uid94_constMult(ADD,93)@14 lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((38 downto 37 => p1_uid92_constMult_q(36)) & p1_uid92_constMult_q); lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000" & p0_uid93_constMult_q); lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b)); lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(37 downto 0); --sR_uid95_constMult(BITSELECT,94)@14 sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(36 downto 0); sR_uid95_constMult_b <= sR_uid95_constMult_in(36 downto 2); --ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b(DELAY,254)@0 ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b : dspba_delay GENERIC MAP ( width => 1, depth => 14 ) PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --addTermOne_uid45_fpLogETest(MUX,44)@14 addTermOne_uid45_fpLogETest_s <= ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q; addTermOne_uid45_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN addTermOne_uid45_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE addTermOne_uid45_fpLogETest_s IS WHEN "0" => addTermOne_uid45_fpLogETest_q <= sR_uid95_constMult_b; WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q; WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --sumAHighB_uid48_fpLogETest(ADD,47)@15 sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((35 downto 35 => addTermOne_uid45_fpLogETest_q(34)) & addTermOne_uid45_fpLogETest_q); sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((35 downto 30 => highBBits_uid47_fpLogETest_b(29)) & highBBits_uid47_fpLogETest_b); sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b)); sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(35 downto 0); --lowRangeB_uid46_fpLogETest(BITSELECT,45)@15 lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_q(20 downto 0); lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(20 downto 0); --finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@15 finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & lowRangeB_uid46_fpLogETest_b; --FullSumAB56_uid50_fpLogETest(BITSELECT,49)@15 FullSumAB56_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q; FullSumAB56_uid50_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_in(56 downto 56); --notC_uid71_fpLogETest(LOGICAL,70)@15 notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q; notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a; --signTerm2_uid72_fpLogETest(LOGICAL,71)@15 signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q; signTerm2_uid72_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_b; signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b; --ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a(DELAY,285)@0 ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRC1_uid73_fpLogETest(LOGICAL,72)@15 signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q; signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q; signRC1_uid73_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRC1_uid73_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN signRC1_uid73_fpLogETest_q <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b; END IF; END PROCESS; --cstAllZWF_uid8_fpLogETest(CONSTANT,7) cstAllZWF_uid8_fpLogETest_q <= "00000000000000000000000"; --fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0 fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b; fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q; fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0"; --InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0 InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q; InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a; --cstAllOWE_uid12_fpLogETest(CONSTANT,11) cstAllOWE_uid12_fpLogETest_q <= "11111111"; --expXIsMax_uid18_fpLogETest(LOGICAL,17)@0 expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b; expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q; expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0"; --exc_N_uid23_fpLogETest(LOGICAL,22)@0 exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q; exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q; exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b; --InvExc_N_uid24_fpLogETest(LOGICAL,23)@0 InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q; InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a; --exc_I_uid21_fpLogETest(LOGICAL,20)@0 exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q; exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q; exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b; --InvExc_I_uid25_fpLogETest(LOGICAL,24)@0 InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q; InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a; --cstAllZWE_uid14_fpLogETest(CONSTANT,13) cstAllZWE_uid14_fpLogETest_q <= "00000000"; --expXIsZero_uid16_fpLogETest(LOGICAL,15)@0 expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b; expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q; expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0"; --InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0 InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q; InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a; --exc_R_uid27_fpLogETest(LOGICAL,26)@0 exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q; exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q; exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q; exc_R_uid27_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN exc_R_uid27_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN exc_R_uid27_fpLogETest_q <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c; END IF; END PROCESS; --ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a(DELAY,290)@1 ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRC11_uid74_fpLogETest(LOGICAL,73)@16 signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q; signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q; signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b; --reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,220)@0 reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q; END IF; END IF; END PROCESS; --ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a(DELAY,292)@1 ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --signR_uid75_fpLogETest(LOGICAL,74)@16 signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q; signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q; signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b; --signX_uid7_fpLogETest(BITSELECT,6)@0 signX_uid7_fpLogETest_in <= a; signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(31 downto 31); --negNonZero_uid69_fpLogETest(LOGICAL,68)@0 negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q; negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b; negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b; --excRNaN_uid70_fpLogETest(LOGICAL,69)@0 excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q; excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q; excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b; --ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a(DELAY,294)@0 ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@15 InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q; InvExcRNaN_uid76_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid76_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExcRNaN_uid76_fpLogETest_q <= not InvExcRNaN_uid76_fpLogETest_a; END IF; END PROCESS; --signRFull_uid77_fpLogETest(LOGICAL,76)@16 signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q; signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q; signRFull_uid77_fpLogETest_q <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b; --ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,307)@16 ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset ); --zs_uid113_countZ_uid54_fpLogETest(CONSTANT,112) zs_uid113_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000"; --ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,266)@15 ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => FullSumAB56_uid50_fpLogETest_b, xout => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@15 finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q; finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((56 downto 1 => FullSumAB56_uid50_fpLogETest_b(0)) & FullSumAB56_uid50_fpLogETest_b); finalSumOneComp_uid52_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN finalSumOneComp_uid52_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN finalSumOneComp_uid52_fpLogETest_q <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b; END IF; END PROCESS; --finalSumAbs_uid53_fpLogETest(ADD,52)@16 finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((57 downto 57 => finalSumOneComp_uid52_fpLogETest_q(56)) & finalSumOneComp_uid52_fpLogETest_q); finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((57 downto 1 => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q); finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b)); finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(57 downto 0); --rVStage_uid114_countZ_uid54_fpLogETest(BITSELECT,113)@16 rVStage_uid114_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q; rVStage_uid114_countZ_uid54_fpLogETest_b <= rVStage_uid114_countZ_uid54_fpLogETest_in(57 downto 26); --reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1(REG,202)@16 reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= rVStage_uid114_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vCount_uid115_countZ_uid54_fpLogETest(LOGICAL,114)@17 vCount_uid115_countZ_uid54_fpLogETest_a <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q; vCount_uid115_countZ_uid54_fpLogETest_b <= zs_uid113_countZ_uid54_fpLogETest_q; vCount_uid115_countZ_uid54_fpLogETest_q <= "1" when vCount_uid115_countZ_uid54_fpLogETest_a = vCount_uid115_countZ_uid54_fpLogETest_b else "0"; --ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f(DELAY,366)@17 ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid115_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q, ena => en(0), clk => clk, aclr => areset ); --zs_uid121_countZ_uid54_fpLogETest(CONSTANT,120) zs_uid121_countZ_uid54_fpLogETest_q <= "0000000000000000"; --vStage_uid117_countZ_uid54_fpLogETest(BITSELECT,116)@16 vStage_uid117_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(25 downto 0); vStage_uid117_countZ_uid54_fpLogETest_b <= vStage_uid117_countZ_uid54_fpLogETest_in(25 downto 0); --mO_uid116_countZ_uid54_fpLogETest(CONSTANT,115) mO_uid116_countZ_uid54_fpLogETest_q <= "111111"; --cStage_uid118_countZ_uid54_fpLogETest(BITJOIN,117)@16 cStage_uid118_countZ_uid54_fpLogETest_q <= vStage_uid117_countZ_uid54_fpLogETest_b & mO_uid116_countZ_uid54_fpLogETest_q; --reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3(REG,204)@16 reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= cStage_uid118_countZ_uid54_fpLogETest_q; END IF; END IF; END PROCESS; --vStagei_uid120_countZ_uid54_fpLogETest(MUX,119)@17 vStagei_uid120_countZ_uid54_fpLogETest_s <= vCount_uid115_countZ_uid54_fpLogETest_q; vStagei_uid120_countZ_uid54_fpLogETest: PROCESS (vStagei_uid120_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q, reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q) BEGIN CASE vStagei_uid120_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q; WHEN "1" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q; WHEN OTHERS => vStagei_uid120_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid122_countZ_uid54_fpLogETest(BITSELECT,121)@17 rVStage_uid122_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q; rVStage_uid122_countZ_uid54_fpLogETest_b <= rVStage_uid122_countZ_uid54_fpLogETest_in(31 downto 16); --reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1(REG,205)@17 reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= rVStage_uid122_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vCount_uid123_countZ_uid54_fpLogETest(LOGICAL,122)@18 vCount_uid123_countZ_uid54_fpLogETest_a <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q; vCount_uid123_countZ_uid54_fpLogETest_b <= zs_uid121_countZ_uid54_fpLogETest_q; vCount_uid123_countZ_uid54_fpLogETest_q <= "1" when vCount_uid123_countZ_uid54_fpLogETest_a = vCount_uid123_countZ_uid54_fpLogETest_b else "0"; --ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e(DELAY,365)@18 ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid123_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid124_countZ_uid54_fpLogETest(BITSELECT,123)@17 vStage_uid124_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q(15 downto 0); vStage_uid124_countZ_uid54_fpLogETest_b <= vStage_uid124_countZ_uid54_fpLogETest_in(15 downto 0); --reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3(REG,207)@17 reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= vStage_uid124_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vStagei_uid126_countZ_uid54_fpLogETest(MUX,125)@18 vStagei_uid126_countZ_uid54_fpLogETest_s <= vCount_uid123_countZ_uid54_fpLogETest_q; vStagei_uid126_countZ_uid54_fpLogETest: PROCESS (vStagei_uid126_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q, reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q) BEGIN CASE vStagei_uid126_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q; WHEN "1" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q; WHEN OTHERS => vStagei_uid126_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid128_countZ_uid54_fpLogETest(BITSELECT,127)@18 rVStage_uid128_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q; rVStage_uid128_countZ_uid54_fpLogETest_b <= rVStage_uid128_countZ_uid54_fpLogETest_in(15 downto 8); --vCount_uid129_countZ_uid54_fpLogETest(LOGICAL,128)@18 vCount_uid129_countZ_uid54_fpLogETest_a <= rVStage_uid128_countZ_uid54_fpLogETest_b; vCount_uid129_countZ_uid54_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q; vCount_uid129_countZ_uid54_fpLogETest_q <= "1" when vCount_uid129_countZ_uid54_fpLogETest_a = vCount_uid129_countZ_uid54_fpLogETest_b else "0"; --reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3(REG,211)@18 reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= vCount_uid129_countZ_uid54_fpLogETest_q; END IF; END IF; END PROCESS; --zs_uid133_countZ_uid54_fpLogETest(CONSTANT,132) zs_uid133_countZ_uid54_fpLogETest_q <= "0000"; --vStage_uid130_countZ_uid54_fpLogETest(BITSELECT,129)@18 vStage_uid130_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q(7 downto 0); vStage_uid130_countZ_uid54_fpLogETest_b <= vStage_uid130_countZ_uid54_fpLogETest_in(7 downto 0); --vStagei_uid132_countZ_uid54_fpLogETest(MUX,131)@18 vStagei_uid132_countZ_uid54_fpLogETest_s <= vCount_uid129_countZ_uid54_fpLogETest_q; vStagei_uid132_countZ_uid54_fpLogETest: PROCESS (vStagei_uid132_countZ_uid54_fpLogETest_s, en, rVStage_uid128_countZ_uid54_fpLogETest_b, vStage_uid130_countZ_uid54_fpLogETest_b) BEGIN CASE vStagei_uid132_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid132_countZ_uid54_fpLogETest_q <= rVStage_uid128_countZ_uid54_fpLogETest_b; WHEN "1" => vStagei_uid132_countZ_uid54_fpLogETest_q <= vStage_uid130_countZ_uid54_fpLogETest_b; WHEN OTHERS => vStagei_uid132_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid134_countZ_uid54_fpLogETest(BITSELECT,133)@18 rVStage_uid134_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q; rVStage_uid134_countZ_uid54_fpLogETest_b <= rVStage_uid134_countZ_uid54_fpLogETest_in(7 downto 4); --reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1(REG,208)@18 reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= rVStage_uid134_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vCount_uid135_countZ_uid54_fpLogETest(LOGICAL,134)@19 vCount_uid135_countZ_uid54_fpLogETest_a <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q; vCount_uid135_countZ_uid54_fpLogETest_b <= zs_uid133_countZ_uid54_fpLogETest_q; vCount_uid135_countZ_uid54_fpLogETest_q <= "1" when vCount_uid135_countZ_uid54_fpLogETest_a = vCount_uid135_countZ_uid54_fpLogETest_b else "0"; --vStage_uid136_countZ_uid54_fpLogETest(BITSELECT,135)@18 vStage_uid136_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q(3 downto 0); vStage_uid136_countZ_uid54_fpLogETest_b <= vStage_uid136_countZ_uid54_fpLogETest_in(3 downto 0); --reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3(REG,210)@18 reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= vStage_uid136_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vStagei_uid138_countZ_uid54_fpLogETest(MUX,137)@19 vStagei_uid138_countZ_uid54_fpLogETest_s <= vCount_uid135_countZ_uid54_fpLogETest_q; vStagei_uid138_countZ_uid54_fpLogETest: PROCESS (vStagei_uid138_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q, reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q) BEGIN CASE vStagei_uid138_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q; WHEN "1" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q; WHEN OTHERS => vStagei_uid138_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid140_countZ_uid54_fpLogETest(BITSELECT,139)@19 rVStage_uid140_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q; rVStage_uid140_countZ_uid54_fpLogETest_b <= rVStage_uid140_countZ_uid54_fpLogETest_in(3 downto 2); --vCount_uid141_countZ_uid54_fpLogETest(LOGICAL,140)@19 vCount_uid141_countZ_uid54_fpLogETest_a <= rVStage_uid140_countZ_uid54_fpLogETest_b; vCount_uid141_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q; vCount_uid141_countZ_uid54_fpLogETest_q <= "1" when vCount_uid141_countZ_uid54_fpLogETest_a = vCount_uid141_countZ_uid54_fpLogETest_b else "0"; --vStage_uid142_countZ_uid54_fpLogETest(BITSELECT,141)@19 vStage_uid142_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q(1 downto 0); vStage_uid142_countZ_uid54_fpLogETest_b <= vStage_uid142_countZ_uid54_fpLogETest_in(1 downto 0); --vStagei_uid144_countZ_uid54_fpLogETest(MUX,143)@19 vStagei_uid144_countZ_uid54_fpLogETest_s <= vCount_uid141_countZ_uid54_fpLogETest_q; vStagei_uid144_countZ_uid54_fpLogETest: PROCESS (vStagei_uid144_countZ_uid54_fpLogETest_s, en, rVStage_uid140_countZ_uid54_fpLogETest_b, vStage_uid142_countZ_uid54_fpLogETest_b) BEGIN CASE vStagei_uid144_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid144_countZ_uid54_fpLogETest_q <= rVStage_uid140_countZ_uid54_fpLogETest_b; WHEN "1" => vStagei_uid144_countZ_uid54_fpLogETest_q <= vStage_uid142_countZ_uid54_fpLogETest_b; WHEN OTHERS => vStagei_uid144_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid146_countZ_uid54_fpLogETest(BITSELECT,145)@19 rVStage_uid146_countZ_uid54_fpLogETest_in <= vStagei_uid144_countZ_uid54_fpLogETest_q; rVStage_uid146_countZ_uid54_fpLogETest_b <= rVStage_uid146_countZ_uid54_fpLogETest_in(1 downto 1); --vCount_uid147_countZ_uid54_fpLogETest(LOGICAL,146)@19 vCount_uid147_countZ_uid54_fpLogETest_a <= rVStage_uid146_countZ_uid54_fpLogETest_b; vCount_uid147_countZ_uid54_fpLogETest_b <= GND_q; vCount_uid147_countZ_uid54_fpLogETest_q <= "1" when vCount_uid147_countZ_uid54_fpLogETest_a = vCount_uid147_countZ_uid54_fpLogETest_b else "0"; --r_uid148_countZ_uid54_fpLogETest(BITJOIN,147)@19 r_uid148_countZ_uid54_fpLogETest_q <= ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q & ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q & reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q & vCount_uid135_countZ_uid54_fpLogETest_q & vCount_uid141_countZ_uid54_fpLogETest_q & vCount_uid147_countZ_uid54_fpLogETest_q; --reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1(REG,218)@19 reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= r_uid148_countZ_uid54_fpLogETest_q; END IF; END IF; END PROCESS; --cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55) cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010001001"; --expRExt_uid57_fpLogETest(SUB,56)@20 expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q); expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("0000" & reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q); expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b)); expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(9 downto 0); --LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest(BITSELECT,179)@20 LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(54 downto 0); LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in(54 downto 0); --leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest(CONSTANT,178) leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q <= "000"; --leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest(BITJOIN,180)@20 leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b & leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q; --LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest(BITSELECT,176)@20 LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(55 downto 0); LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in(55 downto 0); --leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest(BITJOIN,177)@20 leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b & z2_uid40_fpLogETest_q; --LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest(BITSELECT,173)@20 LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(56 downto 0); LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in(56 downto 0); --leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest(BITJOIN,174)@20 leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b & GND_q; --X9dto0_uid158_normVal_uid55_fpLogETest(BITSELECT,157)@16 X9dto0_uid158_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(9 downto 0); X9dto0_uid158_normVal_uid55_fpLogETest_b <= X9dto0_uid158_normVal_uid55_fpLogETest_in(9 downto 0); --ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg(DELAY,467) ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg : dspba_delay GENERIC MAP ( width => 10, depth => 1 ) PORT MAP ( xin => X9dto0_uid158_normVal_uid55_fpLogETest_b, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b(DELAY,371)@16 ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b : dspba_delay GENERIC MAP ( width => 10, depth => 2 ) PORT MAP ( xin => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest(CONSTANT,156) leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest(BITJOIN,158)@19 leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q <= ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q & leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q; --ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg(DELAY,466) ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => vStage_uid117_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b(DELAY,369)@16 ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b : dspba_delay GENERIC MAP ( width => 26, depth => 2 ) PORT MAP ( xin => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest(BITJOIN,155)@19 leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q <= ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q & zs_uid113_countZ_uid54_fpLogETest_q; --X41dto0_uid152_normVal_uid55_fpLogETest(BITSELECT,151)@16 X41dto0_uid152_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(41 downto 0); X41dto0_uid152_normVal_uid55_fpLogETest_b <= X41dto0_uid152_normVal_uid55_fpLogETest_in(41 downto 0); --ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg(DELAY,465) ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg : dspba_delay GENERIC MAP ( width => 42, depth => 1 ) PORT MAP ( xin => X41dto0_uid152_normVal_uid55_fpLogETest_b, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b(DELAY,368)@16 ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b : dspba_delay GENERIC MAP ( width => 42, depth => 2 ) PORT MAP ( xin => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest(BITJOIN,152)@19 leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q <= ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q & zs_uid121_countZ_uid54_fpLogETest_q; --ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg(DELAY,468) ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg : dspba_delay GENERIC MAP ( width => 58, depth => 1 ) PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c(DELAY,374)@16 ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c : dspba_delay GENERIC MAP ( width => 58, depth => 2 ) PORT MAP ( xin => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest(BITSELECT,159)@19 leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q; leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in(5 downto 4); --leftShiftStage0_uid161_normVal_uid55_fpLogETest(MUX,160)@19 leftShiftStage0_uid161_normVal_uid55_fpLogETest_s <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b; leftShiftStage0_uid161_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid161_normVal_uid55_fpLogETest_s, en, ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q, leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q, leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q) BEGIN CASE leftShiftStage0_uid161_normVal_uid55_fpLogETest_s IS WHEN "00" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q; WHEN "01" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q; WHEN "10" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q; WHEN "11" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q; WHEN OTHERS => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest(BITSELECT,168)@19 LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(45 downto 0); LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in(45 downto 0); --leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest(CONSTANT,167) leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q <= "000000000000"; --leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest(BITJOIN,169)@19 leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q; --reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5(REG,216)@19 reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest(BITSELECT,165)@19 LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(49 downto 0); LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in(49 downto 0); --leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest(BITJOIN,166)@19 leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b & cstAllZWE_uid14_fpLogETest_q; --reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4(REG,215)@19 reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest(BITSELECT,162)@19 LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(53 downto 0); LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in(53 downto 0); --leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest(BITJOIN,163)@19 leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b & zs_uid133_countZ_uid54_fpLogETest_q; --reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3(REG,214)@19 reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2(REG,213)@19 reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest(BITSELECT,170)@19 leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(3 downto 0); leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in(3 downto 2); --reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1(REG,212)@19 reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b; END IF; END IF; END PROCESS; --leftShiftStage1_uid172_normVal_uid55_fpLogETest(MUX,171)@20 leftShiftStage1_uid172_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q; leftShiftStage1_uid172_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid172_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q) BEGIN CASE leftShiftStage1_uid172_normVal_uid55_fpLogETest_s IS WHEN "00" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q; WHEN "01" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q; WHEN "10" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q; WHEN "11" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q; WHEN OTHERS => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest(BITSELECT,181)@19 leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(1 downto 0); leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in(1 downto 0); --reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1(REG,217)@19 reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b; END IF; END IF; END PROCESS; --leftShiftStage2_uid183_normVal_uid55_fpLogETest(MUX,182)@20 leftShiftStage2_uid183_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q; leftShiftStage2_uid183_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid183_normVal_uid55_fpLogETest_s, en, leftShiftStage1_uid172_normVal_uid55_fpLogETest_q, leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q) BEGIN CASE leftShiftStage2_uid183_normVal_uid55_fpLogETest_s IS WHEN "00" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q; WHEN "01" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q; WHEN "10" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q; WHEN "11" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q; WHEN OTHERS => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --fracR_uid58_fpLogETest(BITSELECT,57)@20 fracR_uid58_fpLogETest_in <= leftShiftStage2_uid183_normVal_uid55_fpLogETest_q(56 downto 0); fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(56 downto 33); --expFracConc_uid59_fpLogETest(BITJOIN,58)@20 expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b; --reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,219)@20 reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "0000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q; END IF; END IF; END PROCESS; --expFracPostRnd_uid60_fpLogETest(ADD,59)@21 expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q); expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000" & VCC_q); expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b)); expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(34 downto 0); --expR_uid62_fpLogETest(BITSELECT,61)@21 expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(31 downto 0); expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(31 downto 24); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor(LOGICAL,493) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q <= not (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a or ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top(CONSTANT,489) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q <= "010001"; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp(LOGICAL,490) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q); ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q <= "1" when ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a = ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b else "0"; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg(REG,491) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena(REG,494) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q = "1") THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd(LOGICAL,495) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b <= en; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a and ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b; --InvSignX_uid65_fpLogETest(LOGICAL,64)@0 InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b; InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a; --excRInfC1_uid66_fpLogETest(LOGICAL,65)@0 excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q; excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q; excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b; --excRInf_uid67_fpLogETest(LOGICAL,66)@0 excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q; excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q; excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b; --FPOne_uid63_fpLogETest(BITJOIN,62)@0 FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q; --excRZero_uid64_fpLogETest(LOGICAL,63)@0 excRZero_uid64_fpLogETest_a <= a; excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q; excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0"; --concExc_uid78_fpLogETest(BITJOIN,77)@0 concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg(DELAY,483) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => concExc_uid78_fpLogETest_q, xout => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt(COUNTER,485) -- every=1, low=0, high=17, step=1, init=1 ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i = 16 THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '1'; ELSE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i - 17; ELSE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i,5)); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg(REG,486) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux(MUX,487) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s <= en; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux: PROCESS (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q) BEGIN CASE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s IS WHEN "0" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q; WHEN "1" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q; WHEN OTHERS => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem(DUALMEM,484) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 <= areset; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 5, numwords_a => 18, width_b => 3, widthad_b => 5, numwords_b => 18, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq, address_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa, data_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia ); ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq(2 downto 0); --reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,193)@20 reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q; END IF; END IF; END PROCESS; --excREnc_uid79_fpLogETest(LOOKUP,78)@21 excREnc_uid79_fpLogETest: PROCESS (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q) IS WHEN "000" => excREnc_uid79_fpLogETest_q <= "01"; WHEN "001" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "010" => excREnc_uid79_fpLogETest_q <= "10"; WHEN "011" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "100" => excREnc_uid79_fpLogETest_q <= "11"; WHEN "101" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "110" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "111" => excREnc_uid79_fpLogETest_q <= "00"; WHEN OTHERS => excREnc_uid79_fpLogETest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid87_fpLogETest(MUX,86)@21 expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q; expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, expR_uid62_fpLogETest_b, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q) BEGIN CASE expRPostExc_uid87_fpLogETest_s IS WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q; WHEN "01" => expRPostExc_uid87_fpLogETest_q <= expR_uid62_fpLogETest_b; WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q; WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q; WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79) oneFracRPostExc2_uid80_fpLogETest_q <= "00000000000000000000001"; --fracR_uid61_fpLogETest(BITSELECT,60)@21 fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(23 downto 0); fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(23 downto 1); --fracRPostExc_uid83_fpLogETest(MUX,82)@21 fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q; fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, fracR_uid61_fpLogETest_b, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q) BEGIN CASE fracRPostExc_uid83_fpLogETest_s IS WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q; WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= fracR_uid61_fpLogETest_b; WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q; WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q; WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --RLn_uid88_fpLogETest(BITJOIN,87)@21 RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q; --xOut(GPOUT,4)@21 q <= RLn_uid88_fpLogETest_q; end normal;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/dp_lnlut18.vhd	10	143091	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* DP_LNLUT18.VHD * --* * --* Function: Look Up Table - LN() * --* * --* Generated by MATLAB Utility * --* * --* 18/02/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY dp_lnlut18 IS PORT ( add : IN STD_LOGIC_VECTOR (9 DOWNTO 1); inv : OUT STD_LOGIC_VECTOR (18 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_lnlut18; ARCHITECTURE rtl OF dp_lnlut18 IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "000000000" => inv <= conv_std_logic_vector(131072,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); WHEN "000000001" => inv <= conv_std_logic_vector(262143,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(31,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268391765,28); logexp <= conv_std_logic_vector(1005,11); WHEN "000000010" => inv <= conv_std_logic_vector(262141,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8388752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(327672,28); logexp <= conv_std_logic_vector(1006,11); WHEN "000000011" => inv <= conv_std_logic_vector(262139,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4194504,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(666254,28); logexp <= conv_std_logic_vector(1007,11); WHEN "000000100" => inv <= conv_std_logic_vector(262137,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12583304,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1889508,28); logexp <= conv_std_logic_vector(1007,11); WHEN "000000101" => inv <= conv_std_logic_vector(262135,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2097476,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1982311,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000000110" => inv <= conv_std_logic_vector(262133,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6291940,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3642366,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000000111" => inv <= conv_std_logic_vector(262131,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10486436,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5990414,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000001000" => inv <= conv_std_logic_vector(262129,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14680964,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9223005,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000001001" => inv <= conv_std_logic_vector(262127,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1049154,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6702808,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001010" => inv <= conv_std_logic_vector(262125,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3146450,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9367390,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001011" => inv <= conv_std_logic_vector(262123,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5243762,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12637977,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001100" => inv <= conv_std_logic_vector(262121,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7341090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(16612827,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001101" => inv <= conv_std_logic_vector(262119,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9438434,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21341043,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001110" => inv <= conv_std_logic_vector(262117,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11535794,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26871724,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001111" => inv <= conv_std_logic_vector(262115,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13633170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33303113,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000010000" => inv <= conv_std_logic_vector(262113,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15730562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40684301,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000010001" => inv <= conv_std_logic_vector(262111,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(525377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24532187,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010010" => inv <= conv_std_logic_vector(262109,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1574089,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29270780,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010011" => inv <= conv_std_logic_vector(262107,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2622809,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34582468,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010100" => inv <= conv_std_logic_vector(262105,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3671537,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40499978,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010101" => inv <= conv_std_logic_vector(262103,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4720273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47056037,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010110" => inv <= conv_std_logic_vector(262101,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5769017,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54283367,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010111" => inv <= conv_std_logic_vector(262099,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6817769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62214689,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011000" => inv <= conv_std_logic_vector(262097,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7866529,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70882721,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011001" => inv <= conv_std_logic_vector(262095,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8915297,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80328369,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011010" => inv <= conv_std_logic_vector(262093,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9964073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90567968,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011011" => inv <= conv_std_logic_vector(262091,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11012857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101650610,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011100" => inv <= conv_std_logic_vector(262089,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12061649,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113592623,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011101" => inv <= conv_std_logic_vector(262087,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13110449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126443095,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011110" => inv <= conv_std_logic_vector(262085,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14159257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140226541,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011111" => inv <= conv_std_logic_vector(262083,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15208073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(154975663,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000100000" => inv <= conv_std_logic_vector(262081,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16256897,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170731353,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000100001" => inv <= conv_std_logic_vector(262079,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(264256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227972692,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100010" => inv <= conv_std_logic_vector(262077,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(788676,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236897961,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100011" => inv <= conv_std_logic_vector(262075,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1313100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246371462,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100100" => inv <= conv_std_logic_vector(262073,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1837528,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256409541,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100101" => inv <= conv_std_logic_vector(262071,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2361960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267028543,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100110" => inv <= conv_std_logic_vector(262069,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2886397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9813450,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100111" => inv <= conv_std_logic_vector(262067,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3410837,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21647423,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101000" => inv <= conv_std_logic_vector(262065,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3935281,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34111345,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101001" => inv <= conv_std_logic_vector(262063,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4459729,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47221557,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101010" => inv <= conv_std_logic_vector(262061,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4984181,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60998494,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101011" => inv <= conv_std_logic_vector(262059,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5508637,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75454397,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101100" => inv <= conv_std_logic_vector(262057,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6033097,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90605604,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101101" => inv <= conv_std_logic_vector(262055,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6557561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106472545,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101110" => inv <= conv_std_logic_vector(262053,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7082029,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123067460,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101111" => inv <= conv_std_logic_vector(262051,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7606501,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140410777,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110000" => inv <= conv_std_logic_vector(262049,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8130977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158510638,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110001" => inv <= conv_std_logic_vector(262047,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8655457,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177395659,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110010" => inv <= conv_std_logic_vector(262045,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9179941,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197069887,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110011" => inv <= conv_std_logic_vector(262043,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9704429,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217561932,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110100" => inv <= conv_std_logic_vector(262041,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10228921,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238875840,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110101" => inv <= conv_std_logic_vector(262039,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10753417,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261036127,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110110" => inv <= conv_std_logic_vector(262037,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11277918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15623661,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110111" => inv <= conv_std_logic_vector(262035,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11802422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39521584,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111000" => inv <= conv_std_logic_vector(262033,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12326930,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64314859,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111001" => inv <= conv_std_logic_vector(262031,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12851442,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90015713,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111010" => inv <= conv_std_logic_vector(262029,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13375958,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116644561,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111011" => inv <= conv_std_logic_vector(262027,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13900478,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144213628,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111100" => inv <= conv_std_logic_vector(262025,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14425002,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172743328,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111101" => inv <= conv_std_logic_vector(262023,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14949530,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202249979,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111110" => inv <= conv_std_logic_vector(262021,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15474062,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232745802,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111111" => inv <= conv_std_logic_vector(262019,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15998598,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264251207,28); logexp <= conv_std_logic_vector(1011,11); WHEN "001000000" => inv <= conv_std_logic_vector(262017,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16523139,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28347053,28); logexp <= conv_std_logic_vector(1011,11); WHEN "001000001" => inv <= conv_std_logic_vector(262015,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(135233,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165175963,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000010" => inv <= conv_std_logic_vector(262013,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(397507,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182491979,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000011" => inv <= conv_std_logic_vector(262011,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(659783,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(200343364,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000100" => inv <= conv_std_logic_vector(262009,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(922061,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218740319,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000101" => inv <= conv_std_logic_vector(262007,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1184341,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237688954,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000110" => inv <= conv_std_logic_vector(262005,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1446623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257201513,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000111" => inv <= conv_std_logic_vector(262003,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1708908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(8846602,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001000" => inv <= conv_std_logic_vector(262001,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1971194,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29507379,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001001" => inv <= conv_std_logic_vector(261999,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2233482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50752445,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001010" => inv <= conv_std_logic_vector(261997,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2495772,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72592000,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001011" => inv <= conv_std_logic_vector(261995,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2758064,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95036240,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001100" => inv <= conv_std_logic_vector(261993,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3020358,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118089223,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001101" => inv <= conv_std_logic_vector(261991,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3282654,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141761145,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001110" => inv <= conv_std_logic_vector(261989,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3544952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166062202,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001111" => inv <= conv_std_logic_vector(261987,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3807252,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190996450,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010000" => inv <= conv_std_logic_vector(261985,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4069554,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216576129,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010001" => inv <= conv_std_logic_vector(261983,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4331858,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242805295,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010010" => inv <= conv_std_logic_vector(261981,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4594165,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1260730,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010011" => inv <= conv_std_logic_vector(261979,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4856473,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28821495,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010100" => inv <= conv_std_logic_vector(261977,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5118783,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57056185,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010101" => inv <= conv_std_logic_vector(261975,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5381095,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85977038,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010110" => inv <= conv_std_logic_vector(261973,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5643409,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115590153,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010111" => inv <= conv_std_logic_vector(261971,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5905725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145903675,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011000" => inv <= conv_std_logic_vector(261969,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6168043,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176927792,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011001" => inv <= conv_std_logic_vector(261967,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6430363,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208668602,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011010" => inv <= conv_std_logic_vector(261965,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6692685,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241134248,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011011" => inv <= conv_std_logic_vector(261963,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6955010,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5901507,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011100" => inv <= conv_std_logic_vector(261961,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7217336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39843294,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011101" => inv <= conv_std_logic_vector(261959,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7479664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74536387,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011110" => inv <= conv_std_logic_vector(261957,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7741994,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109988926,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011111" => inv <= conv_std_logic_vector(261955,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8004326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146207004,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100000" => inv <= conv_std_logic_vector(261953,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8266660,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183200806,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100001" => inv <= conv_std_logic_vector(261951,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8528996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220976425,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100010" => inv <= conv_std_logic_vector(261949,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8791334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259546091,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100011" => inv <= conv_std_logic_vector(261947,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9053675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30478393,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100100" => inv <= conv_std_logic_vector(261945,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9316017,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70652380,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100101" => inv <= conv_std_logic_vector(261943,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9578361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111644825,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100110" => inv <= conv_std_logic_vector(261941,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9840707,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153461817,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100111" => inv <= conv_std_logic_vector(261939,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10103055,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196109445,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101000" => inv <= conv_std_logic_vector(261937,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10365405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239597890,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101001" => inv <= conv_std_logic_vector(261935,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10627758,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15499830,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101010" => inv <= conv_std_logic_vector(261933,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10890112,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60696356,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101011" => inv <= conv_std_logic_vector(261931,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11152468,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106756053,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101100" => inv <= conv_std_logic_vector(261929,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11414826,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153689099,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101101" => inv <= conv_std_logic_vector(261927,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11677186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201505673,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101110" => inv <= conv_std_logic_vector(261925,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11939548,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250209813,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101111" => inv <= conv_std_logic_vector(261923,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12201913,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31378287,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110000" => inv <= conv_std_logic_vector(261921,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12464279,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81888089,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110001" => inv <= conv_std_logic_vector(261919,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12726647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133313941,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110010" => inv <= conv_std_logic_vector(261917,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12989017,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185659877,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110011" => inv <= conv_std_logic_vector(261915,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13251389,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238938120,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110100" => inv <= conv_std_logic_vector(261913,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13513764,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24721341,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110101" => inv <= conv_std_logic_vector(261911,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13776140,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79886532,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110110" => inv <= conv_std_logic_vector(261909,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14038518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136006365,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110111" => inv <= conv_std_logic_vector(261907,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14300898,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193091012,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111000" => inv <= conv_std_logic_vector(261905,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14563280,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251146552,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111001" => inv <= conv_std_logic_vector(261903,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14825665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41747701,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111010" => inv <= conv_std_logic_vector(261901,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15088051,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101773495,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111011" => inv <= conv_std_logic_vector(261899,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15350439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162796601,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111100" => inv <= conv_std_logic_vector(261897,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15612829,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224823097,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111101" => inv <= conv_std_logic_vector(261895,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15875222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19427696,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111110" => inv <= conv_std_logic_vector(261893,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16137616,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83489431,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111111" => inv <= conv_std_logic_vector(261891,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16400012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148578923,28); logexp <= conv_std_logic_vector(1012,11); WHEN "010000000" => inv <= conv_std_logic_vector(261889,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16662410,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214708384,28); logexp <= conv_std_logic_vector(1012,11); WHEN "010000001" => inv <= conv_std_logic_vector(261887,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(73797,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140941945,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000010" => inv <= conv_std_logic_vector(261885,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(204998,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175055756,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000011" => inv <= conv_std_logic_vector(261883,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(336200,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209701733,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000100" => inv <= conv_std_logic_vector(261881,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(467403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244882910,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000101" => inv <= conv_std_logic_vector(261879,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(598608,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12167891,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000110" => inv <= conv_std_logic_vector(261877,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(729813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48431647,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000111" => inv <= conv_std_logic_vector(261875,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(861019,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85243804,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001000" => inv <= conv_std_logic_vector(261873,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(992226,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122607396,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001001" => inv <= conv_std_logic_vector(261871,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1123434,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160526482,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001010" => inv <= conv_std_logic_vector(261869,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1254643,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199006142,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001011" => inv <= conv_std_logic_vector(261867,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1385853,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238049411,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001100" => inv <= conv_std_logic_vector(261865,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1517065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9224891,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001101" => inv <= conv_std_logic_vector(261863,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1648277,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49409594,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001110" => inv <= conv_std_logic_vector(261861,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1779490,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90169054,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001111" => inv <= conv_std_logic_vector(261859,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1910704,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131510396,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010000" => inv <= conv_std_logic_vector(261857,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2041919,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173435630,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010001" => inv <= conv_std_logic_vector(261855,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2173135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215949833,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010010" => inv <= conv_std_logic_vector(261853,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2304352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259057063,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010011" => inv <= conv_std_logic_vector(261851,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2435571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34325917,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010100" => inv <= conv_std_logic_vector(261849,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2566790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78630340,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010101" => inv <= conv_std_logic_vector(261847,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2698010,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123540976,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010110" => inv <= conv_std_logic_vector(261845,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2829231,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169060858,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010111" => inv <= conv_std_logic_vector(261843,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2960453,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215194037,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011000" => inv <= conv_std_logic_vector(261841,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3091676,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261943547,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011001" => inv <= conv_std_logic_vector(261839,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3222901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40881052,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011010" => inv <= conv_std_logic_vector(261837,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3354126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88878449,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011011" => inv <= conv_std_logic_vector(261835,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3485352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137506381,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011100" => inv <= conv_std_logic_vector(261833,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3616579,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186767878,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011101" => inv <= conv_std_logic_vector(261831,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3747807,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236666992,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011110" => inv <= conv_std_logic_vector(261829,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3879037,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18774364,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011111" => inv <= conv_std_logic_vector(261827,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4010267,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69961890,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100000" => inv <= conv_std_logic_vector(261825,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4141498,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121800212,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100001" => inv <= conv_std_logic_vector(261823,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4272730,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174293379,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100010" => inv <= conv_std_logic_vector(261821,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4403963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227445444,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100011" => inv <= conv_std_logic_vector(261819,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4535198,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12823978,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100100" => inv <= conv_std_logic_vector(261817,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4666433,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67305989,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100101" => inv <= conv_std_logic_vector(261815,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4797669,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122458025,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100110" => inv <= conv_std_logic_vector(261813,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4928906,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178285160,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100111" => inv <= conv_std_logic_vector(261811,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5060144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234791442,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101000" => inv <= conv_std_logic_vector(261809,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5191384,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(23545465,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101001" => inv <= conv_std_logic_vector(261807,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5322624,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81422190,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101010" => inv <= conv_std_logic_vector(261805,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5453865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139991231,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101011" => inv <= conv_std_logic_vector(261803,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5585107,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199255616,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101100" => inv <= conv_std_logic_vector(261801,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5716350,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259219392,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101101" => inv <= conv_std_logic_vector(261799,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5847595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51452173,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101110" => inv <= conv_std_logic_vector(261797,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5978840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112827896,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101111" => inv <= conv_std_logic_vector(261795,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6110086,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174915153,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110000" => inv <= conv_std_logic_vector(261793,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6241333,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237719013,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110001" => inv <= conv_std_logic_vector(261791,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6372582,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32808067,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110010" => inv <= conv_std_logic_vector(261789,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6503831,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97057274,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110011" => inv <= conv_std_logic_vector(261787,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6635081,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162034200,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110100" => inv <= conv_std_logic_vector(261785,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6766332,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227743914,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110101" => inv <= conv_std_logic_vector(261783,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6897585,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25755007,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110110" => inv <= conv_std_logic_vector(261781,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7028838,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92942434,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110111" => inv <= conv_std_logic_vector(261779,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7160092,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160875808,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111000" => inv <= conv_std_logic_vector(261777,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7291347,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229557128,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111001" => inv <= conv_std_logic_vector(261775,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7422604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30556006,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111010" => inv <= conv_std_logic_vector(261773,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7553861,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100748419,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111011" => inv <= conv_std_logic_vector(261771,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7685119,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171701934,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111100" => inv <= conv_std_logic_vector(261769,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7816378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243420594,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111101" => inv <= conv_std_logic_vector(261767,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7947639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47474008,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111110" => inv <= conv_std_logic_vector(261765,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8078900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120736110,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111111" => inv <= conv_std_logic_vector(261763,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8210162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194776508,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000000" => inv <= conv_std_logic_vector(261761,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8341426,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1163789,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000001" => inv <= conv_std_logic_vector(261759,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8472690,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76771885,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000010" => inv <= conv_std_logic_vector(261757,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8603955,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153170403,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000011" => inv <= conv_std_logic_vector(261755,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8735221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230363387,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000100" => inv <= conv_std_logic_vector(261753,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8866489,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39919420,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000101" => inv <= conv_std_logic_vector(261751,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8997757,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118713456,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000110" => inv <= conv_std_logic_vector(261749,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9129026,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198314080,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000111" => inv <= conv_std_logic_vector(261747,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9260297,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10289876,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001000" => inv <= conv_std_logic_vector(261745,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9391568,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91515797,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001001" => inv <= conv_std_logic_vector(261743,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9522840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173561448,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001010" => inv <= conv_std_logic_vector(261741,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9654113,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256429848,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001011" => inv <= conv_std_logic_vector(261739,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9785388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71690601,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001100" => inv <= conv_std_logic_vector(261737,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9916663,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156217637,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001101" => inv <= conv_std_logic_vector(261735,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10047939,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241580560,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001110" => inv <= conv_std_logic_vector(261733,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10179217,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59346931,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001111" => inv <= conv_std_logic_vector(261731,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10310495,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146392723,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010000" => inv <= conv_std_logic_vector(261729,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10441774,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234286516,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010001" => inv <= conv_std_logic_vector(261727,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10573055,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54596894,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010010" => inv <= conv_std_logic_vector(261725,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10704336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144198805,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010011" => inv <= conv_std_logic_vector(261723,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10835618,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234660830,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010100" => inv <= conv_std_logic_vector(261721,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10966902,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57551551,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010101" => inv <= conv_std_logic_vector(261719,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11098186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149745915,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010110" => inv <= conv_std_logic_vector(261717,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11229471,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242812504,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010111" => inv <= conv_std_logic_vector(261715,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11360758,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68320919,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011000" => inv <= conv_std_logic_vector(261713,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11492045,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163146107,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011001" => inv <= conv_std_logic_vector(261711,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11623333,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258854605,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011010" => inv <= conv_std_logic_vector(261709,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11754623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87018057,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011011" => inv <= conv_std_logic_vector(261707,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11885913,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184509366,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011100" => inv <= conv_std_logic_vector(261705,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12017205,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14462677,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011101" => inv <= conv_std_logic_vector(261703,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12148497,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113752937,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011110" => inv <= conv_std_logic_vector(261701,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12279790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213947700,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011111" => inv <= conv_std_logic_vector(261699,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12411085,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46617589,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100000" => inv <= conv_std_logic_vector(261697,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12542380,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148636528,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100001" => inv <= conv_std_logic_vector(261695,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12673676,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251573093,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100010" => inv <= conv_std_logic_vector(261693,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12804974,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86995861,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100011" => inv <= conv_std_logic_vector(261691,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12936272,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191780799,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100100" => inv <= conv_std_logic_vector(261689,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13067572,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29060005,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100101" => inv <= conv_std_logic_vector(261687,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13198872,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135708424,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100110" => inv <= conv_std_logic_vector(261685,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13330173,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243295652,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100111" => inv <= conv_std_logic_vector(261683,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13461476,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83390266,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101000" => inv <= conv_std_logic_vector(261681,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13592779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192867209,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101001" => inv <= conv_std_logic_vector(261679,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13724084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34858577,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101010" => inv <= conv_std_logic_vector(261677,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13855389,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146240336,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101011" => inv <= conv_std_logic_vector(261675,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13986695,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258581058,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101100" => inv <= conv_std_logic_vector(261673,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14118003,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103450342,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101101" => inv <= conv_std_logic_vector(261671,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14249311,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217721083,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101110" => inv <= conv_std_logic_vector(261669,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14380621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64528444,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101111" => inv <= conv_std_logic_vector(261667,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14511931,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180746345,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110000" => inv <= conv_std_logic_vector(261665,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14643243,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29508923,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110001" => inv <= conv_std_logic_vector(261663,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14774555,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147690097,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110010" => inv <= conv_std_logic_vector(261661,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14905868,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266859463,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110011" => inv <= conv_std_logic_vector(261659,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15037183,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118585591,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110100" => inv <= conv_std_logic_vector(261657,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15168498,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239742400,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110101" => inv <= conv_std_logic_vector(261655,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15299815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93464027,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110110" => inv <= conv_std_logic_vector(261653,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15431132,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216625411,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110111" => inv <= conv_std_logic_vector(261651,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15562451,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72360690,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111000" => inv <= conv_std_logic_vector(261649,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15693770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197542758,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111001" => inv <= conv_std_logic_vector(261647,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15825091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55306773,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111010" => inv <= conv_std_logic_vector(261645,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15956412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182526652,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111011" => inv <= conv_std_logic_vector(261643,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16087735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42335507,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111100" => inv <= conv_std_logic_vector(261641,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16219058,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171609300,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111101" => inv <= conv_std_logic_vector(261639,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16350383,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33481142,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111110" => inv <= conv_std_logic_vector(261637,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16481708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164824949,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111111" => inv <= conv_std_logic_vector(261635,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16613035,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28774856,28); logexp <= conv_std_logic_vector(1013,11); WHEN "100000000" => inv <= conv_std_logic_vector(261633,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16744362,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162205798,28); logexp <= conv_std_logic_vector(1013,11); WHEN "100000001" => inv <= conv_std_logic_vector(261632,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97880094,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000010" => inv <= conv_std_logic_vector(261630,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(82069,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232492642,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000011" => inv <= conv_std_logic_vector(261628,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(147734,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233414771,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000100" => inv <= conv_std_logic_vector(261626,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(213400,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100649515,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000101" => inv <= conv_std_logic_vector(261624,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(279066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102634341,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000110" => inv <= conv_std_logic_vector(261622,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(344732,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239370238,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000111" => inv <= conv_std_logic_vector(261620,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(410399,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242424784,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001000" => inv <= conv_std_logic_vector(261618,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(476067,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111799989,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001001" => inv <= conv_std_logic_vector(261616,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(541735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115933322,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001010" => inv <= conv_std_logic_vector(261614,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(607403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254826281,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001011" => inv <= conv_std_logic_vector(261612,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(673072,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260045933,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001100" => inv <= conv_std_logic_vector(261610,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(738742,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131594288,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001101" => inv <= conv_std_logic_vector(261608,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(804412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137909323,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001110" => inv <= conv_std_logic_vector(261606,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(870083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10556570,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001111" => inv <= conv_std_logic_vector(261604,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(935754,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17974519,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010000" => inv <= conv_std_logic_vector(261602,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1001425,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160164667,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010001" => inv <= conv_std_logic_vector(261600,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1067097,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168694080,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010010" => inv <= conv_std_logic_vector(261598,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1132770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43564256,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010011" => inv <= conv_std_logic_vector(261596,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1198443,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53213172,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010100" => inv <= conv_std_logic_vector(261594,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1264116,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197642837,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010101" => inv <= conv_std_logic_vector(261592,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1329790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208419294,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010110" => inv <= conv_std_logic_vector(261590,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1395465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85545574,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010111" => inv <= conv_std_logic_vector(261588,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1461140,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97458630,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011000" => inv <= conv_std_logic_vector(261586,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1526815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244160472,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011001" => inv <= conv_std_logic_vector(261584,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1592491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257217653,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011010" => inv <= conv_std_logic_vector(261582,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1658168,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136632180,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011011" => inv <= conv_std_logic_vector(261580,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1723845,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150842541,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011100" => inv <= conv_std_logic_vector(261578,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1789523,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31413754,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011101" => inv <= conv_std_logic_vector(261576,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1855201,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46784817,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011110" => inv <= conv_std_logic_vector(261574,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1920879,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196956715,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011111" => inv <= conv_std_logic_vector(261572,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1986558,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213496513,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100000" => inv <= conv_std_logic_vector(261570,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2052238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96406727,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100001" => inv <= conv_std_logic_vector(261568,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2117918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114123801,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100010" => inv <= conv_std_logic_vector(261566,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2183598,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266650763,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100011" => inv <= conv_std_logic_vector(261564,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2249280,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17118198,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100100" => inv <= conv_std_logic_vector(261562,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2314961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170834480,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100101" => inv <= conv_std_logic_vector(261560,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2380643,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190931217,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100110" => inv <= conv_std_logic_vector(261558,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2446326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77410414,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100111" => inv <= conv_std_logic_vector(261556,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2512009,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98709023,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101000" => inv <= conv_std_logic_vector(261554,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2577692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254830073,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101001" => inv <= conv_std_logic_vector(261552,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2643377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(8903637,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101010" => inv <= conv_std_logic_vector(261550,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2709061,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166239111,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101011" => inv <= conv_std_logic_vector(261548,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2774746,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189966567,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101100" => inv <= conv_std_logic_vector(261546,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2840432,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80089032,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101101" => inv <= conv_std_logic_vector(261544,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2906118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105043970,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101110" => inv <= conv_std_logic_vector(261542,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2971804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264832874,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101111" => inv <= conv_std_logic_vector(261540,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3037492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22586838,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110000" => inv <= conv_std_logic_vector(261538,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3103179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183615258,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110001" => inv <= conv_std_logic_vector(261536,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3168867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211048205,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110010" => inv <= conv_std_logic_vector(261534,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3234556,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104888194,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110011" => inv <= conv_std_logic_vector(261532,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3300245,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133573199,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110100" => inv <= conv_std_logic_vector(261530,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3365935,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28668746,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110101" => inv <= conv_std_logic_vector(261528,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3431625,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(58613318,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110110" => inv <= conv_std_logic_vector(261526,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3497315,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(223408408,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110111" => inv <= conv_std_logic_vector(261524,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3563006,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254621075,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111000" => inv <= conv_std_logic_vector(261522,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3628698,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152253325,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111001" => inv <= conv_std_logic_vector(261520,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3694390,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184742106,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111010" => inv <= conv_std_logic_vector(261518,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3760083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83654478,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111011" => inv <= conv_std_logic_vector(261516,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3825776,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117428410,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111100" => inv <= conv_std_logic_vector(261514,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3891470,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17629430,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111101" => inv <= conv_std_logic_vector(261512,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3957164,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52695507,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111110" => inv <= conv_std_logic_vector(261510,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4022858,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222629156,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111111" => inv <= conv_std_logic_vector(261508,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4088553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258996925,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000000" => inv <= conv_std_logic_vector(261506,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4154249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161800305,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000001" => inv <= conv_std_logic_vector(261504,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4219945,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199477266,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000010" => inv <= conv_std_logic_vector(261502,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4285642,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103593845,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000011" => inv <= conv_std_logic_vector(261500,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4351339,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142588522,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000100" => inv <= conv_std_logic_vector(261498,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4417037,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48026823,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000101" => inv <= conv_std_logic_vector(261496,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4482735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88347226,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000110" => inv <= conv_std_logic_vector(261494,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4548433,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263551224,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000111" => inv <= conv_std_logic_vector(261492,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4614133,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36769906,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001000" => inv <= conv_std_logic_vector(261490,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4679832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213312155,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001001" => inv <= conv_std_logic_vector(261488,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4745532,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256309059,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001010" => inv <= conv_std_logic_vector(261486,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4811233,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165762621,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001011" => inv <= conv_std_logic_vector(261484,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4876934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210109787,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001100" => inv <= conv_std_logic_vector(261482,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4942636,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120917613,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001101" => inv <= conv_std_logic_vector(261480,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5008338,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166624068,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001110" => inv <= conv_std_logic_vector(261478,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5074041,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78795186,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001111" => inv <= conv_std_logic_vector(261476,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5139744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125868425,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010000" => inv <= conv_std_logic_vector(261474,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5205448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39410329,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010001" => inv <= conv_std_logic_vector(261472,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5271152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87859376,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010010" => inv <= conv_std_logic_vector(261470,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5336857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2781090,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010011" => inv <= conv_std_logic_vector(261468,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5402562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52613438,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010100" => inv <= conv_std_logic_vector(261466,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5468267,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237358419,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010101" => inv <= conv_std_logic_vector(261464,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5533974,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20147124,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010110" => inv <= conv_std_logic_vector(261462,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5599680,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206287919,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010111" => inv <= conv_std_logic_vector(261460,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5665387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258912403,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011000" => inv <= conv_std_logic_vector(261458,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5731095,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178022066,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011001" => inv <= conv_std_logic_vector(261456,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5796803,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232054873,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011010" => inv <= conv_std_logic_vector(261454,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5862512,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152577368,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011011" => inv <= conv_std_logic_vector(261452,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5928221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208027007,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011100" => inv <= conv_std_logic_vector(261450,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5993931,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129969822,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011101" => inv <= conv_std_logic_vector(261448,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6059641,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186844290,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011110" => inv <= conv_std_logic_vector(261446,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6125352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110216442,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011111" => inv <= conv_std_logic_vector(261444,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6191063,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168523735,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100000" => inv <= conv_std_logic_vector(261442,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6256775,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93333220,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100001" => inv <= conv_std_logic_vector(261440,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6322487,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153082353,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100010" => inv <= conv_std_logic_vector(261438,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6388200,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79337165,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100011" => inv <= conv_std_logic_vector(261436,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6453913,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140535621,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100100" => inv <= conv_std_logic_vector(261434,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6519627,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68244774,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100101" => inv <= conv_std_logic_vector(261432,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6585341,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130901057,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100110" => inv <= conv_std_logic_vector(261430,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6651056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60072032,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100111" => inv <= conv_std_logic_vector(261428,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6716771,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124194644,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101000" => inv <= conv_std_logic_vector(261426,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6782487,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54835943,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101001" => inv <= conv_std_logic_vector(261424,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6848203,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120433383,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101010" => inv <= conv_std_logic_vector(261422,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6913920,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52552996,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101011" => inv <= conv_std_logic_vector(261421,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6946778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203440839,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101100" => inv <= conv_std_logic_vector(261419,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7012496,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69566203,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101101" => inv <= conv_std_logic_vector(261417,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7078214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70654699,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101110" => inv <= conv_std_logic_vector(261415,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7143932,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206708322,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101111" => inv <= conv_std_logic_vector(261413,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7209651,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209294124,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110000" => inv <= conv_std_logic_vector(261411,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7275371,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78413591,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110001" => inv <= conv_std_logic_vector(261409,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7341091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82505197,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110010" => inv <= conv_std_logic_vector(261407,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7406811,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221569406,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110011" => inv <= conv_std_logic_vector(261405,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7472532,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227174289,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110100" => inv <= conv_std_logic_vector(261403,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7538254,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99321843,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110101" => inv <= conv_std_logic_vector(261401,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7603976,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106448498,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110110" => inv <= conv_std_logic_vector(261399,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7669698,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248557271,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110111" => inv <= conv_std_logic_vector(261397,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7735421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257214192,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111000" => inv <= conv_std_logic_vector(261395,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7801145,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132421765,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111001" => inv <= conv_std_logic_vector(261393,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7866869,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142616931,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111010" => inv <= conv_std_logic_vector(261391,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7932594,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19367251,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111011" => inv <= conv_std_logic_vector(261389,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7998319,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31109665,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111100" => inv <= conv_std_logic_vector(261387,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8064044,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177846168,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111101" => inv <= conv_std_logic_vector(261385,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8129770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191143299,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111110" => inv <= conv_std_logic_vector(261383,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8195497,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71003562,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111111" => inv <= conv_std_logic_vector(261381,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8261224,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85863897,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000000" => inv <= conv_std_logic_vector(261379,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8326951,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235726809,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000001" => inv <= conv_std_logic_vector(261377,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8392679,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252159347,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000010" => inv <= conv_std_logic_vector(261375,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8458408,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135162483,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000011" => inv <= conv_std_logic_vector(261373,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8524137,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153174178,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000100" => inv <= conv_std_logic_vector(261371,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8589867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37761480,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000101" => inv <= conv_std_logic_vector(261369,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8655597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57361328,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000110" => inv <= conv_std_logic_vector(261367,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8721327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211976226,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000111" => inv <= conv_std_logic_vector(261365,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8787058,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233172711,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001000" => inv <= conv_std_logic_vector(261363,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8852790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120952266,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001001" => inv <= conv_std_logic_vector(261361,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8918522,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143753360,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001010" => inv <= conv_std_logic_vector(261359,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8984255,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33142020,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001011" => inv <= conv_std_logic_vector(261357,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9049988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57555694,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001100" => inv <= conv_std_logic_vector(261355,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9115721,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216996886,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001101" => inv <= conv_std_logic_vector(261353,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9181455,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243031622,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001110" => inv <= conv_std_logic_vector(261351,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9247190,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135662403,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001111" => inv <= conv_std_logic_vector(261349,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9312925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163326679,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010000" => inv <= conv_std_logic_vector(261347,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9378661,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57590984,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010001" => inv <= conv_std_logic_vector(261345,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9444397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86893278,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010010" => inv <= conv_std_logic_vector(261343,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9510133,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251234532,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010011" => inv <= conv_std_logic_vector(261341,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9575871,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13747355,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010100" => inv <= conv_std_logic_vector(261339,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9641608,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179738576,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010101" => inv <= conv_std_logic_vector(261337,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9707346,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212340806,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010110" => inv <= conv_std_logic_vector(261335,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9773085,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111555525,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010111" => inv <= conv_std_logic_vector(261333,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9838824,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145820180,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011000" => inv <= conv_std_logic_vector(261331,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9904564,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46701306,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011001" => inv <= conv_std_logic_vector(261329,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9970304,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82636350,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011010" => inv <= conv_std_logic_vector(261327,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10036044,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253627813,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011011" => inv <= conv_std_logic_vector(261325,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10101786,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22806772,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011100" => inv <= conv_std_logic_vector(261323,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10167527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195481587,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011101" => inv <= conv_std_logic_vector(261321,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10233269,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234782825,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011110" => inv <= conv_std_logic_vector(261319,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10299012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140713496,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011111" => inv <= conv_std_logic_vector(261317,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10364755,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181710537,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100000" => inv <= conv_std_logic_vector(261315,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10430499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(89340991,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100001" => inv <= conv_std_logic_vector(261313,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10496243,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132041793,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100010" => inv <= conv_std_logic_vector(261311,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10561988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41379987,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100011" => inv <= conv_std_logic_vector(261309,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10627733,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85793018,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100100" => inv <= conv_std_logic_vector(261307,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10693478,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265282876,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100101" => inv <= conv_std_logic_vector(261305,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10759225,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42980638,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100110" => inv <= conv_std_logic_vector(261303,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10824971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224195170,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100111" => inv <= conv_std_logic_vector(261301,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10890719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3621583,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101000" => inv <= conv_std_logic_vector(261299,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10956466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186568744,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101001" => inv <= conv_std_logic_vector(261297,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11022214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236167729,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101010" => inv <= conv_std_logic_vector(261295,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11087963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152420527,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101011" => inv <= conv_std_logic_vector(261293,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11153712,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203764581,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101100" => inv <= conv_std_logic_vector(261291,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11219462,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121766424,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101101" => inv <= conv_std_logic_vector(261289,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11285212,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174864010,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101110" => inv <= conv_std_logic_vector(261287,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11350963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94623359,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101111" => inv <= conv_std_logic_vector(261285,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11416714,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149482427,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110000" => inv <= conv_std_logic_vector(261283,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11482466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71008255,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110001" => inv <= conv_std_logic_vector(261281,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11548218,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127637265,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110010" => inv <= conv_std_logic_vector(261279,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11613971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50936498,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110011" => inv <= conv_std_logic_vector(261277,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11679724,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109344419,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110100" => inv <= conv_std_logic_vector(261275,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11745478,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34426028,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110101" => inv <= conv_std_logic_vector(261273,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11811232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94620297,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110110" => inv <= conv_std_logic_vector(261271,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11876987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21492737,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110111" => inv <= conv_std_logic_vector(261269,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11942742,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83481301,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111000" => inv <= conv_std_logic_vector(261267,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12008498,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12153029,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111001" => inv <= conv_std_logic_vector(261265,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12074254,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75944853,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111010" => inv <= conv_std_logic_vector(261263,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12140011,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6423814,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111011" => inv <= conv_std_logic_vector(261261,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12205768,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72026842,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111100" => inv <= conv_std_logic_vector(261259,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12271526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4320978,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111101" => inv <= conv_std_logic_vector(261258,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12304405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21141383,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111110" => inv <= conv_std_logic_vector(261256,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12370163,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156129342,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111111" => inv <= conv_std_logic_vector(261254,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12435922,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157813374,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000000" => inv <= conv_std_logic_vector(261252,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12501682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26195972,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000001" => inv <= conv_std_logic_vector(261250,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12567442,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29714068,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000010" => inv <= conv_std_logic_vector(261248,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12633202,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168370156,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000011" => inv <= conv_std_logic_vector(261246,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12698963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173730767,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000100" => inv <= conv_std_logic_vector(261244,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12764725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45797884,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000101" => inv <= conv_std_logic_vector(261242,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12830487,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53009458,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000110" => inv <= conv_std_logic_vector(261240,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12896249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195366963,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000111" => inv <= conv_std_logic_vector(261238,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12962012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204436928,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001000" => inv <= conv_std_logic_vector(261236,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13027776,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80222356,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001001" => inv <= conv_std_logic_vector(261234,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13093540,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91159668,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001010" => inv <= conv_std_logic_vector(261232,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13159304,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237251358,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001011" => inv <= conv_std_logic_vector(261230,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13225069,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250064462,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001100" => inv <= conv_std_logic_vector(261228,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13290835,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129600456,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001101" => inv <= conv_std_logic_vector(261226,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13356601,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144297287,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001110" => inv <= conv_std_logic_vector(261224,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13422368,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25721484,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001111" => inv <= conv_std_logic_vector(261222,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13488135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42309975,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010000" => inv <= conv_std_logic_vector(261220,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13553902,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194065764,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010001" => inv <= conv_std_logic_vector(261218,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13619670,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212554867,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010010" => inv <= conv_std_logic_vector(261216,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13685439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97779777,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010011" => inv <= conv_std_logic_vector(261214,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13751208,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118177423,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010100" => inv <= conv_std_logic_vector(261212,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13816978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5314840,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010101" => inv <= conv_std_logic_vector(261210,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13882748,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27629467,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010110" => inv <= conv_std_logic_vector(261208,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13948518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185123287,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010111" => inv <= conv_std_logic_vector(261206,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14014289,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209363335,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011000" => inv <= conv_std_logic_vector(261204,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14080061,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100351083,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011001" => inv <= conv_std_logic_vector(261202,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14145833,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126524479,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011010" => inv <= conv_std_logic_vector(261200,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14211606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19449539,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011011" => inv <= conv_std_logic_vector(261198,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14277379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47564719,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011100" => inv <= conv_std_logic_vector(261196,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14343152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210871490,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011101" => inv <= conv_std_logic_vector(261194,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14408926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240936379,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011110" => inv <= conv_std_logic_vector(261192,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14474701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137761877,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011111" => inv <= conv_std_logic_vector(261190,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14540476,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169784908,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100000" => inv <= conv_std_logic_vector(261188,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14606252,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68573020,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100001" => inv <= conv_std_logic_vector(261186,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14672028,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102562628,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100010" => inv <= conv_std_logic_vector(261184,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14737805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3321276,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100011" => inv <= conv_std_logic_vector(261182,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14803582,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39285891,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100100" => inv <= conv_std_logic_vector(261180,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14869359,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210458963,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100101" => inv <= conv_std_logic_vector(261178,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14935137,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248407016,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100110" => inv <= conv_std_logic_vector(261176,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15000916,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153132030,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100111" => inv <= conv_std_logic_vector(261174,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15066695,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193071440,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101000" => inv <= conv_std_logic_vector(261172,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15132475,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99791770,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101001" => inv <= conv_std_logic_vector(261170,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15198255,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141730965,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101010" => inv <= conv_std_logic_vector(261168,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15264036,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50455039,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101011" => inv <= conv_std_logic_vector(261166,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15329817,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94401937,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101100" => inv <= conv_std_logic_vector(261164,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15395599,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5138692,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101101" => inv <= conv_std_logic_vector(261162,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15461381,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51101718,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101110" => inv <= conv_std_logic_vector(261160,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15527163,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232294014,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101111" => inv <= conv_std_logic_vector(261158,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15592947,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11846647,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110000" => inv <= conv_std_logic_vector(261156,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15658730,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195067454,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110001" => inv <= conv_std_logic_vector(261154,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15724514,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245088520,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110010" => inv <= conv_std_logic_vector(261152,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15790299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161910803,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110011" => inv <= conv_std_logic_vector(261150,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15856084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213972758,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110100" => inv <= conv_std_logic_vector(261148,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15921870,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132840397,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110101" => inv <= conv_std_logic_vector(261146,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15987656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186951663,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110110" => inv <= conv_std_logic_vector(261144,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16053443,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107873077,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110111" => inv <= conv_std_logic_vector(261142,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16119230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164042073,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111000" => inv <= conv_std_logic_vector(261140,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16185018,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87025173,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111001" => inv <= conv_std_logic_vector(261138,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16250806,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145260319,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111010" => inv <= conv_std_logic_vector(261136,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16316595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70314033,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111011" => inv <= conv_std_logic_vector(261134,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16382384,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130623237,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111100" => inv <= conv_std_logic_vector(261132,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16448174,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57754962,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111101" => inv <= conv_std_logic_vector(261130,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16513964,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120146640,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111110" => inv <= conv_std_logic_vector(261128,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16579755,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49365303,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111111" => inv <= conv_std_logic_vector(261126,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16645546,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113847871,28); logexp <= conv_std_logic_vector(1014,11); WHEN others => inv <= conv_std_logic_vector(0,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_alufp1x.vhd	10	10539	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_ALUFP1X.VHD * --* * --* Function: Single Precision Floating Point * --* Adder * --* * --* 14/07/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --*********************************************** ENTITY hcc_alufp1x IS GENERIC ( mantissa : positive := 36; shiftspeed : integer := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; addsub : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); bbsat, bbzip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_alufp1x; ARCHITECTURE rtl OF hcc_alufp1x IS type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC; signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1); signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1); signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal invertleftff, invertrightff : STD_LOGIC; signal invertleftdelff, invertrightdelff : STD_LOGIC; signal invertleftnode, invertrightnode : STD_LOGIC; signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aluleftdelff : aluleftdelfftype; signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1); signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1); signal switch : STD_LOGIC; signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1); signal expzerochkff : STD_LOGIC; signal expzerochknode : STD_LOGIC; signal expbaseff : expbasefftype; signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_rsftpipe32 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; component hcc_rsftpipe36 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component hcc_rsftcomb32 PORT ( inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; component hcc_rsftcomb36 PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; paa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; bbff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP manleftff(k) <= '0'; manrightff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP expshiftff(k) <= '0'; END LOOP; FOR k IN 1 TO 3+shiftspeed LOOP FOR j IN 1 TO 10 LOOP expbaseff(k)(j) <= '0'; END LOOP; END LOOP; invertleftff <= '0'; invertrightff <= '0'; FOR k IN 1 TO mantissa LOOP manalignff(k) <= '0'; aluff(k) <= '0'; END LOOP; FOR k IN 1 TO 3+shiftspeed LOOP addsubff(k) <= '0'; ccsatff(k) <= '0'; cczipff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN --* LEVEL 1 * aaff <= aa; bbff <= bb; aasatff <= aasat; bbsatff <= bbsat; aazipff <= aazip; bbzipff <= bbzip; addsubff(1) <= addsub; FOR k IN 2 TO 3+shiftspeed LOOP addsubff(k) <= addsubff(k-1); END LOOP; --* LEVEL 2 * FOR k IN 1 TO mantissa LOOP manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch); manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch); END LOOP; FOR k IN 1 TO 10 LOOP expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch); END LOOP; FOR k IN 1 TO 10 LOOP expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch); END LOOP; FOR k IN 2 TO 3+shiftspeed LOOP expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1); END LOOP; invertleftff <= addsubff(1) AND switch; invertrightff <= addsubff(1) AND NOT(switch); ccsatff(1) <= aasatff OR bbsatff; cczipff(1) <= aazipff AND bbzipff; FOR k IN 2 TO 3+shiftspeed LOOP ccsatff(k) <= ccsatff(k-1); cczipff(k) <= cczipff(k-1); END LOOP; --* LEVEL 3 or 4 * FOR k IN 1 TO mantissa LOOP manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode; END LOOP; --* LEVEL 4 or 5 * aluff <= aluleftnode + alurightnode + alucarrynode; END IF; END IF; END PROCESS; gssa: IF (shiftspeed = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa LOOP aluleftff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO mantissa LOOP aluleftff(k) <= manleftff(k) XOR invertleftnode; END LOOP; END IF; END IF; END PROCESS; invertleftnode <= invertleftff; invertrightnode <= invertrightff; expzerochknode <= expzerochk(10); aluleftnode <= aluleftff; alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3); END GENERATE; gssb: IF (shiftspeed = 1) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa LOOP aluleftdelff(1)(k) <= '0'; aluleftdelff(2)(k) <= '0'; END LOOP; invertleftdelff <= '0'; invertrightdelff <= '0'; expzerochkff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff; FOR k IN 1 TO mantissa LOOP aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode; END LOOP; invertleftdelff <= invertleftff; invertrightdelff <= invertrightff; expzerochkff <= expzerochk(10); END IF; END IF; END PROCESS; invertleftnode <= invertleftdelff; invertrightnode <= invertrightdelff; expzerochknode <= expzerochkff; aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1); alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4); END GENERATE; alurightnode <= manalignff; subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1); subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1); switch <= subexpone(10); gsa: IF (mantissa = 32) GENERATE expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not gsb: IF (shiftspeed = 0) GENERATE shiftone: hcc_rsftcomb32 PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; gsc: IF (shiftspeed = 1) GENERATE shifttwo: hcc_rsftpipe32 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; END GENERATE; gsd: IF (mantissa = 36) GENERATE expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not gse: IF (shiftspeed = 0) GENERATE shiftone: hcc_rsftcomb36 PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; gsf: IF (shiftspeed = 1) GENERATE shifttwo: hcc_rsftpipe36 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; END GENERATE; --* OUTPUT * cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1); ccsat <= ccsatff(3+shiftspeed); cczip <= cczipff(3+shiftspeed); --* DEBUG SECTION *** aaexp <= aa(10 DOWNTO 1); bbexp <= bb(10 DOWNTO 1); ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); bbman <= bb(mantissa+10 DOWNTO 11); ccman <= aluff; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_exprnd.vhd	10	7830	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_EXPRND.VHD * --* * --* Function: FP Exponent Output Block - * --* Rounded * --* * --* Generated by MATLAB Utility * --* * --* 18/02/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --*********************************************** ENTITY fp_exprnd IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit nanin : IN STD_LOGIC; rangeerror : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); END fp_exprnd; ARCHITECTURE rtl OF fp_exprnd IS constant expwidth : positive := 8; constant manwidth : positive := 23; type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1); signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal rangeerrorff : STD_LOGIC; signal overflownode, underflownode : STD_LOGIC; signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal manoverflowbitff : STD_LOGIC; signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1); signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal setmanzero, setmanmax : STD_LOGIC; signal setexpzero, setexpmax : STD_LOGIC; BEGIN gzv: FOR k IN 1 TO manwidth-1 GENERATE zerovec(k) <= '0'; END GENERATE; pra: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN nanff <= "00"; rangeerrorff <= '0'; overflowff <= "00"; underflowff <= "00"; manoverflowbitff <= '0'; FOR k IN 1 TO manwidth LOOP roundmantissaff(k) <= '0'; mantissaff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth+2 LOOP exponentoneff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF(enable = '1') THEN nanff(1) <= nanin; nanff(2) <= nanff(1); rangeerrorff <= rangeerror; overflowff(1) <= overflownode; overflowff(2) <= overflowff(1); underflowff(1) <= underflownode; underflowff(2) <= underflowff(1); manoverflowbitff <= manoverflow(manwidth+1); roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1)); -- nan takes precedence (set max) -- nan takes precedence (set max) FOR k IN 1 TO manwidth LOOP mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax; END LOOP; exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax; END LOOP; END IF; END IF; END PROCESS; exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) + (zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff); --***************************** --* PREDICT MANTISSA OVERFLOW * --***************************** manoverflow(1) <= mantissaexp(1); gmoa: FOR k IN 2 TO manwidth+1 GENERATE manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k); END GENERATE; --****************************** --* CHECK GENERATED CONDITIONS * --****************************** -- infinity if exponent == 255 infinitygen(1) <= exponentnode(1); gia: FOR k IN 2 TO expwidth GENERATE infinitygen(k) <= infinitygen(k-1) AND exponentnode(k); END GENERATE; infinitygen(expwidth+1) <= infinitygen(expwidth) OR (exponentnode(expwidth+1) AND NOT(exponentnode(expwidth+2))); -- '1' if infinity -- zero if exponent == 0 zerogen(1) <= exponentnode(1); gza: FOR k IN 2 TO expwidth GENERATE zerogen(k) <= zerogen(k-1) OR exponentnode(k); END GENERATE; zerogen(expwidth+1) <= zerogen(expwidth) AND NOT(exponentnode(expwidth+2)); -- '0' if zero -- trap any other overflow errors -- when sign = 0 and rangeerror = 1, overflow -- when sign = 1 and rangeerror = 1, underflow overflownode <= NOT(signin) AND rangeerror; underflownode <= signin AND rangeerror; -- set mantissa to 0 when infinity or zero condition setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff); -- setmantissa to "11..11" when nan setmanmax <= nanin; -- set exponent to 0 when zero condition setexpzero <= zerogen(expwidth+1); -- set exponent to "11..11" when nan, infinity, or divide by 0 setexpmax <= nanin OR infinitygen(expwidth+1) OR rangeerrorff; --*********** --* OUTPUTS * --************* signout <= '0'; mantissaout <= mantissaff; exponentout <= exponenttwoff; ----------------------------------------------- nanout <= nanff(2); overflowout <= overflowff(2); underflowout <= underflowff(2); END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_atan.vhd	10	17028	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_ATAN.VHD * --* * --* Function: Single Precision Floating Point * --* ArcTangent * --* * --* 23/12/09 ML * --* * --* (c) 2009 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --*********************************************** --*********************************************** --* NOTES * --************************************************* -- slight improvement when "roundbit" is used i.e. round up from -- X.4999 - exact number of bits to be used needs to be tweaked ENTITY fp_atan IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); END fp_atan; ARCHITECTURE rtl OF fp_atan IS constant coredepth : positive := 12; constant b_precision : positive := 10; type exponentinfftype IS ARRAY (coredepth-2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); type exponenttopfftype IS ARRAY (coredepth-3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); type mantissabpfftype IS ARRAY (2coredepth+10 DOWNTO 1) OF STD_LOGIC_VECTOR (23 DOWNTO 1); -- SPR: 380600 type termfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1); signal pi_over_two : STD_LOGIC_VECTOR (36 DOWNTO 1); signal inputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1); signal delinputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1); signal topquotient : STD_LOGIC_VECTOR (36 DOWNTO 1); signal topquotientnumber : STD_LOGIC_VECTOR (36 DOWNTO 1); signal exponentoffset : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exponentinff : exponentinfftype; signal idselectff : STD_LOGIC_VECTOR (2coredepth+10 DOWNTO 1); -- SPR: 380600 signal pathselectff : STD_LOGIC_VECTOR (2coredepth+9 DOWNTO 1); signal exponenttopff : exponenttopfftype; signal forward_shiftff, inverse_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1); signal a_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1); signal a_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal a_fixedpointbus : STD_LOGIC_VECTOR (36 DOWNTO 1); signal a_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1); signal pathcheck : STD_LOGIC_VECTOR (9 DOWNTO 1); signal a_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1); signal b_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1); signal c_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1); signal ab_fixedpoint : STD_LOGIC_VECTOR (37 DOWNTO 1); signal ab_plusone : STD_LOGIC_VECTOR (36 DOWNTO 1); signal numerator, denominator : STD_LOGIC_VECTOR (36 DOWNTO 1); signal addterm : STD_LOGIC_VECTOR (36 DOWNTO 1); signal b_address : STD_LOGIC_VECTOR (10 DOWNTO 1); signal lutterm : STD_LOGIC_VECTOR (36 DOWNTO 1); signal dellutterm : STD_LOGIC_VECTOR (36 DOWNTO 1); signal signff : STD_LOGIC_VECTOR (2coredepth+11 DOWNTO 1); signal mantissabpff : mantissabpfftype; -- SPR: 380600 signal atantermff : termfftype; signal large_atanff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal small_mantissa, small_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal large_mantissa, large_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal mux_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1); signal small_count, small_countff : STD_LOGIC_VECTOR (6 DOWNTO 1); signal small_overflowbus, large_overflowbus : STD_LOGIC_VECTOR (24 DOWNTO 1); signal small_overflowff, large_overflowff : STD_LOGIC; signal mux_overflow : STD_LOGIC; signal roundbit : STD_LOGIC; signal mantissa_roundff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal mantissa_bypass : STD_LOGIC_VECTOR (23 DOWNTO 1); signal exponent_outff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal small_exponent_adjust, large_exponent_adjust : STD_LOGIC_VECTOR (8 DOWNTO 1); signal exponent_adjust, exponent_adjustff : STD_LOGIC_VECTOR (8 DOWNTO 1); -- SPR: 380600 signal expinzero : STD_LOGIC_VECTOR (8 DOWNTO 1); signal expzero : STD_LOGIC; component fp_inv_core GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1); quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_rsft36 PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_del GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_fxmul GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_atanlut PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_clz36 PORT ( mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1); leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1) ); end component; component fp_lsft36 IS PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO 36 GENERATE zerovec(k) <= '0'; END GENERATE; pi_over_two <= x"C90FDAA22"; -- 1.57... --* Invert Input * inputnumber <= '1' & mantissain & "000000000000"; -- will give output between 0.5 and 0.99999... -- will always need to be normalized invcore: fp_inv_core PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>inputnumber, quotient=>topquotient); exponentoffset <= conv_std_logic_vector (127,10); pinx: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO coredepth-2 LOOP FOR j IN 1 TO 8 LOOP exponentinff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO 2coredepth+9 LOOP pathselectff(k) <= '0'; END LOOP; -- SPR: 380600 FOR k IN 1 TO 2coredepth+10 LOOP idselectff(k) <= '0'; END LOOP; FOR k IN 1 TO coredepth-3 LOOP FOR j IN 1 TO 10 LOOP exponenttopff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO 10 LOOP forward_shiftff(k) <= '0'; inverse_shiftff(k) <= '0'; a_shiftff(k) <= '0'; END LOOP; FOR k IN 1 TO 36 LOOP a_fixedpointff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN exponentinff(1)(8 DOWNTO 1) <= exponentin; FOR k IN 2 TO coredepth-2 LOOP exponentinff(k)(8 DOWNTO 1) <= exponentinff(k-1)(8 DOWNTO 1); END LOOP; pathselectff(1) <= pathcheck(9); FOR k IN 2 TO 2coredepth+9 LOOP pathselectff(k) <= pathselectff(k-1); END LOOP; -- SPR: 380600 idselectff(1) <= expzero; FOR k IN 2 TO 2coredepth+10 LOOP idselectff(k) <= idselectff(k-1); END LOOP; -- exponent for inverse, used when exponent > 126 exponenttopff(1)(10 DOWNTO 1) <= exponentoffset - ("00" & exponentinff(1)(8 DOWNTO 1)); exponenttopff(2)(10 DOWNTO 1) <= exponenttopff(1)(10 DOWNTO 1) + exponentoffset; exponenttopff(3)(10 DOWNTO 1) <= exponenttopff(2)(10 DOWNTO 1) - 1; -- inverse always less than 1, decrement exponent FOR k IN 4 TO coredepth-3 LOOP exponenttopff(k)(10 DOWNTO 1) <= exponenttopff(k-1)(10 DOWNTO 1); END LOOP; forward_shiftff <= "0001111111" - ("00" & exponentinff(coredepth-2)(8 DOWNTO 1)); inverse_shiftff <= "0001111111" - exponenttopff(coredepth-3)(10 DOWNTO 1); FOR k IN 1 TO 6 LOOP a_shiftff(k) <= (forward_shiftff(k) AND NOT(pathselectff(coredepth-2))) OR (inverse_shiftff(k) AND pathselectff(coredepth-2)); END LOOP; a_fixedpointff <= a_fixedpointbus; END IF; END IF; END PROCESS; -- if <=126 (<= 0.999999), use atan(x) path, else use (pi/2-atan(1/x)) path pathcheck <= "001111110" - ('0' & exponentinff(1)(8 DOWNTO 1)); cdma: fp_del GENERIC MAP (width=>36,pipes=>coredepth) -- 12 for inv_core PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>inputnumber, cc=>delinputnumber); topquotientnumber <= topquotient(35 DOWNTO 1) & '0'; gma: FOR k IN 1 TO 36 GENERATE a_mantissanode(k) <= (delinputnumber(k) AND NOT(pathselectff(coredepth-1))) OR (topquotientnumber(k) AND pathselectff(coredepth-1)); END GENERATE; casr: fp_rsft36 PORT MAP (inbus=>a_mantissanode,shift=>a_shiftff(6 DOWNTO 1), outbus=>a_fixedpointbus); a_fixedpoint <= a_fixedpointff; b_fixedpoint <= a_fixedpointff(36 DOWNTO 37-b_precision) & zerovec(36-b_precision DOWNTO 1); c_fixedpoint <= a_fixedpointff(36-b_precision DOWNTO 1) & zerovec(b_precision DOWNTO 1); cmone: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37, pipes=>3) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>a_fixedpoint,databb=>b_fixedpoint, result=>ab_fixedpoint); ab_plusone <= '1' & ab_fixedpoint(35 DOWNTO 1); -- ab_fixedpoint always 1/4 true value invtwo: fp_inv_core PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>ab_plusone, quotient=>denominator); cdc: fp_del GENERIC MAP (width=>36,pipes=>coredepth+3) -- inv_core and 3 for 3636 mult PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>c_fixedpoint, cc=>numerator); cmtwo: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36, pipes=>3) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>numerator,databb=>denominator, result=>addterm); b_address <= a_fixedpoint(36 DOWNTO 37-b_precision); clut: fp_atanlut PORT MAP (add=>b_address, data=>lutterm); cdlut: fp_del GENERIC MAP (width=>36,pipes=>18) -- 12 for inv_core and 3 for 3636 mult PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>lutterm, cc=>dellutterm); pimo: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 2coredepth+11 LOOP signff(k) <= '0'; END LOOP; -- SPR: 380600 FOR k IN 1 TO 2coredepth+10 LOOP FOR j IN 1 TO 23 LOOP mantissabpff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO 36 LOOP atantermff(1)(k) <= '0'; atantermff(2)(k) <= '0'; large_atanff(k) <= '0'; small_mantissaff(k) <= '0'; large_mantissaff(k) <= '0'; END LOOP; FOR k IN 1 TO 6 LOOP small_countff(k) <= '0'; END LOOP; small_overflowff <= '0'; large_overflowff <= '0'; FOR k IN 1 TO 23 LOOP mantissa_roundff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP exponent_outff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN signff(1) <= signin; mantissabpff(1)(23 DOWNTO 1) <= mantissain(23 DOWNTO 1); FOR k IN 2 TO 2coredepth+11 LOOP signff(k) <= signff(k-1); END LOOP; -- SPR: 380600 FOR k IN 2 TO 2coredepth+10 LOOP mantissabpff(k)(23 DOWNTO 1) <= mantissabpff(k-1)(23 DOWNTO 1); END LOOP; atantermff(1)(36 DOWNTO 1) <= dellutterm + (zerovec(9 DOWNTO 1) & addterm(36 DOWNTO 10)); atantermff(2)(36 DOWNTO 1) <= atantermff(1)(36 DOWNTO 1); -- always in the range 0.78 to pi/2 large_atanff(36 DOWNTO 1) <= pi_over_two - atantermff(1)(36 DOWNTO 1); small_countff <= small_count; large_mantissaff <= large_mantissa; small_mantissaff <= small_mantissa; small_overflowff <= small_overflowbus(24); large_overflowff <= large_overflowbus(24); exponent_adjustff <= exponent_adjust; --mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + mux_mantissa(12); mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + roundbit; exponent_outff <= "01111111" - exponent_adjustff + mux_overflow; END IF; END IF; END PROCESS; roundbit <= mux_mantissa(12) OR (mux_mantissa(11) AND mux_mantissa(10) AND mux_mantissa(9) AND mux_mantissa(8) AND mux_mantissa(7) AND mux_mantissa(6) AND mux_mantissa(5) AND mux_mantissa(4) AND mux_mantissa(3) AND mux_mantissa(2)); ccsat: fp_clz36 PORT MAP (mantissa=>atantermff(1)(36 DOWNTO 1), leading=>small_count); cssat: fp_lsft36 PORT MAP (inbus=>atantermff(2)(36 DOWNTO 1),shift=>small_countff, outbus=>small_mantissa); small_overflowbus(1) <= small_mantissa(12); gova: FOR k IN 2 TO 24 GENERATE small_overflowbus(k) <= small_overflowbus(k-1) AND small_mantissa(k+11); END GENERATE; glma: FOR k IN 1 TO 35 GENERATE large_mantissa(k+1) <= (large_atanff(k) AND NOT(large_atanff(36))) OR (large_atanff(k+1) AND large_atanff(36)); END GENERATE; large_mantissa(1) <= '0'; large_overflowbus(1) <= large_mantissa(12); govb: FOR k IN 2 TO 24 GENERATE large_overflowbus(k) <= large_overflowbus(k-1) AND large_mantissa(k+11); END GENERATE; gmma: FOR k IN 1 TO 36 GENERATE mux_mantissa(k) <= (small_mantissaff(k) AND NOT(pathselectff(2coredepth+9))) OR (large_mantissaff(k) AND pathselectff(2coredepth+9)); END GENERATE; mux_overflow <= (small_overflowff AND NOT(pathselectff(2coredepth+9))) OR (large_overflowff AND pathselectff(2coredepth+9)); large_exponent_adjust <= "0000000" & NOT(large_atanff(36)); small_exponent_adjust <= "00" & small_countff; gxa: FOR k IN 1 TO 8 GENERATE exponent_adjust(k) <= (small_exponent_adjust(k) AND NOT(pathselectff(2coredepth+8))) OR (large_exponent_adjust(k) AND pathselectff(2coredepth+8)); END GENERATE; -- SPR: 380600 bypass: FOR k IN 1 TO 23 GENERATE mantissa_bypass(k) <= (mantissa_roundff(k) AND NOT(idselectff(2coredepth+10))) OR (mantissabpff(2coredepth+10)(k) AND idselectff(2coredepth+10)); END GENERATE; -- SPR: 380600 expinzero(1) <= exponentinff(1)(1); gxza: FOR k IN 2 TO 8 GENERATE expinzero(k) <= expinzero(k-1) OR exponentinff(1)(k); END GENERATE; expzero <= NOT(expinzero(8)); -- '0' when zero -- OUTPUTS * signout <= signff(2coredepth+11); exponentout <= (others => '0') when idselectff(2coredepth+10) = '1' else exponent_outff; -- SPR: 380600 mantissaout <= mantissa_bypass; end rtl;	mit
ou-cse-378/vhdl-tetris	datastack.vhd	1	3086	-- ================================================================================= -- // Name: Bryan Mason, James Batcheler, & Brad McMahon -- // File: Datastack.vhd -- // Date: 12/9/2004 -- // Description: Datastack -- // Class: CSE 378 -- ================================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity datastack is port ( TLoad : in std_logic; y1 : in STD_LOGIC_VECTOR(15 downto 0); nsel : in STD_LOGIC_VECTOR(1 downto 0); nload : in STD_LOGIC; ssel : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC; dpush : in STD_LOGIC; dpop : in STD_LOGIC; Tin : in STD_LOGIC_VECTOR(15 downto 0); T : out STD_LOGIC_VECTOR(15 downto 0); N : out STD_LOGIC_VECTOR(15 downto 0); N2 : out STD_LOGIC_VECTOR(15 downto 0) ); end datastack; architecture Behavioral of datastack is component stack32x16 port ( d : in STD_LOGIC_VECTOR(15 downto 0); clk : in STD_LOGIC; clr : in STD_LOGIC; push : in STD_LOGIC; pop : in STD_LOGIC; full : out STD_LOGIC; empty : out STD_LOGIC; q : out STD_LOGIC_VECTOR(15 downto 0) ); END component; component mux2g generic(width:positive); Port ( a : in std_logic_vector(width-1 downto 0); b : in std_logic_vector(width-1 downto 0); sel : in std_logic; y : out std_logic_vector(width-1 downto 0) ); end component; component mux4g generic(width:positive); Port ( a : in std_logic_vector(width-1 downto 0); b : in std_logic_vector(width-1 downto 0); c : in std_logic_vector(width-1 downto 0); d : in std_logic_vector(width-1 downto 0); sel : in std_logic_vector(1 downto 0); y : out std_logic_vector(width-1 downto 0) ); end component; component reg generic(width: positive); port ( d : in STD_LOGIC_VECTOR (width-1 downto 0); load : in STD_LOGIC; clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (width-1 downto 0) ); end component; constant bus_width: positive := 16; signal T1: std_logic_vector(15 downto 0); signal N1: std_logic_vector(15 downto 0); signal NS: std_logic_vector(15 downto 0); signal D: std_logic_vector(15 downto 0); signal NIN: std_logic_vector(15 downto 0); signal FULL: std_logic; signal EMPTY: std_logic; begin T <= T1; N <= N1; N2 <= NS; SWtreg : reg generic map (width => bus_width) port map ( d => TIN, load => TLOAD, clr => CLR, clk => CLK, q => T1 ); SWnreg : reg generic map (width => bus_width) port map ( d => NIN, load => NLOAD, clr => CLR, clk => CLK, q => N1 ); SWmux2g: mux2g generic map (width => bus_width) port map ( a => N1, b => T1, sel => SSEL, y => D ); SWmux4g: mux4g generic map (width => bus_width) port map ( a => T1, b => NS, c => Y1, d=> Y1, sel => NSEL, y => NIN ); SWstack32x16: stack32x16 port map ( d => D, clk => CLK, clr => CLR, push => DPUSH, pop => DPOP, full => FULL, empty => EMPTY, q => NS ); end behavioral;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_inv_core.vhd	10	6144	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* SINGLE PRECISION INVERSE - CORE * --* * --* FP_INV_CORE.VHD * --* * --* Function: 36 bit Inverse * --* (multiplicative iterative algorithm) * --* * --* 09/12/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --*********************************************** --*********************************************** --* Notes: Latency = 12 * --*********************************************** ENTITY fp_inv_core IS GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1); quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); END fp_inv_core; ARCHITECTURE rtl OF fp_inv_core IS signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1); signal divisordel : STD_LOGIC_VECTOR (36 DOWNTO 1); signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1); signal delinvdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1); signal scaleden : STD_LOGIC_VECTOR (36 DOWNTO 1); signal twonode : STD_LOGIC_VECTOR (37 DOWNTO 1); signal nextguessff : STD_LOGIC_VECTOR (37 DOWNTO 1); signal quotientnode : STD_LOGIC_VECTOR (36 DOWNTO 1); component fp_div_est IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1); invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1) ); end component; component fp_fxmul IS GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_del GENERIC ( width : positive := 64; pipes : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO 36 GENERATE zerovec(k) <= '0'; END GENERATE; invcore: fp_div_est PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>divisor(36 DOWNTO 18),invdivisor=>invdivisor); delinone: fp_del GENERIC MAP (width=>36,pipes=>5) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>divisor,cc=>divisordel); --****************************** --* ITERATION 0 - SCALE INPUTS * --****************************** -- in level 5, out level 8 mulscaleone: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36, pipes=>3,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>divisordel,databb=>invdivisor, result=>scaleden); --**************** --* ITERATION 1 * --****************** twonode <= '1' & zerovec(36 DOWNTO 1); pita: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 37 LOOP nextguessff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN nextguessff <= twonode - ('0' & scaleden); -- level 9 END IF; END IF; END PROCESS; deloneone: fp_del GENERIC MAP (width=>18,pipes=>4) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>invdivisor, cc=>delinvdivisor); -- in level 9, out level 12 muloneone: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36, pipes=>3,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>nextguessff(36 DOWNTO 1),databb=>delinvdivisor, result=>quotientnode); quotient <= quotientnode(36 DOWNTO 1); END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_sum36x18.vhd	10	18695	-- megafunction wizard: %ALTMULT_ADD% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: ALTMULT_ADD -- ============================================================ -- File Name: sum36x18.vhd -- Megafunction Name(s): -- ALTMULT_ADD -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ********************************************************** -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 8.1 Build 163 10/28/2008 SJ Full Version -- ********************************************************** --Copyright (C) 1991-2008 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY fp_sum36x18 IS PORT ( aclr3 : IN STD_LOGIC := '0'; clock0 : IN STD_LOGIC := '1'; dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0'); dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0'); datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0'); datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0'); ena0 : IN STD_LOGIC := '1'; result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0) ); END fp_sum36x18; ARCHITECTURE SYN OF fp_sum36x18 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0); SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0); COMPONENT altmult_add GENERIC ( accumulator : STRING; addnsub_multiplier_aclr1 : STRING; addnsub_multiplier_pipeline_aclr1 : STRING; addnsub_multiplier_pipeline_register1 : STRING; addnsub_multiplier_register1 : STRING; chainout_adder : STRING; chainout_register : STRING; dedicated_multiplier_circuitry : STRING; input_aclr_a0 : STRING; input_aclr_a1 : STRING; input_aclr_b0 : STRING; input_aclr_b1 : STRING; input_register_a0 : STRING; input_register_a1 : STRING; input_register_b0 : STRING; input_register_b1 : STRING; input_source_a0 : STRING; input_source_a1 : STRING; input_source_b0 : STRING; input_source_b1 : STRING; intended_device_family : STRING; lpm_type : STRING; multiplier1_direction : STRING; multiplier_aclr0 : STRING; multiplier_aclr1 : STRING; multiplier_register0 : STRING; multiplier_register1 : STRING; number_of_multipliers : NATURAL; output_aclr : STRING; output_register : STRING; port_addnsub1 : STRING; port_signa : STRING; port_signb : STRING; representation_a : STRING; representation_b : STRING; signed_aclr_a : STRING; signed_aclr_b : STRING; signed_pipeline_aclr_a : STRING; signed_pipeline_aclr_b : STRING; signed_pipeline_register_a : STRING; signed_pipeline_register_b : STRING; signed_register_a : STRING; signed_register_b : STRING; width_a : NATURAL; width_b : NATURAL; width_chainin : NATURAL; width_result : NATURAL; zero_chainout_output_aclr : STRING; zero_chainout_output_register : STRING; zero_loopback_aclr : STRING; zero_loopback_output_aclr : STRING; zero_loopback_output_register : STRING; zero_loopback_pipeline_aclr : STRING; zero_loopback_pipeline_register : STRING; zero_loopback_register : STRING ); PORT ( dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0); clock0 : IN STD_LOGIC ; aclr3 : IN STD_LOGIC ; ena0 : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire6 <= datab_1(35 DOWNTO 0); sub_wire3 <= dataa_1(17 DOWNTO 0); result <= sub_wire0(54 DOWNTO 0); sub_wire1 <= dataa_0(17 DOWNTO 0); sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0); sub_wire4 <= datab_0(35 DOWNTO 0); sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0); ALTMULT_ADD_component : ALTMULT_ADD GENERIC MAP ( accumulator => "NO", addnsub_multiplier_aclr1 => "ACLR3", addnsub_multiplier_pipeline_aclr1 => "ACLR3", addnsub_multiplier_pipeline_register1 => "CLOCK0", addnsub_multiplier_register1 => "CLOCK0", chainout_adder => "NO", chainout_register => "UNREGISTERED", dedicated_multiplier_circuitry => "AUTO", input_aclr_a0 => "ACLR3", input_aclr_a1 => "ACLR3", input_aclr_b0 => "ACLR3", input_aclr_b1 => "ACLR3", input_register_a0 => "CLOCK0", input_register_a1 => "CLOCK0", input_register_b0 => "CLOCK0", input_register_b1 => "CLOCK0", input_source_a0 => "DATAA", input_source_a1 => "DATAA", input_source_b0 => "DATAB", input_source_b1 => "DATAB", intended_device_family => "Stratix III", lpm_type => "altmult_add", multiplier1_direction => "ADD", multiplier_aclr0 => "ACLR3", multiplier_aclr1 => "ACLR3", multiplier_register0 => "CLOCK0", multiplier_register1 => "CLOCK0", number_of_multipliers => 2, output_aclr => "ACLR3", output_register => "CLOCK0", port_addnsub1 => "PORT_UNUSED", port_signa => "PORT_UNUSED", port_signb => "PORT_UNUSED", representation_a => "UNSIGNED", representation_b => "UNSIGNED", signed_aclr_a => "ACLR3", signed_aclr_b => "ACLR3", signed_pipeline_aclr_a => "ACLR3", signed_pipeline_aclr_b => "ACLR3", signed_pipeline_register_a => "CLOCK0", signed_pipeline_register_b => "CLOCK0", signed_register_a => "CLOCK0", signed_register_b => "CLOCK0", width_a => 18, width_b => 36, width_chainin => 1, width_result => 55, zero_chainout_output_aclr => "ACLR3", zero_chainout_output_register => "CLOCK0", zero_loopback_aclr => "ACLR3", zero_loopback_output_aclr => "ACLR3", zero_loopback_output_register => "CLOCK0", zero_loopback_pipeline_aclr => "ACLR3", zero_loopback_pipeline_register => "CLOCK0", zero_loopback_register => "CLOCK0" ) PORT MAP ( dataa => sub_wire2, datab => sub_wire5, clock0 => clock0, aclr3 => aclr3, ena0 => ena0, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add" -- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1" -- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1" -- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1" -- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0" -- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1" -- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0" -- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0" -- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0" -- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0" -- Retrieval info: PRIVATE: HAS_MAC STRING "0" -- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0" -- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0" -- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0" -- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1" -- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III" -- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1" -- Retrieval info: PRIVATE: NUM_MULT STRING "2" -- Retrieval info: PRIVATE: OP1 STRING "Add" -- Retrieval info: PRIVATE: OP3 STRING "Add" -- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0" -- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: REG_OUT NUMERIC "1" -- Retrieval info: PRIVATE: RNFORMAT STRING "55" -- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1" -- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ROTATE_REG STRING "1" -- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15" -- Retrieval info: PRIVATE: RTS_WIDTH STRING "55" -- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1" -- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1" -- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1" -- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0" -- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0" -- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1" -- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1" -- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None" -- Retrieval info: PRIVATE: SIGNA STRING "Unsigned" -- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: SIGNA_REG STRING "1" -- Retrieval info: PRIVATE: SIGNB STRING "Unsigned" -- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: SIGNB_REG STRING "1" -- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input" -- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: WIDTHA STRING "18" -- Retrieval info: PRIVATE: WIDTHB STRING "36" -- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO" -- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED" -- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO" -- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA" -- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA" -- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB" -- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add" -- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD" -- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3" -- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3" -- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0" -- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2" -- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED" -- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED" -- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36" -- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1" -- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55" -- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0" -- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3" -- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0" -- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]" -- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]" -- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]" -- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]" -- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0" -- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]" -- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0 -- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0 -- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0 -- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0 -- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0 -- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0 -- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE -- Retrieval info: LIB_FILE: altera_mf	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_tanlut1.vhd	10	94202	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_TANLUT1.VHD * --* * --* Function: Tangent Look Up Table * --* (Generated by MATLAB Utility) * --* * --* 22/12/09 ML * --* * --* (c) 2009 Altera Corporation * --* * --* Change History * --* * --* * --* * --************************************************* ENTITY fp_tanlut1 IS PORT ( add : IN STD_LOGIC_VECTOR (9 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1) ); END fp_tanlut1; ARCHITECTURE rtl OF fp_tanlut1 IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "000000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5); WHEN "000000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131072,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174764,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5); WHEN "000000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131074,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174780,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5); WHEN "000000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196617,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5); WHEN "000000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131082,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175036,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163860,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219287,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196644,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2074,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229433,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131114,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179133,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147516,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(204485,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163923,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(100723,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180334,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261788,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196752,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33207,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213175,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71403,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229604,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246559,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246041,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166927,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131242,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244778,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139469,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18368,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147699,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126224,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155934,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110829,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164174,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39099,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172418,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240249,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180668,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257224,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188924,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157429,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197186,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(8449,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205453,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140199,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213727,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96362,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222007,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(207256,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230295,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16983,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238589,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118443,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246891,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(56191,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255200,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161457,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131758,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251787,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135921,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182851,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140088,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170994,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144259,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251287,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148435,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196795,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152616,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(42877,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156801,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87190,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160991,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103258,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165186,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126910,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169386,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194144,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173592,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78984,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177803,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79918,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182019,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233473,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186242,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52073,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190470,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96910,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194704,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142940,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198944,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227466,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203191,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125851,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207444,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137961,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211704,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39590,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215970,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131044,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220243,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188568,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224523,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(250786,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228811,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94417,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233106,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20713,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69033,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241718,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16848,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246035,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166180,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250361,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32888,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254694,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181681,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259036,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128971,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131693,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88946,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133872,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184862,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110880,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138244,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150087,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140437,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61438,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142634,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128336,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144836,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110058,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147043,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(28193,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149254,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166641,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151471,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(23046,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153692,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(143802,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155919,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(26909,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158150,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219127,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160387,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218828,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162630,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48862,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164877,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256563,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167131,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78745,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169390,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63145,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171654,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233418,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173925,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89145,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176201,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178694,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178484,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2082,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180772,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108121,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183066,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259423,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185367,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218831,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187675,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11570,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189988,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187394,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192308,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247729,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194635,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218538,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196969,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126042,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199309,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258866,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201657,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119470,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204011,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259160,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206373,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180942,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208742,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174537,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211119,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5664,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213502,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226767,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215894,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79866,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218293,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118006,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220700,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108111,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223115,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79560,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225538,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62056,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227969,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85630,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180644,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232856,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115658,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235312,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183865,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237777,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154523,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240251,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(59395,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242733,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192751,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(245225,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62806,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(247725,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226729,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250235,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(193502,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252754,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258933,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255283,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194946,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257822,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36018,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260370,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79189,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131464,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48818,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132748,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63557,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134037,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101912,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135331,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182207,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136631,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60853,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137936,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18783,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139246,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(75024,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140561,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248849,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141883,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(35488,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143209,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241146,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144542,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99421,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145880,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154894,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147224,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(165983,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148574,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153522,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149930,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138624,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151292,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142687,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152660,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187397,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154035,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32592,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155415,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(224845,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156803,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(313,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158196,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168333,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159596,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227841,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161003,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202385,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162417,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115847,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163837,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(254593,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165265,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118901,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166699,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257978,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168141,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172818,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169590,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(151210,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171046,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219176,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172510,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140977,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173981,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205552,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175460,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177949,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176947,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85768,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178441,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219166,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179944,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(82294,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181454,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(228309,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182973,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(162236,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184500,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175979,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186036,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37616,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187580,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39982,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189132,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214250,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190694,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(67791,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192264,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157055,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193843,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252568,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195432,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125382,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197030,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71365,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198637,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(124791,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200254,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(58341,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201880,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169556,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203516,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(232268,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205163,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20904,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206819,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96928,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208485,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235993,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210162,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214385,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211850,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71183,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213548,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108271,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215257,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103923,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216977,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99249,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218708,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(136066,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220450,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256917,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222204,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242940,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223970,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225747,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249580,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227537,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(98477,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229338,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(255571,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231152,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(243824,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232979,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111333,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(234818,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169210,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236670,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205169,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238536,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7833,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240414,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153192,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242306,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169612,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244212,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110728,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246132,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248065,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248754,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250014,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33745,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251976,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230368,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253954,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111078,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255946,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(260182,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257954,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214570,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259978,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36603,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(262017,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52004,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132036,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31728,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133071,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199603,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134115,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170119,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135167,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(239798,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136228,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181565,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137298,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31195,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138376,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87334,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139463,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125082,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140559,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182447,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141665,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36078,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142779,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249858,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143904,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77779,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145038,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85397,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(146182,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52708,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147336,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(22748,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148500,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39467,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149674,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(147762,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150859,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131351,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152055,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37096,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153261,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175023,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154479,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69779,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155708,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33524,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156948,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117385,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158200,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111488,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159464,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69279,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160740,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45413,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162028,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95789,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163329,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(15442,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164642,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125012,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165968,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222206,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167308,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(106129,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168661,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101608,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170028,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10664,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161129,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172803,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95974,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174212,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(146219,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175636,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(120264,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177075,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90370,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178529,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130571,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179999,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54581,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181484,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202287,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182986,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(129087,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184504,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178815,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186039,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173083,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187591,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197786,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189161,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78873,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190748,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168858,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192354,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193978,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38109,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195621,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10173,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197283,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52606,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198965,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6187,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200666,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238745,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202389,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(72398,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204132,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142943,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205897,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(40664,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207683,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145442,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(209492,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54008,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211323,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(152917,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213178,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45809,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126393,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216959,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5720,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218886,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85177,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220838,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(245917,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222817,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111146,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224822,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94854,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226854,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91265,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228913,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261427,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231001,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246970,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233118,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218857,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235265,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91152,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237442,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45510,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(239650,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7099,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241889,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169116,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244161,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(206583,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246467,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63025,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248806,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(212871,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251181,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88861,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253591,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179473,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256038,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194218,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258523,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(112522,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(261046,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184058,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131804,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202396,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133106,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(127604,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134429,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5700,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135772,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241668,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137138,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196914,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138527,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(24498,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139938,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145076,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141373,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(198575,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142833,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(93021,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144318,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(4818,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145828,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116886,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147365,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94683,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148929,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(135102,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150521,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180373,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152142,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180573,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153793,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94005,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155474,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149742,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(157187,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61623,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158932,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77284,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160710,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192200,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162523,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150199,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164371,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230433,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166256,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199372,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168179,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(97853,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170140,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241724,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172142,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173961,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174185,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238269,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176272,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6999,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178402,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116996,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180578,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173338,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182802,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61011,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185074,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(208074,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187398,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(13879,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189773,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(209544,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192203,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237754,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194690,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89118,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197235,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(41457,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199840,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137068,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202508,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184378,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205242,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(21881,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208043,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(44347,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210914,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156319,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213859,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36498,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216879,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188732,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(219979,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(109619,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223161,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126346,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226429,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89021,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229786,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(160435,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233237,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33224,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236784,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244509,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240434,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83006,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244189,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(215105,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(68494,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252038,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196984,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256142,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(189406,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260373,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249093,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132369,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(76283,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134621,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153043,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136947,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90777,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139350,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(80594,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141834,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118724,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144404,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(12410,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147063,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172855,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149818,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(49588,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152672,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235640,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155633,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117182,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158705,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242792,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161896,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237423,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165213,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125600,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168663,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83253,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172254,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191313,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175996,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191297,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179899,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(29637,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183972,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142533,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188228,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(171026,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192680,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38953,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197340,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248662,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202226,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(84469,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207353,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16170,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(212739,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177173,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218406,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161382,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224376,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140334,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230674,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156722,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237328,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218000,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244370,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(144312,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251834,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222783,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259761,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(51093,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134097,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16112,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138592,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11144,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143394,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60483,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148536,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(104003,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37731,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159996,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218457,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191255,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173350,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(113148,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180890,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(176944,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189110,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(163200,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198106,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(211327,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207994,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247747,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218914,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252397,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231037,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174172,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244573,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197553,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259786,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(53842,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138503,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202780,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148332,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62994,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159656,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230897,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172847,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240508,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183509,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207041,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119228,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229756,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71260,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258060,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153597,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147154,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32322,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171195,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78299,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204618,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(105365,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254248,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(141622,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167825,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(19278,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5); WHEN "110010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246850,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149873,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5); WHEN "110010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233251,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(216105,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(15,5); WHEN "110010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132278,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191927,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(19,5); WHEN others => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5); END CASE; END PROCESS; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_pos52.vhd	10	6864	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_POS52.VHD * --* * --* Function: 6 Bit Count Leading Zeros * --* Component * --* * --* 22/12/09 ML * --* * --* (c) 2009 Altera Corporation * --* * --* Change History * --* * --* * --* * --************************************************* ENTITY fp_pos52 IS GENERIC (start : integer := 10); PORT ( ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1); position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1) ); END fp_pos52; ARCHITECTURE sss of fp_pos52 IS BEGIN ptab: PROCESS (ingroup) BEGIN CASE ingroup IS WHEN "000000" => position <= conv_std_logic_vector(0,6); WHEN "000001" => position <= conv_std_logic_vector(start+5,6); WHEN "000010" => position <= conv_std_logic_vector(start+4,6); WHEN "000011" => position <= conv_std_logic_vector(start+4,6); WHEN "000100" => position <= conv_std_logic_vector(start+3,6); WHEN "000101" => position <= conv_std_logic_vector(start+3,6); WHEN "000110" => position <= conv_std_logic_vector(start+3,6); WHEN "000111" => position <= conv_std_logic_vector(start+3,6); WHEN "001000" => position <= conv_std_logic_vector(start+2,6); WHEN "001001" => position <= conv_std_logic_vector(start+2,6); WHEN "001010" => position <= conv_std_logic_vector(start+2,6); WHEN "001011" => position <= conv_std_logic_vector(start+2,6); WHEN "001100" => position <= conv_std_logic_vector(start+2,6); WHEN "001101" => position <= conv_std_logic_vector(start+2,6); WHEN "001110" => position <= conv_std_logic_vector(start+2,6); WHEN "001111" => position <= conv_std_logic_vector(start+2,6); WHEN "010000" => position <= conv_std_logic_vector(start+1,6); WHEN "010001" => position <= conv_std_logic_vector(start+1,6); WHEN "010010" => position <= conv_std_logic_vector(start+1,6); WHEN "010011" => position <= conv_std_logic_vector(start+1,6); WHEN "010100" => position <= conv_std_logic_vector(start+1,6); WHEN "010101" => position <= conv_std_logic_vector(start+1,6); WHEN "010110" => position <= conv_std_logic_vector(start+1,6); WHEN "010111" => position <= conv_std_logic_vector(start+1,6); WHEN "011000" => position <= conv_std_logic_vector(start+1,6); WHEN "011001" => position <= conv_std_logic_vector(start+1,6); WHEN "011010" => position <= conv_std_logic_vector(start+1,6); WHEN "011011" => position <= conv_std_logic_vector(start+1,6); WHEN "011100" => position <= conv_std_logic_vector(start+1,6); WHEN "011101" => position <= conv_std_logic_vector(start+1,6); WHEN "011110" => position <= conv_std_logic_vector(start+1,6); WHEN "011111" => position <= conv_std_logic_vector(start+1,6); WHEN "100000" => position <= conv_std_logic_vector(start,6); WHEN "100001" => position <= conv_std_logic_vector(start,6); WHEN "100010" => position <= conv_std_logic_vector(start,6); WHEN "100011" => position <= conv_std_logic_vector(start,6); WHEN "100100" => position <= conv_std_logic_vector(start,6); WHEN "100101" => position <= conv_std_logic_vector(start,6); WHEN "100110" => position <= conv_std_logic_vector(start,6); WHEN "100111" => position <= conv_std_logic_vector(start,6); WHEN "101000" => position <= conv_std_logic_vector(start,6); WHEN "101001" => position <= conv_std_logic_vector(start,6); WHEN "101010" => position <= conv_std_logic_vector(start,6); WHEN "101011" => position <= conv_std_logic_vector(start,6); WHEN "101100" => position <= conv_std_logic_vector(start,6); WHEN "101101" => position <= conv_std_logic_vector(start,6); WHEN "101110" => position <= conv_std_logic_vector(start,6); WHEN "101111" => position <= conv_std_logic_vector(start,6); WHEN "110000" => position <= conv_std_logic_vector(start,6); WHEN "110001" => position <= conv_std_logic_vector(start,6); WHEN "110010" => position <= conv_std_logic_vector(start,6); WHEN "110011" => position <= conv_std_logic_vector(start,6); WHEN "110100" => position <= conv_std_logic_vector(start,6); WHEN "110101" => position <= conv_std_logic_vector(start,6); WHEN "110110" => position <= conv_std_logic_vector(start,6); WHEN "110111" => position <= conv_std_logic_vector(start,6); WHEN "111000" => position <= conv_std_logic_vector(start,6); WHEN "111001" => position <= conv_std_logic_vector(start,6); WHEN "111010" => position <= conv_std_logic_vector(start,6); WHEN "111011" => position <= conv_std_logic_vector(start,6); WHEN "111100" => position <= conv_std_logic_vector(start,6); WHEN "111101" => position <= conv_std_logic_vector(start,6); WHEN "111110" => position <= conv_std_logic_vector(start,6); WHEN "111111" => position <= conv_std_logic_vector(start,6); WHEN others => position <= conv_std_logic_vector(0,6); END CASE; END PROCESS; END sss;	mit
Reiuiji/ECE368-Lab	Lab 1/MealyFSM/mealy-testbench.vhd	1	2187	--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2016 -- Module Name: MEALY TestBench -- Project Name: MEALY MACHINE -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: Mealy -- Finite State Machine (FSM) -- Mealy: The Output is a function of a present -- state and inputs --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; entity mealy_tb is end mealy_tb; architecture io_test of mealy_tb is component mealy port ( CLK: in BIT; RST: in BIT; X: in BIT; Z: out BIT); end component; signal CLK_TEST: BIT := '0'; signal RESET_TEST: BIT := '0'; signal X_IN_TEST: BIT := '0'; signal Z_OUT_TEST: BIT; -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 begin -- Instantiate the Unit Under Testing (UUT) uut: mealy port map( CLK => CLK_TEST, RST => RESET_TEST, X => X_IN_TEST, Z => Z_OUT_TEST ); --Another Method of Port Map --uut: mealy port map(CLK_TEST,RESET_TEST,X_IN_TEST,Z_OUT_TEST); CLK_Process: process begin CLK_TEST <= '0'; wait for period; CLK_TEST <= '1'; wait for period; end process CLK_Process; tb : process begin wait for 100 ns; report "Starting mealy Test Bench" severity NOTE; ----- Unit Test ----- --Reset RESET_TEST <= '1'; wait for period; RESET_TEST <= '0'; wait for period; X_IN_TEST <= '0'; wait for 50 ns; X_IN_TEST <= '1'; wait for 90 ns; X_IN_TEST <= '0'; wait for 130 ns; X_IN_TEST <= '0'; wait for 170 ns; X_IN_TEST <= '1'; wait for 210 ns; X_IN_TEST <= '1'; wait for 250 ns; X_IN_TEST <= '0'; end process; end;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/math_package.vhd	20	16832	-- (C) 2010 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_LIBRARY_PACKAGE.VHD * --* * --* Function: Component Declarations of * --* compiler instantiated library functions * --* * --* 06/02/08 ML * --* * --* Change History * --* * --* * --* * --* * --* * --*********************************************** PACKAGE math_package IS --******************************* --* SINGLE PRECISION COMPONENTS * --******************************* component fp_inv GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component fp_invsqr GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component fp_sqr PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component fp_exp GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); end component; component fp_log GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component fp_ldexp PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component fp_fabs PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component fp_neg PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component fp_sin GENERIC ( device : integer := 0; width : positive := 30; depth : positive := 18; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_cos GENERIC ( device : integer := 0; width : positive := 30; depth : positive := 18; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_tan PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_asin GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_acos GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_atan PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; --******************************* --* DOUBLE PRECISION COMPONENTS * --********************************* component dp_inv GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component dp_invsqr GENERIC ( doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component dp_sqr PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component dp_exp GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); end component; component dp_log GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_ldexp PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component dp_fabs PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component dp_neg PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component dp_fixfloat IS GENERIC ( unsigned : integer := 0; -- unsigned = 0, signed = 1 decimal : integer := 18; fractional : integer := 14; precision : integer := 0; -- single = 0, double = 1 speed : integer := 0 -- low speed = 0, high speed = 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1); sign : OUT STD_LOGIC; exponent : OUT STD_LOGIC_VECTOR (8+3precision DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23+29precision DOWNTO 1) ); END component; component dp_floatfix IS GENERIC ( unsigned : integer := 1; -- unsigned = 0, signed = 1 decimal : integer := 14; fractional : integer := 6; precision : integer := 0; -- single = 0, double = 1 speed : integer := 0 -- low speed = 0, high speed = 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; sign : IN STD_LOGIC; exponent : IN STD_LOGIC_VECTOR (8+3precision DOWNTO 1); mantissa : IN STD_LOGIC_VECTOR (23+29precision DOWNTO 1); fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1) ); END component; END math_package;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_rsftcomb64.vhd	10	4574	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_RSFTCOMB64.VHD * --* * --* Function: Combinatorial arithmetic right * --* shift for a 64 bit number * --* * --* 14/07/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY hcc_rsftcomb64 IS PORT ( inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); END hcc_rsftcomb64; ARCHITECTURE rtl OF hcc_rsftcomb64 IS signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1); BEGIN levzip <= inbus; -- shift by 0,1,2,3 gaa: FOR k IN 1 TO 61 GENERATE levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR (levzip(k+2) AND shift(2) AND NOT(shift(1))) OR (levzip(k+3) AND shift(2) AND shift(1)); END GENERATE; levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(63) AND NOT(shift(2)) AND shift(1)) OR (levzip(64) AND shift(2)); levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(64) AND ((shift(2)) OR shift(1))); levone(64) <= levzip(64); -- shift by 0,4,8,12 gba: FOR k IN 1 TO 52 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k+4) AND NOT(shift(4)) AND shift(3)) OR (levone(k+8) AND shift(4) AND NOT(shift(3))) OR (levone(k+12) AND shift(4) AND shift(3)); END GENERATE; gbb: FOR k IN 53 TO 56 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k+4) AND NOT(shift(4)) AND shift(3)) OR (levone(k+8) AND shift(4) AND NOT(shift(3))) OR (levone(64) AND shift(4) AND shift(3)); END GENERATE; gbc: FOR k IN 57 TO 60 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k+4) AND NOT(shift(4)) AND shift(3)) OR (levone(64) AND shift(4)); END GENERATE; gbd: FOR k IN 61 TO 63 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(64) AND (shift(4) OR shift(3))); END GENERATE; levtwo(64) <= levone(64); gca: FOR k IN 1 TO 16 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR (levtwo(k+48) AND shift(6) AND shift(5)); END GENERATE; gcb: FOR k IN 17 TO 32 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR (levtwo(64) AND shift(6) AND shift(5)); END GENERATE; gcc: FOR k IN 33 TO 48 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(64) AND shift(6) ); END GENERATE; gcd: FOR k IN 49 TO 63 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(64) AND (shift(6) OR shift(5))); END GENERATE; levthr(64) <= levtwo(64); outbus <= levthr; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_lnlutpow.vhd	10	19605	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_LNLUTPOW.VHD * --* * --* Function: Look Up Table - LN() * --* * --* Generated by MATLAB Utility * --* * --* 22/02/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY fp_lnlutpow IS PORT ( add : IN STD_LOGIC_VECTOR (7 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_lnlutpow; ARCHITECTURE rtl OF fp_lnlutpow IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000" => logman <= conv_std_logic_vector(0,23); logexp <= conv_std_logic_vector(0,8); WHEN "0000001" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(126,8); WHEN "0000010" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(127,8); WHEN "0000011" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(128,8); WHEN "0000100" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(128,8); WHEN "0000101" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(128,8); WHEN "0000110" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(129,8); WHEN "0000111" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001001" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001010" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001011" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001100" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(130,8); WHEN "0001101" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(130,8); WHEN "0001110" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(130,8); WHEN "0001111" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010001" => logman <= conv_std_logic_vector(3967289,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010010" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010011" => logman <= conv_std_logic_vector(5420924,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010100" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010101" => logman <= conv_std_logic_vector(6874559,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010110" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010111" => logman <= conv_std_logic_vector(8328194,23); logexp <= conv_std_logic_vector(130,8); WHEN "0011000" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011001" => logman <= conv_std_logic_vector(696611,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011010" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011011" => logman <= conv_std_logic_vector(1423428,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011100" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011101" => logman <= conv_std_logic_vector(2150246,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011110" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011111" => logman <= conv_std_logic_vector(2877063,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100001" => logman <= conv_std_logic_vector(3603881,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100010" => logman <= conv_std_logic_vector(3967289,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100011" => logman <= conv_std_logic_vector(4330698,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100100" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100101" => logman <= conv_std_logic_vector(5057516,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100110" => logman <= conv_std_logic_vector(5420924,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100111" => logman <= conv_std_logic_vector(5784333,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101000" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101001" => logman <= conv_std_logic_vector(6511151,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101010" => logman <= conv_std_logic_vector(6874559,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101011" => logman <= conv_std_logic_vector(7237968,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101100" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101101" => logman <= conv_std_logic_vector(7964786,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101110" => logman <= conv_std_logic_vector(8328194,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101111" => logman <= conv_std_logic_vector(151498,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110000" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110001" => logman <= conv_std_logic_vector(514906,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110010" => logman <= conv_std_logic_vector(696611,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110011" => logman <= conv_std_logic_vector(878315,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110100" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110101" => logman <= conv_std_logic_vector(1241724,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110110" => logman <= conv_std_logic_vector(1423428,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110111" => logman <= conv_std_logic_vector(1605133,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111000" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111001" => logman <= conv_std_logic_vector(1968541,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111010" => logman <= conv_std_logic_vector(2150246,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111011" => logman <= conv_std_logic_vector(2331950,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111100" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111101" => logman <= conv_std_logic_vector(2695359,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111110" => logman <= conv_std_logic_vector(2877063,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111111" => logman <= conv_std_logic_vector(3058768,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000001" => logman <= conv_std_logic_vector(3422176,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000010" => logman <= conv_std_logic_vector(3603881,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000011" => logman <= conv_std_logic_vector(3785585,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000100" => logman <= conv_std_logic_vector(3967289,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000101" => logman <= conv_std_logic_vector(4148994,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000110" => logman <= conv_std_logic_vector(4330698,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000111" => logman <= conv_std_logic_vector(4512403,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001000" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001001" => logman <= conv_std_logic_vector(4875811,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001010" => logman <= conv_std_logic_vector(5057516,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001011" => logman <= conv_std_logic_vector(5239220,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001100" => logman <= conv_std_logic_vector(5420924,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001101" => logman <= conv_std_logic_vector(5602629,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001110" => logman <= conv_std_logic_vector(5784333,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001111" => logman <= conv_std_logic_vector(5966038,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010000" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010001" => logman <= conv_std_logic_vector(6329446,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010010" => logman <= conv_std_logic_vector(6511151,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010011" => logman <= conv_std_logic_vector(6692855,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010100" => logman <= conv_std_logic_vector(6874559,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010101" => logman <= conv_std_logic_vector(7056264,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010110" => logman <= conv_std_logic_vector(7237968,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010111" => logman <= conv_std_logic_vector(7419673,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011000" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011001" => logman <= conv_std_logic_vector(7783081,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011010" => logman <= conv_std_logic_vector(7964786,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011011" => logman <= conv_std_logic_vector(8146490,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011100" => logman <= conv_std_logic_vector(8328194,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011101" => logman <= conv_std_logic_vector(60645,23); logexp <= conv_std_logic_vector(133,8); WHEN "1011110" => logman <= conv_std_logic_vector(151498,23); logexp <= conv_std_logic_vector(133,8); WHEN "1011111" => logman <= conv_std_logic_vector(242350,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100000" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100001" => logman <= conv_std_logic_vector(424054,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100010" => logman <= conv_std_logic_vector(514906,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100011" => logman <= conv_std_logic_vector(605759,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100100" => logman <= conv_std_logic_vector(696611,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100101" => logman <= conv_std_logic_vector(787463,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100110" => logman <= conv_std_logic_vector(878315,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100111" => logman <= conv_std_logic_vector(969167,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101000" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101001" => logman <= conv_std_logic_vector(1150872,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101010" => logman <= conv_std_logic_vector(1241724,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101011" => logman <= conv_std_logic_vector(1332576,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101100" => logman <= conv_std_logic_vector(1423428,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101101" => logman <= conv_std_logic_vector(1514280,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101110" => logman <= conv_std_logic_vector(1605133,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101111" => logman <= conv_std_logic_vector(1695985,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110000" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110001" => logman <= conv_std_logic_vector(1877689,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110010" => logman <= conv_std_logic_vector(1968541,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110011" => logman <= conv_std_logic_vector(2059394,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110100" => logman <= conv_std_logic_vector(2150246,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110101" => logman <= conv_std_logic_vector(2241098,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110110" => logman <= conv_std_logic_vector(2331950,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110111" => logman <= conv_std_logic_vector(2422802,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111000" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111001" => logman <= conv_std_logic_vector(2604507,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111010" => logman <= conv_std_logic_vector(2695359,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111011" => logman <= conv_std_logic_vector(2786211,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111100" => logman <= conv_std_logic_vector(2877063,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111101" => logman <= conv_std_logic_vector(2967915,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111110" => logman <= conv_std_logic_vector(3058768,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111111" => logman <= conv_std_logic_vector(3149620,23); logexp <= conv_std_logic_vector(133,8); WHEN others => logman <= conv_std_logic_vector(0,23); logexp <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_delay.vhd	10	3399	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_DELAY.VHD * --* * --* Function: Delay an arbitrary width an * --* arbitrary number of stages * --* * --* 14/07/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY hcc_delay IS GENERIC ( width : positive := 32; delay : positive := 10; synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delay; ARCHITECTURE rtl OF hcc_delay IS type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1); signal delmemff : delmemfftype; signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1); component hcc_delmem GENERIC ( width : positive := 64; delay : positive := 18 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gda: IF (delay = 1) GENERATE pone: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delinff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delinff <= aa; END IF; END IF; END PROCESS; cc <= delinff; END GENERATE; gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE ptwo: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR j IN 1 TO delay LOOP FOR k IN 1 TO width LOOP delmemff(j)(k) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delmemff(1)(width DOWNTO 1) <= aa; FOR k IN 2 TO delay LOOP delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1); END LOOP; END IF; END IF; END PROCESS; cc <= delmemff(delay)(width DOWNTO 1); END GENERATE; gdc: IF (delay > 4 AND synthesize = 1) GENERATE core: hcc_delmem GENERIC MAP (width=>width,delay=>delay) PORT MAP (sysclk=>sysclk,enable=>enable, aa=>aa,cc=>cc); END GENERATE; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_del.vhd	10	3579	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_DEL.VHD * --* * --* Function: Generic Bus Delay * --* * --* 31/01/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY fp_del IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del; ARCHITECTURE rtl OF fp_del IS component fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_del_var IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN genone: IF (pipes = 1) GENERATE delone: fp_del_one GENERIC MAP (width=>width) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; genvar: IF (pipes > 1) GENERATE delvar: fp_del_var GENERIC MAP (width=>width,pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp1x_sv.vhd	10	12224	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_NORMFP1X.VHD * --* * --* Function: Normalize single precision * --* number * --* * --* 14/07/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* 28/12/07 - divider target uses all of * --* mantissa width * --* 06/02/08 - fix divider norm * --* 21/03/08 - fix add tree output norm * --* 16/04/09 - add NAN support * --* 08/11/10 - +0,-0 mantissa case * --* * --*********************************************** --*********************************************** --* LATENCY : * --*********************************************** --*********************************************** --* NOTES: * --* normalize signed numbers (x input format) * --* for 1x multipliers * --* format signed32/36 bit mantissa and 10 bit * --* exponent * --* unsigned numbers for divider (S,1,23 bit * --* mantissa for divider) divider packed into * --* 32/36bit mantissa + exponent * --*********************************************** ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip, aanan : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip, ccnan : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff, aananff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal maximumnumberff : STD_LOGIC; signal zeroexponent, zeroexponentff : STD_LOGIC; signal exponentmiddle : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aasatdelff, aazipdelff, aanandelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --**************************************************** --* scale multiplier * --* multiplier format [S][1][mantissa....] * --* one clock latency * --**************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; aananff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; aananff <= aanan; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; ccnan <= aananff; END GENERATE; --**************************************************** --* full normalization of input - 4 stages * --* unlike double, no round required on output, as * --* no information lost * --**************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; maximumnumberff <= '0'; zeroexponentff <= '0'; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; aanandelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exponentmiddle; expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); -- 08/11/09 maximumnumberff <= aaff(mantissa+10) XOR aaff(mantissa+9); zeroexponentff <= zeroexponent; aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; aanandelff(1) <= aanan; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); aanandelff(k) <= aanandelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 -- 08/11/10 - also where exponentmiddle is used -- '1' if true : if countsign 0, then "111...111" (-0) or "000...000" (+0) case, zero exponent output zeroexponent <= NOT(countsign(6) OR countsign(5) OR countsign(4) OR countsign(3) OR countsign(2) OR countsign(1) OR maximumnumberff); gen_exp_mid: FOR k IN 1 TO 10 GENERATE exponentmiddle(k) <= exptopff(2)(k) AND NOT(zeroexponentff); END GENERATE; gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --* OUTPUTS * ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); ccnan <= aanandelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --* OUTPUTS * ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exponentmiddle; END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); ccnan <= aanandelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --* OUTPUTS * gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exponentmiddle; END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); ccnan <= aanandelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --* DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/fp_cordic_start1.vhd	10	3284	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_CORDIC_START1.VHD * --* * --* Function: Table for Initial Value of X * --* for SIN and COS CORDIC Core * --* * --* 22/12/09 ML * --* * --* (c) 2009 Altera Corporation * --* * --* Change History * --* * --* * --* * --************************************************* ENTITY fp_cordic_start1 IS GENERIC (width : positive := 36); PORT ( index : IN STD_LOGIC_VECTOR (4 DOWNTO 1); value : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_cordic_start1; ARCHITECTURE rtl of fp_cordic_start1 IS signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1); BEGIN pva: PROCESS (index) BEGIN CASE index IS WHEN "0000" => valuenode <= x"26DD3B6A1"; WHEN "0001" => valuenode <= x"36F656C5A"; WHEN "0010" => valuenode <= x"3D731DFFB"; WHEN "0011" => valuenode <= x"3F5743B24"; WHEN "0100" => valuenode <= x"3FD574860"; WHEN "0101" => valuenode <= x"3FF557499"; WHEN "0110" => valuenode <= x"3FFD5574A"; WHEN "0111" => valuenode <= x"3FFF55575"; WHEN "1000" => valuenode <= x"3FFFD5557"; WHEN "1001" => valuenode <= x"3FFFF5555"; WHEN "1010" => valuenode <= x"3FFFFD555"; WHEN "1011" => valuenode <= x"3FFFFF555"; WHEN "1101" => valuenode <= x"3FFFFFD55"; WHEN "1100" => valuenode <= x"3FFFFFF55"; WHEN "1111" => valuenode <= x"3FFFFFFD5"; WHEN "1110" => valuenode <= x"3FFFFFFF5"; WHEN others => valuenode <= x"000000000"; END CASE; END PROCESS; value <= valuenode (36 DOWNTO 37-width); END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	Gaussian_Filter/ip/Gaussian_Filter/dp_addb.vhd	10	2971	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* DOUBLE PRECISION CORE LIBRARY * --* * --* DP_ADDB.VHD * --* * --* Function: Behavioral Fixed Point Adder * --* * --* 31/01/08 ML * --* * --* (c) 2008 Altera Corporation * --* * --* Change History * --* * --* * --* * --* * --* * --************************************************* ENTITY dp_addb IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END dp_addb; ARCHITECTURE rtl OF dp_addb IS type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1); signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); signal pipeff : pipefftype; signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1); BEGIN gza: FOR k IN 1 TO width-1 GENERATE zerovec(k) <= '0'; END GENERATE; ccnode <= aa + bb + (zerovec & carryin); gda: IF (pipes = 1) GENERATE pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff <= ccnode; END IF; END IF; END PROCESS; cc <= delff; END GENERATE; gpa: IF (pipes > 1) GENERATE ppa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO pipes LOOP FOR j IN 1 TO width LOOP pipeff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN pipeff(1)(width DOWNTO 1) <= ccnode; FOR k IN 2 TO pipes LOOP pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1); END LOOP; END IF; END IF; END PROCESS; cc <= pipeff(pipes)(width DOWNTO 1); END GENERATE; END rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp2x_sv.vhd	10	15740	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* ALTERA FLOATING POINT DATAPATH COMPILER * --* * --* HCC_NORMFP2X.VHD * --* * --* Function: Normalize double precision * --* number * --* * --* 14/07/07 ML * --* * --* (c) 2007 Altera Corporation * --* * --* Change History * --* * --* 05/03/08 - correct expbotffdepth constant * --* 20/04/09 - add NAN support, add overflow * --* check in target=0 code * --* * --* * --************************************************* ENTITY hcc_normfp2x IS GENERIC ( roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' roundnormalize : integer := 1; -- global switch - round all normalizations when '1' normspeed : positive := 3; -- 1,2, or 3 pipes for norm core doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles target : integer := 1; -- 1(internal), 0 (multiplier, divider) synthesize : integer := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip, aanan : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (67+10target DOWNTO 1); ccsat, cczip, ccnan : OUT STD_LOGIC ); END hcc_normfp2x; ARCHITECTURE rtl OF hcc_normfp2x IS constant latency : positive := 3 + normspeed + (roundconvertdoublespeed) + (roundnormalize + roundnormalizedoublespeed); constant exptopffdepth : positive := 2 + roundconvertdoublespeed; constant expbotffdepth : positive := normspeed + roundnormalize(1+doublespeed); -- 05/03/08 -- if internal format, need to turn back to signed at this point constant invertpoint : positive := 1 + normspeed + (roundconvertdoublespeed); type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1); type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1); signal exptopff : exptopfftype; signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1); signal expbotdelff : expbotfftype; signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1); signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1); signal aasatff, aazipff, aananff : STD_LOGIC_VECTOR (latency DOWNTO 1); signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1); signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1); signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1); signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normalaaff : STD_LOGIC_VECTOR (55+9target DOWNTO 1); signal overflowbitnode : STD_LOGIC_VECTOR (55 DOWNTO 1); signal overflowcondition : STD_LOGIC; signal overflowconditionff : STD_LOGIC; signal mantissa : STD_LOGIC_VECTOR (54+10target DOWNTO 1); signal aamannode : STD_LOGIC_VECTOR (54+10target DOWNTO 1); signal aamanff : STD_LOGIC_VECTOR (54+10target DOWNTO 1); signal sign : STD_LOGIC; component hcc_addpipeb GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component hcc_addpipes GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component hcc_normus64 IS GENERIC (pipes : positive := 1); -- currently 1 or 3 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO 64 GENERATE zerovec(k) <= '0'; END GENERATE; --* INPUT REGISTER * pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 77 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO exptopffdepth LOOP FOR j IN 1 TO 13 LOOP exptopff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO latency LOOP aasatff(k) <= '0'; aazipff(k) <= '0'; END LOOP; FOR k IN 1 TO latency-1 LOOP mulsignff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp; FOR k IN 2 TO exptopffdepth LOOP exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1); END LOOP; aasatff(1) <= aasat; aazipff(1) <= aazip; aananff(1) <= aanan; FOR k IN 2 TO latency LOOP aasatff(k) <= aasatff(k-1); aazipff(k) <= aazipff(k-1); aananff(k) <= aananff(k-1); END LOOP; mulsignff(1) <= aaff(77); FOR k IN 2 TO latency-1 LOOP mulsignff(k) <= mulsignff(k-1); END LOOP; END IF; END IF; END PROCESS; -- exponent bottom half gxa: IF (expbotffdepth = 1) GENERATE pxa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 13 LOOP expbotff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm); END IF; END IF; END PROCESS; exponent <= expbotff; END GENERATE; gxb: IF (expbotffdepth = 2) GENERATE pxb: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 2 LOOP FOR j IN 1 TO 13 LOOP expbotdelff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm); expbotdelff(2)(13 DOWNTO 1) <= expbotdelff(1)(13 DOWNTO 1) + ("000000000000" & overflowcondition); END IF; END IF; END PROCESS; exponent <= expbotdelff(2)(13 DOWNTO 1); END GENERATE; gxc: IF (expbotffdepth > 2) GENERATE pxb: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO expbotffdepth LOOP FOR j IN 1 TO 13 LOOP expbotdelff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm); FOR k IN 2 TO expbotffdepth-1 LOOP expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1); END LOOP; expbotdelff(expbotffdepth)(13 DOWNTO 1) <= expbotdelff(expbotffdepth-1)(13 DOWNTO 1) + ("000000000000" & overflowcondition); END IF; END IF; END PROCESS; exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1); END GENERATE; -- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets adjustexp <= "0000000000100"; gna: FOR k IN 1 TO 64 GENERATE aainvnode(k) <= aaff(k+13) XOR aaff(77); END GENERATE; --* APPLY ROUNDING TO ABS VALUE (IF REQUIRED) * gnb: IF ((roundconvert = 0) OR (roundconvert = 1 AND doublespeed = 0)) GENERATE gnc: IF (roundconvert = 0) GENERATE aaabsnode <= aainvnode; END GENERATE; gnd: IF (roundconvert = 1) GENERATE aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77)); END GENERATE; pnb: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP aaabsff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaabsff <= aaabsnode; END IF; END IF; END PROCESS; aaabs <= aaabsff; END GENERATE; gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE gsa: IF (synthesize = 0) GENERATE absone: hcc_addpipeb GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aainvnode,bb=>zerovec,carryin=>aaff(77), cc=>aaabs); END GENERATE; gsb: IF (synthesize = 1) GENERATE abstwo: hcc_addpipes GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aainvnode,bb=>zerovec,carryin=>aaff(77), cc=>aaabs); END GENERATE; END GENERATE; --* NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) normcore: hcc_normus64 GENERIC MAP (pipes=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaabs, countout=>countnorm,fracout=>normalaa); gta: IF (target = 0) GENERATE pnc: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 54 LOOP normalaaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN normalaaff <= normalaa(64 DOWNTO 10); END IF; END IF; END PROCESS; --* ROUND NORMALIZED VALUE (IF REQUIRED)* --* note: normal output is 64 bits gne: IF (roundnormalize = 0) GENERATE mantissa <= normalaaff(55 DOWNTO 2); overflowcondition <= '0'; -- 20/05/09 used in exponent calculation END GENERATE; gnf: IF (roundnormalize = 1) GENERATE overflowbitnode(1) <= normalaaff(1); gova: FOR k IN 2 TO 55 GENERATE overflowbitnode(k) <= overflowbitnode(k-1) AND normalaaff(k); END GENERATE; gng: IF (doublespeed = 0) GENERATE overflowcondition <= overflowbitnode(55); aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1)); pnd: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 54 LOOP aamanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aamanff <= aamannode; END IF; END IF; END PROCESS; mantissa <= aamanff; END GENERATE; gnh: IF (doublespeed = 1) GENERATE pne: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN overflowconditionff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN overflowconditionff <= overflowbitnode(55); END IF; END IF; END PROCESS; overflowcondition <= overflowconditionff; gra: IF (synthesize = 0) GENERATE rndone: hcc_addpipeb GENERIC MAP (width=>54,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1), cc=>mantissa); END GENERATE; grb: IF (synthesize = 1) GENERATE rndtwo: hcc_addpipes GENERIC MAP (width=>54,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1), cc=>mantissa); END GENERATE; END GENERATE; END GENERATE; sign <= mulsignff(latency-1); cc <= sign & (mantissa(54) OR mantissa(53)) & mantissa(52 DOWNTO 1) & exponent; ccsat <= aasatff(latency); cczip <= aazipff(latency); ccnan <= aananff(latency); END GENERATE; gtb: IF (target = 1) GENERATE -- overflow cannot happen here, dont insert overflowcondition <= '0'; -- 20/05/09 used for exponent pnf: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP normalaaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO 59 LOOP normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint); END LOOP; normalaaff(60) <= mulsignff(invertpoint); normalaaff(61) <= mulsignff(invertpoint); normalaaff(62) <= mulsignff(invertpoint); normalaaff(63) <= mulsignff(invertpoint); normalaaff(64) <= mulsignff(invertpoint); END IF; END IF; END PROCESS; gni: IF (roundnormalize = 0) GENERATE mantissa <= normalaaff; -- 1's complement END GENERATE; gnj: IF (roundnormalize = 1) GENERATE gnk: IF (doublespeed = 0) GENERATE aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1)); png: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP aamanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aamanff <= aamannode; END IF; END IF; END PROCESS; mantissa <= aamanff; END GENERATE; gnl: IF (doublespeed = 1) GENERATE grc: IF (synthesize = 0) GENERATE rndone: hcc_addpipeb GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1), cc=>mantissa); END GENERATE; grd: IF (synthesize = 1) GENERATE rndtwo: hcc_addpipes GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1), cc=>mantissa); END GENERATE; END GENERATE; END GENERATE; cc <= mantissa(64 DOWNTO 1) & exponent; ccsat <= aasatff(latency); cczip <= aazipff(latency); ccnan <= aananff(latency); END GENERATE; end rtl;	mit
Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC	bin_Gaussian_Filter/ip/Gaussian_Filter/fp_sin.vhd	10	14482	-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --************************************************* --* * --* FLOATING POINT CORE LIBRARY * --* * --* FP_SIN.VHD * --* * --* Function: Single Precision SIN Core * --* * --* 10/01/10 ML * --* * --* (c) 2010 Altera Corporation * --* * --* Change History * --* * --* * --* * --*********************************************** --*********************************************** --* Notes: * --* 1. Input < 0.5 radians, take cos(pi/2-input)* --* 2. latency = depth + range_depth (11) + 7 * --* (1 more than cos) * --*********************************************** ENTITY fp_sin IS GENERIC ( device : integer := 0; width : positive := 30; depth : positive := 18; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); END fp_sin; ARCHITECTURE rtl of fp_sin IS constant cordic_width : positive := width; constant cordic_depth : positive := depth; constant range_depth : positive := 11; signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1); signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1); signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1); -- range reduction signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1); signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1); signal quadrantsign, quadrantselect : STD_LOGIC; signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1); signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1); signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1); signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1); -- circle to radians mult signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1); signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1); signal indexbit : STD_LOGIC; signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1); signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1); signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1); signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1); signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1); signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1); signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1); signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1); signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1); signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1); signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1); signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal signoutff : STD_LOGIC; component fp_range1 GENERIC (device : integer); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1); negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_cordic_m1 GENERIC ( width : positive := 36; depth : positive := 20; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1] indexbit : IN STD_LOGIC; sincosbit : IN STD_LOGIC; sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_clz36 IS PORT ( mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1); leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1) ); end component; component fp_lsft36 IS PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_fxmul GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_del IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN -- pi/2 = 1.57 piovertwo <= x"c90fdaa22"; zerovec <= x"000000000"; --* SIN(X) = X when exponent < 115 * input_number <= signin & exponentin & mantissain; -- level 1 in, level range_depth+cordic_depth+7 out cdin: fp_del GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>input_number, cc=>input_number_delay); --* RANGE REDUCTION *** crr: fp_range1 GENERIC MAP(device=>device) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signin,exponentin=>exponentin,mantissain=>mantissain, circle=>circle,negcircle=>negcircle); quadrantsign <= circle(36); -- sin negative in quadrants 3&4 quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4 gra: FOR k IN 1 TO 34 GENERATE quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR (negcircle(k) AND quadrantselect); END GENERATE; -- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin positive_quadrant <= '0' & quadrant & '0'; gnqa: FOR k IN 1 TO 36 GENERATE negative_quadrant(k) <= NOT(positive_quadrant(k)); fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR (negative_quadrant(k) AND NOT(quadrant(34))); END GENERATE; one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant pfa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO range_depth LOOP signinff(k) <= '0'; END LOOP; FOR k IN 1 TO cordic_depth+6 LOOP signcalcff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP exponentinff(k) <= '0'; END LOOP; FOR k IN 1 TO range_depth+cordic_depth+5 LOOP selectoutputff(k) <= '0'; END LOOP; FOR k IN 1 TO 36 LOOP quadrant_sumff(k) <= '0'; END LOOP; FOR k IN 1 TO 4 LOOP select_sincosff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN signinff(1) <= signin; FOR k IN 2 TO range_depth LOOP signinff(k) <= signinff(k-1); END LOOP; -- level range_depth+1 to range_depth+cordic_depth+6 signcalcff(1) <= quadrantsign XOR signinff(range_depth); FOR k IN 2 TO cordic_depth+6 LOOP signcalcff(k) <= signcalcff(k-1); END LOOP; exponentinff <= exponentin; -- level 1 selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6 FOR k IN 2 TO range_depth+cordic_depth+5 LOOP selectoutputff(k) <= selectoutputff(k-1); END LOOP; -- range 0-0.9999 quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1 -- level range depth+1 to range_depth+4 select_sincosff(1) <= quadrant(34); FOR k IN 2 TO 4 LOOP select_sincosff(k) <= select_sincosff(k-1); END LOOP; END IF; END IF; END PROCESS; -- if exponent < 115, sin = input exponentcheck <= ('0' & exponentinff) - ('0' & x"73"); -- levels range_depth+2,3,4 cmul: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width, pipes=>3,synthesize=>1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>quadrant_sumff,databb=>piovertwo, result=>radiansnode); indexcheck(1) <= radiansnode(cordic_width-1); gica: FOR k IN 2 TO 16 GENERATE indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k); END GENERATE; -- for safety, give an extra bit of space indexbit <= NOT(indexcheck(indexpoint+1)); ccc: fp_cordic_m1 GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, radians=>radiansnode, indexbit=>indexbit, sincosbit=>select_sincosff(4), sincos=>fixed_sincos); gfxa: IF (width < 36) GENERATE fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1); END GENERATE; gfxb: IF (width = 36) GENERATE fixed_sincosnode <= fixed_sincos; END GENERATE; clz: fp_clz36 PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode); sft: fp_lsft36 PORT MAP (inbus=>fixed_sincosff,shift=>countff, outbus=>mantissanormnode); -- maximum sin or cos = 1.0 = 1.0e127 single precision -- 1e128 - 1 (leading one) gives correct number exponentnormnode <= "10000000" - ("00" & countff); overflownode(1) <= mantissanormnode(12); gova: FOR k IN 2 TO 24 GENERATE overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1); END GENERATE; -- OUTPUT poa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 36 LOOP fixed_sincosff(k) <= '0'; END LOOP; countff <= "000000"; FOR k IN 1 TO 23 LOOP mantissanormff(k) <= '0'; mantissaoutff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP exponentnormff(k) <= '0'; exponentoutff(k) <= '0'; END LOOP; signoutff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5 countff <= countnode; -- level range_depth+4+cordic_depth+5 -- level range_depth+cordic_depth+6 mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12); exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24); -- level range_depth+cordic_depth+7 FOR k IN 1 TO 23 LOOP mantissaoutff(k) <= (mantissanormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR (input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5)); END LOOP; FOR k IN 1 TO 8 LOOP exponentoutff(k) <= (exponentnormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR (input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5)); END LOOP; signoutff <= (signcalcff(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR (input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5)); END IF; END IF; END PROCESS; mantissaout <= mantissaoutff; exponentout <= exponentoutff; signout <= signoutff; END rtl;	mit
lfmunoz/vhdl	ip_blocks/sip_router_async_s1d2_x4_b/src/sip_router_async_s1d2_x4_b_stellar_cmd.vhd	1	11535	-------------------------------------------------------------------------------- -- file name : sip_router_async_s1d2_x4_b_stellar_cmd.vhd -- -- author : e. barhorst -- -- company : 4dsp -- -- item : number -- -- units : entity -sip_router_async_s1d2_x4_b_stellar_cmd -- arch_itecture - arch_sip_router_async_s1d2_x4_b_stellar_cmd -- -- language : vhdl -- -------------------------------------------------------------------------------- -- description -- =========== -- -- -- notes: -------------------------------------------------------------------------------- -- -- disclaimer: limited warranty and disclaimer. these designs are -- provided to you as is. 4dsp specifically disclaims any -- implied warranties of merchantability, non-infringement, or -- fitness for a particular purpose. 4dsp does not warrant that -- the functions contained in these designs will meet your -- requirements, or that the operation of these designs will be -- uninterrupted or error free, or that defects in the designs -- will be corrected. furthermore, 4dsp does not warrant or -- make any representations regarding use or the results of the -- use of the designs in terms of correctness, accuracy, -- reliability, or otherwise. -- -- limitation of liability. in no event will 4dsp or its -- licensors be liable for any loss of data, lost profits, cost -- or procurement of substitute goods or services, or for any -- special, incidental, consequential, or indirect damages -- arising from the use or operation of the designs or -- accompanying documentation, however caused and on any theory -- of liability. this limitation will apply even if 4dsp -- has been advised of the possibility of such damage. this -- limitation shall apply not-withstanding the failure of the -- essential purpose of any limited remedies herein. -- -- from -- ver pcb mod date changes -- === ======= ======== ======= -- -- 0.0 0 19-01-2009 new version -- 31-08-2009 added the mailbox input port ---------------------------------------------- -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- specify libraries. -------------------------------------------------------------------------------- library ieee ; use ieee.std_logic_unsigned.all ; use ieee.std_logic_misc.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_1164.all ; -------------------------------------------------------------------------------- -- entity declaration -------------------------------------------------------------------------------- entity sip_router_async_s1d2_x4_b_stellar_cmd is generic ( start_addr :std_logic_vector(27 downto 0):=x"0000000"; stop_addr :std_logic_vector(27 downto 0):=x"0000010" ); port ( reset :in std_logic; --command if clk_cmd :in std_logic; --cmd_in and cmd_out are synchronous to this clock; out_cmd :out std_logic_vector(63 downto 0); out_cmd_val :out std_logic; in_cmd :in std_logic_vector(63 downto 0); in_cmd_val :in std_logic; --register interface clk_reg :in std_logic; --register interface is synchronous to this clock out_reg :out std_logic_vector(31 downto 0);--caries the out register data out_reg_val :out std_logic; --the out_reg has valid data (pulse) out_reg_addr :out std_logic_vector(27 downto 0);--out register address in_reg :in std_logic_vector(31 downto 0);--requested register data is placed on this bus in_reg_val :in std_logic; --pulse to indicate requested register is valid in_reg_req :out std_logic; --pulse to request data in_reg_addr :out std_logic_vector(27 downto 0); --requested address --mailbox interface mbx_out_reg :out std_logic_vector(31 downto 0);--value of the mailbox to send mbx_out_val :out std_logic; mbx_in_reg :in std_logic_vector(31 downto 0);--value of the mailbox to send mbx_in_val :in std_logic --pulse to indicate mailbox is valid ); end entity sip_router_async_s1d2_x4_b_stellar_cmd ; -------------------------------------------------------------------------------- -- arch_itecture declaration -------------------------------------------------------------------------------- architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd of sip_router_async_s1d2_x4_b_stellar_cmd is ----------------------------------------------------------------------------------- --constant declarations ----------------------------------------------------------------------------------- constant cmd_mbx :std_logic_vector(3 downto 0) :=x"0"; constant cmd_rd :std_logic_vector(3 downto 0) :=x"2"; constant cmd_wr :std_logic_vector(3 downto 0) :=x"1"; constant cmd_rd_ack :std_logic_vector(3 downto 0) :=x"4"; ----------------------------------------------------------------------------------- --signal declarations ----------------------------------------------------------------------------------- signal register_wr :std_logic; signal register_rd :std_logic; signal out_cmd_val_sig :std_logic; signal in_reg_addr_sig :std_logic_vector(27 downto 0); signal mbx_in_val_sig :std_logic; signal mbx_received :std_logic; signal mbx_out_val_sig :std_logic; ----------------------------------------------------------------------------------- --component declarations ----------------------------------------------------------------------------------- component pulse2pulse port ( in_clk :in std_logic; out_clk :in std_logic; rst :in std_logic; pulsein :in std_logic; inbusy :out std_logic; pulseout :out std_logic ); end component; begin ----------------------------------------------------------------------------------- --component instantiations ----------------------------------------------------------------------------------- p2p0: pulse2pulse port map ( in_clk =>clk_cmd, out_clk =>clk_reg, rst =>reset, pulsein =>register_wr, inbusy =>open, pulseout =>out_reg_val ); p2p1: pulse2pulse port map ( in_clk =>clk_cmd, out_clk =>clk_reg, rst =>reset, pulsein =>register_rd, inbusy =>open, pulseout =>in_reg_req ); p2p2: pulse2pulse port map ( in_clk =>clk_reg, out_clk =>clk_cmd , rst =>reset, pulsein =>in_reg_val, inbusy =>open, pulseout =>out_cmd_val_sig ); p2p3: pulse2pulse port map ( in_clk =>clk_reg, out_clk =>clk_cmd , rst =>reset, pulsein =>mbx_in_val, inbusy =>open, pulseout =>mbx_in_val_sig ); p2p4: pulse2pulse port map ( in_clk =>clk_cmd, out_clk =>clk_reg , rst =>reset, pulsein =>mbx_out_val_sig, inbusy =>open, pulseout =>mbx_out_val ); ----------------------------------------------------------------------------------- --synchronous processes ----------------------------------------------------------------------------------- in_reg_proc: process(clk_cmd ) begin if(clk_cmd'event and clk_cmd='1') then --register the requested address when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr; end if; --generate the read req pulse when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then register_rd <= '1'; else register_rd <= '0'; end if; --mailbox has less priority then command acknowledge --create the output packet if (out_cmd_val_sig='1' and mbx_in_val_sig='1') then mbx_received <= '1'; elsif( mbx_received ='1' and out_cmd_val_sig = '0') then mbx_received <= '0'; end if; if (out_cmd_val_sig='1') then out_cmd(31 downto 0) <=in_reg; out_cmd(59 downto 32)<=in_reg_addr_sig+start_addr; out_cmd(63 downto 60)<=cmd_rd_ack; elsif (mbx_in_val_sig='1' or mbx_received='1' ) then out_cmd(31 downto 0) <=mbx_in_reg; out_cmd(59 downto 32)<=start_addr; out_cmd(63 downto 60)<=cmd_mbx; else out_cmd(63 downto 0)<=(others=>'0'); end if; if (out_cmd_val_sig='1') then out_cmd_val <= '1'; elsif (mbx_in_val_sig='1' or mbx_received='1' ) then out_cmd_val <= '1'; else out_cmd_val <= '0'; end if; end if; end process; out_reg_proc: process(clk_cmd ) begin if(clk_cmd'event and clk_cmd='1') then --register the requested address when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then out_reg_addr <= in_cmd(59 downto 32)-start_addr; out_reg <= in_cmd(31 downto 0); end if; --generate the write req pulse when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then register_wr <= '1'; else register_wr <= '0'; end if; if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx) then mbx_out_reg <= in_cmd(31 downto 0); end if; if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx ) then mbx_out_val_sig <= '1'; else mbx_out_val_sig <= '0'; end if; end if; end process; ----------------------------------------------------------------------------------- --asynchronous processes ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --asynchronous mapping ----------------------------------------------------------------------------------- in_reg_addr <= in_reg_addr_sig; end architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd ; -- of sip_router_async_s1d2_x4_b_stellar_cmd	mit
lfmunoz/vhdl	types.vhd	1	5888	-- -- Package File Template -- -- Purpose: This package defines supplemental types, subtypes, -- constants, and functions -- -- To use any of the example code shown below, uncomment the lines and modify as necessary -- -- -- -- -- How to use? --note this line.The package is compiled to this directory by default. --so don't forget to include this directory. --library work; --this line also is must.This includes the particular package into your program. --use work.test_pkg.all; -- -- -- -- ---------------------------------------------------------------------------------------------------- -- LIBRARIES ---------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; ---------------------------------------------------------------------------------------------------- -- PACKGE ---------------------------------------------------------------------------------------------------- package types is type bus002 is array(natural range <>) of std_logic_vector( 1 downto 0); type bus004 is array(natural range <>) of std_logic_vector( 3 downto 0); type bus005 is array(natural range <>) of std_logic_vector( 4 downto 0); type bus006 is array(natural range <>) of std_logic_vector( 5 downto 0); type bus007 is array(natural range <>) of std_logic_vector( 6 downto 0); type bus008 is array(natural range <>) of std_logic_vector( 7 downto 0); type bus009 is array(natural range <>) of std_logic_vector( 8 downto 0); type bus010 is array(natural range <>) of std_logic_vector( 9 downto 0); type bus011 is array(natural range <>) of std_logic_vector( 10 downto 0); type bus012 is array(natural range <>) of std_logic_vector( 11 downto 0); type bus013 is array(natural range <>) of std_logic_vector( 12 downto 0); type bus014 is array(natural range <>) of std_logic_vector( 13 downto 0); type bus015 is array(natural range <>) of std_logic_vector( 14 downto 0); type bus016 is array(natural range <>) of std_logic_vector( 15 downto 0); type bus017 is array(natural range <>) of std_logic_vector( 16 downto 0); type bus018 is array(natural range <>) of std_logic_vector( 17 downto 0); type bus019 is array(natural range <>) of std_logic_vector( 18 downto 0); type bus020 is array(natural range <>) of std_logic_vector( 19 downto 0); type bus021 is array(natural range <>) of std_logic_vector( 20 downto 0); type bus022 is array(natural range <>) of std_logic_vector( 21 downto 0); type bus023 is array(natural range <>) of std_logic_vector( 22 downto 0); type bus024 is array(natural range <>) of std_logic_vector( 23 downto 0); type bus025 is array(natural range <>) of std_logic_vector( 24 downto 0); type bus026 is array(natural range <>) of std_logic_vector( 25 downto 0); type bus027 is array(natural range <>) of std_logic_vector( 26 downto 0); type bus028 is array(natural range <>) of std_logic_vector( 27 downto 0); type bus029 is array(natural range <>) of std_logic_vector( 28 downto 0); type bus030 is array(natural range <>) of std_logic_vector( 29 downto 0); type bus031 is array(natural range <>) of std_logic_vector( 30 downto 0); type bus032 is array(natural range <>) of std_logic_vector( 31 downto 0); type bus064 is array(natural range <>) of std_logic_vector( 63 downto 0); type bus128 is array(natural range <>) of std_logic_vector(127 downto 0); type bus256 is array(natural range <>) of std_logic_vector(255 downto 0); -- type <new_type> is -- record -- <type_name> : std_logic_vector( 7 downto 0); -- <type_name> : std_logic; -- end record; -- -- Declare constants -- -- constant <constant_name> : time := <time_unit> ns; -- constant <constant_name> : integer := <value; -- -- Declare functions and procedure -- -- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>; -- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>); -- --************************************************************************************************* end types; --*********************************************************************************************** ---------------------------------------------------------------------------------------------------- -- PACKGE BODY ---------------------------------------------------------------------------------------------------- package body types is function reverse_any_vector (a: in std_logic_vector) return std_logic_vector is variable result: std_logic_vector(a'RANGE); alias aa: std_logic_vector(a'REVERSE_RANGE) is a; begin for i in aa'RANGE loop result(i) := aa(i); end loop; return result; end; ---- Example 1 -- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is -- variable <variable_name> : <type_declaration>; -- begin -- <variable_name> := <signal_name> xor <signal_name>; -- return <variable_name>; -- end <function_name>; ---- Example 2 -- function <function_name> (signal <signal_name> : in <type_declaration>; -- signal <signal_name> : in <type_declaration> ) return <type_declaration> is -- begin -- if (<signal_name> = '1') then -- return <signal_name>; -- else -- return 'Z'; -- end if; -- end <function_name>; ---- Procedure Example -- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is -- -- begin -- -- end <procedure_name>; --********************************************************************************************** end types; --*************************************************************************************************	mit
stanford-ppl/spatial-lang	spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_inst.vhd	1	660	component ghrd_10as066n2_sys_id is port ( clock : in std_logic := 'X'; -- clk readdata : out std_logic_vector(31 downto 0); -- readdata address : in std_logic := 'X'; -- address reset_n : in std_logic := 'X' -- reset_n ); end component ghrd_10as066n2_sys_id; u0 : component ghrd_10as066n2_sys_id port map ( clock => CONNECTED_TO_clock, -- clk.clk readdata => CONNECTED_TO_readdata, -- control_slave.readdata address => CONNECTED_TO_address, -- .address reset_n => CONNECTED_TO_reset_n -- reset.reset_n );	mit
hubertokf/VHDL-Fast-Adders	CLAH/CLA2bits/8bits/CLAH8bits/CLA2bits.vhd	4	760	LIBRARY Ieee; USE ieee.std_logic_1164.all; ENTITY CLA2bits IS PORT ( val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0); SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); CarryIn: IN STD_LOGIC; CarryOut: OUT STD_LOGIC; P, G: OUT STD_LOGIC ); END CLA2bits; ARCHITECTURE strc_cla2bits of CLA2bits is SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN -- soma dos valores e propagação do carry -- Sum<=val1 xor val2; Prop<=val1 or val2; Gen<=val1 and val2; PROCESS (Gen,Prop,Carry) BEGIN Carry(1) <= Gen(0) OR (Prop(0) AND CarryIn); END PROCESS; SomaResult(0) <= Sum(0) XOR CarryIn; SomaResult(1) <= Sum(1) XOR Carry(1); P <= Prop(1) AND Prop(0); G <= Gen(1) OR (Prop(1) AND Gen(0)); END strc_cla2bits;	mit
stanford-ppl/spatial-lang	spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_inst.vhd	1	2111	component ghrd_10as066n2_f2sdram0_m is port ( clk_clk : in std_logic := 'X'; -- clk clk_reset_reset : in std_logic := 'X'; -- reset master_address : out std_logic_vector(31 downto 0); -- address master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata master_read : out std_logic; -- read master_write : out std_logic; -- write master_writedata : out std_logic_vector(31 downto 0); -- writedata master_waitrequest : in std_logic := 'X'; -- waitrequest master_readdatavalid : in std_logic := 'X'; -- readdatavalid master_byteenable : out std_logic_vector(3 downto 0); -- byteenable master_reset_reset : out std_logic -- reset ); end component ghrd_10as066n2_f2sdram0_m; u0 : component ghrd_10as066n2_f2sdram0_m port map ( clk_clk => CONNECTED_TO_clk_clk, -- clk.clk clk_reset_reset => CONNECTED_TO_clk_reset_reset, -- clk_reset.reset master_address => CONNECTED_TO_master_address, -- master.address master_readdata => CONNECTED_TO_master_readdata, -- .readdata master_read => CONNECTED_TO_master_read, -- .read master_write => CONNECTED_TO_master_write, -- .write master_writedata => CONNECTED_TO_master_writedata, -- .writedata master_waitrequest => CONNECTED_TO_master_waitrequest, -- .waitrequest master_readdatavalid => CONNECTED_TO_master_readdatavalid, -- .readdatavalid master_byteenable => CONNECTED_TO_master_byteenable, -- .byteenable master_reset_reset => CONNECTED_TO_master_reset_reset -- master_reset.reset );	mit
DE5Amigos/SylvesterTheDE2Bot	DE2Botv3Fall16Main/DAC_BEEP.vhd	1	2398	LIBRARY IEEE; LIBRARY ALTERA_MF; LIBRARY LPM; USE ALTERA_MF.ALTERA_MF_COMPONENTS.ALL; USE LPM.LPM_COMPONENTS.ALL; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DAC_BEEP IS PORT( RESETN : IN STD_LOGIC; FSEL : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DURATION : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CS : IN STD_LOGIC; CLK_32Hz : IN STD_LOGIC; DAC_WCLK : IN STD_LOGIC; DAC_BCLK : IN STD_LOGIC; DAC_DAT : OUT STD_LOGIC ); END DAC_BEEP; ARCHITECTURE a OF DAC_BEEP IS signal timer : std_logic_vector(15 downto 0); signal phase : std_logic_vector(15 downto 0); signal step : std_logic_vector(7 downto 0); signal sounddata : std_logic_vector(15 downto 0); BEGIN -- ROM to hold the waveform SOUND_LUT : altsyncram GENERIC MAP ( lpm_type => "altsyncram", width_a => 16, numwords_a => 512, widthad_a => 9, init_file => "SOUND.mif", intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE" ) PORT MAP ( clock0 => NOT(DAC_WCLK), address_a => phase(10 DOWNTO 2), -- input is angle q_a => sounddata -- output is amplitude ); -- shift register to serialize the data to the DAC DAC_SHIFT : lpm_shiftreg GENERIC MAP ( lpm_direction => "LEFT", lpm_type => "LPM_SHIFTREG", lpm_width => 32 ) PORT MAP ( load => DAC_WCLK, clock => NOT(DAC_BCLK), data => sounddata & sounddata, shiftout => DAC_DAT ); -- process to perform DDS PROCESS(RESETN, CS) BEGIN IF RESETN = '0' THEN phase <= x"0000"; ELSIF RISING_EDGE(DAC_WCLK) THEN IF step = x"00" THEN phase <= x"0000"; ELSE phase <= phase + step; -- increment the phase END IF; END IF; END PROCESS; -- process to catch data from SCOMP and run the timer PROCESS(RESETN, CS, CLK_32Hz) BEGIN IF RESETN = '0' THEN timer <= x"0000"; step <= x"00"; ELSIF CS = '1' THEN timer <= ("000000"&DURATION&"00")-1; -- -1 so that 0 is infinite step <= FSEL; ELSIF RISING_EDGE(CLK_32Hz) THEN IF timer /= x"FFFF" THEN timer <= timer - 1; IF timer = x"0000" THEN step <= x"00"; END IF; END IF; END IF; END PROCESS; END a;	mit
hubertokf/VHDL-Fast-Adders	CLAH/CLA2bits/32bits/CLAH32bits/CLAH32bits.vhd	1	6893	LIBRARY Ieee; USE ieee.std_logic_1164.all; ENTITY CLAH32bits IS PORT ( val1,val2: IN STD_LOGIC_VECTOR(31 DOWNTO 0); CarryIn: IN STD_LOGIC; CarryOut: OUT STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; SomaResult:OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END CLAH32bits; ARCHITECTURE strc_CLAH32bits of CLAH32bits is SIGNAL Cin_sig, Cout_sig: STD_LOGIC; SIGNAL P0_sig, P1_sig, P2_sig, P3_sig, P4_sig, P5_sig, P6_sig, P7_sig, P8_sig, P9_sig, P10_sig, P11_sig, P12_sig, P13_sig, P14_sig, P15_sig: STD_LOGIC; SIGNAL G0_sig, G1_sig, G2_sig, G3_sig, G4_sig, G5_sig, G6_sig, G7_sig, G8_sig, G9_sig, G10_sig, G11_sig, G12_sig, G13_sig, G14_sig, G15_sig: STD_LOGIC; SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig, Cout4_temp_sig, Cout5_temp_sig, Cout6_temp_sig, Cout7_temp_sig: STD_LOGIC; SIGNAL Cout8_temp_sig, Cout9_temp_sig, Cout10_temp_sig, Cout11_temp_sig, Cout12_temp_sig, Cout13_temp_sig, Cout14_temp_sig, Cout15_temp_sig: STD_LOGIC; SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL SomaT1,SomaT2,SomaT3,SomaT4,SomaT5,SomaT6,SomaT7,SomaT8,SomaT9,SomaT10,SomaT11,SomaT12,SomaT13,SomaT14,SomaT15,SomaT16:STD_LOGIC_VECTOR(1 DOWNTO 0); Component CLA2bits PORT ( val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0); SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); CarryIn: IN STD_LOGIC; P, G: OUT STD_LOGIC ); end component; Component Reg1Bit PORT ( valIn: in std_logic; clk: in std_logic; rst: in std_logic; valOut: out std_logic ); end component; Component Reg32Bit PORT ( valIn: in std_logic_vector(31 downto 0); clk: in std_logic; rst: in std_logic; valOut: out std_logic_vector(31 downto 0) ); end component; Component CLGB PORT ( P0, P1, G0, G1, Cin: IN STD_LOGIC; Cout1, Cout2: OUT STD_LOGIC ); end component; BEGIN --registradores-- Reg_CarryIn: Reg1Bit PORT MAP ( valIn=>CarryIn, clk=>clk, rst=>rst, valOut=>Cin_sig ); Reg_A: Reg32Bit PORT MAP ( valIn=>val1, clk=>clk, rst=>rst, valOut=>A_sig ); Reg_B: Reg32Bit PORT MAP ( valIn=>val2, clk=>clk, rst=>rst, valOut=>B_sig ); Reg_CarryOut: Reg1Bit PORT MAP ( valIn=>Cout_sig, clk=>clk, rst=>rst, valOut=>CarryOut ); Reg_Ssoma: Reg32Bit PORT MAP ( valIn=>Out_sig, clk=>clk, rst=>rst, valOut=>SomaResult ); Som1: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0), val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0), CarryIn=>Cin_sig, P=>P0_sig, G=>G0_sig, SomaResult=>SomaT1 ); CLGB1: CLGB PORT MAP( P0=>P0_sig, G0=>G0_sig, P1=>P1_sig, G1=>G1_sig, Cin=>Cin_sig, Cout1=>Cout1_temp_sig, Cout2=>Cout2_temp_sig ); Som2: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2), val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2), CarryIn=>Cout1_temp_sig, P=>P1_sig, G=>G1_sig, SomaResult=>SomaT2 ); Som3: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4), val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4), CarryIn=>Cout2_temp_sig, P=>P2_sig, G=>G2_sig, SomaResult=>SomaT3 ); CLGB2: CLGB PORT MAP( P0=>P2_sig, G0=>G2_sig, P1=>P3_sig, G1=>G3_sig, Cin=>Cout2_temp_sig, Cout1=>Cout3_temp_sig, Cout2=>Cout4_temp_sig ); Som4: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6), val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6), CarryIn=>Cout3_temp_sig, P=>P3_sig, G=>G3_sig, SomaResult=>SomaT4 ); --novoooooooo-- Som5: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(9 DOWNTO 8), val2(1 DOWNTO 0) => B_sig(9 DOWNTO 8), CarryIn=>Cout4_temp_sig, P=>P4_sig, G=>G4_sig, SomaResult=>SomaT5 ); CLGB3: CLGB PORT MAP( P0=>P4_sig, G0=>G4_sig, P1=>P5_sig, G1=>G5_sig, Cin=>Cout4_temp_sig, Cout1=>Cout5_temp_sig, Cout2=>Cout6_temp_sig ); Som6: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(11 DOWNTO 10), val2(1 DOWNTO 0) => B_sig(11 DOWNTO 10), CarryIn=>Cout5_temp_sig, P=>P5_sig, G=>G5_sig, SomaResult=>SomaT6 ); Som7: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(13 DOWNTO 12), val2(1 DOWNTO 0) => B_sig(13 DOWNTO 12), CarryIn=>Cout6_temp_sig, P=>P6_sig, G=>G6_sig, SomaResult=>SomaT7 ); CLGB4: CLGB PORT MAP( P0=>P6_sig, G0=>G6_sig, P1=>P7_sig, G1=>G7_sig, Cin=>Cout6_temp_sig, Cout1=>Cout7_temp_sig, Cout2=>Cout8_temp_sig ); Som8: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(15 DOWNTO 14), val2(1 DOWNTO 0) => B_sig(15 DOWNTO 14), CarryIn=>Cout7_temp_sig, P=>P7_sig, G=>G7_sig, SomaResult=>SomaT8 ); --novoooooooo-- Som9: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(17 DOWNTO 16), val2(1 DOWNTO 0) => B_sig(17 DOWNTO 16), CarryIn=>Cout8_temp_sig, P=>P8_sig, G=>G8_sig, SomaResult=>SomaT9 ); CLGB5: CLGB PORT MAP( P0=>P8_sig, G0=>G8_sig, P1=>P9_sig, G1=>G9_sig, Cin=>Cout8_temp_sig, Cout1=>Cout9_temp_sig, Cout2=>Cout10_temp_sig ); Som10: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(19 DOWNTO 18), val2(1 DOWNTO 0) => B_sig(19 DOWNTO 18), CarryIn=>Cout9_temp_sig, P=>P9_sig, G=>G9_sig, SomaResult=>SomaT10 ); Som11: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(21 DOWNTO 20), val2(1 DOWNTO 0) => B_sig(21 DOWNTO 20), CarryIn=>Cout10_temp_sig, P=>P10_sig, G=>G10_sig, SomaResult=>SomaT11 ); CLGB6: CLGB PORT MAP( P0=>P10_sig, G0=>G10_sig, P1=>P11_sig, G1=>G11_sig, Cin=>Cout10_temp_sig, Cout1=>Cout11_temp_sig, Cout2=>Cout12_temp_sig ); Som12: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(23 DOWNTO 22), val2(1 DOWNTO 0) => B_sig(23 DOWNTO 22), CarryIn=>Cout11_temp_sig, P=>P11_sig, G=>G11_sig, SomaResult=>SomaT12 ); --novoooooooo-- Som13: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(25 DOWNTO 24), val2(1 DOWNTO 0) => B_sig(25 DOWNTO 24), CarryIn=>Cout12_temp_sig, P=>P12_sig, G=>G12_sig, SomaResult=>SomaT13 ); CLGB7: CLGB PORT MAP( P0=>P12_sig, G0=>G12_sig, P1=>P13_sig, G1=>G13_sig, Cin=>Cout12_temp_sig, Cout1=>Cout13_temp_sig, Cout2=>Cout14_temp_sig ); Som14: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(27 DOWNTO 26), val2(1 DOWNTO 0) => B_sig(27 DOWNTO 26), CarryIn=>Cout13_temp_sig, P=>P13_sig, G=>G13_sig, SomaResult=>SomaT14 ); Som15: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(29 DOWNTO 28), val2(1 DOWNTO 0) => B_sig(29 DOWNTO 28), CarryIn=>Cout14_temp_sig, P=>P14_sig, G=>G14_sig, SomaResult=>SomaT15 ); CLGB8: CLGB PORT MAP( P0=>P14_sig, G0=>G14_sig, P1=>P15_sig, G1=>G15_sig, Cin=>Cout14_temp_sig, Cout1=>Cout15_temp_sig, Cout2=>Cout_sig ); Som16: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(31 DOWNTO 30), val2(1 DOWNTO 0) => B_sig(31 DOWNTO 30), CarryIn=>Cout15_temp_sig, P=>P15_sig, G=>G15_sig, SomaResult=>SomaT16 ); Out_sig <= SomaT16 & SomaT15 & SomaT14 & SomaT13 & SomaT12 & SomaT11 & SomaT10 & SomaT9 & SomaT8 & SomaT7 & SomaT6 & SomaT5 & SomaT4 & SomaT3 & SomaT2 & SomaT1; END strc_CLAH32bits;	mit
DE5Amigos/SylvesterTheDE2Bot	DE2Botv3Fall16Main/lpm_shiftreg_db0.vhd	1	4514	-- megafunction wizard: %LPM_SHIFTREG% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_shiftreg -- ============================================================ -- File Name: lpm_shiftreg_db0.vhd -- Megafunction Name(s): -- lpm_shiftreg -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ********************************************************** -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ********************************************************** --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_shiftreg_db0 IS PORT ( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); load : IN STD_LOGIC ; shiftout : OUT STD_LOGIC ); END lpm_shiftreg_db0; ARCHITECTURE SYN OF lpm_shiftreg_db0 IS SIGNAL sub_wire0 : STD_LOGIC ; COMPONENT lpm_shiftreg GENERIC ( lpm_direction : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( load : IN STD_LOGIC ; clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); shiftout : OUT STD_LOGIC ); END COMPONENT; BEGIN shiftout <= sub_wire0; lpm_shiftreg_component : lpm_shiftreg GENERIC MAP ( lpm_direction => "LEFT", lpm_type => "LPM_SHIFTREG", lpm_width => 32 ) PORT MAP ( load => load, clock => clock, data => data, shiftout => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: LeftShift NUMERIC "1" -- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1" -- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "1" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "0" -- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" -- Retrieval info: PRIVATE: nBit NUMERIC "32" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] -- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load -- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 -- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0 -- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm	mit
lfmunoz/vhdl	ip_blocks/sip_router_async_s1d2_x4_b/src/fifo_async_fwft_64x513_v8_2/fifo_generator_v8_2.vhd	1	341898	------------------------------------------------------------------------------- -- -- FIFO Generator - VHDL Behavioral Model -- ------------------------------------------------------------------------------- -- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- -- Filename: fifo_generator_v8_2.vhd -- -- Author : Xilinx -- ------------------------------------------------------------------------------- -- Structure: -- -- fifo_generator_v8_2.vhd -- \| -- +-fifo_generator_v8_2_conv -- \| -- +-fifo_generator_v8_2_bhv_as -- \| -- +-fifo_generator_v8_2_bhv_ss -- \| -- +-fifo_generator_v8_2_bhv_preload0 -- ------------------------------------------------------------------------------- -- Description: -- -- The VHDL behavioral model for the FIFO Generator. -- -- The behavioral model has three parts: -- - The behavioral model for independent clocks FIFOs (_as) -- - The behavioral model for common clock FIFOs (_ss) -- - The "preload logic" block which implements First-word Fall-through -- ------------------------------------------------------------------------------- --############################################################################# --############################################################################# -- Independent Clocks FIFO Behavioral Model --############################################################################# --############################################################################# ------------------------------------------------------------------------------- -- Library Declaration ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------------------------------------------------------- -- Independent Clocks Entity Declaration - This is NOT the top-level entity ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2_bhv_as IS GENERIC ( --------------------------------------------------------------------------- -- Generic Declarations --------------------------------------------------------------------------- C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 2; C_HAS_RST : integer := 1; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 2; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( --------------------------------------------------------------------------- -- Input and Output Declarations --------------------------------------------------------------------------- RST : IN std_logic; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; WR_RST : IN std_logic; RD_RST : IN std_logic; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); RD_CLK : IN std_logic; RD_EN : IN std_logic; RD_EN_USER : IN std_logic; WR_CLK : IN std_logic; WR_EN : IN std_logic; PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; USER_EMPTY_FB : IN std_logic := '1'; EMPTY : OUT std_logic := '1'; FULL : OUT std_logic := '0'; ALMOST_EMPTY : OUT std_logic := '1'; ALMOST_FULL : OUT std_logic := '0'; PROG_EMPTY : OUT std_logic := '1'; PROG_FULL : OUT std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); VALID : OUT std_logic := '0'; WR_ACK : OUT std_logic := '0'; UNDERFLOW : OUT std_logic := '0'; OVERFLOW : OUT std_logic := '0'; RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_bhv_as; ------------------------------------------------------------------------------- -- Architecture Heading ------------------------------------------------------------------------------- ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_as IS ----------------------------------------------------------------------------- -- FUNCTION actual_fifo_depth -- Returns the actual depth of the FIFO (may differ from what the user -- specified) -- -- The FIFO depth is always represented as 2^n (16,32,64,128,256) -- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain -- options. This function returns the actual depth of the fifo, as seen by -- the user. ------------------------------------------------------------------------------- FUNCTION actual_fifo_depth( C_FIFO_DEPTH : integer; C_PRELOAD_REGS : integer; C_PRELOAD_LATENCY : integer) RETURN integer IS BEGIN RETURN C_FIFO_DEPTH - 1; END actual_fifo_depth; ----------------------------------------------------------------------------- -- FUNCTION div_roundup -- Returns data_value / divisor, with the result rounded-up (if fractional) ------------------------------------------------------------------------------- FUNCTION divroundup ( data_value : integer; divisor : integer) RETURN integer IS VARIABLE div : integer; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; ----------------------------------------------------------------------------- -- FUNCTION int_2_std_logic -- Returns a single bit (as std_logic) from an integer 1/0 value. ------------------------------------------------------------------------------- FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS BEGIN IF (value=1) THEN RETURN '1'; ELSE RETURN '0'; END IF; END int_2_std_logic; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ----------------------------------------------------------------------------- -- FUNCTION hexstr_to_std_logic_vec -- Returns a std_logic_vector for a hexadecimal string ------------------------------------------------------------------------------- FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index4)+j < size THEN result((index4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; ----------------------------------------------------------------------------- -- FUNCTION get_lesser -- Returns a minimum value ------------------------------------------------------------------------------- FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a < b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; ----------------------------------------------------------------------------- -- Derived Constants ----------------------------------------------------------------------------- CONSTANT C_FIFO_WR_DEPTH : integer := actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY); CONSTANT C_FIFO_RD_DEPTH : integer := actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY); CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH); CONSTANT C_DEPTH_RATIO_WR : integer := if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1); CONSTANT C_DEPTH_RATIO_RD : integer := if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1); -- "Extra Words" is the number of write words which fit into the two -- first-word fall-through output register stages (if using FWFT). -- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1. -- This value is used to calculate the adjusted PROG_FULL threshold -- value for FWFT. -- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD -- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 -- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) -- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 -- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD); -- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT -- value for the core when using FWFT. -- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD -- C_DEPTH_RATIO_WR \| C_DEPTH_RATIO_RD \| C_PNTR_WIDTH \| EXTRA_WORDS_DC -- -----------------\|------------------\|-----------------\|--------------- -- 1 \| 8 \| C_RD_PNTR_WIDTH \| 2 -- 1 \| 4 \| C_RD_PNTR_WIDTH \| 2 -- 1 \| 2 \| C_RD_PNTR_WIDTH \| 2 -- 1 \| 1 \| C_WR_PNTR_WIDTH \| 2 -- 2 \| 1 \| C_WR_PNTR_WIDTH \| 4 -- 4 \| 1 \| C_WR_PNTR_WIDTH \| 8 -- 8 \| 1 \| C_WR_PNTR_WIDTH \| 16 CONSTANT EXTRA_WORDS_DC : integer := if_then_else ((C_DEPTH_RATIO_WR = 1),2, (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD)); CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED; CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED; CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT -- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error -- injection is selected. CONSTANT NO_ERR_INJECTION : integer := if_then_else(C_USE_ECC = 0,1, if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0)); -- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection -- is selected. CONSTANT SBIT_ERR_INJECTION : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 1),1,0); -- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection -- is selected. CONSTANT DBIT_ERR_INJECTION : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 2),1,0); -- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit -- error injection are selected. CONSTANT BOTH_ERR_INJECTION : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 3),1,0); CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2); ------------------------------------------------------------------------------- -- Signals Declaration ------------------------------------------------------------------------------- SIGNAL wr_point : integer := 0; SIGNAL rd_point : integer := 0; SIGNAL wr_point_d1 : integer := 0; SIGNAL rd_point_d1 : integer := 0; SIGNAL num_wr_words : integer := 0; SIGNAL num_rd_words : integer := 0; SIGNAL adj_wr_point : integer := 0; SIGNAL adj_rd_point : integer := 0; SIGNAL adj_wr_point_d1: integer := 0; SIGNAL adj_rd_point_d1: integer := 0; SIGNAL wr_rst_i : std_logic := '0'; SIGNAL rd_rst_i : std_logic := '0'; SIGNAL wr_rst_d1 : std_logic := '0'; SIGNAL wr_ack_i : std_logic := '0'; SIGNAL overflow_i : std_logic := '0'; SIGNAL valid_i : std_logic := '0'; SIGNAL valid_d1 : std_logic := '0'; SIGNAL valid_out : std_logic := '0'; SIGNAL underflow_i : std_logic := '0'; SIGNAL prog_full_reg : std_logic := '0'; SIGNAL prog_empty_reg : std_logic := '1'; SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL width_gt1 : std_logic := '0'; SIGNAL sbiterr_i : std_logic := '0'; SIGNAL dbiterr_i : std_logic := '0'; SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS=>'0'); SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS=>'0'); SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS=>'0'); SIGNAL empty_int : boolean := TRUE; SIGNAL empty_comb : std_logic := '1'; SIGNAL ram_rd_en : std_logic := '0'; SIGNAL ram_rd_en_d1 : std_logic := '0'; SIGNAL empty_comb_d1 : std_logic := '1'; SIGNAL almost_empty_int : boolean := TRUE; SIGNAL full_int : boolean := FALSE; SIGNAL full_comb : std_logic := '0'; SIGNAL ram_wr_en : std_logic := '0'; SIGNAL almost_full_int : boolean := FALSE; SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0'); SIGNAL stage1_valid : std_logic := '0'; SIGNAL stage2_valid : std_logic := '0'; SIGNAL diff_pntr_wr : integer := 0; SIGNAL diff_pntr_rd : integer := 0; SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); ------------------------------------------------------------------------------- --Linked List types ------------------------------------------------------------------------------- TYPE listtyp; TYPE listptr IS ACCESS listtyp; TYPE listtyp IS RECORD data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0); older : listptr; newer : listptr; END RECORD; ------------------------------------------------------------------------------- --Processes for linked list implementation. The functions are --1. "newlist" - Create a new linked list --2. "add" - Add a data element to a linked list --3. "read" - Read the data from the tail of the linked list --4. "remove" - Remove the tail from the linked list --5. "sizeof" - Calculate the size of the linked list ------------------------------------------------------------------------------- --1. Create a new linked list PROCEDURE newlist ( head : INOUT listptr; tail : INOUT listptr; cntr : INOUT integer) IS BEGIN head := NULL; tail := NULL; cntr := 0; END; --2. Add a data element to a linked list PROCEDURE add ( head : INOUT listptr; tail : INOUT listptr; data : IN std_logic_vector; cntr : INOUT integer; inj_err : IN std_logic_vector(2 DOWNTO 0) ) IS VARIABLE oldhead : listptr; VARIABLE newhead : listptr; VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0); BEGIN -------------------------------------------------------------------------- --a. Create a pointer to the existing head, if applicable --b. Create a new node for the list --c. Make the new node point to the old head --d. Make the old head point back to the new node (for doubly-linked list) --e. Put the data into the new head node --f. If the new head we just created is the only node in the list, -- make the tail point to it --g. Return the new head pointer -------------------------------------------------------------------------- IF (head /= NULL) THEN oldhead := head; END IF; newhead := NEW listtyp; newhead.older := oldhead; IF (head /= NULL) THEN oldhead.newer := newhead; END IF; CASE (inj_err(1 DOWNTO 0)) IS -- For both error injection, pass only the double bit error injection -- as dbit error has priority over single bit error injection WHEN "11" => newhead.data := inj_err(1) & '0' & data; WHEN "10" => newhead.data := inj_err(1) & '0' & data; WHEN "01" => newhead.data := '0' & inj_err(0) & data; WHEN OTHERS => newhead.data := '0' & '0' & data; END CASE; -- Increment the counter when data is added to the list cntr := cntr + 1; IF (newhead.older = NULL) THEN tail := newhead; END IF; head := newhead; END; --3. Read the data from the tail of the linked list PROCEDURE read ( tail : INOUT listptr; data : OUT std_logic_vector; err_type : OUT std_logic_vector(1 DOWNTO 0) ) IS VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0'); VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); BEGIN data_int := tail.data; -- MSB two bits carry the error injection type. err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH); IF (err_type_int(1) = '0') THEN data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0); ELSIF (C_DOUT_WIDTH = 2) THEN data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0); ELSIF (C_DOUT_WIDTH > 2) THEN data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) & data_int(data_int'high-4 DOWNTO 0); ELSE data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0); END IF; err_type := err_type_int; END; --4. Remove the tail from the linked list PROCEDURE remove ( head : INOUT listptr; tail : INOUT listptr; cntr : INOUT integer) IS VARIABLE oldtail : listptr; VARIABLE newtail : listptr; BEGIN -------------------------------------------------------------------------- --Make a copy of the old tail pointer --a. If there is no newer node, then set the tail pointer to nothing -- (list is empty) -- otherwise, make the next newer node the new tail, and make it point -- to nothing older --b. Clean up the memory for the old tail node --c. If the new tail is nothing, then we have an empty list, and head -- should also be set to nothing --d. Return the new tail -------------------------------------------------------------------------- oldtail := tail; IF (oldtail.newer = NULL) THEN newtail := NULL; ELSE newtail := oldtail.newer; newtail.older := NULL; END IF; DEALLOCATE(oldtail); IF (newtail = NULL) THEN head := NULL; END IF; tail := newtail; -- Decrement the counter when data is removed from the list cntr := cntr - 1; END; --5. Calculate the size of the linked list PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS VARIABLE curlink : listptr; VARIABLE tmpsize : integer := 0; BEGIN -------------------------------------------------------------------------- --a. If head is null, then there is nothing in the list to traverse -- start with the head node (which implies at least one node exists) -- Loop through each node until you find the one that points to nothing -- (the tail) --b. Return the number of nodes -------------------------------------------------------------------------- IF (head /= NULL) THEN curlink := head; tmpsize := 1; WHILE (curlink.older /= NULL) LOOP tmpsize := tmpsize + 1; curlink := curlink.older; END LOOP; END IF; size := tmpsize; END; ----------------------------------------------------------------------------- -- converts integer to specified length std_logic_vector : dropping least -- significant bits if integer is bigger than what can be represented by -- the vector ----------------------------------------------------------------------------- FUNCTION count( fifo_count : IN integer; pointer_width : IN integer; counter_width : IN integer) RETURN std_logic_vector IS VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width); IF (counter_width <= pointer_width) THEN output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width); ELSE output := temp(counter_width - 1 DOWNTO 0); END IF; RETURN output; END count; ------------------------------------------------------------------------------- -- architecture begins here ------------------------------------------------------------------------------- BEGIN ------------------------------------------------------------------------------- -- Asynchronous FIFO ------------------------------------------------------------------------------- gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH); rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH); wr_rst_i <= WR_RST; rd_rst_i <= RD_RST; ------------------------------------------------------------------------------- -- calculate number of words in wr and rd domain according to the deepest port -- -- These steps circumvent the linked-list data structure and keep track of -- wr_point and rd_point pointers much like the core itself does. The behavioral -- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done -- because the sizeof() function always returns the exact number of words in -- the linked list, and can not account for delays when crossing clock domains. ------------------------------------------------------------------------------- adj_wr_point <= wr_point * C_DEPTH_RATIO_RD; adj_rd_point <= rd_point * C_DEPTH_RATIO_WR; adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD; adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR; width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0'; PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1) BEGIN IF (adj_wr_point >= adj_rd_point_d1) THEN num_wr_words <= adj_wr_point - adj_rd_point_d1; ELSE num_wr_words <= C_WR_DEPTHC_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1; END IF; IF (adj_wr_point_d1 >= adj_rd_point) THEN num_rd_words <= adj_wr_point_d1 - adj_rd_point; ELSE num_rd_words <= C_RD_DEPTHC_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point; END IF; END PROCESS; ------------------------------------------------------------------------------- --Calculate WR_ACK based on C_WR_ACK_LOW parameters ------------------------------------------------------------------------------- gwalow : IF (C_WR_ACK_LOW = 0) GENERATE WR_ACK <= wr_ack_i; END GENERATE gwalow; gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE WR_ACK <= NOT wr_ack_i; END GENERATE gwahgh; ------------------------------------------------------------------------------- --Calculate OVERFLOW based on C_OVERFLOW_LOW parameters ------------------------------------------------------------------------------- govlow : IF (C_OVERFLOW_LOW = 0) GENERATE OVERFLOW <= overflow_i; END GENERATE govlow; govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE OVERFLOW <= NOT overflow_i; END GENERATE govhgh; ------------------------------------------------------------------------------- --Calculate VALID based on C_VALID_LOW ------------------------------------------------------------------------------- gnvl : IF (C_VALID_LOW = 0) GENERATE VALID <= valid_out; END GENERATE gnvl; gnvh : IF (C_VALID_LOW = 1) GENERATE VALID <= NOT valid_out; END GENERATE gnvh; ------------------------------------------------------------------------------- --Calculate UNDERFLOW based on C_UNDERFLOW_LOW ------------------------------------------------------------------------------- gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE UNDERFLOW <= underflow_i; END GENERATE gnul; gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE UNDERFLOW <= NOT underflow_i; END GENERATE gnuh; ------------------------------------------------------------------------------- --Assign PROG_FULL and PROG_EMPTY ------------------------------------------------------------------------------- PROG_FULL <= prog_full_reg; PROG_EMPTY <= prog_empty_reg; ------------------------------------------------------------------------------- --Assign RD_DATA_COUNT and WR_DATA_COUNT ------------------------------------------------------------------------------- rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH); END GENERATE grdc_fwft_ext; gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH); END GENERATE gnrdc_fwft_ext; END GENERATE rdc; nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE RD_DATA_COUNT <= (OTHERS=>'0'); END GENERATE nrdc; wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH); END GENERATE gwdc_fwft_ext; gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH); END GENERATE gnwdc_fwft_ext; END GENERATE wdc; nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE WR_DATA_COUNT <= (OTHERS=>'0'); END GENERATE nwdc; ------------------------------------------------------------------------------- -- Write data count calculation if Use Extra Logic option is used ------------------------------------------------------------------------------- wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE CONSTANT C_PNTR_WIDTH : integer := if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH), C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH); SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0) := conv_std_logic_vector( if_then_else ((C_DEPTH_RATIO_WR=1),2 ,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD)) ,C_PNTR_WIDTH+1); SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); BEGIN ----------------------------------------------------------------------------- --Adjust write and read pointer to the deepest port width ----------------------------------------------------------------------------- --C_PNTR_WIDTH=C_WR_PNTR_WIDTH gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE adjusted_wr_pntr <= wr_pntr; adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr_wr; adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0'); END GENERATE gpadr; --C_PNTR_WIDTH=C_RD_PNTR_WIDTH gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH) <= wr_pntr; adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0'); adjusted_rd_pntr <= rd_pntr_wr; END GENERATE gpadw; --C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE adjusted_wr_pntr <= wr_pntr; adjusted_rd_pntr <= rd_pntr_wr; END GENERATE ngpad; ----------------------------------------------------------------------------- --Calculate words in write domain ----------------------------------------------------------------------------- --Subtract the pointers to get the number of words in the RAM, THEN pad --the result diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr; diff_wr_rd <= '0' & diff_wr_rd_tmp; pwdc : PROCESS (WR_CLK, wr_rst_i) BEGIN IF (wr_rst_i = '1') THEN wr_data_count_i <= (OTHERS=>'0'); ELSIF (WR_CLK'event AND WR_CLK = '1') THEN wr_data_count_i <= diff_wr_rd + extra_words; END IF; END PROCESS pwdc; gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE wdc_fwft_ext_as <= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0); END GENERATE gdc0; gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE wdc_fwft_ext_as <= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH); END GENERATE gdc1; END GENERATE wdc_fwft_ext; ------------------------------------------------------------------------------- -- Read data count calculation if Use Extra Logic option is used ------------------------------------------------------------------------------- rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1); SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1); SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); BEGIN ---------------------------------------------------------------------------- -- If write depth is smaller than read depth, pad write pointer. -- If write depth is bigger than read depth, trim write pointer. ---------------------------------------------------------------------------- gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH) <= WR_PNTR_RD; adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0'); END GENERATE gpad; gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE adjusted_wr_pntr_r <= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH); END GENERATE gtrim; ----------------------------------------------------------------------------- -- This accounts for preload 0 by explicitly handling the preload states -- which do not have both output stages filled. As a result, the rd_data_count -- produced will always accurately reflect the number of READABLE words at -- a given time. ----------------------------------------------------------------------------- diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR; diff_wr_rd <= '0' & diff_wr_rd_tmp; prdc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN rdc_fwft_ext_as <= zero; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN IF (stage2_valid = '0') THEN rdc_fwft_ext_as <= zero; ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN rdc_fwft_ext_as <= one; ELSE rdc_fwft_ext_as <= diff_wr_rd + two; END IF; END IF; END PROCESS prdc; END GENERATE rdc_fwft_ext; ------------------------------------------------------------------------------- -- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation ------------------------------------------------------------------------------- gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH) <= wr_pntr_rd; adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0'); END GENERATE gpad; gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE adj_wr_pntr_rd <= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH); END GENERATE gtrim; ------------------------------------------------------------------------------- -- Generate Empty ------------------------------------------------------------------------------- -- ram_rd_en used to determine EMPTY should depend on the EMPTY. ram_rd_en <= RD_EN AND (NOT empty_comb); empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND (adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Generate Almost Empty ------------------------------------------------------------------------------- almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND (adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Registering Empty & Almost Empty -- Generate read data count if Use Extra Logic is not selected. ------------------------------------------------------------------------------- empty_proc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN empty_comb <= '1' AFTER C_TCQ; empty_comb_d1 <= '1' AFTER C_TCQ; ALMOST_EMPTY <= '1' AFTER C_TCQ; rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) - rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ; empty_comb_d1 <= empty_comb AFTER C_TCQ; IF (empty_int) THEN empty_comb <= '1' AFTER C_TCQ; ELSE empty_comb <= '0' AFTER C_TCQ; END IF; IF (empty_comb = '0') THEN IF (almost_empty_int) THEN ALMOST_EMPTY <= '1' AFTER C_TCQ; ELSE ALMOST_EMPTY <= '0' AFTER C_TCQ; END IF; END IF; END IF; END PROCESS empty_proc; ------------------------------------------------------------------------------- -- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation ------------------------------------------------------------------------------- gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE adj_rd_pntr_wr (C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr_wr; adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0'); END GENERATE gfpad; gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE adj_rd_pntr_wr <= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH); END GENERATE gftrim; ------------------------------------------------------------------------------- -- Generate Full ------------------------------------------------------------------------------- -- ram_wr_en used to determine FULL should depend on the FULL. ram_wr_en <= WR_EN AND (NOT full_comb); full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND (adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Generate Almost Full ------------------------------------------------------------------------------- almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND (adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Registering Full & Almost Full -- Generate write data count if Use Extra Logic is not selected. ------------------------------------------------------------------------------- full_proc : PROCESS (WR_CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ; ELSIF (WR_CLK'event AND WR_CLK = '1') THEN wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) - adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ; IF (full_int) THEN full_comb <= '1' AFTER C_TCQ; ELSE full_comb <= '0' AFTER C_TCQ; END IF; IF (RST_FULL_GEN = '1') THEN ALMOST_FULL <= '0' AFTER C_TCQ; ELSIF (full_comb = '0') THEN IF (almost_full_int) THEN ALMOST_FULL <= '1' AFTER C_TCQ; ELSE ALMOST_FULL <= '0' AFTER C_TCQ; END IF; END IF; END IF; END PROCESS full_proc; ------------------------------------------------------------------------------- -- Counter that determines the FWFT read duration. ------------------------------------------------------------------------------- -- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT. grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE SIGNAL user_empty_fb_d1 : std_logic := '1'; BEGIN grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN rd_fwft_cnt <= (others => '0'); user_empty_fb_d1 <= '1'; stage1_valid <= '0'; stage2_valid <= '0'; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN user_empty_fb_d1 <= USER_EMPTY_FB; IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN rd_fwft_cnt <= (others => '0') AFTER C_TCQ; ELSIF (empty_comb = '0') THEN IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ; END IF; END IF; IF (stage1_valid = '0' AND stage2_valid = '0') THEN IF (empty_comb = '0') THEN stage1_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '0' AFTER C_TCQ; END IF; ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN IF (empty_comb = '1') THEN stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; END IF; ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN IF (empty_comb = '1' AND RD_EN_USER = '1') THEN stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '0' AFTER C_TCQ; ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '0' AFTER C_TCQ; ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; END IF; ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN IF (empty_comb = '1' AND RD_EN_USER = '1') THEN stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; END IF; ELSE stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '0' AFTER C_TCQ; END IF; END IF; END PROCESS grd_fwft_proc; END GENERATE grd_fwft; gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE rd_fwft_cnt <= X"2"; END GENERATE gnrd_fwft; ------------------------------------------------------------------------------- -- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY ------------------------------------------------------------------------------- FULL <= full_comb; EMPTY <= empty_comb; ------------------------------------------------------------------------------- -- Asynchronous FIFO using linked lists ------------------------------------------------------------------------------- FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i) --Declare the linked-list head/tail pointers and the size value VARIABLE head : listptr; VARIABLE tail : listptr; VARIABLE size : integer := 0; VARIABLE cntr : integer := 0; VARIABLE cntr_size_var_int : integer := 0; --Data is the internal version of the DOUT bus VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0) := hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width); VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); --Temporary values for calculating adjusted prog_empty/prog_full thresholds VARIABLE prog_empty_actual_assert_thresh : integer := 0; VARIABLE prog_empty_actual_negate_thresh : integer := 0; VARIABLE prog_full_actual_assert_thresh : integer := 0; VARIABLE prog_full_actual_negate_thresh : integer := 0; VARIABLE diff_pntr : integer := 0; BEGIN -- Calculate the current contents of the FIFO (size) -- Warning: This value should only be calculated once each time this -- process is entered. -- It is updated instantaneously for both write and read operations, -- so it is not ideal to use for signals which must consider the -- latency of crossing clock domains. -- cntr_size_var_int is updated only once when the process is entered -- This variable is used in the conditions instead of cntr which has the -- latest value. cntr_size_var_int := cntr; -- RESET CONDITIONS IF wr_rst_i = '1' THEN wr_point <= 0 after C_TCQ; wr_point_d1 <= 0 after C_TCQ; wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr_d2 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr_d3 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr_d4 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr <= (OTHERS => '0') after C_TCQ; --Create new linked list newlist(head, tail,cntr); diff_pntr := 0; --------------------------------------------------------------------------- -- Write to FIFO --------------------------------------------------------------------------- ELSIF WR_CLK'event AND WR_CLK = '1' THEN -- Delay the write pointer before passing to RD_CLK domain to accommodate -- the binary to gray converion wr_pntr_rd1 <= wr_pntr after C_TCQ; -- Read pointer synchronization in WR_CLK domain rd_pntr_wr_d2 <= rd_pntr_wr_d1 after C_TCQ; rd_pntr_wr_d3 <= rd_pntr_wr_d2 after C_TCQ; rd_pntr_wr_d4 <= rd_pntr_wr_d2 after C_TCQ; -- Delay the synchronized read pointer to accommodate the gray to binary -- converion in WR_CLK domain rd_pntr_wr <= rd_pntr_wr_d4 after C_TCQ; wr_point_d1 <= wr_point after C_TCQ; --The following IF statement setup default values of full_i and almost_full_i. --The values might be overwritten in the next IF statement. --If writing, then it is not possible to predict how many --words will actually be in the FIFO after the write concludes --(because the number of reads which happen in this time can -- not be determined). --Therefore, treat it pessimistically and always assume that -- the write will happen without a read (assume the FIFO is -- C_DEPTH_RATIO_RD fuller than it is). --Note: --1. cntr_size_var_int is the deepest depth between write depth and read depth -- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain. --2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle -- if wr_en=1 (C_DEPTH_RATIO_RD=one write word) --3. For asymmetric FIFO, if write width is narrower than read width. Don't -- have to consider partial words. --4. For asymmetric FIFO, if read width is narrower than write width, -- the worse case that FIFO is going to full is depicted in the following -- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a -- is the worse case. Therefore, in the calculation, actual FIFO depth is -- substarcted to one write word and added one read word. -- ------- -- \| \| \| -- wr_pntr-->\| \|--- -- \| \| \| -- ---\|--- -- \| \| \| -- \| \|--- -- \| \| \| -- ---\|--- -- \| \| \|<--rd_pntr_a -- \| \|--- -- \| \| \|<--rd_pntr_b -- ---\|--- -- Update full_i and almost_full_i if user is writing to the FIFO. -- Assign overflow and wr_ack. IF WR_EN = '1' THEN IF full_comb /= '1' THEN -- User is writing to a FIFO which is NOT reporting FULL IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN -- FIFO really is Full --Report Overflow and do not acknowledge the write ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN -- FIFO is almost full -- This write will succeed, and FIFO will go FULL FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP add(head, tail, DIN((C_SMALLER_DATA_WIDTHh)-1 DOWNTO C_SMALLER_DATA_WIDTH(h-1)),cntr, (width_gt1 & INJECTDBITERR & INJECTSBITERR)); END LOOP; wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ; ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN -- FIFO is one away from almost full -- This write will succeed, and FIFO will go almost_full_i FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP add(head, tail, DIN((C_SMALLER_DATA_WIDTHh)-1 DOWNTO C_SMALLER_DATA_WIDTH(h-1)),cntr, (width_gt1 & INJECTDBITERR & INJECTSBITERR)); END LOOP; wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ; ELSE -- FIFO is no where near FULL --Write will succeed, no change in status FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP add(head, tail, DIN((C_SMALLER_DATA_WIDTHh)-1 DOWNTO C_SMALLER_DATA_WIDTH(h-1)),cntr, (width_gt1 & INJECTDBITERR & INJECTSBITERR)); END LOOP; wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ; END IF; ELSE --IF full_i = '1' -- User is writing to a FIFO which IS reporting FULL --Write will fail END IF; --full_i ELSE --WR_EN/='1' --No write attempted, so neither overflow or acknowledge END IF; --WR_EN END IF; --WR_CLK --------------------------------------------------------------------------- -- Read from FIFO --------------------------------------------------------------------------- IF rd_rst_i = '1' THEN -- Whenever user is attempting to read from -- an EMPTY FIFO, the core should report an underflow error, even if -- the core is in a RESET condition. rd_point <= 0 after C_TCQ; rd_point_d1 <= 0 after C_TCQ; rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ; wr_pntr_rd2 <= (OTHERS => '0') after C_TCQ; wr_pntr_rd3 <= (OTHERS => '0') after C_TCQ; wr_pntr_rd <= (OTHERS => '0') after C_TCQ; -- DRAM resets asynchronously IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); END IF; -- BRAM resets synchronously IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN IF (RD_CLK'event AND RD_CLK = '1') THEN data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); END IF; END IF; -- Reset only if ECC is not selected as ECC does not support reset. IF (C_USE_ECC = 0) THEN err_type := (OTHERS => '0'); END IF ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- Delay the read pointer before passing to WR_CLK domain to accommodate -- the binary to gray converion rd_pntr_wr_d1 <= rd_pntr after C_TCQ; -- Write pointer synchronization in RD_CLK domain wr_pntr_rd2 <= wr_pntr_rd1 after C_TCQ; wr_pntr_rd3 <= wr_pntr_rd2 after C_TCQ; -- Delay the synchronized write pointer to accommodate the gray to binary -- converion in RD_CLK domain wr_pntr_rd <= wr_pntr_rd3 after C_TCQ; rd_point_d1 <= rd_point after C_TCQ; --------------------------------------------------------------------------- -- Read Latency 1 --------------------------------------------------------------------------- --The following IF statement setup default values of empty_i and --almost_empty_i. The values might be overwritten in the next IF statement. --Note: --cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain. IF (ram_rd_en = '1') THEN IF empty_comb /= '1' THEN IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN --FIFO is going almost empty FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP read(tail, data((C_SMALLER_DATA_WIDTHh)-1 DOWNTO C_SMALLER_DATA_WIDTH(h-1)), err_type); remove(head, tail,cntr); END LOOP; rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ; ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN --FIFO is going empty FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP read(tail, data((C_SMALLER_DATA_WIDTHh)-1 DOWNTO C_SMALLER_DATA_WIDTH(h-1)), err_type); remove(head, tail,cntr); END LOOP; rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ; ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN --FIFO is empty ELSE --FIFO is not empty FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP read(tail, data((C_SMALLER_DATA_WIDTHh)-1 DOWNTO C_SMALLER_DATA_WIDTH(h-1)), err_type); remove(head, tail,cntr); END LOOP; rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ; END IF; ELSE --FIFO is empty END IF; END IF; --RD_EN END IF; --RD_CLK dout_i <= data after C_TCQ; sbiterr_i <= err_type(0) after C_TCQ; dbiterr_i <= err_type(1) after C_TCQ; END PROCESS; ----------------------------------------------------------------------------- -- Programmable FULL flags ----------------------------------------------------------------------------- proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE) BEGIN IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC); ELSE -- Multiple threshold inputs pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH); pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH); END IF; ELSE -- STD IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input pf_input_thr_assert_val <= PROG_FULL_THRESH; ELSE -- Multiple threshold inputs pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT; pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE; END IF; END IF; END PROCESS proc_pf_input; proc_pf: PROCESS(WR_CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); diff_pntr_wr <= 0; ELSIF (WR_CLK'event AND WR_CLK = '1') THEN IF (ram_wr_en = '0') THEN diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ; ELSIF (ram_wr_en = '1') THEN diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ; END IF; IF (RST_FULL_GEN = '1') THEN prog_full_reg <= '0' after C_TCQ; ELSIF (C_PROG_FULL_TYPE = 1) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN prog_full_reg <= '1' after C_TCQ; ELSE prog_full_reg <= '0' after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSIF (C_PROG_FULL_TYPE = 2) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN prog_full_reg <= '1' after C_TCQ; ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN prog_full_reg <= '0' after C_TCQ; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSIF (C_PROG_FULL_TYPE = 3) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN prog_full_reg <= '1' after C_TCQ; ELSE prog_full_reg <= '0' after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSIF (C_PROG_FULL_TYPE = 4) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN prog_full_reg <= '1' after C_TCQ; ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN prog_full_reg <= '0' after C_TCQ; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; END IF; --C_PROG_FULL_TYPE END IF; -- WR_CLK END PROCESS proc_pf; --------------------------------------------------------------------------- -- Programmable EMPTY Flags --------------------------------------------------------------------------- proc_pe: PROCESS(RD_CLK, rd_rst_i) VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN IF (rd_rst_i = '1') THEN diff_pntr_rd <= 0; prog_empty_reg <= '1'; pe_thr_assert_val := (OTHERS => '0'); pe_thr_negate_val := (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK = '1') THEN IF (ram_rd_en = '0') THEN diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ; ELSIF (ram_rd_en = '1') THEN diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ; ELSE diff_pntr_rd <= diff_pntr_rd after C_TCQ; END IF; IF (C_PROG_EMPTY_TYPE = 1) THEN IF (empty_comb = '0') THEN IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN prog_empty_reg <= '1' after C_TCQ; ELSE prog_empty_reg <= '0' after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSIF (C_PROG_EMPTY_TYPE = 2) THEN IF (empty_comb = '0') THEN IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN prog_empty_reg <= '1' after C_TCQ; ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN prog_empty_reg <= '0' after C_TCQ; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSIF (C_PROG_EMPTY_TYPE = 3) THEN -- If empty input threshold is selected, then subtract 2 for FWFT to -- compensate the FWFT stage, otherwise assign the input value. IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT pe_thr_assert_val := PROG_EMPTY_THRESH - "10"; ELSE pe_thr_assert_val := PROG_EMPTY_THRESH; END IF; IF (empty_comb = '0') THEN IF (diff_pntr_rd <= pe_thr_assert_val) THEN prog_empty_reg <= '1' after C_TCQ; ELSE prog_empty_reg <= '0' after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSIF (C_PROG_EMPTY_TYPE = 4) THEN -- If empty input threshold is selected, then subtract 2 for FWFT to -- compensate the FWFT stage, otherwise assign the input value. IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10"; pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10"; ELSE pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT; pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE; END IF; IF (empty_comb = '0') THEN IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN prog_empty_reg <= '1' after C_TCQ; ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN prog_empty_reg <= '0' after C_TCQ; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; END IF; --C_PROG_EMPTY_TYPE END IF; -- RD_CLK END PROCESS proc_pe; ----------------------------------------------------------------------------- -- overflow_i generation: Asynchronous FIFO ----------------------------------------------------------------------------- govflw: IF (C_HAS_OVERFLOW = 1) GENERATE povflw: PROCESS (WR_CLK) BEGIN IF WR_CLK'event AND WR_CLK = '1' THEN overflow_i <= full_comb AND WR_EN after C_TCQ; END IF; END PROCESS povflw; END GENERATE govflw; ----------------------------------------------------------------------------- -- underflow_i generation: Asynchronous FIFO ----------------------------------------------------------------------------- gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE punflw: PROCESS (RD_CLK) BEGIN IF RD_CLK'event AND RD_CLK = '1' THEN underflow_i <= empty_comb and RD_EN after C_TCQ; END IF; END PROCESS punflw; END GENERATE gunflw; ----------------------------------------------------------------------------- -- wr_ack_i generation: Asynchronous FIFO ----------------------------------------------------------------------------- gwack: IF (C_HAS_WR_ACK = 1) GENERATE pwack: PROCESS (WR_CLK,wr_rst_i) BEGIN IF wr_rst_i = '1' THEN wr_ack_i <= '0' after C_TCQ; ELSIF WR_CLK'event AND WR_CLK = '1' THEN wr_ack_i <= '0' after C_TCQ; IF WR_EN = '1' THEN IF full_comb /= '1' THEN wr_ack_i <= '1' after C_TCQ; END IF; END IF; END IF; END PROCESS pwack; END GENERATE gwack; ---------------------------------------------------------------------------- -- valid_i generation: Asynchronous FIFO ---------------------------------------------------------------------------- gvld_i: IF (C_HAS_VALID = 1) GENERATE PROCESS (rd_rst_i , RD_CLK ) BEGIN IF rd_rst_i = '1' THEN valid_i <= '0' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN valid_i <= '0' after C_TCQ; IF RD_EN = '1' THEN IF empty_comb /= '1' THEN valid_i <= '1' after C_TCQ; END IF; END IF; END IF; END PROCESS; ----------------------------------------------------------------- -- Delay valid_d1 --if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1 ----------------------------------------------------------------- gv0_as: IF (C_USE_EMBEDDED_REG=1 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE PROCESS (rd_rst_i , RD_CLK ) BEGIN IF rd_rst_i = '1' THEN valid_d1 <= '0' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN valid_d1 <= valid_i after C_TCQ; END IF; END PROCESS; END GENERATE gv0_as; gv1_as: IF NOT (C_USE_EMBEDDED_REG=1 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE valid_d1 <= valid_i; END GENERATE gv1_as; END GENERATE gvld_i; ----------------------------------------------------------------------------- --Use delayed Valid AND DOUT if we have a LATENCY=2 configurations -- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 ) --Otherwise, connect the valid and DOUT values up directly, with no --additional latency. ----------------------------------------------------------------------------- gv0: IF (C_PRELOAD_LATENCY=2 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE gv1: IF (C_HAS_VALID = 1) GENERATE valid_out <= valid_d1; END GENERATE gv1; PROCESS (rd_rst_i , RD_CLK ) BEGIN IF (rd_rst_i = '1') THEN -- BRAM resets synchronously IF (C_USE_DOUT_RST = 1) THEN IF (RD_CLK 'event AND RD_CLK = '1') THEN DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; END IF; IF (C_USE_ECC = 0) THEN SBITERR <= '0' after C_TCQ; DBITERR <= '0' after C_TCQ; END IF; ram_rd_en_d1 <= '0' after C_TCQ; ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN ram_rd_en_d1 <= ram_rd_en after C_TCQ; IF (ram_rd_en_d1 = '1') THEN DOUT <= dout_i after C_TCQ; SBITERR <= sbiterr_i after C_TCQ; DBITERR <= dbiterr_i after C_TCQ; END IF; END IF; END PROCESS; END GENERATE gv0; gv1: IF NOT (C_PRELOAD_LATENCY=2 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE gv2a: IF (C_HAS_VALID = 1) GENERATE valid_out <= valid_i; END GENERATE gv2a; DOUT <= dout_i; SBITERR <= sbiterr_i after C_TCQ; DBITERR <= dbiterr_i after C_TCQ; END GENERATE gv1; END GENERATE gnll_afifo; ------------------------------------------------------------------------------- -- Low Latency Asynchronous FIFO ------------------------------------------------------------------------------- gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0')); SIGNAL write_allow : std_logic := '0'; SIGNAL read_allow : std_logic := '0'; SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL ll_afifo_full : std_logic := '0'; SIGNAL ll_afifo_empty : std_logic := '1'; SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0'; SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0'; SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0'; SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0'; BEGIN wr_rst_i <= WR_RST; rd_rst_i <= RD_RST; write_allow <= WR_EN AND (NOT ll_afifo_full); read_allow <= RD_EN AND (NOT ll_afifo_empty); wrptr_proc : PROCESS (WR_CLK,wr_rst_i) BEGIN IF (wr_rst_i = '1') THEN wr_pntr_ll_afifo <= (OTHERS => '0'); ELSIF (WR_CLK'event AND WR_CLK = '1') THEN IF (write_allow = '1') THEN wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ; END IF; END IF; END PROCESS wrptr_proc; ------------------------------------------------------------------------------- -- Fill the Memory ------------------------------------------------------------------------------- wr_mem : PROCESS (WR_CLK) BEGIN IF (WR_CLK'event AND WR_CLK = '1') THEN IF (write_allow = '1') THEN memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ; END IF; END IF; END PROCESS wr_mem; rdptr_proc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN rd_pntr_ll_afifo_q <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK = '1') THEN rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ; END IF; END PROCESS rdptr_proc; rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q; ------------------------------------------------------------------------------- -- Generate DOUT for DRAM ------------------------------------------------------------------------------- rd_mem : PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK = '1') THEN DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ; END IF; END PROCESS rd_mem; ------------------------------------------------------------------------------- -- Generate EMPTY ------------------------------------------------------------------------------- wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0'; wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector( (conv_integer(rd_pntr_ll_afifo_q)+1), C_RD_PNTR_WIDTH)) ELSE '0'; proc_empty : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN ll_afifo_empty <= '1'; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ; END IF; END PROCESS proc_empty; ------------------------------------------------------------------------------- -- Generate FULL ------------------------------------------------------------------------------- rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector( (conv_integer(wr_pntr_ll_afifo)+1), C_WR_PNTR_WIDTH)) ELSE '0'; rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector( (conv_integer(wr_pntr_ll_afifo)+2), C_WR_PNTR_WIDTH)) ELSE '0'; proc_full : PROCESS (WR_CLK, wr_rst_i) BEGIN IF (wr_rst_i = '1') THEN ll_afifo_full <= '1'; ELSIF (WR_CLK'event AND WR_CLK = '1') THEN ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ; END IF; END PROCESS proc_full; EMPTY <= ll_afifo_empty; FULL <= ll_afifo_full; END GENERATE gll_afifo; END behavioral; --############################################################################# --############################################################################# -- Common Clock FIFO Behavioral Model --############################################################################# --############################################################################# ------------------------------------------------------------------------------- -- Library Declaration ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------------------------------------------------------- -- Common-Clock Entity Declaration - This is NOT the top-level entity ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2_bhv_ss IS GENERIC ( -------------------------------------------------------------------------------- -- Generic Declarations (alphabetical) -------------------------------------------------------------------------------- C_DATA_COUNT_WIDTH : integer := 2; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RST : integer := 0; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); RD_EN : IN std_logic := '0'; WR_EN : IN std_logic := '0'; PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); EMPTY : OUT std_logic := '1'; FULL : OUT std_logic := '0'; ALMOST_EMPTY : OUT std_logic := '1'; ALMOST_FULL : OUT std_logic := '0'; PROG_EMPTY : OUT std_logic := '1'; PROG_FULL : OUT std_logic := '0'; OVERFLOW : OUT std_logic := '0'; WR_ACK : OUT std_logic := '0'; VALID : OUT std_logic := '0'; UNDERFLOW : OUT std_logic := '0'; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_bhv_ss; ------------------------------------------------------------------------------- -- Architecture Heading ------------------------------------------------------------------------------- ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_ss IS ----------------------------------------------------------------------------- -- FUNCTION actual_fifo_depth -- Returns the actual depth of the FIFO (may differ from what the user -- specified) -- -- The FIFO depth is always represented as 2^n (16,32,64,128,256) -- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain -- options. This function returns the actual depth of the fifo, as seen by -- the user. ------------------------------------------------------------------------------- FUNCTION actual_fifo_depth( C_FIFO_DEPTH : integer; C_PRELOAD_REGS : integer; C_PRELOAD_LATENCY : integer; C_COMMON_CLOCK : integer) RETURN integer IS BEGIN RETURN C_FIFO_DEPTH; END actual_fifo_depth; ----------------------------------------------------------------------------- -- FUNCTION int_2_std_logic -- Returns a single bit (as std_logic) from an integer 1/0 value. ------------------------------------------------------------------------------- FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS BEGIN IF (value=1) THEN RETURN '1'; ELSE RETURN '0'; END IF; END int_2_std_logic; ----------------------------------------------------------------------------- -- FUNCTION hexstr_to_std_logic_vec -- Returns a std_logic_vector for a hexadecimal string ------------------------------------------------------------------------------- FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index4)+j < size THEN result((index4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; ----------------------------------------------------------------------------- -- FUNCTION get_lesser -- Returns a minimum value ------------------------------------------------------------------------------- FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a < b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; -------------------------------------------------------------------------------- -- Constant Declaration -------------------------------------------------------------------------------- CONSTANT C_FIFO_WR_DEPTH : integer := actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1); CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH); CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH; CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0), C_DIN_WIDTH+2, C_DIN_WIDTH); TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); ------------------------------------------------------------------------------- -- Internal Signals ------------------------------------------------------------------------------- SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0')); SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL write_allow : std_logic := '0'; SIGNAL read_allow : std_logic := '0'; SIGNAL empty_i : std_logic := '1'; SIGNAL full_i : std_logic := '0'; SIGNAL almost_empty_i : std_logic := '1'; SIGNAL almost_full_i : std_logic := '0'; SIGNAL rst_asreg : std_logic := '0'; SIGNAL rst_asreg_d1 : std_logic := '0'; SIGNAL rst_asreg_d2 : std_logic := '0'; SIGNAL rst_comb : std_logic := '0'; SIGNAL rst_reg : std_logic := '0'; SIGNAL rst_i : std_logic := '0'; SIGNAL srst_i : std_logic := '0'; -- FULL_FLAG_RESET value given for SRST as well. SIGNAL srst_i_d1 : std_logic := '0'; SIGNAL srst_i_d2 : std_logic := '0'; SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wr_ack_i : std_logic := '0'; SIGNAL overflow_i : std_logic := '0'; SIGNAL valid_i : std_logic := '0'; SIGNAL valid_d1 : std_logic := '0'; SIGNAL underflow_i : std_logic := '0'; --The delayed reset is used to deassert prog_full SIGNAL rst_q : std_logic := '0'; SIGNAL prog_full_reg : std_logic := '0'; SIGNAL prog_full_noreg : std_logic := '0'; SIGNAL prog_empty_reg : std_logic := '1'; SIGNAL prog_empty_noreg: std_logic := '1'; SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL sbiterr_i : std_logic := '0'; SIGNAL dbiterr_i : std_logic := '0'; SIGNAL ram_rd_en_d1 : std_logic := '0'; SIGNAL mem_pntr : integer := 0; SIGNAL ram_wr_en_i : std_logic := '0'; SIGNAL ram_rd_en_i : std_logic := '0'; SIGNAL comp1 : std_logic := '0'; SIGNAL comp0 : std_logic := '0'; SIGNAL going_full : std_logic := '0'; SIGNAL leaving_full : std_logic := '0'; SIGNAL ram_full_comb : std_logic := '0'; SIGNAL ecomp1 : std_logic := '0'; SIGNAL ecomp0 : std_logic := '0'; SIGNAL going_empty : std_logic := '0'; SIGNAL leaving_empty : std_logic := '0'; SIGNAL ram_empty_comb : std_logic := '0'; ------------------------------------------------------------------------------- -- architecture begins here ------------------------------------------------------------------------------- BEGIN rst_i <= RST; --SRST gsrst : IF (C_HAS_SRST=1) GENERATE srst_i <= SRST; END GENERATE gsrst; --No SRST nosrst : IF (C_HAS_SRST=0) GENERATE srst_i <= '0'; END GENERATE nosrst; gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN diff_count <= wr_pntr - rd_pntr; gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count; DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ; END GENERATE; gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE DATA_COUNT <= diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH); END GENERATE; END GENERATE gdc; gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE DATA_COUNT <= (OTHERS => '0'); END GENERATE gndc; ------------------------------------------------------------------------------- --Calculate WR_ACK based on C_WR_ACK_LOW parameters ------------------------------------------------------------------------------- gwalow : IF (C_WR_ACK_LOW = 0) GENERATE WR_ACK <= wr_ack_i; END GENERATE gwalow; gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE WR_ACK <= NOT wr_ack_i; END GENERATE gwahgh; ------------------------------------------------------------------------------- --Calculate OVERFLOW based on C_OVERFLOW_LOW parameters ------------------------------------------------------------------------------- govlow : IF (C_OVERFLOW_LOW = 0) GENERATE OVERFLOW <= overflow_i; END GENERATE govlow; govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE OVERFLOW <= NOT overflow_i; END GENERATE govhgh; ------------------------------------------------------------------------------- --Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings ------------------------------------------------------------------------------- gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE gnvl : IF (C_VALID_LOW = 0) GENERATE VALID <= valid_d1; END GENERATE gnvl; gnvh : IF (C_VALID_LOW = 1) GENERATE VALID <= NOT valid_d1; END GENERATE gnvh; END GENERATE gvlat1; ------------------------------------------------------------------------------- -- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings ------------------------------------------------------------------------------- guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE UNDERFLOW <= underflow_i; END GENERATE gnul; gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE UNDERFLOW <= NOT underflow_i; END GENERATE gnuh; END GENERATE guflat1; FULL <= full_i; ALMOST_FULL <= almost_full_i; EMPTY <= empty_i; ALMOST_EMPTY <= almost_empty_i; write_allow <= WR_EN AND (NOT full_i); read_allow <= RD_EN AND (NOT empty_i); wrptr_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN wr_pntr <= (OTHERS => '0'); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN wr_pntr <= (OTHERS => '0') AFTER C_TCQ; ELSIF (write_allow = '1') THEN wr_pntr <= wr_pntr + "1" AFTER C_TCQ; END IF; END IF; END PROCESS wrptr_proc; gecc_mem: IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE wr_mem : PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF (write_allow = '1') THEN memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ; END IF; END IF; END PROCESS wr_mem; END GENERATE gecc_mem; gnecc_mem: IF NOT (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE wr_mem : PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF (write_allow = '1') THEN memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ; END IF; END IF; END PROCESS wr_mem; END GENERATE gnecc_mem; rdptr_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN rd_pntr <= (OTHERS => '0'); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN rd_pntr <= (OTHERS => '0') AFTER C_TCQ; ELSIF (read_allow = '1') THEN rd_pntr <= rd_pntr + "1" AFTER C_TCQ; END IF; END IF; END PROCESS rdptr_proc; ------------------------------------------------------------------------------- -- Generate DOUT for common clock low latency FIFO ------------------------------------------------------------------------------- gll_dout: IF(C_FIFO_TYPE = 2) GENERATE SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q; dout_reg : PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN dout_q <= dout_i AFTER C_TCQ; END IF; END PROCESS dout_reg; END GENERATE gll_dout; gnll_dout: IF (C_FIFO_TYPE < 2) GENERATE ------------------------------------------------------------------------------- -- Generate DOUT for BRAM ------------------------------------------------------------------------------- gbm_dout: IF (C_MEMORY_TYPE < 2) GENERATE BEGIN rd_mem : PROCESS (CLK) VARIABLE dout_tmp : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN IF (CLK'event AND CLK = '1') THEN IF (RST_FULL_FF = '1' OR srst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ; END IF; ELSIF (read_allow = '1') THEN dout_tmp := memory(conv_integer(rd_pntr)); IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) THEN IF (dout_tmp(dout_tmp'high) = '1') THEN IF (C_DOUT_WIDTH > 2) THEN dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 2) & NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ; ELSIF (C_DOUT_WIDTH = 2) THEN dout_i <= NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ; ELSE dout_i(0) <= dout_tmp(0) AFTER C_TCQ; END IF; dbiterr_i <= dout_tmp(dout_tmp'high) AFTER C_TCQ; sbiterr_i <= '0' AFTER C_TCQ; ELSE dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 0) AFTER C_TCQ; sbiterr_i <= dout_tmp(dout_tmp'high-1) AFTER C_TCQ; dbiterr_i <= '0' AFTER C_TCQ; END IF; ELSE dout_i <= dout_tmp AFTER C_TCQ; END IF; END IF; END IF; END PROCESS rd_mem; END GENERATE gbm_dout; ------------------------------------------------------------------------------- -- Generate DOUT for DRAM ------------------------------------------------------------------------------- gdm_dout: IF (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3) GENERATE rd_mem : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN IF (C_USE_DOUT_RST = 1) THEN dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); END IF; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ; END IF; ELSIF (read_allow = '1') THEN dout_i <= memory(conv_integer(rd_pntr)) AFTER C_TCQ; END IF; END IF; END PROCESS rd_mem; END GENERATE gdm_dout; END GENERATE gnll_dout; ------------------------------------------------------------------------------- -- Generate FULL flag ------------------------------------------------------------------------------- comp1 <= '1' WHEN (rd_pntr = (wr_pntr + "1")) ELSE '0'; comp0 <= '1' WHEN (rd_pntr = wr_pntr) ELSE '0'; going_full <= (comp1 AND write_allow AND NOT read_allow); leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN; ram_full_comb <= going_full OR (NOT leaving_full AND full_i); full_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSE full_i <= ram_full_comb AFTER C_TCQ; END IF; END IF; END PROCESS full_proc; ------------------------------------------------------------------------------- -- Generate ALMOST_FULL flag ------------------------------------------------------------------------------- gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE SIGNAL fcomp2 : std_logic := '0'; SIGNAL going_afull : std_logic := '0'; SIGNAL leaving_afull : std_logic := '0'; SIGNAL ram_afull_comb : std_logic := '0'; BEGIN fcomp2 <= '1' WHEN (rd_pntr = (wr_pntr + "10")) ELSE '0'; going_afull <= (fcomp2 AND write_allow AND NOT read_allow); leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN; ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i); af_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSE almost_full_i <= ram_afull_comb AFTER C_TCQ; END IF; END IF; END PROCESS af_proc; END GENERATE gaf_ss; ------------------------------------------------------------------------------- -- Generate EMPTY flag ------------------------------------------------------------------------------- ecomp1 <= '1' WHEN (wr_pntr = (rd_pntr + "1")) ELSE '0'; ecomp0 <= '1' WHEN (wr_pntr = rd_pntr) ELSE '0'; going_empty <= (ecomp1 AND NOT write_allow AND read_allow); leaving_empty <= (ecomp0 AND write_allow); ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i); empty_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN empty_i <= '1' AFTER C_TCQ; ELSE empty_i <= ram_empty_comb AFTER C_TCQ; END IF; END IF; END PROCESS empty_proc; ------------------------------------------------------------------------------- -- Generate ALMOST_EMPTY flag ------------------------------------------------------------------------------- gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE SIGNAL ecomp2 : std_logic := '0'; SIGNAL going_aempty : std_logic := '0'; SIGNAL leaving_aempty : std_logic := '0'; SIGNAL ram_aempty_comb : std_logic := '1'; BEGIN ecomp2 <= '1' WHEN (wr_pntr = (rd_pntr + "10")) ELSE '0'; going_aempty <= (ecomp2 AND NOT write_allow AND read_allow); leaving_aempty <= (ecomp1 AND write_allow AND NOT read_allow); ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i); ae_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN almost_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN almost_empty_i <= '1' AFTER C_TCQ; ELSE almost_empty_i <= ram_aempty_comb AFTER C_TCQ; END IF; END IF; END PROCESS ae_proc; END GENERATE gae_ss; ------------------------------------------------------------------------------- -- Generate PROG_FULL and PROG_EMPTY flags ------------------------------------------------------------------------------- gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE SIGNAL diff_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL write_allow_q : std_logic := '0'; SIGNAL read_allow_q : std_logic := '0'; SIGNAL write_only : std_logic := '0'; SIGNAL write_only_q : std_logic := '0'; SIGNAL read_only : std_logic := '0'; SIGNAL read_only_q : std_logic := '0'; SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL); SIGNAL prog_empty_i : std_logic := '1'; CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_FULL_THRESH_ASSERT_VAL - 2, -- FWFT C_PROG_FULL_THRESH_ASSERT_VAL); -- STD CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_FULL_THRESH_NEGATE_VAL - 2, -- FWFT C_PROG_FULL_THRESH_NEGATE_VAL); -- STD CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, C_PROG_EMPTY_THRESH_ASSERT_VAL); CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, C_PROG_EMPTY_THRESH_NEGATE_VAL); BEGIN write_only <= write_allow AND NOT read_allow; write_only_q <= write_allow_q AND NOT read_allow_q; read_only <= read_allow AND NOT write_allow; read_only_q <= read_allow_q AND NOT write_allow_q; wr_rd_q_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN write_allow_q <= '0'; read_allow_q <= '0'; diff_pntr <= (OTHERS => '0'); diff_pntr_pe <= (OTHERS => '0'); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN write_allow_q <= '0' AFTER C_TCQ; read_allow_q <= '0' AFTER C_TCQ; diff_pntr <= (OTHERS => '0') AFTER C_TCQ; diff_pntr_pe <= (OTHERS => '0') AFTER C_TCQ; ELSE write_allow_q <= write_allow AFTER C_TCQ; read_allow_q <= read_allow AFTER C_TCQ; -- Add 1 to the difference pointer value when only write happens. IF (write_only = '1') THEN diff_pntr <= wr_pntr - rd_pntr + "1" AFTER C_TCQ; ELSE diff_pntr <= wr_pntr - rd_pntr AFTER C_TCQ; END IF; -- Add 1 to the difference pointer value when write or both write & read or no write & read happen. IF (read_only = '1') THEN diff_pntr_pe <= wr_pntr - rd_pntr - "1" AFTER C_TCQ; ELSE diff_pntr_pe <= wr_pntr - rd_pntr AFTER C_TCQ; END IF; END IF; END IF; END PROCESS wr_rd_q_proc; ------------------------------------------------------------------------------- -- Generate PROG_FULL flag ------------------------------------------------------------------------------- gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE ------------------------------------------------------------------------------- -- Generate PROG_FULL for single programmable threshold constant ------------------------------------------------------------------------------- gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE pf1_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf1_proc; END GENERATE gpf1; ------------------------------------------------------------------------------- -- Generate PROG_FULL for multiple programmable threshold constants ------------------------------------------------------------------------------- gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE pf2_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf2_proc; END GENERATE gpf2; ------------------------------------------------------------------------------- -- Generate PROG_FULL for single programmable threshold input port ------------------------------------------------------------------------------- gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pf_assert_val <= PROG_FULL_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH; pf3_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr) > pf_assert_val) THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN IF (read_only_q = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= '1' AFTER C_TCQ; END IF; ELSE prog_full_i <= '0' AFTER C_TCQ; END IF; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf3_proc; END GENERATE gpf3; ------------------------------------------------------------------------------- -- Generate PROG_FULL for multiple programmable threshold input ports ------------------------------------------------------------------------------- gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pf_assert_val <= PROG_FULL_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT; pf_negate_val <= PROG_FULL_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE; pf4_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr) >= pf_assert_val) THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR (conv_integer(diff_pntr) < pf_negate_val)) THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf4_proc; END GENERATE gpf4; PROG_FULL <= prog_full_i; END GENERATE gpf; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY flag ------------------------------------------------------------------------------- gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for single programmable threshold constant ------------------------------------------------------------------------------- gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE pe1_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe1_proc; END GENERATE gpe1; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for multiple programmable threshold constants ------------------------------------------------------------------------------- gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE pe2_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe2_proc; END GENERATE gpe2; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for single programmable threshold input port ------------------------------------------------------------------------------- gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH; pe3_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN IF (write_only_q = '1') THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= '1' AFTER C_TCQ; END IF; ELSE prog_empty_i <= '0' AFTER C_TCQ; END IF; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe3_proc; END GENERATE gpe3; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for multiple programmable threshold input ports ------------------------------------------------------------------------------- gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL pe_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT; pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE; pe4_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR (conv_integer(diff_pntr_pe) > pe_negate_val)) THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe4_proc; END GENERATE gpe4; PROG_EMPTY <= prog_empty_i; END GENERATE gpe; END GENERATE gpf_pe; ------------------------------------------------------------------------------- -- overflow_i generation: Synchronous FIFO ------------------------------------------------------------------------------- govflw: IF (C_HAS_OVERFLOW = 1) GENERATE povflw: PROCESS (CLK) BEGIN IF CLK'event AND CLK = '1' THEN overflow_i <= full_i AND WR_EN after C_TCQ; END IF; END PROCESS povflw; END GENERATE govflw; ------------------------------------------------------------------------------- -- underflow_i generation: Synchronous FIFO ------------------------------------------------------------------------------- gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE punflw: PROCESS (CLK) BEGIN IF CLK'event AND CLK = '1' THEN underflow_i <= empty_i and RD_EN after C_TCQ; END IF; END PROCESS punflw; END GENERATE gunflw; ------------------------------------------------------------------------------- -- wr_ack_i generation: Synchronous FIFO ------------------------------------------------------------------------------- gwack: IF (C_HAS_WR_ACK = 1) GENERATE pwack: PROCESS (CLK,rst_i) BEGIN IF rst_i = '1' THEN wr_ack_i <= '0' after C_TCQ; ELSIF CLK'event AND CLK = '1' THEN wr_ack_i <= '0' after C_TCQ; IF srst_i = '1' THEN wr_ack_i <= '0' after C_TCQ; ELSIF WR_EN = '1' THEN IF full_i /= '1' THEN wr_ack_i <= '1' after C_TCQ; END IF; END IF; END IF; END PROCESS pwack; END GENERATE gwack; ----------------------------------------------------------------------------- -- valid_i generation: Synchronous FIFO ----------------------------------------------------------------------------- gvld_i: IF (C_HAS_VALID = 1) GENERATE PROCESS (rst_i , CLK ) BEGIN IF rst_i = '1' THEN valid_i <= '0' after C_TCQ; ELSIF CLK'event AND CLK = '1' THEN IF srst_i = '1' THEN valid_i <= '0' after C_TCQ; ELSE --srst_i=0 -- Setup default value for underflow and valid valid_i <= '0' after C_TCQ; IF RD_EN = '1' THEN IF empty_i /= '1' THEN valid_i <= '1' after C_TCQ; END IF; END IF; END IF; END IF; END PROCESS; END GENERATE gvld_i; ----------------------------------------------------------------------------- --Delay Valid AND DOUT --if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD ----------------------------------------------------------------------------- gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE gv0: IF (C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0)) AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE PROCESS (rst_i , CLK ) BEGIN IF (rst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN IF (CLK'event AND CLK = '1') THEN DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; END IF; IF (C_USE_ECC = 0) THEN SBITERR <= '0' after C_TCQ; DBITERR <= '0' after C_TCQ; END IF; ram_rd_en_d1 <= '0' after C_TCQ; valid_d1 <= '0' after C_TCQ; ELSIF (CLK 'event AND CLK = '1') THEN ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ; valid_d1 <= valid_i after C_TCQ; IF (srst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; ram_rd_en_d1 <= '0' after C_TCQ; valid_d1 <= '0' after C_TCQ; ELSIF (ram_rd_en_d1 = '1') THEN DOUT <= dout_i after C_TCQ; SBITERR <= sbiterr_i after C_TCQ; DBITERR <= dbiterr_i after C_TCQ; END IF; END IF; END PROCESS; END GENERATE gv0; END GENERATE gnll_fifo1; gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0)) AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE valid_d1 <= valid_i; DOUT <= dout_i; SBITERR <= sbiterr_i; DBITERR <= dbiterr_i; END GENERATE gv1; END behavioral; --############################################################################# --############################################################################# -- Preload Latency 0 (First-Word Fall-Through) Module --############################################################################# --############################################################################# LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fifo_generator_v8_2_bhv_preload0 IS GENERIC ( C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_HAS_RST : integer := 0; C_HAS_SRST : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USERVALID_LOW : integer := 0; C_USERUNDERFLOW_LOW : integer := 0; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT ( RD_CLK : IN std_logic; RD_RST : IN std_logic; SRST : IN std_logic; RD_EN : IN std_logic; FIFOEMPTY : IN std_logic; FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FIFOSBITERR : IN std_logic; FIFODBITERR : IN std_logic; USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); USERVALID : OUT std_logic; USERUNDERFLOW : OUT std_logic; USEREMPTY : OUT std_logic; USERALMOSTEMPTY : OUT std_logic; RAMVALID : OUT std_logic; FIFORDEN : OUT std_logic; USERSBITERR : OUT std_logic := '0'; USERDBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_bhv_preload0; ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_preload0 IS ----------------------------------------------------------------------------- -- FUNCTION hexstr_to_std_logic_vec -- Returns a std_logic_vector for a hexadecimal string ------------------------------------------------------------------------------- FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index4)+j < size THEN result((index4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); SIGNAL preloadstage1 : std_logic := '0'; SIGNAL preloadstage2 : std_logic := '0'; SIGNAL ram_valid_i : std_logic := '0'; SIGNAL read_data_valid_i : std_logic := '0'; SIGNAL ram_regout_en : std_logic := '0'; SIGNAL ram_rd_en : std_logic := '0'; SIGNAL empty_i : std_logic := '1'; SIGNAL empty_q : std_logic := '1'; SIGNAL rd_en_q : std_logic := '0'; SIGNAL almost_empty_i : std_logic := '1'; SIGNAL almost_empty_q : std_logic := '1'; SIGNAL rd_rst_i : std_logic := '0'; SIGNAL srst_i : std_logic := '0'; BEGIN -- behavioral grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE rd_rst_i <= RD_RST; end generate grst; ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE rd_rst_i <= '0'; END GENERATE ngrst; --SRST gsrst : IF (C_HAS_SRST=1) GENERATE srst_i <= SRST; END GENERATE gsrst; --SRST ngsrst : IF (C_HAS_SRST=0) GENERATE srst_i <= '0'; END GENERATE ngsrst; gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE -------------------------------------------------------------------------------- -- preloadstage2 indicates that stage2 needs to be updated. This is true -- whenever read_data_valid is false, and RAM_valid is true. -------------------------------------------------------------------------------- preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN); -------------------------------------------------------------------------------- -- preloadstage1 indicates that stage1 needs to be updated. This is true -- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is -- false (indicating that Stage1 needs updating), or preloadstage2 is active -- (indicating that Stage2 is going to update, so Stage1, therefore, must -- also be updated to keep it valid. -------------------------------------------------------------------------------- preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY)); -------------------------------------------------------------------------------- -- Calculate RAM_REGOUT_EN -- The output registers are controlled by the ram_regout_en signal. -- These registers should be updated either when the output in Stage2 is -- invalid (preloadstage2), OR when the user is reading, in which case the -- Stage2 value will go invalid unless it is replenished. -------------------------------------------------------------------------------- ram_regout_en <= preloadstage2; -------------------------------------------------------------------------------- -- Calculate RAM_RD_EN -- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to -- update the value in Stage1. -- One case when this happens is when preloadstage1=true, which indicates -- that the data in Stage1 or Stage2 is invalid, and needs to automatically -- be updated. -- The other case is when the user is reading from the FIFO, which guarantees -- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is -- replinished by data from the memory. So, as long as the RAM has data in it, -- a read of the RAM should occur. -------------------------------------------------------------------------------- ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1; END GENERATE gnll_fifo; gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE SIGNAL empty_d1 : STD_LOGIC := '1'; SIGNAL fe_of_empty : STD_LOGIC := '0'; SIGNAL curr_state : STD_LOGIC := '0'; SIGNAL next_state : STD_LOGIC := '0'; SIGNAL leaving_empty_fwft : STD_LOGIC := '0'; SIGNAL going_empty_fwft : STD_LOGIC := '0'; BEGIN fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN) BEGIN CASE curr_state IS WHEN '0' => IF (FIFOEMPTY = '0') THEN next_state <= '1'; ELSE next_state <= '0'; END IF; WHEN '1' => IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN next_state <= '0'; ELSE next_state <= '1'; END IF; WHEN OTHERS => next_state <= '0'; END CASE; END PROCESS fsm_proc; empty_reg: PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN empty_d1 <= '1'; empty_i <= '1'; ram_valid_i <= '0'; curr_state <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (srst_i = '1') THEN empty_d1 <= '1' AFTER C_TCQ; empty_i <= '1' AFTER C_TCQ; ram_valid_i <= '0' AFTER C_TCQ; curr_state <= '0' AFTER C_TCQ; ELSE empty_d1 <= FIFOEMPTY AFTER C_TCQ; curr_state <= next_state AFTER C_TCQ; empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ; ram_valid_i <= next_state AFTER C_TCQ; END IF; END IF; END PROCESS empty_reg; fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY); prege: PROCESS (curr_state, FIFOEMPTY, RD_EN) BEGIN CASE curr_state IS WHEN '0' => IF (FIFOEMPTY = '0') THEN ram_regout_en <= '1'; ram_rd_en <= '1'; ELSE ram_regout_en <= '0'; ram_rd_en <= '0'; END IF; WHEN '1' => IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN ram_regout_en <= '1'; ram_rd_en <= '1'; ELSE ram_regout_en <= '0'; ram_rd_en <= '0'; END IF; WHEN OTHERS => ram_regout_en <= '0'; ram_rd_en <= '0'; END CASE; END PROCESS prege; ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty BEGIN CASE curr_state IS WHEN '0' => leaving_empty_fwft <= fe_of_empty; WHEN '1' => leaving_empty_fwft <= '1'; WHEN OTHERS => leaving_empty_fwft <= '0'; END CASE; END PROCESS ple; pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty BEGIN CASE curr_state IS WHEN '1' => IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN going_empty_fwft <= '1'; ELSE going_empty_fwft <= '0'; END IF; WHEN OTHERS => going_empty_fwft <= '0'; END CASE; END PROCESS pge; END GENERATE gll_fifo; -------------------------------------------------------------------------------- -- Calculate ram_valid -- ram_valid indicates that the data in Stage1 is valid. -- -- If the RAM is being read from on this clock cycle (ram_rd_en=1), then -- ram_valid is certainly going to be true. -- If the RAM is not being read from, but the output registers are being -- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, -- therefore causing ram_valid to be false. -- Otherwise, ram_valid will remain unchanged. -------------------------------------------------------------------------------- gvalid: IF (C_FIFO_TYPE < 2) GENERATE regout_valid: PROCESS (RD_CLK, rd_rst_i) BEGIN -- PROCESS regout_valid IF rd_rst_i = '1' THEN -- asynchronous reset (active high) ram_valid_i <= '0' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge IF srst_i = '1' THEN -- synchronous reset (active high) ram_valid_i <= '0' after C_TCQ; ELSE IF ram_rd_en = '1' THEN ram_valid_i <= '1' after C_TCQ; ELSE IF ram_regout_en = '1' THEN ram_valid_i <= '0' after C_TCQ; ELSE ram_valid_i <= ram_valid_i after C_TCQ; END IF; END IF; END IF; END IF; END PROCESS regout_valid; END GENERATE gvalid; -------------------------------------------------------------------------------- -- Calculate READ_DATA_VALID -- READ_DATA_VALID indicates whether the value in Stage2 is valid or not. -- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1, -- such that the data in Stage1 is propogated into Stage2. -------------------------------------------------------------------------------- regout_dvalid : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i='1') THEN read_data_valid_i <= '0' after C_TCQ; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (srst_i='1') THEN read_data_valid_i <= '0' after C_TCQ; ELSE read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ; END IF; END IF; --RD_CLK END PROCESS regout_dvalid; ------------------------------------------------------------------------------- -- Calculate EMPTY -- Defined as the inverse of READ_DATA_VALID -- -- Description: -- -- If read_data_valid_i indicates that the output is not valid, -- and there is no valid data on the output of the ram to preload it -- with, then we will report empty. -- -- If there is no valid data on the output of the ram and we are -- reading, then the FIFO will go empty. -- ------------------------------------------------------------------------------- gempty: IF (C_FIFO_TYPE < 2) GENERATE regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i) BEGIN IF (rd_rst_i='1') THEN empty_i <= '1' after C_TCQ; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (srst_i='1') THEN empty_i <= '1' after C_TCQ; ELSE empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ; END IF; END IF; --RD_CLK END PROCESS regout_empty; END GENERATE gempty; regout_empty_q: PROCESS (RD_CLK) BEGIN -- PROCESS regout_rd_en IF RD_CLK'event AND RD_CLK = '1' THEN -- empty_q <= empty_i after C_TCQ; END IF; END PROCESS regout_empty_q; regout_rd_en: PROCESS (RD_CLK) BEGIN -- PROCESS regout_rd_en IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge rd_en_q <= RD_EN after C_TCQ; END IF; END PROCESS regout_rd_en; ------------------------------------------------------------------------------- -- Calculate user_almost_empty -- user_almost_empty is defined such that, unless more words are written -- to the FIFO, the next read will cause the FIFO to go EMPTY. -- -- In most cases, whenever the output registers are updated (due to a user -- read or a preload condition), then user_almost_empty will update to -- whatever RAM_EMPTY is. -- -- The exception is when the output is valid, the user is not reading, and -- Stage1 is not empty. In this condition, Stage1 will be preloaded from the -- memory, so we need to make sure user_almost_empty deasserts properly under -- this condition. ------------------------------------------------------------------------------- regout_aempty: PROCESS (RD_CLK, rd_rst_i) BEGIN -- PROCESS regout_empty IF rd_rst_i = '1' THEN -- asynchronous reset (active high) almost_empty_i <= '1' after C_TCQ; almost_empty_q <= '1' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge IF srst_i = '1' THEN -- synchronous reset (active high) almost_empty_i <= '1' after C_TCQ; almost_empty_q <= '1' after C_TCQ; ELSE IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN almost_empty_i <= FIFOEMPTY after C_TCQ; END IF; almost_empty_q <= almost_empty_i after C_TCQ; END IF; END IF; END PROCESS regout_aempty; USEREMPTY <= empty_i; USERALMOSTEMPTY <= almost_empty_i; FIFORDEN <= ram_rd_en; RAMVALID <= ram_valid_i; guvh: IF C_USERVALID_LOW=0 GENERATE USERVALID <= read_data_valid_i; END GENERATE guvh; guvl: if C_USERVALID_LOW=1 GENERATE USERVALID <= NOT read_data_valid_i; END GENERATE guvl; gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE USERUNDERFLOW <= empty_q AND rd_en_q; END GENERATE gufh; gufl: if C_USERUNDERFLOW_LOW=1 GENERATE USERUNDERFLOW <= NOT (empty_q AND rd_en_q); END GENERATE gufl; regout_lat0: PROCESS (RD_CLK, rd_rst_i) BEGIN -- PROCESS regout_lat0 IF (rd_rst_i = '1') THEN -- asynchronous reset (active high) IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF USERSBITERR <= '0' after C_TCQ; USERDBITERR <= '0' after C_TCQ; END IF; -- DRAM resets asynchronously IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; -- BRAM resets synchronously IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN IF (RD_CLK'event AND RD_CLK = '1') THEN USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; END IF; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge IF (srst_i = '1') THEN -- synchronous reset (active high) IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF USERSBITERR <= '0' after C_TCQ; USERDBITERR <= '0' after C_TCQ; END IF; IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high) USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; ELSE IF (ram_regout_en = '1') THEN USERDATA_int <= FIFODATA after C_TCQ; USERSBITERR <= FIFOSBITERR after C_TCQ; USERDBITERR <= FIFODBITERR after C_TCQ; END IF; END IF; END IF; END PROCESS regout_lat0; USERDATA <= USERDATA_int ; -- rle, fixed bug R62 END behavioral; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Top-level Behavioral Model for Conventional FIFO ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY XilinxCoreLib; USE XilinxCoreLib.fifo_generator_v8_2_bhv_as; USE XilinxCoreLib.fifo_generator_v8_2_bhv_ss; ------------------------------------------------------------------------------- -- Top-level Entity Declaration - This is the top-level of the conventional -- FIFO Bhv Model ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2_conv IS GENERIC ( --------------------------------------------------------------------------- -- Generic Declarations --------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; --not used C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; --not used C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; --not used C_FAMILY : string := ""; --not used in bhv model C_FULL_FLAGS_RST_VAL : integer := 0; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; --not used C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; --not used in bhv model C_HAS_MEMINIT_FILE : integer := 0; --not used C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; --not used C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; --not used C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; --not used C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; --not used C_OPTIMIZATION_MODE : integer := 0; --not used C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; --not used in bhv model C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; --not used in bhv model C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; --not used C_MSGON_VAL : integer := 1; --not used in bhv model C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- BACKUP : IN std_logic := '0'; BACKUP_MARKER : IN std_logic := '0'; CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_CLK : IN std_logic := '0'; WR_RST : IN std_logic := '0'; RD_CLK : IN std_logic := '0'; RD_RST : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); -- WR_EN : IN std_logic; --Mandatory input RD_EN : IN std_logic; --Mandatory input --Mandatory input PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INT_CLK : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FULL : OUT std_logic; ALMOST_FULL : OUT std_logic; WR_ACK : OUT std_logic; OVERFLOW : OUT std_logic; EMPTY : OUT std_logic; ALMOST_EMPTY : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); PROG_FULL : OUT std_logic; PROG_EMPTY : OUT std_logic; SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_conv; ------------------------------------------------------------------------------- -- Definition of Parameters ------------------------------------------------------------------------------- -- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) -- C_COUNT_TYPE : --not used -- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus -- C_DEFAULT_VALUE : --not used -- C_DIN_WIDTH : Width of DIN bus -- C_DOUT_RST_VAL : Reset value of DOUT -- C_DOUT_WIDTH : Width of DOUT bus -- C_ENABLE_RLOCS : --not used -- C_FAMILY : not used in bhv model -- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) -- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag -- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag -- C_HAS_BACKUP : --not used -- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus -- C_HAS_INT_CLK : not used in bhv model -- C_HAS_MEMINIT_FILE : --not used -- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag -- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus -- C_HAS_RD_RST : --not used -- C_HAS_RST : 1=Core has Async Rst -- C_HAS_SRST : 1=Core has Sync Rst -- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag -- C_HAS_VALID : 1=Core has VALID flag -- C_HAS_WR_ACK : 1=Core has WR_ACK flag -- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus -- C_HAS_WR_RST : --not used -- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram -- 1=Common-Clock ShiftRam -- 2=Indep. Clocks Bram/Dram -- 3=Virtex-4 Built-in -- 4=Virtex-5 Built-in -- C_INIT_WR_PNTR_VAL : --not used -- C_MEMORY_TYPE : 1=Block RAM -- 2=Distributed RAM -- 3=Shift RAM -- 4=Built-in FIFO -- C_MIF_FILE_NAME : --not used -- C_OPTIMIZATION_MODE : --not used -- C_OVERFLOW_LOW : 1=OVERFLOW active low -- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 -- C_PRELOAD_REGS : 1=Use output registers -- C_PRIM_FIFO_TYPE : not used in bhv model -- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold -- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold -- C_PROG_EMPTY_TYPE : 0=No programmable empty -- 1=Single prog empty thresh constant -- 2=Multiple prog empty thresh constants -- 3=Single prog empty thresh input -- 4=Multiple prog empty thresh inputs -- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold -- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold -- C_PROG_FULL_TYPE : 0=No prog full -- 1=Single prog full thresh constant -- 2=Multiple prog full thresh constants -- 3=Single prog full thresh input -- 4=Multiple prog full thresh inputs -- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus -- C_RD_DEPTH : Depth of read interface (2^N) -- C_RD_FREQ : not used in bhv model -- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) -- C_UNDERFLOW_LOW : 1=UNDERFLOW active low -- C_USE_DOUT_RST : 1=Resets DOUT on RST -- C_USE_ECC : not used in bhv model -- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register -- C_USE_FIFO16_FLAGS : not used in bhv model -- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count -- C_VALID_LOW : 1=VALID active low -- C_WR_ACK_LOW : 1=WR_ACK active low -- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus -- C_WR_DEPTH : Depth of write interface (2^N) -- C_WR_FREQ : not used in bhv model -- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) -- C_WR_RESPONSE_LATENCY : --not used ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- BACKUP : Not used -- BACKUP_MARKER: Not used -- CLK : Clock -- DIN : Input data bus -- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag -- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag -- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag -- PROG_FULL_THRESH : Threshold for Programmable Full Flag -- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag -- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag -- RD_CLK : Read Domain Clock -- RD_EN : Read enable -- RD_RST : Not used -- RST : Asynchronous Reset -- SRST : Synchronous Reset -- WR_CLK : Write Domain Clock -- WR_EN : Write enable -- WR_RST : Not used -- INT_CLK : Internal Clock -- ALMOST_EMPTY : One word remaining in FIFO -- ALMOST_FULL : One empty space remaining in FIFO -- DATA_COUNT : Number of data words in fifo( synchronous to CLK) -- DOUT : Output data bus -- EMPTY : Empty flag -- FULL : Full flag -- OVERFLOW : Last write rejected -- PROG_EMPTY : Programmable Empty Flag -- PROG_FULL : Programmable Full Flag -- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) -- UNDERFLOW : Last read rejected -- VALID : Last read acknowledged, DOUT bus VALID -- WR_ACK : Last write acknowledged -- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) -- SBITERR : Single Bit ECC Error Detected -- DBITERR : Double Bit ECC Error Detected ------------------------------------------------------------------------------- ARCHITECTURE behavioral OF fifo_generator_v8_2_conv IS ----------------------------------------------------------------------------- -- FUNCTION two_comp -- Returns a 2's complement value ------------------------------------------------------------------------------- FUNCTION two_comp( vect : std_logic_vector) RETURN std_logic_vector IS VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0); VARIABLE toggle : integer := 0; BEGIN FOR i IN 0 TO vect'high LOOP IF (toggle = 1) THEN IF (vect(i) = '0') THEN local_vect(i) := '1'; ELSE local_vect(i) := '0'; END IF; ELSE local_vect(i) := vect(i); IF (vect(i) = '1') THEN toggle := 1; END IF; END IF; END LOOP; RETURN local_vect; END two_comp; ----------------------------------------------------------------------------- -- FUNCTION int_2_std_logic_vector -- Returns a std_logic_vector for an integer value for a given width. ------------------------------------------------------------------------------- FUNCTION int_2_std_logic_vector( value, bitwidth : integer ) RETURN std_logic_vector IS VARIABLE running_value : integer := value; VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0); BEGIN IF (value < 0) THEN running_value := -1 * value; END IF; FOR i IN 0 TO bitwidth-1 LOOP IF running_value MOD 2 = 0 THEN running_result(i) := '0'; ELSE running_result(i) := '1'; END IF; running_value := running_value/2; END LOOP; IF (value < 0) THEN -- find the 2s complement RETURN two_comp(running_result); ELSE RETURN running_result; END IF; END int_2_std_logic_vector; COMPONENT fifo_generator_v8_2_bhv_as GENERIC ( -------------------------------------------------------------------------------- -- Generic Declarations -------------------------------------------------------------------------------- C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 2; C_HAS_RST : integer := 1; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 2; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); RD_CLK : IN std_logic; RD_EN : IN std_logic; RD_EN_USER : IN std_logic; RST : IN std_logic; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; WR_RST : IN std_logic; RD_RST : IN std_logic; WR_CLK : IN std_logic; WR_EN : IN std_logic; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; USER_EMPTY_FB : IN std_logic := '1'; ALMOST_EMPTY : OUT std_logic; ALMOST_FULL : OUT std_logic; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); EMPTY : OUT std_logic; FULL : OUT std_logic; OVERFLOW : OUT std_logic; PROG_EMPTY : OUT std_logic; PROG_FULL : OUT std_logic; VALID : OUT std_logic; RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); UNDERFLOW : OUT std_logic; WR_ACK : OUT std_logic; WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); DBITERR : OUT std_logic := '0'; SBITERR : OUT std_logic := '0' ); END COMPONENT; COMPONENT fifo_generator_v8_2_bhv_ss GENERIC ( -------------------------------------------------------------------------------- -- Generic Declarations (alphabetical) -------------------------------------------------------------------------------- C_DATA_COUNT_WIDTH : integer := 2; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RST : integer := 0; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_ECC : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- CLK : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); RD_EN : IN std_logic := '0'; RST : IN std_logic := '0'; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_EN : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; ALMOST_EMPTY : OUT std_logic; ALMOST_FULL : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); EMPTY : OUT std_logic; FULL : OUT std_logic; OVERFLOW : OUT std_logic; PROG_EMPTY : OUT std_logic; PROG_FULL : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; WR_ACK : OUT std_logic; DBITERR : OUT std_logic := '0'; SBITERR : OUT std_logic := '0' ); END COMPONENT; COMPONENT fifo_generator_v8_2_bhv_preload0 GENERIC ( C_DOUT_RST_VAL : string; C_DOUT_WIDTH : integer; C_HAS_RST : integer; C_HAS_SRST : integer; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USERVALID_LOW : integer := 0; C_USERUNDERFLOW_LOW : integer := 0; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT ( RD_CLK : IN std_logic; RD_RST : IN std_logic; SRST : IN std_logic; RD_EN : IN std_logic; FIFOEMPTY : IN std_logic; FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FIFOSBITERR : IN std_logic; FIFODBITERR : IN std_logic; USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); USERVALID : OUT std_logic; USERUNDERFLOW : OUT std_logic; USEREMPTY : OUT std_logic; USERALMOSTEMPTY : OUT std_logic; RAMVALID : OUT std_logic; FIFORDEN : OUT std_logic; USERSBITERR : OUT std_logic; USERDBITERR : OUT std_logic ); END COMPONENT; -- Constant to have clock to register delay CONSTANT C_TCQ : time := 100 ps; SIGNAL zero : std_logic := '0'; SIGNAL CLK_INT : std_logic := '0'; ----------------------------------------------------------------------------- -- Internal Signals for delayed input signals -- All the input signals except Clock are delayed by 100 ps and then given to -- the models. ----------------------------------------------------------------------------- SIGNAL rst_delayed : std_logic := '0'; SIGNAL srst_delayed : std_logic := '0'; SIGNAL wr_rst_delayed : std_logic := '0'; SIGNAL rd_rst_delayed : std_logic := '0'; SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wr_en_delayed : std_logic := '0'; SIGNAL rd_en_delayed : std_logic := '0'; SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL injectdbiterr_delayed : std_logic := '0'; SIGNAL injectsbiterr_delayed : std_logic := '0'; ----------------------------------------------------------------------------- -- Internal Signals -- In the normal case, these signals tie directly to the FIFO's inputs and -- outputs. -- In the case of Preload Latency 0 or 1, these are the intermediate -- signals between the internal FIFO and the preload logic. ----------------------------------------------------------------------------- SIGNAL rd_en_fifo_in : std_logic; SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); SIGNAL empty_fifo_out : std_logic; SIGNAL almost_empty_fifo_out : std_logic; SIGNAL valid_fifo_out : std_logic; SIGNAL underflow_fifo_out : std_logic; SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL SS_FWFT_RD : std_logic := '0' ; SIGNAL SS_FWFT_WR : std_logic := '0' ; SIGNAL FULL_int : std_logic ; SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); signal valid_p0_out : std_logic; signal empty_p0_out : std_logic; signal underflow_p0_out : std_logic; signal almost_empty_p0_out : std_logic; signal empty_p0_out_q : std_logic; signal almost_empty_p0_out_q : std_logic; SIGNAL ram_valid : std_logic; --Internal signal used to monitor the --ram_valid state signal rst_fwft : std_logic; signal sbiterr_fifo_out : std_logic; signal dbiterr_fifo_out : std_logic; signal wr_rst_i : std_logic := '0'; signal rd_rst_i : std_logic := '0'; signal rst_i : std_logic := '0'; signal rst_full_gen_i : std_logic := '0'; signal rst_full_ff_i : std_logic := '0'; signal rst_2_sync : std_logic := '0'; signal clk_2_sync : std_logic := '0'; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ----------------------------------------------------------------------------- -- FUNCTION log2roundup -- Returns a log2 of the input value ----------------------------------------------------------------------------- FUNCTION log2roundup ( data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt 2; END LOOP; END IF; RETURN width; END log2roundup; CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL); CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0); CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0); BEGIN rst_delayed <= RST AFTER C_TCQ; srst_delayed <= SRST AFTER C_TCQ; wr_rst_delayed <= WR_RST AFTER C_TCQ; rd_rst_delayed <= RD_RST AFTER C_TCQ; din_delayed <= DIN AFTER C_TCQ; wr_en_delayed <= WR_EN AFTER C_TCQ; rd_en_delayed <= RD_EN AFTER C_TCQ; prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ; prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ; prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ; prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ; prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ; prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ; injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ; injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ; --Assign Ground Signal zero <= '0'; ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models for Virtex-4, Virtex-5, Virtex-6 and 7-Series FPGA's built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information." SEVERITY FAILURE; -- ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE; ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE; ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE; gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1)) GENERATE fgss : fifo_generator_v8_2_bhv_ss GENERIC MAP ( C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_DIN_WIDTH => C_DIN_WIDTH, C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => C_DOUT_WIDTH, C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_HAS_RST => C_HAS_RST, C_HAS_SRST => C_HAS_SRST, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_HAS_VALID => C_HAS_VALID, C_HAS_WR_ACK => C_HAS_WR_ACK, C_MEMORY_TYPE => C_MEMORY_TYPE, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL, C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE, C_RD_DEPTH => C_RD_DEPTH, C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_USE_ECC => C_USE_ECC, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, C_VALID_LOW => C_VALID_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DEPTH => C_WR_DEPTH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH, C_TCQ => C_TCQ, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_FIFO_TYPE => C_FIFO_TYPE ) PORT MAP( --Inputs CLK => CLK, DIN => din_delayed, PROG_EMPTY_THRESH => prog_empty_thresh_delayed, PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed, PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed, PROG_FULL_THRESH => prog_full_thresh_delayed, PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed, PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed, RD_EN => rd_en_fifo_in, RST => rst_i, SRST => srst_delayed, RST_FULL_GEN => rst_full_gen_i, RST_FULL_FF => rst_full_ff_i, WR_EN => wr_en_delayed, INJECTDBITERR => injectdbiterr_delayed, INJECTSBITERR => injectsbiterr_delayed, --Outputs ALMOST_EMPTY => almost_empty_fifo_out, ALMOST_FULL => ALMOST_FULL, DATA_COUNT => data_count_fifo_out, DOUT => dout_fifo_out, EMPTY => empty_fifo_out, FULL => FULL_int, OVERFLOW => OVERFLOW, PROG_EMPTY => PROG_EMPTY, PROG_FULL => PROG_FULL, UNDERFLOW => underflow_fifo_out, VALID => valid_fifo_out, WR_ACK => WR_ACK, DBITERR => dbiterr_fifo_out, SBITERR => sbiterr_fifo_out ); END GENERATE gen_ss; gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE fgas : fifo_generator_v8_2_bhv_as GENERIC MAP ( C_DIN_WIDTH => C_DIN_WIDTH, C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => C_DOUT_WIDTH, C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT, C_HAS_RST => C_HAS_RST, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_HAS_VALID => C_HAS_VALID, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT, C_MEMORY_TYPE => C_MEMORY_TYPE, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL, C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE, C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH, C_RD_DEPTH => C_RD_DEPTH, C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_USE_ECC => C_USE_ECC, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, C_VALID_LOW => C_VALID_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH, C_WR_DEPTH => C_WR_DEPTH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH, C_TCQ => C_TCQ, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_FIFO_TYPE => C_FIFO_TYPE ) PORT MAP( --Inputs WR_CLK => WR_CLK, RD_CLK => RD_CLK, RST => rst_i, RST_FULL_GEN => rst_full_gen_i, RST_FULL_FF => rst_full_ff_i, WR_RST => wr_rst_i, RD_RST => rd_rst_i, DIN => din_delayed, RD_EN => rd_en_fifo_in, WR_EN => wr_en_delayed, RD_EN_USER => rd_en_delayed, PROG_FULL_THRESH => prog_full_thresh_delayed, PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed, PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed, PROG_EMPTY_THRESH => prog_empty_thresh_delayed, PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed, PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed, INJECTDBITERR => injectdbiterr_delayed, INJECTSBITERR => injectsbiterr_delayed, USER_EMPTY_FB => empty_p0_out, --Outputs DOUT => dout_fifo_out, FULL => FULL_int, ALMOST_FULL => ALMOST_FULL, WR_ACK => WR_ACK, OVERFLOW => OVERFLOW, EMPTY => empty_fifo_out, ALMOST_EMPTY => almost_empty_fifo_out, VALID => valid_fifo_out, UNDERFLOW => underflow_fifo_out, RD_DATA_COUNT => rd_data_count_fifo_out, WR_DATA_COUNT => wr_data_count_fifo_out, PROG_FULL => PROG_FULL, PROG_EMPTY => PROG_EMPTY, DBITERR => dbiterr_fifo_out, SBITERR => sbiterr_fifo_out ); END GENERATE gen_as; ------------------------------------------------------------------------- -- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK --- ------------------------------------------------------------------------- clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE CLK_INT <= CLK; END GENERATE clock_fwft_common; clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE CLK_INT <= RD_CLK; END GENERATE clock_fwft; ----------------------------------------------------------------------------- -- Connect Internal Signals -- In the normal case, these signals tie directly to the FIFO's inputs and -- outputs. -- In the case of Preload Latency 0 or 1, these are the intermediate -- signals between the internal FIFO and the preload logic. ----------------------------------------------------------------------------- latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE rd_en_fifo_in <= rd_en_delayed; DOUT <= dout_fifo_out; VALID <= valid_fifo_out; EMPTY <= empty_fifo_out; ALMOST_EMPTY <= almost_empty_fifo_out; UNDERFLOW <= underflow_fifo_out; RD_DATA_COUNT <= rd_data_count_fifo_out; WR_DATA_COUNT <= wr_data_count_fifo_out; SBITERR <= sbiterr_fifo_out; DBITERR <= dbiterr_fifo_out; END GENERATE latnrm; lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0'; lat0logic : fifo_generator_v8_2_bhv_preload0 GENERIC MAP ( C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => C_DOUT_WIDTH, C_HAS_RST => C_HAS_RST, C_HAS_SRST => C_HAS_SRST, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_ECC => C_USE_ECC, C_USERVALID_LOW => C_VALID_LOW, C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_MEMORY_TYPE => C_MEMORY_TYPE, C_FIFO_TYPE => C_FIFO_TYPE ) PORT MAP ( RD_CLK => CLK_INT, RD_RST => rst_fwft, SRST => srst_delayed, RD_EN => rd_en_delayed, FIFOEMPTY => empty_fifo_out, FIFODATA => dout_fifo_out, FIFOSBITERR => sbiterr_fifo_out, FIFODBITERR => dbiterr_fifo_out, USERDATA => dout_p0_out, USERVALID => valid_p0_out, USEREMPTY => empty_p0_out, USERALMOSTEMPTY => almost_empty_p0_out, USERUNDERFLOW => underflow_p0_out, RAMVALID => ram_valid, --Used for observing the state of the ram_valid FIFORDEN => rd_en_fifo_in, USERSBITERR => SBITERR, USERDBITERR => DBITERR ); rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) GENERATE eclk: PROCESS (CLK_INT,rst_fwft) BEGIN -- process eclk IF (rst_fwft='1') THEN empty_p0_out_q <= '1' after C_TCQ; almost_empty_p0_out_q <= '1' after C_TCQ; ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge empty_p0_out_q <= empty_p0_out after C_TCQ; almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ; END IF; END PROCESS eclk; rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q, almost_empty_p0_out_q,rst_fwft) BEGIN -- process rcsproc IF (empty_p0_out_q='1' OR rst_fwft='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH); ELSIF (almost_empty_p0_out_q='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH); ELSE RD_DATA_COUNT <= rd_data_count_fifo_out ; END IF; END PROCESS rcsproc; END GENERATE rdcg; rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH)) GENERATE eclk1: PROCESS (CLK_INT,rst_fwft) BEGIN -- process eclk IF (rst_fwft='1') THEN empty_p0_out_q <= '1' after C_TCQ; almost_empty_p0_out_q <= '1' after C_TCQ; ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge empty_p0_out_q <= empty_p0_out after C_TCQ; almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ; END IF; END PROCESS eclk1; rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q, almost_empty_p0_out_q,rst_fwft) BEGIN -- process rcsproc IF (empty_p0_out_q='1' OR rst_fwft='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH); ELSIF (almost_empty_p0_out_q='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH); ELSE RD_DATA_COUNT <= rd_data_count_fifo_out ; END IF; END PROCESS rcsproc1; END GENERATE rdcg1; nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE RD_DATA_COUNT <= rd_data_count_fifo_out; END GENERATE nrdcg; WR_DATA_COUNT <= wr_data_count_fifo_out; --------------------------------------------------- -- logics for common-clock data count with fwft -- For common-clock FIFOs with FWFT, data count -- is calculated as an up-down counter to maintain -- accuracy. --------------------------------------------------- gfwft_rd: IF (C_VALID_LOW = 0) GENERATE SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ; END GENERATE gfwft_rd; ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ; END GENERATE ngfwft_rd; SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ; cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE count_fwft: PROCESS (CLK, rst_fwft) BEGIN IF (rst_fwft = '1' AND C_HAS_RST=1) THEN DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ; ELSIF CLK'event AND CLK = '1' THEN IF (srst_delayed='1' AND C_HAS_SRST=1) THEN DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ; ELSE IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ; ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ; ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ; ELSE DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ; END IF ; END IF; END IF; END PROCESS count_fwft; END GENERATE cc_data_cnt; ---------------------------------------------- DOUT <= dout_p0_out; VALID <= valid_p0_out; EMPTY <= empty_p0_out; ALMOST_EMPTY <= almost_empty_p0_out; UNDERFLOW <= underflow_p0_out; END GENERATE lat0; gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE begin ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR (C_USE_FWFT_DATA_COUNT = 0) )GENERATE begin DATA_COUNT <= data_count_fifo_out ; end generate ss_count ; ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND (C_USE_FWFT_DATA_COUNT = 1) ) GENERATE begin DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ; end generate ss_count_fwft1 ; ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND (C_USE_FWFT_DATA_COUNT = 1)) GENERATE begin DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ; end generate ss_count_fwft2 ; end generate gdc_fwft; FULL <= FULL_int; ------------------------------------------------------------------------------- -- If there is a reset input, generate internal reset signals -- The latency of reset will match the core behavior ------------------------------------------------------------------------------- --Single RST grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE grst : IF (C_HAS_RST = 1) GENERATE gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE SIGNAL rd_rst_asreg : std_logic:= '0'; SIGNAL rd_rst_asreg_d1 : std_logic:= '0'; SIGNAL rd_rst_asreg_d2 : std_logic:= '0'; SIGNAL rd_rst_comb : std_logic:= '0'; SIGNAL rd_rst_reg : std_logic:= '0'; SIGNAL wr_rst_asreg : std_logic:= '0'; SIGNAL wr_rst_asreg_d1 : std_logic:= '0'; SIGNAL wr_rst_asreg_d2 : std_logic:= '0'; SIGNAL wr_rst_comb : std_logic:= '0'; SIGNAL wr_rst_reg : std_logic:= '0'; BEGIN PROCESS (WR_CLK, rst_delayed) BEGIN IF (rst_delayed = '1') THEN wr_rst_asreg <= '1' after C_TCQ; ELSIF (WR_CLK'event and WR_CLK = '1') THEN IF (wr_rst_asreg_d1 = '1') THEN wr_rst_asreg <= '0' after C_TCQ; END IF; END IF; IF (WR_CLK'event and WR_CLK = '1') THEN wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ; wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ; END IF; END PROCESS; PROCESS (wr_rst_asreg, wr_rst_asreg_d2) BEGIN wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg; END PROCESS; PROCESS (WR_CLK, wr_rst_comb) BEGIN IF (wr_rst_comb = '1') THEN wr_rst_reg <= '1' after C_TCQ; ELSIF (WR_CLK'event and WR_CLK = '1') THEN wr_rst_reg <= '0' after C_TCQ; END IF; END PROCESS; PROCESS (RD_CLK, rst_delayed) BEGIN IF (rst_delayed = '1') THEN rd_rst_asreg <= '1' after C_TCQ; ELSIF (RD_CLK'event and RD_CLK = '1') THEN IF (rd_rst_asreg_d1 = '1') THEN rd_rst_asreg <= '0' after C_TCQ; END IF; END IF; IF (RD_CLK'event and RD_CLK = '1') THEN rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ; rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ; END IF; END PROCESS; PROCESS (rd_rst_asreg, rd_rst_asreg_d2) BEGIN rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg; END PROCESS; PROCESS (RD_CLK, rd_rst_comb) BEGIN IF (rd_rst_comb = '1') THEN rd_rst_reg <= '1' after C_TCQ; ELSIF (RD_CLK'event and RD_CLK = '1') THEN rd_rst_reg <= '0' after C_TCQ; END IF; END PROCESS; wr_rst_i <= wr_rst_reg; rd_rst_i <= rd_rst_reg; END GENERATE gic_rst; gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE SIGNAL rst_asreg : std_logic := '0'; SIGNAL rst_asreg_d1 : std_logic := '0'; SIGNAL rst_asreg_d2 : std_logic := '0'; SIGNAL rst_comb : std_logic := '0'; SIGNAL rst_reg : std_logic := '0'; BEGIN PROCESS (CLK, rst_delayed) BEGIN IF (rst_delayed = '1') THEN rst_asreg <= '1' after C_TCQ; ELSIF (CLK'event and CLK = '1') THEN IF (rst_asreg_d1 = '1') THEN rst_asreg <= '0' after C_TCQ; ELSE rst_asreg <= rst_asreg after C_TCQ; END IF; END IF; IF (CLK'event and CLK = '1') THEN rst_asreg_d1 <= rst_asreg after C_TCQ; rst_asreg_d2 <= rst_asreg_d1 after C_TCQ; END IF; END PROCESS; PROCESS (rst_asreg, rst_asreg_d2) BEGIN rst_comb <= NOT rst_asreg_d2 AND rst_asreg; END PROCESS; PROCESS (CLK, rst_comb) BEGIN IF (rst_comb = '1') THEN rst_reg <= '1' after C_TCQ; ELSIF (CLK'event and CLK = '1') THEN rst_reg <= '0' after C_TCQ; END IF; END PROCESS; rst_i <= rst_reg; END GENERATE gcc_rst; END GENERATE grst; gnrst : IF (C_HAS_RST = 0) GENERATE wr_rst_i <= '0'; rd_rst_i <= '0'; rst_i <= '0'; END GENERATE gnrst; END GENERATE grst_sync; gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE wr_rst_i <= wr_rst_delayed; rd_rst_i <= rd_rst_delayed; rst_i <= '0'; END GENERATE gnrst_sync; rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed; clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK; grstd1 : IF (C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE -- RST_FULL_GEN replaces the reset falling edge detection used to de-assert -- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. -- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & -- PROG_FULL grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE SIGNAL rst_d1 : STD_LOGIC := '1'; SIGNAL rst_d2 : STD_LOGIC := '1'; SIGNAL rst_d3 : STD_LOGIC := '1'; BEGIN grst_f: IF (C_HAS_SRST = 0) GENERATE prst: PROCESS (rst_2_sync, clk_2_sync) BEGIN IF (rst_2_sync = '1') THEN rst_d1 <= '1'; rst_d2 <= '1'; rst_d3 <= '1'; rst_full_gen_i <= '0'; ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN rst_d1 <= '0' AFTER C_TCQ; rst_d2 <= rst_d1 AFTER C_TCQ; rst_d3 <= rst_d2 AFTER C_TCQ; rst_full_gen_i <= rst_d3 AFTER C_TCQ; END IF; END PROCESS prst; rst_full_ff_i <= rst_d2; END GENERATE grst_f; ngrst_f: IF (C_HAS_SRST = 1) GENERATE prst: PROCESS (clk_2_sync) BEGIN IF (clk_2_sync'event AND clk_2_sync = '1') THEN IF (srst_delayed = '1') THEN rst_d1 <= '1' AFTER C_TCQ; rst_d2 <= '1' AFTER C_TCQ; rst_d3 <= '1' AFTER C_TCQ; rst_full_gen_i <= '0' AFTER C_TCQ; ELSE rst_d1 <= '0' AFTER C_TCQ; rst_d2 <= rst_d1 AFTER C_TCQ; rst_d3 <= rst_d2 AFTER C_TCQ; rst_full_gen_i <= rst_d3 AFTER C_TCQ; END IF; END IF; END PROCESS prst; rst_full_ff_i <= '0'; END GENERATE ngrst_f; END GENERATE grst_full; gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE rst_full_gen_i <= '0'; rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i; END GENERATE gnrst_full; END GENERATE grstd1; END behavioral; ------------------------------------------------------------------------------- -- -- Register Slice -- Register one AXI channel on forward and/or reverse signal path -- ---------------------------------------------------------------------------- -- -- Structure: -- reg_slice -- ---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fifo_generator_v8_2_axic_reg_slice IS GENERIC ( C_FAMILY : string := ""; C_DATA_WIDTH : integer := 32; C_REG_CONFIG : integer := 0 ); PORT ( -- System Signals ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; -- Slave side S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC := '0'; -- Master side M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_VALID : OUT STD_LOGIC := '0'; M_READY : IN STD_LOGIC ); END fifo_generator_v8_2_axic_reg_slice; ARCHITECTURE xilinx OF fifo_generator_v8_2_axic_reg_slice IS SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register -- Constant to have clock to register delay CONSTANT TFF : time := 100 ps; BEGIN -------------------------------------------------------------------- -- -- Both FWD and REV mode -- -------------------------------------------------------------------- gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL load_s1 : STD_LOGIC; SIGNAL load_s2 : STD_LOGIC; SIGNAL load_s1_from_s2 : BOOLEAN; BEGIN -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; -- Reset delay register PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN areset_d1 <= ARESET AFTER TFF; END IF; END PROCESS; -- Load storage1 with either slave side data or from storage2 PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (load_s1 = '1') THEN IF (load_s1_from_s2) THEN storage_data1 <= storage_data2 AFTER TFF; ELSE storage_data1 <= S_PAYLOAD_DATA AFTER TFF; END IF; END IF; END IF; END PROCESS; -- Load storage2 with slave side data PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (load_s2 = '1') THEN storage_data2 <= S_PAYLOAD_DATA AFTER TFF; END IF; END IF; END PROCESS; M_PAYLOAD_DATA <= storage_data1; -- Always load s2 on a valid transaction even if it's unnecessary load_s2 <= S_VALID AND s_ready_i; -- Loading s1 PROCESS(state,S_VALID,M_READY) BEGIN IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction -- Load when ONE if we both have read and write at the same time (state = ONE AND S_VALID = '1' AND M_READY = '1') OR -- Load when TWO and we have a transaction on Master side (state = TWO AND M_READY = '1')) THEN load_s1 <= '1'; ELSE load_s1 <= '0'; END IF; END PROCESS; load_s1_from_s2 <= (state = TWO); -- State Machine for handling output signals PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (ARESET = '1') THEN s_ready_i <= '0' AFTER TFF; state <= ZERO AFTER TFF; ELSIF (areset_d1 = '1') THEN s_ready_i <= '1' AFTER TFF; ELSE CASE (state) IS WHEN ZERO => -- No transaction stored locally IF (S_VALID = '1') THEN -- Got one so move to ONE state <= ONE AFTER TFF; END IF; WHEN ONE => -- One transaction stored locally IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO state <= ZERO AFTER TFF; END IF; IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO state <= TWO AFTER TFF; s_ready_i <= '0' AFTER TFF; END IF; WHEN TWO => -- TWO transaction stored locally IF (M_READY = '1') THEN -- Read out one so move to ONE state <= ONE AFTER TFF; s_ready_i <= '1' AFTER TFF; END IF; WHEN OTHERS => state <= state AFTER TFF; END CASE; END IF; END IF; END PROCESS; -- s_ready_i <= state(1); m_valid_i <= state(0); END GENERATE gfwd_rev; -------------------------------------------------------------------- -- -- C_REG_CONFIG = 1 -- Light-weight mode. -- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining -- Operates same as 1-deep FIFO -- -------------------------------------------------------------------- gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; -- Reset delay register PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN areset_d1 <= ARESET AFTER TFF; END IF; END PROCESS; -- Load storage1 with slave side data PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (ARESET = '1') THEN s_ready_i <= '0' AFTER TFF; m_valid_i <= '0' AFTER TFF; ELSIF (areset_d1 = '1') THEN s_ready_i <= '1' AFTER TFF; ELSIF (m_valid_i = '1' AND M_READY = '1') THEN s_ready_i <= '1' AFTER TFF; m_valid_i <= '0' AFTER TFF; ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN s_ready_i <= '0' AFTER TFF; m_valid_i <= '1' AFTER TFF; END IF; IF (m_valid_i = '0') THEN storage_data1 <= S_PAYLOAD_DATA AFTER TFF; END IF; END IF; END PROCESS; M_PAYLOAD_DATA <= storage_data1; END GENERATE gfwd_rev_pipeline1; end xilinx;-- reg_slice ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Top-level Behavioral Model for AXI ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY XilinxCoreLib; USE XilinxCoreLib.fifo_generator_v8_2_conv; ------------------------------------------------------------------------------- -- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2 IS GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; C_FAMILY : string := ""; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; C_HAS_MEMINIT_FILE : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; C_OPTIMIZATION_MODE : integer := 0; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; C_MSGON_VAL : integer := 1; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL : integer := 0; C_HAS_AXI_RD_CHANNEL : integer := 0; C_HAS_SLAVE_CE : integer := 0; C_HAS_MASTER_CE : integer := 0; C_ADD_NGC_CONSTRAINT : integer := 0; C_USE_COMMON_OVERFLOW : integer := 0; C_USE_COMMON_UNDERFLOW : integer := 0; C_USE_DEFAULT_SETTINGS : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH : integer := 0; C_AXI_ADDR_WIDTH : integer := 0; C_AXI_DATA_WIDTH : integer := 0; C_HAS_AXI_AWUSER : integer := 0; C_HAS_AXI_WUSER : integer := 0; C_HAS_AXI_BUSER : integer := 0; C_HAS_AXI_ARUSER : integer := 0; C_HAS_AXI_RUSER : integer := 0; C_AXI_ARUSER_WIDTH : integer := 0; C_AXI_AWUSER_WIDTH : integer := 0; C_AXI_WUSER_WIDTH : integer := 0; C_AXI_BUSER_WIDTH : integer := 0; C_AXI_RUSER_WIDTH : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA : integer := 0; C_HAS_AXIS_TID : integer := 0; C_HAS_AXIS_TDEST : integer := 0; C_HAS_AXIS_TUSER : integer := 0; C_HAS_AXIS_TREADY : integer := 0; C_HAS_AXIS_TLAST : integer := 0; C_HAS_AXIS_TSTRB : integer := 0; C_HAS_AXIS_TKEEP : integer := 0; C_AXIS_TDATA_WIDTH : integer := 1; C_AXIS_TID_WIDTH : integer := 1; C_AXIS_TDEST_WIDTH : integer := 1; C_AXIS_TUSER_WIDTH : integer := 1; C_AXIS_TSTRB_WIDTH : integer := 1; C_AXIS_TKEEP_WIDTH : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH : integer := 0; C_IMPLEMENTATION_TYPE_WDCH : integer := 0; C_IMPLEMENTATION_TYPE_WRCH : integer := 0; C_IMPLEMENTATION_TYPE_RACH : integer := 0; C_IMPLEMENTATION_TYPE_RDCH : integer := 0; C_IMPLEMENTATION_TYPE_AXIS : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Sync FIFO -- 3 = Low Latency Async FIFO C_APPLICATION_TYPE_WACH : integer := 0; C_APPLICATION_TYPE_WDCH : integer := 0; C_APPLICATION_TYPE_WRCH : integer := 0; C_APPLICATION_TYPE_RACH : integer := 0; C_APPLICATION_TYPE_RDCH : integer := 0; C_APPLICATION_TYPE_AXIS : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH : integer := 0; C_USE_ECC_WDCH : integer := 0; C_USE_ECC_WRCH : integer := 0; C_USE_ECC_RACH : integer := 0; C_USE_ECC_RDCH : integer := 0; C_USE_ECC_AXIS : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH : integer := 0; C_ERROR_INJECTION_TYPE_WDCH : integer := 0; C_ERROR_INJECTION_TYPE_WRCH : integer := 0; C_ERROR_INJECTION_TYPE_RACH : integer := 0; C_ERROR_INJECTION_TYPE_RDCH : integer := 0; C_ERROR_INJECTION_TYPE_AXIS : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH : integer := 1; C_DIN_WIDTH_WDCH : integer := 1; C_DIN_WIDTH_WRCH : integer := 1; C_DIN_WIDTH_RACH : integer := 1; C_DIN_WIDTH_RDCH : integer := 1; C_DIN_WIDTH_AXIS : integer := 1; C_WR_DEPTH_WACH : integer := 16; C_WR_DEPTH_WDCH : integer := 16; C_WR_DEPTH_WRCH : integer := 16; C_WR_DEPTH_RACH : integer := 16; C_WR_DEPTH_RDCH : integer := 16; C_WR_DEPTH_AXIS : integer := 16; C_WR_PNTR_WIDTH_WACH : integer := 4; C_WR_PNTR_WIDTH_WDCH : integer := 4; C_WR_PNTR_WIDTH_WRCH : integer := 4; C_WR_PNTR_WIDTH_RACH : integer := 4; C_WR_PNTR_WIDTH_RDCH : integer := 4; C_WR_PNTR_WIDTH_AXIS : integer := 4; C_HAS_DATA_COUNTS_WACH : integer := 0; C_HAS_DATA_COUNTS_WDCH : integer := 0; C_HAS_DATA_COUNTS_WRCH : integer := 0; C_HAS_DATA_COUNTS_RACH : integer := 0; C_HAS_DATA_COUNTS_RDCH : integer := 0; C_HAS_DATA_COUNTS_AXIS : integer := 0; C_HAS_PROG_FLAGS_WACH : integer := 0; C_HAS_PROG_FLAGS_WDCH : integer := 0; C_HAS_PROG_FLAGS_WRCH : integer := 0; C_HAS_PROG_FLAGS_RACH : integer := 0; C_HAS_PROG_FLAGS_RDCH : integer := 0; C_HAS_PROG_FLAGS_AXIS : integer := 0; C_PROG_FULL_TYPE_WACH : integer := 0; C_PROG_FULL_TYPE_WDCH : integer := 0; C_PROG_FULL_TYPE_WRCH : integer := 0; C_PROG_FULL_TYPE_RACH : integer := 0; C_PROG_FULL_TYPE_RDCH : integer := 0; C_PROG_FULL_TYPE_AXIS : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 0; C_PROG_EMPTY_TYPE_WACH : integer := 0; C_PROG_EMPTY_TYPE_WDCH : integer := 0; C_PROG_EMPTY_TYPE_WRCH : integer := 0; C_PROG_EMPTY_TYPE_RACH : integer := 0; C_PROG_EMPTY_TYPE_RDCH : integer := 0; C_PROG_EMPTY_TYPE_AXIS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 0; C_REG_SLICE_MODE_WACH : integer := 0; C_REG_SLICE_MODE_WDCH : integer := 0; C_REG_SLICE_MODE_WRCH : integer := 0; C_REG_SLICE_MODE_RACH : integer := 0; C_REG_SLICE_MODE_RDCH : integer := 0; C_REG_SLICE_MODE_AXIS : integer := 0 ); PORT( ------------------------------------------------------------------------------ -- Input and Output Declarations ------------------------------------------------------------------------------ -- Conventional FIFO Interface Signals BACKUP : IN std_logic := '0'; BACKUP_MARKER : IN std_logic := '0'; CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_CLK : IN std_logic := '0'; WR_RST : IN std_logic := '0'; RD_CLK : IN std_logic := '0'; RD_RST : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); WR_EN : IN std_logic := '0'; RD_EN : IN std_logic := '0'; -- Optional inputs PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INT_CLK : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FULL : OUT std_logic; ALMOST_FULL : OUT std_logic; WR_ACK : OUT std_logic; OVERFLOW : OUT std_logic; EMPTY : OUT std_logic; ALMOST_EMPTY : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); PROG_FULL : OUT std_logic; PROG_EMPTY : OUT std_logic; SBITERR : OUT std_logic; DBITERR : OUT std_logic; -- AXI Global Signal M_ACLK : IN std_logic := '0'; S_ACLK : IN std_logic := '0'; S_ARESETN : IN std_logic := '0'; M_ACLK_EN : IN std_logic := '0'; S_ACLK_EN : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN std_logic := '0'; S_AXI_AWREADY : OUT std_logic; S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN std_logic := '0'; S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WVALID : IN std_logic := '0'; S_AXI_WREADY : OUT std_logic; S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0); S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); S_AXI_BVALID : OUT std_logic; S_AXI_BREADY : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0); M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); M_AXI_AWVALID : OUT std_logic; M_AXI_AWREADY : IN std_logic := '0'; M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); M_AXI_WLAST : OUT std_logic; M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); M_AXI_WVALID : OUT std_logic; M_AXI_WREADY : IN std_logic := '0'; M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_BVALID : IN std_logic := '0'; M_AXI_BREADY : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0); S_AXI_RLAST : OUT std_logic; S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0); M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); M_AXI_ARVALID : OUT std_logic; M_AXI_ARREADY : IN std_logic := '0'; M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RLAST : IN std_logic := '0'; M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RVALID : IN std_logic := '0'; M_AXI_RREADY : OUT std_logic; -- AXI Streaming Slave Signals (Write side) S_AXIS_TVALID : IN std_logic := '0'; S_AXIS_TREADY : OUT std_logic; S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TLAST : IN std_logic := '0'; S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) M_AXIS_TVALID : OUT std_logic; M_AXIS_TREADY : IN std_logic := '0'; M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); M_AXIS_TLAST : OUT std_logic; M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals AXI_AW_INJECTSBITERR : IN std_logic := '0'; AXI_AW_INJECTDBITERR : IN std_logic := '0'; AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); AXI_AW_SBITERR : OUT std_logic; AXI_AW_DBITERR : OUT std_logic; AXI_AW_OVERFLOW : OUT std_logic; AXI_AW_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Write Data Channel Signals AXI_W_INJECTSBITERR : IN std_logic := '0'; AXI_W_INJECTDBITERR : IN std_logic := '0'; AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); AXI_W_SBITERR : OUT std_logic; AXI_W_DBITERR : OUT std_logic; AXI_W_OVERFLOW : OUT std_logic; AXI_W_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Write Response Channel Signals AXI_B_INJECTSBITERR : IN std_logic := '0'; AXI_B_INJECTDBITERR : IN std_logic := '0'; AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); AXI_B_SBITERR : OUT std_logic; AXI_B_DBITERR : OUT std_logic; AXI_B_OVERFLOW : OUT std_logic; AXI_B_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Read Address Channel Signals AXI_AR_INJECTSBITERR : IN std_logic := '0'; AXI_AR_INJECTDBITERR : IN std_logic := '0'; AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); AXI_AR_SBITERR : OUT std_logic; AXI_AR_DBITERR : OUT std_logic; AXI_AR_OVERFLOW : OUT std_logic; AXI_AR_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Read Data Channel Signals AXI_R_INJECTSBITERR : IN std_logic := '0'; AXI_R_INJECTDBITERR : IN std_logic := '0'; AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); AXI_R_SBITERR : OUT std_logic; AXI_R_DBITERR : OUT std_logic; AXI_R_OVERFLOW : OUT std_logic; AXI_R_UNDERFLOW : OUT std_logic; -- AXI Streaming FIFO Related Signals AXIS_INJECTSBITERR : IN std_logic := '0'; AXIS_INJECTDBITERR : IN std_logic := '0'; AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); AXIS_SBITERR : OUT std_logic; AXIS_DBITERR : OUT std_logic; AXIS_OVERFLOW : OUT std_logic; AXIS_UNDERFLOW : OUT std_logic ); END fifo_generator_v8_2; ARCHITECTURE behavioral OF fifo_generator_v8_2 IS COMPONENT fifo_generator_v8_2_conv IS GENERIC ( --------------------------------------------------------------------------- -- Generic Declarations --------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; --not used C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; --not used C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; --not used C_FAMILY : string := ""; --not used in bhv model C_FULL_FLAGS_RST_VAL : integer := 0; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; --not used C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; --not used in bhv model C_HAS_MEMINIT_FILE : integer := 0; --not used C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; --not used C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; --not used C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; --not used C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; --not used C_OPTIMIZATION_MODE : integer := 0; --not used C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; --not used in bhv model C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; --not used in bhv model C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; --not used C_MSGON_VAL : integer := 1; --not used in bhv model C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- BACKUP : IN std_logic := '0'; BACKUP_MARKER : IN std_logic := '0'; CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_CLK : IN std_logic := '0'; WR_RST : IN std_logic := '0'; RD_CLK : IN std_logic := '0'; RD_RST : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); -- WR_EN : IN std_logic; --Mandatory input RD_EN : IN std_logic; --Mandatory input --Mandatory input PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INT_CLK : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FULL : OUT std_logic; ALMOST_FULL : OUT std_logic; WR_ACK : OUT std_logic; OVERFLOW : OUT std_logic; EMPTY : OUT std_logic; ALMOST_EMPTY : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); PROG_FULL : OUT std_logic; PROG_EMPTY : OUT std_logic; SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END COMPONENT; COMPONENT fifo_generator_v8_2_axic_reg_slice IS GENERIC ( C_FAMILY : string := ""; C_DATA_WIDTH : integer := 32; C_REG_CONFIG : integer := 0 ); PORT ( -- System Signals ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; -- Slave side S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC := '0'; -- Master side M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_VALID : OUT STD_LOGIC := '0'; M_READY : IN STD_LOGIC ); END COMPONENT; CONSTANT C_AXI_LEN_WIDTH : integer := 8; CONSTANT C_AXI_SIZE_WIDTH : integer := 3; CONSTANT C_AXI_BURST_WIDTH : integer := 2; CONSTANT C_AXI_LOCK_WIDTH : integer := 2; CONSTANT C_AXI_CACHE_WIDTH : integer := 4; CONSTANT C_AXI_PROT_WIDTH : integer := 3; CONSTANT C_AXI_QOS_WIDTH : integer := 4; CONSTANT C_AXI_REGION_WIDTH : integer := 4; CONSTANT C_AXI_BRESP_WIDTH : integer := 2; CONSTANT C_AXI_RRESP_WIDTH : integer := 2; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed and returns string. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : boolean; true_case : string; false_case : string) RETURN string IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; -------------------------------------------------------- -- FUNCION : map_ready_valid -- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL -- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY -------------------------------------------------------- FUNCTION map_ready_valid( pf_pe_type : integer; full_empty : std_logic; af_ae : std_logic; pf_pe : std_logic) RETURN std_logic IS BEGIN IF (pf_pe_type = 5) THEN RETURN NOT full_empty; ELSIF (pf_pe_type = 6) THEN RETURN NOT af_ae; ELSE RETURN NOT pf_pe; END IF; END map_ready_valid; SIGNAL inverted_reset : std_logic := '0'; BEGIN inverted_reset <= NOT S_ARESETN; --------------------------------------------------------------------------- -- Top level instance for Conventional FIFO. --------------------------------------------------------------------------- gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE inst_conv_fifo: fifo_generator_v8_2_conv GENERIC map( C_COMMON_CLOCK => C_COMMON_CLOCK, C_COUNT_TYPE => C_COUNT_TYPE, C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_DIN_WIDTH => C_DIN_WIDTH, C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"), C_DOUT_WIDTH => C_DOUT_WIDTH, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_FAMILY => C_FAMILY, C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT, C_HAS_RD_RST => C_HAS_RD_RST, C_HAS_RST => C_HAS_RST, C_HAS_SRST => C_HAS_SRST, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_HAS_VALID => C_HAS_VALID, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT, C_HAS_WR_RST => C_HAS_WR_RST, C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MEMORY_TYPE => C_MEMORY_TYPE, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL, C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE, C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH, C_RD_DEPTH => C_RD_DEPTH, C_RD_FREQ => C_RD_FREQ, C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_ECC => C_USE_ECC, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, C_VALID_LOW => C_VALID_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH, C_WR_DEPTH => C_WR_DEPTH, C_WR_FREQ => C_WR_FREQ, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, -- Enable Distributed RAM Low latency FIFO for FWFT Built-in FIFO, otherwise use Distributed RAM C_FIFO_TYPE => if_then_else((C_PRELOAD_LATENCY /= 0 AND C_MEMORY_TYPE = 4), 1,if_then_else((C_IMPLEMENTATION_TYPE > 2), 2, 0)) ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, CLK => CLK, RST => RST, SRST => SRST, WR_CLK => WR_CLK, WR_RST => WR_RST, RD_CLK => RD_CLK, RD_RST => RD_RST, DIN => DIN, WR_EN => WR_EN, RD_EN => RD_EN, PROG_EMPTY_THRESH => PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE, PROG_FULL_THRESH => PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE, INT_CLK => INT_CLK, INJECTDBITERR => INJECTDBITERR, INJECTSBITERR => INJECTSBITERR, --Outputs DOUT => DOUT, FULL => FULL, ALMOST_FULL => ALMOST_FULL, WR_ACK => WR_ACK, OVERFLOW => OVERFLOW, EMPTY => EMPTY, ALMOST_EMPTY => ALMOST_EMPTY, VALID => VALID, UNDERFLOW => UNDERFLOW, DATA_COUNT => DATA_COUNT, RD_DATA_COUNT => RD_DATA_COUNT, WR_DATA_COUNT => WR_DATA_COUNT, PROG_FULL => PROG_FULL, PROG_EMPTY => PROG_EMPTY, SBITERR => SBITERR, DBITERR => DBITERR ); END GENERATE gconvfifo; -- End of conventional FIFO --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Top level instance for ramfifo in AXI Streaming FIFO core. It implements: -- BRAM based FIFO -- * Dist RAM based FIFO --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXI_TYPE = 0) AND (C_AXIS_TYPE < 2)) GENERATE SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL axis_full : std_logic := '0'; SIGNAL axis_almost_full : std_logic := '0'; SIGNAL axis_prog_full : std_logic := '0'; SIGNAL axis_empty : std_logic := '0'; SIGNAL axis_almost_empty : std_logic := '0'; SIGNAL axis_prog_empty : std_logic := '0'; SIGNAL axis_s_axis_tready : std_logic := '0'; SIGNAL axis_m_axis_tvalid : std_logic := '0'; SIGNAL axis_wr_en : std_logic := '0'; SIGNAL axis_rd_en : std_logic := '0'; CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS); CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET); CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET); CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET); CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET); CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET); BEGIN -- Generate the DIN to FIFO by concatinating the AXIS optional ports gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA; M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET); END GENERATE gdin1; gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB; M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET); END GENERATE gdin2; gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP; M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET); END GENERATE gdin3; gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID; M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET); END GENERATE gdin4; gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST; M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET); END GENERATE gdin5; gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER; M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET); END GENERATE gdin6; gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE axis_din(0) <= S_AXIS_TLAST; M_AXIS_TLAST <= axis_dout(0); END GENERATE gdin7; -- Write protection -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 5) GENERATE axis_wr_en <= S_AXIS_TVALID; END GENERATE gaxis_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 5) GENERATE axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID; END GENERATE gaxis_wr_en2; -- Read protection -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 5) GENERATE axis_rd_en <= M_AXIS_TREADY; END GENERATE gaxis_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 5) GENERATE axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY; END GENERATE gaxis_rd_en2; gaxisf: IF (C_AXIS_TYPE = 0) GENERATE axisf : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_AXIS, C_WR_DEPTH => C_WR_DEPTH_AXIS, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS, C_DOUT_WIDTH => C_DIN_WIDTH_AXIS, C_RD_DEPTH => C_WR_DEPTH_AXIS, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS, C_USE_ECC => C_USE_ECC_AXIS, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_AXIS = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_AXIS = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_AXIS, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => C_HAS_SLAVE_CE, -- C_USE_OUTPUT_CE => C_HAS_MASTER_CE, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => 0, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => 0, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => axis_wr_en,--S_AXIS_TVALID, RD_EN => axis_rd_en,--M_AXIS_TREADY, PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXIS_INJECTDBITERR, INJECTSBITERR => AXIS_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => S_ACLK_EN, -- OUTPUT_CE => M_ACLK_EN, -- END_OF_PACKET => '0', -- BYTE_STROBE => (OTHERS => '0'), DIN => axis_din, DOUT => axis_dout, FULL => axis_full, ALMOST_FULL => axis_almost_full, PROG_FULL => axis_prog_full, EMPTY => axis_empty, ALMOST_EMPTY => axis_almost_empty, PROG_EMPTY => axis_prog_empty, WR_ACK => OPEN, OVERFLOW => AXIS_OVERFLOW, VALID => OPEN, UNDERFLOW => AXIS_UNDERFLOW, DATA_COUNT => AXIS_DATA_COUNT, RD_DATA_COUNT => AXIS_RD_DATA_COUNT, WR_DATA_COUNT => AXIS_WR_DATA_COUNT, SBITERR => AXIS_SBITERR, DBITERR => AXIS_DBITERR ); axis_s_axis_tready <= map_ready_valid(C_PROG_FULL_TYPE_AXIS,axis_full,axis_almost_full,axis_prog_full); axis_m_axis_tvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_AXIS,axis_empty,axis_almost_empty,axis_prog_empty); S_AXIS_TREADY <= axis_s_axis_tready;--map_ready_valid(C_PROG_FULL_TYPE_AXIS,axis_full,axis_almost_full,axis_prog_full); M_AXIS_TVALID <= axis_m_axis_tvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_AXIS,axis_empty,axis_almost_empty,axis_prog_empty); END GENERATE gaxisf; -- Register Slice for AXI Streaming gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE axis_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_AXIS, C_REG_CONFIG => C_REG_SLICE_MODE_AXIS ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => axis_din, S_VALID => S_AXIS_TVALID, S_READY => S_AXIS_TREADY, -- Master side M_PAYLOAD_DATA => axis_dout, M_VALID => M_AXIS_TVALID, M_READY => M_AXIS_TREADY ); END GENERATE gaxis_reg_slice; END GENERATE gaxis_fifo; gaxifull: IF (C_INTERFACE_TYPE = 1) AND (C_AXI_TYPE /= 0) GENERATE SIGNAL axi_rd_underflow_i : std_logic := '0'; SIGNAL axi_rd_overflow_i : std_logic := '0'; SIGNAL axi_wr_underflow_i : std_logic := '0'; SIGNAL axi_wr_overflow_i : std_logic := '0'; BEGIN gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wach_full : std_logic := '0'; SIGNAL wach_almost_full : std_logic := '0'; SIGNAL wach_prog_full : std_logic := '0'; SIGNAL wach_empty : std_logic := '0'; SIGNAL wach_almost_empty : std_logic := '0'; SIGNAL wach_prog_empty : std_logic := '0'; SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wdch_full : std_logic := '0'; SIGNAL wdch_almost_full : std_logic := '0'; SIGNAL wdch_prog_full : std_logic := '0'; SIGNAL wdch_empty : std_logic := '0'; SIGNAL wdch_almost_empty : std_logic := '0'; SIGNAL wdch_prog_empty : std_logic := '0'; SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wrch_full : std_logic := '0'; SIGNAL wrch_almost_full : std_logic := '0'; SIGNAL wrch_prog_full : std_logic := '0'; SIGNAL wrch_empty : std_logic := '0'; SIGNAL wrch_almost_empty : std_logic := '0'; SIGNAL wrch_prog_empty : std_logic := '0'; SIGNAL axi_aw_underflow_i : std_logic := '0'; SIGNAL axi_w_underflow_i : std_logic := '0'; SIGNAL axi_b_underflow_i : std_logic := '0'; SIGNAL axi_aw_overflow_i : std_logic := '0'; SIGNAL axi_w_overflow_i : std_logic := '0'; SIGNAL axi_b_overflow_i : std_logic := '0'; SIGNAL wach_s_axi_awready : std_logic := '0'; SIGNAL wach_m_axi_awvalid : std_logic := '0'; SIGNAL wach_wr_en : std_logic := '0'; SIGNAL wach_rd_en : std_logic := '0'; SIGNAL wdch_s_axi_wready : std_logic := '0'; SIGNAL wdch_m_axi_wvalid : std_logic := '0'; SIGNAL wdch_wr_en : std_logic := '0'; SIGNAL wdch_rd_en : std_logic := '0'; SIGNAL wrch_s_axi_bvalid : std_logic := '0'; SIGNAL wrch_m_axi_bready : std_logic := '0'; SIGNAL wrch_wr_en : std_logic := '0'; SIGNAL wrch_rd_en : std_logic := '0'; CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH); CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH; CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET); CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET); CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET); CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET); CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET); CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH; CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH; CONSTANT AWREGION_OFFSET : integer := AWQOS_OFFSET - C_AXI_REGION_WIDTH; CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET); CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH); CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH; CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8; CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET); CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH); CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH; CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET); BEGIN -- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports axi_full_din_wr_ch: IF (C_AXI_TYPE = 1) GENERATE gwach1: IF (C_WACH_TYPE < 2) GENERATE gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE wach_din <= S_AXI_AWID & S_AXI_AWADDR & S_AXI_AWLEN & S_AXI_AWSIZE & S_AXI_AWBURST & S_AXI_AWLOCK & S_AXI_AWCACHE & S_AXI_AWPROT & S_AXI_AWQOS & S_AXI_AWREGION & S_AXI_AWUSER; M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET); END GENERATE gwach_din1; gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE wach_din <= S_AXI_AWID & S_AXI_AWADDR & S_AXI_AWLEN & S_AXI_AWSIZE & S_AXI_AWBURST & S_AXI_AWLOCK & S_AXI_AWCACHE & S_AXI_AWPROT & S_AXI_AWQOS & S_AXI_AWREGION; M_AXI_AWUSER <= (OTHERS => '0'); END GENERATE gwach_din2; M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET); M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET); M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET); M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET); M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET); M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET); M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET); M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET); M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET); M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET); END GENERATE gwach1; -- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports gwdch1: IF (C_WDCH_TYPE < 2) GENERATE gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE wdch_din <= S_AXI_WID & S_AXI_WDATA & S_AXI_WSTRB & S_AXI_WUSER & S_AXI_WLAST; M_AXI_WLAST <= wdch_dout(0); M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET); END GENERATE gwdch_din1; gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE wdch_din <= S_AXI_WID & S_AXI_WDATA & S_AXI_WSTRB & S_AXI_WLAST; M_AXI_WLAST <= wdch_dout(0); M_AXI_WUSER <= (OTHERS => '0'); END GENERATE gwdch_din2; M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET); M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET); M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET); END GENERATE gwdch1; -- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports gwrch1: IF (C_WRCH_TYPE < 2) GENERATE gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE wrch_din <= M_AXI_BID & M_AXI_BRESP & M_AXI_BUSER; S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET); END GENERATE gwrch_din1; gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE wrch_din <= M_AXI_BID & M_AXI_BRESP; S_AXI_BUSER <= (OTHERS => '0'); END GENERATE gwrch_din2; S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET); S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET); END GENERATE gwrch1; END GENERATE axi_full_din_wr_ch; -- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE gwach1: IF (C_WACH_TYPE < 2) GENERATE wach_din <= S_AXI_AWADDR & S_AXI_AWPROT; M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET); M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET); END GENERATE gwach1; gwdch1: IF (C_WDCH_TYPE < 2) GENERATE wdch_din <= S_AXI_WDATA & S_AXI_WSTRB; M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET); M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET); END GENERATE gwdch1; gwrch1: IF (C_WRCH_TYPE < 2) GENERATE wrch_din <= M_AXI_BRESP; S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET); END GENERATE gwrch1; END GENERATE axi_lite_din_wr_ch; -- Write protection for Write Address Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 5) GENERATE wach_wr_en <= S_AXI_AWVALID; END GENERATE gwach_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 5) GENERATE wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID; END GENERATE gwach_wr_en2; -- Write protection for Write Data Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 5) GENERATE wdch_wr_en <= S_AXI_WVALID; END GENERATE gwdch_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 5) GENERATE wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID; END GENERATE gwdch_wr_en2; -- Write protection for Write Response Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 5) GENERATE wrch_wr_en <= M_AXI_BVALID; END GENERATE gwrch_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 5) GENERATE wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID; END GENERATE gwrch_wr_en2; -- Read protection for Write Address Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 5) GENERATE wach_rd_en <= M_AXI_AWREADY; END GENERATE gwach_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 5) GENERATE wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY; END GENERATE gwach_rd_en2; -- Read protection for Write Data Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 5) GENERATE wdch_rd_en <= M_AXI_WREADY; END GENERATE gwdch_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 5) GENERATE wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY; END GENERATE gwdch_rd_en2; -- Read protection for Write Response Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 5) GENERATE wrch_rd_en <= S_AXI_BREADY; END GENERATE gwrch_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 5) GENERATE wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY; END GENERATE gwrch_rd_en2; gwach2: IF (C_WACH_TYPE = 0) GENERATE axi_wach : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_WACH, C_WR_DEPTH => C_WR_DEPTH_WACH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH, C_DOUT_WIDTH => C_DIN_WIDTH_WACH, C_RD_DEPTH => C_WR_DEPTH_WACH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH, C_USE_ECC => C_USE_ECC_WACH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WACH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WACH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_WACH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => wach_wr_en,--S_AXI_AWVALID, RD_EN => wach_rd_en,--M_AXI_AWREADY, PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_AW_INJECTDBITERR, INJECTSBITERR => AXI_AW_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_AW_INPUT_CE, -- OUTPUT_CE => AXI_AW_OUTPUT_CE, -- END_OF_PACKET => AXI_AW_END_OF_PACKET, -- BYTE_STROBE => AXI_AW_BYTE_STROBE, DIN => wach_din, DOUT => wach_dout, FULL => wach_full, ALMOST_FULL => wach_almost_full, PROG_FULL => wach_prog_full, EMPTY => wach_empty, ALMOST_EMPTY => wach_almost_empty, PROG_EMPTY => wach_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_aw_overflow_i, VALID => OPEN, UNDERFLOW => axi_aw_underflow_i, DATA_COUNT => AXI_AW_DATA_COUNT, RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT, WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT, SBITERR => AXI_AW_SBITERR, DBITERR => AXI_AW_DBITERR ); wach_s_axi_awready <= map_ready_valid(C_PROG_FULL_TYPE_WACH,wach_full,wach_almost_full,wach_prog_full); wach_m_axi_awvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WACH,wach_empty,wach_almost_empty,wach_prog_empty); S_AXI_AWREADY <= wach_s_axi_awready;--map_ready_valid(C_PROG_FULL_TYPE_WACH,wach_full,wach_almost_full,wach_prog_full); M_AXI_AWVALID <= wach_m_axi_awvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WACH,wach_empty,wach_almost_empty,wach_prog_empty); gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_AW_UNDERFLOW <= axi_aw_underflow_i; END GENERATE gaxi_wr_ch_uf1; gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_AW_OVERFLOW <= axi_aw_overflow_i; END GENERATE gaxi_wr_ch_of1; END GENERATE gwach2; -- Register Slice for Write Address Channel gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE wach_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_WACH, C_REG_CONFIG => C_REG_SLICE_MODE_WACH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => wach_din, S_VALID => S_AXI_AWVALID, S_READY => S_AXI_AWREADY, -- Master side M_PAYLOAD_DATA => wach_dout, M_VALID => M_AXI_AWVALID, M_READY => M_AXI_AWREADY ); END GENERATE gwach_reg_slice; gwdch2: IF (C_WDCH_TYPE = 0) GENERATE axi_wdch : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_WDCH, C_WR_DEPTH => C_WR_DEPTH_WDCH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH, C_DOUT_WIDTH => C_DIN_WIDTH_WDCH, C_RD_DEPTH => C_WR_DEPTH_WDCH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH, C_USE_ECC => C_USE_ECC_WDCH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WDCH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WDCH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => wdch_wr_en,--S_AXI_WVALID, RD_EN => wdch_rd_en,--M_AXI_WREADY, PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_W_INJECTDBITERR, INJECTSBITERR => AXI_W_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_W_INPUT_CE, -- OUTPUT_CE => AXI_W_OUTPUT_CE, -- END_OF_PACKET => AXI_W_END_OF_PACKET, -- BYTE_STROBE => AXI_W_BYTE_STROBE, DIN => wdch_din, DOUT => wdch_dout, FULL => wdch_full, ALMOST_FULL => wdch_almost_full, PROG_FULL => wdch_prog_full, EMPTY => wdch_empty, ALMOST_EMPTY => wdch_almost_empty, PROG_EMPTY => wdch_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_w_overflow_i, VALID => OPEN, UNDERFLOW => axi_w_underflow_i, DATA_COUNT => AXI_W_DATA_COUNT, RD_DATA_COUNT => AXI_W_RD_DATA_COUNT, WR_DATA_COUNT => AXI_W_WR_DATA_COUNT, SBITERR => AXI_W_SBITERR, DBITERR => AXI_W_DBITERR ); wdch_s_axi_wready <= map_ready_valid(C_PROG_FULL_TYPE_WDCH,wdch_full,wdch_almost_full,wdch_prog_full); wdch_m_axi_wvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WDCH,wdch_empty,wdch_almost_empty,wdch_prog_empty); S_AXI_WREADY <= wdch_s_axi_wready;--map_ready_valid(C_PROG_FULL_TYPE_WDCH,wdch_full,wdch_almost_full,wdch_prog_full); M_AXI_WVALID <= wdch_m_axi_wvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WDCH,wdch_empty,wdch_almost_empty,wdch_prog_empty); gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_W_UNDERFLOW <= axi_w_underflow_i; END GENERATE gaxi_wr_ch_uf2; gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_W_OVERFLOW <= axi_w_overflow_i; END GENERATE gaxi_wr_ch_of2; END GENERATE gwdch2; -- Register Slice for Write Data Channel gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE wdch_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_WDCH, C_REG_CONFIG => C_REG_SLICE_MODE_WDCH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => wdch_din, S_VALID => S_AXI_WVALID, S_READY => S_AXI_WREADY, -- Master side M_PAYLOAD_DATA => wdch_dout, M_VALID => M_AXI_WVALID, M_READY => M_AXI_WREADY ); END GENERATE gwdch_reg_slice; gwrch2: IF (C_WRCH_TYPE = 0) GENERATE axi_wrch : fifo_generator_v8_2_conv -- Write Response Channel GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_WRCH, C_WR_DEPTH => C_WR_DEPTH_WRCH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH, C_DOUT_WIDTH => C_DIN_WIDTH_WRCH, C_RD_DEPTH => C_WR_DEPTH_WRCH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH, C_USE_ECC => C_USE_ECC_WRCH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WRCH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WRCH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => wrch_wr_en,--M_AXI_BVALID, RD_EN => wrch_rd_en,--S_AXI_BREADY, PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_B_INJECTDBITERR, INJECTSBITERR => AXI_B_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_B_INPUT_CE, -- OUTPUT_CE => AXI_B_OUTPUT_CE, -- END_OF_PACKET => AXI_B_END_OF_PACKET, -- BYTE_STROBE => AXI_B_BYTE_STROBE, DIN => wrch_din, DOUT => wrch_dout, FULL => wrch_full, ALMOST_FULL => wrch_almost_full, PROG_FULL => wrch_prog_full, EMPTY => wrch_empty, ALMOST_EMPTY => wrch_almost_empty, PROG_EMPTY => wrch_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_b_overflow_i, VALID => OPEN, UNDERFLOW => axi_b_underflow_i, DATA_COUNT => AXI_B_DATA_COUNT, RD_DATA_COUNT => AXI_B_RD_DATA_COUNT, WR_DATA_COUNT => AXI_B_WR_DATA_COUNT, SBITERR => AXI_B_SBITERR, DBITERR => AXI_B_DBITERR ); wrch_s_axi_bvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WRCH,wrch_empty,wrch_almost_empty,wrch_prog_empty); wrch_m_axi_bready <= map_ready_valid(C_PROG_FULL_TYPE_WRCH,wrch_full,wrch_almost_full,wrch_prog_full); S_AXI_BVALID <= wrch_s_axi_bvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WRCH,wrch_empty,wrch_almost_empty,wrch_prog_empty); M_AXI_BREADY <= wrch_m_axi_bready;--map_ready_valid(C_PROG_FULL_TYPE_WRCH,wrch_full,wrch_almost_full,wrch_prog_full); gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_B_UNDERFLOW <= axi_b_underflow_i; END GENERATE gaxi_wr_ch_uf3; gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_B_OVERFLOW <= axi_b_overflow_i; END GENERATE gaxi_wr_ch_of3; END GENERATE gwrch2; -- Register Slice for Write Response Channel gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE wrch_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_WRCH, C_REG_CONFIG => C_REG_SLICE_MODE_WRCH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => wrch_din, S_VALID => M_AXI_BVALID, S_READY => M_AXI_BREADY, -- Master side M_PAYLOAD_DATA => wrch_dout, M_VALID => S_AXI_BVALID, M_READY => S_AXI_BREADY ); END GENERATE gwrch_reg_slice; gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i; END GENERATE gaxi_wr_ch_uf4; gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i; END GENERATE gaxi_wr_ch_of4; END GENERATE gwrch; grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rach_full : std_logic := '0'; SIGNAL rach_almost_full : std_logic := '0'; SIGNAL rach_prog_full : std_logic := '0'; SIGNAL rach_empty : std_logic := '0'; SIGNAL rach_almost_empty : std_logic := '0'; SIGNAL rach_prog_empty : std_logic := '0'; SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdch_full : std_logic := '0'; SIGNAL rdch_almost_full : std_logic := '0'; SIGNAL rdch_prog_full : std_logic := '0'; SIGNAL rdch_empty : std_logic := '0'; SIGNAL rdch_almost_empty : std_logic := '0'; SIGNAL rdch_prog_empty : std_logic := '0'; SIGNAL axi_ar_underflow_i : std_logic := '0'; SIGNAL axi_ar_overflow_i : std_logic := '0'; SIGNAL axi_r_underflow_i : std_logic := '0'; SIGNAL axi_r_overflow_i : std_logic := '0'; SIGNAL rach_s_axi_arready : std_logic := '0'; SIGNAL rach_m_axi_arvalid : std_logic := '0'; SIGNAL rach_wr_en : std_logic := '0'; SIGNAL rach_rd_en : std_logic := '0'; SIGNAL rdch_m_axi_rready : std_logic := '0'; SIGNAL rdch_s_axi_rvalid : std_logic := '0'; SIGNAL rdch_wr_en : std_logic := '0'; SIGNAL rdch_rd_en : std_logic := '0'; CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH); CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH; CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET); CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET); CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET); CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET); CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET); CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH; CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH; CONSTANT ARREGION_OFFSET : integer := ARQOS_OFFSET - C_AXI_REGION_WIDTH; CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET); CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH); CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH; CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH; CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET); BEGIN -- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports axi_full_din_rd_ch: IF (C_AXI_TYPE = 1) GENERATE grach1: IF (C_RACH_TYPE < 2) GENERATE grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE rach_din <= S_AXI_ARID & S_AXI_ARADDR & S_AXI_ARLEN & S_AXI_ARSIZE & S_AXI_ARBURST & S_AXI_ARLOCK & S_AXI_ARCACHE & S_AXI_ARPROT & S_AXI_ARQOS & S_AXI_ARREGION & S_AXI_ARUSER; M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET); END GENERATE grach_din1; grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE rach_din <= S_AXI_ARID & S_AXI_ARADDR & S_AXI_ARLEN & S_AXI_ARSIZE & S_AXI_ARBURST & S_AXI_ARLOCK & S_AXI_ARCACHE & S_AXI_ARPROT & S_AXI_ARQOS & S_AXI_ARREGION; M_AXI_ARUSER <= (OTHERS => '0'); END GENERATE grach_din2; M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET); M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET); M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET); M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET); M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET); M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET); M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET); M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET); M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET); M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET); END GENERATE grach1; -- Generate the DIN to FIFO by concatinating the AXI Full Read Data Channel optional ports grdch1: IF (C_RDCH_TYPE < 2) GENERATE grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE rdch_din <= M_AXI_RID & M_AXI_RDATA & M_AXI_RRESP & M_AXI_RUSER & M_AXI_RLAST; S_AXI_RLAST <= rdch_dout(0); S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET); END GENERATE grdch_din1; grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE rdch_din <= M_AXI_RID & M_AXI_RDATA & M_AXI_RRESP & M_AXI_RLAST; S_AXI_RLAST <= rdch_dout(0); S_AXI_RUSER <= (OTHERS => '0'); END GENERATE grdch_din2; S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET); S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET); S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET); END GENERATE grdch1; END GENERATE axi_full_din_rd_ch; -- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE grach1: IF (C_RACH_TYPE < 2) GENERATE rach_din <= S_AXI_ARADDR & S_AXI_ARPROT; M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET); M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET); END GENERATE grach1; grdch1: IF (C_RDCH_TYPE < 2) GENERATE rdch_din <= M_AXI_RDATA & M_AXI_RRESP; S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET); S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET); END GENERATE grdch1; END GENERATE axi_lite_din_rd_ch; -- Write protection for Read Address Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 5) GENERATE rach_wr_en <= S_AXI_ARVALID; END GENERATE grach_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 5) GENERATE rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID; END GENERATE grach_wr_en2; -- Write protection for Read Data Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 5) GENERATE rdch_wr_en <= M_AXI_RVALID; END GENERATE grdch_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 5) GENERATE rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID; END GENERATE grdch_wr_en2; -- Read protection for Read Address Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 5) GENERATE rach_rd_en <= M_AXI_ARREADY; END GENERATE grach_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 5) GENERATE rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY; END GENERATE grach_rd_en2; -- Read protection for Read Data Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 5) GENERATE rdch_rd_en <= S_AXI_RREADY; END GENERATE grdch_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 5) GENERATE rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY; END GENERATE grdch_rd_en2; grach2: IF (C_RACH_TYPE = 0) GENERATE axi_rach : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_RACH, C_WR_DEPTH => C_WR_DEPTH_RACH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH, C_DOUT_WIDTH => C_DIN_WIDTH_RACH, C_RD_DEPTH => C_WR_DEPTH_RACH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH, C_USE_ECC => C_USE_ECC_RACH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_RACH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_RACH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_RACH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_WR_FREQ => C_WR_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_RD_FREQ => C_RD_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => rach_wr_en,--S_AXI_ARVALID, RD_EN => rach_rd_en,--M_AXI_ARREADY, PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_AR_INJECTDBITERR, INJECTSBITERR => AXI_AR_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_AR_INPUT_CE, -- OUTPUT_CE => AXI_AR_OUTPUT_CE, -- END_OF_PACKET => AXI_AR_END_OF_PACKET, -- BYTE_STROBE => AXI_AR_BYTE_STROBE, DIN => rach_din, DOUT => rach_dout, FULL => rach_full, ALMOST_FULL => rach_almost_full, PROG_FULL => rach_prog_full, EMPTY => rach_empty, ALMOST_EMPTY => rach_almost_empty, PROG_EMPTY => rach_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_ar_overflow_i, VALID => OPEN, UNDERFLOW => axi_ar_underflow_i, DATA_COUNT => AXI_AR_DATA_COUNT, RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT, WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT, SBITERR => AXI_AR_SBITERR, DBITERR => AXI_AR_DBITERR ); rach_s_axi_arready <= map_ready_valid(C_PROG_FULL_TYPE_RACH,rach_full,rach_almost_full,rach_prog_full); rach_m_axi_arvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RACH,rach_empty,rach_almost_empty,rach_prog_empty); S_AXI_ARREADY <= rach_s_axi_arready;--map_ready_valid(C_PROG_FULL_TYPE_RACH,rach_full,rach_almost_full,rach_prog_full); M_AXI_ARVALID <= rach_m_axi_arvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_RACH,rach_empty,rach_almost_empty,rach_prog_empty); gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_AR_UNDERFLOW <= axi_ar_underflow_i; END GENERATE gaxi_rd_ch_uf1; gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_AR_OVERFLOW <= axi_ar_overflow_i; END GENERATE gaxi_rd_ch_of1; END GENERATE grach2; -- Register Slice for Read Address Channel grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE rach_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_RACH, C_REG_CONFIG => C_REG_SLICE_MODE_RACH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => rach_din, S_VALID => S_AXI_ARVALID, S_READY => S_AXI_ARREADY, -- Master side M_PAYLOAD_DATA => rach_dout, M_VALID => M_AXI_ARVALID, M_READY => M_AXI_ARREADY ); END GENERATE grach_reg_slice; grdch2: IF (C_RDCH_TYPE = 0) GENERATE axi_rdch : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_RDCH, C_WR_DEPTH => C_WR_DEPTH_RDCH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH, C_DOUT_WIDTH => C_DIN_WIDTH_RDCH, C_RD_DEPTH => C_WR_DEPTH_RDCH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH, C_USE_ECC => C_USE_ECC_RDCH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_RDCH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_RDCH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_WR_FREQ => C_WR_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_RD_FREQ => C_RD_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => rdch_wr_en,--M_AXI_RVALID, RD_EN => rdch_rd_en,--S_AXI_RREADY, PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_R_INJECTDBITERR, INJECTSBITERR => AXI_R_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_R_INPUT_CE, -- OUTPUT_CE => AXI_R_OUTPUT_CE, -- END_OF_PACKET => AXI_R_END_OF_PACKET, -- BYTE_STROBE => AXI_R_BYTE_STROBE, DIN => rdch_din, DOUT => rdch_dout, FULL => rdch_full, ALMOST_FULL => rdch_almost_full, PROG_FULL => rdch_prog_full, EMPTY => rdch_empty, ALMOST_EMPTY => rdch_almost_empty, PROG_EMPTY => rdch_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_r_overflow_i, VALID => OPEN, UNDERFLOW => axi_r_underflow_i, DATA_COUNT => AXI_R_DATA_COUNT, RD_DATA_COUNT => AXI_R_RD_DATA_COUNT, WR_DATA_COUNT => AXI_R_WR_DATA_COUNT, SBITERR => AXI_R_SBITERR, DBITERR => AXI_R_DBITERR ); rdch_s_axi_rvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RDCH,rdch_empty,rdch_almost_empty,rdch_prog_empty); rdch_m_axi_rready <= map_ready_valid(C_PROG_FULL_TYPE_RDCH,rdch_full,rdch_almost_full,rdch_prog_full); S_AXI_RVALID <= rdch_s_axi_rvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_RDCH,rdch_empty,rdch_almost_empty,rdch_prog_empty); M_AXI_RREADY <= rdch_m_axi_rready;--map_ready_valid(C_PROG_FULL_TYPE_RDCH,rdch_full,rdch_almost_full,rdch_prog_full); gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_R_UNDERFLOW <= axi_r_underflow_i; END GENERATE gaxi_rd_ch_uf2; gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_R_OVERFLOW <= axi_r_overflow_i; END GENERATE gaxi_rd_ch_of2; END GENERATE grdch2; -- Register Slice for Read Data Channel grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE rdch_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_RDCH, C_REG_CONFIG => C_REG_SLICE_MODE_RDCH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => rdch_din, S_VALID => M_AXI_RVALID, S_READY => M_AXI_RREADY, -- Master side M_PAYLOAD_DATA => rdch_dout, M_VALID => S_AXI_RVALID, M_READY => S_AXI_RREADY ); END GENERATE grdch_reg_slice; gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i; END GENERATE gaxi_rd_ch_uf3; gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i; END GENERATE gaxi_rd_ch_of3; END GENERATE grdch; gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i; END GENERATE grdwr_uf1; grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE UNDERFLOW <= axi_wr_underflow_i; END GENERATE grdwr_uf2; grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE UNDERFLOW <= axi_rd_underflow_i; END GENERATE grdwr_uf3; END GENERATE gaxi_comm_uf; gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i; END GENERATE grdwr_of1; grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE OVERFLOW <= axi_wr_overflow_i; END GENERATE grdwr_of2; grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE OVERFLOW <= axi_rd_overflow_i; END GENERATE grdwr_of3; END GENERATE gaxi_comm_of; END GENERATE gaxifull; --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Pass Through Logic or Wiring Logic --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel M_AXI_AWID <= S_AXI_AWID; M_AXI_AWADDR <= S_AXI_AWADDR; M_AXI_AWLEN <= S_AXI_AWLEN; M_AXI_AWSIZE <= S_AXI_AWSIZE; M_AXI_AWBURST <= S_AXI_AWBURST; M_AXI_AWLOCK <= S_AXI_AWLOCK; M_AXI_AWCACHE <= S_AXI_AWCACHE; M_AXI_AWPROT <= S_AXI_AWPROT; M_AXI_AWQOS <= S_AXI_AWQOS; M_AXI_AWREGION <= S_AXI_AWREGION; M_AXI_AWUSER <= S_AXI_AWUSER; S_AXI_AWREADY <= M_AXI_AWREADY; M_AXI_AWVALID <= S_AXI_AWVALID; END GENERATE gwach_pass_through; -- Wiring logic for Write Data Channel gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE M_AXI_WID <= S_AXI_WID; M_AXI_WDATA <= S_AXI_WDATA; M_AXI_WSTRB <= S_AXI_WSTRB; M_AXI_WLAST <= S_AXI_WLAST; M_AXI_WUSER <= S_AXI_WUSER; S_AXI_WREADY <= M_AXI_WREADY; M_AXI_WVALID <= S_AXI_WVALID; END GENERATE gwdch_pass_through; -- Wiring logic for Write Response Channel gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE S_AXI_BID <= M_AXI_BID; S_AXI_BRESP <= M_AXI_BRESP; S_AXI_BUSER <= M_AXI_BUSER; M_AXI_BREADY <= S_AXI_BREADY; S_AXI_BVALID <= M_AXI_BVALID; END GENERATE gwrch_pass_through; -- Pass Through Logic for Read Channel grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel M_AXI_ARID <= S_AXI_ARID; M_AXI_ARADDR <= S_AXI_ARADDR; M_AXI_ARLEN <= S_AXI_ARLEN; M_AXI_ARSIZE <= S_AXI_ARSIZE; M_AXI_ARBURST <= S_AXI_ARBURST; M_AXI_ARLOCK <= S_AXI_ARLOCK; M_AXI_ARCACHE <= S_AXI_ARCACHE; M_AXI_ARPROT <= S_AXI_ARPROT; M_AXI_ARQOS <= S_AXI_ARQOS; M_AXI_ARREGION <= S_AXI_ARREGION; M_AXI_ARUSER <= S_AXI_ARUSER; S_AXI_ARREADY <= M_AXI_ARREADY; M_AXI_ARVALID <= S_AXI_ARVALID; END GENERATE grach_pass_through; grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel S_AXI_RID <= M_AXI_RID; S_AXI_RLAST <= M_AXI_RLAST; S_AXI_RUSER <= M_AXI_RUSER; S_AXI_RDATA <= M_AXI_RDATA; S_AXI_RRESP <= M_AXI_RRESP; S_AXI_RVALID <= M_AXI_RVALID; M_AXI_RREADY <= S_AXI_RREADY; END GENERATE grdch_pass_through; gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming M_AXIS_TDATA <= S_AXIS_TDATA; M_AXIS_TSTRB <= S_AXIS_TSTRB; M_AXIS_TKEEP <= S_AXIS_TKEEP; M_AXIS_TID <= S_AXIS_TID; M_AXIS_TDEST <= S_AXIS_TDEST; M_AXIS_TUSER <= S_AXIS_TUSER; M_AXIS_TLAST <= S_AXIS_TLAST; S_AXIS_TREADY <= M_AXIS_TREADY; M_AXIS_TVALID <= S_AXIS_TVALID; END GENERATE gaxis_pass_through; END GENERATE gaxi_pass_through; END behavioral;	mit
stanford-ppl/spatial-lang	spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_inst.vhd	1	4666	component pr_region_default_mm_bridge_1 is generic ( DATA_WIDTH : integer := 32; SYMBOL_WIDTH : integer := 8; HDL_ADDR_WIDTH : integer := 10; BURSTCOUNT_WIDTH : integer := 1; PIPELINE_COMMAND : integer := 1; PIPELINE_RESPONSE : integer := 1 ); port ( clk : in std_logic := 'X'; -- clk m0_waitrequest : in std_logic := 'X'; -- waitrequest m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata m0_readdatavalid : in std_logic := 'X'; -- readdatavalid m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address m0_write : out std_logic; -- write m0_read : out std_logic; -- read m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable m0_debugaccess : out std_logic; -- debugaccess reset : in std_logic := 'X'; -- reset s0_waitrequest : out std_logic; -- waitrequest s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata s0_readdatavalid : out std_logic; -- readdatavalid s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address s0_write : in std_logic := 'X'; -- write s0_read : in std_logic := 'X'; -- read s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable s0_debugaccess : in std_logic := 'X' -- debugaccess ); end component pr_region_default_mm_bridge_1; u0 : component pr_region_default_mm_bridge_1 generic map ( DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH, SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH, HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH, BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH, PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND, PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE ) port map ( clk => CONNECTED_TO_clk, -- clk.clk m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata m0_address => CONNECTED_TO_m0_address, -- .address m0_write => CONNECTED_TO_m0_write, -- .write m0_read => CONNECTED_TO_m0_read, -- .read m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess reset => CONNECTED_TO_reset, -- reset.reset s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata s0_address => CONNECTED_TO_s0_address, -- .address s0_write => CONNECTED_TO_s0_write, -- .write s0_read => CONNECTED_TO_s0_read, -- .read s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess );	mit
lfmunoz/vhdl	ip_blocks/packer_12bit/packer_128.vhd	1	6929	------------------------------------------------------------------------------------- -- FILE NAME : packer_128.vhd -- AUTHOR : Luis -- COMPANY : -- UNITS : Entity - packer_128 -- Architecture - Behavioral -- LANGUAGE : VHDL -- DATE : Jan 10, 2015 ------------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------- -- DESCRIPTION -- =========== -- 16-bits as 8 samples =128-bits -- 12-bits as 8 samples =96-bits -- 12-bits * 8 samples * 4 cycles = 384-bits -- 16-bits * 8 samples * 3 cycles = 384-bits -- When val_in = '1', this entity will accept 4 chuncks of 128-bits unpacked and output -- 3 chucks of 128-bits packed. -- -- ------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------- -- LIBRARIES ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; Library UNISIM; use UNISIM.vcomponents.all; ------------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------------- entity packer_128 is port ( clk_in : in std_logic; rst_in : in std_logic; val_in : in std_logic; data_in : in std_logic_vector(127 downto 0); val_out : out std_logic; data_out : out std_logic_vector(127 downto 0); test_mode : in std_logic ); end packer_128; ------------------------------------------------------------------------------------- -- ARCHITECTURE ------------------------------------------------------------------------------------- architecture Behavioral of packer_128 is ------------------------------------------------------------------------------------- -- CONSTANTS ------------------------------------------------------------------------------------- type state_machine is (state0, state1, state2, state3); ------------------------------------------------------------------------------------- -- SIGNALS ------------------------------------------------------------------------------------- signal sm_reg : state_machine; signal reg0 : std_logic_vector(127 downto 0); signal sample0 : std_logic_vector(11 downto 0); signal sample1 : std_logic_vector(11 downto 0); signal sample2 : std_logic_vector(11 downto 0); signal sample3 : std_logic_vector(11 downto 0); signal sample4 : std_logic_vector(11 downto 0); signal sample5 : std_logic_vector(11 downto 0); signal sample6 : std_logic_vector(11 downto 0); signal sample7 : std_logic_vector(11 downto 0); signal sample0_cnt : std_logic_vector(11 downto 0); signal sample1_cnt : std_logic_vector(11 downto 0); signal sample2_cnt : std_logic_vector(11 downto 0); signal sample3_cnt : std_logic_vector(11 downto 0); signal sample4_cnt : std_logic_vector(11 downto 0); signal sample5_cnt : std_logic_vector(11 downto 0); signal sample6_cnt : std_logic_vector(11 downto 0); signal sample7_cnt : std_logic_vector(11 downto 0); signal counter : std_logic_vector(11 downto 0); signal valid_reg : std_logic; signal zero_32 : std_logic_vector(31 downto 0); signal zero_64 : std_logic_vector(63 downto 0); signal zero_96 : std_logic_vector(95 downto 0); --********************************************************************************* begin --******************************************************************************* zero_96 <= (others=>'0'); zero_64 <= (others=>'0'); zero_32 <= (others=>'0'); -- Genereate a counting test pattern process(clk_in, rst_in) begin if rst_in = '1' then counter <= (others=>'0'); elsif rising_edge(clk_in) then if val_in = '1' then counter <= counter + 8; end if; end if; end process; sample0_cnt <= counter + 0; sample1_cnt <= counter + 1; sample2_cnt <= counter + 2; sample3_cnt <= counter + 3; sample4_cnt <= counter + 4; sample5_cnt <= counter + 5; sample6_cnt <= counter + 6; sample7_cnt <= counter + 7; -- select between test pattern or input data process(clk_in) begin if rising_edge(clk_in) then valid_reg <= val_in; if test_mode = '0' then sample0 <= data_in(11 downto 0); sample1 <= data_in(27 downto 16); sample2 <= data_in(43 downto 32); sample3 <= data_in(59 downto 48); sample4 <= data_in(75 downto 64); sample5 <= data_in(91 downto 80); sample6 <= data_in(107 downto 96); sample7 <= data_in(123 downto 112); else sample0 <= sample0_cnt; sample1 <= sample1_cnt; sample2 <= sample2_cnt; sample3 <= sample3_cnt; sample4 <= sample4_cnt; sample5 <= sample5_cnt; sample6 <= sample6_cnt; sample7 <= sample7_cnt; end if; end if; end process; -- packing state machine process(clk_in, rst_in) begin if rising_edge(clk_in) then if rst_in = '1' then data_out <= (others=>'0'); val_out <= '0'; reg0 <= (others=>'0'); sm_reg <= state0; else --default val_out <= '0'; case sm_reg is when state0 => if valid_reg = '1' then sm_reg <= state1; reg0 <= zero_32 & sample7 & sample6 & sample5 & sample4 & sample3 & sample2 & sample1 & sample0; end if; when state1 => sm_reg <= state2; val_out <= '1'; data_out <= sample2(7 downto 0) & sample1 & sample0 & reg0(95 downto 0); reg0 <= zero_64 & sample7 & sample6 & sample5 & sample4 & sample3 & sample2(11 downto 8); when state2 => sm_reg <= state3; val_out <= '1'; data_out <= sample5(3 downto 0) & sample4 & sample3 & sample2 & sample1 & sample0 & reg0(63 downto 0); reg0 <= zero_96 & sample7 & sample6 & sample5(11 downto 4); when state3 => sm_reg <= state0; val_out <= '1'; data_out <= sample7 & sample6 & sample5 & sample4 & sample3 & sample2 & sample1 & sample0 & reg0(31 downto 0); when others => sm_reg <= state0; end case; end if; end if; end process; --******************************************************************************* end architecture Behavioral; --*********************************************************************************	mit
AlexMitakos/DES-in-VHDL	testbenches/test_right_shift_by_1.vhdl	1	474	library ieee; use ieee.std_logic_1164.all; use work.all; entity test_right_shift_by_1 is end test_right_shift_by_1; architecture behavior of test_right_shift_by_1 is signal data_in: std_logic_vector(0 to 27); signal data_out: std_logic_vector(0 to 27); begin uut: entity right_shift_by_1 port map (data_in, data_out); testprocess: process is begin data_in<="0111111111111111111111111110"; wait for 10 ns; end process testprocess; end architecture behavior;	mit
AlexMitakos/DES-in-VHDL	testbenches/test_round.vhdl	1	741	library ieee; use ieee.std_logic_1164.all; use work.all; entity test_round is end test_round; architecture behavior of test_round is signal left_plain: std_logic_vector(0 to 31); signal right_plain: std_logic_vector(0 to 31); signal subkey: std_logic_vector(0 to 47); signal left_data_out: std_logic_vector(0 to 31); signal right_data_out: std_logic_vector(0 to 31); begin uut: entity round port map(left_plain,right_plain,subkey,left_data_out,right_data_out); testprocess: process is begin left_plain<="00000000000000000000000000000000"; right_plain<="00000000000000000000000000000000"; subkey<="000000000000000000000000000000000000000000000000"; wait for 10 ns; end process testprocess; end architecture behavior;	mit
MrDoomBringer/DSD-Labs	Lab 8/reaction.vhd	1	4056	-- FPGA reaction time tester for Altera DE-2 board -- Cliff Chapman -- 10/27/2013 -- -- Lab 8 - Digital Systems Design LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY reaction IS PORT ( -- Reset system rst : IN STD_LOGIC; -- Set time interval set : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Trigger button trig : IN STD_LOGIC; -- 50 Mhz external clock clk : IN STD_LOGIC; -- Sevenseg displays d_HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX3 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- Trigger light LEDR : OUT STD_LOGIC ); END reaction; ARCHITECTURE rtl OF reaction IS COMPONENT sevenseg_bcd_display PORT ( r : IN STD_LOGIC_VECTOR (7 DOWNTO 0); s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT; -- This feels like a GREAT way to screw yourself over with -- overloading common names. Maybe that's just me. -- Either way that's why we have the _s hungarian postfix on these. TYPE state_type IS (idle_s, wait_s, runprep_s, run_s, hold_s); SIGNAL state : state_type; SIGNAL clock_1 : STD_LOGIC := '0'; SIGNAL cnt_rst : STD_LOGIC; SIGNAL disp_buf: STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL mil_cnt : STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL cnt : STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL cnt_div :STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000000"; BEGIN -- Milliseconds elapsed display disp_low: sevenseg_bcd_display PORT MAP ( r => disp_buf (15 DOWNTO 8), s => '0', HEX2 => OPEN, HEX1 => d_hex3, HEX0 => d_hex2 ); disp_high: sevenseg_bcd_display PORT MAP ( r => disp_buf (7 DOWNTO 0), s => '0', HEX2 => OPEN, HEX1 => d_hex1, HEX0 => d_hex0 ); -- Clock divider for millisecond from 50Mhz clock_div: PROCESS (clk, rst) BEGIN IF (rising_edge(clk)) THEN IF (cnt_div >= x"61A7") THEN cnt_div <= x"00000000"; clock_1 <= NOT clock_1; ELSE cnt_div <= cnt_div+1; END IF; END IF; END PROCESS clock_div; -- Counter for milliseconds timer mil_clock : PROCESS (clock_1, cnt_rst, state, cnt) BEGIN IF (cnt_rst = '0') THEN cnt <= x"0000"; ELSIF (rising_edge(clock_1) AND cnt_rst = '1') THEN cnt <= cnt + '1'; ELSE cnt <= cnt; END IF; mil_cnt <= cnt; END PROCESS mil_clock; state_monitor: PROCESS (state, clk, rst) BEGIN IF (rst = '0') THEN state <= idle_s; ELSIF (rising_edge(clk) AND rst = '1') THEN CASE state IS WHEN idle_s => IF (trig = '0') THEN state <= wait_s; ELSE state <= idle_s; END IF; WHEN wait_s => IF (mil_cnt >= ((x"00" & set) * x"3E8")) THEN state <= runprep_s; ELSE state <= wait_s; END IF; WHEN runprep_s => IF (mil_cnt = x"0000") THEN state <= run_s; ELSE state <= runprep_s; END IF; WHEN run_s => IF (trig = '0') THEN state <= hold_s; ELSE state <= run_s; END IF; WHEN hold_s => state <= hold_s; WHEN OTHERS => state <= idle_s; END CASE; END IF; END PROCESS state_monitor; output_monitor: PROCESS (state, clk, rst, mil_cnt) BEGIN IF (rst = '0') THEN cnt_rst <= '0'; LEDR <= '0'; disp_buf <= x"0000"; ELSIF (rst = '1' AND rising_edge(clk)) THEN CASE (state) IS WHEN idle_s => LEDR <= '0'; cnt_rst <= '0'; disp_buf <= x"0000"; WHEN wait_s => LEDR <= '1'; cnt_rst <= '1'; disp_buf <= x"0000"; WHEN runprep_s => LEDR <= '1'; cnt_rst <= '0'; disp_buf <= x"0000"; WHEN run_s => LEDR <= '0'; cnt_rst <= '1'; disp_buf <= mil_cnt; WHEN hold_s => LEDR <= '0'; cnt_rst <= '1'; disp_buf <= disp_buf; WHEN OTHERS => cnt_rst <= '0'; LEDR <= '0'; disp_buf <= x"0000"; END CASE; END IF; END PROCESS output_monitor; END ARCHITECTURE;	mit
Given-Jiang/Binarization	Binarization_dspbuilder/db/alt_dspbuilder_vcc_GN.vhd	20	373	library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_vcc_GN is port( output : out std_logic); end entity; architecture rtl of alt_dspbuilder_vcc_GN is Begin output <= '1'; end architecture;	mit
Given-Jiang/Binarization	tb_Binarization/db/alt_dspbuilder_ASAT.vhd	20	3282	-------------------------------------------------------------------------------------------- -- DSP Builder (Version 9.1) -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera -- Corporation's design tools, logic functions and other software and tools, and its -- AMPP partner logic functions, and any output files any of the foregoing -- (including device programming or simulation files), and any associated -- documentation or information are expressly subject to the terms and conditions -- of the Altera Program License Subscription Agreement, Altera MegaCore Function -- License Agreement, or other applicable license agreement, including, without -- limitation, that your use is for the sole purpose of programming logic devices -- manufactured by Altera and sold by Altera or its authorized distributors. -- Please refer to the applicable agreement for further details. -------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; library altera; use altera.alt_dspbuilder_package.all; entity alt_dspbuilder_ASAT is generic ( widthin : natural :=8; widthout : natural :=4; lpm_signed : BusArithm :=BusIsSigned ); port ( xin : in std_logic_vector(widthin-1 downto 0); yout : out std_logic_vector(widthout-1 downto 0) ); end alt_dspbuilder_ASAT; architecture ASAT_SYNTH of alt_dspbuilder_ASAT is function GetWidthUsgn(win: natural;wout: natural ) return natural is variable res : natural; begin if (win-wout>0) then res :=win-wout-1; else res := 0; end if; return res; end ; signal msbone : std_logic_vector(widthin-widthout downto 0); signal msbzero : std_logic_vector(widthin-widthout downto 0); signal Unsignedmsbzero : std_logic_vector(GetWidthUsgn(widthin,widthout) downto 0); signal MsbOverFlow : std_logic; begin ev:if widthin=widthout generate yout <= xin; end generate ev; sat:if (widthin>widthout) generate Gs : if lpm_signed=BusIsSigned generate msbone <= (others=>'1'); msbzero <= (others=>'0'); MsbOverFlow <= '0' when (xin(widthin-1 downto widthout-1) = msbone or xin(widthin-1 downto widthout-1) = msbzero) else '1'; process(xin,MsbOverFlow) begin if (MsbOverFlow='0') then yout(widthout-1 downto 0) <= xin(widthout-1 downto 0); else if (xin(widthin-1)='0') then for i in 0 to widthout-2 loop yout(i) <= '1'; -- max positif end loop; yout(widthout-1) <='0'; else for i in 0 to widthout-2 loop yout(i) <= '0'; -- max Negatif end loop; yout(widthout-1) <='1'; end if; end if; end process; end generate Gs; Gus : if lpm_signed=BusIsUnsigned generate Unsignedmsbzero <= (others=>'0'); MsbOverFlow <= '0' when xin(widthin-1 downto widthout) = Unsignedmsbzero else '1'; process(xin,MsbOverFlow) begin if (MsbOverFlow='0') then yout(widthout-1 downto 0) <= xin(widthout-1 downto 0); else yout <=(others=>'1'); -- Max Positive end if; end process; end generate Gus; end generate sat; end ASAT_SYNTH;	mit
Given-Jiang/Binarization	Binarization_dspbuilder/hdl/alt_dspbuilder_decoder_GNSCEXJCJK.vhd	13	947	library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;	mit
Given-Jiang/Binarization	Binarization_dspbuilder/db/alt_dspbuilder_decoder_GNSCEXJCJK.vhd	13	947	library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;	mit
benjmarshall/hls_scratchpad	hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd	20	103154	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AbrLtZEWaMZ9QRIEqn+KbGJaY9tnAHwhbFbsPC7WH49ehpa1EbqXv+qkeNRGupFwZ63XKanLVUyO My0fDcdlyQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jBjvZpZ5ZMxrEO8+CEfz6CEl8aMhkYM5vXXCdl+QFohneB/4ao6UdzksCSxNPxkQX54YmGSOciXP wgiPEkvihckzTQ7V+IwmdcU3758CZsJi1jYV4WKld6YxfbWBrziJy4pEooel9pwm0aG1jMx1yNUM erFXjNZfwKELIgXdp9g= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bNlKYiiGIQP+R/ChMF9YxWObkJMdPWBzZKUDypAuNCvFSKj2ODeFkzLXYHokfw+rz7RZe5YojYmq 4UkICxShbV1k/N1YYli9QKFi7npsW0xHaRa8L0tSoNNqAKETg1msjVmjBV5kKgQ78l19v/4te7qL zUqdthBriU3NcZYre5k= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0gJe90X6qrVRqoGU7iK/i5s05zq/0GlJ22Kt2H/04aXbES5oZ4I0aGRfiLSYUCL8istn1JleJ/n3 1/LRSIHwjesRoSy/6j9iedPDLLSSnKq+N+ZcvCJl8gg/L6B9ChU+h5YNE7HqJVfqJzqKWKPqsHB4 WVtjQ/Uh+QwxJp4Q/GXnPw1qlnDs2s6lJ8EK8000R7Any16QZ06T5S1IW5s5v9bKhWJj2Oj7lmWo 6QSr9mTUFxCIV/m+pXzsIOsSgFWqsBmD8jksQw5AorgxI1HaqEa3+sl/imtv2p//6lwEVtz8coiR PUlfIUpZ3ecBYh1Zuc/GrakwiRgEs/Yjfe+jCA== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ux0aTH3zrSOSGrjxNBhNJ8nXWhxNzkLj/DcKiIgChJ1nxm8i4YMzp0L+VdbHtn6L3ZPNF7NTEh1P v7Gcx16JuF2FM4sw/t6m+FCjX3oHl0zUFDs/HfDB1IEXz+2hsgoR9SYF+bXbSth9Ql5SVw6WlbpS yFwlhS2eW7RGdfH7yFg8yRwWXcYySMv+L+udV6VzSwe0SODgbmC4o26VRMdm0RBQjLnYxl3eT+4N Qf9DbWnbFLLU2LtQWORMV3hNidJEmt4J99c08slF3izsh110Cv87/wiU6Xuvi2AB6jI3wVkno8/h 1xSxQBnRHm/fJHMh/8PrydoVk8qMhMXs9UM3dA== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block A3eq7CQ1ZEC2Oz4Co0wE9eavdVVL5N2w7vnxu/t08WjNVvgkDcorbVB3GWcUKigHFQo0FHxElw0D PA15/K+npi+dagAdVUmv5cfV+KYrdhCLG+Kvl0Tcm6fhXM4RH49frRlov9a41BctZWlMEXzlO2Ei 69nxF8+cDN/RPLjSUoKp8oVTX2g6+udi83fdCBYaBZQYCaaDSNeGqephcoL2zlXyK7vU9KpsDUWJ oZshHV12Yw5hL+4YuSmKv1aODQadN1UJ8qyFc0vRYTAqwP+hcDUwxiR48olGBo7U7czJnFk4AkkD qULDB9rPKRIK3YJacz6Pp3GAHUDGm2JO78Eg8A== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224) `protect data_block JcYdUx53b3OsTtOdv/P3/dHcfx3utNQitl84Eb3aQ6aN2AhKiDHBCYuvObX/v/9/q30o29Voi9Xv 1eu+5HrxgmBEFCpVYOVqTx+/1TnGsOn7DKuzvOHcne9bSxaTDrHQUCa38xlkHitY67JkqOSIhVm4 jpO7JF5H+JCbmXDt6F2T2wcpFyMe6Oyq6RJfEQlANaFqDnOQOn74eKDH4FfNR3DAsyf+4EzHf5OG TW+7XXmSI6vfomJkezPGmHNVoROjvgFnK7TnF0VmsgNYiKlql/PnEKKsUxo7PMuYq6GHoxcRo6tI +AJMZXAcc5avne6SU/2mOc1O1rYlDfuMOYM72e7no1V5trXotFkDNz5Yw9t1TNO5PzYih/V3YVbU NDBobDLVy/wQ7ecc0PsBimCh2Y7dqxU/EZO5RSJamz23VZJzVUVgJ45yBITzYoilSrt0WNdaFHyC PWPFiPnYKP0yDw05pHULxNgTnxK3YRDelWlT8Le5QF60m/HLUi8Nyi4fLPTjArMLSc5DKmg658jh JSjyTrQq++qYQaFFjKBUDtVvAWZYVhPnCexdXjRceDsgeTaL1yHhb8dS3xjv6QOjRzHBL3HR2Ob5 H+AbHQEQSXdGVxRnFCXi/TKUvtom8R7+JjrA+0H8CcmsD19UbQmxBAIgVidUDxKPApBiSOboEK1x FB7wxHjCEI+8HPUeIwoxSg1FWY9CWrNhv4GbD+j0JemUcvG9HF+3zIwWbp/5UG1Z4uD4VYnIGsT7 ozoOFMVqAbZ9MVvvKWapv0P5mEIR6VlYk3l75W/7tanWiiOn2mFXHWzb40Nep2bXDj+PtAa317DY eJIwtVGdN/D22e6H24LqEMCT5OepE3aFof4S5dNwpe/x93UfOQs30Ddd+SejlVq1yxXLn0H6PsBG 2LJDA1F5NhqqlcVCkAuKwjG2QTvH5xG2s2mBjJsZDcB5mVc2E341U9VvVXgaof5srM2G8VPHbjwv DXh5h2kfGC+1flf2tSWIBfCB9zePvwkF/0HWgEUaLfu9AKO9sJBs+saKvXtVjYY3AmDruCCXM26z hl4STPxaAahx5qIMIXOmXmFBD9wypKP7t90uopZxOSL37I7VO78QjxQB0+h89IrOPr/h3l7Stls3 ewOcb6q5Gu0IOyJEW7lb+6eXgSWd6x0g3hzg/N/0fHiWVO+zcwfulD3tlAEoE9KyD4i0vdFlepNu nehaW4Kl/Hhl/1NzQ/03nZP9nkSMADlhZm6pW4XVN1+sZ2EXsC3fe1zc08URdBUVJy52cj/GAK5+ 2r2x64XO8C9VxmE1bQzv8MFRwuIYwXfn5XQLCu7rRvRxHn1nhqdbNOfyQkaftCvt6pn3YYMqCEsh NaCh/3weMZZ4R+2N4RQjrFQJ0LGf6cr9DluL4GBsTewvbZWsSk1RPYOSofv5WBejf1lv4vjZeYKx RT0N6mYldxbDlWR3AdlUyhsionLdPrjCVil218uZBhEBmIUJjEj+IIixWvDe9zXMdMXAfVeqpZe5 iqQSeghvfFX5u+6aI2+Ysjs6Ee6x2Z4Sl4txYDlqsF71hPL2hXSc6O6Lu6rePadCuS7gF4Rym8ap yTKLTCVQAgHEZym5o0HsXcbzF/5aPPlp31wgnRZmfNLo2MAbQRLWMxImz74O29tn8MGcexq3D763 RrcOOFbske3p1O7voWsQMf3AsMCkdnbqqLGvM/KVFvjqoISK583P/ZBvCj/dKJWuQjiHORGHhex+ CJk6OvfiOuxlB11yDfvQf9E/gaw2yiIbz0M7scZ69+/8as+HhFR3umpKPNlaPOvlqBl73MtouusL kxQKrCgQpSj7Qz9TERJ471PsJouLReRBseMZ5wZBc9oD/lblzy0p0qnJaa7AAmUfPxj6GfEm2BtD Ltq3GUYuAqcA5UHCxOS7a4jFsBN3Em6nYBPNTjIQ1GoTDASpjgEbjJ94V8PqXr46HFPrZbhAJoh6 BC7jmwzTPL1boaxSsIHZiq5XkWjiG0Fl2kMRo9pnxn2Djx1GRrzI9JCNWjeGEje8mNA7/sMq2xGf JoX60sufhWSY6pdJOLeF5ykh3P46LEqWul5krASGOygQ8jsElx0mqMqjwb+rcDi+Bjvk8Mpz+TMB uvf2Kp7Y/jjNDWbMbS362U1Rz1ik69PIdnDDFhoPs6s+CW6/XvFssTPUPaudKJ9nNu0oEDYW7cjn dgkTk8++gdo8oLTSQtn/RF2U4FWmN2FPMb9oDXTciVWpMl+r7AfNJpuQ/2qFis4h+iRY615JsAJ7 NrGL/DTL4CzkpsLzb44Im1Le6aGOw6z5DZBueGX2rWkGPbDzW7IdyY0X+JRZlgLcNV0VUYOjrg1i Q9UCKpY7g3KEHrFiBjrZkPVrmQQWHqhyiTEAjTDTMgaxk5M5wWGtMAe9erd1WbNWN877pjT6GkKD oR2tonp7V0nHHp2Y9wkittxj4vvtES4nMKMle3rQNn7xz3s5/5wYLOcyKn+J9FybgXezdTbch+3d nnmF+yZPBt4R71KvlR+NWPI2QTnnFME2T0xXQOpkX9Rm7meHqjpI6cUHaDWKNDxSbZwH7ABw2MZQ JAFoCu4cHJXWp9PzgxPtuaDrEgxrisO+kyIDzYu0bhr0sE1euNGSHpE7jR2flPgvS3d8F6mzkSsG LrhGYr5DYGHY3XyRT9mbTgCpgq9+vDOAHnOPh+s5IK7xC2BcD/aL5NLUWbvxtaAjHPhAVXoJdwup RK3PBpnBswLbjodqVTjZaL4FH79yg8rOmiOGwbOcEaU1+7vhBSX9+Dk6xqZontADrIkL/mI6/lqc 3Ojb8VdJOdxhWKZ0w53OFUYxCLecLiCeye9ZFo6Uh6ZncDqgz3jJFTXhS0tH1j5aHfXiImxrPp4I /Qmpiw0ZKIaqkGBKYY9368wMcMQNLfEms1B0JJsmahj1namwvs5DE8cHOO1LlHvPOiPm/qFRWTsp YULmolXqQN3/c/nT2N5bOilFSAj+w0cMfxlWIsnGtGt6x59GN0AsG8PvKo30zEsrjlGc5gii/dwv 6XUuMnvKl+CoOytiFqMjMFV2IaP42joEd4iocd8r/iIOf6IYliossSyQRPFgyMTvcEpKf/AMNPN4 AtaJ8dUn630dEokCmuq1ydM51QFUmf28+9Hy7V7sBhKaMz0J48hve1vluXF+5yy/IpIO+KRooQYO V0mXcy1Y/RCsmzVk6NKI70DO7/CeSJbZVMig7igFkjxDoi2NzqRTkpd4zAjDpUnIwfjnXZBhtraG VjPyVRAydV231L3nsz86ywAEQwWGBC7je45ybk7MjxHAN6D/lieDBBVyq2DVXo3qTL7bhVylE4CW uWfebqqYrXBCii7/pXCvLhvW3SCziIQc8S8wqpaq+J3BoH/fnmtv+53dEN2zhD2Jrki5jpxVMNWH SCaBDh2r0jwRJ4zkidB+kCuNyteD9V6rH5a7BbKEw/PwqFZB5vQScCy2rz8LJ4lMvDcl937sCcXW cpcm21xpoSSrEibBkSeZvqz2EdAvqiAHGMzjdDbfQXMnW/sivNDSxFCxvXndmzYZwvOUArLN2t0R aQZwzyfYWHVx3+rGhSePGi/njGN9N6sBQA9Jl8EMOwt/2rTVzvgNamWDldYkkwTKdWN/pR9tt7J9 y6YlakfarE3ffId0LW7zpmneR0naXLxJBPT9GqkXEy5aYx2UzAm50SWVM2Pbm8i/s7JQDfBSog/J O44R/R7AEHGp5iIRokL/fQqohmHLNJmc1iQ3Ne7fAXlOH5MOgBlbbZyTy4PQxZ+1dJLhSHy7aHoT BcQeS5aAZrRMtoGRVL9w8dofqnynherR7FMfx3nLQlUZqgKvuzXIRHZEEH+2gZooyUn8c6z8r9/W bbz3HVmF+J5ytAYVq6TAm5Jp6bwZ+YJRaNXxiaqQTWLYDeyamHQeZ4PVMP7Tel0iibLAKkHZ/yTM L1cnxFm7TXC470HHRqomxUoDy7YMsBvZdPOwL4zTCDupNCS51ljfcwj73VPL+deuBxkEeMlh1npP OVNqxyQ2K3WUbFFMZaCcf9NI+db6FQAm//ghHe1mIOJHwUmAUwnAOoYKeysyzLQiWF66UuQ0vHfe oeeb6X7UmQyIitKPXi9/8vZo1QMrU3bKeUOfv/Phvaz2ykHcnLaexeXHY0odDTeA/wbmLLMbnU1Z F14963JOnWa8EI8xVIBOVCndXGs7dHcGUBecRU6D27/gP+MIcbUyu+MomX5Edpzw/RlQMeTRUv+X gVCepP5hOwpqNENL8PQoEd1+l3QN+CmDrpqxKuDbMruCH1klQGi2KyURrk0xW3tvRx78BzADC6z/ e4krry4RIbgpjKpCMZ36KJhZhOJ4XrMNQOASJHrs/tvs4uubgKfELrt5ffESa0A8mbpQBU4diU/O jEtRKd4epHxn41mOiRYaHTqpSDWcwv6ETHyqceJCAzmPi5GhHZ0aUYiz3CIV7bOvynVTC6iTkNvY Fjc16r6Y1AF4aON5OX0kVZO4WQCBVK/j9xz+kFdZtK0WUb96KOXdn8+99oQp/XiLXzlmFCTVa1hk YeOIbueyaNdKmfjdONFE0ucCtf7MOuHzR7+0E7n9J1cqzYbsW6LMHq0kqwSrE3z80zKDhaPL3ZST V89l/yh7jw5kkbSnMy0QJLDrU+9YWKdtI2UHS5hLThDdgcMhLv8XU0W81bhsd53nwoI/xPyUKmee lueOrrko18nZgmGewHoRSJErs+j48xiYcWr0OGSVq1E/EXQp/I0rnG26R6ZMDUS1UlC0M+yzSUKC KeNa0JnstdmEiAcc2NbqwAkyf6zikHbOmZu7fq0kHO92qH1uIsXGUtn1PPV//e6upK0jNPwS4JG6 W+fAmEd5Wz/lmsUiSgf9YXz44Z2i5CbWP2RuFFTBNbyD9LFni/ox6MuVOkBxtuFhmstwNT9gqMEd lDbiRGAzlHSBvDfYmvS6pt8YtlIsL4v2RdpKzxu9okBFcaL4dSPCNv9Nde8Cr8h7DgZ5ohreqfr9 r+hYLwBRTUd7nyROUSNYtamBNa8gFFkrWX4gEkuCTz4RW9i9sIVfKRQJ6QN6IticXRe5Ik1GzcO/ AC+Wv6GYuGFVlU5ymWRhL//1GQ0aspVTyq27DhWucO1AQmEH2Le4QTUJzg1zzS2qAIB0TN1lfzRV qz8RrNO37JkB0SfFFeqMRwoEpRkx6p41enKF7KhvYyLK439yo37yRaQtdIgoWEjrGq743/rj3eMa XfbwzE1IBPNONtBtmfAm8RhCZDJyGluA7z56GXCnPdm9fNReTlz7L4m2BfO8oaUUr1WevXuYAF/Q HrxDyxC6BKRD6JWGGNRN6x03NgBssWWLrfVqn4lX85iBN3A6pug+7r6Y5ZNkfKU8FVrbuOqsHlBI PAaZ0qYincGQoNZs604N10cwNrizRdHbbygRGdqZrrjOX0y788Fa7UrL9KR2mtaO4x+emY/LamW+ /GUGaVhUYUu4SP0mGdFvy9IBl7ORg9VWvzGPQArn2YJwA+a6byIv3fJkkn09rPQxk2EzeSJ7VdO0 2qT/qYJhZoOb0fBEESWBEAGYed+4pgpc/xPo6vdGPYRmxQOcevPZFCuS9f12/LBx976Lq5E4GdKE BnfH9oHmho57b4VcG6afOLk4VfiqgDpH0oe8+09JtJvIXfzbAHZuNc+OPKf1cgMv7jXQjMhMwkzW 8EA+ZRCMwXy7HedH0b7Lriy/zl5fVlMDRnzmi9cQbE6FPQ8KWLfYNK7tU4xsTaKOHOLDvmuGVpTH ePdwPKG+N3CqkoXNTM2mfLtow7XbNKflv8klPybOpGPRLXBNlQoXyz2oxIRPAPtIHp1EBciJSDaW nlm+7Ykx9BI4mAecCUSiyCUGdOhzIA+myCSX02+Q5R8U/4PSFhNgbZo0PVJSs7xBdgq23eVrYHPl EvhwBx9wyxbasow6R6plTcXdLVyxaVVNat98d77Yi67juUARbex2GWyi/VakJtF47wRT0izyf/fy B601vCy+lGibHhtljMWAm59ahjCseUxcXcY2mif00YPlwzzgR6mMzEBC97KyNB2bvknFAvEXENP3 1UqCTPvZFCzxiiO0TqRi2Vu7SPI7RKcJhzh2gZSXBbHjUBtKheRR7HKqdQBYG99XmSWwg+DOfq0B xPCoFTLUzkSuRQl3CWs1gSCw4WaDaN8INIFw5NX4CPiQtmu72WOpCEjqaZOLS+UFqQX5i2Z5lWMF KMBLc/2dQt5mw0aXUCDvBTgkpZJV7/hejuiGISy5l3doCfteWxAplUsqitu+ykMLdMjqIXuAyFLq ETohUWC+tHJ+VY0kNxhk/1uSSlzx12cvV/z9lic18VYylN6pzktvG+jRrhBVo73eIDgIIv14BPrw I+lptJAlOlGsafAJPMuYvP9Fw5WYky2Y1AqW1VQ7a/TfAHjn01q02r2Db/DtzJQ8DRnVEsNr1rnF boJhSaFcZbmi/Kx4/wlSQBpqA+AJWAS1SP3eDPdv9TA112Oa22AUIQvIalRfsM7LxvT8eCgi+jy6 XJ1azPffzo0+yjdl1ZT4r4RQ8TB4x2g+RAJNx05n1M5fXymF2Y/YR5X17uGfyQC9zuB7kXZACMFQ D+x6zkLjhZankOAqjdTeikgRRitfIf0urJf9MgP/anRKHIUiG045w6kykistBjUIeQ3XmRT6Xll8 KeE+lRMdmwh5fpGykkGVqdOG4syihTbZ48iNXfpv57sq3D7V0bWkIRAh/pi51PQXWQL06zUeO7r/ DnqH16ELZfkt9Y9+cxFiHNVASWV9LH+ytec/7jJilZovfl+OMm5syDPatNIjxS9KkAVITSJTo5lO J2usU4984wQ3QRmJW5QHCj1tl1P7E6aVVxBnNvUE7+LbULBIM8hwbcwsnYR2eGZrV+krufP78VXy b0YVkqUVqu6QPS6AlfPLtllcBMKY7o/ahkMR0mPLUqwUTOt54NFhkGz+qcX6B+d0Via9QyD74ira CU6sVmDJkm7Ce5UkQz8cYFZRQ/w2LrT2Ed4/zV0s44qhChpbDKHN/XLpG2k8PWf3IDInJpR0J/HR NCkInRjOI5skGW48TGGODnJpfi1vUawK8EZW4fpSlSQO2GYUaL1YmiyECRD7EfD/ag/pW5ecJHmt UNqo676wBpztAKd5JcFwFnNLA+WXgotD1W4EbO//gXt/rEJ1z0S/L0CDCtVyJK0E4qJ9CQE8NxJp wxgdNgL+Iw3C8MRK6ty/XYIeFSvudQ+BWxBp5ZVdnBYAGzEuTxES5650IFL17dwAGQ+aTywCXI6P adhoH8ADojBD9cN8qOaBoLI+xOhY7BFeCrsdRZELLmDYHNgSBR7P/iMoewh7mHqVkzdXGq0V18PM 8fR2kB8odtL1WYIzgeoJeo4lNfL30glLNQhgEQOa/eaOJnS8cZHacut338uG6+8Fs2FEjy+aFHJY ETIWZn+hnhvFaZLhTyqQM9URooPYhJ5Czpj/l2RvPed63LMNULVRalShMU9+jNbPxeYxYOTzQ/rB f9krblIuZE3TZYYPNhwldp4cj0ggSkjdf28lF3219361YkXf9J7ghLDCxBk/WzcTJlWHmRhp/np8 mWRyZsmsKoBzBdCamBk0p4QkIpJJRvIZpc5+Sso/OffOtwyXjjtr4hYCsIXWPRAz8EjxUTshP2QR aSoKIchtBRHpA02q1SEmWRSs7OMDm8uXxgN/VaXhaPa6wCqbKDL0fk8tZaP3xxSWKU4vuqLutX9h Dnm8xXrdk/o3Kvy61T8s3WFtVYxP0Q/o0vvlZ1Hnrobw7HxUxuneE/bN1QDXzGVTu0UrlGYd7Bpx qtkkAr//N5c4wlMGrzT8HYPzYKLG6fpv3sVxoRPZNmD3Bxc8I0+/f4F+Q87NIisF/zU0qALx957A LufULMilHM1kCVN4BY7Q+LB3Pdn3M/bZb+n3vzJ5dqI8PXZs1sm2Ryfm672gKiOKHTghStPmrMzY 5MLrmhRn7QFHYv6u1aQ/9ETQDgaLrF7RGwoyVk4x1cdlw+VvPLV7BXjUjPsI4e594MK22t2/QiVF tspBL8yFduk1taZhJ7PDwB+bm7xTWUWC417C50aOqQ5H5A/F2m7faSP7g8kRlqytknbkL5pRol06 MeBV1jyUz6DuDyf2plkgn/DDOIxUdOIw4/YyJv1VZ2emWnkTKlEh5lCkVXy9H5mYTKWilBQ9zBAo lUsNnDI8aD4S3z36IW7T5AuD+NQiPyg78T1QiwpUuq9hr/2ocrU4vhexSz+cP6diumwEQnzs97R5 p379+2H71G5pQQEM+KJiB3nvMG+d7EqTDH6U+iLtCpvbqYCscGkAvGQ2D/uwrK1I0xFQ/5HM7QPS zUTJibf5t/XIH4mvjKmGobAbqZkRmPxfCdTk76wwpy8tFca2/5yLehDfE773G1apqZXK6DuDySNo 4RzwtVJLKjuVl+wBts4y3dqY647qoKr1lWi0Nyl1KIH/Cn3Efv5/L1XjjGj0L9UxsXpxNcQbrZoS tbnc6s3M9h1YhYkLknJggmZ8y7elf5iKpzrBvqdeltXAZ5SD3xr21im5/RCxsOe+JA9ORkzw2C70 eAsPcBt5A0WqXqSQ2xbvPOXHrzgjrLlU+TXmAoCFM1i1El0Y4ylbdaLusiLdAM4uwsPuc5UCxoy0 ljVYY/RFA7wMbK/JaiKALb8gUpdmGTs1wfJgxKIwAM8yZNS1klu5fJ1HY7JFsqF62DJcivymTMnM nf3gCJ5vfg+LoAStQKYKCgP4Xv/jkPavOJ/SL/cEclAum2Ykz/HmFCBIC+bd8u7yT7W5SePoxJEw KEgCpNPn27kQTJyDgYWF4hHNLKf2E7L7AR5IHw2c49E00gwuW1WuISObl0c5aZgltrb60GsYxvEC knKA1oD8BAUfNFMGNa66ej7jRlrbbzMY2L9hdHMEA+p3VLEx8Au9b3I19PjOUzPa1FEeFY7b3tp4 wgDW8yOEqcLW1nmz/8mDKQUtm9MM9fAVi5DsVNfKoRhf6uL+5qK+u0/2mHJu6HMSoSBzfpWpZVNB i+otpbVNBOrkX3nKfwMPhmFjfkJ0nQ81rcFeO2QUUC8LGKal/1Wsyw9eIVanJt8d4u3rweSnd8/b eB4KYEaa6pIruitbg7RmnZOS8CSb79Ut8NMGoiOl7LT3kQnO7/4fgg5VNeVCHobiXVCEiXEQWrSb XfImRKyx8+zu5otLSggxzNiym9h2v8E9ivBQsbWTooJjX7+2poHqVzyVTn4HwbKcAksTBwWPcpJz GYEH1RIvBJZ+iqX4Z+9GsxKOs/J/FZMwFcaNZM/BvHGNfgQzN8grdFihcBaiiTZFf3CvN935mvSd wwOsoLgCFZsL75LDt1vmXHytDMPpPTQ0cDv2U6baB74MBU1aFp4auUJ1gg9INJZswLRqEPxjhxT7 pvqyXzxEugYYb08I9PIKRTa9WsC1ZU50HEcNzYH7YB5dMbYTVVlQlIi9R9AnN697NzQLc4nOImjK mUezr2B3YOd3qvT8SpVISiZb5PTFIrqUi/SCsQNuQwWZZa/TD8BjsLRxARC4twUHG1XrBIVR2gpW 8pFuVJZ4+5XJZcZqu7np+fxFzGx279Re+CRJ6OzDed6LvKJoz3QHpJsarYpUJN/ZREIuyLDpPsDO ju/nMmkkhGuBK2E/pLNJTnSrNIirAlWWU3pEyOTM+kv/3uR3mqrAPPXMkHHaWe33GKulRioUI+jW syslOFL77lyYEc8gULqjJkGD1kdEs+aXCjG/1D5RrxMQ+sRWLnyxWYKuCQdk/3emZ19XI0KDph/7 p23cMw1QHvd7vJYhcF041ZaoDhoeEaIJ8XmYgmNI9PUc2U3EiwV31U/uBwDCpoYGXGyojA19pwt8 ZNHUMPmI9pSVYYY2NvpsBuX6+koHR4SYS1YiXSGo/CLHKYWoKE/swVSeR9R2J3X5tDHa9e464wgT aUd8ArB5HWs6Mxgmi+eglAVeIwYmMODHD/0ERj9LHA5AOBeeenieACCywwu3YaHgqUVLirc0b3od QbpSiZdV72iCzUxKiJF/nnCPPeL4WmZ9dggPJuWSa4UiiRAkc22NHu9ZbuATZDJJK1xY/KLM44c0 19d8aqVLkyYr8XJ0VxCpfQtoEgyGL9BNW+E7Y6rJbzOSC2RPNW80IrIfSQ1Jxahd8mQDBGIjgz2B LSa/iitquayrmOMwY1NnmVve3zzW1f3WtuIWJFYIhGGnx345jyarn1vOS3Xj9p674sTITMaZiVpR 7pI3JJ9U/MWkbAjTv455xlDdsFMXDfNVs9VkRAwqaNx6KtT/VNytZqyUCaFRSDWsitwmQdr0kSif IbwcRmuAxF1cLZgKgAg7qBKCva29KuARigz5TcIv9TDuwnFZxgC9u65AxFtNVH3RkBvD0rPD77pf maxYisgU3WJOvCoYRg3xJ0BZ4nTGlrAS2gqqMLqWEKTNpaF3EHZHGOkADS0DXhXHqOOjz3S98dAo 6Dm9WcOvhv7d6l7JsqujYrVevdWtzFbSuJAYSaQIla/pOWRqAsr5Z+CutTwQX88MWNgT11jrOMkM sI1ZpRGpTtisritvFIxnR/2l+sZwlW94qoj4pgIfvW6DLQ4xMKU3TSvp9OWCrYu+YLULCZbDIwVE xIaI5OEcOAJG7r0SZtE6X12Yt74R+4hQcE1VJjRbrcQrs3v5gJ63KrDQnXGr0U/9fpm9mwxBzn9y 4U6iGmw68kCfqv94cG110M7TYvBVexdMiRYH3gE12bLE6aS6BWXq0uS/ThsucyScEGTXRQQicIAK 7IDvIbuQ69ErdJ8+JTZe8hKbfGACRHuuogoL8yxY8Qmmn3p8zSs/QxPfARNH6NRwP6xd5QTWRSU1 /6F2t+CPp6Jdge12ieWnJrYdQRPsieOL5QtMOsLTltHt/AUwRxdsG0NTvdY6sH4daZ1JrbPWQZ1e ba8fjhsgT2uMXjiai6sM9zvbXhYvc+ekq/6EnzOJ4SYZj139ygCvK+FsLxvihrWe9wp+rhUlNkai ZhAQ7AhJ0He2berfZrFTPCBWNpH6ey30tkTo6FzsvvCdXnqiBcUTaPc4dKyVr+WJ7S1ApSz6GKH9 MCgyAnSGAXw/J7dbl769zy+AUeTk5bjK54sD46dXM/2tRMT2UtLdA2KPHrkjq9lBh+39412Q+pyQ mOZrpp161lq7/lVVz0nsyAl48sif1RhhAV26x9/I5vIfQ2oF+WDuBIZoggVUF2cQ5NrdW47tTzD2 0cncagjmIgdzMTSGXsgnZRW8+NV0dN4wC7PWxgySUYaIEwmWJXDa+cbnfe1vUN4XMrDHvPY2Q94g ymEPVfCj1DPMhxsdKJteB4IvgCisPRUBAlOG5rZvhN9sV8AkokorL+2bsyq1RvyDMVAG52zGuYgs Yk0LeDPZt26Qp/lKQlwyd7S6k/Z6l2kGfkqBAyPUSNaDdyVUUJZuRk1B0XW4FsxAMfB9SJThPrq5 bguvqBKfceLelr+Dz/qlXIam1Z0ZeGXoh/grHfJy8Z3Grh46CXKlYFAECzSn3qBmFfgNDP7IHx+X DlAj29MklmzDJt49muk8qRTiRDBsQ6Ncre/EpqW+mgLvGWwyQS9uvaAkOSHewnijoVwQPhJUzG8g lrryRx8V+m6sBE0N7OEiUT2FJofYL62FpV5M8RAAUzbQ1Axnz+qoy9sKUQly2sbPrdb9Cdn7KAek p4De0gHdIeI1gfOcYC9m3IrJ+zOaarxywNN9nMptAgCmzM2MwVO+Jw+Tdd1OR/vbcIICIhIo2doV vwN4s+HbR7n68+v/jkG+JEBoxvpPiW6uDtd2pDR5tsJqwHrQWsZ6pvJZDSUwkj4XSrCZBhhwwurz O9A2K0VNCFfR/2YAP0GcnqKD7G0zqqfeexODeCifmWoKvryXu+BcBGnuRIpefnlhT+in8FVF1YN9 ZOYJY89AuhdE8DW3mtEFyPpyEdghzBmt0LhR5lUHj9JrY05fyD8TCV70Wg+u7W2Fe0dKLUV7Ki/+ kvPPb7V6EjWAFIk+MGOAv4o9A7SzzhWs8beqhYfAObTEmDEZqa1gKUGcPnJJo+y4qPYJplmqAbLQ 7+uxBNRjqoYYCYPhq6bdiKY+lqMWnOr8cCgdplkYZKxrbIyCFO3/8X0b4CzoumCs2fO5EsIceGQE ImryN3EjWshlFGDnocxKObgxpsKRPoGDPVJoIhfS+8u0bA3AC4TauUsKJypkyohhsEEU+Fcir/yM uamx3cY/LwNyOE1JqZg0fz5ZeyAxLADrLGeUtKS1IjzWTiNBXWeNeOx48kk2L8jThLBNqP+UlZYk J6MoCz3puRlkf6pC/v1dnvJvcLK0jeR2dt9EHdz+joD7/VoGXA8CW0WjRuE9JypFb97D17ZZi9iI 4z12ubW2sLjwei6XIetG/cGRoRCmGjp0KA16L8XrrlZclGYtIE65YHw15YVdwFZWLbMTKErOXkQa MyQbduPRSja1RMfVtN9tIg4HMXMcUZTC6+z7lKRjx922S7B0fHkAszrLZdVmhCKO8WzvTOXRG7an QbWoRzU0hVZqj3xVe2VPBePUFEfD2nHTBNUHjl68osL5YlQpgShYk/1eojJkxtYZuOMVAiDgYfdM l+LAphuHNK1EQjchqQRaZdV4m4M/DVakoH8f3JOi8lY6HQDeB3VPC6OMeGYTyNx/9JpvxNiY6Gd2 ck9XazVm5BRSauFViMRvGT2uy627TiKMM/JMtTKCPUkraQM9ZoNNePAVW41eze52GvjONGrXFkrk akjotj7v3x7qG3kUQc9Rd1S8qdq1T3Pbz4V9X/lEm6i1el/NrTcVrVQWr3RCxXIGzG1brM7BH8qp tpO4C7xfstbzSvgxVWtxSLFp9iP1QV1BP9uJ5KZ4yxtH/F8J28r5kDGgxwszNvtH4+FfS13SBKuA Uv64P3f10hddaZJIMf33Og2tBH8QE06xOhFKOZEaig0wnI8f4UieZKZRUqmQtNEuAiGo5kVQKBSB awFbyHqyje58KFujQxFYYOmv+5y/RcifbaDMo0rbI4cl5WYg8QQ6+mbSFfJRU/yVBjEgy4FZlRm4 0hLIJvDwRn76XySt6LRXBeDb0tCmPPZEkCSe7AnVsbG4R/UbFt2DKjKbl4URmSvqzQYeI1/fw9Yr xRpSdi8P8CQWgbKCt45eINwGzab4sr7cSOnhHVHwMdGARVF+FSmX089gP+U+cmQK+8bWgjeucltf 89ZwZNXNSru6dM1S/KwBkBh+04Vmyln5SF/DDM3PuSXhYBl5FPRv+BxEs0AnP2+dC3Z60ytddep1 iJFCERgqzsTG/73OBNeGZi2D+hJ+Hn70qKtnJy3jtNuq7jPGgWM0ifgj4DVL78hzOb3eUPQy1M1W vRUQruEyOmZf3FAwNpQJnKEm2Xf3BeW6ajE5VkIq0M9VDFEgtjC2wuRg7v9vc81EIIuIhQYtktCY 19Cn6E52ToW/pmHsGujHwgzVpaQsTvWiQlo9xdW/IBdKW5LlJE7KdxsCxZV46+TGokXVVuByXnab ky7XEeBEkFwtLPxHkEcVoE0u5oAbH7StocuhSuj/45c8+lppu2csOBRjeRhNU+WP4Ca4nmWPUCTj qQZYcYC+sXEsy5E7qFy9GvPqGtXAUx8fVsG0OCWEj+qERsXfS5gMM3HK16R6eQtKuOCeV09A3EkW +vM9y+eNQL8dG3Fi4SuKjdD5ZyiaZT7yRw75YSy7euLpbBu9JuVj53tl/wXNVLs3r7B5w2+8KPSy mWyVOI4FLGN9wWyy7E9bwaBw1VRmXECID8mllSc+e1W9DT4OYJE3gkfjPHeAe/eh3kb/tvb8m6zQ QDQPrN1yHJP4CoPX+dwr7Ott2AerFjgPgMCmPgXeXe4B3d3VNctfvYVPcChKZi3OgkIWJdLjiNNm h3TzngBkmOGbPwv100TVzJcl7gzVHi1B6DbV43IwICvL4Bv5ljKfTHch+57iXykuz9HNTUcpJEg9 l1gajgzcSNwU3jnROTUuD8KSfwUHMwQoglnunc9GQIDqQtxCqzLvGPuQf/WeHxgUHFY0OGw+/SYo FaFBA6vX3d0T/T0GvV3GCNWQQ0/1IZ62AWedi/l8CR/IG4ymQ4q9iMQ1kWh46NY8ujo+4c3vGG9Y rWj17IrnVuEdMvpfKBpvifAYOxTk4f90xGVgl0srnhWjFhWJCKODlxaFdvm+gSnpJAoecINNyM6X h4xtsNbzGa77eDLiWc+r2GcafI/l+F9aTTn40OdNJl8u7lz7MG6Hj4TBgAWGXyrboeMP+Hmonwyb wWMVRuqC2Fj/X95901o7T73hJJAOlUSWuor9ilpcIpy/bzR7Tf2KCnm/JS5X3Thd5m/KgcIzzxiP 3/gb9OHU2y0SlrGcqSDBkGTQvqVjEtav7WL0noGT3C54XiKGlIbbytZoKNLe5fbJY260WBI9EjJ+ AEkGnSzYXcsjjRv0TdedQUOCrhqFMtS4wXPQFx6M/VmBiMrsF2Uaa7nqfxaRRsyVj5ih7zAutcYc ehrvYTJous7+AxAotI97YRYRcoweGIwywE3seKuOia1iroengMLFyb9kYZOQkMQG3/QPL+qijt7b ipOPv2KK+aIn6XRCdgHmXOXTuP9uhPiAmYpLSyqsQsmnl5+kWGPgsig/lWB46DiJHyGlJ0/BdCwy +Pm6mwINdDIPWqAu763b2qhTbnYdu8UYW+5m4lSWf8l+iZbZidb5XeSPg3k7IqNDKJpH8/XacAgw G0yC6xiJe7IaoqahzZzsWswmrjLoTIhM9LbKFtQaza1Ntd8+BiAVuoYAbWbM/AnWLUXz6rqudqzq 03pICqagICTZS/0R1Z35Qpyl45SJUOh1SS6WizvdBWnTpvNUzeJt5vtCgiPxuevJNkcS3f1//UOU PKpOowqBZH6c/vjg9u2G+0lVQc6wwDGlI62yBdejy0uIDOr72Y7e56xe+IloQAMckshvrrtEOmA6 0mKiCNdRVsoOMKH4VB8iO/0ZRtU4x/cvp5r3FYviaG5/t76Silqzz17b8u3HHVXXrTQnnaCXmQGc qydebcQ2IcCuFInPWJmDKCVHYY2hpXgYohE6x6uN30Aoz4j+3sEpOlxq3T7OitRYUHi/KOXQQ+NN t6Nl3/E8t+YhU921JnOWSvOFPd+LfwOBXFcqQSTfEe2rO554H9m19jMUpBGrVuXH7vePL9ibIYQy Gy39BB05M9RCvhM1L37KTtkRfZv/M3DJ7VgyHAYW6TEFjtYA4Feut0m9fJgbyf2BhFhB/7Rs8cxB TgjXxacFR2xRLP1T6uFkGbvCZDfllnhqqIhy9dp1gNz0XKOBwv/rQhrSfP4p1wfvapouBg01O71h W/oCXDGmVKVFcnCxlWOdT4z03K8L8TKqnGZ2gDc2UDxfXbIFhNLM1+EUjedcf/wfyg+Iaoup9iUV Pb8f1C31P2+d8IOmtDFW/aKLcT63oF8xgMIQ5kDNDf1cXhOAsKqahR0JGmmjinJDgQZUh/8xJSMz 8ncCzHJmJAvJR2SQc5Smowi1caGTYSrDqIPmMHWMCUSSOkhDKFhMdxz0YEsC0qleBQtyICVWm2IM xDa6DZvDZQ4GBGuPNtBFXdTiFVKJrhpnf0heLBsAxkBuUbF0BhZLm/asrAX/emp9eFl5U/pliQQ/ be748yAL7TtinA5NoEY2gCsCPw/vpr6D1Tl8BTnUktJQfsJSseuH2gcvM+6d78Cfji/+meOLHL7m NQO+fBrdlvmZi/Jzt+whMwM5ZhxDGgPbllaNrEg9siYK3NZCZ9IeadHUg6USFU9oyWwHrLxrDpvO ufoh9QA94CDxoDpN9AOCBCRdbxHYvOkwIACNupqKuE7IPIM5hP1WLT2hUQIigveMYruSXIbz5cc2 lwbv5pguB9eznThFkBfoYWfpWHS6PDtf/yRqD/YsSikxSvm48M/IH1t36foasHtH8Av5maQeAWdv WUPt8J5EpE1vq7b9/mfXiX3kFPrse31lSKOQwkxg6YdajXLYjbxokNf/JBgUfbwoS4E4oDhrocTV SZ2BSCiYqtq9sr0eEQs4zvY5w1UR0zCp0fw6EMA/Gi+GkXyR72BjD/h9pcvElZg4VpebVZSDeDLF 0/sEiYko/lLI2J+82jyIwfdIy0wkwHUe0gsdrzlKf0Yz2NrtCMZkjjv5llJFgagcfSS5lD1mNxtS W4KY1qkjf8BdFe4q98WFg7sbnpybNL7bTeUlFgGRZFfFKRFYOfAKqFXvv51laNJlqC1hzuLDKVl6 ZPj9EuTAvaMmRNryR6bKHC4A6GtztdvgCvK88XEiI6irfRhG07wqakIehn5Nk92iRR0e0UdMYPWR qae9UPpViTtCyo6GYP902hPo7yvozwxtoKZvvRwNYP6fviOWHfyFvu61GJ1prsU/rmo2RAbNVWhi yrJxtbJZuHcRV3Z7Roj9AjFWPD/CcDIo7nKmxOEJStSBXtEvAJEgGnCVzEYFNX/+PkAHxON9hdxr smrCMa5VP+Kp7IraLz15Bl2lb29wYUo/9loS++BWMm5Z0d5kdzv4r3AOrhy7LZ26QhncntOL5kd1 CiwdMbsNkfnrwscqHi8g5s4ojWWTpskA/T4ekWj5TthdnbWy0t8KbaoWvgWBwqZr5o6v4HnPrW/J uoXEvNZ473ASwOPEqRNqQ+SlLeVEm/aSiyi4z4xhn1CNhCik9zc/XzJfs2pb53SkondFMWGpsR4m 84GgGc5wIFoVUjcwUDclfL2xByM6MXMwKR4z1sG+dnlMZYUGB+lkwupDW5xNqdlUEoxVcajmYlDv mrVtaeXhNAin0u6pOCPT5ofhFbyQVB9mAaAR7f/ZGIdWt43x7Pc27aX6Aa6P8c8V6lb3QJ396VNN 1u9HiN/ywU2SU2yV+7J19l2M3FW9B48g1bJgGLI6EsNXf6sLQWs94L+nZZ2yAu9f4M6MzPEF6+E+ DI9skMZfnbgz+1f0//1Bji4bVZtJWRX6Tpo7h9qFiYi3h1VMyNk3uKqGvyMvjzeW/vhVbre72xv/ umJrFxV5pAeQ5IXoLdWPl1MpvbO6+7B0aPFD3Yi8KlS+nWW/PW6RMY1IaMdhBU0g6FcpHiTEqwQH icS3CuqvOerSkdniXboBC8llqmQlpgymLB99445lQ7LXy+6T+rxqzGG76DjV8j72+Fv+lRReSUwy n9TX9mxrXyv0+T6eH4D3JIfKD83g2By1qAJIGo2+Z2ZlRVGBJic3HVwMbGq52wFIMM5i2UIzHgoN Ei/VHQFLKiTGBBhEyayJwDFeu9WezVibxW0gNZXOAYVbDgltbKjwbYmclogxPm6yJAk3wj4vjwfY aUwEx3S8sP0yySxtLwVrawhVkDi3nEB8gy8h6hRwts2W9+X9jImXQcp1kkcouPf4J2S8M8oJ31sg Ob+he6XOCj8bQYsvR9FLmhgLQGyIOFZdsyru1T6wMqF+Y0G0JfSzpFuipfRwBP8/oAbCiq8sC6T7 U9VsHFxHXh4c8+Ozd65JWq2h6IdMizWSc3S4Zh8tyqiDgoRq1y9feRb0Im15shQs8WhGdmHwWx6U UngO4UBkHYB6mYV/RAd7uI3/Ia78hxj5wqXMNW9rsOBisp19fk1YGuxLl9WRidJp5xs1bqv2+5ME COvyBScinwQ5sYOG3HsUCp8xvI7IxO7YoUYnn4xNng47eL5x07DfCvN8RgiXwede068/tBXvAMbu S+gTG5EJJnQ3/hu5NIokqwKcd41Nq+U+uEglWS/AJQ+S0TYofj9tDxZAcK/r2WZNAUVr5+6aXFz2 J/E221v964+iz1qcx/t57YTdYnxWLJeekToI/IZ7jinteFjAxadwilw2RZF/y6ZrzI9ujuOU3waA 5/ix7IfcC9rn+jtpfEw71qXrjzJvHsuAtQTAxMoAUQty5e5shU0hmRoOEYdLN9OWZmlAbh7wO3k4 FhBc6ZJiYiWjq0f1orgWRt+ilNyb/Fy4+uXe6XrvySx3mJJ5Wy8NJxgmKP/XWXAgsJfJUVYch6rD zBrxtANsDssp2lA8IrvzCvmty3iQz3Hv3xClBdW5hJHj2hWY50gaCzIgspntTRVRO3NEtA7+7nHN bJepMGUoRXoFq0/Cx/csKzXgIf/hddibsT3c9p3j8txs5i2y7PI9xllpXocnmVHYaSqeHJimEmeh U+vYrW3UYGuEXYkhU3AhJ/vE/ouboLHOhPWW0pI3x47r+kqMbg99VEDpUg9+jk9La4Pwa8wtDH9d Bt76gHiOxJgqHINu+91wqcahDkCALo4u89VudqE+8ddPLCUK8j+pqFlpHWskAiLY0vVPaJfaXWsh JPysgyqXWcnCNA5dosPnZWKvAeUPuFxehPN9oZZGAlLVJHuAk/Y53n3OC5451k+zsqUjN6Izn11a RRNDq17VRuWMDul8yh8ysoXtJGcNwStKmKnxki/dB+dsroBnIW1pST9UpqR97RKhbQi9EAcC7J+v hKS1+GPPVpYP21G0BWEPLSgFNNcDOPw0t6fvu6/2hwuVe3RVWFYARNR5p0voiVXFGs2HBrm0Pu4d ZSAu8wORtialobZun3MY9oWE94t2yCPRLCBQnjlDdms60alo1JYYB8RH4Aqleb/hl2B9mHf89mUC ovHA0m4SgMgLBTtQfpUun/Wg1pk19oL3wBptABgQTXJXkhxNS54RLxb78KleuLZzJhqWfPt0liDk nkwYzY61VXCWUtVTxmJT8Kyp6IANR5eOC3m6NKL6bioU+kFK/wss/jV42kdthYzrPUGnoSPhR64+ 1aldq+HCfJReK0kqHDqodXrdEFPnRuwUsIRcWOP9dhnitn/gYbZedWoU/1Vv6sp9/DiABPaZWs4R i7AmD9XTedIUW0y5Dqtwe4HQ2eoqtiD5uOiSd6iuJtMtBHE1JRY8RhkHiCj++zPGpKPh2Ftb6dKS 1PSvqnMLq04cqsTTdd7ABbhYbQOi72uwaIUtXinVfCdDnD5HBvK4FMiczAoYM8KZYTk4uk4EnFC6 4b0fG2n35x+9Gz+vWKXSvmVNaPpsJA3AlK39bDUxItaRNuHvKnUv9GjjHJyO09N+wcgK7dTDEjur rE1+Prw+oUaJUgYsKnOCdIVrm9WEZiIy+oQzj33r7FUb5yFpedWvFD/iWiQ6fMouJMa43JqR+8zd /7i/q8wR4rsi4qjQvkYOMX/o0HAx4VNboooRxzf9ACcjbgtOFzd7Fl/kMhprIS91hAAm0QakOo+k jBLNVN4NZeOw0iOVUl4iOj7422aigqUk0UeK03BwrV9+9Jg5twRVJW3zj6XaVX0TA2ZtvE7FRKI7 hLzBohap7EbqZCFcJa3HrMynH16mj/E7nsbwyLlapwM85rq84bjHkKOKaEL1b7j/s6jUEiduZgEU kLUwjrc+NcqETsCAk86V2QlJzO3b1OJK3XvVeonOiiAGKnCKFmOzuwLJxsAoqAQIGuodd9vtppdn NS/BsZCuPrqAchkCRGQ8wHDvYqBrT66TSAEktDN47QaH+WC3gCK4hlnC7uRZP0SgweiXhjkhbk4s J+cYRr4ChIWpc9iofjskI+y+dTmjKnKp4Ttdcdk/vgwafgBqWXjOb0TuU77P5kOAjs4kAJJqeRjw MsSHX8n3B03k/i3vI7oZZAg54dHJZNr5ObZswhL66ATMJSTod3l6dULK9rGp+PDRDXjrxzVqQutP +aCalU9rG9/fwtV+jqK/eaRQtzWTCZtW8zxbhjzC6xwyaoXz9T41gf+iG/Z49yRm/ZxrhyIC/pK5 HtFmYzX4KsPKhQs/1LKJQp7TJf2GXzJxbtKknSEe4clk+M33q2zSRVT8vN5qHMcVENgQenKW9hHK dba7l+SrAbIL3r2i/OPRZCCYe9M+kTZvHu2CTGNymu/Mm0ocwbE0kFt8Gr5ZZnPgjur3iLxe/rpx SZaolNHKGDo09pFuxER0a9s0Ey/dqzV9ShJuDKzxtT38q0Um+KwK2zqEidJSGu3FiIoYD8uh11Xp vn7/MwrGepHge9vM2fwIxke00DL1sZuHWJ9L93z/sSuDbotkRHL13ep7D6qGbxdCMYOrB0vXh5YI 2KGzRzIPVJErb2gF7jmO42Y8AtsNiB86lUmTEH6uBMrCQlKRrUeBkgJMc70qWmZFUus6bXJYuO2V M90Li8UCkinY6O9O9hrSGPziTPy6hksfNIp+L70MwaWiQxZql0uKjEW/bkeCpsoZFCa0efuOZO1/ Tf5+ykHiKHxyuvM0z2A0+sJpzdiUk92VEmo+0V/QL6XfPcNUxJItK5iooHx0WsSwRyjCYqccjhWo 7FWmQ2+UBQG++x8Sz9yrNOHZLWfAX09pVwfyhnF/OEgvUUe7wASxJI0DjYTbtMgixglat49aiCxp 5WiF4J2plpe96n8id01/o4+o3MweVdgzSbKnqt1aWO7yD0ZHfSmsEtiQoBoPnFNL/pOJ4oAYCObf u63eMZ8zkoikYbSI7R/5iy/Y38uHSYvjHUwCDeZh6Thq3HCafz6fOxF9HXYg/9MBTbp90JAviNIy QLnnPOgi5aCaMUbwDWjXMhkiN0FTklVjvT/2ILkavaR7nmeEyR5gbuxsk0MF0BPfessdk6WiExHY SZNR4nQWFNxvXuHWFmKuP0HYVm87WoAcnyURd00oSrJH550NZnv6be6Z/8ZzkI2fJoym9XKNcl8w JTN0Tf4m1+afImS/biLsqn6ZGlSGdcU1acQ6A6h36jmesM8Z8HFDJ1V3Pge8hz/+WKkLaW+2UEhM kNjGblptVGd/Qr8FU2EuHTqV5rm3GakYe3iZSbZRp2Ukc2hmsVOoB7yW64dT34KtR1NyxcAm88cx 54hnZ4BP9jTo5zrrLXsWKeEIA3YGFp2d4dy/PGX3G/IMJgNypWL/1qDFoCk1Gno0nhFFlVISn7pc OhkCWlBxOFyj7l/crIfJBmr0UnxP1HsXbfmk8WPbYvgiHNOTjvS1Sydkdt2oaqWwr943rkopufn5 5LR/bn9noscx5eDXLkPalAjEY1a3Rgxh/oG8aONhi4ILldP4SC/trUDNh+BrFpBOpAc9F8knNZ15 pE9+vsauP801fz9anjnnMy/ailfhtSO8dwUA22dbULLga20HIBY66l9Q4+LhZK0BSwyXCeCH1QM0 WD8Xv3SHvSW9PZuHvVFMxvtW1sqR208UcGbJ+EBtPP+sljvAEAlj9PxciO+a1hTTQbczyZFQePRL AlT+y5Iic5FZ25dvi/T7iwYTSoDXQP8LZzxquum7yzE/XxeyHXzzrqNlvC8aSqC4V9wki94+3dyp SNv8HdNiIsNtaKRzVVZvMgeuLNkj2IDuTMxZ1ndpit2SANlNRRvuEzRVLWdcpbYXEVKl8LlANMkv KUB13U+mUEPciyFG72DMDEVNpXwLY+AZNmmmKS0hCujH0lb8SjYNy6b79aVmXTY1D7YS48QJiz0B FOr5XjzWUQT4ADBLeM6KvW3VKPDynh+V5xyPbQ7bGSpPndkj0801bfTb7zTd2XZsmq63jTZhr3zV aSPYsnHE0KVofOX4haAaAyA3gSdaYk0kjO7zZc3E9PyHzfGS+ewhRrUh7+sentiuDB9h0gP2dCMr gsTfpK9rVGMIsTsVlAiS/8OK77JfINdt7/l19yinmEVxONDpOVfHi0zBjaf6VbiS/tDh0F2EizNc TryoJpofOOQIBhndUchFK4YRp1W9jU7ux3UlUnMBGaYhEOwOvzLXS4/o2QP/nNUuBwntYLYrY8sg 0fqMlbaivsPLkskyGQab0xsVMVtayALuTrCOO06CpKzioAUPc/UsFHcRzDN17HQ3j6Pb6k1tEIuv jhA5ExHgz0jk1tE58qzhn2WwUUzcmxLL/j61nKdXTt5keTfcps+Nfg5XkVyu0h7uQ8TE5aOMMQVi ZREwi+S1/b9K3vBqk7iMaSVBdYwzo1FgpRXpqxgywq1XDhbpzHl3FcxIahnZPcue9uTYssm/Y8W2 6yMPnrOSdA2AiVkfnGTivAsPbd6PbnCAll/lNP7vpZiMsEfTFR0ee+GppwhmtAVSjOY8oS9aO2xP 8IeubCAsMOtzgn5HeMoUi2jjY7211I+ocZxFQET0YLGtuqFPOtNJr7kZdlPGxL8CwzK8N87gf54C 11wra4TUqGJyg0Y+V7ju8t4Z0gaKkopOncDZgBrUasti1q/xGxoIRwpEdbwyAYv1FfSvjokT+kQf ToA+XU4I5Rlpz79RVX8iv3OkDfAcwBnxB8e1v228VT4AmuK9oqomllObsNzPJVGOexEFKMAjowk4 ITGY/PyzrVEtkKmyppLmdYzs0ITjbKhRgV7U66eOL/4AdwkqHrxQzZaia04Zy7EAojs9jfLmUbtE 5gIdSDXUon5idj0jtw6NFs2uiBV2+VXVgWp5vB9qYngt4/uv4nI8zSXPb3LKSEplQ2d7vEj8PZO9 JAY2/G66HByS8FwPVujFpYFqGNS5dEB8uOP7ms3CfcHKnJR3/2oKujsiPV4+XIed9XZN28aASgE6 7fyisT/3GDtXdJKnWnlLJEawUeoEoukwjPh/DQbUl+Z0M1chMw24wTZq5lz2tPZDRWlM8xHL6raQ TtsT/uVlXrqPbsfloPiuqvp3e40YL55A5UB5XE2mGf/SBFk4uqWsqq46BFo2P3WC7U112cSyUrFR TZuV67kuH8dL/0dTBQjnOHmX7yC2ty5nnjs1xcZ92u60UHn6I3HDNY6sgQxQpTrR+ISJONcuxsMu 6/xQqroaaOc0ZOx+55iJPUfw18QgdU25ay/vdSuH90hFgjqEQyuUsBTFkJImAb+MUZ8oxNnWGp8O 1ViKxkHag1FJgKUwfKJEyduSwyYez/aWQ36NVYywkQHTXTRDR0L7N3rn57nzaeqmsst/Noev/se7 2TTVQ4MJV3cAgAWT5Dq7Zumnf0m9k3Jk8MW0w/o+s3mbKlYLhrEbOHBxH2ozh54JHuEEFwHo0HEg Tycr+G1RlUlzFvNfLVs2pUe7NMKQQkKnCevDjdIAsi0ffRtWR0jYIZW9H+wAO1XRl+P90NGChKdH Bl3b9+gmvgREe+pqyakstahfkONGxGxNRIxOV0BXyRt3Izmw+zup5Lu0+hc3YwjQQKg1wykjqiLu 4pNcO7rs52jmQleIA7G//vFTKYxpVk/bJMWixmsnDGuRYDCVgfJFanvLAgHTNUSe1fuuIsot+3Lg V+qALuYrh5Jgz/8C1RCjbKSR2FZWB9S18syGFareYAL6dDOM+fr08lWsi00xxg9r522/EBpY3Yue vU/52s6GHe4vbbpmSh32FNZL5G8MlOWt61VWdcG0vjAplbsh6HvnFeEF45nwgnzHQUkXOxO74jbb mYkX4EI71u0/1UF+5UTwCCmvhdSO63dFPW5YtU2WvxY5cmBFsyoJ6mZ/iqaObMJvyuixnaIx6gFf aeSkD1cNImwVEVfWWi+ubzNscfLjo2/99x5IrRLCwXNP/ExoS9qWEZrJkExq4qJPMGoJVtPXFj7V Bqq7bufAWu98R2TOGw9vDu6NqKultKWjKY27t+gZ3tijKgwLsJzYhJrItBG1qrQ4TSzzHMXZKIlr 0NVKSD1WDGWgMt2kFmDmRT72j1GAdZ1frH9s+4dfNV4Kf3IoCFyrRJnE0GEzw/ykmEFu7/o/7KYS uWaSmb/qQ0zvOdV8b9+I0MiYXkOkrm2ZxieF3PTvo0GmjRYVUV847NSX2sC1LSjRDlH8nhf+kIWH RWKY4oxb6KXmNJpQNRaPdYbvUDuTy9JchpBseSkvPnrh+IOwFT/Zc9MO3WYytpRtc6szXYWkSKiW W9/Kqt6NI6qlVWSyvPQ0AcEGT59azpkixzpk5suHLIxcomxnVpUON3IXSg2diaNh93BJSv+ub8qc RpypAWa1kKqvWLXOt2FnT8gpTMSqxBB4qPF7+QG27Cpb9zM5wrLaBBImdUQ5MuibloXTA/hoLZSN Vp5LeRJSpYUTv9qxjQqcnwVt3PEXyUlAXCgLb+Ti/82GVqFbkVQA+d8KUtLcD7mNQC5+Z8VbgnI1 OQsIiUDDe/DMJ7JJ8NnRT964TLnteBQyiYwU0phA5fZNDfKJsEYQN7ZkmEcZOr9BE6SpJwVXqoZS PMXFUn6lMFQYRUwA5vXTrRZBPjIebW0vxA+orK3q/yFYDvGnYpV0a2edNiV3QLFUc2nTO2/IpZxB rH7FjB+uOTCWmFhCE4rqakY4ZSPIkEIKRMNkY+1DtbrK09vkS/FLUuoEC3IK6OytJVuzvWOqHxeW 8efbN03HEQuuFkh8yZE6Iot53inpEX5ONwi9mL8zd18IDU8Nb2FHJaRgfv6OMoxEP4drU1esT9Xz /+ozcTxEB7W//lx4W5QgxVsNWv0woSZY3mpgvVpDjMUS3tq8yeRDmyG6Gxi3cQwzumGs/p7NeZRb 3RLDw1d0vWawYakltUa3tcQSlk8xs/6zVr9luaLtrBwe6k7gKQLrs5dpPHVZBAL8rtJOw4c5NO4M eM2WSptEp9vaqhQ5w98+j2bFPUxKyQz2dTn1u6XZWe0Ts09nQKyeQW3ymI1mbaEcwDd8HWucirug As7ZMY2BjsnoGcILZquembUEf6I8z60LMExgpRrHTIA+kMdOjI8+lLim/oa+A2FN5r8KldwCAqhz ATsb5jI3k+/E29BeFfAa/lJ0wZcw716JxuZgLqUFy5Xe3vQUSEj/t/vSjV8DhGkcYVEoi/uBfnhQ eyOiil3arT5B1bx9J4xIyjHNBywD6MiDh+/34Op0mr/J78F3SKEcDdJaCM7w9x98TDKSMBTKHxoX BKCz3z9UN8OXYwciOsvmlEaY5Pg/v2UtLHzP8NHhjKFOqSv8NIfbAySBRzMKA3naBJxhUYwR2Nv/ jS7FOajSP1CcmZuaxigETBEOS34AinoJ9EosbtyDTVj+YqZo/w3v9LU7Jtv4RQLC9HaKk7MCUwVC XuDiEjD2WoUfs0hlOtKfOMTtaEnrc1v4QKSwGsDPbeNRXeDGuUbzvEXUor7Zv5ScfPQJTHI6FdbT r2Njr36r/aBPH9m2cj6/pJTEG8X/J+ALiVoXwLu/VFn/NADKhveLKRdY7rziWvdxTaAyWloQ0lsS JGIkqLOuHRKIH88LNlIgmBFtB7hHeU/PlrIghKLsA5/RK7IoGsarmPmQJTNtzaDDpb1dClIUN3Si IHy4fxqS5ayxXkMo9jg5T3aUb6DqozsZX9PA2nMmgBM+OYnLBh6zi1jctWVyon5cEYesqze1a0vT Az9P/yCslfcU7IeY9wKGM7npwmxDN2EjYQlLAZDKxfXg0OQJs58cpwoMDcDIJwicxtViL0NOFdYU zacnZMtFF6oCFUMNkmYnBjFAe5zoEUKbNBHFqeQmMiF3ySg44YzCY6PdGzBOcfpU7TbXHKIAjjfx 4iGSLtyrK0qsrCeYuiw5qxfzyib0THOpR0JareWvFpNhR02knNi8IxM/M3N9bDsubF4lmnoaz3K7 syNU51C3FB9boPG/S5pvUk9coc18NBQINRDUIhGv66YIy0ADrOChMagkvAwwXGy3ZUbPmIjt6kr2 kD4JBS0cDC3GqoT60emMpdhrFnA4cfjO7zAJtouXKq/fdk6n/b0Snp3n78oyC76p4a6dN7XuaohK otDhcAreQFuGogwzR8MlLaj235eRh1/UxIANiMPk5L5NRV0tZy5i8PYoQnvlDgIh7aOjLj46eGbl 2HDV4c00YfAaxjUHiH43wYlIk2AcD/1Aa1QadopBJu5NEVuzZbTa2wvns9v4afIipf/XCcALOlwz 1p7kvcR/Wj+cgIeZvVHGWo/6bVReYckXotW3WTQd8V8QBMzcn8MtTGIfXIxuSDfaCTLgJ9reoCEV qWNyJwhpptvBTk3pPQewRLsFpzyKsC3Nr4KTXNWqiWiEvHkmALK/Ee62lx9j+rJneTw4kzoF+4+p iBxVNHcs9X/lTL1KC8cNTEJLtoqjSjpvU6HryF1sTYF5O/XR7taqb0x5oPsF/s37hKDhPJsIfPlX Qg1hXpeIQPpOXSTXcZtIJuFlyNt0QXjCOds0SDQeWoJuu/U7zS9iJX+xNz+xhNUF0Y1DgyYejMRN UvNcXSswFEAnYOPP4EVWLT+14hCIm/S+4A1pPCuZAtfLbtyuqNik7ks2Bify49C6dg7ygrF5zbTG LD0lEt6hDiXGVSatg+ZtV516iAFPsMucPtA2c/P69vn00GluiH+WvKD+Lh87ebzLI7E5TFSDDGBx 37nHnJCvOj6zu0og/t+wlAcp4t9udZnXnriEzXWcvAM6av5TKKdZhvmYdDmQYmp1Z8erxd7L8STb R55qmdkqR99WC4a1J7h5ib6V2o1aGpPa9wXIBpJNtkIRRBkzNvr5oOBP5pjQNrclnSfRWggHIWV5 uTlT04rQEFX/QYDJzRlpnpYOhs6nVasWh/Jjp4OXcP0edFoMZZLjMA9tpotHwDx4N/n5mXEenq1M w9n0uBE8IPjEWmdn71m6s+HaQAk47qY6Pzv/82Wlha9xeFGaFehUqf6W99ejSM27rGW47Wi7xcJV P9BzQi/Q5hVLZogzznHgLWYxihaY4HX1TvhrXZaMV2kRZyivknsbis/Oqn5VKkqqG2+BgsGS/9MD EDFnNcLJ8taEIZG3p6hEnMzfaJLFoX2EVXfmCuCMOsKGj9FM81kDdmaLfLuzZfodJ4t5+NdvC8/W Tgnqbx9MHb/+Gviuj7w7WjyZLGFKBRMtCkTtTxzA/BxM88sC0PhUavwo1L6F48tI8PB96bhFAvUO u5crPyhYpsmAP31pxWM3LmY8mflmuEUl/X2XrOgn5lji3njnYqzQwm8+bH70mKuM5vha5urkTwwQ 6zcQvtQJak8U/QLVuZAkfiZHeLywfbFftr20/r8wfnvzmPeI+RAZ8G5nalKddAN/tlylLPwYEiDK NGBDSVvkBfWPmUJyxlB1NWKDISN8wXKbTRAD4JY5d5g68rLLBVln4Wnu0RZyIrgWfs5n8mlAFOmq e+WClNYeFVt0ZYQQ7PyHt5vyiNYKV6gbglx/tsPxhxF/yYFtGSF4frQPg1wbQulhkFd+pu6TRBku PYhnsWpfiNhKwES86XCAsVPEwZQoBdC7IiRjf111iCQFQvPfjUqBrNZl9MvzcA9cbGoZPH+cHz9D AmWPRxdFKbDCA7K/iBtiP0WYGsUQrLFwVGw9/52NGFOpYde4KUhSDcIZ5yYZPIniOrhvbCIWCxJD ids6ppAiUNd/i8vE4Fqfd6ZrD0f1RErevu4cWsN9rRu1jlGUNBO8BxRRudxgCHh2/qzl89Wg9zP3 E09bWqsjdZ2tHZDf/zLYgOmU29t8ZOVCHx2QHoydzNVvqaf3ZJrVSKJ0cmi73nctfuSp4XEMN2Fr lb6wxlGylV/WUEHoBoq29paVKJcVXCxc/sNq9++vxHF4R8jj4GSBLI2zDnACgCYxgFJaZMb8Ycv7 S742ELy9UpjAE4Y8aS5XTdk+B1ekQPs2GZtGLYJ31j1PIwLr36Kf6trFjBjPxtjuDmXyi4FW6mIK BSQF5j5z5WyTPhexpL2RjKZ/jHbLr30cd7y0JSuNvKTR7Jw9m0+Xkj67yBIISFb0tt2upnVyiIoV LOgqMezaQHte/7Z/6l0wPtAF6plYik0SI4VWRNysDVu/mdnaA18erS0sDUKSEsfzmbapbBJbEk1A ManysZ9hrJgzDTJlJLXTsCMUBTUqIuRTWjsA+M5QCgva8cvxa9rDWijhEfhmhCFsYVxHVv4UJ5G9 J0QmrupeBVV69fyEBRA/HV24qtE0ARMun00mZ1KXWgTCvCXKEpbG8KLqjm3vD1OatqBX5BqQr5Ve 640Gq4pWfYYV+orEikvP4ScBOgklYJxgneTuaLrNmPDeeNPlyNLBxZRMm7lqt/hBYpRiWa+FCTQk uBfLdofT6fPSjlaVEO7Rbaiyb8ymJykwX477xPFQjiwXBD4P5wfM/+beKSaxe2BsK3o8niKJu/I4 8elImV4s1drTGzgv/0dVMFnfb+7kwR2EnhPkTDmHebhoay0gukDuidQs4NsTtLuJJFD2CwFJvA4O 5XL0id4r3hkkNGw9FKiLN+WxYwkNORL0aCTePlOuC9pZ1HKZT8I9ejkBmQ13Q0zaoTdGU3zsnV5s 4tqGIpTAnZcCbF+CIS0VKKTEF7FMplYDblgMUC93H1uFax+cEIb+njDAV276nYuTVLkOwCxtZCyn N12y9fAmeFqamZ2g4t/LplOL2AvqfgONtGH3EqOT8oVbiue7DNAFdtdcwPV9xMFxPIwrUt6bmwvk xMNRMBn4/OrqejycRhEybd3Ywm+B/woBdiLr2Ktw3dOXc2iflDYttFf2ws9DqT3uadZmLmHf/pUo /kXoFtTUPHt6GNUgW8XSloUponHW9obMsYAWpS9qe5+G51DLSQVDlxLpT6jiLACfVnPZrvrS6dm/ MNwyzR5PrIJMrDLdKhBZJqIzEO9AAU8jiXY5m2Ka7UMRT5OD6WeukwdL1okJQt3v1CzVkHc2wT7+ g0TTwgiK0EoNZUSwV2TdttzH7709amBBgIOnu7vzyH/6SBfMykGu7Vl8H6GShvRlw+/xrN7L46Bc abIl6d+pq+exwqdFcvMf0EvswOw+MXWj/bU/7tJsdJor6V4OeyQU2EjGpedbYeiF2r/HpdZV42G0 jxtYYUOwUJAtPJheXTmqRA0AUMWQitVunA3PAedGBNs2KyyJVh+OtmDcixRS1PshFxW/pO1Bbfrf 1UxN4WqfdpwCrO5MVpa6/l6indAxqrzQXqNzPkaY7hQ1J1l9JePTV69r3v3W1zoMP7O9tRn6tEWW EsC6NoWDV/9FrVsBIkYL6ORrCFvU/RJBj455gPpHJ7WOduLhCFxOv2rj7wapzxxnpxLGND0pBW5h duPiaelmmv+x2ImrhbNv/F3uzBGcwGyj0qediEK0614CPOhijYxmvGcrMgjMAT5WQFC5qefe+qAQ Gtlt938yxRyb+21FLS/Q571ySk6BOIW6OL5f7iuK/g1LUhp9Y6rPQaq9mRmEqfwaK1T7+ErzIqEA ZghsUajqkU8SFUd5mZVYBWdCrzj6NCkT2DS+/ilOiqbNPjWOAB8xIKlTI+uTxg4iayhWLqMiHu1I 7QOIcbNf4aO6ey6wXPntUrAwTBQk1LphLtjErVLgLNU8MdSPobT1PUmdGr2MDfuAvc/TMm7KR29j XCDC02LiwmZcISn1Q5qiKK3SyTbEfhWk0w/2JVOwikO06mwFlFDpc/O3ALgOcGThkB+PDjnW8i3W 1UJ9lyrT7JMhmvFhNJFAIDg4WS3VXKv4kNiNDPlJPx15dT3/CgM43S8AW9PqylubaLdb3MJTNbAu PCVBWYTKesrSwOPlZbqVvEixA6ep7lVh8y4/nV5vjR6BELXnC5qaaXH9V21l/4bO/qhHh9Cl/8tV eLYvjhuNlgc/dX6RRAEghKLeT+53soVTPwob2rAiknUpaR2do4faxSQ2HWE9hTyJOjH9yakByfua WYqCY3X5TaQtV+PCEilMBQ8OqSvLWRf5jP2m0yPUy2Kkae+1XOg6D9fPbsziVvjcwyZUuUgeCLEM Xuuve+jyghEdtLECcyJK62CfadbntXuKg54KQ25PYg6f9H1gaouP+HtR17KoKxbgLYqe9eDkbMPy rD2hIcUOZtX3kcnF5IdX0rv0wWhOruHqnqZ9ME+cTI8X1EC1YIunJUN+gFuT00tIKXDNstNKw6su BycG9B/+hB/au795mTAjoCM65dzYMd56dG6cGLiJZFRecpdcGfIF06y0tZa7Oyotv7+fY+xokXWM v7lmxMeG2oOtXER1NzwASIzLTdfxLGr3r/Dy8xYADtN4MfcgOChBLN+ilmPNm4vN84vfbwUiQmNa GwCIIm3Uk0UEsnb/YvNOCX+W9ZTU6V9DDFvDrUS0kpVZA1uRjzg8dGRa08oMeM9Uq/jE3qhB5lE6 4oPKboavpRv+UvPr/+VE8dxM6QjPGPO00UUv1r7OePBP9z2dj+NaQEvhFJ+Yr6eEVdUnQNjtOuwX lutMH7CHBcNBO15ZzYMOIKYR+H82Ik8thKplf4Sj5bj0KPCjKDIbdlbnWbsRs6JQjE1Sxb1ASD1V 55XcTNqVGCtjytL9P2Igs4d/I7o0kHNHYSM3qTSfqT0n/2af44wxMS0tMkTZ/yBXO4phoohkBPgU 2Ry5d+IjKz3b615ovPgLuMxjNkvxNdwzxyGaJ5X34erQbGceijCNoUm3T+kKnv9kAes82GK9j0wD ZyhPQgadKNzyhHqmUkhgxy1s4/dOzuqG+Qo79OPMP2SsS4YN6btVfYltRBCmMwh7PpV/+cO3UA7y /a1NrMCEtnowCKcwTe3AykvN7HCXTy4UnTcZCweezj5obmuu8BMO5+45mtwkx6W5YT7akrFisVNX PXhtoNSIOqxMyxA89ETyVlbI3X/zSgP746i5QJdJvNM23YuWQYqSBnnnABa9m7SVuY0fVXlg4qX/ CcC1sfUxhImH98IwWMm8fMaIllfQKwH241xNMXiRLytWlRUmr5OvHsW0i8j/GPGDHoH232Ra3aND e0hUJoLP9ZXkkS10knD8uDS/aYiYzR7epJmoSTG3s4jcDdfV7Qn8qJ7SnvAopX+8hWRUTUwmZRRr 05pqH/yePxZ+o5zUH7U81pMG+HsUqAIMfmKXrNQ7a9bLIYyE29bnnFhEVV6XLIAO7Lzui14xiYy3 g1/fU4Vkl6qmHchC0IyPZDbCbJOz7fKq8rssv1jMajLElN0EJ6T39wlyw7zesFyEqLctPU1vS1mH 0JFNOxW1EotSwd1Da6OzXB1hUBgZmr+GVgfrJsohmQP2RnPu6mZ1kQYHLpAVRpBgqSL/RZ52c5a5 wp0MFvXYmIpE8PtIefjH0rBtsCL6ErOgXPMcXjDDIKIgFc7DgkEdhIK/mmVfNvAhytA2Ey/KnyR8 AVwpUVyaIvJjVCzCSCRaULbd9zbHNtVes4Lbm0gXvtnN2lr1Sza/Hrlu0M48O32UmBgQ2p+xRqK9 A6aj1kSObrADfUXkGLm7dS6qhgtxzMrLnEi8g2q39TI4gF0KpGBefEydA6JVwoXRa8gAYANL7eBF 2NHy2t4VEbFGZFK/LpLWzuGmQZI5cJo4gTBg8zvomqdk7pD/AK+c+4z6SszxPcy0cR+ACx4hh0xG 8A9tPzscgcGlePtc9b0Fu4O0SLWeQyB2PM65tAZxx7wzyYgui2XV5GAGlCd9g/XWAhfRrJ7eWAO9 i9wUYtEVN4yFjW+scVzob86FPHScMMZmFF+SAU+abK7G/QhrTMgden8RtGS4R02xAQeivML5VI6i RckU49wZGGf5xhz/soopFFLZ7AcBOE3p0P5x34TdXAoAv368r+I079Gi7lKsDPfmBiIi6yHIAFkq cAbZx8jJ8BRiRV5ZeF2nBK3HhN/APY67i43TeN+fKmH3RAx2R4GN/QPn9QNgkjNKMrTvygWOnEnR QcRfrnundGIXj9+v5tEYaMni0MlxQNEQJyWB96qf+aoGVJMpBXGwHKHQy2oyPsaptJ41HfD1XDds wvVIo8rrnkwZ15uKLf42D12MnUpqskHgaHVYrp5GTr9Ws5+fpz6gYocBTWGqc7dp/AARIET358C6 fPkmNPtCyQhSFUEbfuR3iqIV7p6ke/Hgc/SruFGRktq3UVtg4z3DoFsqVWI0qZ5H1Gc1w0728Chy rq+rftj9cUsBv9DcnHc4YgzbprxJKJ48yf8QUL+DeZBxCaQvTVOIQ00CgBXTfGyQX4oBE+inwOuy 6vTiJDuvEDd2MGjEDJyutinU/DrH1GvVcAKAtqTps6FobhCxMXH/gL0vBOjdRPWdouEEpqVl4393 kQ9htDEzO09lyyncAK+ePkUBWKw3l2fIPuT6wx01rjqGE963Irodp9mqUenGr9QHtsJyciinCDqz cFlPVVN90AWRkzn9saGtUuXoRq7+B4WxDmcS/JKvw79At5bULnrK685eU6yTMDt5L2st667zkOZx FJyXU21eJiu913FKK2R0PepblyToKQvUhivCWt3ye3TcotMprOh6xE7WkPes/UA/WFS2Xqtk4064 HvsCAMeH0nVQZmzbueZ5JurbJquQQZriyO/RHRBQWM++62RNGHKMwAD7Axg3kIrG9kqu/SUvPY3e j8BKWQm1uDasV7r426Wdcj5tYRkhgSLPaD+Y2Tp08oN4+FVzeoxHkMOTFG5JvD0Lb1AVBT/UHDSr odIFrf4hOzlMU00EJdXWHRIN8wwCHEAGxgUcjtfew9WEElK6E+EgbTHQCOAiuK3yOcLZmRpXYQ0J tXpvJ4gNxPnU9pX411n8DnHNkwm1sjk37MGi3x4EjGyv4lIewJ3w+Sp5X8wyTesMXSlZzxsD5X19 ntvkpHe+VSeDtHrR/qAnS/Z3y0eYuuFbb3/DzKskRWNaQt0NGvVzgf0zcTTJnSelgyH55lupbXIY oiAIxpKrrYtxwF4z0F+5+nXBcIx+v2KE/z3rlEyWe0uk1cMg05IzNEKgmJvgqIOyCC0E7+u1MB85 bWJmUmNH2vafWtypvdINF4QqqebqmBjUEbPtHCZmVoJhA/rdapoo1EGS4G4+J66qtMNj9uoMnctK wGwijsQNKCPXjJDd/9FViY1/uKC9GlkO4vTGgvSW9DcPMLvGXfqRl4h0h1xAGf3KNmZxkrJC0sAm w/FrHvHG1yZweBpZ4chjsHFgP6kvE54eIlPX0jsln9n5ZnBUXoJT/KruAP1DOv9ba4nuMoZ0HP0z pupqquuKlO/exnFF3tyBczHhSHjg0gIR/vBVeIlOCGYZY5r+GbI0UNTIXNnD3u14fVV163OXHKxM cz/74k2ZCGMPS1SoyDVRfDWr+PFrTxC7761FS1zSyWzG6+rn6FJuCNhicpU2DVcWG9NqdZUKqu4N HgiozMOn6o6KNm17gB6cMuwmYYtEyc59f8IwvBExic/+aKpcNnPr5lYN5Xvc5q7fb7MFuJPMFYI6 9paPOR98ouaUJn2vWfCBoKo/VWJ6d9osaduaaxqoDG2dlAfHVxDO3DjyAcV0V3dJtJygroxaOaH8 CCIoVsj6pQtvIE/sdbzZwt/eiHN+swel0fF5dTDF7vUiN3CjZnOh9HpFTB9rFyKEyjuJH217Xsvr 5xcyl0DWL2mzeqXtIb27ZVP/bulHf/cIbtF33AkidKwXhWFVPkf8EM4YfkyTJuggIYr00n76J9l1 kR7Otss6h428b/iOJ5NHfuRxEYqVvvO9OTn+H2nitqs4Qx+wVnT9r0csYpmbCAc2fTF8WzqjR34q EpQgP6JmDxqAW06SWJJr+2jp1x1YQ5wAzcODROjaHuIFJngkWDYo4reog233QnJjiy0E8t5CPuOJ EtVMwG2P5MW3GhrejUw1WNBRKbrwjV/KuSpjGlzm9Hg2Pdqa/7Nf2WqeuG4c9jO5Tbsc1wdNzmhW jKc3pvU8lSlGZacx6JjcedP2oLIomqb4ZPSkrWkheVjQEs710wbTekvjmcnf9CL8pJMrbknYfkyo DYzTNUG4xRHa3CWcqmMKTA6EqFr13Qx3iACcHmBVYcsr+vx0DTtVRlN03Cl/Iw8CUuTGg1V3dI8h IhrelZOMjdgoWK0Fs9Ltk1hWGTpFYuyY0+nvaWg3XyaWpMtM6xJTPP8W+X8o3q455CcEzaP7PYZl +vCpl6gorY61d/3jRFKw+Kh5PFUIRLIJV+YU0CvD+AU13Ccvzxqff7x9j7+rsVtLpImo35HmWuZH LrOXSJUEcr507N5jgWSiYXPFTIkLjicElSwT9b1MccIDj7lF/gM6bq/z4ROPPuwljwrFh02f2Z7B kLmeCnmhO4dASSl9aLc8MWH7C/0Mnplq5NYKxeZl8kDoavG0spJrELRSN17q4GnUakmUy3vAxuPR cSRZPdRsvIBa1WtZIVMPxUD9LpC1zw6GCpUdJ0DN759Mdqs1lxcHHt8aukPrlODrA+yv43ENtYTf 7QqpLRSuQApl8Q0RJ3BHFYt2xRzLM4HgTNdoIVn4Rj16V+qbfmXxZPCV285MWqwz5+2Ccy4dS5LW KDhgkKriC6kbjCwDpDxhDJj7ADs0AVFHInYM41acNjfE5xc39oeFNpVd3hD9/bFZ7gDPXXK8OWl8 DIh8XfC0vkDfTklL6K6COI+jcZQZJ+TCFrNOSbp1bH1F1hwCV8i0miUeaUNyCLGfC+8sclONgmqR IiyyP6eDJXnOiGXaG2NxSNK1Hp9R04V3iruF9uBTc23Azg3bOmfKMXY6N7byUvdMWkLpPgLW5JF3 ggmE31zEx1YsYbD5dfXTXjQFcRK1IdH7tQZQmOalz/jppKy4NqfMxB2DWh/tayxREXZG4Ehxphjv FL/iIIC40edpLfiYpHKBK120M96DHFXn4g1nYj++hGOY7jvo1OS+TiqJ2XY1w3A3KtaKKCtBRIT9 9RYcnnLoSHV/wCL+xxIgoHIkx/gJOKK0OmftIfzzg/+UUbe+xKB8xg2Nex9juDEVdKMQuPR/JVAE CqIiDI10UPhZHx/fKaIj5DlW9OWs+s1a/hKhUTdCNM9f19ArVoNbKxTyi9QdkdbEZwIalC+9RIpx P8QWgAV+UGD9hyVHlety0xejX/VOVusvoIqtiUaX/LvI1Jln0oo2k43GRtOBGsWX3vGPngOJSgCP hHmetkbcNAmYQrd+XRiGD0ecUgyCPwNaZwOHuhccj0hxMmkMsIhpqqBpSf65xDPR/ddpZ5RSddOu MKgyiFwOUXZa+6lDuJeupeMTbXETCWf6seoTKKd2yyp4UHwLysVkVA22hSJPKsy7jWiWzHMtK932 tN51Twsl1K3NWHsGognKRpb+XakBjFhuD5Lt0AFVoFFvWhd5cdLUgMKfFiZwCVGP9WL22uDNlEH2 1Ek1c4S+YfIQ3WoVjKGrCUMhK6JSvd3T0l6SQZ7LE+DkgM5ohL1FZstuaSmmf0V4mJaV4QX1vCdK E+DmWh1uYRWu8WrtFyhN2K77XhlwfcCMQ/LpE2Ej4JXGsqCD5I8zWr9p0Zt8ljeXmdqdDQ5ebcxK 6DUEfJ+uPnwlYWDhmL47YNg/ArHvoaT2mStqNd/48mWzFOv9zC3aaPeedIJOzJnsCLlIMXDCH/X+ 7WXOhwmXkKlPRBdSEDBTEZljKy5d4nj3oAUOUzGyvVzw0BQTzTY5d4EYIu7JNj8AeX7A0uQ+zAF2 iAfWb6DxrjzWdCDCvjLU2amBR7lNxGBrA/QvAGgXJK55rEJ+F86vm5grc+576E3MR9CLlYHtDqzU khjZlMYuiyhkpIZsV67dSPh1fUQ3nD74ADzATffPT4UPNV9ZLRp+B3u2Zb1SbcB2SGnCVAsWnabL 3U+lUCygOh3WbS0k7QC6OzEKCnPqv3XxjajdjovOCM2Xo/6DqHgZ5J+tpIX2z8DspfzkDHbW9KEL p7swoE+8+mQvlifd3ieNZco9zVPwIi0T+x9Hllut4SoQi5qvAuq5FSQtkoQCLiGzb4X2iBSq9wxl jyuHLzb2fFfmaTQ3afsZtGr3Ud19TE6GaP9MYVHpWyImm2fkE0ItStlnTFTxoIALdqfribgETNp7 rv2PwNAFIk6wFiMg+Ikx0VgYz8tJmTNmF+nE+XmXpDKYRFEWvHeuOHtWfgh3UNwcg/0ySbjGHp0I YycB/g71RGJP1uufXjox6s9WjwrqfkAejHAxXXTjHyB75YUF1mQ8dbrzbcpNXuo/ILoyOMvLITnX ZU2ghMGAzTuDfGCyw43kzyaz7deLIKZt/x48d9oo4zpibODCK3w7cffiYCst9VqNlSY/gnqyBFXR wMR1pXtOZz8mJLDczxeNgqNUeZbcHEjNxkS3rudh7yVoXKgJkXhBVYdk20prq45ZBvSbJRLDSSkK PcC80XfhRukSSGP/FwR+UrDOpH1yqMyQkW2jEF8+Qkwh4aH3Zhbno5+QoymNQ8RDhRta+g0NsoAF YVGWef/NGuM8BiTiPA7zBf49qhphvfXDZ70Ip6urDkHluymW2UKcqzn5IeqwgP5Y7g/I1YSaPF2d fwXE45Ev4B1ATnaLk5npuJkerYr24ZTVX8ou6YQJKI/i+eu3aMM12Ze7Ldqtm78v5acjtkLnX/5H lluYy74RzJILe107n4B3Q0F4GnOFFPJgT6TkA6XPjfgMzcvFPx8G0HJJJLMb28ZFNkS9WGtWC4eQ k+NQoMfzoEVz+103+4kg4STS/+daiHtbn/eTLgWL06QlEhymZUT2f93MjxQH+ylP10TRIdFJSzWA Q/DhcptHVKj+k6ce51OgIzoJKIE8gXpbucbiJD40YjlQdC123vhNb/TXeyP8F4I3xDc8wQRpugli i10oQz5m73qFJlJdK1VfEa71VDXW6VwJcVW3qRbAhCWSeV3C4m9Lr00WqU4mduNmEH53I0wZKi0W Od2gLkBnO+Z/VMw1i+hAGaeVMDBJRxYBtzhssZArz0D4b7ZDOHWU1A5UE3LMaq6DUgYN4K+h7zAX S0Rl6Y8/ATsVd1h3yCVHCQ6Jherir1WxxhXTZ2b7V0egzWX/1Hntp/nl2AR/2jp7ctbkWgect3HZ wSA9YrPuLsWgRx53VxqQ8fGaJB0YdFtBWRsrwr8JnPHq2g/gi9g7pZdDm0i5eGPqV+z4klRtlOfr EJchIncBfY9xWREsXauOrEEVrX14JzdKEPzoO8piGN/vZhZCWXBh+eOVFNo1RpsGz87WLbr/24EC O+SR1A8ELIN/JzW/y+WbKoXHxEitycEPhKPlfdQ7kYo/3eBEwGsrUYlnwSkrWo3x8PDZcAdNoOlJ HfFuBwn4KEp8UWYqyd012KPIyuGnS/9PmwUYjiPZz5ORPcIaPL2R4Hf8WTorSOLqsnm8sIduUq4J xm8O9inkW1SlnTW3AYvpUiBGo1Vt2u7UKSprmuwQmAlVhFtOLIc9nf2ZZFm61Fzm8W69fs/Hn4Vk ix1gDvrQwKrKVlgraaG7px8GKcsrRgHTxDrlwsjAwHmtGgf7Rqmbkeuf3+JzSzkNaonBEqTdWKiX ESNl1X+YoSsdaqyhOsDdynBmdqyiB0hxO4pxd8BPPDWJYwuzXdwweWldYOcmsryqhP5g8zQeoBGo WjQTPr9JYUnc+QTT9PbLWR+p7+Fxa+97EpviP6VAAxnYLOkallfFRm9fSuS9HcnjyIw13DYSgHRg igGtUqGWaHuBuGlv0hTf8ity4I8EcuREjE6Gac8P4936sSH3uFE20slRZVFgzaziO1xK2apZ8RT/ LQkVf5Pd+Y3wmEdY+iUAuWgeeZe0XZeQLRwqAZc25gKEWKk7X1iI6p4RXtuwDKQPDwauo4fLS5xZ wm4190/QOMBnxkAan2xVnCLRX2rLzCbeNNioABs9qNFJG/aHEtnNFqbYa0/BeZRZxX9ZC83dTDxu JTgDi2pxKE8xIWBtcyyaNjAgO6YTmqhl5uvjcO3oRvg+LIg1SivFLZXN2OfTmFbPw003a83M+KuT eTlX2Yd3ju9bfNqb84MMGgA58fUn/t8LQdNKFjNczd8zAMEI+QFl3BeEtbfAtkEtSVubPWiBIQ+N Lv0S99GgYOi+V0FmB39XDQTcZOkz2yi4Hf9kCqAhr7fowfyQpCFmHSjFsq6qQXhJy7Bnn16qqwJ2 NcrloXZYxBbbcvb7weFDd0+0bkCskAGxOvoP0YKmDZoKjxspU7njulXc5iFkVLTq5XvAgUWsVasx 220ZCGe4qbR6akR+TT9mwxjO7wkKk6zOU6AlTcWtIlAXYhiqQ0vdjQgSqaYKbeMfO4SfPzxAeF1O 3XIEV9SiirXPXTFM12ZfSZgzxFezATUP0K0SpNK5uhTPEj7XyVnn+/3a2i6Ijh3XOQYoFgnGaW/P pvwbninyoVIDktGheg8EivLF86+JPNe9Deq4KN5zXolVW1A/Xa7tqKpEGTgJoIn5nG/B5uSH+Qa9 KvnZIfA5aIv+eOj0HFCJ6fEHye289t+YCHZ6VY5WOFkEOSjAFniC25Mu+SaCowS67uQwWkj1qXbs LO0C83nnNkN5Nc6qGRDqwAzGFe1bTW4o/QbJOtydiOpWi7IHNnmYt0LQPZ1lb6ufHG0zRvdrrE08 /GhsTksUSXLvENRJ288JyGDTfjH/8FL3SqZ1gS31VtNcGBB2Ls8uSZCGfSvXg5TUX/aDEAJxLAhM c3qiwR4gj6wFDjlWrNIK+6tmxtK3UKiaF2GJRvm/HI3xcaawy2Q8VfG0PFXbhuFl90ghosQpDg8t rxeuFmG0tsLdKeWML3SV29zeXi+iyyXpRplsIrzjvGSEw9KYgXByIfWulP+tFHw0iQtve6tbz2d8 FZaMWtLmD8Su0I8g0gD99l2zHzkfvTiPAy8gXuSA2EWyA6L7n4+bhaZ9Wt3KOqh44D+Cix8w4G8I lkuL3dAOz+MMOUIxA48LxWwzsLHg5oA2CPSDlhoz+LGQafS0DAY+sVKhyjchsuZxKOMYf9tauYRX GnkV1F6s3RGqlzDQPHjI2nwQrnfGVHrOkfZo6AtlfAwiiyi48l8SGMyd7leUKldxnrdBCD1fhons 18TDCkl3ysy6x1baXYTOaDoqTLTY4EVDTs+nVbTu2LzDB+3j4tjjxQLu/FyppjPcO4RqALlnBZ0D 9fU7UAckW/0ycyYA/B0V6cEJbo86zpZthMXxzQZloRoFp/3iIUgiDWbxNSYDLevwFI6sKS3wm1v7 MlZzFejQ6olrykPjPoFpT6WMpOdeR0AJyTrEshDwfe0RFN1iwbAYqQkAuR8SUrLj98dQXuFF07EF Yt0YD1cqx0Jj38ycQKdmMm3Mcu3oCqN/WyXyO8vgoyCV0jReh34jbG4oS7zkvZJRu2SPYvQr74aR W1GM5/v4rmGmqLhEKnNSQUwumJENNM7NgJO18bXx1Y18CF0r64ZsDayERq07BDog7yPoUTGpXkX+ IsmtYx9KP/rHNLSgXPVNbm3sYPbgGEJzlwKgXo6OrBzvqb+zej7CvXKWkStq7uqbsOLzlTxKsjYI qvLtzh+O4XmmPr+ka5eW4kZhh3mmk/Qb9xeb+jgMp36M661v/I2yPz6QbF9nSjGV4LyEnbxlKKx6 xDJw3iXK7AhJSbqIPtU6KxTPMgdfcekwQ4r9k2H1C3T/Jj9JHSt/icQQZzhY2rLbBbdc5E5YkCB8 4YYhRWm/si8h4QkK6UtQLi16fNoLwKbCEWEriaKBDfwyudstWczJxvk/Bk5VhvAPm9MEOrNeKG/i ucMOunfl2zwdWh60OlqUtRgp3QTzEPiRSO0NIntjwg5RA40Vi8VlcmLcpHdEW6+7E08lyyvM5YDU VBTKg7efweWx6cNd32BKMNQg4QIHjeUHYA+zPerxlw03RuQVSnEfTSOXQwRC9kJjCl0J4bY17w4L trFyBkcaXkbxDEAUx7GTEeFIGh/SLPwwDb8pwtlCqnDnfLWreFxYfrtQTA19LYKilWcWyWwdGXbn HDyeSP9bkMerEkOw4yMMmcmQNr+FbY3R5oda2gnvrmJhednMsN8rG5rh+/LZdX/nMywXdnWu3xRi axHLL2LOoO2awVaaK/GtmSpLBQgCZJTg3suIoOSiINCcF32s8L0l3aB+kNJVUEOCvXXzjcvGPi9I i4cYCUUe8T25pDV7NIfAQJyZ3zBeBtuzeaTEYJZ1tr7iuu+JeD4vG+eYhLOi7fnyogSIfmftd8HQ NM7btqMZZPFOmav9VmLyGHaHILNfCA+clxXrQRAqvGiFwKa40ZlDG1O3sxt0BH9Tw8MdqprmEMga Kqs+aOZkcrCTf3F5byI8oPK/Wh1wGHoPFvHGOgqXTALkw7jjxNhmxhY7sass0+v5vOqFpmAp8sXq wmbeeC8nP91G8d2gH4+WKm+WzJ1XvzXfbOvs1g/AuszVwAZUt5L9uyGZav/PW1+A5wfOjc7qj1jJ 2wFV6pF6uM1KOoi7jd/xoLb0YGrdhMO09MaWQbaYohG+wLePnP5OO8bVN9p+ISytVzm9AAyM0NRP Lmri/rwMl60E9vpIgzrYteh1Kdfn4Du0SfgOebaAsA4xAX60i0y6Uk1HuWgMji072wK2Ws2r7mN/ zbtaWPizAYvCyXW5kt8fRvEqXDvPj2T8bcGnMfsZnrpKGZas19gWPsl3pswMwg449B4cc2TiR4h2 eikMS9abDkgOd9/v9Sy3FWQOb0WISIBG0mcIP9Dh+I7FITX4na9W5SnmLUNmcxE9oZYGZXHR44sJ Nywu7tBr78jktNamLCLjuMeYPKoUEkpOtxipIspT98nDQ72Sau4ZCmEtV7BpDG/DmXd0NzOQ1MlJ YKwiF3N2vkYq0p+un249STq5N+FbcImCW6Xr5QYgoHAA33CE7Gus+jTQZpDl9+OmIMn+2l+SLF5A Vl+2mE1MEXT9SgM76qn+SccGRIgj01jqeSm6YEge03X6btjDu48J/1Pd0Li/Wn/89G30yFD4g/e0 qSwxPbwO/oeQer99PFovwC0FFqxnopzBoGBbVcXfL5L7sfwxHipHXgfa6PQNsV64+TBRXTB67CdZ 2FOr0v9ZIi1JqDSWmUBbwCgDpNSUfik7P/CMpjzU5hmAI2Bo2Ty5b2dXWewpCACARI1/WfOtCo80 QrRcoJ9Y0wltQgykfavoQCm3fViJ8htEBmeUG4Si4X+/2E8vzAMtXTQHtJp8D5bCnPn7LPWvT08Z Efw9zYIebaSx1gP18kpI7Neo0fHB2i3AUFtI55EVwDL8AK3XxxbklLOGv5zYxlVmFnLhj+a0cIwv s6NrjoHKzXDGpGU2Fw9kVZ8tSw40Ozz1vy8omLthVP2582iyrtQI/H4m+DcQ6D6MkYHnvZ9EVK+p 0Z2wpwqkW/HtO2uc1T2kfoT5meHZZdbFdDktKw/bpuDiH6xd4QUDjaGBxrvhbYjFnAU56OpkBY1s s/pQNMFEpbyjDMnKQDtqlz3Nc/23gyipg3hY5vxezcS+8jmcs7adkUryri3xNa66Yc2HFyXj/0bb 9SGSr6ILB6LGwhlavV3PUUSS20mTI0hM3Tr0yIY8xEAvAav1yMi4yPw8WyzCr87/5KGl94z/qW89 5+jn2UERedMvFzE3ImY97iWzToHSxrAurctmcUk7SUmRRWlfODtINpL43dJAtuZiGcGHluHwJTy2 2EmDUQy+MyNU9C57Y/zK0poIkTkpaXOrPyZveRTqtCNyT1+LXMaOFZGmbGOXjl7naPHqzOguhHAn tHrLvy7tzL4r9Oe+gC8yhZj8MX8GZQce+/4N3//cj5+ZRvAvuNtBqQimL9ZJ+bLwIOb/ZRc0/FoE owcVPXt/2qJpFVWdyhjqZ0sQwxRBiTey+6Xnf08B8SbBjLPBj8RXI77u2yEuadizrLnhWykVaLcP 933eGpEl/kP3TP5AtBUtzqNcqr18nZaq/Q9I/5vPhe/UbinkAGAatqR5k0OuRL71mI21g3b6AlxA 74Pzd7wNX6IIMNOdhUMKZBF/LzXiD8KgOzkpHk3cK/OJTbtTf8aL3KBG9zezq/YPS5Ayg1tVsIXg syW/EBG0ompYtIWSwglVmNefWw3brPChoEGkq/qvkWXsF7Ji89RdnmfKJWrLY9j62QlLbHMp26U8 zjlKLHASH3kCsXQsiX52fuix5WBu/u4Sv/cc3Z1iayR9Bolj+KrFYrEtCAGiX/3HGLNsLK6D7oLx b2Ep+X3HVMpWvap0VCgOJL49K9ENmT9JvNPkx7xgdTqtMTZofPvUvWk7/VWOyLqVUfpVL56VZ5OT TgG3VrXBjHIo0Mv6AyH0eCYCylFJu2dutb2cJUTUB5IZAFA+/X3/EvsoG/m/9TAi7w2yTudUePju opI8jF9+eJ24QF8jpFnwLFinN5aLUk0y5YKTEMT5atp0+EOrjxPTKXt1BirJkcGJdAIjjfS9D7MX d7Blxb+u1WmYO4JqlKlR7XCQe7y9/aGlSQiZpy1mqyvsmadktBY0ofbiPQpSzvwER6utZ+XB8FsD yhjdCxembGWggYoZKEtW5fQPVHJ55JuY/uE4ZwYMxuFdy+AD3rdBmqy/DF7k74xlOzHYAgJwVjML O14jsakRzlAoWLFeL3Nq61BZL551K7TF1vfEWqHZ1W6AvihkdrxZXyTomwMUPydU2EUvHHhFU+Tp x+LgaZcdxXwJAuCCBegktMeUKVVFiFTwfxEUMOF2/9eZmFzq3W0+a1gAeExVgqyc7C4sC40S5f5y HibJ5GXri1UnEHsUKHy+6/poZO96UAOcRP6ORc/b3uPjvJUYQx/kUsmZ0P+j0SzmDgmBJeSHS4ji oa+ffdDn9nhqnXM/MvxlBsYZRfWvuGpyc1cU7Wb54Pc1CDTCpM3eW3/xQdZsaX4BUohQu4+n7ijT Mz6lMnqhf2Q4kpDO4QrT1Ur77RUYMVDfdmJb80qhzcVqmR76KExX7ykYXIKl/zl9HqxbQ8rpD3G6 v0wsAGh5/YkWNno0TCXcwcYVW873shkAZUrBO7hPiiwlZKbw/1EGMs2zTvqRAOc9+2KjFHhF7s6m FasnXJuPYEvVDfXNW3EpnnnieLO1E+ozUvYuImC/0k6L8bYsWfrYtTBHeDYADKCvgqmP+PkppdpJ 5U3EitGQf1tKpaO4n5Mo6EwddWml/fe5HFo18wUf723Ei0i1bp8tHP23Hav5ghbQ+kCug/ysnr9Q joZZrPyksBNNQGTkOFvBLtUsbss6+7KStG0lBRbm6Y96wyq0mfJiPOEUn6nFeOu+AsVRN6MhFMjY zZcdUpJOEqhlKSh5uzj0a1mmTzl7dg9s/bh1xDDnNG1nUUocdm/IYT7r7dzb/NVf9UiU0m2mcc6A z/ia4nMTJhrGWsMuz1MSkoR/VDFhD4kOQukdMvjufLbA73LWHtcZ07AQnQe+KsoljAh4pm+DTcAH FJQLcJUzE9DHGjUHBdU00QRoRpF4xFEKVM0rMH4mx8LyYQZS6glbiwzJTLGTCJ4/qHJ9DWhSd0MX 7vIgZYUuUQM9FOV9FBZNFPwNEU/Csn7lMyIc9VTWrKKeL93XDhOMbwhBqaF3Pwavgb//o9xoP0e5 Lq5UcVs5ejRaPIViEEmyzBEJiAg9M+2RGVgRrMpKzoUhnrcSyw4BG+VEODdet0ARJ9q4SxNCcXgN UTEoPdBnU51TvqwCm0S6Kr/3+n8vDdaboUJ0er3OC3GNmYDUxwvhNhlXBH30JZsx2YNjSWqX6UCk NoIoj564qIg8VejW7Mz+arqBBbPGdhFy6dZcCSJzFeflPQ48/H4HkMjaCTc1UegGN1QR9osJiYO1 vAQ+Ois+fFFoAXfnHC+8Hepg6GicksHC+GU1R/wnYXoWcscVo0I18FL+X9RzykcsoC6kAuT0Tp/S Z2GDt342lDnenYogqGNcMGrE31UWWv8d07dpWYTz3y1BORFP7/zRYzPiu31xqGVbnwel9/NRdM2Z Pr6iHkhWw2BS4wKb7fxcnW7Q8lH+LIVkTotQBaOj/w+gWb8geHX0JaI8xEWPXVYo1cN5+F1Zx5Rd 9sRk9FOzyTBYyVtv4JFMgDshdzrnSr5zhlTm68OeLBTiCXLcyLzdh8SlMyaHWdqjifU50wNK1zCb WWtQyI0y/L0LNOSGwc4WWpm/5P1/KBCI038oO9JAcHWrjFZb0C4fFP1UNoRzULzKQMW751IJIq3z PCFjacsdC2BmXJgjF0sqfiAP9DaY/otd5/HURsXnRnXU3oOPI675p97mZSVg67cLCtu3cvyFYpwL hR0eFmMEoYSmijsHCuVsSN3BARHd9ShMpHaxnB8RGWJHOgJOT1Xt7ZPUeU9oOcH2QlK1ajGdFI5T vvRAlME0sa39Rqm1Efkgcecqe6bjL9QbjFoa9P2C1Hgbp4O6W1qctoUCdAp8qzH05cW3Fk9Ty/k0 s1BTbhgkgoOCIt3f+wWceIn5ylJAOT45jFeUS+1eON6ywwy75PytMkyfOaGh/QJTE+nsVRaviN1u gz61wl57YrRaTfvV0KthhL4aDr4qt7O2Dg09Du6XKdtQPSiSEfDKx8gRPPXxoVTeFqDUDKyml4+p lLPfHmrFXlMFcTVPZo06rY0tdexhr0SVmriNxJ9fmx2lZSTY1HuL/trsXB7k9oVFXJjxVwcrjuAH HmDolKQbQ5fcMutlE3utHcnpkilighsoqpLnk8l5aSKHt7DYmbpZP6eHp73VhkZ5gLuoBKzBQ4jS FBYNDxcS9evnq/KZlhYuGqCIGdfYbDpZsIltccYWI1gTlPb2x8OFQiHzFUoRZ4EX5MDM8/gsEHp5 E02vKn76cj+V2D5zO+dZi3plAgkYE0Hb7C7823eFY9wgmBhz25thJQIsduD6ZsL+JC6tAunp8a8H xm6SSwiglEIDzKx5TfhPMDJ5Ow6mvQ0NTD5olo4EZ10OAjOrSO84T0y8oQZsC6gXz2hF7NbDIRxl 1I1H45gB+Y3ULBrxRWKPlZa5sULVKJ9obTc2AQQOR9iwPcZoOcSAl9ej8H3MpjZAmZOHCgs3xeiK S/Uz3fNQdeBk06FeE2f4vJZXFqljFZ5yoNCYvDPOYtxMh/NDxANDNPpCyN5Lnd4VNzYEtlLD8QON iqOOde4e2QyNEaIkqb31GiC4che++Ka7VkeWmPr3ub3fRzpDy/zCKGEl7MbrGQbL4pSz/GlAbyyx FXY2HvO8VoXZdwwhxJA20/Gt+t6XNosy99A6d/7C/O7sfH5+nvT5t4luhF4LHdntFy4Xhp/omPnO EE1EpEs4Dc1S5M+O10OSzlKrqKzFdWhncYkjAAvtDLT3LLnYYvBJxvb8XACM/Qh7vPektdIa1Lre Apl/hFv76p//8pG9iTq4WTLT7CX0doHt/UYEysKLfYA+CJL/3z0Rerxar1nOizYKVSnXTs/cnQNO vBFRR7oGDQz8RGlt3s87UcvWPL0zf9pQEKFGIINRrZdOiU4xoLz2dXBxM9TyxbjLUbfWb0DJXM/3 LFuWSoJUwwFQD4CiqxfIKtRXtdhHAj5J/kzJPSb2+3adZzowsuof8KNfv63eZ1TuX26fiDH7IedB SqlYpPGnYqIc18CpLaXUbldFr4dLWB43UXHU5K+PvmT8fCSQfC9KdXqsuTnNGwBfMbvuUtYRfcAF pwAj0FUPTueRO+2Hh85/SVKbUVcw7o6TEUaAYpOrbvDKxQo2yTEcYSl1XOTVK2LNmtHjCSxGA/58 BEes/7B+1a1osSKyS5cEKfx28UWpK9LQY0pVW8MHPFrfWCNmhdsbRFgQtk1A6WmIX6ANJx5HE327 wFseJPX07m9RDRLBjhbcBY42uyDxX50VXkoYN8/5KgZbt4sRgnAJbnEGyS9wVMrGboCwbFA7zhH6 u7B/zRTuWtBiq3dC4JHchbXUi7Nv+82SkCOMY3Q4DNTm+ziSZdHIttfHv5xi/SmO4e8HSy+44bp4 ofqSxOOYPA4fiJc+ZkwohMbJihDwdioz+K5WEJFD2dnsx2CxULBCqL2Em6AvKvcD5sxC2sN9PjEn l0yz5UzFZMCWa1Wy0Br+U7N/h+rc1ScicVY3f+HnxmQ6HgxRYMVdR+0SWjtckeTApzqZAambAGUs 7/CfsvwaOk0Z+qMBJsMFVP1GVQirwKaviUKzmpdGS4hLqpB1MN45zOMS/fSFIoFRmuNZqmEXW0eL dqB6McE0p1aWyYFGAXjRZWOSazRdZWvWo6BaFgiqhD5hBujDwh6ftXkvpawSRoqnEjiiFo8iHyR6 TnLci6OeR2aRe1ZAiJCddIwOFEmeZXQJbYE6fQ1yn0OEJLPRX4gDuuHI5utM2vfqRY75/d4AO8I3 s8kHn6Isyf1YnrbQr5qNKjahUSm47QroTnuJIfwLp69aqut7slXUuJeaSlG+jdX3o48TVnwmHWDc 4c29Q+qw2SzzdVj+jWAcVxlvJyLynD/6CVk8uaLZvyyJQ/gUp6cVPC3kl3yjuF9dc8bKRC5NXz4S 7u1jzBFJeXVkvysUE3qJabG1D+fB5Ea0seir84n0WdOdCzvQFwg72fiowp7yIpDIOAA2q1B+G4/I HP3/HAWsApK9MZJQTNeirqsyuSRYADD3dPe43nH6Mol4JtKzKAVsiuZKxujv5kIWYPazO+ngVkK8 aUsFy+f9jRHk+bP8qyyKaHFcCg7f39VihoCOxEhrufS6oJ2xJNIp75rRPmG4uWHWlCr/zlCT8FQM R3w0QCyQpIb7hSzZdU0CMa+AQIUwe6VUzWSeeftmvWdgTQEVb+13oTN4BeQ6LtUkKidxxtTPdTDM 1quBR4kp2BM+F8ONwroVNmQ9Q0OOJMcddJnFB40UClVQzypPS6wGwAW07w6Rlq8pXcX5FsLlNRRH 1S3VNDv5Fu7hHYLA/nTCOI6sSr2LdidIa+vPpWRy01gJaG0mJg5AkTWfMofsOsEIAWSBwR/7ycL5 0mEXBV6IcGXOrPrE8fjPCkgPbbf6+0/XKktS0RUBfppbPBAboXzbSYcfhKidsj6VPqvbwQ26jR/m hZWQHqRAdo9I2PvSZ1ZHFY3hoevySU0p9CkEYfAIDep9Ql56pdsIYhRr07MP02wpXPBnOY//fdEx Pc4pu1Rgh8CL6pFjLvX2m0ieAa/2inprumTRuQEVq5h2ketyqyTxVxSZAWkIdUWVx4T8CmQE2qiv pXkyVPrcgyABLXW59T2LFwfQxDWxKZC0nLRK8rto/gAlUr45aK9BMuJkbQbxKmwsB/2m7Vw4UppB QpFDeEXr1BxUy6uc00L3gvL6zU2oZXaWIMUIHR6HRihOyr9M5ir7GqwAiXkJnA2zHzkY1rU9u/QN lKxZezUZFwRAlotukmkQQ6tTv7SXFN6NJMQ27yhNFaifVV1/lpdjKLNluAnjrmDJxwEcygJtN/Rt 1bJ90rNP3/n6R9nMvCZYsmyT/zU7qxnWnE2RAh5b2zEvkqkz/I3Y0YReZRsZI3c4ATdAduzyu5rN 4TH2iSddiF+r5CIkjXZOmZ4AG1q5CKyQbTnDO/7LzC6eaXLipyAhy1Sg1oNnJctEMaxPiQ4vK5TD Xy/IeksOflwI4boMSH6xcMeyHTz0bN5ctlqkHEjDhPNm+QxD1UHex77dXo0cdqlQIQTUFFHC59U9 lxd3RYteF8xaqPJvO3LOT1bwQU+4CCG/DkzwdPa8dywHV92hkn+aX3i3IZU0cgNw2B0veQDfxz2P Hxhh3mMDhbtOH5xozu/K9r26nTTyliL6MEcBZK/9YfqgRtDvv25wby9ucfQZNPDgUcuagMBkYEr0 ofMfnXGe/K4p4sOtCQA8538w2Qy6LgDAPg+dJj4ZzeQmEEpOFh+uxx1NAHYlHvMG9NpyalH49ntO 8MClgFW56KxGH4R+DLXY1ciZq8y2PZus1qc1NlCHnV6dBAR2xV++6sE8kmx6BZv9OKNZ72og6S51 xFOkAd3+WgLechTDpzBj219CbfIKvvL1//ZE51Th2uDWZRMHH2sMsZdwPgbsZtN+Gv97QyHW8HF3 SgYqJLvCMczAkAzSX8vRxgT6u0qgrUKKPcDDIHvTgsd6MpVnHGGm9ocTcAcXvqiYUvl8ls0ChwAX 2QWLP4NuK4NRykQ/hdIHAFfZ1gK4sWr21HxGBZAgSxIzlMtpOmCsdI/PWXI0EY/rAwv6nKjtjeS1 DZqdywBDcyXz8EvA65WVTO326/NitSEFiIXONx9ErPkuUSozHJc/S3MaHIqKl3Dng0Fs5L5/wqiF 0QtOGqpFYz/vueX+L4Esq+BdDLG7qzoUTbh2s7rLcPhRT2Mrw19sx0MmOSk1YwgPaw318I9hRIzW KpX2q1gv61I7bHOwvVat2JM2I9EamMwLbRRldHB0eBlemUUtRT/pRCNVsWtloeYAGGUD1N+YNy49 H7WiBt8BU+dzR7Tn7NuO+s9NkzGNB6DkswwO4ky6RMsSQj0Rh2c0qHkdgf7C75Tco5/8a+MyYy8F wshWV3H82GFvGVwkZI19Oa2m6yPWAx53JC1TcvUyCfATkbaxzQ+IRq9+A+6cKD8HwfzKoqoBtde6 oDdGWCs25dPvf9c1W/I3wCNwIscBpelFMgEu9uDlc89ze9h96TYCVZXdpBazP8U9uQvN254Q9M/w FOOomAW9RWTEV6h67m7CMTkd8BKughYlDNDqbMQ+luDfNNkpdyGhgMKlIaFG21JD3fpiOnfFM0Qu D0WTDx1G81r0yY7/WKVFrnCZZXPyv1mAhjQch71Bo8y4eFRY9rzrgISeJJslqHzNvjNQW7980mxx 5ViQAmcmH+EEVhMKDFp5rHB8E2Bhnt+25yczcukO6RIHvS+LB0hceLgh20o+MT/GYuTduwtFZ0H5 wlk0t/t6dFbQCVf3/WhIygdaapdF4uuhneVc/AHUXEzS8aFSxZ4Oi+8++6Hqu067yPNu+mKQs3mY 0e1rD88FvSjS+sRRgOtbT33LHm4jiB5ZYWX1RTcOwYXTXnCw2s9/uYF/QV1HVMH269ZIjyLvWWK+ Q12YpXE+auPrL9F29XXoGL+RDIrUT1waUUjruBaHkbxTR1UQxuvrIxdBAIA4oZvhFF3YJ2wtcz+m 7hyAHZxG0F3+54Os6g4MQ+9m8bHZWLiHnhpNhsrUJeCB66Wylx82g7stIN6L6OXMo8VhNeY84BMu NayLxgyL8aPkzluUDJb535P6q6quaiEFezt/rXrLkFj/BdfK/LDPTYpJMPCsvjmG9Ho9TEBS20Zh 463xx9zLcDizsQlUtrh62kJ83Tex9NlQ+meaQ3rkq8Hym2ZgxZwh9C27Dil/8xJCr52uUKx5lSVn ryTrRdTt2SObsfaHGHoNZJXzeFZh4W2UpYCr8wkYTV+CnevGQTw9V0hNSs7Yls4fx5Qh2jkNjD4X c87k2WRilCkU/2fr8+z8kMhrBdLfJUItCb6CuvbjpGsqB52mZ04J7Hg6rb70o3cQFewjbPsOkp/T ue6Lpmw0Nvfn3PnO8r0j+XzTRgV5uj+lUSoHI7GkCZ9hi7BRvSrzfv2SAZ3H24eeyB2NJ8plq3p2 gNhxLMqF22yfifwAkDfBuoSwMIHqD9PJwHAX2XZn0RH2XdThhtP399XQ6E5Nl8+i23ZRkHuW0O4Q cvp1HOsZvwA1vDTL8gjEYzIj9X4jYjuZ3aXy2rLw81SWKjSAuma42BmrxeqkUgYxgug8voHusaDI Vdvu/579wO5tgPcrJaWvvtXGQ+uts1hWFkP6qsFuGORKBDY9kNAR1Ay/qhW9LVap1DNiz7HWe2FC JT7GDf/B+JuAEp+QM0rX+o9bW0JYzTeQZNbDp+V0XzE8hDu178TTF0ub7iWBwq9/peJefPreQK28 O76g9DdUQ5fnaELd+ln2g/l7rq/hnyBQbWc2yw6Erw34+9uXvX7Wa8Kb8tEC/b5VTrE1xFyvXr0U BtMS3wZIneycyEkQLgjtlnZ289fj1gBbg8vwbzlpn27Od7h0BJnq5+NOayjoC4F7zSG3aow04CQu cW/tpSq8q709ZqEIlGCnR/FZJKLvTyKeimyxOgujo7GDJMmjkTQVhbn8SPj3dJqDIpR1H303W1oc JTXF5Az+uMZjREOYp3bXsM3U73CeoUt9ZJiY1GsYJLuLgeztOTtG1+r7R7WPriszEk6M6avKUQlp N95YcpUBTTPTNNNSUjUsz2CuYZSCesUNrel3zwwre6rXJtoEAc6tkJJxUnjAVCT/tSklaRHPvFYz 442GzDsVpIsCs9cNT6T6NA0wejygO0UeV9sjbNcX5NDpLfxSSPqgclgUqb6EfR3BTpoxfW+ENjDp LD81JWgTIooRjVt7dXawsTpG1Y+Jk88rf823M7AsRW3go7DPI+4cMBwZrnZK7VpUiSKV9qRjU7tl t4AOAdbEBgF/eykfHkoyxdh3BWKsx5VVcFDMHcY8TMqUUJZr82bhDfF9xxHAbO9GS2+fUfLoDPNT 68uXYvS6Es6PkDuAN2GVydk9r1iiUlA7W22MEexGc5T53AVgmUdtHDpXk/GjHHRoCtftYH+qn+3F tI34kkZiVFbeHOKMQEy/6DDaLX7NV66yBJZf5s4gxCY/qn9COOywvWnQ02ZNqsqNywLx6TtbO5Gn RJL/5JkRq1kD8ylSiD1VyQ5Fx7Y9hc/e9hEFkJGe24Il4rTQgCKb/r43qoiSA4q3/B/OuWhyeceX 7HbDj+Zsv+DWS0FVDxaPFcr9h5od1zukwI9w2qETcakq6LI23AeHLdiw0vB1EjPwO4+TNsS0D3bC gjZHWTsRqHfuvio5v72+TnHV3HPYGvIPeu7xeDSFm9yiSRUEejmHIaG4pUSvGa17D/CaVQ/DmpKE lXzpKMqzj3pWbBYWYp9hSoVD4Wsnkw1HMhyfBSzaFGByXzFv3np1yO645NA7GU/77Y7jvOHPsCQj /gcwUFbqDcYlUA1rxJKpDmTQu3RiIaxI/obNIPJZ7hQKSoRYAVJLchoXWLFO46r6SyL5iVsVfBnX wf0LmCU5LgMR1s3gs4rJyTsDnhlWXVoJkRaEQw8eD70h8ppa1cirM4aGcJiQRFX39h/5bvMtsEYk ixJStE4AoTBK59EQfi5m1M+gFOVZ/vQRfGHMI0MQ6xVBoGTKdy432El4BR0JnagOkThbROQfQeQX b97F4cwiPjI6G66awm1Rv7Ebc7OdeN9guJ1oUwRvVZBcfdxLV8oWQeCjYlq65HtgIj/oT7izngQH RftDGj4gCR3OVjjKeWebVi36vYmseBnZAZzgn82keFilAujllNsnjrOtzEJlYL1wZayFkiPSiUIR Y/x73KIuhaljPdIAQ/0xUXerotqH+GvV4H9efxnr/v4qOnO4QnHPCo/PTwz/zh0JhsrwqH3a8R7G c0zWkYsELO1daIOjDNZ2+YdHcWVuhEB6isQo1aWy2Q+HI9m8ir0kF2+Dr36uWuiqnJVZwJcSHwtY 7SGHHtE91tGVbdM36zSaenQT2xPQnP6OmyXo3tewcmn1nQu+d5KmLQ5PYddrMFfejVEdfszeI5wX GoVGEBKuy2LEocZYM7gaOwpn5Uvbgl/eSNOrup3OZC6B05lAAtxKK/WS7ui1qMGVPt22reS7VfVz zBlzYEkVPW8Hii5uH32zPiOcntupE/DQCkleRsFF6ZcQygfF6m/s2dQKLTPnxWVXL0WBu6RUfrIP xn5c8sEZpKg9vaiaZNW86IOXCBDNiJ0jkLIaUrTgC18doL6c6efIdPj3xTk9hRg/O7WN5bn8ma7Z FCV3CkMcGGa9ziduBnZ3tY/WSutLDaVWDcdsK+il3svkvu0BwoBkQHfGSL88XYjZCRWIO75PR9RE ebhcxwS8v9QARNJ6Jnqir7d5zXMLhFkqba5cholsgKgGeSdUaKJVmFUrsTfnmsMJnLuDK9txXGWd mFQ71Ae6iLwY1k0Gylhu1BBrXNvvvfV3TnFTC00CF8s0HQb9bJzCHiLQg5nkFFEiJZTE5o5b1sKW NjEvyHb+LiSSC2HMZQL/UA98IMvFeWdnxXkOsManQ5aOkV4ddp/Qp8qvgREQXxPShi/2xRIRV21a ajdjvKxyzZQGf0TFjW2/6EQ3uKGCurpwixf6cYayTUhnYmPg1OAClp9lQRbE97qyfVBgmZ4+VpE0 LqcdYby05FaK0djpzk/P523sQ1g9jdTCL8pjT1EpfbI+GOOBT0XXpo74h+lJy4DijYi3l0ZDqNSX yeUq1S9l8u+qdv1DTTvBy1HWfyVz27MM1hCYqnaGBKJwO60md9VtvKjogCjv8MF8zTciKRKqX/Pg Js1euJiif1HcpCz8yhDklgEMeaJMUkVDRUQdmv0Citu4RvGXiF4HXlLw10bpZu5tqctxcPxxeHr7 hN4+B0ysrhlw52gu/ZD1rsgBtQvm8eJ/tlPyMP9ftIyjNqqSaH5jeAp1d7qzyBgay97PleLvDzgH LH7VDeX3rp3k9t+AutsX0/z0o7OLe3WCDt0Xws2jB4+AYAiNvAY4k1wrtf4Lp2/XN4miS+YRXtb1 36ixpGO7uZB0z8k3RHHmXdRsNmtmp10NRhP7mjV2DwWjPT/hyrOlwK5svcU2TEtpL19+k756SNnk BLR4A9/jV2LzD/P0nrxTT5VMhUfCxoJGsw3n0kokn33uIO9OuHH294wDJ4No/WQzCPJVJ9ea7bcJ uSf7oC09rzeoeXigauvIDNXlEAnEKHNX1XuPKqP3ExytCkrBA2b4DluNhKoFDuH6Axygs1fB5ezN XAINtXIuHjqmSnj0KbqBFHjVTgPv31c0zbXDz/vrBAL3dLS3aXOmDf+SpZzeM3vwMDo4bE2cBhZe dBLMpqU2JXGTL34nDcXC8FOZMEvA++RStcEQsP+XupigK1SN53eNq9earYQ0uDawWmCBT78E84IS EsVLWrfxz7cZ2noqRc0DGb/Fok/OVZgzRfbuTz/rsQDD5wskIgv/jOywP3JsM4Ww0qoBkq1oEz57 X+Z6Km0CDONgFQAIRM+niVFQMeBvXVWCcoLo0bB27JiOEySz7Z9CSrCohAkx3l/IdDgaknyy4iFW TAb57iyTGBZI87oKKdqH5lV0K2DHhn3+wIKL4ej/X62l9DrdpyCM1lI/Of9ciZ6WaSYnrRVrc+HX r3ZKptmWeviqoqpaR5igIiGSTZmXuCSw2bhSZwypQCkJ5MJZonwT42CmL+ZZPHfbCcVvt9i0UIK+ 5gn4ZldCirv0QJTFB1lABazTSH8vX6ga0TyfEOLb4+YaffqT2IEdTGPhwPzKcG4/7OWie+jHfVGW BpEN3B5OW3g3j12fu+3fzUwc9h/ozTknvbeFEoKwfXct7Zz4pSECLMcSYf4NOJ7dHa+/TN3iurcN FvPQojozHXRT5axSheUxPvGiW/8xqmXgDoFeoGr3IJTqM6xX4VDOrpi63bxnB+zXI3vXu26JydVF O4WinZ+ZohAomQuqF/wD+ZCiU4iK5bjQHDPEvIe/pLeXKJs5QzJg2xN0Ou9g9YHujBBY2WeFQz+U XXvT15EOs3Lj3NGQuBUS1WMCHGeUs2EMt7ilgSz9lD4wjimiS6UD/HOJZesW+gywvaS7hiKxeZ3O Qg9LtskAR/x5CWAaT9Il7jHC0e3OrH71oGugkOEkBU8dSaqqbddjczbU0Y0T+677aOl5C9xzO2im P5t+5+eOc4Ob+33LSwG8KOESrGgQUC0vb1wmI7Plk+yGbeel21+TsBCLch7VZqp4V062CF23Fi7s 8PL/c1hfWm2WUWSfX+y4U0KvH3SKlXJ+s2kH8AFVg8RrKHiSkzfBUJULIdSsbAiJi0VIrNFe/mom 13MSNJ+tHLX0a7t9dVeFBAgVSqF3br82xf6fkeV+9TmNxCHUyXpCWMoj8jghoC0toSt3/ucWyzCW JvLQm6OR0Dpnn4/osSLPoGtBK9o5CRXx5EgPQ8INB/+rtK0xXdYVSwL7lANv3/2wZEzw8s2e9kdq LHvcEGWs9qijtqlrNHaoQYwA24ndb9TFjwP/tZeXQYLIWJZJC1OFJQ7dgfTKBvTpZ7DYVCUyeDaP EN0ixM/HLBfiBImEhPC3H/SOHNwOAmvcvJYMZocQSFr8Ph/wi/JcpJthBgOmZa6ay6/fN6aF0AQS RPsvcYkA6uC+x42orQNwTdh7ncZpexrPDTeCwek8DvOQYAzY7egtwqtGmjfUnVxv/ZBe2Oj+jnv2 Pi5vpxcR1YnhENCfLu62lJwPAIMUqjrf31Of6LbuPh5ncivVZ11/J8MAnjV9lZZFQSg59ToNd6Da BUthyVjSb+irW6olZP9z3qlfkr8EoXzSJw+BCAahdO2pxQkYMetyyBM+LYDXX4xn0YcD5I7hg2t9 5QAgPOqY1dfmE/R9x09uzXlXF1aeXH+G4/Fc6qXkrRWjXDakSYsF20T1CcfZ5XSVsZuJ/c9enV5W Hnt6vdyQYDwTwpakkMUVh598WBvEpX4rSI1tNK9gAcVXdUsXI2aJQaq+Q7YhlbWXablT7UypxQxU M32MorDxQ0jjPFsqRgPg3t6YVdgiq8LmhYLPbKOO7mxOBk0kU2Z4PfkKro9GuYd3ttVzD10vo8f8 p4obbxd95E19Mq54iIrm5r5ze3gThH4yvvmZy7699m4El41qxm92zowdCab/c0z8ifTOuwJGw5my CIyy6ogOWwFYIwN6v7SCayvGS9OTqGuLSlpsjdy2SHH0gh31UxepsOsivhhHy3ipNymQ0xpXSJWv Jx/hz36YAdrcum71jCHw5Axf5AC6arSFQ8ifXjagf4/tgTMfBxfBaSi4LZ9IAx7gQ3oFDnuU628Q oMloT5KbskXWcbmgIKjMTA1rpByvhOpUOG7h6pv4iLkUsrdrV1GyojnwMlT3OH5sbGPARoTCYMqt qVKRpLMdowKixUSgprWwrVcY6IxMBhSc+1wpFslUIXPlWNcTsvb80qjPJbOWQKgelsyCVYlWvbK1 Kx9+6GwAV/2KrPhyhQS3+LppIuFSIC02kvD63FGFF+8FZ5NdO2iER9vMvq+SJYlA4I7jUb0tKEwz ZZF09Oomn504oZ+zSN1jucg9h67Sfh1XcD1jxHBjXJBb71HGcA3cc+HWCum8WC4EFvsWEK4JFojc DGKGZJofbg/mhPAKwQxKuzJ3MqM7A7fDeyCfyXvFEMbwWzcn9lcIUdoODlWZOmNjXycrUrUNAmH1 F4WHbRSxi/6fn6yJO6Lvay4lQEkx8LT2ykmKO1m8CgqIL/sTzqVzbabu23bnA2yUnT+J4bkR/18N dR3zwK0y1rYoV4pLoLJNkte8k0RKMjKLhvZMDpxBrnZC+JlP2AdyNQI56EweOUJNimj2teskTwC7 uil7RiTPkFBhepCWYmQPSmqpLqlWoSOro3hf0tcpFcgBikBDZ9pX8H5D6J7s/XZ8WxpKwa7kKz64 qgi2HE5cG+jXRIt4lPrK+ShWeQKcBmMYjTnj3p6Hvkl2ayiEWZCSY30JMuiyUIr1TlrL4VdE7Hux /d8oMRRUNIOrDs+TQSLXcELaGe7qtYRlkpdnYrmlsjuF+Aam0YR6yeShFxn/AEn1DaoOLS0uXWbx QY2ppeadhzmSEowQ2PBl85zhjNsUkuML7BC1G4RSXxaHcF1DR9gTXdF5ntyJS+GF/pYkm2FQnk5h mvbkKZ8uf7WG2lM0QX5wm9gtVkxXWZ4LwJ3T5x+I6/fxL6VQ76VOweb/dO/L/KYWk6i1jXKPv6Ff wlUG2f3s+tkI8YM/Q09+FJVKnC2YqQ0C7MiqJJWQIAjbCZ4bUVfrKUQPYNiNlnQe5m5Ox8uLt1Wu 8UM78mZvH8OLTUs9IwkFuJjLYgdNhVx6074rrbH1C+rYdw1xv/4avEr654KtpDE/XlmOoCQFb9g1 6a2Ih5M36TimpF4IvcQ5wVAKprJbdfjNhp6ISyNrSqU5rLwAzXv+eypRFMK2yIrdMtYzfhQIzazh fruLpVnUASGW9TWcGLlK0oFAHRjAq/T9KR3Fh2T2fo+LrX7de+i6Q800d9gtkndcrb+i8Fxk0fCs kb/13H9OdKVQYARWOoT7CYBCKGHMc/d6VTcnTDgcFXZd+S4TPKvtTWENA+B76+Pfc1UTjhqArWab EIy9NBHn4PQzH1kAhNEADG+FafDgZb0iUcqhqJ1ZgMZssBrbHsJTzBsWSX23lV6pyY5KDHsnI7+C 3ojVactNevU6H6le04ZFe1k5be21s2rPYsngJUBrV87UL5bQALxY59gYN5uqp3ZMoVjzVIaUn1iK OHXaQ8vKeQfWvI5G9ncFuXonyla6K3MddPVGhLyVQ5hFB7kY3sfcQMneHo2GpWGB0kfGCGcwZrex ZnGerLk3HZpWIT8qQhIiwbCigrB2MFpCjoQXl2AZgYMrafu1sq39+db52WbLfbd9fskL92zIG++a 5OSC9jSqHgzifHaKf6fAWL764PeT0Yf2XdDR+XXPobdS494mILS1YAXgrLCHwPNEQsQHMbllzw10 OcX9qiszTjUOtxkZSPG2Q1ps6OYiXHy61aekw8eXLOx1xHoDQBDeEW3A0Pc8XMOkjhWMN8lfz4Dj 2j9AK4Ybr40HDys+cVXSYR5tdW7gPabErvs8oO5bBwx2duq/rRxs8YaRg0sy6cbQSKepiTBu1y3/ 0v1XgX1DNxOwnoKYJixLsU1Ym3TdNtqZJPzkVsh9Wxhpp0cXx6D95FfZgJJZOYv79kVSs9Xog3kf IEOav2ebcHrgU9lcP1AiqRYg3+qdIF0TpYS7ay0KKHBLSwriNh7hy7OuLHHfhpN2sJED3jTPz9j/ vEKD9Pm8FlOozUdZfhE0qt9qA88X0Uq23owvREqB1JA+D+6W/D0OAmRKX1xqqzwqxdoj9EasxUN+ s/VNa8dFg8PTyxs8rpwzcc7R4CJ3gHBQ2Ua4CN6tAk9GDZ/YXekSGtJy6WYBy76ay38njky/NXHq pzc7QlHSeWtwfH4TPPd8H1pf0Y5KqveGW+MlLrrzK1u0E5i54UatunIUqaTubgNW9GCpGf5eZB0y lPPiH94/Y/3AEDGukMxGTF6sFr56Mju/0pw04/ul8PsN8DQZdUq3Wmx2JhjRotg30PPqp2IceV2u Lqw35qx3OElp3t2SixGcfvM7h8pN0362GfUZnnMqZSYquo4LLvet2dAjiCx9q0eZFg7hvH26T+Fw VXFY8b0fDAPOJVYzkYGEbbnwYVejX5BCajmYLqTwUvEELINozu9DmPv4Vj4oC2PI2a6lKW2JCtT3 6ytr7zvEuVpY7geyBjQFvMpQ6UO4jkIkp82FKqLXOOKIZKovgeEthR6sjaz6DikurOgnzxFrPTju 5lcjS26BP2W+zAKGf+PQkWhjgkKX3l/hvKOjVL/fq5ybUWyTTYgyiHx0Fx8B0KK1P+KmyTfQEjgT 43OiwZpEsCgrdlysg3wa1ms7RL60tKTeARAKWgQk4i6Gpjqs1RpCDG3XxWbPP+9kF0JEbnqNL5x4 PaL9wnQmFLZGoWLrX6uDQCA9cv05WhhOdkXydNSY0VAr8zr8EZQhwwMh+EgqEdqiyfTh3fWX3OXD leWwpcDJ0roLU8EeUkoW9MPd5i3KvSARXLxXdiJZMcHDFsj7NQ7o4CbrVUT43S1L3gbyIgaCatQ6 CtrhA3iHEm9isqGZIT7b8VnAUI36nP2J5Dv8dh7EG06azh9m8Nrzbv1s8Jh+MsPahaBSaou/xMw9 p0YPi5gX/1iqqdgoqekY1E/TIovnIYHKwKTnNb7j5V8NKJ9UKEhqE9ne9Jhd6Iyz0ZxXJnB2RQ/2 nShnsgEDR9xJ8+OfzvAV6AaLOrEaeCGc+PRiOHO+F4uOg0VXNoKkEUi0peggrmthcs4teQUvCdKl CtNs9xc3PDavbHgUHQBN+qwYjwn5gAQk2bTs78NG+h7HyGKenk0Muo3ixQ9yA8uzS6MFvrA58i5W cDe64M+eD3tDRTH58UdSUYYUWW5IEUX+/sNvfkF8P6srCBq3eWrWAGfLi7Gnr20MUOzMjYXiHIXQ t/vecvxuKG55ktQWM4EZut9XF8ibyD32PLYMRI4UcHH2xuAaZDdjGtR+JXf8VZfTCkEwr1Skm08e mll1yk8ykyR/QSchWw3P4UPDL+dyyntaxf/aB6eqAEkT4KqdGK5LCT/szsbhe3nDJ9Muhg+whH9x Z7q1fPlCDlMKvWqmWiTpgim7I2W7PNuIzWKjt61XkieW1LnuJmSWYfsLBK3L3QdfTaDTJ3xFgtu6 IIBLLs6egMbT0jbds5DOUVeg1a7emKSzSTYjx3KOzeyPXnFdFV8rLzT68MUFZOAvuP0xVcjVucaS 47ion9yLa05LwFyXv1Zv2pvaBcBlZVx1iPgMovOQnw1D7n/8iLCKEEJXMa5MkYslWZ2xRnDyjf7M E+JUrOD1uu9K/JjeXUI1QfSKmftXbz7gkzCqyDRH32nqqGh3nfLWkU29/H+5gU3GeilfhmunfeTP I4/FJR3ITlz+oFU9mWuAjVPHekDkvZgHyL5LfQakkwWU/IlS57p1yzbNx7X935lAXaTvztaGvcfv yF105bFxE9Wz094EB1FeVU+hAp6u2dlbIHwEUBWXPrWhU3WQ7TZ+l03olTJ/gNEKonuC5YC8PnSi kuhlxHKvyS8FtnvVXUmPKsFOYUTdl6BaGWbd5zeKS7ysOsZpd6eX6/bEP+pC20j4bUEhDUHTCjEJ 8HCFe4O9yAsTPGtOJNcj8mIv925AXGaJMSqLLRDVyHht3HKdgfhE/2IAd5Gn6gTplGT57DaJhdq6 2diyDmzZzbNVp+4ICtITyhsUVm7bUy5IWmQfw5C4Visqeva8GJVZ9pWs41K2rY2AX7LxdN8NPaR+ TIYm/hk9qcMza9F85bZG53snKW3HJL7IcqaVVgexXvKh3Sq3d8GByixBfSL7aIDESlu8et9TKr0I 1n9AFo4DZsQLWIvwyNVVnFQS0gROYLwI7GZTceP34dukxl0RxGCPjONp9FBRvAjPqqkgz7VDUVdX uaXM711VA2H1ylG2PN4sDdQvE1vJb1ghvhdVOGd9LxahGor18+14XWfAyeh1FKkqBecbdn5hpMhz lMZ42NE13JzOPHwJeudYsuSvOICWB9xjJPlcTkB5C4ujndeGnsmost0H6VD6Wjg2KU83i6kQXEHl lJas6WF3hRVDVFnZKwUoaJ7e7aNQ0nYdVh/6Z8mIjXUD0Y8ar9VHayfTmIb9YGA5WdLWJRhRe4GU 4CYeJzjv6JfvqsTgAICY1h/N69C3xXBFX3/mBzlBl7co5zB8TTY9u8OQgEtIof/UvaRXFJXx/TfP 7uRHErGPLGfDYzUCzS95YoOujORyBL2v2xMAALt5RRTKvy/yDJ/tGhwP6E9hPpxaDldIl/AMnw1L caeMp0vNIgNDuZdIDqdzBujJw6XiaHC8xc1EBWwmO00qLsugM3Y6EZZUTMPdenB1ISeS7Ce8+oYg P4QVkiZUEtMmKEPqYvlFzwQh8OMMctGPr+qpM3ipmgDeiLAtuCWQz1Ti3mQMVypEWWcnVG4u/ZEn z9P40eT1mylU3u7Im5jceSso8uvbUdv5TC6pe6sWsCAWimerhvKKaoTxhJN5QrD8Rf4tbLPIna53 LRqeTd8351CtkHHMgmUkV7lmKgShtgDHHZeMyxQpKf1z91OOd0VF54rtUQqUDD4HfPpQe+oiva4u Of+GBJiiXL14aO1qERb+y1J5TZHGuTBV7q6QL7hjDMdfv5baWeBUGEcI6GZnXPLZcXUr55SmWSS4 PoUxxP9AAn8O0cmGOe58iONeKHv5cVNh9SXGpuTcUZf6GNcl4fGdMg10c5SIgNZl9ZV5I0Mp7GHV viiE+FGS+jQVgsnDbEL6qRyfVgMrFwVH3xa5/Yfzo0SRfFcw/4pSO+97EtogwPzeK923LJ1BPPhZ rPLftm8pFXD4ibW8iUI7VAzOAy0QTjkrK7KA0XcaUo6WGp9At/4Xm3XQ07tF3U1FKf5iNIuM3wc0 zjlAuqlaKkT9awEJsM7DZreZFWDjVctmFSWlIO3RAzAEt+KtGk/EXOyy/7FlH0Vy1He0UtiuQ0Fd U/wQEVyJimcLJemexlD3eokvGiLwXjzrwQ6HmNKBgaDpRojs/32ZMn+yqyBmcBglyerqiJuEoMh6 CuaX5sWOopHriiYZpeM4ckpisYmwcS5+u5If1OXXLfYdOJ4dxrOdlt5h2+nrny+KoRZedB9ViKBL TysKMHl1DERORuAfe2AXyeB08DrfnXSFUwO0xUXeGhBJm4m9brd8JdoNgRFY71O3SZ44WFoVl9XR svOoFtSBqHimcWdopybuDHE+08LVV6qtWG76IzmjNrCQbYV6xGzMn/iL1S/rPFTltHADz2doaCkO b4QPuttNZhGYxuLI4CqUC7p4NRXkIht8fxcJAkf2l6SG5jnT4VDeAb0OEaUmrrv3HE6M0qFdW2QH HNgNWQkO72mObUfDYou3O9QIhedP/4V+gzhxs6v7PYgJGI6HDEBaT4xp+Mczls8e+zx37HZx8nIR 0CVtPCRVPJm773hJ8TK4252dneew4xNgiVWqOt282QvxVrAxB7VYdNMK5Q8BmMIwX9vt4XM7dq9f BNAb9M4rZozVttUK6J+pDSQlmX/OaU/HaoQLcYDryFq1QgBN2R/xJox7X5DkO+IGDxgKkxiUBI52 PrHBFLDAdtM3hbs7+CDczXmx2DHtKxVCGG2qb6h0XR52CESwkvjScP4LmMea/W/F90yDM6I7tDFR FR2SN9OrEPAbMUPLuVkjoUJKj17vbLwYS3/u1FyziQTMiACkZvQpWyMORpRtSmuv23Hj6wF/sRKk XA+bJGFIs1xO8HUaWfRUkWR2qhzyHyGnITTsfTaSHsoJHeL8GDqoHrxyIpKHbat/idRYfG6ahYBP uuEZ1Eb1B/0WhlQrFam8jZkhshg61hyiHdcONpIHrAMXOYvZQ8Yd67Wr0fBAZYQi6ICpmX+vB4cd nGwmOJJ8LscIUlFCPcsmmgfD3VvvEL5bpj5zqxtF3QegUzTXUf6iWIC97mvQadVO7zHYclEosd7p 0ESrfT8yW8POSvPtWRgQ1wxTPwdpk+4Kjr13kppWwyvk0dgawAVLFBkGBMxCZ4TBabR+1Trrffdx cv39qio39/NexKsOnmENzDUwDZSyDFX1eupwnEUdGDKFozQooLyNyCNeEkMVdwz3MxQL8dXlVxzP TcBIzkYX9f9r/rDuZp7Sn2l/dZRCfkb4zDMQL+Bt9zpWK9TYPeAMRuTc6FVbkK5Sv+Ry5u0H6cnG 9KvSymICqvmtWGZK5+ghF0+xaKVKqkt0D9gnZ5G9/vEjXdg1MaF/wIomJjBfnLUg3h/3AjxnYMxq gXNkePdDkxenPAoeBW9xdLUqhJgdRsTNyJiYykg7RnOo26naQ9XyLsPZ+XDuGBnxSi8OB2+baqwL oHwWxCdtFQjdxNGapq541Y5N/osAiz41Yj1enxY/HzRPcgQTVSU3pFFXLh1Pk8bzVeMr4PLN1DYO JxDCIoFinhh6pLtil+AgvqU6ewMkkelRu7eXEX+j3MfJFhEeenb/v8Vs6rTv17FXhSeRTB65xoIv w7coEumoxrHvv6Fr/8rTJLMr4NM2UC/rPiEjjoDAaTIkVszglCChoqQcDxaszCmD1ICnsjnC0662 +jmJX54iBcoYOnQXfjvgtOxa8jV+YnnCT/0qKGkw2d0oPLY63JSYKyFDiLhHxMTiEBx23fTXkk0B qGa1GMJJhshnAMxWgC+CCqCIfZ3k9nTxiHOS3DSablSDx9kaUWnxSxa8H5ic044JA6InFQ6rOSUD m7uxBJxs47U/c9h4mnhKs7K2y8YVPy7Xt4o3FxRcj15e21Z5ZDH7KmvxQjpmg/kNelAQf6VVNmbt meg8hah/ZxrnPPdoMMc2oXeRvU4BlJnMDx1Q84KdCv8hetoZL+J/wLrU6d+0PnW2j88pQaKuaqrm AiKCAu0U2NK2qIGIex7Z4puzkruoqv25kBksiz8hS8YiFnrq96WxGLj+LO/aOE6ozgwlYNbCXLlg dxVXcNIwaEG49YvfHTu+MHUlcXKj4c7K6vz8TnC/03La7EfcZFlnGUzFAubnV7DW0NVutm3bf5H7 asRaGz8fM5f4nEkFvzyIuCo9FgCmtICoIcUqGggZ+slfJMap9gP2vNbn47CWPKRb4fvQU+NFIDaG 7qS2ATZ7h9BepRD9OsAmC7JOxPlvMFZVl4kmTAlVgQHinFJGby6cx50qlWfzZeiEgNDHz1JaWJyi jOuX+LRjO/FdjpUnnTOhQmDnf3lfHZ40dWgc1fnC4xG+9i1n4+9Axxgs8JrbVRGssHVA1eJQCl21 qx8USmhdsmtdNUL+tQKs+/YSDBxn1rMzN4KTiraW5ZPIc9SIun7Aa+XQGx0Pkgk6RRCPgTJGvZ+d tfKkTDJwirValli26rMaL5aLXLkgbzcz//FP1mjWE2TW53d0NJMGCKZWw6BdVCYfW3DHOhZjCdh9 hOlLBDvh459MkHMYw8nuAjZpB7re3i73/QXYFA1SoJ2JlhF7oTfv1+XHTt/iziFmjgeq9Mxs7EQZ j4Ue0oWPXd6cguoTjAdcC2pqWhMVixnOdoz0KTyeaIOeX1LxmjpOhW6bP5DI6VKcTQPZJ11JF4f1 tAGMMrW2zDKI/iqbH5CNeAzS5OGVpLIaJvgtlj0Sty0b9yUGd+Le1taSixxWU4zTLtjbzvSYaY6t qGGOre1GttadWk3iE4hlzLBw29GJLQZ2ru68Bf4FnT0faAMzmipTKBe1R1SCW/hwmtWMRAG4Dr/f ScOABTku9VhUC0ij3AIxhz62DjKVrsDXQPI3+7M1hFSPHOfIq9niz8BEgAE7TJE/i033LgDjt+mT QBkIMtfuEOkTXXDu+77rYakxC1qx/DtsnqKwOHAAcXV5LzWJ19NNVSNT15ovRJcotaXU9Ddaa/Tz YU7ylF6Q3diAvywrIgon6NMVccz7IOCd26R0AtdczifyiqJwBxG8MS5CrKkkMes7JpWt7UK7oIeC eLF9rZAQFK8T7Mim+ry7T6EIvWOQaCsICI7UaoPbLOuogzzQMVEztn0duhVRHIcEnWnHe/OWDrFS 5BVfBorWISmTd/6VR2CWAQuGeSMQ7Iav5uwtUwLb4830jtqtenZO2f6HrB9k6IESwo9+6FF3Tqh0 TvbkBa+9JLofHICPJlGywit9cjwlUm0/DDgll71Nfkx+t8lAVAl8F90GIkktQYmBA4CRIZH7XyQT vQ9p12q4YQj+/2u03X5KsVP1dShJSBbt/OcS306e0uxOvreaieGGjvP8ctc6QDK3Pa22JxHfttQa r1jroQraOtNENsxDDQZXdIsZYGNiliTEl49lmA5oroNbW3+GA7YPf0WbmKQbg+xWe2D7dO/9d2te PzUSgDhL71WYh9O1X2Zm3XgpTHQ7sFzHA9jfnCXc1ydd1YKtGFJlal9hbGLZr0yazrf2KDhIqjz0 FaD+6eGMmAlsM3q6636jkS6DqyFEcFXD+f9JyRiThqRnBISRsDC0VMTmVPBEjOkUybPtZGvd2y9G dIeUg2ovaAcCieFBM42HQgREZxTsIFMhdilNV0vRwMRxYJty3cKuUzcuJTGgIQXnbrFcu4Ny+VYU JVe8rfpaZL0ILkChA29wZEZkjS94269i9Sh41YG7ZHU+KRbG2FEyEpaa0P3zZx+ZxpHrGSRowH+h QzQd70B2YqKP3fM7Inroz3aJ4ohrJZWf9Kwi9y6ll1qxpH4KIbi/wbwdVKcz4rTm7+SDzKoCjv9s glKvC7hTbt9Wl0LG2VYbqV38tanvGSByLxnl24nykTg4VRVemKaXdeUsG5PyK7YR724rbXjZaRgc 3uddMvAFqHddnmUYfbeeACvyAZ4p29sPgStyTMD7MGWe2UTqDBRvnhMsI/tGGMDQxHLx2J6WT/Q4 yfpuSxbrTFF1UgUGGds071GCQXBV5kLrnjM+0prZFCpUJejuH2+Ac5rh1Md9jTr9TSYI33vXn7lC kcrgIoOX26zo190a+0oaJK0ImO+DcSpmlsn2uqEpUh8xGYWQWVeSP+WGiCPC2ZcxqyMBucZ5kTFm 2h/A4DOz+T3UC++NJQUWUXhlkK+Xc9n55U7eQMr/54bAo92xmMjIlRBxOceC8aDdz1D4YGLwxzuJ hHtFFI/yY8BwlqhCWIb0An2E51Q9cm1W0JfhlaGnrmIuyoMIK0vjcZG3hWWwOiWGL4jJfetgX+tx uf4Yup2VH6bkpOuW9jAOebjGn2mm9mDxmMkXinnKkVfNCOlxCMc7xyrJ4a63p90RrdAR+WgHpdvu jfAe5+elkbTuL7XtJQiJF1JjBlqq3ZKgD6JAY1XS59Pkaumz6RpPl7Rn+ansfz9JCJBE+e4Tfa9v PIqEnRnYgbwB7MuKqW1rHq6hLk1ebhFXQIYc/dOca11UMtiy7nc0tAwF7DTxVF57ZuqWvBOoSOBl QxEZhmSdoRyzsdXIle3VblvZYaVRNz1xvMVNhqxIZmMTN0x52Qc1eZVkcMVlyXDXIBwi97vZdnjf PxZQvt6U5sUGbtquSIbvm6qTtmhNtiVJf785RRQUtrmA0kOz+Sp2/1yksd+SI+ZMgQgTwUtiLf4P NwZdT6KPBofQoA94WSshgWk/OSJhGXC5v36ZpnTaVJsCndu1u/apLjyJaTRqOyO0PsMFrxt4/hmh REPz4mB3xZlcwf23enemQzvUYGQYHqp1p1SD9LasBqU6aBoRuei8mAuWpmeY/phNPTg+w+HKnWTf 2YsTpJ2jSBs0Desf04Dv9X5VhjZiqubcRRGHrngEQgk2lJzTY9+9dCv6VrW+MwS5CfSHZ+FxnKsk 4skSVz9uzH8AkgtVZbpYF54St0mM3EnL3m6w6VL0p/V0NWDUgCXc0UB/Q8OvLM1ulsmDFAlaFB5k bQCpe6fcT8WBXNrXqwb51Nmx4cFiYvw97O10dwMgg/8kGOBcQI6PzJBM77npaOy8fHNppnrnhdRU RrAm4ywoIOXLwX6rAqELvuq3TmlxdUdUD0FOL/v7/t8ukAETPxPeufpXKG/Xblh8m6GKhPq12Nix mh19qzJ9CWIkvDDmdeDZpPxiBVJwqVeBRi6fwac7HsBfahtOqeozYNBlbQhVHVNTwC8hZx275/jN EcelVFZDQ99muBHkPGSLrojq9YuYjqKfSPGJSdvXMeujQfG95OeEnyfTBkfE8+iVRU7MEQv6XBXW zO6iPxmGPURneoyEd74bOSi4AqDkob8n9MdjJC7qb/qfyw5qT9Bk2h5cYVGHvyfxuFAw9dejYhqa vTf0Q05b90Od8KC9Vax3F1g8xw2vZIby8MXp6C24agehdSn7poR7ZGmaLGLxbwtxs62XsSAsM1/Q HaDwNrSYNKkjYnXuif7Npo6swcs8nMFcpKsSvRYksOA65Wqiw/I+cXjPADDXCdHB25vhW1NJuDU/ F422a+5d/6kw+cieHtJzjKlW9HZm34NCEx7KxoOXaGi1hVlMGgwss+o/BQETkc9BJ4XNxaCThbUg +BdvMh/aaMWF07cBMrHJLEj1nOeI33TjKmmSt0zSvUk7k1u+1zj0OoZNl9vDBK5gukb3P13kDXVQ DS8dd1VSoZLY8WPIxzTR/TEPoQjTQcmr3K3fg3GEWYNTPjMyv11osqECfNwAqdg+XlMQvjwesdFW WBwyJFt1c5fWEH4LIWQQKpXdo+ci1x/QsIixFScVICsphhLqmia0mR/zDIv1VtKJNRIBJV+M0vIM c/VghBZkMwntgGyq3lg9EysaOv2/UYoW77OiznDHNB4iODF0PolRbnDaUdx3i3UP3MAe4Bj/kvxs d6mbClcidRPcnJbUsPjzP30JqwEmOJVAzTHgo8bHADM2n+ZvV5SYyZvTnkmRrSN7jbY1pf0VEFwf 7/rUb1XC7W/dwZCQifVvVjmgNZX6l5mNHvQZFgSQ5W/mPYQQdcK57TWh+RblrlaW7Vjv9FXty9M6 +tbkT1E6jyyEFY2vra2dLVRkShEq70f14MKsinFCh+HDaL/cz1jWyYidt69ZuUpAjHPgR2V3uOJg 5WaaVqssETdfLok60Fro/KU3FFIaUBGA+BzwU5mjXX/MSkvmNakbzG4u+zpieKI3/aagug8sr+GV kvBSSmYuH4Gh3PeAo8rZxvABo+JmsjRwWHS1Hr5J+j3fO7UJFLcbWvok0H5gX4aFf+MOJfsrtomE 75V3Pt908j1XkUe5kznFkMHL/fhxKVkJAbDaDOkEpthdoofvUNnmxZO+Tk0v49nfZO5SJRXff2yz 3rEOM9/13GQUC+qjqkkO6RxzMsN5KEv/jaxuyNU3pdKoDxhidWNYRRxRKrsc0/XPyOzbgkUheN6F YJChK23Cuxbf8TVCX0YAJhcz6Hv9EkzJDh2fAXjZOT+CwCfKn7HtwOKsjCPv+CnP5tjwjmExCM9k JmG9y7TJL2p7xG+9C0XB6XX9Xhz+JRL2QSlNMc7PmuoXiZFXHbht41uI9024wUkcbwLg9KWWzyZX 9n8z1cU+i6bkd4mEIzPriYJLA0d/hwxFkpZYI05ClbeN5v8GMYhiKwb221mvAkenNgxsvpInzZtl 3FaSTEaiQoJ0YcHxL3cClUm71pE0AKOQQhkWB2glb+8nAfxcb7MYYC4n5tMbviRqjhCXXGLcDGeK ralBjbLrQNHu/VQYRDISVdwBmVAcCgbZlk1HA1Ljau280IlHs0T51R9Na+lAZt18l3ewhU2lHC2Y MkVGUkEo82rRD1igb82OiUzFNPEXnFHlLlZRDUfmswmu7ixrSDGu1Zuj9iWTTsTPqK4blQlBo/+s v+RCc1Fi6cIJKXbZdzPtKpVAYPGm7aJKpaYV7TQ4cKtXAkoonwck0kzfS7i3W53OTBjCrWgdCpSq jKMW4jDq1gdu7vwACpnSWOHuG0fe1LyyT7V6l/bdg17yWTsNxZ3IOLehuviLvB3DAYUSacoJamaS LFKlKD7ObNwXIPbLVcWvplpy76dMith/4aO4dokS6/hEjfUjEgHeXLNAgzvhjmIiKn1dC4v3H95W bWq4on1R+jjRtjaSsC4AiFlaWj9jmfMOlrYFmw71uaqXe18ZS/K1Z9p6VCiA0lyViVp8OxjTqsIq HsO8vmDxXJ20/ROXgXG3K18gMvbBhooPtnS13ijhKguNKrw8yryuhroyiZVJZIu7CuO7oyO75UmW DICJin1EZi7wxrZM88+eFyL4wyKi9st2HYJap60WzPM0MvhlaTUT9+6cThLLu1OQgM3TzO7CwXJ2 NzoHYLEdXbB0/oMmArPcOP78QQk1TCafcpUbmzEXcIWM7EoucqfMX8OB9C3piexkI8odlqkXNLPm r96IXLvc2k0TqE7DGZxMAbtgGYtbHtJsI1wrGn0lFpFe0sqcaCwMV3nfzoTBgQjqlr1apY1X2xFz Xfyxh/mBdAK68eLFgG5WC+mgUvBo0KlodQT/9wpVsN/MDyDZMHbT9YtpT4i2CgnIqGSVJNH1VKer c2feMAlV6K6owW04Qoml7XaaywjC9D5fYt6Z1fledV6B036hwLiOyxDqPW8vh4qPtBd3mic9bWlW 7wgrrVTSF2aHtILvojTtcxFIrQdRZQp2seCRWbG2BkrTv3/1bKZYnGQeaPoJ8cwmNqnnaVolla6b lUsQOEWia9hB2dZeuE8cuwBqhHcgVoVvvr6bYfCUvY8Q3No6t8prA5eH0SBMStRt5cEdzz/pOLdI 5R6hEOMw6JtbUfYBLPyrTmxSPjZTJPWdRQDzvIi3z0+Pyv5oIFxbSjvT9Vgz5+YJuJFTh0rVfg+l 5DDQsr0aEqpBoajvIUfxU734qOF+R2c3uBoWMNtJUdYn57ygEU3MeH/2MTutznAyClgNDWTWjybg 0tTvEeyV2mNZaQC+nGCAcMqPX4fmU9yuasTmHcuo/tLiXZxDE2heILAzPogw2fCaA8Mbcj7q7qQW Ut8KSZSNTPiLK6lxSnInN/WYWGikumoBf/w1bkSRgmjhvtLYnKwYnuBrtZLbQ3q3gMrK9Om3J3x5 FoORawc0pin4AzVIQQdWn0Wd0E87+lpqBzjh0tBv69gzK+jfpHDlXnlZFqrDh0zfFqm8nojOe9yY qiscPhyp8ezAlgS8tQFR7pTF/ysS5udL3GVEEWHCfc2ylNpo/vJodv04tWLe0iW7rRCDcbSUbx09 NMukphcqf38Th+uE8TjBENAj+DbwgXf1/M9lp4dh7+BnSB51fsvRIeoXaEtAAOYMaljNjUE+o8Qi 6GZHX8IeT0o30xHl8ST/hJ5c5z9g8Hm5n5GAlhXn7WXyNrtu4qREdeADPOIAQi9/aN5Fiol75Eam fYc7aVJwu0SeJdWr0bU4xhTmNKbDmakaUP9SIaeR0ehoitOTkizOLpeHdgoRg/64c9SLaQPsCe3I ajfoHR8NUe6wmEVSHVco2STg4EPYgqlGx8kXUquWilIgKhdY3MUgn7NNPOKR4IpnIVyy1cv61tqj x4Pp4Bz0SaBcEsOhuPJNJc2cVR2kQoHtrdhZbcEalbzknYH6DE8VOom2xW+2AY5Ub3vyQCbzbvJk plWdfFaFqQUjcaLHXEulCNE6D2FMhyV/8PmPPuXh7i+vDiDv6pUngNfrWXgP9SkTKhnK4KSyZt+e EBU1QO+nGhCUJcbzi60wYvswafRk5BTw1k/6fDffzT+o5Dbt2Fm0yxJshVrqMvwBBrebEpWeL3gf R1BqbOihhyZvklkwzLChYb6yL1CaB+4LAekiJhhZDRLNP6Ek6PZHoNOW0/sjC/A7pPreTPT97yw5 Ut9Y7FWKji3w4nLPRn+Byy+TuVpjwGZ+/PPWouMentg8vOtNtY8FgvaqzBYc6QclXCpzwlNKGnux V7tMV5qOrk4K2fdXApTFebb1GZhdGUMGwdSGMq9GyMRIvcNgNo8gzV4w91KRInuPS4Mvl+THKVZ3 SSotRtj+iKGjEodWYJlfA8Sxdgggncagc9jP1Kl6Tx03LBPwdOthrhgsv6ufLS2A4VjYzJ/kzJ/H 3Z6f7I54dGK9cziOyjLGya7EJYcOPzBzfQvEoBtRcoOU3gmIX7APf2IUaFWfC7+IPHxkKBDmwnKN QCt5LTIgj7DYUTg2c4hAh9qTQwh3XhlzYrhTaxY3zmJzJm27YtaTPwTw9ldCjutK5NaICodvM+0w pbIzS6ZzGkmQHHfq4sejqsx4uOgRfIhq8pnNm+hcGoQIJzQ8HQTnEOwNSF0SrKt9Fm8yDgvm9Qs3 dONOhdkJFKVcRgtKIf88Xc6eqXpRsgKgY3zZytgoiViuD7JK/cRh2wpSWVT76BCLWC2Qcj4XOag3 1Q+unlrh1HKJ6uhSUZrsuV6UO3s9qH2qr2T9fPPkFhsN/ey0ybR0QaOaBR4+7j/2YNM65CCnlo5t ZTKfkn+plwTZ1Ks8N2AGOQ+fp7aT0pXOaz8CsZycI7/trB8kbDD1adHIxskNDECBRYjJDKVaecD+ lZj4NmnpqTMimMS/ZcNtOsYNcx2nEu+EJDR3vFc3quPtdVzBmckq6yYC0O20ECe3YLGaKhLIXvMC X8BLzfskMNaJXNrM9FSV472T1deF8YyB57ZHHwDoTqKFzZPoVNluAk+DZtFGb5lpp1j9J3/8F/nt 6tlkF34T8zLeCIzi2aYAo4Gc7/RIPJxo0FWdPDmwiw73YWTbZjQxQaGs+WbgGT7ntAjf6w2at1/0 ZMsaL9gPS4ToF0st7+MnALnohj3drJ5eKw9GYq7RNt/f2ajsEWacBef/ms3UMzU9cQ9LOidiOTqe gJ6AsKAQLF4rubIuTVfNSepahE80jU2121xtAuw9WTUex+I3gQ1xYDNBNiIlVaFrrRnVO3Ie1viw SnJsnntvFxr1PqXLeSXLmDnfdpxD2kF4MOLTK7l4HSa0TQaJucPGBY1Yd63Tie7FYOzFIPkRdG1X O+olnYxE74o8+yRy+1GmmWGO5f54JREM1MuJUzUU4HLN926nSekVE62AbCS1TLu9El65PiPanD2O p7UDDjnd93dh0Olynh3OWdUP3jfc00NIZK6NQq/gwJCbmhmFSU/H2AEpXjlWBnNhFmS/TEFS7N/g 8A2LzSW9NclZ5UH+3IbjiukUBhdkm1yrVUz6sl6vW2MBs/IKMXLFyWx6ko/oyBipHDHNgqFkw59A sG5zX0qzzaCmFJssU2WyCdgVhmHo+7lDnNUO4EyuiV5iJL5fjcpRdmuNsYKJ2Zles7wk9CoDsonC tHcOeHe8JxgoS3H0jVjB5tIkvtv2SuNhNiD+wbdYX75C8iTFqLqZwks0DYp4ZDeQkLiNWy5am7G2 jG4bvtJxFuiq4l0xnugPkEp51PlkIAwKcT3Fb8jOLG3x1N4e8laXimPKGwvAhyH32BGSADBwl4eH zSuSMkcm0vx8MZxYgx1AAA74iaHcDdh7sqUpy6wbo/zI6+I/0n3a97U0XB8LuPXlbPSZyoPlzCJE 40/rS89rSHtRKIta/QyiIHEE4tqOa1v9sm5Y7CnFEvkOxcYWbstILv9nRjV9zujaMsUBJASlKI8M bNkSMQwL2MjEOjtr/H3g378+wTkhwCTBsOJFjbLJ+qByEuVhpaNKpSjPpmnH+94xJHFyqPRs1kWs 4MxBKvTv8kQ3Eir82t2r5dyX0zknU6ZL305y0oZ2yVfhK3yN2xsKjPS+itoPgCFNkqkhLbfG4PE3 TC+5unStJdO0/yiL56FcnuerhOTr5zYS6F2hB1SLUNlMQsl1VMR+UlqTXQr02bobT6PlbKtlOMg/ R9DOROOQpkjjkVMPNdUFJU7s5xhoe39uJ+W885D1/6N91sgg9P4NH5UKJb5UKYGNT5ACYJ+WeN4m hUWxU3c3OCsZp2CqiWrLMKtgPmCEzCHzUHACnEmc/mA17yGzUAtHXS/0lZmc5lonuDuQHTsnZXhm MD8243MFed664GMIhCQ/clcsBwnaXCapV8IhoKfPNhIorialVLv+boBc5WVcs/WGk1iCajozJORx 7lA+dG4AltS9k2Ge9WD2iGGixCXOPC8VDMSa0o8r0is8qGCKoZtD+Oujp+ZC4XGkS7hhjTqsIlAv ++LH0nWmsMkNSzxzbxMAmNX3B4SfQnlrugHtdb2vj5CLNwhkCqx4mP0HD5Iut4mAKvPRxP8nwOKM UzLu5MRGpEwZMGFeGrsJrzv8n23Ja+gAuqF9g14BPNxSJKJIsKdwkBJoVAcio/pvYeeVzgV/4kon 10tCymIlvNLfX+LzBaqe4yoINSL7N/mvRUnkPFhvLyEk30BZfNvWyuzF/7dU1RrGXRERMg1m3BDK 23XKt7pL/fyrKY97g2OPmnzVSLtaLomgLHAGKRlp+ZlggW5NniK7DtyZDcHNvZxHeSqlvpo5qgZM EgcqTZKphDPI5NhtFCqD8GjJKd+WPgkPQJtaHe5HhbgrbH8vEzju4Vbt3fzCv2S9e3eNPHXYaEg4 15LeGAkCtEVosWO/1dozVGOORUc0U1WkMy+B1Vr28ivrprjLJ7dkUmIKH9eVSLHOiyyoE0vvTwM/ D+WHswrw1tMnL5YJ90qsyLzMmpRzc0upQDDgAAV0JIdOiH86ANnxIKvsqJCfY3lL4P/fsaxu5fge sR5uDYpR3FT+3N+8zv021EdUIsbz3oiHdGE/hTkg72jHqi5xNLVv59IK71a9VDSxqH8NsO699C6R iPC4aSXayg10r5K627IwAHs0LVglCF1Iw4mH2WqTKlfnnAh2r65AQe5IHOAuLG8mQCDEUbwArEoI HeeNTtB20aVmsPVdZBPD4uGFj2N2qkchCkcgGeZMPXyaHyrOpkexBeU0OfbQ2Ww5w9cHmkLPw1hl cJFbh9mk9gClfpZOrD04iXNViVkXzoa+vqAmpTJ4nz0HxdSjW+6px5B3MMUG7hQs7+pIBGyTVofZ /PVfJuSNdbuZdPZR3IU02eeastc764i+lT482wQ/WADKpjax0F3yn+i7BIYG80p4nvbqEcJ22NHX tGA4rC/TPv8gWFULr++TGX3eNNjovlGAYD3qtn5SEwKQjfzMAiB6mwHaCO8OG0WwfiZOitP9kBY/ 7sS9VKi1oDefj2r4+TZDsrMS8/+R8hKU7L/Bh/ZmtwPik7nPDe5c1pftGVaj/PVY3/vC/uX+QaJf XRx0R+TQ3zeChjDIm0vwuIy6BUPl08JaOCOSoD0DC3f65KRQgIK21iiSKVqt8ERiPQWL651s48oC Qxz6RphQFU7aaGLZ54LZxcWpEhCutR5mTpaeN7anbdI0k4URgw0esgrhzfdmxcGNPODKT+/Nq9ux QHQE0E6+nNoAHi27JUZednXllXRoXRXORFUS9v7BAw0OBP/wgsuwRrdmYAhGYMhx/Wckiudiamae vADcBib0JxaNUGnxqYIX0cpRTyJxuNoCOEek79VNBttYwxkvBFL1+rD3sMHTWjbcR6zkZfgFiOHj KoWikxX+99t5mwHZ3NVB592rOgllSdU0NzrgKhpYgvjBmY7wJaKUBATd7qpL2cgrqMwt+cOqetU5 n8/dxiABLZxPxEeZdjinU4cHKBswkkkhpHgslYC7UpGtThyU60rf2mdvx50nWKfL0RO9qoKJeH8L WhKnhUyZ0H+ywXD64rGDt8yDdFMLzvnax9h/lJd61uQYLMdOCMAvmUY6A2bLChe+DOsnU526VfDj QXDzsY9HFT4ssiuvVy/9KfOrwqYAFnUOSrQS2xppt6dhsIoVAxjOl4YsjnPaxMVEVyMHZyaG5kPf TyCWmZAg5dX41gxeQ8T8XJvPVHgGm44Q49+ZAuvS8uFlyFpXNUgKNRRIUyxC5jaM7t6+nz9J3jPW Ji+CVHc+hMnZHGe0JNIxuHF6RRr07YAJ4gmGrdtKJoRwxWkE4xEnQqotiAwC8+aEFJZHTJk+oWCP sMohJd3cl93x6hmcjtv2b0wcCyKYYnnE1HjPbP8gXFxPn6zeFL4rpsSAjCdvmPgzBDxFo1pB0HBR EnHOBQAwXTdhXrRuy/s9xyfAnFTK2oV5330UzqiMYinSRGYs5o+gIk+B8ZASk52Aq2IehCaD/b2e uKX0/AHiyCwZyYng/b4NIPE62yWcQruNl2oQUKglwveZH3k/tCQZW9ekoXF0sLHPVLsisidkbB6M pFVmkc/x0RZlwf6enpxuJtVZy6Ud9oji/GkBg1JutRsfFG131cT1L6bk9aaFBihw9RJOoGQcyM4y CPWSrnbF7zwTEXjoax0fgspMr4JvunDuu+CRm5cU48t1lyLl+v+uEWOU++NdPjxxML6YMriGpefm NKt01j1ekgJcLxdCtH3Gyc2m5B6Jq9X6Qn9saon8jXEVwQ17425oITHQ3rY/gpUC/MjwetmF090Y yBdwDuzB/CgZqfgajquEmLrafICyyxv4c2IPht2gzj8jB8k7FGQfKsbROKTZ+AhSVrLvMSZaXjSK whEkLTIphoUUtho9Sg+XzGe6ZeDe06aRBwTd/gDodntK8O63taufoD71nmZYPIGfmZ4MnAfjVwkP wvgkAJVyhOHZD+iZpPHHoQXi58viQ8YMrLq9DUVUPpnqGO+eD5iZFIYAuFC3b8IySlD6jlLeTSuX Un3dObXeIOsNAohnX4SzvTzuID5U2a8U0WQgZsF7I1eQFW8jQ2GHtgdiqeOZvo4KTR6K7/cJq1Sx aKpdqlAQNWAjzfFy18O2TPL94puULAszOVHU88IBkqN97nk+pdGddgp7aWDomchT3zFxVJWtSoGz UcOYVEXKluLUek2RH2KS0hFpHxCs0Pypcq2OXus74VEZpE23qNTpfoMfK2yhK+6hluniXgkYfls8 edE4X3lOrnDJf+ewrRMebvLGYcxwSfep8il6NzeO93DHH0Orr0mOwiVLs1ajXZvjmEBlLmIhlrLE orAYN03QC2nAa5uyXV4In0kTXxrz6y2ymU/okkMMOLLp/p5rXcVPWJaSjMdW3reZujP3/7u7mqZS iw9jAx6heCFgI50fNKDZT5FA1cb+pWCCRMpuxJ7KL3H3t+33ph+NBiLJMM/xAyF/YJgl90mFHmVS F2ySS7WKTxwKnCgQsd0BGfIWckd2tSqsIJrvRxY1HB0DtCiImC5I3YYRQoxMMXQFC2sFfIelOY8d DMM6P7Obs76wTZ3MycG005D1sAo2huDeoHywdIWd8uMek/TPUcCbSw+ZBQhvjhNZC2KWk/U8fREb fqfh83kBtbKfC7X2+pUmzjU77QjYyM4TXE76I7DIm7qWQ+cUpK9OyyZ77GJbA1a7cQrU/YJBNRMe aAP9Osgel1k3TJ6tJTzoR9UF2ylMH2NraeBsC2xda0jx1H1erNUGQyp76bnuTMiSfG7RFHs6667C XNqVyxG4TxlAoihMko0o3R/qpuS6w47gijGN8m4HabHnlwDK6ysSM2fwZmRD5NbpZIy7qsMN2gqE L6HkdLI+/JpQqLsxumsshhqL5rEaZ9SqI2Pxb9EYYWn/Mvhs/+EvdDL0CEQEsJMcK2NYyaHq3YuK Vnebrq2SJpSjVhfnsVyc9Izy9kMNKKyoNJNV4sQ7+vRRvcwPN+G17GYhbr/ISeqsvCadbITNDcIv aDL8vZoDI6woO3bQ4l9bPw76mjLrHJbjBjnX3OL5zCLcVEtFVH1c+MVZnqrVzLMVzG2c6XIIDMJ0 h2uwUOJvyBfVf4+IPsCaBp6zPz8gf7Fdle1/l52Qr56EdPdmEXe3Gg05HMSGSAkpnjjw+Z2+Dent e5qFVdMdLE8uSRc8JxZqUjbRBXpUxRBbskvIRe661HqqPufk1OZ4kb76pQwYUXJASgsCEe3aOVlm 9N9ICaL5jUOJedzSEoJmGTOcOZBckB+C22jt9W57bLbGO1RffVQJdMbhVgxCBklKmzAZ5Jdw1TbJ 80FxWhk3cPmaeMKxjSbOMH59FTbGgJw3Q4foE//W4LjV4kLmrUj6eQu9dcFde/aBgJFEMuuLvidi +2sdG6x+NT7rBHggz9Vw5S0xEF8aQL39PoupTaypkCJGkouDxAGnaHgUzohTqa6c5rnM4BwHCZ1O +75hgxyjOhwK26+D6XJHV5SMGBBkhSFLD02vumnzekjXL+0961TcEQRuUftjbbPwRufzGwfGFINe aOX2jjqXEep1pENciMWfiwijNn0SOdURwB3w+717xdzm/lI7hvnJfMZW3/U/RKR6mtoXDV+ijoyx qoH0NPCmhgW/EyWSKmSgvIQXG0sQ5VLypZLrRIBLU4c6aX75H86z64ovVTocoxnxhkw9EZNdkkw0 9RSXKg8KIwwC8HQBo3Jlv83LCxGSsRuw6MmHCTfJSpnTWCLJfRlLCi6GH6lt4/a1/TBfDLlLW7UN AhVzcMRCalDOScyHF+rQR13wrkJe0bjwGL8NLWx0Yit0ES/sN0fco7YJu6KjHFM0ViKvQUAuGeKx +EfgTGMkZJnzRV4B0WSDO2lmSfYkdl17EI/OxtXUyTpsu9TBR4XDyoCZJUaleWNaylpoMtIikfyp VCq+jANnG0Rzec6Mpk8c8Un1lSXBQPwJnZSEGPxnRG0dW/l3z24YxeYUIhzL0MvIVl+KltdQiB9V kbjZt1xoA7k0jy6GbN4+Izt79u3AcfGhnhJiaaNaiaQC50FkPT3uKDf5iRFZBxKEAWuoEL3Sl6fT I9yKXyYiD0w/kdZeqT+8Nmtix293rSnprterokk8DvrBzv3hWv89kved68N0iwvGLIp8rUtmCfJm fdHX4KMiXtHCNfOCTyF01K+JyGN+STeLLgr/AJpj7TociRxSXFqEY4z4Du2agOeT0LUUtuMSwlCg CimQlk8BCzIB3IRtc+YO6OpfnMNlBX8zGYhDA2qkrp0UsAIMafLWffTrRc1soPX+AJglxrXMjJVd c4ihyRZmp/aTOV4o0WET0MtXM2jh9f3Kfwsw9jwFtlptX9popMj8YMwOqammy4k78GdzGZFDNiO4 acSIflOA9t3CxLXmoKhHuVZ3c0g7tG9UjtNmB3LtFgfj1GEK9C3FCBCWhIxwsQIsWDgy7wR04qoM SKb2GYNsMmokkXRQP9+7YZaHp+0XrFlKyfcKJ4q3uW4HV9xL7Abl4glTNKM6csQpLkv03VqFZVQD QckLCzY31fNh//Vb7KftZPunp+Mpg60LUla+e+LIV/xf+VR0Ff6Dhu7YD/WO541ApBUK1s14XnaH BCkAKOSyCx6IQFnRzn2FjJEStpvloVpqWWJuGOrelvSsctoh9tWkJq3KQv43Mmv+lz/nQ1dtiFia Ak4eS/iBeHstcgUJfS9v3fKTl2dkSml6Kx8o2bUhoSFTU7h9r5HUoUIUBURGBJdbe+V/5aHUaaoC Q5A9sJBcGZu0swsS4zyWFPC6NEEPsAGlEBtIwpgieIslBQ6uU1ywSGB5A8wgrht9vt0zUf9nqwkj C1eatsez3G3h2tSMfoyj8799E3MjvSAPxsA/hzWtKF3505zN7Fxr1cmDpYgf+pOSSACBrvjFFQkC KXA8tlKC2Wu0cS7cCNknMUqs45l4Zg35F7nKNPcCchKCLE2kzxvEuU3976wVlTIttPV4+EcRjSil glcN+yqCeHO1CD4QaDWMAOIbkWretVW2Ul/iq6XDEkSuUuEAIwrYpCkcqURgO/X2nYVwd69tPTsn yXmkq4aKhhs1PfXw7g/BO0wCCe/uHbt7sLSQuc8/eJ/hhOekQbPB0xofiU24v8QqfbhuqjC3K3F5 hd5/n/ky8zk94NWNDzODnKtSF7Khy/lkLvQFE2tSesou4lTaLxp3PgKpPb7X+INZuI++P4ygNNO1 z43PhcdJJaVFDByXCu6YZXzKPclePEBhP+uP6R+IDO/iB6kY6TAm2BSTAw06xWEtmfhAtUO7G4Au cJIBPD0AeJ+MzxAup+RxcydOt88nfkBOVARCugQt9dSYKuVIZMCO2RiY0PXv9Fk5HsrCAmY0ZoPb CjLb1yiprP5+4t7dTgP75rhPPMd0OL+/8XmaJbGWI8p533imkQaRnDlTBI/34Gb4kAeIzsE3MfMX taPXdyr+oAMBOzCuVE5+UX+PsnjfVuy00Aejr0Jn01Lv0+PfNNltC9itVB+dYVPCFnqLp8xKnugO JXGMDAkwCAC1MbgaSQ7wvL0/88JXRdgy0+mGS/LbJquaIFIhPqO8/64yFx9NcLwxwnX5vSGGce6I xRba6k+SwQh0CFWBYx6YuUouPrwSMOAhPzK5P9SB3WM7d4LWPXsV11BMFKTyFIiBPJKWB7HaMqh5 EKaR/TNsz3AMGLX0t3ipCt2txRxWnGGlaMKwIWWk5hunJnxNpjBCCrkCwnKzuGy4BcfewKTbvCOS eOe6Jvw43Ds+2haAGePMinAt3X2rWFkDYI6WOQ43ntRfIbSeMXXWVVX/cXXW/TQOV2IWHOMexZgN Oy9jf6Xus8JF+bOOgD1qnPhD1YOp0rdMtnpY7rvP47uBkLzYSUiXb9KYlvm9jEZHOUgMsLsyrDn/ pZXehSAWGPewAhqxQ8Sd9cEhfZCmvylLc4crbDQXa2P9FclcCsvpEjaAcCoh8Rh0HhHUBKKLaDhL WHFGFVvbxBCq2sUjJYOX7S6OG7OkmsUPt8fzfNFS7DEzhMkTTklW4RnR5EccFakKdgp4C1+UPtkp rysaIcOVaNg33rxfysNHC+OByJCdfDmCzoPMmRuoh/wvHU1MJJJ7/1bSK7z41cfbG7HcClas/pEF KRlU9aCyt5JkcYU6sor5Vu6I3d6zRQE3dmQHnuiSys5ysbnQomnrekdvpMgQZU0lc0dVtqRfdu3P zE1VCpLmhYyatdz0h0UxCHjF6FjZYbTNCRWtIM/o4wMreU46OaD6HjizI7YYYzasx9w8zctdR8Ee 2pvYozDzwRKpfONtKbYpPp3MJji8rIR3cRDcSsMLpsPTKvlQTi9Kw7dwMFT6ScC4QblbFMr/XIp9 tCmN/7HJhjg5nRdX0evXISxfb3UezgVB7UCtd10X4USmwDZyej2Zwu/XQNV3KvbobeV6f7dk12p4 bmcJQQPi6NxaCJo7vFsTZ1omM2Y/T842JIh+Maw7H3v8vg8fYV/LJUwPvIMtwD7Mo6eKC05qVE/J 8NGesoyF7kc+0QdTrGJNzpa3rrTEWQu0xcbb6gwzclUqtNFmtA1vPsOWGohjwARJg42TMPX0OLFN PlIqKxmLI7WBDXSiifQac2utwZKa89s3TU6ALf04o+5VBHwwhL4ibqvF/3SGBV+j2ZDcaVNt8n5e UMX4FedHfh2LmFw5ro3avGU9jRGKOaimppMx5CNbIPdqd80lEcJvdFBRDvBi62TYcNehziSKP4uF swrBa8flp3cKDzFu9Kv7EyToPPv+YCfSM4U780S697VQ4FTx5jLHGsxCKn6scZ73gNwqxGgEN78U 26KVbGT4h427lnLUXN1XGu7rl9EdvoKF6Rb1a81CLeTpjfGEzlTLmBLumWx/8jPeR890EcfyCrBN UXIsJEdw9+Rh47hGzGTWQF8UEVIS7BQ2TQzCPMIfgC58BQ7V/u4Fv6yGA7bX3Z90nS2wKYwEjdrY 0ValpsKC/9BihAEcvDw3kNzVo74O9cXrWdNucexO0BYCblOINhMQqfHCa6nWZcMxuWO0R0VVkGEp VCEWLhWYJwKp2A6V4D7qM9rsswC9bkx8koGNr80vSMElxyyWFCjjBK6y70Nkb3PuCbhJwfVCLYK/ Li6gcMLYTf6y0PfIdJL05XHEAdNOplD7FaAv9GoT3HazeFdpBMCeJx1OQoJOSJbKttbsv/CkKPop UlpAyqEFrAoUTff8Pt2mx3JWRcajh/yUiPz0KenDn6ZeZs4xMSJugeac43qX/m6u9RZ6w6oeBLwr oXc1iClGd+3P1WVUPmkr4mmEodJtayc852BXGI0R9tcIEeb0q6jsGsn5y2g86GqTC5p4dvvbnhOa WvyMaq7Mo/0Z0oOcNsJt6A5owhYnAFoKWGQH5utsS64RebYDJnPdRBjQl34NcpSJC3YTcIP0IBlh cSHnTTUjiUmpk1Kb1AyPV6gsh62es7NwJxW2xedLuvfs5BGVqrpvhwQ/3qYv29D9zvMbEQRPk75x f5RNaQoGGAEY3GVCWwORWKozb18x5IyI5kWTQZp35JAIHGWMkUSnUUNAsB/UtRsWfy6/kSA5VoW9 bz4SE9ysxi+jc86lz84yU+Gt0uL0FSLVV4BaOGOyS1vLIlImtJHFXnaIAkre312kYki2awYZNCMa O7jsrp5eKNdRwlhuvGzrmn8o0ibppRXqXyJ9wpxAarKhWx4CbJrAAde14xvvlk5S1lI403K+glhx 5gyeNTuE/zedaOekbClJmuCb1BbkuDMHSFrDj8/6kaM67Zxnld8NS+RDdBvrhxqD8MFBizampZe6 86rNvhmHlPUMNbq0E4Hqr/3TQNjjY7+dRsrtTwzDjaHvjHPZyo53tVxnUqtAL4XuCZ5zN0aG4mQH 9brsEwDMUCBlOSTt5NGowseB93gC063tvKJm6f+dZyZ8KdbeczrWhQOKd0qeaKzcXJFE6Pio7Gao QMVJ5PYYXKCxSzELSV6Yfw1D64nr8MlqoaySLfXqB4pbeqk/jPE+bLPCsTGvcE/UA5RsZ1X2+SNa M6ba2xkt7MnGdn1c1J35nF3DUSp7g8QOjXGnZS5FqnX178tocs98lGJVJlN9ZUVYqylqm06dkgCA OghuC5vaTeWc9mKKQ3KY4U0bNEUAOD4RO4qOOEmnAbtCNjnjNux3khpS9OlQPQZPIGkY0s1Obd0n x0x5ymF3NJZOhutxiznyjYB+DwaQb7sExQUeamra/eXLjo9id2DkWc/x/YAqAlOxzCOdQ3hz4GNd 6P0b4ytPfXHpNvOhTAthKdi6f2QAm1q5I3Vj5fdSEGgsv5/RTiD/8xnxR+veX+IX1WDwBhKcVzpE YKPAaOvfhDul7t6pw81rCE8W59Pv3zVSXkVZnNYfOXROUBmmqpVb3WS1jxgnJSjxZkzlbDIxkG3B HrmQAFsGRIaaCyFNLAj/Tyoxix33eNk993inYagKzMnvbCKQRcCnjC+BmP8SnRbjyaygBV1anLW7 +zh3SHPmTvft1u8RTB17z+mCsIN+r7ZihT3wlEO/MoDfS/MqAeAk2qCsnOZ6HyUxz34W20uDRbGM mDRTuPqdDBEfXzcJAhFujZXtKdcV04kQga/sSqjqewsiAS+vckqjHqUOF/MgmuG96tT3OxLNXLV7 LhUS4+NZWsKbBiMdWc8OmiToPgMKlbY3bjUawARXMI0l2mAcAiorIvh69SBeN+ryOMq/N2cs7t+h CQsspEJ3Jv72/FY9mNinj6R/ormTmIvY1fpHFrYsWQO6Wxh6kEMNgE5Z2PgEAM9N5vxCEjgWRYrm NRnxZNKg1x7LB4clETjoMn4l7FeIQ9gcuUzh7F+pa+4Uw/e0zxuiw5H4hlOGnGm9MTCuaJOHh+PV IDObKFFWBe3JBd7WULEmLfHhhOgp4bPbkLmIZkNTfPUyB/StgutCotRT8mnNN45dKpZM24VvL3Gg nqyh+/yXOh+NMnw0TeqwLbmawaVjHU15rbJwAcLjBLA0yMvdcYlEIpsbqXwM4Uw1v8zKTaG/oyMM RYnC+hUxY29/TzY9HFJKY1PKB7F9A3pVRjIBba4d8Ca2KsbnKVZqy/HMYbqFtVws1uRVfB+6Mwi2 y84UZRltgaHIXU17dA+gaW18KBVHgx3k4LsLQu9nFz11Ak5dkdaEbWYZ8XqhjbHQIpWtLmp29yAd +g5Ez2oq4PUoy4M+9SHgAWYFu1HeZoj+3Or3FlNUFC63+FtTppcW2TL64uyNYehfBOTA6EMfWtjo o7CsBOv1kZguCm0UcvHs7eMtDb7ppyrYU2osSxE5+Yf8NArPBuhGk6nRD9lrcuwHCpOGl+1E+d87 XkForkIqDT1MphRc/FP1yLO+uDLpZRsVNvKNYJrnVmzO7FjVcNwxYOPUXt3DrWt0yslLoXUwjqH7 j+0o338J5SShaRn0MhWoj3kXwNTe2Ml7TTDbhKRyUomck+LX/0psqYhK1CAdPx79QNZxu9o8lhWj wL2xTNUjkj15pPgdpo5L0aibL7ne7D4RsoZfQXnqud7d/fh+ipncWKl7CuzSjOzt3FzcH8XZ7+ek kc4HCeZt7/h2RDSaYrqFCDNs/DiSS5LWmLbIZGvE33C4nE3DMFpksbp3ta6TTH2qmPoeMPu8SxDi PVG9bYEe1u3aBV4wzAvH7y5MjFpjIRfRRJVaTqWnK+jmEUVoZQWSMRXSvLHiAmaDAO1j4MQ02TLu Y2YbHyvzijizKVQLzRDXN3MNLGBH50+GyJyU+btH93OMRMeFLv0JPQ/kDVaeU/+kD1IolPJQFy+X AjOrge+nvVJvvWqMIOb8wT/el+6QQ7ERzpswB5dOctESdEERFTwl/DtJ0Lh+S1WGZY2roJ2f9bcF 9qUS19GMxNu6PmlKHpLKeu8dWJNxYTx8i5/9JNH/YeF8fbSjg+iPts5bCs7ZAYGtSX7lBxc0yTZY X5I5D2JO2AHErrUO30RJ7e32B9UKm01t4RBvRkMYJQkVLGjoozSoKtnACC1D27KxgoOnyGo15Amj uHBKyRnGb6ZAKZLZmnNv80yR/binSsc5+O8MUWL2MXmk2MnOBLFcLhcT5hq20WSZIDr/0arKHp+9 5zYIGCYZpQHwbaqbaQ/qg4CsgH5gH7+Y0ziEOfQ+8YTkFCWdYrtJsi5cP5010B1/0RZb3JPVC1rJ NaytL+Nx5wE6HuszU9OhS4lMQAO2P8McIpdsXWMQT9qEbcao4rgJAEUb79ZN/o0nuIasD0uQoXqm Jhsol7fxQUugHs3VOzhLmnIYdGljs6wwbCw1AiQtUAjZa8NGOp+IiCHaD9VbfSPl9xDkYx4vdJf8 oIhkd2/2WjEVRWU1qsVdtEpwa+zp+D8NaXiB5iJhAgvXEfdemv1d/igigKgyphGZcMlsyOgDrqIU wcJ9uFNtooYjDaMljuGuQCuLpGjb2ightuk+Qv8QV6ufs1SDJR2UNRdzqDyjGwL62FpK9fCNi/bA vw3JXQMMbg7EIv2MGBhyqlW8EBDUEYkG6p1JB9+ZjaemjSVID0IyJ26vkdSjffEUFkn3qWcemTfh cgHk6DUFQmiFkomG4ozWIqxK1GZIss/F7UQaYuJGXlNpNrCbJdPmHy2VisZsnIGDWwn9go9xkl+o AeJqPWFvbBBKcjTW5ZZfiVSJkzBZIc4GrCOJ+KdjP+0FneQop1Z/NJRpZw0SoMLEd92Ss9hhs/bs IYx/iVqaWEsLtcBnYlqBTHu0p22cPp6DcNL8zqmFNegXoh5zhVXVkr5atnKABU+IMriXCP6l4qfO xINykOD/H6oT1e8MEV5dzSn/iN/Ux05xX0DI4eNBpiqIyFFDJLWyGy1HdFzrSxmZiZIRxy7Ry21A RUD+YmXyZPOqfy6e2e2BqBve28frMLaNDeEw3VHDhMsl0au5qdR2mVk38Tj6aNil1Izlbd0HPVw+ UksrwLgNBOc5L+bzl/M9HwLOLBIPIDvGdRBTJFS69XioAFRelfKb1GXSa3o6aZ0hejfigUJ1+Ggd WFGsz1Gq0qrY/Mv7w8+/JbwLRVudGRSYkt592wm2qq5zDFFRhXZczrcqYpsnkuIvHEWU4Wjjopwo 0o/jxo9oyM0kipaIgdsCqLI17T8JlAfJK3C67vBLw0Cka1lIon2ndlsLTvhvuUwkRfo0iLPiC1ao RL+sieu2+DEgdlkwdW1Z0lKbBGg0K5QKy7np9l5s3VmlexU5ZDj/Y2O/A7HfqP4Cp3WkokOjSTsn ozRhdOdqIHW3xA6MQqGyBAeqsPEjyu4H1pLwNLVucAGUexbTc/Z+wnrkTMDL5b+QqgQhjj/CrW0e azUd+gtbrFH1q6h6MzKxSU0ynaPJfWLNGShz/h1zu+GRtj2Ty1OPeyY2mea1Xj9i5opy/9Kk/RYd /AgH7yH+cyNJOJvGBnsQ2+64K8z3q9JoW3CxZhRFUBxMVsd8jVnhPap3ZLL9weu03E6YryX9vrlB p7nIetGXoQOxBEr/nn33WRc9jQ/jnKMsK1wPnXrXXFk3dUTiiPdIFFt9LPO4s/w7LWpwzxubNWYX TRYcAZHLK8C1Ho8BMFUdPHXOXoKtmY/nnPKt8pHJcHO7WBb4MIPL6j6CZFuSiieOuK/9ZYZ54Pec xMmRWJNCsLICImadEOpU8X60EqqTeoQSE9Y6JcgdLl5c9FaAAoDyz9S+atK5lxeNbVZU2qMl+7sj XklnA2vYZKyYfdI7vWGoDzY5stVOxOPMaKJUTEa9qsJqPUJjr31GfuodK6Nsy9Oazfy2WwVqgib3 QOzy+dmoRt6/wu+i9X4ZArccPkUJkaEYBxHH5dduEd0tD/mjMU+Nhq7V5WcY2j0Y0Mz6simPqCQ1 uXLCXnI0s7UCUUymWvIQPSOtR8CRi2UQ8EHU8UXBA82RnY+NFqWutEXBZThBnvEbKPKNya/quAzN 2VYe4ekHWXqen72M4eY4Nzn3uzK3EYk9jJO036J3GHMHEPjy/424D0npyy7xHunNXFFJ+x0UmBSP QKR1k29YQI9i3YVDHSyDHZBFdjWIQK/unsjVF31gAkNW77hSJ2kVm/ownxZjv9Cz28WzN1SRJlVj qLT12PFsyR3ZGbF/OC8egx+jxI1rYYkNRwWFkgBv6bLobftwmNolXHSrM/K0gkOqmcaqhY2NuDDu KXZNue2oc4b77NeAC19M9L4kYPX1P1fOOCBiyJvgoN+BweWdcOpVixANYrEBE/coO75cZQ1X6lnv eE5GHgxE2rlxiThkDOZx0fMXWNM4xecuhuQ/pFRHH9MojD3NKZBD/4evxbA7yjSvxDEHOhtUMQ9A mAxkKyj3DH0oqmAm1FGDki9lHJsxnoN0suib0idfXZ2zf0d0FM9r21yJEM37NpkjaGIQoi7+WVW1 80Ovkt7q3RWhLa8DC3SPHVb2q2uaqSNauUkt9dttdzDH9XnsI2mnzkkkWO/+acCxg9BgWp/nO74R yKyE9sZJX4Ey48UkiWMD6EaDGKOpt/NXIANq7kMSqxOr3V+gjyd4kVEcsg3D78wD0fHffzQnCE0r 3pbUEFfj+DCgD4PX+Na2e1rIcP8F/nuAZeTWqyF2Ik86TvV+KUok2LdSANeoX8HFFB1TStzpsb7L Gutjiw+y6Gtk98dsDRPhsWOqftMoKXcGmX2W6S/edkQCWSfQ3i3MvwrJo1tbjOPETjP2i8QEzFBU ixnyJ4eScq7ahaki8URwaBjMMMZNUipzyD5+Bh538ljk2JoYH86RB/zWomKscLutZkaakfA9TnOU I8/lQ/F46PNpnW2oXIUt7HmlGM6DA8rDDqaHwFV3C2euLQAmU2ow1MfhwcqH9dMnWeuNURtetYHo A7GHaWJ80484zftZPtPkWW/f7TYl2H3BtPy1FV0z1NJjR8hw3hHb2/u3DzaAwSus83iv/RTfdY/u 8JdlPbGNfQ7NIOwooX4CmnydI5L2EfrSqRtOP9Xoh6wtyFIs7DwjMAk/5uStGQgQoJ58gpmxCBcd 7DQ2ifNTFEzuCiDXCmEF6u1AVPHDKBqhTDB3qKaNv+iXsrOZl/LPCZQlvPy61k8ZqBtTuxuHU6EU l/TzDz5v1OlIZtDHDuaybSffLfcx0XSlxE1DMaNy7epTRh8Qk3r7wQE7WAGLoIA0Ylkdso0rpMId 7OEY7axt36ImGEozcYuLaImlQfCtLT38/95F7BEzWcdabPue9qWBnFtsdAG+m/F/LMsK4PWszb/g wxsMODIxbxFySQA4nCxT3kwA5yAVRV+sbXNvX58qmORfGxl3P0WTGtuCcW3Itbo5rv8aHA5WoTwQ 6lgqaEPKH6KY0GiTw4UB/8ccpbRfgYyGUUYnGkRKWUG9iSmMZhgwf/wGl8x/dIMi5vpsyw2JwZux KIvO1yaR2v8kXHa/AMoJ/naKGBwXh1kwO8pUqPegP82Li8MlJ16T4o1WjuZnNVdveHE8Yv7NvkpC 1alYHfdsdQUsSbYhY8fApGNfvpg7xHWVw/8AxnORDD57BMepPd6nElIeGTa0WljH2scKgkcIDGHl 23ALnlKw5TdBfHplQuJOch5DkZcRQFOgx2K+rTVUbKh5CNi9CPgep09digSBB50bfyaFmQmGzLG8 XirbWarxPOz85fLxrwhwgQqzg0m6Br72I9Gf2ST+7qeprCheeSAjGuhGWIWDqwyVZafTlXN57RYr jc7V6jzI8/8y5wqO99depsyzcVK8t9zWZAeHsF7ZoihaWw5/WIyJ/UYfHgZYZ8HrGyuqRkC7U1Zb 2GDfzVjc9iEkPFHn2DPe+F0vZ9Tr/AqxBUJMmZFNtZ1zXllHZWvzxYnEfYWackE5CjwxCdzG9lFK bAOg98strHi9yroo43Nb05e9X8FYfQmn9wFx+/Gn6w/Coa6h4b4i2cGtSbeHL76kZPSpwDduF3gl UsQkixW5ttkebGvXNcTmxnHbMQHtqqMGi3tGEv1bvHKBbWVWs90WHeLpaCQy/eMqL8Bv8ABs19oj wSMoXXvx8khQ2/jhXUhf3JgsVWUbFYA1mMY9c2UDUB2//tKn7KssoI+5OHBN43r7O7j0Z16bNE5o jCrfoOjl7ud/2JcM+p7PNHyNGy9k8ZlyE31vHaRAaQHvVqvd6R01FhHBZet8ATaVPnVgSnyRaA1l 2jGgmxR42fXWuqAz2n8I1/+kIFQR0u4cuEHx1/+K0YhXgnh/ha8eEU3rpYGIo/HvV4otOZ2Le6Yl H2LAf0F56gel56jIYSHysr8vPK4/CoX8bR9+HfTDN24sWRbcU6aq3IoPh4BOEErwqb19dW2DLw5F M0VICtW+o7lZG2dknJCjWSXZzuNZWsHl2fefnUeVB7MXV9qxlglCEeig5cPunkVU39hme3N94HXK CEftN8sr+SS6gHZM61WQhU/wniPWZykSjBfG8oLS7+bzGcjx3aICJwIUWHYxddVRu15V8Lco8NhF C7iOM3fCQ94pHHI3nGEnt5uEVxSOmC888yNialsglB5covJ6cyRQxsDCsrwSqBd+2JIoGYSxeEzK LhrqBvlYmo/Q5xRPaSlx8XA2s+eUNagPmou0Q2h2cj4okfGBua0gbTAV/IuQZaIqtRa/xQeUoVRm XLUzMEX9En+Lv4PMjUPz18ypVbRrkqmxKwWotKSnL08aJxYjPvl6uos29VWnFBgHnApK3QgiB0Y3 ayCLNR+hO9Piq3IRHeK3AL+7Rz3lVWcmTWq5o1DXaeIRd7vqjcMjHaxvC9LxKspXGDrBxO/o1xMk WDbNSGx7zhNKrL0QZ/HNMMXOIQMYChLeXQXCRVjFp+6mR/Aq9Hx6KgVrAwF3c9tHupdc7SUeF37v X1hKkNKfcWDDxjI4cpnZgk8CJGE9vty2UmETgzeZ5jKjOj7J+b55+WxNSydFMBMlALsJV4XDq6Cj qZLaoE7ueykZZ+yO5Q2B3FhakL3aMlELbhluO5RZGJtSj0/BdfCXO2oAeYw3oS8xI854b98nOVOw 5dDMbs1ztejqClMrAtbou+AhUdCvcipiRMbB0FEIslHDXcJmJcsF4RuQuONpTn6lsN0uuLaijJe8 tou1iIfXdy5irD9nI4syBoNiYb++GTRsmMH3TnEr0dQlvfV2FvUOvbDpgAZPTvgP9qiiQBV2P3E3 6xcAViIK8bqVoCfMaD04QFn2w+zCHd3WE2LD7dgGyDNys/SuSw5+2mOiCw9UPJWeY/OtKBMItorW tLt8wUZe/hxTVimDedE9cRSq5IPgdZdLkWfhHqUrXzmGuR7vUMOJyzVXe43l4mvPztRfI2NvUSwm BEszSzt3sJ802rJLTvJd/fpyDg4DinD9sh/pv43hZYE5ZJn/B+a5IdV42ZLocdAFdB0LNDWQ10K6 rDQ4nBVbqL7a7kzuYhFxvZ5ORn6WGS7SWPFXRPTSjG0OtjapwJSjSHX+ASuiYrR4m6xgHWKyegmR FgD7tPpnH2JKrEGBEzWefAtae/E6x5GFb4Zpa/WBVvZzJpxy84M6/h0FTMWyHZYEvckOCvQtFr8g wKhE4JCdXKYZVkIpEQYCssqnIT4YI8zjl7VeJpDxbrYtMWo1xU0sXbGxUrIpzRUsAP9f8DvkAqmv 0ORwlnALsfqG6TRL5PY9ZC5d7LOTIUnRMxZipcZoGCbcHwCeJehBIHUiXH0X9Dv7AE19Z7B+plF4 OGUYm07gQQSK4eutQAa+qXf4yJIvSbQ1h0unoq9e7ILmx1DnJXf4miDyVrUBea3Puya3mLjKuCJJ Zh+xuod00/5opLHI5xq15wxQ99jG9tYxamEViRuPYZSeR5tAj+UsLpmzyy49IFxaHVSEJ+drClL+ DqooVhHBvhDUrbESJBA3Cz/fWFMoOG6s5MTs8HdTFqmSVd73U7DUY7kcpOY9QYtokvHSojwXhAO2 +XsZ2ZnOeLComdfDuSftP+35Y6gSSwxxk8e1xTfMUxMZbGHrCY6vEYkA3tOA0nwilriOWbd7kova rGSwOgwWmqi9Q8VkYgCJHhqz18neQsCtQt5N4z8Saeywcut5/rwIdckh3Bl9R2dy4Qx3/x/uATCx OCMVlYkhxF6j+hF6weAMBsvOErGUXnVmYwF5Mlyrwv9ZoLIabEkwPy+dKNfbMwKNtf6D+You4NQa 8W+Egcv4x4/eEqA/YOO13hQHKy8Ta+qEdT8tWc+TGK8GCgLah184lfiETn7LcK4QK6nHTXeVkDOj 1Mz6kvPVW+xf2b42VCQ1F+UougWt/6fzZf69bvgL6/OFQcAIZSFrcBIjiHRt+eBJ7OUS7y8FrWIY OZ8gKP4u2wm7WrD05mDxY9zZQUpVb5jJcTGELLLNF5aLwmeuzlKmg7VAwlb8r8me+Bj+F4O1Rwqy MNphW+ruqqP45r67R/Gq+r/WSl1G20kNyamdPfBCmIoWQ9NLdudro4dSdxR1lgillOeqocenye47 3nZyUAC1FXOVzFa/rzrE9Ja6Z6UMiL8HS0uSGqYJ8EbA4vJAaKpxjpJB24V1bB3J7opSdc55u5pq ueRIbvHHTYKgDlmHKla0pktyXTmWGQmo8ljcZjQcSESXZu8FkSL/HaYWVve13dOxTa0mTppXwkCE E0cTEhxaIR4EIeejr80/nLtNCIzdzs8cbW8L+p28Q6KRm+dh8SpRzR27QZqgHSRJm1kPUD+WBsav ONBBA6dQzg5qSqoYP7rR61rJltAHX8xbFUX/fVAHj0wS64gOmS8C89PFTEWpkfkXVu1/0NUhxz76 BgWlvDQ+9d/vyCnBkJC24ZS8vDZJtDi8NcXj4by7+iOET7GvaFAuirRVy9pdNaFt1DiGcKAAADGi vzGM2F9bjcGcXkeffREsAkVvq/gNO7ShdY80E0TeehOjpvjQOgc8WjHk7grbbBCqkcid4gSHWKBG MFpdBhStLECAqbqN61yvFfKfUjM7JqvQeEC2ql7h885ERvmhyS8V/2+baFv5o19HEHFngZBYlkD1 YxVOKjWTUo8dryl+08nSHS5EsosSAcmSeG1ufEVpwG3igz/PXCbR08FlslgJPAV1vz9TQIRqnGgv S4QtAVE9NKTHOuFGeQTHwR5txOTgEbnmPSJt884wlSL9+Y1KcPWlr5TOBO3K/61gD5CnpyLzOMD/ J1sw/uC+ZxeJhIu/LQZlSMPIOmM3w0pNYZFN4eG03UlLEzgBhYBLsTWYsSAGomIYQLNtL7p0YNTd AqfuwT1HML63UJzBhwCazcHLbW+I7DJs1Oo1ZlXxgrjIFAy2+Yw4/8d91pqzwbfhQiuiCTbv0rjE 18TYisfxAeLmdF9NGdm2cAMapCy6iGnJfaTM0fEAs8+3ZdVMk98jdONR44kCAChvY5fiPIt/RfIg YD+ILn+JFBKAsM1s0UehGoOKFx4R+gfEPSUByF4t23mA5B9IZbi3x8595JcURtGlS0sfdO8Yxibj jQYjgNX2KX3B5D35JmMVxpfXrzjo1AMo77FRRslmAu+Wa7Ylyi/6HppTyrZ4wwRKRISdY4ZT4y3p nVZAXjdciDM+3xjFkbQFOIA/koHHzWlkz3jiSsA9WH4U4nSipeNSiu49VXn4yz32ZcphWP6n9s5h BcD24LTD2wRRwZt6e9i7QWgppkc+hjZWDQZQVsKeXupucen+UBB+kanGUUEnj1JCgNSN1Wv4mTLB a1r8jziD2nNKAkDC/KqkqkOJGqgkz1JU76wWc7jvc0Hj6pBl468cj5Ang9TKh5/eZ4wGMnHJpnpK Zk0tIteA1Tgyz+vhzoZgUMWHL/32tm7jSwETiPDg9hG0tPTahzS75wMw4Y+hWOApAarQ5FiTcosi VNEyvjpK9VdzNbrYWcHpIb0+UG4ue9MxF87Lkjgx0Cjg0SoDcghY5CvXBll659q56lTbRurlcITn FYT9kPm9rfHjW8dlyiZmchnPt7ygnXqwcHEGzdZTGwJuw1UliAyxtZVFQAdoqz3s7AGgkg6G1uHO nPl52YAyE8ggX3LndvQnHVB4RUowiQIPwcoNgt9r5nJcCRcgoICV0tts8AJaJmLj42LAxs8puHSy rzFeItRbmxcj3Klq0iC9WJuYluBxV7//ubdisOI7hlrHU0gEZB9V2DaYRrb2KpcK26YdMPuRqveQ 6nmOaeLqC6CdZ7EzVnc7Ba0at0/kcD9D169Fkp9sDJ3ICpUAkeQKKYHbhpPGIwoDljNdLxjKWQa9 7g174s7SEpgcE6pKs5VE1gGqS8ftrlaU1TWOW78TZSr2tclzPW9cecWcq0dzs09z+/Gh3MXnL9eG LwbeM9RHZHGop3Ps3BAwVxwC30us+7zLivjxODTvKsr3un9q7OAqYLfbVMKnig1dauIFz7+SphTu dwXy4XBpzJwuwFbPXwCaJ+9Jttlm6nHNruHP0QMqr2NK0SPZ4BLfHlyHIkVTs/isyFpbUe437y9M EMdoP+HCyqi6RXdRylj1cyrUPLRYtr8FyxSyOkt2YfvZc0cwsdhO5CO+nDbKLJUIuuRoAm+xRdVX hXjNeIdCH5ULIXxoPMZi2eK+aaqn121NFXtur2XAfcRPOZfDmihSZk3vFanfBo4TbAJ5BNes8UIf 6VoapfUi3DG0lkNRX2GUXgHs7vLAWxhTx3b5xBXr9I8f9rhnrfEHWwhhhfCEr3D3gWftdQTdYMFj WjbEEo0hLQ3XQtcDwpJpGyg9I14rcLJqJ6vnnUz5Mr0QTfX0QCXNSNRmzQsAOP8liX8C8/8TMPaU evVnu/quhjCUSM6Acwe3r/sW28PVCTXZSdzeBWnBs3/CDnJH+xCRbU52a2W9ckKQnmblXr0/AdQi O0cEnSwJitssuzLa8m0tNC7T5K6WJ8HwJuMhJlS+uHgtWDQvG7NazeIC8MbZbaca3iDdnlyqppPD UHuhevws/U145fP9/i5sxXhTZ3SmwQWeiHtQT8jy4SxpOeZR3Oea/0yRstY3hG9gDs09UjxdOty9 tWHjKSmp9aX7dGTygQrw5IEGKYtHUQtYFuYFyhzmrcwOygK5bOyDBGr1j1R3Clkd9hkIRoEf2xyQ EQKS4qE99m2N11eGYyxtGUi3znW/3tgyDJPUj4YuMDBFQdCL05qG//c++1Przm9xV1nGw2YvTnI8 /GM5S+39mFJKMxaVZrcRxC3b5j93nXerGKgKZHLBopGi/bgbySKo4tODFXE03T8u4jpr4STiJPRt WN8q8zmUYJVU8OgckNVkCg/IyaWm+ghIm0BZPycbtatjy76nVTOOON/YcbtJ6y1TvS+5ESkYRys4 K6wOn0PpZLIUL0ASjcz/CEqwD5YeDbjBWUbXc/d0R+AJ1gJvcIXD0zcpaqn2qXwP9bF2gha9oDYY GIBg/geKmvp0TMcVD5TPLcn4oKW6fpZb1/m93NQ2XYC7EIX16f+Qk/vK1rcWCbc8IkmYCHTQsvbF AuvO7QNEOwEUUaX4KeIJo4FiKjrsqjm7L3i/LY0qieiQwR48HY+CZwv5WptZHRvoIxrT5fdoKqBW qVJz7s8sfV02XnlLFY0q0LXQKIXggR5yS1NzMqgzen2jSCBIz2dKSSYegYCxayAxS82WX2vMMWDU 8FCBJ+MY0Ey7qDB/riIuf2pQxLbIqOp7kwGitAjAjdE4+dS2hyc+Jco8hcA/AtGRW1UCPr7GEp4A iXU2xe+DITh6nthXbbfI8HDA6khXGQAIyHNrVyOAj9My5ZNRC5PACjwWOWLrjtgleTWIZ1+bo3p8 ZRnLWN8JbJWWI8cbMPftNmWTlgawWmRQrbCS33HJ1kz1lulcbCymETkuQHyhOG+fnJbiO6ECrTZN UEWcFO+OfpHvs+5CCU9rAfK2fJYKcOvd/olE3IBVz16N1UuFr0b4YmILFwe0aTu7I/mtYKB3wKfC ZgLiYT3Hy+dC3TNR2bqur7WBqZdQta5mhF/+1dlUofwU+zVbxArhCImQgLijPkRQ63/EOAZ1NE0F lE08VgGPgSPOE1YZRwhdR/+uI0HpliffDnwtqjc/L4+3ckwi1EEscIcVjxcDFBki9oItaUNQJ0iQ ty+KxIb0Bf1nszHNG++vQ+E84kb0WrHVpU96iUpglpx9j7m6t+ai5CZWeWI0GnSa7Q2/1p/z+Ck8 8pHGA9zL2qPmMpopYGFr8BfkIhea61X/skGR3EGTU0+r0as853nUxw2dCmS6ZDa2gP6yEwpfPR5R 9tTXg4gVMFLCgGSf0a4JsZaWq3kwNe+o7JD41h0seEf672thWFsMXmhS4Zlvacf4NxY4yhxntCPm bZKTgd4RG5YjntuUSQTp+yVgh0TaVlo9KYbgXZmxbbLJ60n3crHjLXOP5pS82YsgKGXDCYrXMQBD NhEec5cM8RAB/RtrA5MWoV6/PtsCIszyNNaqgxCBIo/9BDxTarwAWWH0TMYOxcXwAbFGKYzOqNh/ daakI9nDpnOp+gjwwfoF3wafMyVGGn4+Al++5+iV+BDell/nwMH6MgnDK17SySGRbKrv/8FToH5I k0q7SpkFgE3Rx0I+Kk40Oo3vbJyjC0usgBY7myLAdKlhZ0i8JZobEHP/lbmTuGxdw5DEwAFa6h32 ScHh/XGHtx68gfWx6S/k+hfEBORaIYVm6XaaoIBJCZwfivWtt1G2mv+5jdw5c6b5L/vfOCr7HirV 4A4XTx9HbJ5ItkStCqNVKR8VszYFmskIaHYR3FaQYQeUepjy+Fp50GeOzbajv+CbALc9v2r3iSNY UWyNy5vVjCytgI17cdmYoD+tAlvMFUczXjDxrHNVp3ejvrGNjSRC9MgRbGpE66bwF2GSw3Ir/gBP mt/wGuDYlvDM8xwGkJD8lNVNxN8eaKF+ZpsEuBkGIc/JpqKPCnl2KzgNbAzk3llkMuJn20xA2YM7 mGf0jvOPKsYDBWJeTa9DR8alQExzG/twaGPHjyxMAwfEHbkk/CnrsllFiWWzSAQl3WAZ6kCPmRLM PY8cjw42zUvFAvLMvutxpOB8X2nbXIGXObq4NI5Vu0sgVF+NAMng2UTQz766ROIl12D66Wf9tM2N RBDYzqigUC5n7uADSfRPKlhmBTlSXae4hLY3cmgYHibZjGCAHFaJ15CkGDCTYMbcsa6soiuOhFAh +C77GckZlRLkcQ7IQKlHgphNx6kPfuDQ9bmB4UFMswyfNYlfAPi+6qPYLaDtBreSHnjMYkEYFCs/ HOgIeEzD70pUj6uhk2pM7XEX5pv4aVvB6jgNyUQWDNhWi0rxcuFlSfRNyaCmOSlxC+DMrXwLGS9B O/WqZM5FdDbiOaklqSWzGVLBvE1qTpH8ZznZqeL9XvlI2b9YQ17MtuKx8dFp/sUbSOXFgQxDnQ9v 1vsoq9gq5W2SofygzSZX9krdHnwe3yYTOPRSl40OVsTBAjFrUmEk0KL7QkMv9+aTeXiD/ThJe156 ttTkdmyMf+DTCKXc4r+9SwBvss/1oA6BzY2c4Gvx0Cb5JwObv5VTiax0qsAXTyOJLp0q6PvEXVZP mzgRbXuo7BFY3g9p3w1EinOuF6uejvhCBPrE0HhF98ab4By8WCDdhdSs2gm7kVrFdC72P2gWqz60 Rjh+XaVKTj99kfVj3CwnIsJAVL8sEo0/aGRNE4bxzRP+qPL7rPXigMFWohFvwzqljMWFhLt9jk9F i17GPOqmQJ8rrgGCunoHsemrGOWhZVK8+GefndukrCO76cAGhXy/VUz/qtl4CVpuYWNCJT2Z/fAt y8fRuRKLTSTHjyC5stGwYpoeYZhTxvjKNcPC31AUGEIBUe0hNXZuR8vYA5c0YKak7MyCGdpx0vbb b74xSYZby4l2MezgKI7SWF2UjI/V7nlaME6AsgzHE2O+ygQ+0fuXpyYl7wZHP3FtUrXmsA/NJQyO joSqhzgn5HTPP27yGQgCt7yKJFxqbI/zTSh8jM73NHL0lIeecNMRzwlAl64gEXO+z6LcPhQAqZ2J KC6Am4PuKl6FG++MMaF6gUL+mDU+4dhLc/KWvNgIsHptCDdTr8pmbaO0epj6kRI0mp0bcYSsduy+ 9X0RVHES1G4qOyVLHZucw5chIsb1QvwEgu5tNTjLJjZx92+LArAvwPbZz3yzEkT6Ig2J99uzVpX6 xJFFtE6iNV/+bY7K7K45cmdtZM3u6CrR2QRYvTnGSz15xQ/FIHavicWVEl+6H8ttsMHIG3jK5lZN D6PH3aFWJ9EcOpuXvEYFDNz00lKDeL2yNKY4hprcU1oJfUAGldPU1/lDFxgBSUCBAwFHCT5dcRts PH54dBY44HQ37HEBXe2ueaPk6hSBTkZIhaYJxBQWUe+kKBMT8nLMMFrbOX/wt1lYSyrrB4RBk/k7 np1ZQ7x07UP+vWA6R4JHmtql43xB7q5jS7sy9LLYvWfStB7pmLfUAvOs6fRgXp3du03uhBAVPt8n QQp5wlghNW+iYz/cRhKlgHrFHftoK6dMTZW5jsowkGzBLLFnCpy3QLetJlEeOp1pqTJPL4i8JPFi aMSa16AyMyjBJmylF2aMMg/e4CecbXrtDsuRP0FCARXL4JnBm67DRr4Rmu7IuQaC/YsWZ4wiPEpS +S92cXXWEt3eElADDTrUt0Nxe4K82ptn3zPUGcqnUDItLBh7pGg4vCWnwtKXa5MidpGZCtYLXnEM yi1vSz4AbfqOkHc+UDx7wEPx8UwjLvxLxG6EH7j9DenqV67J2rOHWDjMLbWz+VNxisfCDhrR1WlW G7ZmppSyMIJw1jB/zQ3TiSiFrmXuIF7Ev/ujJZrTAb1rz98Ftorg1TL7Y+cAXOkd2M0elrk0Aidl TPUJPP2QOUunivrDKQbwhJILdhp1kEogh9raA5CP5wpfwp1B1M40EBDI7zjAFLWpefzUikG3H3YC 2JXS+cRMAjONzbb0CyTGaoHNcg1zxu6YcL7HUXzAoU7NpV/BqqehfwjgBmwIAcMd2gEyNrfcIOI9 wqfxGxeSQPfbTcAnZTGSazGxEq5YLUi1dhegw2eiARhMSOHBcy8SphcnHUv+gQnO5Z0gaxy/TdSo XiuXRjCVJebgbveZA1xehH6EweqyMjOfHV/dO88oongjrvB5RsVxUonE9RwKFB6si/uYQKKZYHuq 5dCv/AIjqeYv9rRYuJo/CHZDzZkso7ixFsIJRjJ9sTlSQO5V2UDBsI0oyPlSjb4avUizHQqnV58c jEkuk9UIszV2grOnn+voJI3rXCjTWJ9K4YfOFGDew7IvbDENO2vHvaM7UFp/lQ64BeUKU0XqRV0I qKIlu8MHLdLO5lV6BL2lqfRzQDLcs4xrQ7oBgoi18ePXR+ZLRoW6YvXyQhK75/7G49tZyQJfew3y 7D7nge3E6iUKzgim9VLZAfA1Sk5cnCMMXmkdWKIjI/iRe+1uMuNXnCoLKcU/mS/r+lgjUU1DBt24 Pyw+OP2KhRs+M3eNiVCItp+mmwca5i8uUxMrs9fCOO3lzLUekBrKR9L16q7xFzOyyd9FHgpDkNlR +TLGd/Q2sidn4AswKqzZ5Mnxqy66xie2TgaDtRmhru3x9OrIn4xBcV5Sh9b1G6mMRtSU/QTG5UVg 5u74HTdJwFsiyd8jLdhLTAuq9XkdsjdY+uP8euFv2yGOGTe4/1MBCZFMEQhLd2LhsZcLWZHr/Uco cNl0utq9z9p8yLbZbpAgoKonLbp7zpvY0VFswZyS2I6+AJ8GKSHuqDXKswrAs7Bb2JZGCFbT6g+v +Mtoz6ROhELjdEMw8azcamO8jTDUtTJrELXIpGPqXPkNzCnYe0JMQxWA4mjp+cBsZekBQkKiwJ+L auCCehdrR4eoyTfFJ67V5zzfhO6rTmPlrVCcqNAa8V/3S/q9T8kSJQFBhxFS93vaOTXJdlWe5oYb bx7k2l1uXnygqc9h8+AeJMxBRros+TZipVGFhzlyOepuUxAXXkitD3WYKPqQu7+t9q54LPd7LaiL njpR615OQiYxqzfVBXrP+UqxtW+PbvFHiMcl/VPuXNsukXM6fvo88UGYEQiYO2rzWKPCEneakZxM WHAY3qCjUl4xLDlTfRIOAyLTSNC/krZv61pMFvWHBkWL3b5e2/RwCCHfV+thmLsEq2FkA01mKi8I oPQe76p24/zzpENYLDjdyRXr8LWLuvjyH+N2H/b5lm7vUSOIgNbij7sHOfuP4rqMw5F4JFr//MoZ /gcKklt4nPd3pU60/0bBBZgtnlIOLgsljE244CpbaiPX6RxHMX2ikP4ZQf2FrhDFwJwriP/kKd/d Quh9ZeOIyGU4NUdS7TR7iUKV9ZvJlhrpFLlJmqsBMhrRSzAvre0C2xKqro1CBpc5203l6eMurV5c GoN6y+5xsdHMpjU0JDheAChhKa8XsZT0eaA5vAXf45Kpw2XH63HpoKvf6lwU2y4TRf2lYPsii94B h5HVe9SVaob2WiVA9A7B5r8HJWaih2hP4enj7yLZWNrmz4/Vl2KgDciPypOm8UIq/2YdR9GT3CNb 2rzIfqsAQR+Mu06iMoGuBUL1iAor+ZQJ6hehngkEzmWyEualg2tJBXagOWo7AfrL6DLno1U4vcS+ EUHCWT+FNDZBq+72G6AT+m9zNMPSoKNrmBh+93rsnnvXjL+56XUY01fkpHNPQgxFdPxXDCgZpWBb jlhJOD/Yp2OjxHdnmq3+9pMVSv9hhxo8swfrL7ehslv5b06Rt9iD/Ly1AF39L1dUDbvdM++2bYZ2 UrJILc35HIMryXNdebctAXSUjrm0txZSIaiN27IWXJMu0/v+X3LSICkb8GeUwgiA+SGEnT3kPAZm 77LIBh+SEcgA3P/26UMXWWCFgPelTI0Z5d2rPEAheDLX8gD7Xty5v7pOFN9GhCPI4lxt16VsUySY ZbIs5ACH+gET0eyAR06VPhg+1XTYdBACoqCsBlTW69p7T3yaAXgGURgkKApi1yMaktW3p5q6lIc0 fIms5bIhijKcsW+uKUwgKHZWhWsoy4L/5Zw4rg6e570S33p8pLHzBVqyUYrwZlFYpVbwGgs8MO24 Sg6XKmszqDq9cEu29/rKwW+okYQHDY+uyR2yeKCCVgv1YFUXmZ/fJJbNl9FI7aXJFErp5LgyLIX0 9hnGWT4bzmlTDp/1RjJRqQUObSc7PodApCx/d42YdNsvEjkQHNJaNnY+VDjMylAtAUX+1uENzemG hxl9qgMnd9Yqt4E93887zVF3jcNoDG9i8nYwcoozAR5r/dndUxfLBcTMqubD5tjogc5zSmCO/CAH 36XbjAd9+tKVGi6ENeroLtsTJ+cp9tGT/KzQrOl7j9Pekiey0X0DBjVceOYejUPpp2AY4oCjrhew u2fH8r6Nwz2r0x0OTqOdlGcDXo7CdV60uOXHMo7A5cmRWh84FuLKjds7sAfNbGXplVvpsLv/Ui1A Z6SqI2vPBuaCmf6coIYtWUCg5hUmvMIw6tXoJrURt35lfSyoNYi9nKE8aEXIxtLRoub6MugZN6+b ESEyoptewHrDIyFtJ5v2yGZ1u5MTXH18g1utVR9YllSiqb97eYvPqq+r8hT0uHhqIXgeU7tFa9Ze mKBMHQaKwvuTyQgMOIJ9cceRw/sz5yT9RS+ZAxOQwQL0nzxPNOjr8b2hP8D22jc16gTROyJFpThu efh1uTt9f7yW0jhjDpA8RoSgae1TBSGP0IEP1SNlzzSIbiCcwwfu9+1Tfp6V6n6jS4bVjCV0pKI6 aI+oEZg1iSjRZgsFzAkkfat6ZrDoFLZZjlG0q3z4sZ+CYBproa5tAsF7jvPdCpVqI2HG4717OWHw sUFQwsh+WVIk8BzF1R2C7n19C6FSiAx44dH7bPlK+BOiAE6qGqtIfP7t7FikgE3txmnSvKBQ1lez PSBbSGcORE7QoTSmThCIYi+I8rrGj26j6HUyMFSIchAdfGVG+xAWb1HlLTrUIHE4bgWlX0mWHD0D rqF5WwT7UUjvHaK9uG0iardgKd8+CjmRmuoMcRTa2sO5RtXAewZ9PUkUqKU1ku/L5+P3IMOtZdvi s748CeGByuL9/5oioEVQz81jCgl+PWeaBNKvrtBBKPPIa5ldBe1024sx5Kn8g1HKX8Pe/EkYxqyY YsgEBHxh/WjZj+TCXGS59aL5UqXv8tsMFOobSjWEds5a1uCENAlxxRw3BVeGxUiTIHGBhq9z1STy rgWh6XHS4pzFtjMAZ+FvxbsjE/OMbbGcvvHe84+5lLEN9PQgNQLnpPuwfyCcgMxzfMxo/WSVW3NO 7xXNVIeZGBzeI/DDq2wtFv/H8rwseFXMU7s85Y4jCYGDwtGBAbhl9cg1HFSIFMBIYLGQ5FehAJKe N9vphVrmPYk89pSkIIrC52QBQGZ/QKYkYRUU2IGC8M3EWmrmwybUcTUcOCdp6hDDgr7whY5qlvJ1 TS+u+tJEDY5pG3Pgl8eQtYPiM8TubY7yAWrXRVWNkNN5GhdUepf7Yi+VUYfd0GOMSubgGWjT974F 1I05PvFNG++87akoSEUgrKnNt1PsO+MpbHo5hmleLUur1GlRyIkxlflQWizEcYL0MJ+JFj8yWfMo m9C00gY93aRxtYN8PiIF7O3B+XSxH9tma94TToUATEQx2YAtWvsEl11/LQXoVAfsxx54g/+T9vB4 JOWhi4FumdtLsXz3uHECb5XZ0cuzvCd3izbpCPuTEQDShKKJKFcD1U+WFH79NmjoJHCNm0KOwiMa mlm5QLua/gk3JVM/CsloPfEj/2CKP0aE0cxeu9y01v3sKpCQGQ09m1fCgR+jCnC8phoX44ewhSdV FtJD4+IWAvr1ccQRmlG74dR86dcY8W74Y1bgdAgyXHhATYvxrlRhOocNRQLQ2QGy0sgYiGFhFYJP 2zNPdvB8mYuM28tFo8lX8PLm60X/2gDAXI7UP5J1/6kGHkOQCDkefrSDBuiLmFBDCY7oHSGa3TXN /Ahr8f1dULQU7wdSY+3GGRGmQRaGo0T0RF8FwrmmvsZTZlOo9H0SLGmbjy+i0/TWqWcTBm6ooyc+ dhj0Z7+gKi4hBscEXYkjV0Jgg1tFXj7YmkleVKYsh8h6S4M2chsoMMQL9J4lL4W08qcOuhVriuG7 P6beQbHl2OdfEx9cydi+/CUJe79GBJMSM1XE1mzeQy39hibl+tQlzVUmWG6anXim2CZaAnLdFTQU o3MrZ661NpbdJXh8I7vgnuDcRd0+vz7YjtOrPAr8DtjmnA5vOclmyml3xXWfx+kz4RRvNvBlaw6P OcN/4ZmcYMx+yLu8jeQpGy4iGSWktgJZBfZXNPHPPGZIeOn7xD0n+Y5rmjZSQl1Tp5fxsPqMmJzJ O43FGn4W2APEj5i8djzHccMcGjO5VhpvksNFgd3yk4dy4VWhZaFYJZLxiibiL+tXNKdZqasVLhjO pj4YHBpL6xgEA8QE2/2QgAKGKERUhlc5P9l/cSMZk0AutfiaHoxQbO9PIu/O21Df4Z7F13r8FsjN q2LGA29MgrsZIAYwRpjANNWqkHdgdN9X5Xro9n/BrOgTwn5cuN1sdbgct44iRT+MFBRXDKe+MFqY DRni/e3soqhJQXhNtWqYE+0JPwRG9nSEkcrLHOc8TEz6v/CXzEjKFMMncU3Yyj+QkT35fDO77k/A QJQiiZ95UcfEp27UnQ6wFWUX2/iLskvxmy2EnQbiAscN3OdUKHFXjX03aWZN0yJSvV4z1GkaCOQh yt8J2pGWkPV4X3258qAvxhJDBcNVsu0dTvwhJoPJpBySUl8JYuZFSwmB+WszptX49S05PqUt/Cfh MrJSVNozt667LWNfSzPArVFHfLYwQtSJ3tol+EQSWh4uKeKaNBJsbMXnin4GhIjRZXgZrDmMcvYX Rq/r5J+qB8DJrkHxZSipxsXEADYgqH2rbWIXFBL523siPLdmaL83WGhVt23pVjNFG+AxdhXikA8S e1A5VGAyxxOhUmspL2xeeY0n9S25euRZ4ryCgycMc7a5qSS+Be/blI39I36QgfrAozJpO5yJk2ka ybYXJIJRI23QcPOG3A2WKjm+LwxDvrCG5LrqT98RA11VUABt8NJdJ4JDoSQtPP5017X+xa05tH4v sDiTlJSUIl26HPJXubuO0ULvSG4EspM8OlGNNnK274jVaB5q6o9OXoDQhPmMrilOPdmIuPq7dwEt nxKGucabu7vdZw== `protect end_protected	mit
benjmarshall/hls_scratchpad	hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dmul_4_max_dsp_64/hdl/xbip_bram18k_v3_0_vh_rfs.vhd	20	103154	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AbrLtZEWaMZ9QRIEqn+KbGJaY9tnAHwhbFbsPC7WH49ehpa1EbqXv+qkeNRGupFwZ63XKanLVUyO My0fDcdlyQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jBjvZpZ5ZMxrEO8+CEfz6CEl8aMhkYM5vXXCdl+QFohneB/4ao6UdzksCSxNPxkQX54YmGSOciXP wgiPEkvihckzTQ7V+IwmdcU3758CZsJi1jYV4WKld6YxfbWBrziJy4pEooel9pwm0aG1jMx1yNUM erFXjNZfwKELIgXdp9g= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bNlKYiiGIQP+R/ChMF9YxWObkJMdPWBzZKUDypAuNCvFSKj2ODeFkzLXYHokfw+rz7RZe5YojYmq 4UkICxShbV1k/N1YYli9QKFi7npsW0xHaRa8L0tSoNNqAKETg1msjVmjBV5kKgQ78l19v/4te7qL zUqdthBriU3NcZYre5k= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0gJe90X6qrVRqoGU7iK/i5s05zq/0GlJ22Kt2H/04aXbES5oZ4I0aGRfiLSYUCL8istn1JleJ/n3 1/LRSIHwjesRoSy/6j9iedPDLLSSnKq+N+ZcvCJl8gg/L6B9ChU+h5YNE7HqJVfqJzqKWKPqsHB4 WVtjQ/Uh+QwxJp4Q/GXnPw1qlnDs2s6lJ8EK8000R7Any16QZ06T5S1IW5s5v9bKhWJj2Oj7lmWo 6QSr9mTUFxCIV/m+pXzsIOsSgFWqsBmD8jksQw5AorgxI1HaqEa3+sl/imtv2p//6lwEVtz8coiR PUlfIUpZ3ecBYh1Zuc/GrakwiRgEs/Yjfe+jCA== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ux0aTH3zrSOSGrjxNBhNJ8nXWhxNzkLj/DcKiIgChJ1nxm8i4YMzp0L+VdbHtn6L3ZPNF7NTEh1P v7Gcx16JuF2FM4sw/t6m+FCjX3oHl0zUFDs/HfDB1IEXz+2hsgoR9SYF+bXbSth9Ql5SVw6WlbpS yFwlhS2eW7RGdfH7yFg8yRwWXcYySMv+L+udV6VzSwe0SODgbmC4o26VRMdm0RBQjLnYxl3eT+4N Qf9DbWnbFLLU2LtQWORMV3hNidJEmt4J99c08slF3izsh110Cv87/wiU6Xuvi2AB6jI3wVkno8/h 1xSxQBnRHm/fJHMh/8PrydoVk8qMhMXs9UM3dA== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block A3eq7CQ1ZEC2Oz4Co0wE9eavdVVL5N2w7vnxu/t08WjNVvgkDcorbVB3GWcUKigHFQo0FHxElw0D PA15/K+npi+dagAdVUmv5cfV+KYrdhCLG+Kvl0Tcm6fhXM4RH49frRlov9a41BctZWlMEXzlO2Ei 69nxF8+cDN/RPLjSUoKp8oVTX2g6+udi83fdCBYaBZQYCaaDSNeGqephcoL2zlXyK7vU9KpsDUWJ oZshHV12Yw5hL+4YuSmKv1aODQadN1UJ8qyFc0vRYTAqwP+hcDUwxiR48olGBo7U7czJnFk4AkkD qULDB9rPKRIK3YJacz6Pp3GAHUDGm2JO78Eg8A== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224) `protect data_block JcYdUx53b3OsTtOdv/P3/dHcfx3utNQitl84Eb3aQ6aN2AhKiDHBCYuvObX/v/9/q30o29Voi9Xv 1eu+5HrxgmBEFCpVYOVqTx+/1TnGsOn7DKuzvOHcne9bSxaTDrHQUCa38xlkHitY67JkqOSIhVm4 jpO7JF5H+JCbmXDt6F2T2wcpFyMe6Oyq6RJfEQlANaFqDnOQOn74eKDH4FfNR3DAsyf+4EzHf5OG TW+7XXmSI6vfomJkezPGmHNVoROjvgFnK7TnF0VmsgNYiKlql/PnEKKsUxo7PMuYq6GHoxcRo6tI +AJMZXAcc5avne6SU/2mOc1O1rYlDfuMOYM72e7no1V5trXotFkDNz5Yw9t1TNO5PzYih/V3YVbU NDBobDLVy/wQ7ecc0PsBimCh2Y7dqxU/EZO5RSJamz23VZJzVUVgJ45yBITzYoilSrt0WNdaFHyC PWPFiPnYKP0yDw05pHULxNgTnxK3YRDelWlT8Le5QF60m/HLUi8Nyi4fLPTjArMLSc5DKmg658jh JSjyTrQq++qYQaFFjKBUDtVvAWZYVhPnCexdXjRceDsgeTaL1yHhb8dS3xjv6QOjRzHBL3HR2Ob5 H+AbHQEQSXdGVxRnFCXi/TKUvtom8R7+JjrA+0H8CcmsD19UbQmxBAIgVidUDxKPApBiSOboEK1x FB7wxHjCEI+8HPUeIwoxSg1FWY9CWrNhv4GbD+j0JemUcvG9HF+3zIwWbp/5UG1Z4uD4VYnIGsT7 ozoOFMVqAbZ9MVvvKWapv0P5mEIR6VlYk3l75W/7tanWiiOn2mFXHWzb40Nep2bXDj+PtAa317DY eJIwtVGdN/D22e6H24LqEMCT5OepE3aFof4S5dNwpe/x93UfOQs30Ddd+SejlVq1yxXLn0H6PsBG 2LJDA1F5NhqqlcVCkAuKwjG2QTvH5xG2s2mBjJsZDcB5mVc2E341U9VvVXgaof5srM2G8VPHbjwv DXh5h2kfGC+1flf2tSWIBfCB9zePvwkF/0HWgEUaLfu9AKO9sJBs+saKvXtVjYY3AmDruCCXM26z hl4STPxaAahx5qIMIXOmXmFBD9wypKP7t90uopZxOSL37I7VO78QjxQB0+h89IrOPr/h3l7Stls3 ewOcb6q5Gu0IOyJEW7lb+6eXgSWd6x0g3hzg/N/0fHiWVO+zcwfulD3tlAEoE9KyD4i0vdFlepNu nehaW4Kl/Hhl/1NzQ/03nZP9nkSMADlhZm6pW4XVN1+sZ2EXsC3fe1zc08URdBUVJy52cj/GAK5+ 2r2x64XO8C9VxmE1bQzv8MFRwuIYwXfn5XQLCu7rRvRxHn1nhqdbNOfyQkaftCvt6pn3YYMqCEsh NaCh/3weMZZ4R+2N4RQjrFQJ0LGf6cr9DluL4GBsTewvbZWsSk1RPYOSofv5WBejf1lv4vjZeYKx RT0N6mYldxbDlWR3AdlUyhsionLdPrjCVil218uZBhEBmIUJjEj+IIixWvDe9zXMdMXAfVeqpZe5 iqQSeghvfFX5u+6aI2+Ysjs6Ee6x2Z4Sl4txYDlqsF71hPL2hXSc6O6Lu6rePadCuS7gF4Rym8ap yTKLTCVQAgHEZym5o0HsXcbzF/5aPPlp31wgnRZmfNLo2MAbQRLWMxImz74O29tn8MGcexq3D763 RrcOOFbske3p1O7voWsQMf3AsMCkdnbqqLGvM/KVFvjqoISK583P/ZBvCj/dKJWuQjiHORGHhex+ CJk6OvfiOuxlB11yDfvQf9E/gaw2yiIbz0M7scZ69+/8as+HhFR3umpKPNlaPOvlqBl73MtouusL kxQKrCgQpSj7Qz9TERJ471PsJouLReRBseMZ5wZBc9oD/lblzy0p0qnJaa7AAmUfPxj6GfEm2BtD Ltq3GUYuAqcA5UHCxOS7a4jFsBN3Em6nYBPNTjIQ1GoTDASpjgEbjJ94V8PqXr46HFPrZbhAJoh6 BC7jmwzTPL1boaxSsIHZiq5XkWjiG0Fl2kMRo9pnxn2Djx1GRrzI9JCNWjeGEje8mNA7/sMq2xGf JoX60sufhWSY6pdJOLeF5ykh3P46LEqWul5krASGOygQ8jsElx0mqMqjwb+rcDi+Bjvk8Mpz+TMB uvf2Kp7Y/jjNDWbMbS362U1Rz1ik69PIdnDDFhoPs6s+CW6/XvFssTPUPaudKJ9nNu0oEDYW7cjn dgkTk8++gdo8oLTSQtn/RF2U4FWmN2FPMb9oDXTciVWpMl+r7AfNJpuQ/2qFis4h+iRY615JsAJ7 NrGL/DTL4CzkpsLzb44Im1Le6aGOw6z5DZBueGX2rWkGPbDzW7IdyY0X+JRZlgLcNV0VUYOjrg1i Q9UCKpY7g3KEHrFiBjrZkPVrmQQWHqhyiTEAjTDTMgaxk5M5wWGtMAe9erd1WbNWN877pjT6GkKD oR2tonp7V0nHHp2Y9wkittxj4vvtES4nMKMle3rQNn7xz3s5/5wYLOcyKn+J9FybgXezdTbch+3d nnmF+yZPBt4R71KvlR+NWPI2QTnnFME2T0xXQOpkX9Rm7meHqjpI6cUHaDWKNDxSbZwH7ABw2MZQ JAFoCu4cHJXWp9PzgxPtuaDrEgxrisO+kyIDzYu0bhr0sE1euNGSHpE7jR2flPgvS3d8F6mzkSsG LrhGYr5DYGHY3XyRT9mbTgCpgq9+vDOAHnOPh+s5IK7xC2BcD/aL5NLUWbvxtaAjHPhAVXoJdwup RK3PBpnBswLbjodqVTjZaL4FH79yg8rOmiOGwbOcEaU1+7vhBSX9+Dk6xqZontADrIkL/mI6/lqc 3Ojb8VdJOdxhWKZ0w53OFUYxCLecLiCeye9ZFo6Uh6ZncDqgz3jJFTXhS0tH1j5aHfXiImxrPp4I /Qmpiw0ZKIaqkGBKYY9368wMcMQNLfEms1B0JJsmahj1namwvs5DE8cHOO1LlHvPOiPm/qFRWTsp YULmolXqQN3/c/nT2N5bOilFSAj+w0cMfxlWIsnGtGt6x59GN0AsG8PvKo30zEsrjlGc5gii/dwv 6XUuMnvKl+CoOytiFqMjMFV2IaP42joEd4iocd8r/iIOf6IYliossSyQRPFgyMTvcEpKf/AMNPN4 AtaJ8dUn630dEokCmuq1ydM51QFUmf28+9Hy7V7sBhKaMz0J48hve1vluXF+5yy/IpIO+KRooQYO V0mXcy1Y/RCsmzVk6NKI70DO7/CeSJbZVMig7igFkjxDoi2NzqRTkpd4zAjDpUnIwfjnXZBhtraG VjPyVRAydV231L3nsz86ywAEQwWGBC7je45ybk7MjxHAN6D/lieDBBVyq2DVXo3qTL7bhVylE4CW uWfebqqYrXBCii7/pXCvLhvW3SCziIQc8S8wqpaq+J3BoH/fnmtv+53dEN2zhD2Jrki5jpxVMNWH SCaBDh2r0jwRJ4zkidB+kCuNyteD9V6rH5a7BbKEw/PwqFZB5vQScCy2rz8LJ4lMvDcl937sCcXW cpcm21xpoSSrEibBkSeZvqz2EdAvqiAHGMzjdDbfQXMnW/sivNDSxFCxvXndmzYZwvOUArLN2t0R aQZwzyfYWHVx3+rGhSePGi/njGN9N6sBQA9Jl8EMOwt/2rTVzvgNamWDldYkkwTKdWN/pR9tt7J9 y6YlakfarE3ffId0LW7zpmneR0naXLxJBPT9GqkXEy5aYx2UzAm50SWVM2Pbm8i/s7JQDfBSog/J O44R/R7AEHGp5iIRokL/fQqohmHLNJmc1iQ3Ne7fAXlOH5MOgBlbbZyTy4PQxZ+1dJLhSHy7aHoT BcQeS5aAZrRMtoGRVL9w8dofqnynherR7FMfx3nLQlUZqgKvuzXIRHZEEH+2gZooyUn8c6z8r9/W bbz3HVmF+J5ytAYVq6TAm5Jp6bwZ+YJRaNXxiaqQTWLYDeyamHQeZ4PVMP7Tel0iibLAKkHZ/yTM L1cnxFm7TXC470HHRqomxUoDy7YMsBvZdPOwL4zTCDupNCS51ljfcwj73VPL+deuBxkEeMlh1npP OVNqxyQ2K3WUbFFMZaCcf9NI+db6FQAm//ghHe1mIOJHwUmAUwnAOoYKeysyzLQiWF66UuQ0vHfe oeeb6X7UmQyIitKPXi9/8vZo1QMrU3bKeUOfv/Phvaz2ykHcnLaexeXHY0odDTeA/wbmLLMbnU1Z F14963JOnWa8EI8xVIBOVCndXGs7dHcGUBecRU6D27/gP+MIcbUyu+MomX5Edpzw/RlQMeTRUv+X gVCepP5hOwpqNENL8PQoEd1+l3QN+CmDrpqxKuDbMruCH1klQGi2KyURrk0xW3tvRx78BzADC6z/ e4krry4RIbgpjKpCMZ36KJhZhOJ4XrMNQOASJHrs/tvs4uubgKfELrt5ffESa0A8mbpQBU4diU/O jEtRKd4epHxn41mOiRYaHTqpSDWcwv6ETHyqceJCAzmPi5GhHZ0aUYiz3CIV7bOvynVTC6iTkNvY Fjc16r6Y1AF4aON5OX0kVZO4WQCBVK/j9xz+kFdZtK0WUb96KOXdn8+99oQp/XiLXzlmFCTVa1hk YeOIbueyaNdKmfjdONFE0ucCtf7MOuHzR7+0E7n9J1cqzYbsW6LMHq0kqwSrE3z80zKDhaPL3ZST V89l/yh7jw5kkbSnMy0QJLDrU+9YWKdtI2UHS5hLThDdgcMhLv8XU0W81bhsd53nwoI/xPyUKmee lueOrrko18nZgmGewHoRSJErs+j48xiYcWr0OGSVq1E/EXQp/I0rnG26R6ZMDUS1UlC0M+yzSUKC KeNa0JnstdmEiAcc2NbqwAkyf6zikHbOmZu7fq0kHO92qH1uIsXGUtn1PPV//e6upK0jNPwS4JG6 W+fAmEd5Wz/lmsUiSgf9YXz44Z2i5CbWP2RuFFTBNbyD9LFni/ox6MuVOkBxtuFhmstwNT9gqMEd lDbiRGAzlHSBvDfYmvS6pt8YtlIsL4v2RdpKzxu9okBFcaL4dSPCNv9Nde8Cr8h7DgZ5ohreqfr9 r+hYLwBRTUd7nyROUSNYtamBNa8gFFkrWX4gEkuCTz4RW9i9sIVfKRQJ6QN6IticXRe5Ik1GzcO/ AC+Wv6GYuGFVlU5ymWRhL//1GQ0aspVTyq27DhWucO1AQmEH2Le4QTUJzg1zzS2qAIB0TN1lfzRV qz8RrNO37JkB0SfFFeqMRwoEpRkx6p41enKF7KhvYyLK439yo37yRaQtdIgoWEjrGq743/rj3eMa XfbwzE1IBPNONtBtmfAm8RhCZDJyGluA7z56GXCnPdm9fNReTlz7L4m2BfO8oaUUr1WevXuYAF/Q HrxDyxC6BKRD6JWGGNRN6x03NgBssWWLrfVqn4lX85iBN3A6pug+7r6Y5ZNkfKU8FVrbuOqsHlBI PAaZ0qYincGQoNZs604N10cwNrizRdHbbygRGdqZrrjOX0y788Fa7UrL9KR2mtaO4x+emY/LamW+ /GUGaVhUYUu4SP0mGdFvy9IBl7ORg9VWvzGPQArn2YJwA+a6byIv3fJkkn09rPQxk2EzeSJ7VdO0 2qT/qYJhZoOb0fBEESWBEAGYed+4pgpc/xPo6vdGPYRmxQOcevPZFCuS9f12/LBx976Lq5E4GdKE BnfH9oHmho57b4VcG6afOLk4VfiqgDpH0oe8+09JtJvIXfzbAHZuNc+OPKf1cgMv7jXQjMhMwkzW 8EA+ZRCMwXy7HedH0b7Lriy/zl5fVlMDRnzmi9cQbE6FPQ8KWLfYNK7tU4xsTaKOHOLDvmuGVpTH ePdwPKG+N3CqkoXNTM2mfLtow7XbNKflv8klPybOpGPRLXBNlQoXyz2oxIRPAPtIHp1EBciJSDaW nlm+7Ykx9BI4mAecCUSiyCUGdOhzIA+myCSX02+Q5R8U/4PSFhNgbZo0PVJSs7xBdgq23eVrYHPl EvhwBx9wyxbasow6R6plTcXdLVyxaVVNat98d77Yi67juUARbex2GWyi/VakJtF47wRT0izyf/fy B601vCy+lGibHhtljMWAm59ahjCseUxcXcY2mif00YPlwzzgR6mMzEBC97KyNB2bvknFAvEXENP3 1UqCTPvZFCzxiiO0TqRi2Vu7SPI7RKcJhzh2gZSXBbHjUBtKheRR7HKqdQBYG99XmSWwg+DOfq0B xPCoFTLUzkSuRQl3CWs1gSCw4WaDaN8INIFw5NX4CPiQtmu72WOpCEjqaZOLS+UFqQX5i2Z5lWMF KMBLc/2dQt5mw0aXUCDvBTgkpZJV7/hejuiGISy5l3doCfteWxAplUsqitu+ykMLdMjqIXuAyFLq ETohUWC+tHJ+VY0kNxhk/1uSSlzx12cvV/z9lic18VYylN6pzktvG+jRrhBVo73eIDgIIv14BPrw I+lptJAlOlGsafAJPMuYvP9Fw5WYky2Y1AqW1VQ7a/TfAHjn01q02r2Db/DtzJQ8DRnVEsNr1rnF boJhSaFcZbmi/Kx4/wlSQBpqA+AJWAS1SP3eDPdv9TA112Oa22AUIQvIalRfsM7LxvT8eCgi+jy6 XJ1azPffzo0+yjdl1ZT4r4RQ8TB4x2g+RAJNx05n1M5fXymF2Y/YR5X17uGfyQC9zuB7kXZACMFQ D+x6zkLjhZankOAqjdTeikgRRitfIf0urJf9MgP/anRKHIUiG045w6kykistBjUIeQ3XmRT6Xll8 KeE+lRMdmwh5fpGykkGVqdOG4syihTbZ48iNXfpv57sq3D7V0bWkIRAh/pi51PQXWQL06zUeO7r/ DnqH16ELZfkt9Y9+cxFiHNVASWV9LH+ytec/7jJilZovfl+OMm5syDPatNIjxS9KkAVITSJTo5lO J2usU4984wQ3QRmJW5QHCj1tl1P7E6aVVxBnNvUE7+LbULBIM8hwbcwsnYR2eGZrV+krufP78VXy b0YVkqUVqu6QPS6AlfPLtllcBMKY7o/ahkMR0mPLUqwUTOt54NFhkGz+qcX6B+d0Via9QyD74ira CU6sVmDJkm7Ce5UkQz8cYFZRQ/w2LrT2Ed4/zV0s44qhChpbDKHN/XLpG2k8PWf3IDInJpR0J/HR NCkInRjOI5skGW48TGGODnJpfi1vUawK8EZW4fpSlSQO2GYUaL1YmiyECRD7EfD/ag/pW5ecJHmt UNqo676wBpztAKd5JcFwFnNLA+WXgotD1W4EbO//gXt/rEJ1z0S/L0CDCtVyJK0E4qJ9CQE8NxJp wxgdNgL+Iw3C8MRK6ty/XYIeFSvudQ+BWxBp5ZVdnBYAGzEuTxES5650IFL17dwAGQ+aTywCXI6P adhoH8ADojBD9cN8qOaBoLI+xOhY7BFeCrsdRZELLmDYHNgSBR7P/iMoewh7mHqVkzdXGq0V18PM 8fR2kB8odtL1WYIzgeoJeo4lNfL30glLNQhgEQOa/eaOJnS8cZHacut338uG6+8Fs2FEjy+aFHJY ETIWZn+hnhvFaZLhTyqQM9URooPYhJ5Czpj/l2RvPed63LMNULVRalShMU9+jNbPxeYxYOTzQ/rB f9krblIuZE3TZYYPNhwldp4cj0ggSkjdf28lF3219361YkXf9J7ghLDCxBk/WzcTJlWHmRhp/np8 mWRyZsmsKoBzBdCamBk0p4QkIpJJRvIZpc5+Sso/OffOtwyXjjtr4hYCsIXWPRAz8EjxUTshP2QR aSoKIchtBRHpA02q1SEmWRSs7OMDm8uXxgN/VaXhaPa6wCqbKDL0fk8tZaP3xxSWKU4vuqLutX9h Dnm8xXrdk/o3Kvy61T8s3WFtVYxP0Q/o0vvlZ1Hnrobw7HxUxuneE/bN1QDXzGVTu0UrlGYd7Bpx qtkkAr//N5c4wlMGrzT8HYPzYKLG6fpv3sVxoRPZNmD3Bxc8I0+/f4F+Q87NIisF/zU0qALx957A LufULMilHM1kCVN4BY7Q+LB3Pdn3M/bZb+n3vzJ5dqI8PXZs1sm2Ryfm672gKiOKHTghStPmrMzY 5MLrmhRn7QFHYv6u1aQ/9ETQDgaLrF7RGwoyVk4x1cdlw+VvPLV7BXjUjPsI4e594MK22t2/QiVF tspBL8yFduk1taZhJ7PDwB+bm7xTWUWC417C50aOqQ5H5A/F2m7faSP7g8kRlqytknbkL5pRol06 MeBV1jyUz6DuDyf2plkgn/DDOIxUdOIw4/YyJv1VZ2emWnkTKlEh5lCkVXy9H5mYTKWilBQ9zBAo lUsNnDI8aD4S3z36IW7T5AuD+NQiPyg78T1QiwpUuq9hr/2ocrU4vhexSz+cP6diumwEQnzs97R5 p379+2H71G5pQQEM+KJiB3nvMG+d7EqTDH6U+iLtCpvbqYCscGkAvGQ2D/uwrK1I0xFQ/5HM7QPS zUTJibf5t/XIH4mvjKmGobAbqZkRmPxfCdTk76wwpy8tFca2/5yLehDfE773G1apqZXK6DuDySNo 4RzwtVJLKjuVl+wBts4y3dqY647qoKr1lWi0Nyl1KIH/Cn3Efv5/L1XjjGj0L9UxsXpxNcQbrZoS tbnc6s3M9h1YhYkLknJggmZ8y7elf5iKpzrBvqdeltXAZ5SD3xr21im5/RCxsOe+JA9ORkzw2C70 eAsPcBt5A0WqXqSQ2xbvPOXHrzgjrLlU+TXmAoCFM1i1El0Y4ylbdaLusiLdAM4uwsPuc5UCxoy0 ljVYY/RFA7wMbK/JaiKALb8gUpdmGTs1wfJgxKIwAM8yZNS1klu5fJ1HY7JFsqF62DJcivymTMnM nf3gCJ5vfg+LoAStQKYKCgP4Xv/jkPavOJ/SL/cEclAum2Ykz/HmFCBIC+bd8u7yT7W5SePoxJEw KEgCpNPn27kQTJyDgYWF4hHNLKf2E7L7AR5IHw2c49E00gwuW1WuISObl0c5aZgltrb60GsYxvEC knKA1oD8BAUfNFMGNa66ej7jRlrbbzMY2L9hdHMEA+p3VLEx8Au9b3I19PjOUzPa1FEeFY7b3tp4 wgDW8yOEqcLW1nmz/8mDKQUtm9MM9fAVi5DsVNfKoRhf6uL+5qK+u0/2mHJu6HMSoSBzfpWpZVNB i+otpbVNBOrkX3nKfwMPhmFjfkJ0nQ81rcFeO2QUUC8LGKal/1Wsyw9eIVanJt8d4u3rweSnd8/b eB4KYEaa6pIruitbg7RmnZOS8CSb79Ut8NMGoiOl7LT3kQnO7/4fgg5VNeVCHobiXVCEiXEQWrSb XfImRKyx8+zu5otLSggxzNiym9h2v8E9ivBQsbWTooJjX7+2poHqVzyVTn4HwbKcAksTBwWPcpJz GYEH1RIvBJZ+iqX4Z+9GsxKOs/J/FZMwFcaNZM/BvHGNfgQzN8grdFihcBaiiTZFf3CvN935mvSd wwOsoLgCFZsL75LDt1vmXHytDMPpPTQ0cDv2U6baB74MBU1aFp4auUJ1gg9INJZswLRqEPxjhxT7 pvqyXzxEugYYb08I9PIKRTa9WsC1ZU50HEcNzYH7YB5dMbYTVVlQlIi9R9AnN697NzQLc4nOImjK mUezr2B3YOd3qvT8SpVISiZb5PTFIrqUi/SCsQNuQwWZZa/TD8BjsLRxARC4twUHG1XrBIVR2gpW 8pFuVJZ4+5XJZcZqu7np+fxFzGx279Re+CRJ6OzDed6LvKJoz3QHpJsarYpUJN/ZREIuyLDpPsDO ju/nMmkkhGuBK2E/pLNJTnSrNIirAlWWU3pEyOTM+kv/3uR3mqrAPPXMkHHaWe33GKulRioUI+jW syslOFL77lyYEc8gULqjJkGD1kdEs+aXCjG/1D5RrxMQ+sRWLnyxWYKuCQdk/3emZ19XI0KDph/7 p23cMw1QHvd7vJYhcF041ZaoDhoeEaIJ8XmYgmNI9PUc2U3EiwV31U/uBwDCpoYGXGyojA19pwt8 ZNHUMPmI9pSVYYY2NvpsBuX6+koHR4SYS1YiXSGo/CLHKYWoKE/swVSeR9R2J3X5tDHa9e464wgT aUd8ArB5HWs6Mxgmi+eglAVeIwYmMODHD/0ERj9LHA5AOBeeenieACCywwu3YaHgqUVLirc0b3od QbpSiZdV72iCzUxKiJF/nnCPPeL4WmZ9dggPJuWSa4UiiRAkc22NHu9ZbuATZDJJK1xY/KLM44c0 19d8aqVLkyYr8XJ0VxCpfQtoEgyGL9BNW+E7Y6rJbzOSC2RPNW80IrIfSQ1Jxahd8mQDBGIjgz2B LSa/iitquayrmOMwY1NnmVve3zzW1f3WtuIWJFYIhGGnx345jyarn1vOS3Xj9p674sTITMaZiVpR 7pI3JJ9U/MWkbAjTv455xlDdsFMXDfNVs9VkRAwqaNx6KtT/VNytZqyUCaFRSDWsitwmQdr0kSif IbwcRmuAxF1cLZgKgAg7qBKCva29KuARigz5TcIv9TDuwnFZxgC9u65AxFtNVH3RkBvD0rPD77pf maxYisgU3WJOvCoYRg3xJ0BZ4nTGlrAS2gqqMLqWEKTNpaF3EHZHGOkADS0DXhXHqOOjz3S98dAo 6Dm9WcOvhv7d6l7JsqujYrVevdWtzFbSuJAYSaQIla/pOWRqAsr5Z+CutTwQX88MWNgT11jrOMkM sI1ZpRGpTtisritvFIxnR/2l+sZwlW94qoj4pgIfvW6DLQ4xMKU3TSvp9OWCrYu+YLULCZbDIwVE xIaI5OEcOAJG7r0SZtE6X12Yt74R+4hQcE1VJjRbrcQrs3v5gJ63KrDQnXGr0U/9fpm9mwxBzn9y 4U6iGmw68kCfqv94cG110M7TYvBVexdMiRYH3gE12bLE6aS6BWXq0uS/ThsucyScEGTXRQQicIAK 7IDvIbuQ69ErdJ8+JTZe8hKbfGACRHuuogoL8yxY8Qmmn3p8zSs/QxPfARNH6NRwP6xd5QTWRSU1 /6F2t+CPp6Jdge12ieWnJrYdQRPsieOL5QtMOsLTltHt/AUwRxdsG0NTvdY6sH4daZ1JrbPWQZ1e ba8fjhsgT2uMXjiai6sM9zvbXhYvc+ekq/6EnzOJ4SYZj139ygCvK+FsLxvihrWe9wp+rhUlNkai ZhAQ7AhJ0He2berfZrFTPCBWNpH6ey30tkTo6FzsvvCdXnqiBcUTaPc4dKyVr+WJ7S1ApSz6GKH9 MCgyAnSGAXw/J7dbl769zy+AUeTk5bjK54sD46dXM/2tRMT2UtLdA2KPHrkjq9lBh+39412Q+pyQ mOZrpp161lq7/lVVz0nsyAl48sif1RhhAV26x9/I5vIfQ2oF+WDuBIZoggVUF2cQ5NrdW47tTzD2 0cncagjmIgdzMTSGXsgnZRW8+NV0dN4wC7PWxgySUYaIEwmWJXDa+cbnfe1vUN4XMrDHvPY2Q94g ymEPVfCj1DPMhxsdKJteB4IvgCisPRUBAlOG5rZvhN9sV8AkokorL+2bsyq1RvyDMVAG52zGuYgs Yk0LeDPZt26Qp/lKQlwyd7S6k/Z6l2kGfkqBAyPUSNaDdyVUUJZuRk1B0XW4FsxAMfB9SJThPrq5 bguvqBKfceLelr+Dz/qlXIam1Z0ZeGXoh/grHfJy8Z3Grh46CXKlYFAECzSn3qBmFfgNDP7IHx+X DlAj29MklmzDJt49muk8qRTiRDBsQ6Ncre/EpqW+mgLvGWwyQS9uvaAkOSHewnijoVwQPhJUzG8g lrryRx8V+m6sBE0N7OEiUT2FJofYL62FpV5M8RAAUzbQ1Axnz+qoy9sKUQly2sbPrdb9Cdn7KAek p4De0gHdIeI1gfOcYC9m3IrJ+zOaarxywNN9nMptAgCmzM2MwVO+Jw+Tdd1OR/vbcIICIhIo2doV vwN4s+HbR7n68+v/jkG+JEBoxvpPiW6uDtd2pDR5tsJqwHrQWsZ6pvJZDSUwkj4XSrCZBhhwwurz O9A2K0VNCFfR/2YAP0GcnqKD7G0zqqfeexODeCifmWoKvryXu+BcBGnuRIpefnlhT+in8FVF1YN9 ZOYJY89AuhdE8DW3mtEFyPpyEdghzBmt0LhR5lUHj9JrY05fyD8TCV70Wg+u7W2Fe0dKLUV7Ki/+ kvPPb7V6EjWAFIk+MGOAv4o9A7SzzhWs8beqhYfAObTEmDEZqa1gKUGcPnJJo+y4qPYJplmqAbLQ 7+uxBNRjqoYYCYPhq6bdiKY+lqMWnOr8cCgdplkYZKxrbIyCFO3/8X0b4CzoumCs2fO5EsIceGQE ImryN3EjWshlFGDnocxKObgxpsKRPoGDPVJoIhfS+8u0bA3AC4TauUsKJypkyohhsEEU+Fcir/yM uamx3cY/LwNyOE1JqZg0fz5ZeyAxLADrLGeUtKS1IjzWTiNBXWeNeOx48kk2L8jThLBNqP+UlZYk J6MoCz3puRlkf6pC/v1dnvJvcLK0jeR2dt9EHdz+joD7/VoGXA8CW0WjRuE9JypFb97D17ZZi9iI 4z12ubW2sLjwei6XIetG/cGRoRCmGjp0KA16L8XrrlZclGYtIE65YHw15YVdwFZWLbMTKErOXkQa MyQbduPRSja1RMfVtN9tIg4HMXMcUZTC6+z7lKRjx922S7B0fHkAszrLZdVmhCKO8WzvTOXRG7an QbWoRzU0hVZqj3xVe2VPBePUFEfD2nHTBNUHjl68osL5YlQpgShYk/1eojJkxtYZuOMVAiDgYfdM l+LAphuHNK1EQjchqQRaZdV4m4M/DVakoH8f3JOi8lY6HQDeB3VPC6OMeGYTyNx/9JpvxNiY6Gd2 ck9XazVm5BRSauFViMRvGT2uy627TiKMM/JMtTKCPUkraQM9ZoNNePAVW41eze52GvjONGrXFkrk akjotj7v3x7qG3kUQc9Rd1S8qdq1T3Pbz4V9X/lEm6i1el/NrTcVrVQWr3RCxXIGzG1brM7BH8qp tpO4C7xfstbzSvgxVWtxSLFp9iP1QV1BP9uJ5KZ4yxtH/F8J28r5kDGgxwszNvtH4+FfS13SBKuA Uv64P3f10hddaZJIMf33Og2tBH8QE06xOhFKOZEaig0wnI8f4UieZKZRUqmQtNEuAiGo5kVQKBSB awFbyHqyje58KFujQxFYYOmv+5y/RcifbaDMo0rbI4cl5WYg8QQ6+mbSFfJRU/yVBjEgy4FZlRm4 0hLIJvDwRn76XySt6LRXBeDb0tCmPPZEkCSe7AnVsbG4R/UbFt2DKjKbl4URmSvqzQYeI1/fw9Yr xRpSdi8P8CQWgbKCt45eINwGzab4sr7cSOnhHVHwMdGARVF+FSmX089gP+U+cmQK+8bWgjeucltf 89ZwZNXNSru6dM1S/KwBkBh+04Vmyln5SF/DDM3PuSXhYBl5FPRv+BxEs0AnP2+dC3Z60ytddep1 iJFCERgqzsTG/73OBNeGZi2D+hJ+Hn70qKtnJy3jtNuq7jPGgWM0ifgj4DVL78hzOb3eUPQy1M1W vRUQruEyOmZf3FAwNpQJnKEm2Xf3BeW6ajE5VkIq0M9VDFEgtjC2wuRg7v9vc81EIIuIhQYtktCY 19Cn6E52ToW/pmHsGujHwgzVpaQsTvWiQlo9xdW/IBdKW5LlJE7KdxsCxZV46+TGokXVVuByXnab ky7XEeBEkFwtLPxHkEcVoE0u5oAbH7StocuhSuj/45c8+lppu2csOBRjeRhNU+WP4Ca4nmWPUCTj qQZYcYC+sXEsy5E7qFy9GvPqGtXAUx8fVsG0OCWEj+qERsXfS5gMM3HK16R6eQtKuOCeV09A3EkW +vM9y+eNQL8dG3Fi4SuKjdD5ZyiaZT7yRw75YSy7euLpbBu9JuVj53tl/wXNVLs3r7B5w2+8KPSy mWyVOI4FLGN9wWyy7E9bwaBw1VRmXECID8mllSc+e1W9DT4OYJE3gkfjPHeAe/eh3kb/tvb8m6zQ QDQPrN1yHJP4CoPX+dwr7Ott2AerFjgPgMCmPgXeXe4B3d3VNctfvYVPcChKZi3OgkIWJdLjiNNm h3TzngBkmOGbPwv100TVzJcl7gzVHi1B6DbV43IwICvL4Bv5ljKfTHch+57iXykuz9HNTUcpJEg9 l1gajgzcSNwU3jnROTUuD8KSfwUHMwQoglnunc9GQIDqQtxCqzLvGPuQf/WeHxgUHFY0OGw+/SYo FaFBA6vX3d0T/T0GvV3GCNWQQ0/1IZ62AWedi/l8CR/IG4ymQ4q9iMQ1kWh46NY8ujo+4c3vGG9Y rWj17IrnVuEdMvpfKBpvifAYOxTk4f90xGVgl0srnhWjFhWJCKODlxaFdvm+gSnpJAoecINNyM6X h4xtsNbzGa77eDLiWc+r2GcafI/l+F9aTTn40OdNJl8u7lz7MG6Hj4TBgAWGXyrboeMP+Hmonwyb wWMVRuqC2Fj/X95901o7T73hJJAOlUSWuor9ilpcIpy/bzR7Tf2KCnm/JS5X3Thd5m/KgcIzzxiP 3/gb9OHU2y0SlrGcqSDBkGTQvqVjEtav7WL0noGT3C54XiKGlIbbytZoKNLe5fbJY260WBI9EjJ+ AEkGnSzYXcsjjRv0TdedQUOCrhqFMtS4wXPQFx6M/VmBiMrsF2Uaa7nqfxaRRsyVj5ih7zAutcYc ehrvYTJous7+AxAotI97YRYRcoweGIwywE3seKuOia1iroengMLFyb9kYZOQkMQG3/QPL+qijt7b ipOPv2KK+aIn6XRCdgHmXOXTuP9uhPiAmYpLSyqsQsmnl5+kWGPgsig/lWB46DiJHyGlJ0/BdCwy +Pm6mwINdDIPWqAu763b2qhTbnYdu8UYW+5m4lSWf8l+iZbZidb5XeSPg3k7IqNDKJpH8/XacAgw G0yC6xiJe7IaoqahzZzsWswmrjLoTIhM9LbKFtQaza1Ntd8+BiAVuoYAbWbM/AnWLUXz6rqudqzq 03pICqagICTZS/0R1Z35Qpyl45SJUOh1SS6WizvdBWnTpvNUzeJt5vtCgiPxuevJNkcS3f1//UOU PKpOowqBZH6c/vjg9u2G+0lVQc6wwDGlI62yBdejy0uIDOr72Y7e56xe+IloQAMckshvrrtEOmA6 0mKiCNdRVsoOMKH4VB8iO/0ZRtU4x/cvp5r3FYviaG5/t76Silqzz17b8u3HHVXXrTQnnaCXmQGc qydebcQ2IcCuFInPWJmDKCVHYY2hpXgYohE6x6uN30Aoz4j+3sEpOlxq3T7OitRYUHi/KOXQQ+NN t6Nl3/E8t+YhU921JnOWSvOFPd+LfwOBXFcqQSTfEe2rO554H9m19jMUpBGrVuXH7vePL9ibIYQy Gy39BB05M9RCvhM1L37KTtkRfZv/M3DJ7VgyHAYW6TEFjtYA4Feut0m9fJgbyf2BhFhB/7Rs8cxB TgjXxacFR2xRLP1T6uFkGbvCZDfllnhqqIhy9dp1gNz0XKOBwv/rQhrSfP4p1wfvapouBg01O71h W/oCXDGmVKVFcnCxlWOdT4z03K8L8TKqnGZ2gDc2UDxfXbIFhNLM1+EUjedcf/wfyg+Iaoup9iUV Pb8f1C31P2+d8IOmtDFW/aKLcT63oF8xgMIQ5kDNDf1cXhOAsKqahR0JGmmjinJDgQZUh/8xJSMz 8ncCzHJmJAvJR2SQc5Smowi1caGTYSrDqIPmMHWMCUSSOkhDKFhMdxz0YEsC0qleBQtyICVWm2IM xDa6DZvDZQ4GBGuPNtBFXdTiFVKJrhpnf0heLBsAxkBuUbF0BhZLm/asrAX/emp9eFl5U/pliQQ/ be748yAL7TtinA5NoEY2gCsCPw/vpr6D1Tl8BTnUktJQfsJSseuH2gcvM+6d78Cfji/+meOLHL7m NQO+fBrdlvmZi/Jzt+whMwM5ZhxDGgPbllaNrEg9siYK3NZCZ9IeadHUg6USFU9oyWwHrLxrDpvO ufoh9QA94CDxoDpN9AOCBCRdbxHYvOkwIACNupqKuE7IPIM5hP1WLT2hUQIigveMYruSXIbz5cc2 lwbv5pguB9eznThFkBfoYWfpWHS6PDtf/yRqD/YsSikxSvm48M/IH1t36foasHtH8Av5maQeAWdv WUPt8J5EpE1vq7b9/mfXiX3kFPrse31lSKOQwkxg6YdajXLYjbxokNf/JBgUfbwoS4E4oDhrocTV SZ2BSCiYqtq9sr0eEQs4zvY5w1UR0zCp0fw6EMA/Gi+GkXyR72BjD/h9pcvElZg4VpebVZSDeDLF 0/sEiYko/lLI2J+82jyIwfdIy0wkwHUe0gsdrzlKf0Yz2NrtCMZkjjv5llJFgagcfSS5lD1mNxtS W4KY1qkjf8BdFe4q98WFg7sbnpybNL7bTeUlFgGRZFfFKRFYOfAKqFXvv51laNJlqC1hzuLDKVl6 ZPj9EuTAvaMmRNryR6bKHC4A6GtztdvgCvK88XEiI6irfRhG07wqakIehn5Nk92iRR0e0UdMYPWR qae9UPpViTtCyo6GYP902hPo7yvozwxtoKZvvRwNYP6fviOWHfyFvu61GJ1prsU/rmo2RAbNVWhi yrJxtbJZuHcRV3Z7Roj9AjFWPD/CcDIo7nKmxOEJStSBXtEvAJEgGnCVzEYFNX/+PkAHxON9hdxr smrCMa5VP+Kp7IraLz15Bl2lb29wYUo/9loS++BWMm5Z0d5kdzv4r3AOrhy7LZ26QhncntOL5kd1 CiwdMbsNkfnrwscqHi8g5s4ojWWTpskA/T4ekWj5TthdnbWy0t8KbaoWvgWBwqZr5o6v4HnPrW/J uoXEvNZ473ASwOPEqRNqQ+SlLeVEm/aSiyi4z4xhn1CNhCik9zc/XzJfs2pb53SkondFMWGpsR4m 84GgGc5wIFoVUjcwUDclfL2xByM6MXMwKR4z1sG+dnlMZYUGB+lkwupDW5xNqdlUEoxVcajmYlDv mrVtaeXhNAin0u6pOCPT5ofhFbyQVB9mAaAR7f/ZGIdWt43x7Pc27aX6Aa6P8c8V6lb3QJ396VNN 1u9HiN/ywU2SU2yV+7J19l2M3FW9B48g1bJgGLI6EsNXf6sLQWs94L+nZZ2yAu9f4M6MzPEF6+E+ DI9skMZfnbgz+1f0//1Bji4bVZtJWRX6Tpo7h9qFiYi3h1VMyNk3uKqGvyMvjzeW/vhVbre72xv/ umJrFxV5pAeQ5IXoLdWPl1MpvbO6+7B0aPFD3Yi8KlS+nWW/PW6RMY1IaMdhBU0g6FcpHiTEqwQH icS3CuqvOerSkdniXboBC8llqmQlpgymLB99445lQ7LXy+6T+rxqzGG76DjV8j72+Fv+lRReSUwy n9TX9mxrXyv0+T6eH4D3JIfKD83g2By1qAJIGo2+Z2ZlRVGBJic3HVwMbGq52wFIMM5i2UIzHgoN Ei/VHQFLKiTGBBhEyayJwDFeu9WezVibxW0gNZXOAYVbDgltbKjwbYmclogxPm6yJAk3wj4vjwfY aUwEx3S8sP0yySxtLwVrawhVkDi3nEB8gy8h6hRwts2W9+X9jImXQcp1kkcouPf4J2S8M8oJ31sg Ob+he6XOCj8bQYsvR9FLmhgLQGyIOFZdsyru1T6wMqF+Y0G0JfSzpFuipfRwBP8/oAbCiq8sC6T7 U9VsHFxHXh4c8+Ozd65JWq2h6IdMizWSc3S4Zh8tyqiDgoRq1y9feRb0Im15shQs8WhGdmHwWx6U UngO4UBkHYB6mYV/RAd7uI3/Ia78hxj5wqXMNW9rsOBisp19fk1YGuxLl9WRidJp5xs1bqv2+5ME COvyBScinwQ5sYOG3HsUCp8xvI7IxO7YoUYnn4xNng47eL5x07DfCvN8RgiXwede068/tBXvAMbu S+gTG5EJJnQ3/hu5NIokqwKcd41Nq+U+uEglWS/AJQ+S0TYofj9tDxZAcK/r2WZNAUVr5+6aXFz2 J/E221v964+iz1qcx/t57YTdYnxWLJeekToI/IZ7jinteFjAxadwilw2RZF/y6ZrzI9ujuOU3waA 5/ix7IfcC9rn+jtpfEw71qXrjzJvHsuAtQTAxMoAUQty5e5shU0hmRoOEYdLN9OWZmlAbh7wO3k4 FhBc6ZJiYiWjq0f1orgWRt+ilNyb/Fy4+uXe6XrvySx3mJJ5Wy8NJxgmKP/XWXAgsJfJUVYch6rD zBrxtANsDssp2lA8IrvzCvmty3iQz3Hv3xClBdW5hJHj2hWY50gaCzIgspntTRVRO3NEtA7+7nHN bJepMGUoRXoFq0/Cx/csKzXgIf/hddibsT3c9p3j8txs5i2y7PI9xllpXocnmVHYaSqeHJimEmeh U+vYrW3UYGuEXYkhU3AhJ/vE/ouboLHOhPWW0pI3x47r+kqMbg99VEDpUg9+jk9La4Pwa8wtDH9d Bt76gHiOxJgqHINu+91wqcahDkCALo4u89VudqE+8ddPLCUK8j+pqFlpHWskAiLY0vVPaJfaXWsh JPysgyqXWcnCNA5dosPnZWKvAeUPuFxehPN9oZZGAlLVJHuAk/Y53n3OC5451k+zsqUjN6Izn11a RRNDq17VRuWMDul8yh8ysoXtJGcNwStKmKnxki/dB+dsroBnIW1pST9UpqR97RKhbQi9EAcC7J+v hKS1+GPPVpYP21G0BWEPLSgFNNcDOPw0t6fvu6/2hwuVe3RVWFYARNR5p0voiVXFGs2HBrm0Pu4d ZSAu8wORtialobZun3MY9oWE94t2yCPRLCBQnjlDdms60alo1JYYB8RH4Aqleb/hl2B9mHf89mUC ovHA0m4SgMgLBTtQfpUun/Wg1pk19oL3wBptABgQTXJXkhxNS54RLxb78KleuLZzJhqWfPt0liDk nkwYzY61VXCWUtVTxmJT8Kyp6IANR5eOC3m6NKL6bioU+kFK/wss/jV42kdthYzrPUGnoSPhR64+ 1aldq+HCfJReK0kqHDqodXrdEFPnRuwUsIRcWOP9dhnitn/gYbZedWoU/1Vv6sp9/DiABPaZWs4R i7AmD9XTedIUW0y5Dqtwe4HQ2eoqtiD5uOiSd6iuJtMtBHE1JRY8RhkHiCj++zPGpKPh2Ftb6dKS 1PSvqnMLq04cqsTTdd7ABbhYbQOi72uwaIUtXinVfCdDnD5HBvK4FMiczAoYM8KZYTk4uk4EnFC6 4b0fG2n35x+9Gz+vWKXSvmVNaPpsJA3AlK39bDUxItaRNuHvKnUv9GjjHJyO09N+wcgK7dTDEjur rE1+Prw+oUaJUgYsKnOCdIVrm9WEZiIy+oQzj33r7FUb5yFpedWvFD/iWiQ6fMouJMa43JqR+8zd /7i/q8wR4rsi4qjQvkYOMX/o0HAx4VNboooRxzf9ACcjbgtOFzd7Fl/kMhprIS91hAAm0QakOo+k jBLNVN4NZeOw0iOVUl4iOj7422aigqUk0UeK03BwrV9+9Jg5twRVJW3zj6XaVX0TA2ZtvE7FRKI7 hLzBohap7EbqZCFcJa3HrMynH16mj/E7nsbwyLlapwM85rq84bjHkKOKaEL1b7j/s6jUEiduZgEU kLUwjrc+NcqETsCAk86V2QlJzO3b1OJK3XvVeonOiiAGKnCKFmOzuwLJxsAoqAQIGuodd9vtppdn NS/BsZCuPrqAchkCRGQ8wHDvYqBrT66TSAEktDN47QaH+WC3gCK4hlnC7uRZP0SgweiXhjkhbk4s J+cYRr4ChIWpc9iofjskI+y+dTmjKnKp4Ttdcdk/vgwafgBqWXjOb0TuU77P5kOAjs4kAJJqeRjw MsSHX8n3B03k/i3vI7oZZAg54dHJZNr5ObZswhL66ATMJSTod3l6dULK9rGp+PDRDXjrxzVqQutP +aCalU9rG9/fwtV+jqK/eaRQtzWTCZtW8zxbhjzC6xwyaoXz9T41gf+iG/Z49yRm/ZxrhyIC/pK5 HtFmYzX4KsPKhQs/1LKJQp7TJf2GXzJxbtKknSEe4clk+M33q2zSRVT8vN5qHMcVENgQenKW9hHK dba7l+SrAbIL3r2i/OPRZCCYe9M+kTZvHu2CTGNymu/Mm0ocwbE0kFt8Gr5ZZnPgjur3iLxe/rpx SZaolNHKGDo09pFuxER0a9s0Ey/dqzV9ShJuDKzxtT38q0Um+KwK2zqEidJSGu3FiIoYD8uh11Xp vn7/MwrGepHge9vM2fwIxke00DL1sZuHWJ9L93z/sSuDbotkRHL13ep7D6qGbxdCMYOrB0vXh5YI 2KGzRzIPVJErb2gF7jmO42Y8AtsNiB86lUmTEH6uBMrCQlKRrUeBkgJMc70qWmZFUus6bXJYuO2V M90Li8UCkinY6O9O9hrSGPziTPy6hksfNIp+L70MwaWiQxZql0uKjEW/bkeCpsoZFCa0efuOZO1/ Tf5+ykHiKHxyuvM0z2A0+sJpzdiUk92VEmo+0V/QL6XfPcNUxJItK5iooHx0WsSwRyjCYqccjhWo 7FWmQ2+UBQG++x8Sz9yrNOHZLWfAX09pVwfyhnF/OEgvUUe7wASxJI0DjYTbtMgixglat49aiCxp 5WiF4J2plpe96n8id01/o4+o3MweVdgzSbKnqt1aWO7yD0ZHfSmsEtiQoBoPnFNL/pOJ4oAYCObf u63eMZ8zkoikYbSI7R/5iy/Y38uHSYvjHUwCDeZh6Thq3HCafz6fOxF9HXYg/9MBTbp90JAviNIy QLnnPOgi5aCaMUbwDWjXMhkiN0FTklVjvT/2ILkavaR7nmeEyR5gbuxsk0MF0BPfessdk6WiExHY SZNR4nQWFNxvXuHWFmKuP0HYVm87WoAcnyURd00oSrJH550NZnv6be6Z/8ZzkI2fJoym9XKNcl8w JTN0Tf4m1+afImS/biLsqn6ZGlSGdcU1acQ6A6h36jmesM8Z8HFDJ1V3Pge8hz/+WKkLaW+2UEhM kNjGblptVGd/Qr8FU2EuHTqV5rm3GakYe3iZSbZRp2Ukc2hmsVOoB7yW64dT34KtR1NyxcAm88cx 54hnZ4BP9jTo5zrrLXsWKeEIA3YGFp2d4dy/PGX3G/IMJgNypWL/1qDFoCk1Gno0nhFFlVISn7pc OhkCWlBxOFyj7l/crIfJBmr0UnxP1HsXbfmk8WPbYvgiHNOTjvS1Sydkdt2oaqWwr943rkopufn5 5LR/bn9noscx5eDXLkPalAjEY1a3Rgxh/oG8aONhi4ILldP4SC/trUDNh+BrFpBOpAc9F8knNZ15 pE9+vsauP801fz9anjnnMy/ailfhtSO8dwUA22dbULLga20HIBY66l9Q4+LhZK0BSwyXCeCH1QM0 WD8Xv3SHvSW9PZuHvVFMxvtW1sqR208UcGbJ+EBtPP+sljvAEAlj9PxciO+a1hTTQbczyZFQePRL AlT+y5Iic5FZ25dvi/T7iwYTSoDXQP8LZzxquum7yzE/XxeyHXzzrqNlvC8aSqC4V9wki94+3dyp SNv8HdNiIsNtaKRzVVZvMgeuLNkj2IDuTMxZ1ndpit2SANlNRRvuEzRVLWdcpbYXEVKl8LlANMkv KUB13U+mUEPciyFG72DMDEVNpXwLY+AZNmmmKS0hCujH0lb8SjYNy6b79aVmXTY1D7YS48QJiz0B FOr5XjzWUQT4ADBLeM6KvW3VKPDynh+V5xyPbQ7bGSpPndkj0801bfTb7zTd2XZsmq63jTZhr3zV aSPYsnHE0KVofOX4haAaAyA3gSdaYk0kjO7zZc3E9PyHzfGS+ewhRrUh7+sentiuDB9h0gP2dCMr gsTfpK9rVGMIsTsVlAiS/8OK77JfINdt7/l19yinmEVxONDpOVfHi0zBjaf6VbiS/tDh0F2EizNc TryoJpofOOQIBhndUchFK4YRp1W9jU7ux3UlUnMBGaYhEOwOvzLXS4/o2QP/nNUuBwntYLYrY8sg 0fqMlbaivsPLkskyGQab0xsVMVtayALuTrCOO06CpKzioAUPc/UsFHcRzDN17HQ3j6Pb6k1tEIuv jhA5ExHgz0jk1tE58qzhn2WwUUzcmxLL/j61nKdXTt5keTfcps+Nfg5XkVyu0h7uQ8TE5aOMMQVi ZREwi+S1/b9K3vBqk7iMaSVBdYwzo1FgpRXpqxgywq1XDhbpzHl3FcxIahnZPcue9uTYssm/Y8W2 6yMPnrOSdA2AiVkfnGTivAsPbd6PbnCAll/lNP7vpZiMsEfTFR0ee+GppwhmtAVSjOY8oS9aO2xP 8IeubCAsMOtzgn5HeMoUi2jjY7211I+ocZxFQET0YLGtuqFPOtNJr7kZdlPGxL8CwzK8N87gf54C 11wra4TUqGJyg0Y+V7ju8t4Z0gaKkopOncDZgBrUasti1q/xGxoIRwpEdbwyAYv1FfSvjokT+kQf ToA+XU4I5Rlpz79RVX8iv3OkDfAcwBnxB8e1v228VT4AmuK9oqomllObsNzPJVGOexEFKMAjowk4 ITGY/PyzrVEtkKmyppLmdYzs0ITjbKhRgV7U66eOL/4AdwkqHrxQzZaia04Zy7EAojs9jfLmUbtE 5gIdSDXUon5idj0jtw6NFs2uiBV2+VXVgWp5vB9qYngt4/uv4nI8zSXPb3LKSEplQ2d7vEj8PZO9 JAY2/G66HByS8FwPVujFpYFqGNS5dEB8uOP7ms3CfcHKnJR3/2oKujsiPV4+XIed9XZN28aASgE6 7fyisT/3GDtXdJKnWnlLJEawUeoEoukwjPh/DQbUl+Z0M1chMw24wTZq5lz2tPZDRWlM8xHL6raQ TtsT/uVlXrqPbsfloPiuqvp3e40YL55A5UB5XE2mGf/SBFk4uqWsqq46BFo2P3WC7U112cSyUrFR TZuV67kuH8dL/0dTBQjnOHmX7yC2ty5nnjs1xcZ92u60UHn6I3HDNY6sgQxQpTrR+ISJONcuxsMu 6/xQqroaaOc0ZOx+55iJPUfw18QgdU25ay/vdSuH90hFgjqEQyuUsBTFkJImAb+MUZ8oxNnWGp8O 1ViKxkHag1FJgKUwfKJEyduSwyYez/aWQ36NVYywkQHTXTRDR0L7N3rn57nzaeqmsst/Noev/se7 2TTVQ4MJV3cAgAWT5Dq7Zumnf0m9k3Jk8MW0w/o+s3mbKlYLhrEbOHBxH2ozh54JHuEEFwHo0HEg Tycr+G1RlUlzFvNfLVs2pUe7NMKQQkKnCevDjdIAsi0ffRtWR0jYIZW9H+wAO1XRl+P90NGChKdH Bl3b9+gmvgREe+pqyakstahfkONGxGxNRIxOV0BXyRt3Izmw+zup5Lu0+hc3YwjQQKg1wykjqiLu 4pNcO7rs52jmQleIA7G//vFTKYxpVk/bJMWixmsnDGuRYDCVgfJFanvLAgHTNUSe1fuuIsot+3Lg V+qALuYrh5Jgz/8C1RCjbKSR2FZWB9S18syGFareYAL6dDOM+fr08lWsi00xxg9r522/EBpY3Yue vU/52s6GHe4vbbpmSh32FNZL5G8MlOWt61VWdcG0vjAplbsh6HvnFeEF45nwgnzHQUkXOxO74jbb mYkX4EI71u0/1UF+5UTwCCmvhdSO63dFPW5YtU2WvxY5cmBFsyoJ6mZ/iqaObMJvyuixnaIx6gFf aeSkD1cNImwVEVfWWi+ubzNscfLjo2/99x5IrRLCwXNP/ExoS9qWEZrJkExq4qJPMGoJVtPXFj7V Bqq7bufAWu98R2TOGw9vDu6NqKultKWjKY27t+gZ3tijKgwLsJzYhJrItBG1qrQ4TSzzHMXZKIlr 0NVKSD1WDGWgMt2kFmDmRT72j1GAdZ1frH9s+4dfNV4Kf3IoCFyrRJnE0GEzw/ykmEFu7/o/7KYS uWaSmb/qQ0zvOdV8b9+I0MiYXkOkrm2ZxieF3PTvo0GmjRYVUV847NSX2sC1LSjRDlH8nhf+kIWH RWKY4oxb6KXmNJpQNRaPdYbvUDuTy9JchpBseSkvPnrh+IOwFT/Zc9MO3WYytpRtc6szXYWkSKiW W9/Kqt6NI6qlVWSyvPQ0AcEGT59azpkixzpk5suHLIxcomxnVpUON3IXSg2diaNh93BJSv+ub8qc RpypAWa1kKqvWLXOt2FnT8gpTMSqxBB4qPF7+QG27Cpb9zM5wrLaBBImdUQ5MuibloXTA/hoLZSN Vp5LeRJSpYUTv9qxjQqcnwVt3PEXyUlAXCgLb+Ti/82GVqFbkVQA+d8KUtLcD7mNQC5+Z8VbgnI1 OQsIiUDDe/DMJ7JJ8NnRT964TLnteBQyiYwU0phA5fZNDfKJsEYQN7ZkmEcZOr9BE6SpJwVXqoZS PMXFUn6lMFQYRUwA5vXTrRZBPjIebW0vxA+orK3q/yFYDvGnYpV0a2edNiV3QLFUc2nTO2/IpZxB rH7FjB+uOTCWmFhCE4rqakY4ZSPIkEIKRMNkY+1DtbrK09vkS/FLUuoEC3IK6OytJVuzvWOqHxeW 8efbN03HEQuuFkh8yZE6Iot53inpEX5ONwi9mL8zd18IDU8Nb2FHJaRgfv6OMoxEP4drU1esT9Xz /+ozcTxEB7W//lx4W5QgxVsNWv0woSZY3mpgvVpDjMUS3tq8yeRDmyG6Gxi3cQwzumGs/p7NeZRb 3RLDw1d0vWawYakltUa3tcQSlk8xs/6zVr9luaLtrBwe6k7gKQLrs5dpPHVZBAL8rtJOw4c5NO4M eM2WSptEp9vaqhQ5w98+j2bFPUxKyQz2dTn1u6XZWe0Ts09nQKyeQW3ymI1mbaEcwDd8HWucirug As7ZMY2BjsnoGcILZquembUEf6I8z60LMExgpRrHTIA+kMdOjI8+lLim/oa+A2FN5r8KldwCAqhz ATsb5jI3k+/E29BeFfAa/lJ0wZcw716JxuZgLqUFy5Xe3vQUSEj/t/vSjV8DhGkcYVEoi/uBfnhQ eyOiil3arT5B1bx9J4xIyjHNBywD6MiDh+/34Op0mr/J78F3SKEcDdJaCM7w9x98TDKSMBTKHxoX BKCz3z9UN8OXYwciOsvmlEaY5Pg/v2UtLHzP8NHhjKFOqSv8NIfbAySBRzMKA3naBJxhUYwR2Nv/ jS7FOajSP1CcmZuaxigETBEOS34AinoJ9EosbtyDTVj+YqZo/w3v9LU7Jtv4RQLC9HaKk7MCUwVC XuDiEjD2WoUfs0hlOtKfOMTtaEnrc1v4QKSwGsDPbeNRXeDGuUbzvEXUor7Zv5ScfPQJTHI6FdbT r2Njr36r/aBPH9m2cj6/pJTEG8X/J+ALiVoXwLu/VFn/NADKhveLKRdY7rziWvdxTaAyWloQ0lsS JGIkqLOuHRKIH88LNlIgmBFtB7hHeU/PlrIghKLsA5/RK7IoGsarmPmQJTNtzaDDpb1dClIUN3Si IHy4fxqS5ayxXkMo9jg5T3aUb6DqozsZX9PA2nMmgBM+OYnLBh6zi1jctWVyon5cEYesqze1a0vT Az9P/yCslfcU7IeY9wKGM7npwmxDN2EjYQlLAZDKxfXg0OQJs58cpwoMDcDIJwicxtViL0NOFdYU zacnZMtFF6oCFUMNkmYnBjFAe5zoEUKbNBHFqeQmMiF3ySg44YzCY6PdGzBOcfpU7TbXHKIAjjfx 4iGSLtyrK0qsrCeYuiw5qxfzyib0THOpR0JareWvFpNhR02knNi8IxM/M3N9bDsubF4lmnoaz3K7 syNU51C3FB9boPG/S5pvUk9coc18NBQINRDUIhGv66YIy0ADrOChMagkvAwwXGy3ZUbPmIjt6kr2 kD4JBS0cDC3GqoT60emMpdhrFnA4cfjO7zAJtouXKq/fdk6n/b0Snp3n78oyC76p4a6dN7XuaohK otDhcAreQFuGogwzR8MlLaj235eRh1/UxIANiMPk5L5NRV0tZy5i8PYoQnvlDgIh7aOjLj46eGbl 2HDV4c00YfAaxjUHiH43wYlIk2AcD/1Aa1QadopBJu5NEVuzZbTa2wvns9v4afIipf/XCcALOlwz 1p7kvcR/Wj+cgIeZvVHGWo/6bVReYckXotW3WTQd8V8QBMzcn8MtTGIfXIxuSDfaCTLgJ9reoCEV qWNyJwhpptvBTk3pPQewRLsFpzyKsC3Nr4KTXNWqiWiEvHkmALK/Ee62lx9j+rJneTw4kzoF+4+p iBxVNHcs9X/lTL1KC8cNTEJLtoqjSjpvU6HryF1sTYF5O/XR7taqb0x5oPsF/s37hKDhPJsIfPlX Qg1hXpeIQPpOXSTXcZtIJuFlyNt0QXjCOds0SDQeWoJuu/U7zS9iJX+xNz+xhNUF0Y1DgyYejMRN UvNcXSswFEAnYOPP4EVWLT+14hCIm/S+4A1pPCuZAtfLbtyuqNik7ks2Bify49C6dg7ygrF5zbTG LD0lEt6hDiXGVSatg+ZtV516iAFPsMucPtA2c/P69vn00GluiH+WvKD+Lh87ebzLI7E5TFSDDGBx 37nHnJCvOj6zu0og/t+wlAcp4t9udZnXnriEzXWcvAM6av5TKKdZhvmYdDmQYmp1Z8erxd7L8STb R55qmdkqR99WC4a1J7h5ib6V2o1aGpPa9wXIBpJNtkIRRBkzNvr5oOBP5pjQNrclnSfRWggHIWV5 uTlT04rQEFX/QYDJzRlpnpYOhs6nVasWh/Jjp4OXcP0edFoMZZLjMA9tpotHwDx4N/n5mXEenq1M w9n0uBE8IPjEWmdn71m6s+HaQAk47qY6Pzv/82Wlha9xeFGaFehUqf6W99ejSM27rGW47Wi7xcJV P9BzQi/Q5hVLZogzznHgLWYxihaY4HX1TvhrXZaMV2kRZyivknsbis/Oqn5VKkqqG2+BgsGS/9MD EDFnNcLJ8taEIZG3p6hEnMzfaJLFoX2EVXfmCuCMOsKGj9FM81kDdmaLfLuzZfodJ4t5+NdvC8/W Tgnqbx9MHb/+Gviuj7w7WjyZLGFKBRMtCkTtTxzA/BxM88sC0PhUavwo1L6F48tI8PB96bhFAvUO u5crPyhYpsmAP31pxWM3LmY8mflmuEUl/X2XrOgn5lji3njnYqzQwm8+bH70mKuM5vha5urkTwwQ 6zcQvtQJak8U/QLVuZAkfiZHeLywfbFftr20/r8wfnvzmPeI+RAZ8G5nalKddAN/tlylLPwYEiDK NGBDSVvkBfWPmUJyxlB1NWKDISN8wXKbTRAD4JY5d5g68rLLBVln4Wnu0RZyIrgWfs5n8mlAFOmq e+WClNYeFVt0ZYQQ7PyHt5vyiNYKV6gbglx/tsPxhxF/yYFtGSF4frQPg1wbQulhkFd+pu6TRBku PYhnsWpfiNhKwES86XCAsVPEwZQoBdC7IiRjf111iCQFQvPfjUqBrNZl9MvzcA9cbGoZPH+cHz9D AmWPRxdFKbDCA7K/iBtiP0WYGsUQrLFwVGw9/52NGFOpYde4KUhSDcIZ5yYZPIniOrhvbCIWCxJD ids6ppAiUNd/i8vE4Fqfd6ZrD0f1RErevu4cWsN9rRu1jlGUNBO8BxRRudxgCHh2/qzl89Wg9zP3 E09bWqsjdZ2tHZDf/zLYgOmU29t8ZOVCHx2QHoydzNVvqaf3ZJrVSKJ0cmi73nctfuSp4XEMN2Fr lb6wxlGylV/WUEHoBoq29paVKJcVXCxc/sNq9++vxHF4R8jj4GSBLI2zDnACgCYxgFJaZMb8Ycv7 S742ELy9UpjAE4Y8aS5XTdk+B1ekQPs2GZtGLYJ31j1PIwLr36Kf6trFjBjPxtjuDmXyi4FW6mIK BSQF5j5z5WyTPhexpL2RjKZ/jHbLr30cd7y0JSuNvKTR7Jw9m0+Xkj67yBIISFb0tt2upnVyiIoV LOgqMezaQHte/7Z/6l0wPtAF6plYik0SI4VWRNysDVu/mdnaA18erS0sDUKSEsfzmbapbBJbEk1A ManysZ9hrJgzDTJlJLXTsCMUBTUqIuRTWjsA+M5QCgva8cvxa9rDWijhEfhmhCFsYVxHVv4UJ5G9 J0QmrupeBVV69fyEBRA/HV24qtE0ARMun00mZ1KXWgTCvCXKEpbG8KLqjm3vD1OatqBX5BqQr5Ve 640Gq4pWfYYV+orEikvP4ScBOgklYJxgneTuaLrNmPDeeNPlyNLBxZRMm7lqt/hBYpRiWa+FCTQk uBfLdofT6fPSjlaVEO7Rbaiyb8ymJykwX477xPFQjiwXBD4P5wfM/+beKSaxe2BsK3o8niKJu/I4 8elImV4s1drTGzgv/0dVMFnfb+7kwR2EnhPkTDmHebhoay0gukDuidQs4NsTtLuJJFD2CwFJvA4O 5XL0id4r3hkkNGw9FKiLN+WxYwkNORL0aCTePlOuC9pZ1HKZT8I9ejkBmQ13Q0zaoTdGU3zsnV5s 4tqGIpTAnZcCbF+CIS0VKKTEF7FMplYDblgMUC93H1uFax+cEIb+njDAV276nYuTVLkOwCxtZCyn N12y9fAmeFqamZ2g4t/LplOL2AvqfgONtGH3EqOT8oVbiue7DNAFdtdcwPV9xMFxPIwrUt6bmwvk xMNRMBn4/OrqejycRhEybd3Ywm+B/woBdiLr2Ktw3dOXc2iflDYttFf2ws9DqT3uadZmLmHf/pUo /kXoFtTUPHt6GNUgW8XSloUponHW9obMsYAWpS9qe5+G51DLSQVDlxLpT6jiLACfVnPZrvrS6dm/ MNwyzR5PrIJMrDLdKhBZJqIzEO9AAU8jiXY5m2Ka7UMRT5OD6WeukwdL1okJQt3v1CzVkHc2wT7+ g0TTwgiK0EoNZUSwV2TdttzH7709amBBgIOnu7vzyH/6SBfMykGu7Vl8H6GShvRlw+/xrN7L46Bc abIl6d+pq+exwqdFcvMf0EvswOw+MXWj/bU/7tJsdJor6V4OeyQU2EjGpedbYeiF2r/HpdZV42G0 jxtYYUOwUJAtPJheXTmqRA0AUMWQitVunA3PAedGBNs2KyyJVh+OtmDcixRS1PshFxW/pO1Bbfrf 1UxN4WqfdpwCrO5MVpa6/l6indAxqrzQXqNzPkaY7hQ1J1l9JePTV69r3v3W1zoMP7O9tRn6tEWW EsC6NoWDV/9FrVsBIkYL6ORrCFvU/RJBj455gPpHJ7WOduLhCFxOv2rj7wapzxxnpxLGND0pBW5h duPiaelmmv+x2ImrhbNv/F3uzBGcwGyj0qediEK0614CPOhijYxmvGcrMgjMAT5WQFC5qefe+qAQ Gtlt938yxRyb+21FLS/Q571ySk6BOIW6OL5f7iuK/g1LUhp9Y6rPQaq9mRmEqfwaK1T7+ErzIqEA ZghsUajqkU8SFUd5mZVYBWdCrzj6NCkT2DS+/ilOiqbNPjWOAB8xIKlTI+uTxg4iayhWLqMiHu1I 7QOIcbNf4aO6ey6wXPntUrAwTBQk1LphLtjErVLgLNU8MdSPobT1PUmdGr2MDfuAvc/TMm7KR29j XCDC02LiwmZcISn1Q5qiKK3SyTbEfhWk0w/2JVOwikO06mwFlFDpc/O3ALgOcGThkB+PDjnW8i3W 1UJ9lyrT7JMhmvFhNJFAIDg4WS3VXKv4kNiNDPlJPx15dT3/CgM43S8AW9PqylubaLdb3MJTNbAu PCVBWYTKesrSwOPlZbqVvEixA6ep7lVh8y4/nV5vjR6BELXnC5qaaXH9V21l/4bO/qhHh9Cl/8tV eLYvjhuNlgc/dX6RRAEghKLeT+53soVTPwob2rAiknUpaR2do4faxSQ2HWE9hTyJOjH9yakByfua WYqCY3X5TaQtV+PCEilMBQ8OqSvLWRf5jP2m0yPUy2Kkae+1XOg6D9fPbsziVvjcwyZUuUgeCLEM Xuuve+jyghEdtLECcyJK62CfadbntXuKg54KQ25PYg6f9H1gaouP+HtR17KoKxbgLYqe9eDkbMPy rD2hIcUOZtX3kcnF5IdX0rv0wWhOruHqnqZ9ME+cTI8X1EC1YIunJUN+gFuT00tIKXDNstNKw6su BycG9B/+hB/au795mTAjoCM65dzYMd56dG6cGLiJZFRecpdcGfIF06y0tZa7Oyotv7+fY+xokXWM v7lmxMeG2oOtXER1NzwASIzLTdfxLGr3r/Dy8xYADtN4MfcgOChBLN+ilmPNm4vN84vfbwUiQmNa GwCIIm3Uk0UEsnb/YvNOCX+W9ZTU6V9DDFvDrUS0kpVZA1uRjzg8dGRa08oMeM9Uq/jE3qhB5lE6 4oPKboavpRv+UvPr/+VE8dxM6QjPGPO00UUv1r7OePBP9z2dj+NaQEvhFJ+Yr6eEVdUnQNjtOuwX lutMH7CHBcNBO15ZzYMOIKYR+H82Ik8thKplf4Sj5bj0KPCjKDIbdlbnWbsRs6JQjE1Sxb1ASD1V 55XcTNqVGCtjytL9P2Igs4d/I7o0kHNHYSM3qTSfqT0n/2af44wxMS0tMkTZ/yBXO4phoohkBPgU 2Ry5d+IjKz3b615ovPgLuMxjNkvxNdwzxyGaJ5X34erQbGceijCNoUm3T+kKnv9kAes82GK9j0wD ZyhPQgadKNzyhHqmUkhgxy1s4/dOzuqG+Qo79OPMP2SsS4YN6btVfYltRBCmMwh7PpV/+cO3UA7y /a1NrMCEtnowCKcwTe3AykvN7HCXTy4UnTcZCweezj5obmuu8BMO5+45mtwkx6W5YT7akrFisVNX PXhtoNSIOqxMyxA89ETyVlbI3X/zSgP746i5QJdJvNM23YuWQYqSBnnnABa9m7SVuY0fVXlg4qX/ CcC1sfUxhImH98IwWMm8fMaIllfQKwH241xNMXiRLytWlRUmr5OvHsW0i8j/GPGDHoH232Ra3aND e0hUJoLP9ZXkkS10knD8uDS/aYiYzR7epJmoSTG3s4jcDdfV7Qn8qJ7SnvAopX+8hWRUTUwmZRRr 05pqH/yePxZ+o5zUH7U81pMG+HsUqAIMfmKXrNQ7a9bLIYyE29bnnFhEVV6XLIAO7Lzui14xiYy3 g1/fU4Vkl6qmHchC0IyPZDbCbJOz7fKq8rssv1jMajLElN0EJ6T39wlyw7zesFyEqLctPU1vS1mH 0JFNOxW1EotSwd1Da6OzXB1hUBgZmr+GVgfrJsohmQP2RnPu6mZ1kQYHLpAVRpBgqSL/RZ52c5a5 wp0MFvXYmIpE8PtIefjH0rBtsCL6ErOgXPMcXjDDIKIgFc7DgkEdhIK/mmVfNvAhytA2Ey/KnyR8 AVwpUVyaIvJjVCzCSCRaULbd9zbHNtVes4Lbm0gXvtnN2lr1Sza/Hrlu0M48O32UmBgQ2p+xRqK9 A6aj1kSObrADfUXkGLm7dS6qhgtxzMrLnEi8g2q39TI4gF0KpGBefEydA6JVwoXRa8gAYANL7eBF 2NHy2t4VEbFGZFK/LpLWzuGmQZI5cJo4gTBg8zvomqdk7pD/AK+c+4z6SszxPcy0cR+ACx4hh0xG 8A9tPzscgcGlePtc9b0Fu4O0SLWeQyB2PM65tAZxx7wzyYgui2XV5GAGlCd9g/XWAhfRrJ7eWAO9 i9wUYtEVN4yFjW+scVzob86FPHScMMZmFF+SAU+abK7G/QhrTMgden8RtGS4R02xAQeivML5VI6i RckU49wZGGf5xhz/soopFFLZ7AcBOE3p0P5x34TdXAoAv368r+I079Gi7lKsDPfmBiIi6yHIAFkq cAbZx8jJ8BRiRV5ZeF2nBK3HhN/APY67i43TeN+fKmH3RAx2R4GN/QPn9QNgkjNKMrTvygWOnEnR QcRfrnundGIXj9+v5tEYaMni0MlxQNEQJyWB96qf+aoGVJMpBXGwHKHQy2oyPsaptJ41HfD1XDds wvVIo8rrnkwZ15uKLf42D12MnUpqskHgaHVYrp5GTr9Ws5+fpz6gYocBTWGqc7dp/AARIET358C6 fPkmNPtCyQhSFUEbfuR3iqIV7p6ke/Hgc/SruFGRktq3UVtg4z3DoFsqVWI0qZ5H1Gc1w0728Chy rq+rftj9cUsBv9DcnHc4YgzbprxJKJ48yf8QUL+DeZBxCaQvTVOIQ00CgBXTfGyQX4oBE+inwOuy 6vTiJDuvEDd2MGjEDJyutinU/DrH1GvVcAKAtqTps6FobhCxMXH/gL0vBOjdRPWdouEEpqVl4393 kQ9htDEzO09lyyncAK+ePkUBWKw3l2fIPuT6wx01rjqGE963Irodp9mqUenGr9QHtsJyciinCDqz cFlPVVN90AWRkzn9saGtUuXoRq7+B4WxDmcS/JKvw79At5bULnrK685eU6yTMDt5L2st667zkOZx FJyXU21eJiu913FKK2R0PepblyToKQvUhivCWt3ye3TcotMprOh6xE7WkPes/UA/WFS2Xqtk4064 HvsCAMeH0nVQZmzbueZ5JurbJquQQZriyO/RHRBQWM++62RNGHKMwAD7Axg3kIrG9kqu/SUvPY3e j8BKWQm1uDasV7r426Wdcj5tYRkhgSLPaD+Y2Tp08oN4+FVzeoxHkMOTFG5JvD0Lb1AVBT/UHDSr odIFrf4hOzlMU00EJdXWHRIN8wwCHEAGxgUcjtfew9WEElK6E+EgbTHQCOAiuK3yOcLZmRpXYQ0J tXpvJ4gNxPnU9pX411n8DnHNkwm1sjk37MGi3x4EjGyv4lIewJ3w+Sp5X8wyTesMXSlZzxsD5X19 ntvkpHe+VSeDtHrR/qAnS/Z3y0eYuuFbb3/DzKskRWNaQt0NGvVzgf0zcTTJnSelgyH55lupbXIY oiAIxpKrrYtxwF4z0F+5+nXBcIx+v2KE/z3rlEyWe0uk1cMg05IzNEKgmJvgqIOyCC0E7+u1MB85 bWJmUmNH2vafWtypvdINF4QqqebqmBjUEbPtHCZmVoJhA/rdapoo1EGS4G4+J66qtMNj9uoMnctK wGwijsQNKCPXjJDd/9FViY1/uKC9GlkO4vTGgvSW9DcPMLvGXfqRl4h0h1xAGf3KNmZxkrJC0sAm w/FrHvHG1yZweBpZ4chjsHFgP6kvE54eIlPX0jsln9n5ZnBUXoJT/KruAP1DOv9ba4nuMoZ0HP0z pupqquuKlO/exnFF3tyBczHhSHjg0gIR/vBVeIlOCGYZY5r+GbI0UNTIXNnD3u14fVV163OXHKxM cz/74k2ZCGMPS1SoyDVRfDWr+PFrTxC7761FS1zSyWzG6+rn6FJuCNhicpU2DVcWG9NqdZUKqu4N HgiozMOn6o6KNm17gB6cMuwmYYtEyc59f8IwvBExic/+aKpcNnPr5lYN5Xvc5q7fb7MFuJPMFYI6 9paPOR98ouaUJn2vWfCBoKo/VWJ6d9osaduaaxqoDG2dlAfHVxDO3DjyAcV0V3dJtJygroxaOaH8 CCIoVsj6pQtvIE/sdbzZwt/eiHN+swel0fF5dTDF7vUiN3CjZnOh9HpFTB9rFyKEyjuJH217Xsvr 5xcyl0DWL2mzeqXtIb27ZVP/bulHf/cIbtF33AkidKwXhWFVPkf8EM4YfkyTJuggIYr00n76J9l1 kR7Otss6h428b/iOJ5NHfuRxEYqVvvO9OTn+H2nitqs4Qx+wVnT9r0csYpmbCAc2fTF8WzqjR34q EpQgP6JmDxqAW06SWJJr+2jp1x1YQ5wAzcODROjaHuIFJngkWDYo4reog233QnJjiy0E8t5CPuOJ EtVMwG2P5MW3GhrejUw1WNBRKbrwjV/KuSpjGlzm9Hg2Pdqa/7Nf2WqeuG4c9jO5Tbsc1wdNzmhW jKc3pvU8lSlGZacx6JjcedP2oLIomqb4ZPSkrWkheVjQEs710wbTekvjmcnf9CL8pJMrbknYfkyo DYzTNUG4xRHa3CWcqmMKTA6EqFr13Qx3iACcHmBVYcsr+vx0DTtVRlN03Cl/Iw8CUuTGg1V3dI8h IhrelZOMjdgoWK0Fs9Ltk1hWGTpFYuyY0+nvaWg3XyaWpMtM6xJTPP8W+X8o3q455CcEzaP7PYZl +vCpl6gorY61d/3jRFKw+Kh5PFUIRLIJV+YU0CvD+AU13Ccvzxqff7x9j7+rsVtLpImo35HmWuZH LrOXSJUEcr507N5jgWSiYXPFTIkLjicElSwT9b1MccIDj7lF/gM6bq/z4ROPPuwljwrFh02f2Z7B kLmeCnmhO4dASSl9aLc8MWH7C/0Mnplq5NYKxeZl8kDoavG0spJrELRSN17q4GnUakmUy3vAxuPR cSRZPdRsvIBa1WtZIVMPxUD9LpC1zw6GCpUdJ0DN759Mdqs1lxcHHt8aukPrlODrA+yv43ENtYTf 7QqpLRSuQApl8Q0RJ3BHFYt2xRzLM4HgTNdoIVn4Rj16V+qbfmXxZPCV285MWqwz5+2Ccy4dS5LW KDhgkKriC6kbjCwDpDxhDJj7ADs0AVFHInYM41acNjfE5xc39oeFNpVd3hD9/bFZ7gDPXXK8OWl8 DIh8XfC0vkDfTklL6K6COI+jcZQZJ+TCFrNOSbp1bH1F1hwCV8i0miUeaUNyCLGfC+8sclONgmqR IiyyP6eDJXnOiGXaG2NxSNK1Hp9R04V3iruF9uBTc23Azg3bOmfKMXY6N7byUvdMWkLpPgLW5JF3 ggmE31zEx1YsYbD5dfXTXjQFcRK1IdH7tQZQmOalz/jppKy4NqfMxB2DWh/tayxREXZG4Ehxphjv FL/iIIC40edpLfiYpHKBK120M96DHFXn4g1nYj++hGOY7jvo1OS+TiqJ2XY1w3A3KtaKKCtBRIT9 9RYcnnLoSHV/wCL+xxIgoHIkx/gJOKK0OmftIfzzg/+UUbe+xKB8xg2Nex9juDEVdKMQuPR/JVAE CqIiDI10UPhZHx/fKaIj5DlW9OWs+s1a/hKhUTdCNM9f19ArVoNbKxTyi9QdkdbEZwIalC+9RIpx P8QWgAV+UGD9hyVHlety0xejX/VOVusvoIqtiUaX/LvI1Jln0oo2k43GRtOBGsWX3vGPngOJSgCP hHmetkbcNAmYQrd+XRiGD0ecUgyCPwNaZwOHuhccj0hxMmkMsIhpqqBpSf65xDPR/ddpZ5RSddOu MKgyiFwOUXZa+6lDuJeupeMTbXETCWf6seoTKKd2yyp4UHwLysVkVA22hSJPKsy7jWiWzHMtK932 tN51Twsl1K3NWHsGognKRpb+XakBjFhuD5Lt0AFVoFFvWhd5cdLUgMKfFiZwCVGP9WL22uDNlEH2 1Ek1c4S+YfIQ3WoVjKGrCUMhK6JSvd3T0l6SQZ7LE+DkgM5ohL1FZstuaSmmf0V4mJaV4QX1vCdK E+DmWh1uYRWu8WrtFyhN2K77XhlwfcCMQ/LpE2Ej4JXGsqCD5I8zWr9p0Zt8ljeXmdqdDQ5ebcxK 6DUEfJ+uPnwlYWDhmL47YNg/ArHvoaT2mStqNd/48mWzFOv9zC3aaPeedIJOzJnsCLlIMXDCH/X+ 7WXOhwmXkKlPRBdSEDBTEZljKy5d4nj3oAUOUzGyvVzw0BQTzTY5d4EYIu7JNj8AeX7A0uQ+zAF2 iAfWb6DxrjzWdCDCvjLU2amBR7lNxGBrA/QvAGgXJK55rEJ+F86vm5grc+576E3MR9CLlYHtDqzU khjZlMYuiyhkpIZsV67dSPh1fUQ3nD74ADzATffPT4UPNV9ZLRp+B3u2Zb1SbcB2SGnCVAsWnabL 3U+lUCygOh3WbS0k7QC6OzEKCnPqv3XxjajdjovOCM2Xo/6DqHgZ5J+tpIX2z8DspfzkDHbW9KEL p7swoE+8+mQvlifd3ieNZco9zVPwIi0T+x9Hllut4SoQi5qvAuq5FSQtkoQCLiGzb4X2iBSq9wxl jyuHLzb2fFfmaTQ3afsZtGr3Ud19TE6GaP9MYVHpWyImm2fkE0ItStlnTFTxoIALdqfribgETNp7 rv2PwNAFIk6wFiMg+Ikx0VgYz8tJmTNmF+nE+XmXpDKYRFEWvHeuOHtWfgh3UNwcg/0ySbjGHp0I YycB/g71RGJP1uufXjox6s9WjwrqfkAejHAxXXTjHyB75YUF1mQ8dbrzbcpNXuo/ILoyOMvLITnX ZU2ghMGAzTuDfGCyw43kzyaz7deLIKZt/x48d9oo4zpibODCK3w7cffiYCst9VqNlSY/gnqyBFXR wMR1pXtOZz8mJLDczxeNgqNUeZbcHEjNxkS3rudh7yVoXKgJkXhBVYdk20prq45ZBvSbJRLDSSkK PcC80XfhRukSSGP/FwR+UrDOpH1yqMyQkW2jEF8+Qkwh4aH3Zhbno5+QoymNQ8RDhRta+g0NsoAF YVGWef/NGuM8BiTiPA7zBf49qhphvfXDZ70Ip6urDkHluymW2UKcqzn5IeqwgP5Y7g/I1YSaPF2d fwXE45Ev4B1ATnaLk5npuJkerYr24ZTVX8ou6YQJKI/i+eu3aMM12Ze7Ldqtm78v5acjtkLnX/5H lluYy74RzJILe107n4B3Q0F4GnOFFPJgT6TkA6XPjfgMzcvFPx8G0HJJJLMb28ZFNkS9WGtWC4eQ k+NQoMfzoEVz+103+4kg4STS/+daiHtbn/eTLgWL06QlEhymZUT2f93MjxQH+ylP10TRIdFJSzWA Q/DhcptHVKj+k6ce51OgIzoJKIE8gXpbucbiJD40YjlQdC123vhNb/TXeyP8F4I3xDc8wQRpugli i10oQz5m73qFJlJdK1VfEa71VDXW6VwJcVW3qRbAhCWSeV3C4m9Lr00WqU4mduNmEH53I0wZKi0W Od2gLkBnO+Z/VMw1i+hAGaeVMDBJRxYBtzhssZArz0D4b7ZDOHWU1A5UE3LMaq6DUgYN4K+h7zAX S0Rl6Y8/ATsVd1h3yCVHCQ6Jherir1WxxhXTZ2b7V0egzWX/1Hntp/nl2AR/2jp7ctbkWgect3HZ wSA9YrPuLsWgRx53VxqQ8fGaJB0YdFtBWRsrwr8JnPHq2g/gi9g7pZdDm0i5eGPqV+z4klRtlOfr EJchIncBfY9xWREsXauOrEEVrX14JzdKEPzoO8piGN/vZhZCWXBh+eOVFNo1RpsGz87WLbr/24EC O+SR1A8ELIN/JzW/y+WbKoXHxEitycEPhKPlfdQ7kYo/3eBEwGsrUYlnwSkrWo3x8PDZcAdNoOlJ HfFuBwn4KEp8UWYqyd012KPIyuGnS/9PmwUYjiPZz5ORPcIaPL2R4Hf8WTorSOLqsnm8sIduUq4J xm8O9inkW1SlnTW3AYvpUiBGo1Vt2u7UKSprmuwQmAlVhFtOLIc9nf2ZZFm61Fzm8W69fs/Hn4Vk ix1gDvrQwKrKVlgraaG7px8GKcsrRgHTxDrlwsjAwHmtGgf7Rqmbkeuf3+JzSzkNaonBEqTdWKiX ESNl1X+YoSsdaqyhOsDdynBmdqyiB0hxO4pxd8BPPDWJYwuzXdwweWldYOcmsryqhP5g8zQeoBGo WjQTPr9JYUnc+QTT9PbLWR+p7+Fxa+97EpviP6VAAxnYLOkallfFRm9fSuS9HcnjyIw13DYSgHRg igGtUqGWaHuBuGlv0hTf8ity4I8EcuREjE6Gac8P4936sSH3uFE20slRZVFgzaziO1xK2apZ8RT/ LQkVf5Pd+Y3wmEdY+iUAuWgeeZe0XZeQLRwqAZc25gKEWKk7X1iI6p4RXtuwDKQPDwauo4fLS5xZ wm4190/QOMBnxkAan2xVnCLRX2rLzCbeNNioABs9qNFJG/aHEtnNFqbYa0/BeZRZxX9ZC83dTDxu JTgDi2pxKE8xIWBtcyyaNjAgO6YTmqhl5uvjcO3oRvg+LIg1SivFLZXN2OfTmFbPw003a83M+KuT eTlX2Yd3ju9bfNqb84MMGgA58fUn/t8LQdNKFjNczd8zAMEI+QFl3BeEtbfAtkEtSVubPWiBIQ+N Lv0S99GgYOi+V0FmB39XDQTcZOkz2yi4Hf9kCqAhr7fowfyQpCFmHSjFsq6qQXhJy7Bnn16qqwJ2 NcrloXZYxBbbcvb7weFDd0+0bkCskAGxOvoP0YKmDZoKjxspU7njulXc5iFkVLTq5XvAgUWsVasx 220ZCGe4qbR6akR+TT9mwxjO7wkKk6zOU6AlTcWtIlAXYhiqQ0vdjQgSqaYKbeMfO4SfPzxAeF1O 3XIEV9SiirXPXTFM12ZfSZgzxFezATUP0K0SpNK5uhTPEj7XyVnn+/3a2i6Ijh3XOQYoFgnGaW/P pvwbninyoVIDktGheg8EivLF86+JPNe9Deq4KN5zXolVW1A/Xa7tqKpEGTgJoIn5nG/B5uSH+Qa9 KvnZIfA5aIv+eOj0HFCJ6fEHye289t+YCHZ6VY5WOFkEOSjAFniC25Mu+SaCowS67uQwWkj1qXbs LO0C83nnNkN5Nc6qGRDqwAzGFe1bTW4o/QbJOtydiOpWi7IHNnmYt0LQPZ1lb6ufHG0zRvdrrE08 /GhsTksUSXLvENRJ288JyGDTfjH/8FL3SqZ1gS31VtNcGBB2Ls8uSZCGfSvXg5TUX/aDEAJxLAhM c3qiwR4gj6wFDjlWrNIK+6tmxtK3UKiaF2GJRvm/HI3xcaawy2Q8VfG0PFXbhuFl90ghosQpDg8t rxeuFmG0tsLdKeWML3SV29zeXi+iyyXpRplsIrzjvGSEw9KYgXByIfWulP+tFHw0iQtve6tbz2d8 FZaMWtLmD8Su0I8g0gD99l2zHzkfvTiPAy8gXuSA2EWyA6L7n4+bhaZ9Wt3KOqh44D+Cix8w4G8I lkuL3dAOz+MMOUIxA48LxWwzsLHg5oA2CPSDlhoz+LGQafS0DAY+sVKhyjchsuZxKOMYf9tauYRX GnkV1F6s3RGqlzDQPHjI2nwQrnfGVHrOkfZo6AtlfAwiiyi48l8SGMyd7leUKldxnrdBCD1fhons 18TDCkl3ysy6x1baXYTOaDoqTLTY4EVDTs+nVbTu2LzDB+3j4tjjxQLu/FyppjPcO4RqALlnBZ0D 9fU7UAckW/0ycyYA/B0V6cEJbo86zpZthMXxzQZloRoFp/3iIUgiDWbxNSYDLevwFI6sKS3wm1v7 MlZzFejQ6olrykPjPoFpT6WMpOdeR0AJyTrEshDwfe0RFN1iwbAYqQkAuR8SUrLj98dQXuFF07EF Yt0YD1cqx0Jj38ycQKdmMm3Mcu3oCqN/WyXyO8vgoyCV0jReh34jbG4oS7zkvZJRu2SPYvQr74aR W1GM5/v4rmGmqLhEKnNSQUwumJENNM7NgJO18bXx1Y18CF0r64ZsDayERq07BDog7yPoUTGpXkX+ IsmtYx9KP/rHNLSgXPVNbm3sYPbgGEJzlwKgXo6OrBzvqb+zej7CvXKWkStq7uqbsOLzlTxKsjYI qvLtzh+O4XmmPr+ka5eW4kZhh3mmk/Qb9xeb+jgMp36M661v/I2yPz6QbF9nSjGV4LyEnbxlKKx6 xDJw3iXK7AhJSbqIPtU6KxTPMgdfcekwQ4r9k2H1C3T/Jj9JHSt/icQQZzhY2rLbBbdc5E5YkCB8 4YYhRWm/si8h4QkK6UtQLi16fNoLwKbCEWEriaKBDfwyudstWczJxvk/Bk5VhvAPm9MEOrNeKG/i ucMOunfl2zwdWh60OlqUtRgp3QTzEPiRSO0NIntjwg5RA40Vi8VlcmLcpHdEW6+7E08lyyvM5YDU VBTKg7efweWx6cNd32BKMNQg4QIHjeUHYA+zPerxlw03RuQVSnEfTSOXQwRC9kJjCl0J4bY17w4L trFyBkcaXkbxDEAUx7GTEeFIGh/SLPwwDb8pwtlCqnDnfLWreFxYfrtQTA19LYKilWcWyWwdGXbn HDyeSP9bkMerEkOw4yMMmcmQNr+FbY3R5oda2gnvrmJhednMsN8rG5rh+/LZdX/nMywXdnWu3xRi axHLL2LOoO2awVaaK/GtmSpLBQgCZJTg3suIoOSiINCcF32s8L0l3aB+kNJVUEOCvXXzjcvGPi9I i4cYCUUe8T25pDV7NIfAQJyZ3zBeBtuzeaTEYJZ1tr7iuu+JeD4vG+eYhLOi7fnyogSIfmftd8HQ NM7btqMZZPFOmav9VmLyGHaHILNfCA+clxXrQRAqvGiFwKa40ZlDG1O3sxt0BH9Tw8MdqprmEMga Kqs+aOZkcrCTf3F5byI8oPK/Wh1wGHoPFvHGOgqXTALkw7jjxNhmxhY7sass0+v5vOqFpmAp8sXq wmbeeC8nP91G8d2gH4+WKm+WzJ1XvzXfbOvs1g/AuszVwAZUt5L9uyGZav/PW1+A5wfOjc7qj1jJ 2wFV6pF6uM1KOoi7jd/xoLb0YGrdhMO09MaWQbaYohG+wLePnP5OO8bVN9p+ISytVzm9AAyM0NRP Lmri/rwMl60E9vpIgzrYteh1Kdfn4Du0SfgOebaAsA4xAX60i0y6Uk1HuWgMji072wK2Ws2r7mN/ zbtaWPizAYvCyXW5kt8fRvEqXDvPj2T8bcGnMfsZnrpKGZas19gWPsl3pswMwg449B4cc2TiR4h2 eikMS9abDkgOd9/v9Sy3FWQOb0WISIBG0mcIP9Dh+I7FITX4na9W5SnmLUNmcxE9oZYGZXHR44sJ Nywu7tBr78jktNamLCLjuMeYPKoUEkpOtxipIspT98nDQ72Sau4ZCmEtV7BpDG/DmXd0NzOQ1MlJ YKwiF3N2vkYq0p+un249STq5N+FbcImCW6Xr5QYgoHAA33CE7Gus+jTQZpDl9+OmIMn+2l+SLF5A Vl+2mE1MEXT9SgM76qn+SccGRIgj01jqeSm6YEge03X6btjDu48J/1Pd0Li/Wn/89G30yFD4g/e0 qSwxPbwO/oeQer99PFovwC0FFqxnopzBoGBbVcXfL5L7sfwxHipHXgfa6PQNsV64+TBRXTB67CdZ 2FOr0v9ZIi1JqDSWmUBbwCgDpNSUfik7P/CMpjzU5hmAI2Bo2Ty5b2dXWewpCACARI1/WfOtCo80 QrRcoJ9Y0wltQgykfavoQCm3fViJ8htEBmeUG4Si4X+/2E8vzAMtXTQHtJp8D5bCnPn7LPWvT08Z Efw9zYIebaSx1gP18kpI7Neo0fHB2i3AUFtI55EVwDL8AK3XxxbklLOGv5zYxlVmFnLhj+a0cIwv s6NrjoHKzXDGpGU2Fw9kVZ8tSw40Ozz1vy8omLthVP2582iyrtQI/H4m+DcQ6D6MkYHnvZ9EVK+p 0Z2wpwqkW/HtO2uc1T2kfoT5meHZZdbFdDktKw/bpuDiH6xd4QUDjaGBxrvhbYjFnAU56OpkBY1s s/pQNMFEpbyjDMnKQDtqlz3Nc/23gyipg3hY5vxezcS+8jmcs7adkUryri3xNa66Yc2HFyXj/0bb 9SGSr6ILB6LGwhlavV3PUUSS20mTI0hM3Tr0yIY8xEAvAav1yMi4yPw8WyzCr87/5KGl94z/qW89 5+jn2UERedMvFzE3ImY97iWzToHSxrAurctmcUk7SUmRRWlfODtINpL43dJAtuZiGcGHluHwJTy2 2EmDUQy+MyNU9C57Y/zK0poIkTkpaXOrPyZveRTqtCNyT1+LXMaOFZGmbGOXjl7naPHqzOguhHAn tHrLvy7tzL4r9Oe+gC8yhZj8MX8GZQce+/4N3//cj5+ZRvAvuNtBqQimL9ZJ+bLwIOb/ZRc0/FoE owcVPXt/2qJpFVWdyhjqZ0sQwxRBiTey+6Xnf08B8SbBjLPBj8RXI77u2yEuadizrLnhWykVaLcP 933eGpEl/kP3TP5AtBUtzqNcqr18nZaq/Q9I/5vPhe/UbinkAGAatqR5k0OuRL71mI21g3b6AlxA 74Pzd7wNX6IIMNOdhUMKZBF/LzXiD8KgOzkpHk3cK/OJTbtTf8aL3KBG9zezq/YPS5Ayg1tVsIXg syW/EBG0ompYtIWSwglVmNefWw3brPChoEGkq/qvkWXsF7Ji89RdnmfKJWrLY9j62QlLbHMp26U8 zjlKLHASH3kCsXQsiX52fuix5WBu/u4Sv/cc3Z1iayR9Bolj+KrFYrEtCAGiX/3HGLNsLK6D7oLx b2Ep+X3HVMpWvap0VCgOJL49K9ENmT9JvNPkx7xgdTqtMTZofPvUvWk7/VWOyLqVUfpVL56VZ5OT TgG3VrXBjHIo0Mv6AyH0eCYCylFJu2dutb2cJUTUB5IZAFA+/X3/EvsoG/m/9TAi7w2yTudUePju opI8jF9+eJ24QF8jpFnwLFinN5aLUk0y5YKTEMT5atp0+EOrjxPTKXt1BirJkcGJdAIjjfS9D7MX d7Blxb+u1WmYO4JqlKlR7XCQe7y9/aGlSQiZpy1mqyvsmadktBY0ofbiPQpSzvwER6utZ+XB8FsD yhjdCxembGWggYoZKEtW5fQPVHJ55JuY/uE4ZwYMxuFdy+AD3rdBmqy/DF7k74xlOzHYAgJwVjML O14jsakRzlAoWLFeL3Nq61BZL551K7TF1vfEWqHZ1W6AvihkdrxZXyTomwMUPydU2EUvHHhFU+Tp x+LgaZcdxXwJAuCCBegktMeUKVVFiFTwfxEUMOF2/9eZmFzq3W0+a1gAeExVgqyc7C4sC40S5f5y HibJ5GXri1UnEHsUKHy+6/poZO96UAOcRP6ORc/b3uPjvJUYQx/kUsmZ0P+j0SzmDgmBJeSHS4ji oa+ffdDn9nhqnXM/MvxlBsYZRfWvuGpyc1cU7Wb54Pc1CDTCpM3eW3/xQdZsaX4BUohQu4+n7ijT Mz6lMnqhf2Q4kpDO4QrT1Ur77RUYMVDfdmJb80qhzcVqmR76KExX7ykYXIKl/zl9HqxbQ8rpD3G6 v0wsAGh5/YkWNno0TCXcwcYVW873shkAZUrBO7hPiiwlZKbw/1EGMs2zTvqRAOc9+2KjFHhF7s6m FasnXJuPYEvVDfXNW3EpnnnieLO1E+ozUvYuImC/0k6L8bYsWfrYtTBHeDYADKCvgqmP+PkppdpJ 5U3EitGQf1tKpaO4n5Mo6EwddWml/fe5HFo18wUf723Ei0i1bp8tHP23Hav5ghbQ+kCug/ysnr9Q joZZrPyksBNNQGTkOFvBLtUsbss6+7KStG0lBRbm6Y96wyq0mfJiPOEUn6nFeOu+AsVRN6MhFMjY zZcdUpJOEqhlKSh5uzj0a1mmTzl7dg9s/bh1xDDnNG1nUUocdm/IYT7r7dzb/NVf9UiU0m2mcc6A z/ia4nMTJhrGWsMuz1MSkoR/VDFhD4kOQukdMvjufLbA73LWHtcZ07AQnQe+KsoljAh4pm+DTcAH FJQLcJUzE9DHGjUHBdU00QRoRpF4xFEKVM0rMH4mx8LyYQZS6glbiwzJTLGTCJ4/qHJ9DWhSd0MX 7vIgZYUuUQM9FOV9FBZNFPwNEU/Csn7lMyIc9VTWrKKeL93XDhOMbwhBqaF3Pwavgb//o9xoP0e5 Lq5UcVs5ejRaPIViEEmyzBEJiAg9M+2RGVgRrMpKzoUhnrcSyw4BG+VEODdet0ARJ9q4SxNCcXgN UTEoPdBnU51TvqwCm0S6Kr/3+n8vDdaboUJ0er3OC3GNmYDUxwvhNhlXBH30JZsx2YNjSWqX6UCk NoIoj564qIg8VejW7Mz+arqBBbPGdhFy6dZcCSJzFeflPQ48/H4HkMjaCTc1UegGN1QR9osJiYO1 vAQ+Ois+fFFoAXfnHC+8Hepg6GicksHC+GU1R/wnYXoWcscVo0I18FL+X9RzykcsoC6kAuT0Tp/S Z2GDt342lDnenYogqGNcMGrE31UWWv8d07dpWYTz3y1BORFP7/zRYzPiu31xqGVbnwel9/NRdM2Z Pr6iHkhWw2BS4wKb7fxcnW7Q8lH+LIVkTotQBaOj/w+gWb8geHX0JaI8xEWPXVYo1cN5+F1Zx5Rd 9sRk9FOzyTBYyVtv4JFMgDshdzrnSr5zhlTm68OeLBTiCXLcyLzdh8SlMyaHWdqjifU50wNK1zCb WWtQyI0y/L0LNOSGwc4WWpm/5P1/KBCI038oO9JAcHWrjFZb0C4fFP1UNoRzULzKQMW751IJIq3z PCFjacsdC2BmXJgjF0sqfiAP9DaY/otd5/HURsXnRnXU3oOPI675p97mZSVg67cLCtu3cvyFYpwL hR0eFmMEoYSmijsHCuVsSN3BARHd9ShMpHaxnB8RGWJHOgJOT1Xt7ZPUeU9oOcH2QlK1ajGdFI5T vvRAlME0sa39Rqm1Efkgcecqe6bjL9QbjFoa9P2C1Hgbp4O6W1qctoUCdAp8qzH05cW3Fk9Ty/k0 s1BTbhgkgoOCIt3f+wWceIn5ylJAOT45jFeUS+1eON6ywwy75PytMkyfOaGh/QJTE+nsVRaviN1u gz61wl57YrRaTfvV0KthhL4aDr4qt7O2Dg09Du6XKdtQPSiSEfDKx8gRPPXxoVTeFqDUDKyml4+p lLPfHmrFXlMFcTVPZo06rY0tdexhr0SVmriNxJ9fmx2lZSTY1HuL/trsXB7k9oVFXJjxVwcrjuAH HmDolKQbQ5fcMutlE3utHcnpkilighsoqpLnk8l5aSKHt7DYmbpZP6eHp73VhkZ5gLuoBKzBQ4jS FBYNDxcS9evnq/KZlhYuGqCIGdfYbDpZsIltccYWI1gTlPb2x8OFQiHzFUoRZ4EX5MDM8/gsEHp5 E02vKn76cj+V2D5zO+dZi3plAgkYE0Hb7C7823eFY9wgmBhz25thJQIsduD6ZsL+JC6tAunp8a8H xm6SSwiglEIDzKx5TfhPMDJ5Ow6mvQ0NTD5olo4EZ10OAjOrSO84T0y8oQZsC6gXz2hF7NbDIRxl 1I1H45gB+Y3ULBrxRWKPlZa5sULVKJ9obTc2AQQOR9iwPcZoOcSAl9ej8H3MpjZAmZOHCgs3xeiK S/Uz3fNQdeBk06FeE2f4vJZXFqljFZ5yoNCYvDPOYtxMh/NDxANDNPpCyN5Lnd4VNzYEtlLD8QON iqOOde4e2QyNEaIkqb31GiC4che++Ka7VkeWmPr3ub3fRzpDy/zCKGEl7MbrGQbL4pSz/GlAbyyx FXY2HvO8VoXZdwwhxJA20/Gt+t6XNosy99A6d/7C/O7sfH5+nvT5t4luhF4LHdntFy4Xhp/omPnO EE1EpEs4Dc1S5M+O10OSzlKrqKzFdWhncYkjAAvtDLT3LLnYYvBJxvb8XACM/Qh7vPektdIa1Lre Apl/hFv76p//8pG9iTq4WTLT7CX0doHt/UYEysKLfYA+CJL/3z0Rerxar1nOizYKVSnXTs/cnQNO vBFRR7oGDQz8RGlt3s87UcvWPL0zf9pQEKFGIINRrZdOiU4xoLz2dXBxM9TyxbjLUbfWb0DJXM/3 LFuWSoJUwwFQD4CiqxfIKtRXtdhHAj5J/kzJPSb2+3adZzowsuof8KNfv63eZ1TuX26fiDH7IedB SqlYpPGnYqIc18CpLaXUbldFr4dLWB43UXHU5K+PvmT8fCSQfC9KdXqsuTnNGwBfMbvuUtYRfcAF pwAj0FUPTueRO+2Hh85/SVKbUVcw7o6TEUaAYpOrbvDKxQo2yTEcYSl1XOTVK2LNmtHjCSxGA/58 BEes/7B+1a1osSKyS5cEKfx28UWpK9LQY0pVW8MHPFrfWCNmhdsbRFgQtk1A6WmIX6ANJx5HE327 wFseJPX07m9RDRLBjhbcBY42uyDxX50VXkoYN8/5KgZbt4sRgnAJbnEGyS9wVMrGboCwbFA7zhH6 u7B/zRTuWtBiq3dC4JHchbXUi7Nv+82SkCOMY3Q4DNTm+ziSZdHIttfHv5xi/SmO4e8HSy+44bp4 ofqSxOOYPA4fiJc+ZkwohMbJihDwdioz+K5WEJFD2dnsx2CxULBCqL2Em6AvKvcD5sxC2sN9PjEn l0yz5UzFZMCWa1Wy0Br+U7N/h+rc1ScicVY3f+HnxmQ6HgxRYMVdR+0SWjtckeTApzqZAambAGUs 7/CfsvwaOk0Z+qMBJsMFVP1GVQirwKaviUKzmpdGS4hLqpB1MN45zOMS/fSFIoFRmuNZqmEXW0eL dqB6McE0p1aWyYFGAXjRZWOSazRdZWvWo6BaFgiqhD5hBujDwh6ftXkvpawSRoqnEjiiFo8iHyR6 TnLci6OeR2aRe1ZAiJCddIwOFEmeZXQJbYE6fQ1yn0OEJLPRX4gDuuHI5utM2vfqRY75/d4AO8I3 s8kHn6Isyf1YnrbQr5qNKjahUSm47QroTnuJIfwLp69aqut7slXUuJeaSlG+jdX3o48TVnwmHWDc 4c29Q+qw2SzzdVj+jWAcVxlvJyLynD/6CVk8uaLZvyyJQ/gUp6cVPC3kl3yjuF9dc8bKRC5NXz4S 7u1jzBFJeXVkvysUE3qJabG1D+fB5Ea0seir84n0WdOdCzvQFwg72fiowp7yIpDIOAA2q1B+G4/I HP3/HAWsApK9MZJQTNeirqsyuSRYADD3dPe43nH6Mol4JtKzKAVsiuZKxujv5kIWYPazO+ngVkK8 aUsFy+f9jRHk+bP8qyyKaHFcCg7f39VihoCOxEhrufS6oJ2xJNIp75rRPmG4uWHWlCr/zlCT8FQM R3w0QCyQpIb7hSzZdU0CMa+AQIUwe6VUzWSeeftmvWdgTQEVb+13oTN4BeQ6LtUkKidxxtTPdTDM 1quBR4kp2BM+F8ONwroVNmQ9Q0OOJMcddJnFB40UClVQzypPS6wGwAW07w6Rlq8pXcX5FsLlNRRH 1S3VNDv5Fu7hHYLA/nTCOI6sSr2LdidIa+vPpWRy01gJaG0mJg5AkTWfMofsOsEIAWSBwR/7ycL5 0mEXBV6IcGXOrPrE8fjPCkgPbbf6+0/XKktS0RUBfppbPBAboXzbSYcfhKidsj6VPqvbwQ26jR/m hZWQHqRAdo9I2PvSZ1ZHFY3hoevySU0p9CkEYfAIDep9Ql56pdsIYhRr07MP02wpXPBnOY//fdEx Pc4pu1Rgh8CL6pFjLvX2m0ieAa/2inprumTRuQEVq5h2ketyqyTxVxSZAWkIdUWVx4T8CmQE2qiv pXkyVPrcgyABLXW59T2LFwfQxDWxKZC0nLRK8rto/gAlUr45aK9BMuJkbQbxKmwsB/2m7Vw4UppB QpFDeEXr1BxUy6uc00L3gvL6zU2oZXaWIMUIHR6HRihOyr9M5ir7GqwAiXkJnA2zHzkY1rU9u/QN lKxZezUZFwRAlotukmkQQ6tTv7SXFN6NJMQ27yhNFaifVV1/lpdjKLNluAnjrmDJxwEcygJtN/Rt 1bJ90rNP3/n6R9nMvCZYsmyT/zU7qxnWnE2RAh5b2zEvkqkz/I3Y0YReZRsZI3c4ATdAduzyu5rN 4TH2iSddiF+r5CIkjXZOmZ4AG1q5CKyQbTnDO/7LzC6eaXLipyAhy1Sg1oNnJctEMaxPiQ4vK5TD Xy/IeksOflwI4boMSH6xcMeyHTz0bN5ctlqkHEjDhPNm+QxD1UHex77dXo0cdqlQIQTUFFHC59U9 lxd3RYteF8xaqPJvO3LOT1bwQU+4CCG/DkzwdPa8dywHV92hkn+aX3i3IZU0cgNw2B0veQDfxz2P Hxhh3mMDhbtOH5xozu/K9r26nTTyliL6MEcBZK/9YfqgRtDvv25wby9ucfQZNPDgUcuagMBkYEr0 ofMfnXGe/K4p4sOtCQA8538w2Qy6LgDAPg+dJj4ZzeQmEEpOFh+uxx1NAHYlHvMG9NpyalH49ntO 8MClgFW56KxGH4R+DLXY1ciZq8y2PZus1qc1NlCHnV6dBAR2xV++6sE8kmx6BZv9OKNZ72og6S51 xFOkAd3+WgLechTDpzBj219CbfIKvvL1//ZE51Th2uDWZRMHH2sMsZdwPgbsZtN+Gv97QyHW8HF3 SgYqJLvCMczAkAzSX8vRxgT6u0qgrUKKPcDDIHvTgsd6MpVnHGGm9ocTcAcXvqiYUvl8ls0ChwAX 2QWLP4NuK4NRykQ/hdIHAFfZ1gK4sWr21HxGBZAgSxIzlMtpOmCsdI/PWXI0EY/rAwv6nKjtjeS1 DZqdywBDcyXz8EvA65WVTO326/NitSEFiIXONx9ErPkuUSozHJc/S3MaHIqKl3Dng0Fs5L5/wqiF 0QtOGqpFYz/vueX+L4Esq+BdDLG7qzoUTbh2s7rLcPhRT2Mrw19sx0MmOSk1YwgPaw318I9hRIzW KpX2q1gv61I7bHOwvVat2JM2I9EamMwLbRRldHB0eBlemUUtRT/pRCNVsWtloeYAGGUD1N+YNy49 H7WiBt8BU+dzR7Tn7NuO+s9NkzGNB6DkswwO4ky6RMsSQj0Rh2c0qHkdgf7C75Tco5/8a+MyYy8F wshWV3H82GFvGVwkZI19Oa2m6yPWAx53JC1TcvUyCfATkbaxzQ+IRq9+A+6cKD8HwfzKoqoBtde6 oDdGWCs25dPvf9c1W/I3wCNwIscBpelFMgEu9uDlc89ze9h96TYCVZXdpBazP8U9uQvN254Q9M/w FOOomAW9RWTEV6h67m7CMTkd8BKughYlDNDqbMQ+luDfNNkpdyGhgMKlIaFG21JD3fpiOnfFM0Qu D0WTDx1G81r0yY7/WKVFrnCZZXPyv1mAhjQch71Bo8y4eFRY9rzrgISeJJslqHzNvjNQW7980mxx 5ViQAmcmH+EEVhMKDFp5rHB8E2Bhnt+25yczcukO6RIHvS+LB0hceLgh20o+MT/GYuTduwtFZ0H5 wlk0t/t6dFbQCVf3/WhIygdaapdF4uuhneVc/AHUXEzS8aFSxZ4Oi+8++6Hqu067yPNu+mKQs3mY 0e1rD88FvSjS+sRRgOtbT33LHm4jiB5ZYWX1RTcOwYXTXnCw2s9/uYF/QV1HVMH269ZIjyLvWWK+ Q12YpXE+auPrL9F29XXoGL+RDIrUT1waUUjruBaHkbxTR1UQxuvrIxdBAIA4oZvhFF3YJ2wtcz+m 7hyAHZxG0F3+54Os6g4MQ+9m8bHZWLiHnhpNhsrUJeCB66Wylx82g7stIN6L6OXMo8VhNeY84BMu NayLxgyL8aPkzluUDJb535P6q6quaiEFezt/rXrLkFj/BdfK/LDPTYpJMPCsvjmG9Ho9TEBS20Zh 463xx9zLcDizsQlUtrh62kJ83Tex9NlQ+meaQ3rkq8Hym2ZgxZwh9C27Dil/8xJCr52uUKx5lSVn ryTrRdTt2SObsfaHGHoNZJXzeFZh4W2UpYCr8wkYTV+CnevGQTw9V0hNSs7Yls4fx5Qh2jkNjD4X c87k2WRilCkU/2fr8+z8kMhrBdLfJUItCb6CuvbjpGsqB52mZ04J7Hg6rb70o3cQFewjbPsOkp/T ue6Lpmw0Nvfn3PnO8r0j+XzTRgV5uj+lUSoHI7GkCZ9hi7BRvSrzfv2SAZ3H24eeyB2NJ8plq3p2 gNhxLMqF22yfifwAkDfBuoSwMIHqD9PJwHAX2XZn0RH2XdThhtP399XQ6E5Nl8+i23ZRkHuW0O4Q cvp1HOsZvwA1vDTL8gjEYzIj9X4jYjuZ3aXy2rLw81SWKjSAuma42BmrxeqkUgYxgug8voHusaDI Vdvu/579wO5tgPcrJaWvvtXGQ+uts1hWFkP6qsFuGORKBDY9kNAR1Ay/qhW9LVap1DNiz7HWe2FC JT7GDf/B+JuAEp+QM0rX+o9bW0JYzTeQZNbDp+V0XzE8hDu178TTF0ub7iWBwq9/peJefPreQK28 O76g9DdUQ5fnaELd+ln2g/l7rq/hnyBQbWc2yw6Erw34+9uXvX7Wa8Kb8tEC/b5VTrE1xFyvXr0U BtMS3wZIneycyEkQLgjtlnZ289fj1gBbg8vwbzlpn27Od7h0BJnq5+NOayjoC4F7zSG3aow04CQu cW/tpSq8q709ZqEIlGCnR/FZJKLvTyKeimyxOgujo7GDJMmjkTQVhbn8SPj3dJqDIpR1H303W1oc JTXF5Az+uMZjREOYp3bXsM3U73CeoUt9ZJiY1GsYJLuLgeztOTtG1+r7R7WPriszEk6M6avKUQlp N95YcpUBTTPTNNNSUjUsz2CuYZSCesUNrel3zwwre6rXJtoEAc6tkJJxUnjAVCT/tSklaRHPvFYz 442GzDsVpIsCs9cNT6T6NA0wejygO0UeV9sjbNcX5NDpLfxSSPqgclgUqb6EfR3BTpoxfW+ENjDp LD81JWgTIooRjVt7dXawsTpG1Y+Jk88rf823M7AsRW3go7DPI+4cMBwZrnZK7VpUiSKV9qRjU7tl t4AOAdbEBgF/eykfHkoyxdh3BWKsx5VVcFDMHcY8TMqUUJZr82bhDfF9xxHAbO9GS2+fUfLoDPNT 68uXYvS6Es6PkDuAN2GVydk9r1iiUlA7W22MEexGc5T53AVgmUdtHDpXk/GjHHRoCtftYH+qn+3F tI34kkZiVFbeHOKMQEy/6DDaLX7NV66yBJZf5s4gxCY/qn9COOywvWnQ02ZNqsqNywLx6TtbO5Gn RJL/5JkRq1kD8ylSiD1VyQ5Fx7Y9hc/e9hEFkJGe24Il4rTQgCKb/r43qoiSA4q3/B/OuWhyeceX 7HbDj+Zsv+DWS0FVDxaPFcr9h5od1zukwI9w2qETcakq6LI23AeHLdiw0vB1EjPwO4+TNsS0D3bC gjZHWTsRqHfuvio5v72+TnHV3HPYGvIPeu7xeDSFm9yiSRUEejmHIaG4pUSvGa17D/CaVQ/DmpKE lXzpKMqzj3pWbBYWYp9hSoVD4Wsnkw1HMhyfBSzaFGByXzFv3np1yO645NA7GU/77Y7jvOHPsCQj /gcwUFbqDcYlUA1rxJKpDmTQu3RiIaxI/obNIPJZ7hQKSoRYAVJLchoXWLFO46r6SyL5iVsVfBnX wf0LmCU5LgMR1s3gs4rJyTsDnhlWXVoJkRaEQw8eD70h8ppa1cirM4aGcJiQRFX39h/5bvMtsEYk ixJStE4AoTBK59EQfi5m1M+gFOVZ/vQRfGHMI0MQ6xVBoGTKdy432El4BR0JnagOkThbROQfQeQX b97F4cwiPjI6G66awm1Rv7Ebc7OdeN9guJ1oUwRvVZBcfdxLV8oWQeCjYlq65HtgIj/oT7izngQH RftDGj4gCR3OVjjKeWebVi36vYmseBnZAZzgn82keFilAujllNsnjrOtzEJlYL1wZayFkiPSiUIR Y/x73KIuhaljPdIAQ/0xUXerotqH+GvV4H9efxnr/v4qOnO4QnHPCo/PTwz/zh0JhsrwqH3a8R7G c0zWkYsELO1daIOjDNZ2+YdHcWVuhEB6isQo1aWy2Q+HI9m8ir0kF2+Dr36uWuiqnJVZwJcSHwtY 7SGHHtE91tGVbdM36zSaenQT2xPQnP6OmyXo3tewcmn1nQu+d5KmLQ5PYddrMFfejVEdfszeI5wX GoVGEBKuy2LEocZYM7gaOwpn5Uvbgl/eSNOrup3OZC6B05lAAtxKK/WS7ui1qMGVPt22reS7VfVz zBlzYEkVPW8Hii5uH32zPiOcntupE/DQCkleRsFF6ZcQygfF6m/s2dQKLTPnxWVXL0WBu6RUfrIP xn5c8sEZpKg9vaiaZNW86IOXCBDNiJ0jkLIaUrTgC18doL6c6efIdPj3xTk9hRg/O7WN5bn8ma7Z FCV3CkMcGGa9ziduBnZ3tY/WSutLDaVWDcdsK+il3svkvu0BwoBkQHfGSL88XYjZCRWIO75PR9RE ebhcxwS8v9QARNJ6Jnqir7d5zXMLhFkqba5cholsgKgGeSdUaKJVmFUrsTfnmsMJnLuDK9txXGWd mFQ71Ae6iLwY1k0Gylhu1BBrXNvvvfV3TnFTC00CF8s0HQb9bJzCHiLQg5nkFFEiJZTE5o5b1sKW NjEvyHb+LiSSC2HMZQL/UA98IMvFeWdnxXkOsManQ5aOkV4ddp/Qp8qvgREQXxPShi/2xRIRV21a ajdjvKxyzZQGf0TFjW2/6EQ3uKGCurpwixf6cYayTUhnYmPg1OAClp9lQRbE97qyfVBgmZ4+VpE0 LqcdYby05FaK0djpzk/P523sQ1g9jdTCL8pjT1EpfbI+GOOBT0XXpo74h+lJy4DijYi3l0ZDqNSX yeUq1S9l8u+qdv1DTTvBy1HWfyVz27MM1hCYqnaGBKJwO60md9VtvKjogCjv8MF8zTciKRKqX/Pg Js1euJiif1HcpCz8yhDklgEMeaJMUkVDRUQdmv0Citu4RvGXiF4HXlLw10bpZu5tqctxcPxxeHr7 hN4+B0ysrhlw52gu/ZD1rsgBtQvm8eJ/tlPyMP9ftIyjNqqSaH5jeAp1d7qzyBgay97PleLvDzgH LH7VDeX3rp3k9t+AutsX0/z0o7OLe3WCDt0Xws2jB4+AYAiNvAY4k1wrtf4Lp2/XN4miS+YRXtb1 36ixpGO7uZB0z8k3RHHmXdRsNmtmp10NRhP7mjV2DwWjPT/hyrOlwK5svcU2TEtpL19+k756SNnk BLR4A9/jV2LzD/P0nrxTT5VMhUfCxoJGsw3n0kokn33uIO9OuHH294wDJ4No/WQzCPJVJ9ea7bcJ uSf7oC09rzeoeXigauvIDNXlEAnEKHNX1XuPKqP3ExytCkrBA2b4DluNhKoFDuH6Axygs1fB5ezN XAINtXIuHjqmSnj0KbqBFHjVTgPv31c0zbXDz/vrBAL3dLS3aXOmDf+SpZzeM3vwMDo4bE2cBhZe dBLMpqU2JXGTL34nDcXC8FOZMEvA++RStcEQsP+XupigK1SN53eNq9earYQ0uDawWmCBT78E84IS EsVLWrfxz7cZ2noqRc0DGb/Fok/OVZgzRfbuTz/rsQDD5wskIgv/jOywP3JsM4Ww0qoBkq1oEz57 X+Z6Km0CDONgFQAIRM+niVFQMeBvXVWCcoLo0bB27JiOEySz7Z9CSrCohAkx3l/IdDgaknyy4iFW TAb57iyTGBZI87oKKdqH5lV0K2DHhn3+wIKL4ej/X62l9DrdpyCM1lI/Of9ciZ6WaSYnrRVrc+HX r3ZKptmWeviqoqpaR5igIiGSTZmXuCSw2bhSZwypQCkJ5MJZonwT42CmL+ZZPHfbCcVvt9i0UIK+ 5gn4ZldCirv0QJTFB1lABazTSH8vX6ga0TyfEOLb4+YaffqT2IEdTGPhwPzKcG4/7OWie+jHfVGW BpEN3B5OW3g3j12fu+3fzUwc9h/ozTknvbeFEoKwfXct7Zz4pSECLMcSYf4NOJ7dHa+/TN3iurcN FvPQojozHXRT5axSheUxPvGiW/8xqmXgDoFeoGr3IJTqM6xX4VDOrpi63bxnB+zXI3vXu26JydVF O4WinZ+ZohAomQuqF/wD+ZCiU4iK5bjQHDPEvIe/pLeXKJs5QzJg2xN0Ou9g9YHujBBY2WeFQz+U XXvT15EOs3Lj3NGQuBUS1WMCHGeUs2EMt7ilgSz9lD4wjimiS6UD/HOJZesW+gywvaS7hiKxeZ3O Qg9LtskAR/x5CWAaT9Il7jHC0e3OrH71oGugkOEkBU8dSaqqbddjczbU0Y0T+677aOl5C9xzO2im P5t+5+eOc4Ob+33LSwG8KOESrGgQUC0vb1wmI7Plk+yGbeel21+TsBCLch7VZqp4V062CF23Fi7s 8PL/c1hfWm2WUWSfX+y4U0KvH3SKlXJ+s2kH8AFVg8RrKHiSkzfBUJULIdSsbAiJi0VIrNFe/mom 13MSNJ+tHLX0a7t9dVeFBAgVSqF3br82xf6fkeV+9TmNxCHUyXpCWMoj8jghoC0toSt3/ucWyzCW JvLQm6OR0Dpnn4/osSLPoGtBK9o5CRXx5EgPQ8INB/+rtK0xXdYVSwL7lANv3/2wZEzw8s2e9kdq LHvcEGWs9qijtqlrNHaoQYwA24ndb9TFjwP/tZeXQYLIWJZJC1OFJQ7dgfTKBvTpZ7DYVCUyeDaP EN0ixM/HLBfiBImEhPC3H/SOHNwOAmvcvJYMZocQSFr8Ph/wi/JcpJthBgOmZa6ay6/fN6aF0AQS RPsvcYkA6uC+x42orQNwTdh7ncZpexrPDTeCwek8DvOQYAzY7egtwqtGmjfUnVxv/ZBe2Oj+jnv2 Pi5vpxcR1YnhENCfLu62lJwPAIMUqjrf31Of6LbuPh5ncivVZ11/J8MAnjV9lZZFQSg59ToNd6Da BUthyVjSb+irW6olZP9z3qlfkr8EoXzSJw+BCAahdO2pxQkYMetyyBM+LYDXX4xn0YcD5I7hg2t9 5QAgPOqY1dfmE/R9x09uzXlXF1aeXH+G4/Fc6qXkrRWjXDakSYsF20T1CcfZ5XSVsZuJ/c9enV5W Hnt6vdyQYDwTwpakkMUVh598WBvEpX4rSI1tNK9gAcVXdUsXI2aJQaq+Q7YhlbWXablT7UypxQxU M32MorDxQ0jjPFsqRgPg3t6YVdgiq8LmhYLPbKOO7mxOBk0kU2Z4PfkKro9GuYd3ttVzD10vo8f8 p4obbxd95E19Mq54iIrm5r5ze3gThH4yvvmZy7699m4El41qxm92zowdCab/c0z8ifTOuwJGw5my CIyy6ogOWwFYIwN6v7SCayvGS9OTqGuLSlpsjdy2SHH0gh31UxepsOsivhhHy3ipNymQ0xpXSJWv Jx/hz36YAdrcum71jCHw5Axf5AC6arSFQ8ifXjagf4/tgTMfBxfBaSi4LZ9IAx7gQ3oFDnuU628Q oMloT5KbskXWcbmgIKjMTA1rpByvhOpUOG7h6pv4iLkUsrdrV1GyojnwMlT3OH5sbGPARoTCYMqt qVKRpLMdowKixUSgprWwrVcY6IxMBhSc+1wpFslUIXPlWNcTsvb80qjPJbOWQKgelsyCVYlWvbK1 Kx9+6GwAV/2KrPhyhQS3+LppIuFSIC02kvD63FGFF+8FZ5NdO2iER9vMvq+SJYlA4I7jUb0tKEwz ZZF09Oomn504oZ+zSN1jucg9h67Sfh1XcD1jxHBjXJBb71HGcA3cc+HWCum8WC4EFvsWEK4JFojc DGKGZJofbg/mhPAKwQxKuzJ3MqM7A7fDeyCfyXvFEMbwWzcn9lcIUdoODlWZOmNjXycrUrUNAmH1 F4WHbRSxi/6fn6yJO6Lvay4lQEkx8LT2ykmKO1m8CgqIL/sTzqVzbabu23bnA2yUnT+J4bkR/18N dR3zwK0y1rYoV4pLoLJNkte8k0RKMjKLhvZMDpxBrnZC+JlP2AdyNQI56EweOUJNimj2teskTwC7 uil7RiTPkFBhepCWYmQPSmqpLqlWoSOro3hf0tcpFcgBikBDZ9pX8H5D6J7s/XZ8WxpKwa7kKz64 qgi2HE5cG+jXRIt4lPrK+ShWeQKcBmMYjTnj3p6Hvkl2ayiEWZCSY30JMuiyUIr1TlrL4VdE7Hux /d8oMRRUNIOrDs+TQSLXcELaGe7qtYRlkpdnYrmlsjuF+Aam0YR6yeShFxn/AEn1DaoOLS0uXWbx QY2ppeadhzmSEowQ2PBl85zhjNsUkuML7BC1G4RSXxaHcF1DR9gTXdF5ntyJS+GF/pYkm2FQnk5h mvbkKZ8uf7WG2lM0QX5wm9gtVkxXWZ4LwJ3T5x+I6/fxL6VQ76VOweb/dO/L/KYWk6i1jXKPv6Ff wlUG2f3s+tkI8YM/Q09+FJVKnC2YqQ0C7MiqJJWQIAjbCZ4bUVfrKUQPYNiNlnQe5m5Ox8uLt1Wu 8UM78mZvH8OLTUs9IwkFuJjLYgdNhVx6074rrbH1C+rYdw1xv/4avEr654KtpDE/XlmOoCQFb9g1 6a2Ih5M36TimpF4IvcQ5wVAKprJbdfjNhp6ISyNrSqU5rLwAzXv+eypRFMK2yIrdMtYzfhQIzazh fruLpVnUASGW9TWcGLlK0oFAHRjAq/T9KR3Fh2T2fo+LrX7de+i6Q800d9gtkndcrb+i8Fxk0fCs kb/13H9OdKVQYARWOoT7CYBCKGHMc/d6VTcnTDgcFXZd+S4TPKvtTWENA+B76+Pfc1UTjhqArWab EIy9NBHn4PQzH1kAhNEADG+FafDgZb0iUcqhqJ1ZgMZssBrbHsJTzBsWSX23lV6pyY5KDHsnI7+C 3ojVactNevU6H6le04ZFe1k5be21s2rPYsngJUBrV87UL5bQALxY59gYN5uqp3ZMoVjzVIaUn1iK OHXaQ8vKeQfWvI5G9ncFuXonyla6K3MddPVGhLyVQ5hFB7kY3sfcQMneHo2GpWGB0kfGCGcwZrex ZnGerLk3HZpWIT8qQhIiwbCigrB2MFpCjoQXl2AZgYMrafu1sq39+db52WbLfbd9fskL92zIG++a 5OSC9jSqHgzifHaKf6fAWL764PeT0Yf2XdDR+XXPobdS494mILS1YAXgrLCHwPNEQsQHMbllzw10 OcX9qiszTjUOtxkZSPG2Q1ps6OYiXHy61aekw8eXLOx1xHoDQBDeEW3A0Pc8XMOkjhWMN8lfz4Dj 2j9AK4Ybr40HDys+cVXSYR5tdW7gPabErvs8oO5bBwx2duq/rRxs8YaRg0sy6cbQSKepiTBu1y3/ 0v1XgX1DNxOwnoKYJixLsU1Ym3TdNtqZJPzkVsh9Wxhpp0cXx6D95FfZgJJZOYv79kVSs9Xog3kf IEOav2ebcHrgU9lcP1AiqRYg3+qdIF0TpYS7ay0KKHBLSwriNh7hy7OuLHHfhpN2sJED3jTPz9j/ vEKD9Pm8FlOozUdZfhE0qt9qA88X0Uq23owvREqB1JA+D+6W/D0OAmRKX1xqqzwqxdoj9EasxUN+ s/VNa8dFg8PTyxs8rpwzcc7R4CJ3gHBQ2Ua4CN6tAk9GDZ/YXekSGtJy6WYBy76ay38njky/NXHq pzc7QlHSeWtwfH4TPPd8H1pf0Y5KqveGW+MlLrrzK1u0E5i54UatunIUqaTubgNW9GCpGf5eZB0y lPPiH94/Y/3AEDGukMxGTF6sFr56Mju/0pw04/ul8PsN8DQZdUq3Wmx2JhjRotg30PPqp2IceV2u Lqw35qx3OElp3t2SixGcfvM7h8pN0362GfUZnnMqZSYquo4LLvet2dAjiCx9q0eZFg7hvH26T+Fw VXFY8b0fDAPOJVYzkYGEbbnwYVejX5BCajmYLqTwUvEELINozu9DmPv4Vj4oC2PI2a6lKW2JCtT3 6ytr7zvEuVpY7geyBjQFvMpQ6UO4jkIkp82FKqLXOOKIZKovgeEthR6sjaz6DikurOgnzxFrPTju 5lcjS26BP2W+zAKGf+PQkWhjgkKX3l/hvKOjVL/fq5ybUWyTTYgyiHx0Fx8B0KK1P+KmyTfQEjgT 43OiwZpEsCgrdlysg3wa1ms7RL60tKTeARAKWgQk4i6Gpjqs1RpCDG3XxWbPP+9kF0JEbnqNL5x4 PaL9wnQmFLZGoWLrX6uDQCA9cv05WhhOdkXydNSY0VAr8zr8EZQhwwMh+EgqEdqiyfTh3fWX3OXD leWwpcDJ0roLU8EeUkoW9MPd5i3KvSARXLxXdiJZMcHDFsj7NQ7o4CbrVUT43S1L3gbyIgaCatQ6 CtrhA3iHEm9isqGZIT7b8VnAUI36nP2J5Dv8dh7EG06azh9m8Nrzbv1s8Jh+MsPahaBSaou/xMw9 p0YPi5gX/1iqqdgoqekY1E/TIovnIYHKwKTnNb7j5V8NKJ9UKEhqE9ne9Jhd6Iyz0ZxXJnB2RQ/2 nShnsgEDR9xJ8+OfzvAV6AaLOrEaeCGc+PRiOHO+F4uOg0VXNoKkEUi0peggrmthcs4teQUvCdKl CtNs9xc3PDavbHgUHQBN+qwYjwn5gAQk2bTs78NG+h7HyGKenk0Muo3ixQ9yA8uzS6MFvrA58i5W cDe64M+eD3tDRTH58UdSUYYUWW5IEUX+/sNvfkF8P6srCBq3eWrWAGfLi7Gnr20MUOzMjYXiHIXQ t/vecvxuKG55ktQWM4EZut9XF8ibyD32PLYMRI4UcHH2xuAaZDdjGtR+JXf8VZfTCkEwr1Skm08e mll1yk8ykyR/QSchWw3P4UPDL+dyyntaxf/aB6eqAEkT4KqdGK5LCT/szsbhe3nDJ9Muhg+whH9x Z7q1fPlCDlMKvWqmWiTpgim7I2W7PNuIzWKjt61XkieW1LnuJmSWYfsLBK3L3QdfTaDTJ3xFgtu6 IIBLLs6egMbT0jbds5DOUVeg1a7emKSzSTYjx3KOzeyPXnFdFV8rLzT68MUFZOAvuP0xVcjVucaS 47ion9yLa05LwFyXv1Zv2pvaBcBlZVx1iPgMovOQnw1D7n/8iLCKEEJXMa5MkYslWZ2xRnDyjf7M E+JUrOD1uu9K/JjeXUI1QfSKmftXbz7gkzCqyDRH32nqqGh3nfLWkU29/H+5gU3GeilfhmunfeTP I4/FJR3ITlz+oFU9mWuAjVPHekDkvZgHyL5LfQakkwWU/IlS57p1yzbNx7X935lAXaTvztaGvcfv yF105bFxE9Wz094EB1FeVU+hAp6u2dlbIHwEUBWXPrWhU3WQ7TZ+l03olTJ/gNEKonuC5YC8PnSi kuhlxHKvyS8FtnvVXUmPKsFOYUTdl6BaGWbd5zeKS7ysOsZpd6eX6/bEP+pC20j4bUEhDUHTCjEJ 8HCFe4O9yAsTPGtOJNcj8mIv925AXGaJMSqLLRDVyHht3HKdgfhE/2IAd5Gn6gTplGT57DaJhdq6 2diyDmzZzbNVp+4ICtITyhsUVm7bUy5IWmQfw5C4Visqeva8GJVZ9pWs41K2rY2AX7LxdN8NPaR+ TIYm/hk9qcMza9F85bZG53snKW3HJL7IcqaVVgexXvKh3Sq3d8GByixBfSL7aIDESlu8et9TKr0I 1n9AFo4DZsQLWIvwyNVVnFQS0gROYLwI7GZTceP34dukxl0RxGCPjONp9FBRvAjPqqkgz7VDUVdX uaXM711VA2H1ylG2PN4sDdQvE1vJb1ghvhdVOGd9LxahGor18+14XWfAyeh1FKkqBecbdn5hpMhz lMZ42NE13JzOPHwJeudYsuSvOICWB9xjJPlcTkB5C4ujndeGnsmost0H6VD6Wjg2KU83i6kQXEHl lJas6WF3hRVDVFnZKwUoaJ7e7aNQ0nYdVh/6Z8mIjXUD0Y8ar9VHayfTmIb9YGA5WdLWJRhRe4GU 4CYeJzjv6JfvqsTgAICY1h/N69C3xXBFX3/mBzlBl7co5zB8TTY9u8OQgEtIof/UvaRXFJXx/TfP 7uRHErGPLGfDYzUCzS95YoOujORyBL2v2xMAALt5RRTKvy/yDJ/tGhwP6E9hPpxaDldIl/AMnw1L caeMp0vNIgNDuZdIDqdzBujJw6XiaHC8xc1EBWwmO00qLsugM3Y6EZZUTMPdenB1ISeS7Ce8+oYg P4QVkiZUEtMmKEPqYvlFzwQh8OMMctGPr+qpM3ipmgDeiLAtuCWQz1Ti3mQMVypEWWcnVG4u/ZEn z9P40eT1mylU3u7Im5jceSso8uvbUdv5TC6pe6sWsCAWimerhvKKaoTxhJN5QrD8Rf4tbLPIna53 LRqeTd8351CtkHHMgmUkV7lmKgShtgDHHZeMyxQpKf1z91OOd0VF54rtUQqUDD4HfPpQe+oiva4u Of+GBJiiXL14aO1qERb+y1J5TZHGuTBV7q6QL7hjDMdfv5baWeBUGEcI6GZnXPLZcXUr55SmWSS4 PoUxxP9AAn8O0cmGOe58iONeKHv5cVNh9SXGpuTcUZf6GNcl4fGdMg10c5SIgNZl9ZV5I0Mp7GHV viiE+FGS+jQVgsnDbEL6qRyfVgMrFwVH3xa5/Yfzo0SRfFcw/4pSO+97EtogwPzeK923LJ1BPPhZ rPLftm8pFXD4ibW8iUI7VAzOAy0QTjkrK7KA0XcaUo6WGp9At/4Xm3XQ07tF3U1FKf5iNIuM3wc0 zjlAuqlaKkT9awEJsM7DZreZFWDjVctmFSWlIO3RAzAEt+KtGk/EXOyy/7FlH0Vy1He0UtiuQ0Fd U/wQEVyJimcLJemexlD3eokvGiLwXjzrwQ6HmNKBgaDpRojs/32ZMn+yqyBmcBglyerqiJuEoMh6 CuaX5sWOopHriiYZpeM4ckpisYmwcS5+u5If1OXXLfYdOJ4dxrOdlt5h2+nrny+KoRZedB9ViKBL TysKMHl1DERORuAfe2AXyeB08DrfnXSFUwO0xUXeGhBJm4m9brd8JdoNgRFY71O3SZ44WFoVl9XR svOoFtSBqHimcWdopybuDHE+08LVV6qtWG76IzmjNrCQbYV6xGzMn/iL1S/rPFTltHADz2doaCkO b4QPuttNZhGYxuLI4CqUC7p4NRXkIht8fxcJAkf2l6SG5jnT4VDeAb0OEaUmrrv3HE6M0qFdW2QH HNgNWQkO72mObUfDYou3O9QIhedP/4V+gzhxs6v7PYgJGI6HDEBaT4xp+Mczls8e+zx37HZx8nIR 0CVtPCRVPJm773hJ8TK4252dneew4xNgiVWqOt282QvxVrAxB7VYdNMK5Q8BmMIwX9vt4XM7dq9f BNAb9M4rZozVttUK6J+pDSQlmX/OaU/HaoQLcYDryFq1QgBN2R/xJox7X5DkO+IGDxgKkxiUBI52 PrHBFLDAdtM3hbs7+CDczXmx2DHtKxVCGG2qb6h0XR52CESwkvjScP4LmMea/W/F90yDM6I7tDFR FR2SN9OrEPAbMUPLuVkjoUJKj17vbLwYS3/u1FyziQTMiACkZvQpWyMORpRtSmuv23Hj6wF/sRKk XA+bJGFIs1xO8HUaWfRUkWR2qhzyHyGnITTsfTaSHsoJHeL8GDqoHrxyIpKHbat/idRYfG6ahYBP uuEZ1Eb1B/0WhlQrFam8jZkhshg61hyiHdcONpIHrAMXOYvZQ8Yd67Wr0fBAZYQi6ICpmX+vB4cd nGwmOJJ8LscIUlFCPcsmmgfD3VvvEL5bpj5zqxtF3QegUzTXUf6iWIC97mvQadVO7zHYclEosd7p 0ESrfT8yW8POSvPtWRgQ1wxTPwdpk+4Kjr13kppWwyvk0dgawAVLFBkGBMxCZ4TBabR+1Trrffdx cv39qio39/NexKsOnmENzDUwDZSyDFX1eupwnEUdGDKFozQooLyNyCNeEkMVdwz3MxQL8dXlVxzP TcBIzkYX9f9r/rDuZp7Sn2l/dZRCfkb4zDMQL+Bt9zpWK9TYPeAMRuTc6FVbkK5Sv+Ry5u0H6cnG 9KvSymICqvmtWGZK5+ghF0+xaKVKqkt0D9gnZ5G9/vEjXdg1MaF/wIomJjBfnLUg3h/3AjxnYMxq gXNkePdDkxenPAoeBW9xdLUqhJgdRsTNyJiYykg7RnOo26naQ9XyLsPZ+XDuGBnxSi8OB2+baqwL oHwWxCdtFQjdxNGapq541Y5N/osAiz41Yj1enxY/HzRPcgQTVSU3pFFXLh1Pk8bzVeMr4PLN1DYO JxDCIoFinhh6pLtil+AgvqU6ewMkkelRu7eXEX+j3MfJFhEeenb/v8Vs6rTv17FXhSeRTB65xoIv w7coEumoxrHvv6Fr/8rTJLMr4NM2UC/rPiEjjoDAaTIkVszglCChoqQcDxaszCmD1ICnsjnC0662 +jmJX54iBcoYOnQXfjvgtOxa8jV+YnnCT/0qKGkw2d0oPLY63JSYKyFDiLhHxMTiEBx23fTXkk0B qGa1GMJJhshnAMxWgC+CCqCIfZ3k9nTxiHOS3DSablSDx9kaUWnxSxa8H5ic044JA6InFQ6rOSUD m7uxBJxs47U/c9h4mnhKs7K2y8YVPy7Xt4o3FxRcj15e21Z5ZDH7KmvxQjpmg/kNelAQf6VVNmbt meg8hah/ZxrnPPdoMMc2oXeRvU4BlJnMDx1Q84KdCv8hetoZL+J/wLrU6d+0PnW2j88pQaKuaqrm AiKCAu0U2NK2qIGIex7Z4puzkruoqv25kBksiz8hS8YiFnrq96WxGLj+LO/aOE6ozgwlYNbCXLlg dxVXcNIwaEG49YvfHTu+MHUlcXKj4c7K6vz8TnC/03La7EfcZFlnGUzFAubnV7DW0NVutm3bf5H7 asRaGz8fM5f4nEkFvzyIuCo9FgCmtICoIcUqGggZ+slfJMap9gP2vNbn47CWPKRb4fvQU+NFIDaG 7qS2ATZ7h9BepRD9OsAmC7JOxPlvMFZVl4kmTAlVgQHinFJGby6cx50qlWfzZeiEgNDHz1JaWJyi jOuX+LRjO/FdjpUnnTOhQmDnf3lfHZ40dWgc1fnC4xG+9i1n4+9Axxgs8JrbVRGssHVA1eJQCl21 qx8USmhdsmtdNUL+tQKs+/YSDBxn1rMzN4KTiraW5ZPIc9SIun7Aa+XQGx0Pkgk6RRCPgTJGvZ+d tfKkTDJwirValli26rMaL5aLXLkgbzcz//FP1mjWE2TW53d0NJMGCKZWw6BdVCYfW3DHOhZjCdh9 hOlLBDvh459MkHMYw8nuAjZpB7re3i73/QXYFA1SoJ2JlhF7oTfv1+XHTt/iziFmjgeq9Mxs7EQZ j4Ue0oWPXd6cguoTjAdcC2pqWhMVixnOdoz0KTyeaIOeX1LxmjpOhW6bP5DI6VKcTQPZJ11JF4f1 tAGMMrW2zDKI/iqbH5CNeAzS5OGVpLIaJvgtlj0Sty0b9yUGd+Le1taSixxWU4zTLtjbzvSYaY6t qGGOre1GttadWk3iE4hlzLBw29GJLQZ2ru68Bf4FnT0faAMzmipTKBe1R1SCW/hwmtWMRAG4Dr/f ScOABTku9VhUC0ij3AIxhz62DjKVrsDXQPI3+7M1hFSPHOfIq9niz8BEgAE7TJE/i033LgDjt+mT QBkIMtfuEOkTXXDu+77rYakxC1qx/DtsnqKwOHAAcXV5LzWJ19NNVSNT15ovRJcotaXU9Ddaa/Tz YU7ylF6Q3diAvywrIgon6NMVccz7IOCd26R0AtdczifyiqJwBxG8MS5CrKkkMes7JpWt7UK7oIeC eLF9rZAQFK8T7Mim+ry7T6EIvWOQaCsICI7UaoPbLOuogzzQMVEztn0duhVRHIcEnWnHe/OWDrFS 5BVfBorWISmTd/6VR2CWAQuGeSMQ7Iav5uwtUwLb4830jtqtenZO2f6HrB9k6IESwo9+6FF3Tqh0 TvbkBa+9JLofHICPJlGywit9cjwlUm0/DDgll71Nfkx+t8lAVAl8F90GIkktQYmBA4CRIZH7XyQT vQ9p12q4YQj+/2u03X5KsVP1dShJSBbt/OcS306e0uxOvreaieGGjvP8ctc6QDK3Pa22JxHfttQa r1jroQraOtNENsxDDQZXdIsZYGNiliTEl49lmA5oroNbW3+GA7YPf0WbmKQbg+xWe2D7dO/9d2te PzUSgDhL71WYh9O1X2Zm3XgpTHQ7sFzHA9jfnCXc1ydd1YKtGFJlal9hbGLZr0yazrf2KDhIqjz0 FaD+6eGMmAlsM3q6636jkS6DqyFEcFXD+f9JyRiThqRnBISRsDC0VMTmVPBEjOkUybPtZGvd2y9G dIeUg2ovaAcCieFBM42HQgREZxTsIFMhdilNV0vRwMRxYJty3cKuUzcuJTGgIQXnbrFcu4Ny+VYU JVe8rfpaZL0ILkChA29wZEZkjS94269i9Sh41YG7ZHU+KRbG2FEyEpaa0P3zZx+ZxpHrGSRowH+h QzQd70B2YqKP3fM7Inroz3aJ4ohrJZWf9Kwi9y6ll1qxpH4KIbi/wbwdVKcz4rTm7+SDzKoCjv9s glKvC7hTbt9Wl0LG2VYbqV38tanvGSByLxnl24nykTg4VRVemKaXdeUsG5PyK7YR724rbXjZaRgc 3uddMvAFqHddnmUYfbeeACvyAZ4p29sPgStyTMD7MGWe2UTqDBRvnhMsI/tGGMDQxHLx2J6WT/Q4 yfpuSxbrTFF1UgUGGds071GCQXBV5kLrnjM+0prZFCpUJejuH2+Ac5rh1Md9jTr9TSYI33vXn7lC kcrgIoOX26zo190a+0oaJK0ImO+DcSpmlsn2uqEpUh8xGYWQWVeSP+WGiCPC2ZcxqyMBucZ5kTFm 2h/A4DOz+T3UC++NJQUWUXhlkK+Xc9n55U7eQMr/54bAo92xmMjIlRBxOceC8aDdz1D4YGLwxzuJ hHtFFI/yY8BwlqhCWIb0An2E51Q9cm1W0JfhlaGnrmIuyoMIK0vjcZG3hWWwOiWGL4jJfetgX+tx uf4Yup2VH6bkpOuW9jAOebjGn2mm9mDxmMkXinnKkVfNCOlxCMc7xyrJ4a63p90RrdAR+WgHpdvu jfAe5+elkbTuL7XtJQiJF1JjBlqq3ZKgD6JAY1XS59Pkaumz6RpPl7Rn+ansfz9JCJBE+e4Tfa9v PIqEnRnYgbwB7MuKqW1rHq6hLk1ebhFXQIYc/dOca11UMtiy7nc0tAwF7DTxVF57ZuqWvBOoSOBl QxEZhmSdoRyzsdXIle3VblvZYaVRNz1xvMVNhqxIZmMTN0x52Qc1eZVkcMVlyXDXIBwi97vZdnjf PxZQvt6U5sUGbtquSIbvm6qTtmhNtiVJf785RRQUtrmA0kOz+Sp2/1yksd+SI+ZMgQgTwUtiLf4P NwZdT6KPBofQoA94WSshgWk/OSJhGXC5v36ZpnTaVJsCndu1u/apLjyJaTRqOyO0PsMFrxt4/hmh REPz4mB3xZlcwf23enemQzvUYGQYHqp1p1SD9LasBqU6aBoRuei8mAuWpmeY/phNPTg+w+HKnWTf 2YsTpJ2jSBs0Desf04Dv9X5VhjZiqubcRRGHrngEQgk2lJzTY9+9dCv6VrW+MwS5CfSHZ+FxnKsk 4skSVz9uzH8AkgtVZbpYF54St0mM3EnL3m6w6VL0p/V0NWDUgCXc0UB/Q8OvLM1ulsmDFAlaFB5k bQCpe6fcT8WBXNrXqwb51Nmx4cFiYvw97O10dwMgg/8kGOBcQI6PzJBM77npaOy8fHNppnrnhdRU RrAm4ywoIOXLwX6rAqELvuq3TmlxdUdUD0FOL/v7/t8ukAETPxPeufpXKG/Xblh8m6GKhPq12Nix mh19qzJ9CWIkvDDmdeDZpPxiBVJwqVeBRi6fwac7HsBfahtOqeozYNBlbQhVHVNTwC8hZx275/jN EcelVFZDQ99muBHkPGSLrojq9YuYjqKfSPGJSdvXMeujQfG95OeEnyfTBkfE8+iVRU7MEQv6XBXW zO6iPxmGPURneoyEd74bOSi4AqDkob8n9MdjJC7qb/qfyw5qT9Bk2h5cYVGHvyfxuFAw9dejYhqa vTf0Q05b90Od8KC9Vax3F1g8xw2vZIby8MXp6C24agehdSn7poR7ZGmaLGLxbwtxs62XsSAsM1/Q HaDwNrSYNKkjYnXuif7Npo6swcs8nMFcpKsSvRYksOA65Wqiw/I+cXjPADDXCdHB25vhW1NJuDU/ F422a+5d/6kw+cieHtJzjKlW9HZm34NCEx7KxoOXaGi1hVlMGgwss+o/BQETkc9BJ4XNxaCThbUg +BdvMh/aaMWF07cBMrHJLEj1nOeI33TjKmmSt0zSvUk7k1u+1zj0OoZNl9vDBK5gukb3P13kDXVQ DS8dd1VSoZLY8WPIxzTR/TEPoQjTQcmr3K3fg3GEWYNTPjMyv11osqECfNwAqdg+XlMQvjwesdFW WBwyJFt1c5fWEH4LIWQQKpXdo+ci1x/QsIixFScVICsphhLqmia0mR/zDIv1VtKJNRIBJV+M0vIM c/VghBZkMwntgGyq3lg9EysaOv2/UYoW77OiznDHNB4iODF0PolRbnDaUdx3i3UP3MAe4Bj/kvxs d6mbClcidRPcnJbUsPjzP30JqwEmOJVAzTHgo8bHADM2n+ZvV5SYyZvTnkmRrSN7jbY1pf0VEFwf 7/rUb1XC7W/dwZCQifVvVjmgNZX6l5mNHvQZFgSQ5W/mPYQQdcK57TWh+RblrlaW7Vjv9FXty9M6 +tbkT1E6jyyEFY2vra2dLVRkShEq70f14MKsinFCh+HDaL/cz1jWyYidt69ZuUpAjHPgR2V3uOJg 5WaaVqssETdfLok60Fro/KU3FFIaUBGA+BzwU5mjXX/MSkvmNakbzG4u+zpieKI3/aagug8sr+GV kvBSSmYuH4Gh3PeAo8rZxvABo+JmsjRwWHS1Hr5J+j3fO7UJFLcbWvok0H5gX4aFf+MOJfsrtomE 75V3Pt908j1XkUe5kznFkMHL/fhxKVkJAbDaDOkEpthdoofvUNnmxZO+Tk0v49nfZO5SJRXff2yz 3rEOM9/13GQUC+qjqkkO6RxzMsN5KEv/jaxuyNU3pdKoDxhidWNYRRxRKrsc0/XPyOzbgkUheN6F YJChK23Cuxbf8TVCX0YAJhcz6Hv9EkzJDh2fAXjZOT+CwCfKn7HtwOKsjCPv+CnP5tjwjmExCM9k JmG9y7TJL2p7xG+9C0XB6XX9Xhz+JRL2QSlNMc7PmuoXiZFXHbht41uI9024wUkcbwLg9KWWzyZX 9n8z1cU+i6bkd4mEIzPriYJLA0d/hwxFkpZYI05ClbeN5v8GMYhiKwb221mvAkenNgxsvpInzZtl 3FaSTEaiQoJ0YcHxL3cClUm71pE0AKOQQhkWB2glb+8nAfxcb7MYYC4n5tMbviRqjhCXXGLcDGeK ralBjbLrQNHu/VQYRDISVdwBmVAcCgbZlk1HA1Ljau280IlHs0T51R9Na+lAZt18l3ewhU2lHC2Y MkVGUkEo82rRD1igb82OiUzFNPEXnFHlLlZRDUfmswmu7ixrSDGu1Zuj9iWTTsTPqK4blQlBo/+s v+RCc1Fi6cIJKXbZdzPtKpVAYPGm7aJKpaYV7TQ4cKtXAkoonwck0kzfS7i3W53OTBjCrWgdCpSq jKMW4jDq1gdu7vwACpnSWOHuG0fe1LyyT7V6l/bdg17yWTsNxZ3IOLehuviLvB3DAYUSacoJamaS LFKlKD7ObNwXIPbLVcWvplpy76dMith/4aO4dokS6/hEjfUjEgHeXLNAgzvhjmIiKn1dC4v3H95W bWq4on1R+jjRtjaSsC4AiFlaWj9jmfMOlrYFmw71uaqXe18ZS/K1Z9p6VCiA0lyViVp8OxjTqsIq HsO8vmDxXJ20/ROXgXG3K18gMvbBhooPtnS13ijhKguNKrw8yryuhroyiZVJZIu7CuO7oyO75UmW DICJin1EZi7wxrZM88+eFyL4wyKi9st2HYJap60WzPM0MvhlaTUT9+6cThLLu1OQgM3TzO7CwXJ2 NzoHYLEdXbB0/oMmArPcOP78QQk1TCafcpUbmzEXcIWM7EoucqfMX8OB9C3piexkI8odlqkXNLPm r96IXLvc2k0TqE7DGZxMAbtgGYtbHtJsI1wrGn0lFpFe0sqcaCwMV3nfzoTBgQjqlr1apY1X2xFz Xfyxh/mBdAK68eLFgG5WC+mgUvBo0KlodQT/9wpVsN/MDyDZMHbT9YtpT4i2CgnIqGSVJNH1VKer c2feMAlV6K6owW04Qoml7XaaywjC9D5fYt6Z1fledV6B036hwLiOyxDqPW8vh4qPtBd3mic9bWlW 7wgrrVTSF2aHtILvojTtcxFIrQdRZQp2seCRWbG2BkrTv3/1bKZYnGQeaPoJ8cwmNqnnaVolla6b lUsQOEWia9hB2dZeuE8cuwBqhHcgVoVvvr6bYfCUvY8Q3No6t8prA5eH0SBMStRt5cEdzz/pOLdI 5R6hEOMw6JtbUfYBLPyrTmxSPjZTJPWdRQDzvIi3z0+Pyv5oIFxbSjvT9Vgz5+YJuJFTh0rVfg+l 5DDQsr0aEqpBoajvIUfxU734qOF+R2c3uBoWMNtJUdYn57ygEU3MeH/2MTutznAyClgNDWTWjybg 0tTvEeyV2mNZaQC+nGCAcMqPX4fmU9yuasTmHcuo/tLiXZxDE2heILAzPogw2fCaA8Mbcj7q7qQW Ut8KSZSNTPiLK6lxSnInN/WYWGikumoBf/w1bkSRgmjhvtLYnKwYnuBrtZLbQ3q3gMrK9Om3J3x5 FoORawc0pin4AzVIQQdWn0Wd0E87+lpqBzjh0tBv69gzK+jfpHDlXnlZFqrDh0zfFqm8nojOe9yY qiscPhyp8ezAlgS8tQFR7pTF/ysS5udL3GVEEWHCfc2ylNpo/vJodv04tWLe0iW7rRCDcbSUbx09 NMukphcqf38Th+uE8TjBENAj+DbwgXf1/M9lp4dh7+BnSB51fsvRIeoXaEtAAOYMaljNjUE+o8Qi 6GZHX8IeT0o30xHl8ST/hJ5c5z9g8Hm5n5GAlhXn7WXyNrtu4qREdeADPOIAQi9/aN5Fiol75Eam fYc7aVJwu0SeJdWr0bU4xhTmNKbDmakaUP9SIaeR0ehoitOTkizOLpeHdgoRg/64c9SLaQPsCe3I ajfoHR8NUe6wmEVSHVco2STg4EPYgqlGx8kXUquWilIgKhdY3MUgn7NNPOKR4IpnIVyy1cv61tqj x4Pp4Bz0SaBcEsOhuPJNJc2cVR2kQoHtrdhZbcEalbzknYH6DE8VOom2xW+2AY5Ub3vyQCbzbvJk plWdfFaFqQUjcaLHXEulCNE6D2FMhyV/8PmPPuXh7i+vDiDv6pUngNfrWXgP9SkTKhnK4KSyZt+e EBU1QO+nGhCUJcbzi60wYvswafRk5BTw1k/6fDffzT+o5Dbt2Fm0yxJshVrqMvwBBrebEpWeL3gf R1BqbOihhyZvklkwzLChYb6yL1CaB+4LAekiJhhZDRLNP6Ek6PZHoNOW0/sjC/A7pPreTPT97yw5 Ut9Y7FWKji3w4nLPRn+Byy+TuVpjwGZ+/PPWouMentg8vOtNtY8FgvaqzBYc6QclXCpzwlNKGnux V7tMV5qOrk4K2fdXApTFebb1GZhdGUMGwdSGMq9GyMRIvcNgNo8gzV4w91KRInuPS4Mvl+THKVZ3 SSotRtj+iKGjEodWYJlfA8Sxdgggncagc9jP1Kl6Tx03LBPwdOthrhgsv6ufLS2A4VjYzJ/kzJ/H 3Z6f7I54dGK9cziOyjLGya7EJYcOPzBzfQvEoBtRcoOU3gmIX7APf2IUaFWfC7+IPHxkKBDmwnKN QCt5LTIgj7DYUTg2c4hAh9qTQwh3XhlzYrhTaxY3zmJzJm27YtaTPwTw9ldCjutK5NaICodvM+0w pbIzS6ZzGkmQHHfq4sejqsx4uOgRfIhq8pnNm+hcGoQIJzQ8HQTnEOwNSF0SrKt9Fm8yDgvm9Qs3 dONOhdkJFKVcRgtKIf88Xc6eqXpRsgKgY3zZytgoiViuD7JK/cRh2wpSWVT76BCLWC2Qcj4XOag3 1Q+unlrh1HKJ6uhSUZrsuV6UO3s9qH2qr2T9fPPkFhsN/ey0ybR0QaOaBR4+7j/2YNM65CCnlo5t ZTKfkn+plwTZ1Ks8N2AGOQ+fp7aT0pXOaz8CsZycI7/trB8kbDD1adHIxskNDECBRYjJDKVaecD+ lZj4NmnpqTMimMS/ZcNtOsYNcx2nEu+EJDR3vFc3quPtdVzBmckq6yYC0O20ECe3YLGaKhLIXvMC X8BLzfskMNaJXNrM9FSV472T1deF8YyB57ZHHwDoTqKFzZPoVNluAk+DZtFGb5lpp1j9J3/8F/nt 6tlkF34T8zLeCIzi2aYAo4Gc7/RIPJxo0FWdPDmwiw73YWTbZjQxQaGs+WbgGT7ntAjf6w2at1/0 ZMsaL9gPS4ToF0st7+MnALnohj3drJ5eKw9GYq7RNt/f2ajsEWacBef/ms3UMzU9cQ9LOidiOTqe gJ6AsKAQLF4rubIuTVfNSepahE80jU2121xtAuw9WTUex+I3gQ1xYDNBNiIlVaFrrRnVO3Ie1viw SnJsnntvFxr1PqXLeSXLmDnfdpxD2kF4MOLTK7l4HSa0TQaJucPGBY1Yd63Tie7FYOzFIPkRdG1X O+olnYxE74o8+yRy+1GmmWGO5f54JREM1MuJUzUU4HLN926nSekVE62AbCS1TLu9El65PiPanD2O p7UDDjnd93dh0Olynh3OWdUP3jfc00NIZK6NQq/gwJCbmhmFSU/H2AEpXjlWBnNhFmS/TEFS7N/g 8A2LzSW9NclZ5UH+3IbjiukUBhdkm1yrVUz6sl6vW2MBs/IKMXLFyWx6ko/oyBipHDHNgqFkw59A sG5zX0qzzaCmFJssU2WyCdgVhmHo+7lDnNUO4EyuiV5iJL5fjcpRdmuNsYKJ2Zles7wk9CoDsonC tHcOeHe8JxgoS3H0jVjB5tIkvtv2SuNhNiD+wbdYX75C8iTFqLqZwks0DYp4ZDeQkLiNWy5am7G2 jG4bvtJxFuiq4l0xnugPkEp51PlkIAwKcT3Fb8jOLG3x1N4e8laXimPKGwvAhyH32BGSADBwl4eH zSuSMkcm0vx8MZxYgx1AAA74iaHcDdh7sqUpy6wbo/zI6+I/0n3a97U0XB8LuPXlbPSZyoPlzCJE 40/rS89rSHtRKIta/QyiIHEE4tqOa1v9sm5Y7CnFEvkOxcYWbstILv9nRjV9zujaMsUBJASlKI8M bNkSMQwL2MjEOjtr/H3g378+wTkhwCTBsOJFjbLJ+qByEuVhpaNKpSjPpmnH+94xJHFyqPRs1kWs 4MxBKvTv8kQ3Eir82t2r5dyX0zknU6ZL305y0oZ2yVfhK3yN2xsKjPS+itoPgCFNkqkhLbfG4PE3 TC+5unStJdO0/yiL56FcnuerhOTr5zYS6F2hB1SLUNlMQsl1VMR+UlqTXQr02bobT6PlbKtlOMg/ R9DOROOQpkjjkVMPNdUFJU7s5xhoe39uJ+W885D1/6N91sgg9P4NH5UKJb5UKYGNT5ACYJ+WeN4m hUWxU3c3OCsZp2CqiWrLMKtgPmCEzCHzUHACnEmc/mA17yGzUAtHXS/0lZmc5lonuDuQHTsnZXhm MD8243MFed664GMIhCQ/clcsBwnaXCapV8IhoKfPNhIorialVLv+boBc5WVcs/WGk1iCajozJORx 7lA+dG4AltS9k2Ge9WD2iGGixCXOPC8VDMSa0o8r0is8qGCKoZtD+Oujp+ZC4XGkS7hhjTqsIlAv ++LH0nWmsMkNSzxzbxMAmNX3B4SfQnlrugHtdb2vj5CLNwhkCqx4mP0HD5Iut4mAKvPRxP8nwOKM UzLu5MRGpEwZMGFeGrsJrzv8n23Ja+gAuqF9g14BPNxSJKJIsKdwkBJoVAcio/pvYeeVzgV/4kon 10tCymIlvNLfX+LzBaqe4yoINSL7N/mvRUnkPFhvLyEk30BZfNvWyuzF/7dU1RrGXRERMg1m3BDK 23XKt7pL/fyrKY97g2OPmnzVSLtaLomgLHAGKRlp+ZlggW5NniK7DtyZDcHNvZxHeSqlvpo5qgZM EgcqTZKphDPI5NhtFCqD8GjJKd+WPgkPQJtaHe5HhbgrbH8vEzju4Vbt3fzCv2S9e3eNPHXYaEg4 15LeGAkCtEVosWO/1dozVGOORUc0U1WkMy+B1Vr28ivrprjLJ7dkUmIKH9eVSLHOiyyoE0vvTwM/ D+WHswrw1tMnL5YJ90qsyLzMmpRzc0upQDDgAAV0JIdOiH86ANnxIKvsqJCfY3lL4P/fsaxu5fge sR5uDYpR3FT+3N+8zv021EdUIsbz3oiHdGE/hTkg72jHqi5xNLVv59IK71a9VDSxqH8NsO699C6R iPC4aSXayg10r5K627IwAHs0LVglCF1Iw4mH2WqTKlfnnAh2r65AQe5IHOAuLG8mQCDEUbwArEoI HeeNTtB20aVmsPVdZBPD4uGFj2N2qkchCkcgGeZMPXyaHyrOpkexBeU0OfbQ2Ww5w9cHmkLPw1hl cJFbh9mk9gClfpZOrD04iXNViVkXzoa+vqAmpTJ4nz0HxdSjW+6px5B3MMUG7hQs7+pIBGyTVofZ /PVfJuSNdbuZdPZR3IU02eeastc764i+lT482wQ/WADKpjax0F3yn+i7BIYG80p4nvbqEcJ22NHX tGA4rC/TPv8gWFULr++TGX3eNNjovlGAYD3qtn5SEwKQjfzMAiB6mwHaCO8OG0WwfiZOitP9kBY/ 7sS9VKi1oDefj2r4+TZDsrMS8/+R8hKU7L/Bh/ZmtwPik7nPDe5c1pftGVaj/PVY3/vC/uX+QaJf XRx0R+TQ3zeChjDIm0vwuIy6BUPl08JaOCOSoD0DC3f65KRQgIK21iiSKVqt8ERiPQWL651s48oC Qxz6RphQFU7aaGLZ54LZxcWpEhCutR5mTpaeN7anbdI0k4URgw0esgrhzfdmxcGNPODKT+/Nq9ux QHQE0E6+nNoAHi27JUZednXllXRoXRXORFUS9v7BAw0OBP/wgsuwRrdmYAhGYMhx/Wckiudiamae vADcBib0JxaNUGnxqYIX0cpRTyJxuNoCOEek79VNBttYwxkvBFL1+rD3sMHTWjbcR6zkZfgFiOHj KoWikxX+99t5mwHZ3NVB592rOgllSdU0NzrgKhpYgvjBmY7wJaKUBATd7qpL2cgrqMwt+cOqetU5 n8/dxiABLZxPxEeZdjinU4cHKBswkkkhpHgslYC7UpGtThyU60rf2mdvx50nWKfL0RO9qoKJeH8L WhKnhUyZ0H+ywXD64rGDt8yDdFMLzvnax9h/lJd61uQYLMdOCMAvmUY6A2bLChe+DOsnU526VfDj QXDzsY9HFT4ssiuvVy/9KfOrwqYAFnUOSrQS2xppt6dhsIoVAxjOl4YsjnPaxMVEVyMHZyaG5kPf TyCWmZAg5dX41gxeQ8T8XJvPVHgGm44Q49+ZAuvS8uFlyFpXNUgKNRRIUyxC5jaM7t6+nz9J3jPW Ji+CVHc+hMnZHGe0JNIxuHF6RRr07YAJ4gmGrdtKJoRwxWkE4xEnQqotiAwC8+aEFJZHTJk+oWCP sMohJd3cl93x6hmcjtv2b0wcCyKYYnnE1HjPbP8gXFxPn6zeFL4rpsSAjCdvmPgzBDxFo1pB0HBR EnHOBQAwXTdhXrRuy/s9xyfAnFTK2oV5330UzqiMYinSRGYs5o+gIk+B8ZASk52Aq2IehCaD/b2e uKX0/AHiyCwZyYng/b4NIPE62yWcQruNl2oQUKglwveZH3k/tCQZW9ekoXF0sLHPVLsisidkbB6M pFVmkc/x0RZlwf6enpxuJtVZy6Ud9oji/GkBg1JutRsfFG131cT1L6bk9aaFBihw9RJOoGQcyM4y CPWSrnbF7zwTEXjoax0fgspMr4JvunDuu+CRm5cU48t1lyLl+v+uEWOU++NdPjxxML6YMriGpefm NKt01j1ekgJcLxdCtH3Gyc2m5B6Jq9X6Qn9saon8jXEVwQ17425oITHQ3rY/gpUC/MjwetmF090Y yBdwDuzB/CgZqfgajquEmLrafICyyxv4c2IPht2gzj8jB8k7FGQfKsbROKTZ+AhSVrLvMSZaXjSK whEkLTIphoUUtho9Sg+XzGe6ZeDe06aRBwTd/gDodntK8O63taufoD71nmZYPIGfmZ4MnAfjVwkP wvgkAJVyhOHZD+iZpPHHoQXi58viQ8YMrLq9DUVUPpnqGO+eD5iZFIYAuFC3b8IySlD6jlLeTSuX Un3dObXeIOsNAohnX4SzvTzuID5U2a8U0WQgZsF7I1eQFW8jQ2GHtgdiqeOZvo4KTR6K7/cJq1Sx aKpdqlAQNWAjzfFy18O2TPL94puULAszOVHU88IBkqN97nk+pdGddgp7aWDomchT3zFxVJWtSoGz UcOYVEXKluLUek2RH2KS0hFpHxCs0Pypcq2OXus74VEZpE23qNTpfoMfK2yhK+6hluniXgkYfls8 edE4X3lOrnDJf+ewrRMebvLGYcxwSfep8il6NzeO93DHH0Orr0mOwiVLs1ajXZvjmEBlLmIhlrLE orAYN03QC2nAa5uyXV4In0kTXxrz6y2ymU/okkMMOLLp/p5rXcVPWJaSjMdW3reZujP3/7u7mqZS iw9jAx6heCFgI50fNKDZT5FA1cb+pWCCRMpuxJ7KL3H3t+33ph+NBiLJMM/xAyF/YJgl90mFHmVS F2ySS7WKTxwKnCgQsd0BGfIWckd2tSqsIJrvRxY1HB0DtCiImC5I3YYRQoxMMXQFC2sFfIelOY8d DMM6P7Obs76wTZ3MycG005D1sAo2huDeoHywdIWd8uMek/TPUcCbSw+ZBQhvjhNZC2KWk/U8fREb fqfh83kBtbKfC7X2+pUmzjU77QjYyM4TXE76I7DIm7qWQ+cUpK9OyyZ77GJbA1a7cQrU/YJBNRMe aAP9Osgel1k3TJ6tJTzoR9UF2ylMH2NraeBsC2xda0jx1H1erNUGQyp76bnuTMiSfG7RFHs6667C XNqVyxG4TxlAoihMko0o3R/qpuS6w47gijGN8m4HabHnlwDK6ysSM2fwZmRD5NbpZIy7qsMN2gqE L6HkdLI+/JpQqLsxumsshhqL5rEaZ9SqI2Pxb9EYYWn/Mvhs/+EvdDL0CEQEsJMcK2NYyaHq3YuK Vnebrq2SJpSjVhfnsVyc9Izy9kMNKKyoNJNV4sQ7+vRRvcwPN+G17GYhbr/ISeqsvCadbITNDcIv aDL8vZoDI6woO3bQ4l9bPw76mjLrHJbjBjnX3OL5zCLcVEtFVH1c+MVZnqrVzLMVzG2c6XIIDMJ0 h2uwUOJvyBfVf4+IPsCaBp6zPz8gf7Fdle1/l52Qr56EdPdmEXe3Gg05HMSGSAkpnjjw+Z2+Dent e5qFVdMdLE8uSRc8JxZqUjbRBXpUxRBbskvIRe661HqqPufk1OZ4kb76pQwYUXJASgsCEe3aOVlm 9N9ICaL5jUOJedzSEoJmGTOcOZBckB+C22jt9W57bLbGO1RffVQJdMbhVgxCBklKmzAZ5Jdw1TbJ 80FxWhk3cPmaeMKxjSbOMH59FTbGgJw3Q4foE//W4LjV4kLmrUj6eQu9dcFde/aBgJFEMuuLvidi +2sdG6x+NT7rBHggz9Vw5S0xEF8aQL39PoupTaypkCJGkouDxAGnaHgUzohTqa6c5rnM4BwHCZ1O +75hgxyjOhwK26+D6XJHV5SMGBBkhSFLD02vumnzekjXL+0961TcEQRuUftjbbPwRufzGwfGFINe aOX2jjqXEep1pENciMWfiwijNn0SOdURwB3w+717xdzm/lI7hvnJfMZW3/U/RKR6mtoXDV+ijoyx qoH0NPCmhgW/EyWSKmSgvIQXG0sQ5VLypZLrRIBLU4c6aX75H86z64ovVTocoxnxhkw9EZNdkkw0 9RSXKg8KIwwC8HQBo3Jlv83LCxGSsRuw6MmHCTfJSpnTWCLJfRlLCi6GH6lt4/a1/TBfDLlLW7UN AhVzcMRCalDOScyHF+rQR13wrkJe0bjwGL8NLWx0Yit0ES/sN0fco7YJu6KjHFM0ViKvQUAuGeKx +EfgTGMkZJnzRV4B0WSDO2lmSfYkdl17EI/OxtXUyTpsu9TBR4XDyoCZJUaleWNaylpoMtIikfyp VCq+jANnG0Rzec6Mpk8c8Un1lSXBQPwJnZSEGPxnRG0dW/l3z24YxeYUIhzL0MvIVl+KltdQiB9V kbjZt1xoA7k0jy6GbN4+Izt79u3AcfGhnhJiaaNaiaQC50FkPT3uKDf5iRFZBxKEAWuoEL3Sl6fT I9yKXyYiD0w/kdZeqT+8Nmtix293rSnprterokk8DvrBzv3hWv89kved68N0iwvGLIp8rUtmCfJm fdHX4KMiXtHCNfOCTyF01K+JyGN+STeLLgr/AJpj7TociRxSXFqEY4z4Du2agOeT0LUUtuMSwlCg CimQlk8BCzIB3IRtc+YO6OpfnMNlBX8zGYhDA2qkrp0UsAIMafLWffTrRc1soPX+AJglxrXMjJVd c4ihyRZmp/aTOV4o0WET0MtXM2jh9f3Kfwsw9jwFtlptX9popMj8YMwOqammy4k78GdzGZFDNiO4 acSIflOA9t3CxLXmoKhHuVZ3c0g7tG9UjtNmB3LtFgfj1GEK9C3FCBCWhIxwsQIsWDgy7wR04qoM SKb2GYNsMmokkXRQP9+7YZaHp+0XrFlKyfcKJ4q3uW4HV9xL7Abl4glTNKM6csQpLkv03VqFZVQD QckLCzY31fNh//Vb7KftZPunp+Mpg60LUla+e+LIV/xf+VR0Ff6Dhu7YD/WO541ApBUK1s14XnaH BCkAKOSyCx6IQFnRzn2FjJEStpvloVpqWWJuGOrelvSsctoh9tWkJq3KQv43Mmv+lz/nQ1dtiFia Ak4eS/iBeHstcgUJfS9v3fKTl2dkSml6Kx8o2bUhoSFTU7h9r5HUoUIUBURGBJdbe+V/5aHUaaoC Q5A9sJBcGZu0swsS4zyWFPC6NEEPsAGlEBtIwpgieIslBQ6uU1ywSGB5A8wgrht9vt0zUf9nqwkj C1eatsez3G3h2tSMfoyj8799E3MjvSAPxsA/hzWtKF3505zN7Fxr1cmDpYgf+pOSSACBrvjFFQkC KXA8tlKC2Wu0cS7cCNknMUqs45l4Zg35F7nKNPcCchKCLE2kzxvEuU3976wVlTIttPV4+EcRjSil glcN+yqCeHO1CD4QaDWMAOIbkWretVW2Ul/iq6XDEkSuUuEAIwrYpCkcqURgO/X2nYVwd69tPTsn yXmkq4aKhhs1PfXw7g/BO0wCCe/uHbt7sLSQuc8/eJ/hhOekQbPB0xofiU24v8QqfbhuqjC3K3F5 hd5/n/ky8zk94NWNDzODnKtSF7Khy/lkLvQFE2tSesou4lTaLxp3PgKpPb7X+INZuI++P4ygNNO1 z43PhcdJJaVFDByXCu6YZXzKPclePEBhP+uP6R+IDO/iB6kY6TAm2BSTAw06xWEtmfhAtUO7G4Au cJIBPD0AeJ+MzxAup+RxcydOt88nfkBOVARCugQt9dSYKuVIZMCO2RiY0PXv9Fk5HsrCAmY0ZoPb CjLb1yiprP5+4t7dTgP75rhPPMd0OL+/8XmaJbGWI8p533imkQaRnDlTBI/34Gb4kAeIzsE3MfMX taPXdyr+oAMBOzCuVE5+UX+PsnjfVuy00Aejr0Jn01Lv0+PfNNltC9itVB+dYVPCFnqLp8xKnugO JXGMDAkwCAC1MbgaSQ7wvL0/88JXRdgy0+mGS/LbJquaIFIhPqO8/64yFx9NcLwxwnX5vSGGce6I xRba6k+SwQh0CFWBYx6YuUouPrwSMOAhPzK5P9SB3WM7d4LWPXsV11BMFKTyFIiBPJKWB7HaMqh5 EKaR/TNsz3AMGLX0t3ipCt2txRxWnGGlaMKwIWWk5hunJnxNpjBCCrkCwnKzuGy4BcfewKTbvCOS eOe6Jvw43Ds+2haAGePMinAt3X2rWFkDYI6WOQ43ntRfIbSeMXXWVVX/cXXW/TQOV2IWHOMexZgN Oy9jf6Xus8JF+bOOgD1qnPhD1YOp0rdMtnpY7rvP47uBkLzYSUiXb9KYlvm9jEZHOUgMsLsyrDn/ pZXehSAWGPewAhqxQ8Sd9cEhfZCmvylLc4crbDQXa2P9FclcCsvpEjaAcCoh8Rh0HhHUBKKLaDhL WHFGFVvbxBCq2sUjJYOX7S6OG7OkmsUPt8fzfNFS7DEzhMkTTklW4RnR5EccFakKdgp4C1+UPtkp rysaIcOVaNg33rxfysNHC+OByJCdfDmCzoPMmRuoh/wvHU1MJJJ7/1bSK7z41cfbG7HcClas/pEF KRlU9aCyt5JkcYU6sor5Vu6I3d6zRQE3dmQHnuiSys5ysbnQomnrekdvpMgQZU0lc0dVtqRfdu3P zE1VCpLmhYyatdz0h0UxCHjF6FjZYbTNCRWtIM/o4wMreU46OaD6HjizI7YYYzasx9w8zctdR8Ee 2pvYozDzwRKpfONtKbYpPp3MJji8rIR3cRDcSsMLpsPTKvlQTi9Kw7dwMFT6ScC4QblbFMr/XIp9 tCmN/7HJhjg5nRdX0evXISxfb3UezgVB7UCtd10X4USmwDZyej2Zwu/XQNV3KvbobeV6f7dk12p4 bmcJQQPi6NxaCJo7vFsTZ1omM2Y/T842JIh+Maw7H3v8vg8fYV/LJUwPvIMtwD7Mo6eKC05qVE/J 8NGesoyF7kc+0QdTrGJNzpa3rrTEWQu0xcbb6gwzclUqtNFmtA1vPsOWGohjwARJg42TMPX0OLFN PlIqKxmLI7WBDXSiifQac2utwZKa89s3TU6ALf04o+5VBHwwhL4ibqvF/3SGBV+j2ZDcaVNt8n5e UMX4FedHfh2LmFw5ro3avGU9jRGKOaimppMx5CNbIPdqd80lEcJvdFBRDvBi62TYcNehziSKP4uF swrBa8flp3cKDzFu9Kv7EyToPPv+YCfSM4U780S697VQ4FTx5jLHGsxCKn6scZ73gNwqxGgEN78U 26KVbGT4h427lnLUXN1XGu7rl9EdvoKF6Rb1a81CLeTpjfGEzlTLmBLumWx/8jPeR890EcfyCrBN UXIsJEdw9+Rh47hGzGTWQF8UEVIS7BQ2TQzCPMIfgC58BQ7V/u4Fv6yGA7bX3Z90nS2wKYwEjdrY 0ValpsKC/9BihAEcvDw3kNzVo74O9cXrWdNucexO0BYCblOINhMQqfHCa6nWZcMxuWO0R0VVkGEp VCEWLhWYJwKp2A6V4D7qM9rsswC9bkx8koGNr80vSMElxyyWFCjjBK6y70Nkb3PuCbhJwfVCLYK/ Li6gcMLYTf6y0PfIdJL05XHEAdNOplD7FaAv9GoT3HazeFdpBMCeJx1OQoJOSJbKttbsv/CkKPop UlpAyqEFrAoUTff8Pt2mx3JWRcajh/yUiPz0KenDn6ZeZs4xMSJugeac43qX/m6u9RZ6w6oeBLwr oXc1iClGd+3P1WVUPmkr4mmEodJtayc852BXGI0R9tcIEeb0q6jsGsn5y2g86GqTC5p4dvvbnhOa WvyMaq7Mo/0Z0oOcNsJt6A5owhYnAFoKWGQH5utsS64RebYDJnPdRBjQl34NcpSJC3YTcIP0IBlh cSHnTTUjiUmpk1Kb1AyPV6gsh62es7NwJxW2xedLuvfs5BGVqrpvhwQ/3qYv29D9zvMbEQRPk75x f5RNaQoGGAEY3GVCWwORWKozb18x5IyI5kWTQZp35JAIHGWMkUSnUUNAsB/UtRsWfy6/kSA5VoW9 bz4SE9ysxi+jc86lz84yU+Gt0uL0FSLVV4BaOGOyS1vLIlImtJHFXnaIAkre312kYki2awYZNCMa O7jsrp5eKNdRwlhuvGzrmn8o0ibppRXqXyJ9wpxAarKhWx4CbJrAAde14xvvlk5S1lI403K+glhx 5gyeNTuE/zedaOekbClJmuCb1BbkuDMHSFrDj8/6kaM67Zxnld8NS+RDdBvrhxqD8MFBizampZe6 86rNvhmHlPUMNbq0E4Hqr/3TQNjjY7+dRsrtTwzDjaHvjHPZyo53tVxnUqtAL4XuCZ5zN0aG4mQH 9brsEwDMUCBlOSTt5NGowseB93gC063tvKJm6f+dZyZ8KdbeczrWhQOKd0qeaKzcXJFE6Pio7Gao QMVJ5PYYXKCxSzELSV6Yfw1D64nr8MlqoaySLfXqB4pbeqk/jPE+bLPCsTGvcE/UA5RsZ1X2+SNa M6ba2xkt7MnGdn1c1J35nF3DUSp7g8QOjXGnZS5FqnX178tocs98lGJVJlN9ZUVYqylqm06dkgCA OghuC5vaTeWc9mKKQ3KY4U0bNEUAOD4RO4qOOEmnAbtCNjnjNux3khpS9OlQPQZPIGkY0s1Obd0n x0x5ymF3NJZOhutxiznyjYB+DwaQb7sExQUeamra/eXLjo9id2DkWc/x/YAqAlOxzCOdQ3hz4GNd 6P0b4ytPfXHpNvOhTAthKdi6f2QAm1q5I3Vj5fdSEGgsv5/RTiD/8xnxR+veX+IX1WDwBhKcVzpE YKPAaOvfhDul7t6pw81rCE8W59Pv3zVSXkVZnNYfOXROUBmmqpVb3WS1jxgnJSjxZkzlbDIxkG3B HrmQAFsGRIaaCyFNLAj/Tyoxix33eNk993inYagKzMnvbCKQRcCnjC+BmP8SnRbjyaygBV1anLW7 +zh3SHPmTvft1u8RTB17z+mCsIN+r7ZihT3wlEO/MoDfS/MqAeAk2qCsnOZ6HyUxz34W20uDRbGM mDRTuPqdDBEfXzcJAhFujZXtKdcV04kQga/sSqjqewsiAS+vckqjHqUOF/MgmuG96tT3OxLNXLV7 LhUS4+NZWsKbBiMdWc8OmiToPgMKlbY3bjUawARXMI0l2mAcAiorIvh69SBeN+ryOMq/N2cs7t+h CQsspEJ3Jv72/FY9mNinj6R/ormTmIvY1fpHFrYsWQO6Wxh6kEMNgE5Z2PgEAM9N5vxCEjgWRYrm NRnxZNKg1x7LB4clETjoMn4l7FeIQ9gcuUzh7F+pa+4Uw/e0zxuiw5H4hlOGnGm9MTCuaJOHh+PV IDObKFFWBe3JBd7WULEmLfHhhOgp4bPbkLmIZkNTfPUyB/StgutCotRT8mnNN45dKpZM24VvL3Gg nqyh+/yXOh+NMnw0TeqwLbmawaVjHU15rbJwAcLjBLA0yMvdcYlEIpsbqXwM4Uw1v8zKTaG/oyMM RYnC+hUxY29/TzY9HFJKY1PKB7F9A3pVRjIBba4d8Ca2KsbnKVZqy/HMYbqFtVws1uRVfB+6Mwi2 y84UZRltgaHIXU17dA+gaW18KBVHgx3k4LsLQu9nFz11Ak5dkdaEbWYZ8XqhjbHQIpWtLmp29yAd +g5Ez2oq4PUoy4M+9SHgAWYFu1HeZoj+3Or3FlNUFC63+FtTppcW2TL64uyNYehfBOTA6EMfWtjo o7CsBOv1kZguCm0UcvHs7eMtDb7ppyrYU2osSxE5+Yf8NArPBuhGk6nRD9lrcuwHCpOGl+1E+d87 XkForkIqDT1MphRc/FP1yLO+uDLpZRsVNvKNYJrnVmzO7FjVcNwxYOPUXt3DrWt0yslLoXUwjqH7 j+0o338J5SShaRn0MhWoj3kXwNTe2Ml7TTDbhKRyUomck+LX/0psqYhK1CAdPx79QNZxu9o8lhWj wL2xTNUjkj15pPgdpo5L0aibL7ne7D4RsoZfQXnqud7d/fh+ipncWKl7CuzSjOzt3FzcH8XZ7+ek kc4HCeZt7/h2RDSaYrqFCDNs/DiSS5LWmLbIZGvE33C4nE3DMFpksbp3ta6TTH2qmPoeMPu8SxDi PVG9bYEe1u3aBV4wzAvH7y5MjFpjIRfRRJVaTqWnK+jmEUVoZQWSMRXSvLHiAmaDAO1j4MQ02TLu Y2YbHyvzijizKVQLzRDXN3MNLGBH50+GyJyU+btH93OMRMeFLv0JPQ/kDVaeU/+kD1IolPJQFy+X AjOrge+nvVJvvWqMIOb8wT/el+6QQ7ERzpswB5dOctESdEERFTwl/DtJ0Lh+S1WGZY2roJ2f9bcF 9qUS19GMxNu6PmlKHpLKeu8dWJNxYTx8i5/9JNH/YeF8fbSjg+iPts5bCs7ZAYGtSX7lBxc0yTZY X5I5D2JO2AHErrUO30RJ7e32B9UKm01t4RBvRkMYJQkVLGjoozSoKtnACC1D27KxgoOnyGo15Amj uHBKyRnGb6ZAKZLZmnNv80yR/binSsc5+O8MUWL2MXmk2MnOBLFcLhcT5hq20WSZIDr/0arKHp+9 5zYIGCYZpQHwbaqbaQ/qg4CsgH5gH7+Y0ziEOfQ+8YTkFCWdYrtJsi5cP5010B1/0RZb3JPVC1rJ NaytL+Nx5wE6HuszU9OhS4lMQAO2P8McIpdsXWMQT9qEbcao4rgJAEUb79ZN/o0nuIasD0uQoXqm Jhsol7fxQUugHs3VOzhLmnIYdGljs6wwbCw1AiQtUAjZa8NGOp+IiCHaD9VbfSPl9xDkYx4vdJf8 oIhkd2/2WjEVRWU1qsVdtEpwa+zp+D8NaXiB5iJhAgvXEfdemv1d/igigKgyphGZcMlsyOgDrqIU wcJ9uFNtooYjDaMljuGuQCuLpGjb2ightuk+Qv8QV6ufs1SDJR2UNRdzqDyjGwL62FpK9fCNi/bA vw3JXQMMbg7EIv2MGBhyqlW8EBDUEYkG6p1JB9+ZjaemjSVID0IyJ26vkdSjffEUFkn3qWcemTfh cgHk6DUFQmiFkomG4ozWIqxK1GZIss/F7UQaYuJGXlNpNrCbJdPmHy2VisZsnIGDWwn9go9xkl+o AeJqPWFvbBBKcjTW5ZZfiVSJkzBZIc4GrCOJ+KdjP+0FneQop1Z/NJRpZw0SoMLEd92Ss9hhs/bs IYx/iVqaWEsLtcBnYlqBTHu0p22cPp6DcNL8zqmFNegXoh5zhVXVkr5atnKABU+IMriXCP6l4qfO xINykOD/H6oT1e8MEV5dzSn/iN/Ux05xX0DI4eNBpiqIyFFDJLWyGy1HdFzrSxmZiZIRxy7Ry21A RUD+YmXyZPOqfy6e2e2BqBve28frMLaNDeEw3VHDhMsl0au5qdR2mVk38Tj6aNil1Izlbd0HPVw+ UksrwLgNBOc5L+bzl/M9HwLOLBIPIDvGdRBTJFS69XioAFRelfKb1GXSa3o6aZ0hejfigUJ1+Ggd WFGsz1Gq0qrY/Mv7w8+/JbwLRVudGRSYkt592wm2qq5zDFFRhXZczrcqYpsnkuIvHEWU4Wjjopwo 0o/jxo9oyM0kipaIgdsCqLI17T8JlAfJK3C67vBLw0Cka1lIon2ndlsLTvhvuUwkRfo0iLPiC1ao RL+sieu2+DEgdlkwdW1Z0lKbBGg0K5QKy7np9l5s3VmlexU5ZDj/Y2O/A7HfqP4Cp3WkokOjSTsn ozRhdOdqIHW3xA6MQqGyBAeqsPEjyu4H1pLwNLVucAGUexbTc/Z+wnrkTMDL5b+QqgQhjj/CrW0e azUd+gtbrFH1q6h6MzKxSU0ynaPJfWLNGShz/h1zu+GRtj2Ty1OPeyY2mea1Xj9i5opy/9Kk/RYd /AgH7yH+cyNJOJvGBnsQ2+64K8z3q9JoW3CxZhRFUBxMVsd8jVnhPap3ZLL9weu03E6YryX9vrlB p7nIetGXoQOxBEr/nn33WRc9jQ/jnKMsK1wPnXrXXFk3dUTiiPdIFFt9LPO4s/w7LWpwzxubNWYX TRYcAZHLK8C1Ho8BMFUdPHXOXoKtmY/nnPKt8pHJcHO7WBb4MIPL6j6CZFuSiieOuK/9ZYZ54Pec xMmRWJNCsLICImadEOpU8X60EqqTeoQSE9Y6JcgdLl5c9FaAAoDyz9S+atK5lxeNbVZU2qMl+7sj XklnA2vYZKyYfdI7vWGoDzY5stVOxOPMaKJUTEa9qsJqPUJjr31GfuodK6Nsy9Oazfy2WwVqgib3 QOzy+dmoRt6/wu+i9X4ZArccPkUJkaEYBxHH5dduEd0tD/mjMU+Nhq7V5WcY2j0Y0Mz6simPqCQ1 uXLCXnI0s7UCUUymWvIQPSOtR8CRi2UQ8EHU8UXBA82RnY+NFqWutEXBZThBnvEbKPKNya/quAzN 2VYe4ekHWXqen72M4eY4Nzn3uzK3EYk9jJO036J3GHMHEPjy/424D0npyy7xHunNXFFJ+x0UmBSP QKR1k29YQI9i3YVDHSyDHZBFdjWIQK/unsjVF31gAkNW77hSJ2kVm/ownxZjv9Cz28WzN1SRJlVj qLT12PFsyR3ZGbF/OC8egx+jxI1rYYkNRwWFkgBv6bLobftwmNolXHSrM/K0gkOqmcaqhY2NuDDu KXZNue2oc4b77NeAC19M9L4kYPX1P1fOOCBiyJvgoN+BweWdcOpVixANYrEBE/coO75cZQ1X6lnv eE5GHgxE2rlxiThkDOZx0fMXWNM4xecuhuQ/pFRHH9MojD3NKZBD/4evxbA7yjSvxDEHOhtUMQ9A mAxkKyj3DH0oqmAm1FGDki9lHJsxnoN0suib0idfXZ2zf0d0FM9r21yJEM37NpkjaGIQoi7+WVW1 80Ovkt7q3RWhLa8DC3SPHVb2q2uaqSNauUkt9dttdzDH9XnsI2mnzkkkWO/+acCxg9BgWp/nO74R yKyE9sZJX4Ey48UkiWMD6EaDGKOpt/NXIANq7kMSqxOr3V+gjyd4kVEcsg3D78wD0fHffzQnCE0r 3pbUEFfj+DCgD4PX+Na2e1rIcP8F/nuAZeTWqyF2Ik86TvV+KUok2LdSANeoX8HFFB1TStzpsb7L Gutjiw+y6Gtk98dsDRPhsWOqftMoKXcGmX2W6S/edkQCWSfQ3i3MvwrJo1tbjOPETjP2i8QEzFBU ixnyJ4eScq7ahaki8URwaBjMMMZNUipzyD5+Bh538ljk2JoYH86RB/zWomKscLutZkaakfA9TnOU I8/lQ/F46PNpnW2oXIUt7HmlGM6DA8rDDqaHwFV3C2euLQAmU2ow1MfhwcqH9dMnWeuNURtetYHo A7GHaWJ80484zftZPtPkWW/f7TYl2H3BtPy1FV0z1NJjR8hw3hHb2/u3DzaAwSus83iv/RTfdY/u 8JdlPbGNfQ7NIOwooX4CmnydI5L2EfrSqRtOP9Xoh6wtyFIs7DwjMAk/5uStGQgQoJ58gpmxCBcd 7DQ2ifNTFEzuCiDXCmEF6u1AVPHDKBqhTDB3qKaNv+iXsrOZl/LPCZQlvPy61k8ZqBtTuxuHU6EU l/TzDz5v1OlIZtDHDuaybSffLfcx0XSlxE1DMaNy7epTRh8Qk3r7wQE7WAGLoIA0Ylkdso0rpMId 7OEY7axt36ImGEozcYuLaImlQfCtLT38/95F7BEzWcdabPue9qWBnFtsdAG+m/F/LMsK4PWszb/g wxsMODIxbxFySQA4nCxT3kwA5yAVRV+sbXNvX58qmORfGxl3P0WTGtuCcW3Itbo5rv8aHA5WoTwQ 6lgqaEPKH6KY0GiTw4UB/8ccpbRfgYyGUUYnGkRKWUG9iSmMZhgwf/wGl8x/dIMi5vpsyw2JwZux KIvO1yaR2v8kXHa/AMoJ/naKGBwXh1kwO8pUqPegP82Li8MlJ16T4o1WjuZnNVdveHE8Yv7NvkpC 1alYHfdsdQUsSbYhY8fApGNfvpg7xHWVw/8AxnORDD57BMepPd6nElIeGTa0WljH2scKgkcIDGHl 23ALnlKw5TdBfHplQuJOch5DkZcRQFOgx2K+rTVUbKh5CNi9CPgep09digSBB50bfyaFmQmGzLG8 XirbWarxPOz85fLxrwhwgQqzg0m6Br72I9Gf2ST+7qeprCheeSAjGuhGWIWDqwyVZafTlXN57RYr jc7V6jzI8/8y5wqO99depsyzcVK8t9zWZAeHsF7ZoihaWw5/WIyJ/UYfHgZYZ8HrGyuqRkC7U1Zb 2GDfzVjc9iEkPFHn2DPe+F0vZ9Tr/AqxBUJMmZFNtZ1zXllHZWvzxYnEfYWackE5CjwxCdzG9lFK bAOg98strHi9yroo43Nb05e9X8FYfQmn9wFx+/Gn6w/Coa6h4b4i2cGtSbeHL76kZPSpwDduF3gl UsQkixW5ttkebGvXNcTmxnHbMQHtqqMGi3tGEv1bvHKBbWVWs90WHeLpaCQy/eMqL8Bv8ABs19oj wSMoXXvx8khQ2/jhXUhf3JgsVWUbFYA1mMY9c2UDUB2//tKn7KssoI+5OHBN43r7O7j0Z16bNE5o jCrfoOjl7ud/2JcM+p7PNHyNGy9k8ZlyE31vHaRAaQHvVqvd6R01FhHBZet8ATaVPnVgSnyRaA1l 2jGgmxR42fXWuqAz2n8I1/+kIFQR0u4cuEHx1/+K0YhXgnh/ha8eEU3rpYGIo/HvV4otOZ2Le6Yl H2LAf0F56gel56jIYSHysr8vPK4/CoX8bR9+HfTDN24sWRbcU6aq3IoPh4BOEErwqb19dW2DLw5F M0VICtW+o7lZG2dknJCjWSXZzuNZWsHl2fefnUeVB7MXV9qxlglCEeig5cPunkVU39hme3N94HXK CEftN8sr+SS6gHZM61WQhU/wniPWZykSjBfG8oLS7+bzGcjx3aICJwIUWHYxddVRu15V8Lco8NhF C7iOM3fCQ94pHHI3nGEnt5uEVxSOmC888yNialsglB5covJ6cyRQxsDCsrwSqBd+2JIoGYSxeEzK LhrqBvlYmo/Q5xRPaSlx8XA2s+eUNagPmou0Q2h2cj4okfGBua0gbTAV/IuQZaIqtRa/xQeUoVRm XLUzMEX9En+Lv4PMjUPz18ypVbRrkqmxKwWotKSnL08aJxYjPvl6uos29VWnFBgHnApK3QgiB0Y3 ayCLNR+hO9Piq3IRHeK3AL+7Rz3lVWcmTWq5o1DXaeIRd7vqjcMjHaxvC9LxKspXGDrBxO/o1xMk WDbNSGx7zhNKrL0QZ/HNMMXOIQMYChLeXQXCRVjFp+6mR/Aq9Hx6KgVrAwF3c9tHupdc7SUeF37v X1hKkNKfcWDDxjI4cpnZgk8CJGE9vty2UmETgzeZ5jKjOj7J+b55+WxNSydFMBMlALsJV4XDq6Cj qZLaoE7ueykZZ+yO5Q2B3FhakL3aMlELbhluO5RZGJtSj0/BdfCXO2oAeYw3oS8xI854b98nOVOw 5dDMbs1ztejqClMrAtbou+AhUdCvcipiRMbB0FEIslHDXcJmJcsF4RuQuONpTn6lsN0uuLaijJe8 tou1iIfXdy5irD9nI4syBoNiYb++GTRsmMH3TnEr0dQlvfV2FvUOvbDpgAZPTvgP9qiiQBV2P3E3 6xcAViIK8bqVoCfMaD04QFn2w+zCHd3WE2LD7dgGyDNys/SuSw5+2mOiCw9UPJWeY/OtKBMItorW tLt8wUZe/hxTVimDedE9cRSq5IPgdZdLkWfhHqUrXzmGuR7vUMOJyzVXe43l4mvPztRfI2NvUSwm BEszSzt3sJ802rJLTvJd/fpyDg4DinD9sh/pv43hZYE5ZJn/B+a5IdV42ZLocdAFdB0LNDWQ10K6 rDQ4nBVbqL7a7kzuYhFxvZ5ORn6WGS7SWPFXRPTSjG0OtjapwJSjSHX+ASuiYrR4m6xgHWKyegmR FgD7tPpnH2JKrEGBEzWefAtae/E6x5GFb4Zpa/WBVvZzJpxy84M6/h0FTMWyHZYEvckOCvQtFr8g wKhE4JCdXKYZVkIpEQYCssqnIT4YI8zjl7VeJpDxbrYtMWo1xU0sXbGxUrIpzRUsAP9f8DvkAqmv 0ORwlnALsfqG6TRL5PY9ZC5d7LOTIUnRMxZipcZoGCbcHwCeJehBIHUiXH0X9Dv7AE19Z7B+plF4 OGUYm07gQQSK4eutQAa+qXf4yJIvSbQ1h0unoq9e7ILmx1DnJXf4miDyVrUBea3Puya3mLjKuCJJ Zh+xuod00/5opLHI5xq15wxQ99jG9tYxamEViRuPYZSeR5tAj+UsLpmzyy49IFxaHVSEJ+drClL+ DqooVhHBvhDUrbESJBA3Cz/fWFMoOG6s5MTs8HdTFqmSVd73U7DUY7kcpOY9QYtokvHSojwXhAO2 +XsZ2ZnOeLComdfDuSftP+35Y6gSSwxxk8e1xTfMUxMZbGHrCY6vEYkA3tOA0nwilriOWbd7kova rGSwOgwWmqi9Q8VkYgCJHhqz18neQsCtQt5N4z8Saeywcut5/rwIdckh3Bl9R2dy4Qx3/x/uATCx OCMVlYkhxF6j+hF6weAMBsvOErGUXnVmYwF5Mlyrwv9ZoLIabEkwPy+dKNfbMwKNtf6D+You4NQa 8W+Egcv4x4/eEqA/YOO13hQHKy8Ta+qEdT8tWc+TGK8GCgLah184lfiETn7LcK4QK6nHTXeVkDOj 1Mz6kvPVW+xf2b42VCQ1F+UougWt/6fzZf69bvgL6/OFQcAIZSFrcBIjiHRt+eBJ7OUS7y8FrWIY OZ8gKP4u2wm7WrD05mDxY9zZQUpVb5jJcTGELLLNF5aLwmeuzlKmg7VAwlb8r8me+Bj+F4O1Rwqy MNphW+ruqqP45r67R/Gq+r/WSl1G20kNyamdPfBCmIoWQ9NLdudro4dSdxR1lgillOeqocenye47 3nZyUAC1FXOVzFa/rzrE9Ja6Z6UMiL8HS0uSGqYJ8EbA4vJAaKpxjpJB24V1bB3J7opSdc55u5pq ueRIbvHHTYKgDlmHKla0pktyXTmWGQmo8ljcZjQcSESXZu8FkSL/HaYWVve13dOxTa0mTppXwkCE E0cTEhxaIR4EIeejr80/nLtNCIzdzs8cbW8L+p28Q6KRm+dh8SpRzR27QZqgHSRJm1kPUD+WBsav ONBBA6dQzg5qSqoYP7rR61rJltAHX8xbFUX/fVAHj0wS64gOmS8C89PFTEWpkfkXVu1/0NUhxz76 BgWlvDQ+9d/vyCnBkJC24ZS8vDZJtDi8NcXj4by7+iOET7GvaFAuirRVy9pdNaFt1DiGcKAAADGi vzGM2F9bjcGcXkeffREsAkVvq/gNO7ShdY80E0TeehOjpvjQOgc8WjHk7grbbBCqkcid4gSHWKBG MFpdBhStLECAqbqN61yvFfKfUjM7JqvQeEC2ql7h885ERvmhyS8V/2+baFv5o19HEHFngZBYlkD1 YxVOKjWTUo8dryl+08nSHS5EsosSAcmSeG1ufEVpwG3igz/PXCbR08FlslgJPAV1vz9TQIRqnGgv S4QtAVE9NKTHOuFGeQTHwR5txOTgEbnmPSJt884wlSL9+Y1KcPWlr5TOBO3K/61gD5CnpyLzOMD/ J1sw/uC+ZxeJhIu/LQZlSMPIOmM3w0pNYZFN4eG03UlLEzgBhYBLsTWYsSAGomIYQLNtL7p0YNTd AqfuwT1HML63UJzBhwCazcHLbW+I7DJs1Oo1ZlXxgrjIFAy2+Yw4/8d91pqzwbfhQiuiCTbv0rjE 18TYisfxAeLmdF9NGdm2cAMapCy6iGnJfaTM0fEAs8+3ZdVMk98jdONR44kCAChvY5fiPIt/RfIg YD+ILn+JFBKAsM1s0UehGoOKFx4R+gfEPSUByF4t23mA5B9IZbi3x8595JcURtGlS0sfdO8Yxibj jQYjgNX2KX3B5D35JmMVxpfXrzjo1AMo77FRRslmAu+Wa7Ylyi/6HppTyrZ4wwRKRISdY4ZT4y3p nVZAXjdciDM+3xjFkbQFOIA/koHHzWlkz3jiSsA9WH4U4nSipeNSiu49VXn4yz32ZcphWP6n9s5h BcD24LTD2wRRwZt6e9i7QWgppkc+hjZWDQZQVsKeXupucen+UBB+kanGUUEnj1JCgNSN1Wv4mTLB a1r8jziD2nNKAkDC/KqkqkOJGqgkz1JU76wWc7jvc0Hj6pBl468cj5Ang9TKh5/eZ4wGMnHJpnpK Zk0tIteA1Tgyz+vhzoZgUMWHL/32tm7jSwETiPDg9hG0tPTahzS75wMw4Y+hWOApAarQ5FiTcosi VNEyvjpK9VdzNbrYWcHpIb0+UG4ue9MxF87Lkjgx0Cjg0SoDcghY5CvXBll659q56lTbRurlcITn FYT9kPm9rfHjW8dlyiZmchnPt7ygnXqwcHEGzdZTGwJuw1UliAyxtZVFQAdoqz3s7AGgkg6G1uHO nPl52YAyE8ggX3LndvQnHVB4RUowiQIPwcoNgt9r5nJcCRcgoICV0tts8AJaJmLj42LAxs8puHSy rzFeItRbmxcj3Klq0iC9WJuYluBxV7//ubdisOI7hlrHU0gEZB9V2DaYRrb2KpcK26YdMPuRqveQ 6nmOaeLqC6CdZ7EzVnc7Ba0at0/kcD9D169Fkp9sDJ3ICpUAkeQKKYHbhpPGIwoDljNdLxjKWQa9 7g174s7SEpgcE6pKs5VE1gGqS8ftrlaU1TWOW78TZSr2tclzPW9cecWcq0dzs09z+/Gh3MXnL9eG LwbeM9RHZHGop3Ps3BAwVxwC30us+7zLivjxODTvKsr3un9q7OAqYLfbVMKnig1dauIFz7+SphTu dwXy4XBpzJwuwFbPXwCaJ+9Jttlm6nHNruHP0QMqr2NK0SPZ4BLfHlyHIkVTs/isyFpbUe437y9M EMdoP+HCyqi6RXdRylj1cyrUPLRYtr8FyxSyOkt2YfvZc0cwsdhO5CO+nDbKLJUIuuRoAm+xRdVX hXjNeIdCH5ULIXxoPMZi2eK+aaqn121NFXtur2XAfcRPOZfDmihSZk3vFanfBo4TbAJ5BNes8UIf 6VoapfUi3DG0lkNRX2GUXgHs7vLAWxhTx3b5xBXr9I8f9rhnrfEHWwhhhfCEr3D3gWftdQTdYMFj WjbEEo0hLQ3XQtcDwpJpGyg9I14rcLJqJ6vnnUz5Mr0QTfX0QCXNSNRmzQsAOP8liX8C8/8TMPaU evVnu/quhjCUSM6Acwe3r/sW28PVCTXZSdzeBWnBs3/CDnJH+xCRbU52a2W9ckKQnmblXr0/AdQi O0cEnSwJitssuzLa8m0tNC7T5K6WJ8HwJuMhJlS+uHgtWDQvG7NazeIC8MbZbaca3iDdnlyqppPD UHuhevws/U145fP9/i5sxXhTZ3SmwQWeiHtQT8jy4SxpOeZR3Oea/0yRstY3hG9gDs09UjxdOty9 tWHjKSmp9aX7dGTygQrw5IEGKYtHUQtYFuYFyhzmrcwOygK5bOyDBGr1j1R3Clkd9hkIRoEf2xyQ EQKS4qE99m2N11eGYyxtGUi3znW/3tgyDJPUj4YuMDBFQdCL05qG//c++1Przm9xV1nGw2YvTnI8 /GM5S+39mFJKMxaVZrcRxC3b5j93nXerGKgKZHLBopGi/bgbySKo4tODFXE03T8u4jpr4STiJPRt WN8q8zmUYJVU8OgckNVkCg/IyaWm+ghIm0BZPycbtatjy76nVTOOON/YcbtJ6y1TvS+5ESkYRys4 K6wOn0PpZLIUL0ASjcz/CEqwD5YeDbjBWUbXc/d0R+AJ1gJvcIXD0zcpaqn2qXwP9bF2gha9oDYY GIBg/geKmvp0TMcVD5TPLcn4oKW6fpZb1/m93NQ2XYC7EIX16f+Qk/vK1rcWCbc8IkmYCHTQsvbF AuvO7QNEOwEUUaX4KeIJo4FiKjrsqjm7L3i/LY0qieiQwR48HY+CZwv5WptZHRvoIxrT5fdoKqBW qVJz7s8sfV02XnlLFY0q0LXQKIXggR5yS1NzMqgzen2jSCBIz2dKSSYegYCxayAxS82WX2vMMWDU 8FCBJ+MY0Ey7qDB/riIuf2pQxLbIqOp7kwGitAjAjdE4+dS2hyc+Jco8hcA/AtGRW1UCPr7GEp4A iXU2xe+DITh6nthXbbfI8HDA6khXGQAIyHNrVyOAj9My5ZNRC5PACjwWOWLrjtgleTWIZ1+bo3p8 ZRnLWN8JbJWWI8cbMPftNmWTlgawWmRQrbCS33HJ1kz1lulcbCymETkuQHyhOG+fnJbiO6ECrTZN UEWcFO+OfpHvs+5CCU9rAfK2fJYKcOvd/olE3IBVz16N1UuFr0b4YmILFwe0aTu7I/mtYKB3wKfC ZgLiYT3Hy+dC3TNR2bqur7WBqZdQta5mhF/+1dlUofwU+zVbxArhCImQgLijPkRQ63/EOAZ1NE0F lE08VgGPgSPOE1YZRwhdR/+uI0HpliffDnwtqjc/L4+3ckwi1EEscIcVjxcDFBki9oItaUNQJ0iQ ty+KxIb0Bf1nszHNG++vQ+E84kb0WrHVpU96iUpglpx9j7m6t+ai5CZWeWI0GnSa7Q2/1p/z+Ck8 8pHGA9zL2qPmMpopYGFr8BfkIhea61X/skGR3EGTU0+r0as853nUxw2dCmS6ZDa2gP6yEwpfPR5R 9tTXg4gVMFLCgGSf0a4JsZaWq3kwNe+o7JD41h0seEf672thWFsMXmhS4Zlvacf4NxY4yhxntCPm bZKTgd4RG5YjntuUSQTp+yVgh0TaVlo9KYbgXZmxbbLJ60n3crHjLXOP5pS82YsgKGXDCYrXMQBD NhEec5cM8RAB/RtrA5MWoV6/PtsCIszyNNaqgxCBIo/9BDxTarwAWWH0TMYOxcXwAbFGKYzOqNh/ daakI9nDpnOp+gjwwfoF3wafMyVGGn4+Al++5+iV+BDell/nwMH6MgnDK17SySGRbKrv/8FToH5I k0q7SpkFgE3Rx0I+Kk40Oo3vbJyjC0usgBY7myLAdKlhZ0i8JZobEHP/lbmTuGxdw5DEwAFa6h32 ScHh/XGHtx68gfWx6S/k+hfEBORaIYVm6XaaoIBJCZwfivWtt1G2mv+5jdw5c6b5L/vfOCr7HirV 4A4XTx9HbJ5ItkStCqNVKR8VszYFmskIaHYR3FaQYQeUepjy+Fp50GeOzbajv+CbALc9v2r3iSNY UWyNy5vVjCytgI17cdmYoD+tAlvMFUczXjDxrHNVp3ejvrGNjSRC9MgRbGpE66bwF2GSw3Ir/gBP mt/wGuDYlvDM8xwGkJD8lNVNxN8eaKF+ZpsEuBkGIc/JpqKPCnl2KzgNbAzk3llkMuJn20xA2YM7 mGf0jvOPKsYDBWJeTa9DR8alQExzG/twaGPHjyxMAwfEHbkk/CnrsllFiWWzSAQl3WAZ6kCPmRLM PY8cjw42zUvFAvLMvutxpOB8X2nbXIGXObq4NI5Vu0sgVF+NAMng2UTQz766ROIl12D66Wf9tM2N RBDYzqigUC5n7uADSfRPKlhmBTlSXae4hLY3cmgYHibZjGCAHFaJ15CkGDCTYMbcsa6soiuOhFAh +C77GckZlRLkcQ7IQKlHgphNx6kPfuDQ9bmB4UFMswyfNYlfAPi+6qPYLaDtBreSHnjMYkEYFCs/ HOgIeEzD70pUj6uhk2pM7XEX5pv4aVvB6jgNyUQWDNhWi0rxcuFlSfRNyaCmOSlxC+DMrXwLGS9B O/WqZM5FdDbiOaklqSWzGVLBvE1qTpH8ZznZqeL9XvlI2b9YQ17MtuKx8dFp/sUbSOXFgQxDnQ9v 1vsoq9gq5W2SofygzSZX9krdHnwe3yYTOPRSl40OVsTBAjFrUmEk0KL7QkMv9+aTeXiD/ThJe156 ttTkdmyMf+DTCKXc4r+9SwBvss/1oA6BzY2c4Gvx0Cb5JwObv5VTiax0qsAXTyOJLp0q6PvEXVZP mzgRbXuo7BFY3g9p3w1EinOuF6uejvhCBPrE0HhF98ab4By8WCDdhdSs2gm7kVrFdC72P2gWqz60 Rjh+XaVKTj99kfVj3CwnIsJAVL8sEo0/aGRNE4bxzRP+qPL7rPXigMFWohFvwzqljMWFhLt9jk9F i17GPOqmQJ8rrgGCunoHsemrGOWhZVK8+GefndukrCO76cAGhXy/VUz/qtl4CVpuYWNCJT2Z/fAt y8fRuRKLTSTHjyC5stGwYpoeYZhTxvjKNcPC31AUGEIBUe0hNXZuR8vYA5c0YKak7MyCGdpx0vbb b74xSYZby4l2MezgKI7SWF2UjI/V7nlaME6AsgzHE2O+ygQ+0fuXpyYl7wZHP3FtUrXmsA/NJQyO joSqhzgn5HTPP27yGQgCt7yKJFxqbI/zTSh8jM73NHL0lIeecNMRzwlAl64gEXO+z6LcPhQAqZ2J KC6Am4PuKl6FG++MMaF6gUL+mDU+4dhLc/KWvNgIsHptCDdTr8pmbaO0epj6kRI0mp0bcYSsduy+ 9X0RVHES1G4qOyVLHZucw5chIsb1QvwEgu5tNTjLJjZx92+LArAvwPbZz3yzEkT6Ig2J99uzVpX6 xJFFtE6iNV/+bY7K7K45cmdtZM3u6CrR2QRYvTnGSz15xQ/FIHavicWVEl+6H8ttsMHIG3jK5lZN D6PH3aFWJ9EcOpuXvEYFDNz00lKDeL2yNKY4hprcU1oJfUAGldPU1/lDFxgBSUCBAwFHCT5dcRts PH54dBY44HQ37HEBXe2ueaPk6hSBTkZIhaYJxBQWUe+kKBMT8nLMMFrbOX/wt1lYSyrrB4RBk/k7 np1ZQ7x07UP+vWA6R4JHmtql43xB7q5jS7sy9LLYvWfStB7pmLfUAvOs6fRgXp3du03uhBAVPt8n QQp5wlghNW+iYz/cRhKlgHrFHftoK6dMTZW5jsowkGzBLLFnCpy3QLetJlEeOp1pqTJPL4i8JPFi aMSa16AyMyjBJmylF2aMMg/e4CecbXrtDsuRP0FCARXL4JnBm67DRr4Rmu7IuQaC/YsWZ4wiPEpS +S92cXXWEt3eElADDTrUt0Nxe4K82ptn3zPUGcqnUDItLBh7pGg4vCWnwtKXa5MidpGZCtYLXnEM yi1vSz4AbfqOkHc+UDx7wEPx8UwjLvxLxG6EH7j9DenqV67J2rOHWDjMLbWz+VNxisfCDhrR1WlW G7ZmppSyMIJw1jB/zQ3TiSiFrmXuIF7Ev/ujJZrTAb1rz98Ftorg1TL7Y+cAXOkd2M0elrk0Aidl TPUJPP2QOUunivrDKQbwhJILdhp1kEogh9raA5CP5wpfwp1B1M40EBDI7zjAFLWpefzUikG3H3YC 2JXS+cRMAjONzbb0CyTGaoHNcg1zxu6YcL7HUXzAoU7NpV/BqqehfwjgBmwIAcMd2gEyNrfcIOI9 wqfxGxeSQPfbTcAnZTGSazGxEq5YLUi1dhegw2eiARhMSOHBcy8SphcnHUv+gQnO5Z0gaxy/TdSo XiuXRjCVJebgbveZA1xehH6EweqyMjOfHV/dO88oongjrvB5RsVxUonE9RwKFB6si/uYQKKZYHuq 5dCv/AIjqeYv9rRYuJo/CHZDzZkso7ixFsIJRjJ9sTlSQO5V2UDBsI0oyPlSjb4avUizHQqnV58c jEkuk9UIszV2grOnn+voJI3rXCjTWJ9K4YfOFGDew7IvbDENO2vHvaM7UFp/lQ64BeUKU0XqRV0I qKIlu8MHLdLO5lV6BL2lqfRzQDLcs4xrQ7oBgoi18ePXR+ZLRoW6YvXyQhK75/7G49tZyQJfew3y 7D7nge3E6iUKzgim9VLZAfA1Sk5cnCMMXmkdWKIjI/iRe+1uMuNXnCoLKcU/mS/r+lgjUU1DBt24 Pyw+OP2KhRs+M3eNiVCItp+mmwca5i8uUxMrs9fCOO3lzLUekBrKR9L16q7xFzOyyd9FHgpDkNlR +TLGd/Q2sidn4AswKqzZ5Mnxqy66xie2TgaDtRmhru3x9OrIn4xBcV5Sh9b1G6mMRtSU/QTG5UVg 5u74HTdJwFsiyd8jLdhLTAuq9XkdsjdY+uP8euFv2yGOGTe4/1MBCZFMEQhLd2LhsZcLWZHr/Uco cNl0utq9z9p8yLbZbpAgoKonLbp7zpvY0VFswZyS2I6+AJ8GKSHuqDXKswrAs7Bb2JZGCFbT6g+v +Mtoz6ROhELjdEMw8azcamO8jTDUtTJrELXIpGPqXPkNzCnYe0JMQxWA4mjp+cBsZekBQkKiwJ+L auCCehdrR4eoyTfFJ67V5zzfhO6rTmPlrVCcqNAa8V/3S/q9T8kSJQFBhxFS93vaOTXJdlWe5oYb bx7k2l1uXnygqc9h8+AeJMxBRros+TZipVGFhzlyOepuUxAXXkitD3WYKPqQu7+t9q54LPd7LaiL njpR615OQiYxqzfVBXrP+UqxtW+PbvFHiMcl/VPuXNsukXM6fvo88UGYEQiYO2rzWKPCEneakZxM WHAY3qCjUl4xLDlTfRIOAyLTSNC/krZv61pMFvWHBkWL3b5e2/RwCCHfV+thmLsEq2FkA01mKi8I oPQe76p24/zzpENYLDjdyRXr8LWLuvjyH+N2H/b5lm7vUSOIgNbij7sHOfuP4rqMw5F4JFr//MoZ /gcKklt4nPd3pU60/0bBBZgtnlIOLgsljE244CpbaiPX6RxHMX2ikP4ZQf2FrhDFwJwriP/kKd/d Quh9ZeOIyGU4NUdS7TR7iUKV9ZvJlhrpFLlJmqsBMhrRSzAvre0C2xKqro1CBpc5203l6eMurV5c GoN6y+5xsdHMpjU0JDheAChhKa8XsZT0eaA5vAXf45Kpw2XH63HpoKvf6lwU2y4TRf2lYPsii94B h5HVe9SVaob2WiVA9A7B5r8HJWaih2hP4enj7yLZWNrmz4/Vl2KgDciPypOm8UIq/2YdR9GT3CNb 2rzIfqsAQR+Mu06iMoGuBUL1iAor+ZQJ6hehngkEzmWyEualg2tJBXagOWo7AfrL6DLno1U4vcS+ EUHCWT+FNDZBq+72G6AT+m9zNMPSoKNrmBh+93rsnnvXjL+56XUY01fkpHNPQgxFdPxXDCgZpWBb jlhJOD/Yp2OjxHdnmq3+9pMVSv9hhxo8swfrL7ehslv5b06Rt9iD/Ly1AF39L1dUDbvdM++2bYZ2 UrJILc35HIMryXNdebctAXSUjrm0txZSIaiN27IWXJMu0/v+X3LSICkb8GeUwgiA+SGEnT3kPAZm 77LIBh+SEcgA3P/26UMXWWCFgPelTI0Z5d2rPEAheDLX8gD7Xty5v7pOFN9GhCPI4lxt16VsUySY ZbIs5ACH+gET0eyAR06VPhg+1XTYdBACoqCsBlTW69p7T3yaAXgGURgkKApi1yMaktW3p5q6lIc0 fIms5bIhijKcsW+uKUwgKHZWhWsoy4L/5Zw4rg6e570S33p8pLHzBVqyUYrwZlFYpVbwGgs8MO24 Sg6XKmszqDq9cEu29/rKwW+okYQHDY+uyR2yeKCCVgv1YFUXmZ/fJJbNl9FI7aXJFErp5LgyLIX0 9hnGWT4bzmlTDp/1RjJRqQUObSc7PodApCx/d42YdNsvEjkQHNJaNnY+VDjMylAtAUX+1uENzemG hxl9qgMnd9Yqt4E93887zVF3jcNoDG9i8nYwcoozAR5r/dndUxfLBcTMqubD5tjogc5zSmCO/CAH 36XbjAd9+tKVGi6ENeroLtsTJ+cp9tGT/KzQrOl7j9Pekiey0X0DBjVceOYejUPpp2AY4oCjrhew u2fH8r6Nwz2r0x0OTqOdlGcDXo7CdV60uOXHMo7A5cmRWh84FuLKjds7sAfNbGXplVvpsLv/Ui1A Z6SqI2vPBuaCmf6coIYtWUCg5hUmvMIw6tXoJrURt35lfSyoNYi9nKE8aEXIxtLRoub6MugZN6+b ESEyoptewHrDIyFtJ5v2yGZ1u5MTXH18g1utVR9YllSiqb97eYvPqq+r8hT0uHhqIXgeU7tFa9Ze mKBMHQaKwvuTyQgMOIJ9cceRw/sz5yT9RS+ZAxOQwQL0nzxPNOjr8b2hP8D22jc16gTROyJFpThu efh1uTt9f7yW0jhjDpA8RoSgae1TBSGP0IEP1SNlzzSIbiCcwwfu9+1Tfp6V6n6jS4bVjCV0pKI6 aI+oEZg1iSjRZgsFzAkkfat6ZrDoFLZZjlG0q3z4sZ+CYBproa5tAsF7jvPdCpVqI2HG4717OWHw sUFQwsh+WVIk8BzF1R2C7n19C6FSiAx44dH7bPlK+BOiAE6qGqtIfP7t7FikgE3txmnSvKBQ1lez PSBbSGcORE7QoTSmThCIYi+I8rrGj26j6HUyMFSIchAdfGVG+xAWb1HlLTrUIHE4bgWlX0mWHD0D rqF5WwT7UUjvHaK9uG0iardgKd8+CjmRmuoMcRTa2sO5RtXAewZ9PUkUqKU1ku/L5+P3IMOtZdvi s748CeGByuL9/5oioEVQz81jCgl+PWeaBNKvrtBBKPPIa5ldBe1024sx5Kn8g1HKX8Pe/EkYxqyY YsgEBHxh/WjZj+TCXGS59aL5UqXv8tsMFOobSjWEds5a1uCENAlxxRw3BVeGxUiTIHGBhq9z1STy rgWh6XHS4pzFtjMAZ+FvxbsjE/OMbbGcvvHe84+5lLEN9PQgNQLnpPuwfyCcgMxzfMxo/WSVW3NO 7xXNVIeZGBzeI/DDq2wtFv/H8rwseFXMU7s85Y4jCYGDwtGBAbhl9cg1HFSIFMBIYLGQ5FehAJKe N9vphVrmPYk89pSkIIrC52QBQGZ/QKYkYRUU2IGC8M3EWmrmwybUcTUcOCdp6hDDgr7whY5qlvJ1 TS+u+tJEDY5pG3Pgl8eQtYPiM8TubY7yAWrXRVWNkNN5GhdUepf7Yi+VUYfd0GOMSubgGWjT974F 1I05PvFNG++87akoSEUgrKnNt1PsO+MpbHo5hmleLUur1GlRyIkxlflQWizEcYL0MJ+JFj8yWfMo m9C00gY93aRxtYN8PiIF7O3B+XSxH9tma94TToUATEQx2YAtWvsEl11/LQXoVAfsxx54g/+T9vB4 JOWhi4FumdtLsXz3uHECb5XZ0cuzvCd3izbpCPuTEQDShKKJKFcD1U+WFH79NmjoJHCNm0KOwiMa mlm5QLua/gk3JVM/CsloPfEj/2CKP0aE0cxeu9y01v3sKpCQGQ09m1fCgR+jCnC8phoX44ewhSdV FtJD4+IWAvr1ccQRmlG74dR86dcY8W74Y1bgdAgyXHhATYvxrlRhOocNRQLQ2QGy0sgYiGFhFYJP 2zNPdvB8mYuM28tFo8lX8PLm60X/2gDAXI7UP5J1/6kGHkOQCDkefrSDBuiLmFBDCY7oHSGa3TXN /Ahr8f1dULQU7wdSY+3GGRGmQRaGo0T0RF8FwrmmvsZTZlOo9H0SLGmbjy+i0/TWqWcTBm6ooyc+ dhj0Z7+gKi4hBscEXYkjV0Jgg1tFXj7YmkleVKYsh8h6S4M2chsoMMQL9J4lL4W08qcOuhVriuG7 P6beQbHl2OdfEx9cydi+/CUJe79GBJMSM1XE1mzeQy39hibl+tQlzVUmWG6anXim2CZaAnLdFTQU o3MrZ661NpbdJXh8I7vgnuDcRd0+vz7YjtOrPAr8DtjmnA5vOclmyml3xXWfx+kz4RRvNvBlaw6P OcN/4ZmcYMx+yLu8jeQpGy4iGSWktgJZBfZXNPHPPGZIeOn7xD0n+Y5rmjZSQl1Tp5fxsPqMmJzJ O43FGn4W2APEj5i8djzHccMcGjO5VhpvksNFgd3yk4dy4VWhZaFYJZLxiibiL+tXNKdZqasVLhjO pj4YHBpL6xgEA8QE2/2QgAKGKERUhlc5P9l/cSMZk0AutfiaHoxQbO9PIu/O21Df4Z7F13r8FsjN q2LGA29MgrsZIAYwRpjANNWqkHdgdN9X5Xro9n/BrOgTwn5cuN1sdbgct44iRT+MFBRXDKe+MFqY DRni/e3soqhJQXhNtWqYE+0JPwRG9nSEkcrLHOc8TEz6v/CXzEjKFMMncU3Yyj+QkT35fDO77k/A QJQiiZ95UcfEp27UnQ6wFWUX2/iLskvxmy2EnQbiAscN3OdUKHFXjX03aWZN0yJSvV4z1GkaCOQh yt8J2pGWkPV4X3258qAvxhJDBcNVsu0dTvwhJoPJpBySUl8JYuZFSwmB+WszptX49S05PqUt/Cfh MrJSVNozt667LWNfSzPArVFHfLYwQtSJ3tol+EQSWh4uKeKaNBJsbMXnin4GhIjRZXgZrDmMcvYX Rq/r5J+qB8DJrkHxZSipxsXEADYgqH2rbWIXFBL523siPLdmaL83WGhVt23pVjNFG+AxdhXikA8S e1A5VGAyxxOhUmspL2xeeY0n9S25euRZ4ryCgycMc7a5qSS+Be/blI39I36QgfrAozJpO5yJk2ka ybYXJIJRI23QcPOG3A2WKjm+LwxDvrCG5LrqT98RA11VUABt8NJdJ4JDoSQtPP5017X+xa05tH4v sDiTlJSUIl26HPJXubuO0ULvSG4EspM8OlGNNnK274jVaB5q6o9OXoDQhPmMrilOPdmIuPq7dwEt nxKGucabu7vdZw== `protect end_protected	mit
APastorG/APG	real_const_mult/real_const_mult_pkg.vhd	1	27902	/************************************************************************************************* / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Xilinx's Vivado / A 3 space tab is used throughout the document / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This package contains necessary types, constants, and functions for the parameterized / int_const_mult design. / ***********************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.fixed_generic_pkg.all; use work.fixed_float_types.all; /================================================================================================/ /================================================================================================/ /================================================================================================/ package real_const_mult_pkg is / function used to check the consistency and correctness of generics 1 / /************************************************************************************************/ function real_const_mult_CHECKS( data_high : integer; data_low : integer; unsigned_2comp_opt : boolean; round_to_bit_opt : integer_exc; max_error_pct : real_exc; constants : real_v) return integer; / functions for corrected generics and internal/external port signals 2 / /************************************************************************************************/ --returns a vector with the high index of each of the partial outputs function calculate_high( mult_fundamental : positive; input_high : integer; is_signed : boolean) return integer; --returns the output signals' low index, which is the lowest of the low indexes of the partial output signals function real_const_mult_OL( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_low : integer; is_signed : boolean) return integer; --returns the output signals' high index, which is the highest of the high indexes of the partial output signals function real_const_mult_OH( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return integer; --applies the assigned parameters of round style, round to bit, and max error percentage to transform --the constants to the correct fixed point form. function fixed_from_real_constants( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return u_ufixed_v; / functions to obtain the integer factors from the real multiplicands 3 / /************************************************************************************************/ --returns true if all the values in the boolean vector are true function all_positive( vector : boolean_v) return boolean; --returns a boolean vector which indicates whether the constants are positive function is_positive_vector_from_constants( constants : real_v) return boolean_v; --calculates the needed shift to convert the fixed point constants to an odd natural number function calculate_pre_vp_shift( mult_fixed : u_ufixed_v) return integer_v; --calculates the positive odd numbers from the vector of fixed point ones function calculate_mult_fundamental( mult_fixed : u_ufixed_v; pre_vp_shift : integer_v) return positive_v; / function to generate file names 4 / /************************************************************************************************/ --generates a name from hashing the parameters of the module real_const_int to obtain different --names for each instantiation function generate_file_name( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : positive_v) return string; end package; /================================================================================================/ /================================================================================================/ /================================================================================================/ package body real_const_mult_pkg is /********************************************************************************************* 1 / function real_const_mult_CHECKS( data_high : integer; data_low : integer; unsigned_2comp_opt : boolean; round_to_bit_opt : integer_exc; max_error_pct : real_exc; constants : real_v) return integer is variable output_inter_w : positive; variable output_w : positive; begin / --trying to multiply by 0 assert report " ILLEGAL PARAMETERS in entity const_multiplier: the absolute value of the " & "constants must be greater than 1" severity error; --using unsigned but multiplicating by negative constant assert not(constants<0 and unsigned_2comp_opt) report "ILLEGAL PARAMETERS in entity const_multiplier: the design is set to use unsigned" & " format but the constants is negative. Whenever this happens the parameter "& "unsigned_2comp_opt can only be false." severity error; output_inter_w := int_const_mult_OIW(data_width, unsigned_2comp_opt, constants); output_w := int_const_mult_OW(data_width, unsigned_2comp_opt, output_width_opt, constants); --selected output width is not enough for the result assert not(output_w < output_inter_w) report "ILLEGAL PARAMETERS in entity const_multiplier: The selected output width (" & image(output_w) & ") is not enough to represent all possible " & "results from the multiplication. At least " & image(output_inter_w) & " bits are needed." severity error; / return 0; end function; /********************************************************************************************* 2 / --used to calculate the output'high from each individual mult_fundamentals from the output'high --of the previous fundamentals function calculate_high( mult_fundamental : positive; input_high : integer; is_signed : boolean) return integer is variable result : integer; begin if is_signed then --(a downto b)(c downto d) = (a+c downto b+d), (with exception: see below) --example: -2(1,0)-3(2,0)=6(3,0) result := input_high + min_bits(mult_fundamental, is_signed) - 1; --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 10...0 we have a special case in signed: --the output will need 1 bit more than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = -4(100) . When the input is 100(-4), the result is 16, which in signed -- needs 6 bits (010000). Meanwhile, for a multiplicand = -3(101), the result (12) -- only needs 5 bits (01100) if is_signed and ("mod"(log2(real(mult_fundamental)), 1.0) = 0.0) then result := result + 1; end if; else --(a downto b)(c downto d) = (a+c downto b+d), (with exception: see below) --example: 2(1,0)3(1,0)=6(2,0) result := input_high + min_bits(mult_fundamental, is_signed) - 1; --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 11...1 we have a special case in unsigned: --the output will need 1 bit less than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = 4(100) . When the input is 111(7), the result is 28, which in unsigned -- needs 5 bits (11100). Meanwhile, for a multiplicand = 7(111), the result (49) -- needs 6 bits (110001) if find_rightmost(unsigned(sulv_from_int(mult_fundamental)), '0') = integer'high + 1 then result := result + 1; end if; end if; return result; end function; function output_low( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_low : integer; is_signed : boolean) return integer_v is variable result : integer_v(constants'range); variable u_sat : u_ufixed(75 downto -75); variable s_sat : u_sfixed(75 downto -75); begin if round_to_bit_opt = integer'low then for i in constants'range loop u_sat := resize(to_ufixed(abs(constants(i)), max_error_pct => ite(max_error_pct_opt=real'low, --max_error_pct_opt was not assigned a value 0.0, max_error_pct_opt), round_style => round_style_opt), u_sat); s_sat := resize(to_sfixed(constants(i), max_error_pct => ite(max_error_pct_opt=real'low, --max_error_pct_opt was not assigned a value 0.0, max_error_pct_opt), round_style => round_style_opt), s_sat); if is_signed then result(i) := sfixed_low(0, --irrelevant input_low, '', 0, --irrelevant maximum(find_rightmost(u_sat, '1'), -FRACTIONAL_LIMIT) ); else result(i) := ufixed_low(0, --irrelevant input_low, '', 0, --irrelevant maximum(find_rightmost(u_sat, '1'), FRACTIONAL_LIMIT) ); end if; end loop; else --result := (others => round_to_bit_opt); for i in constants'range loop u_sat := resize(to_ufixed(abs(constants(i)), max_error_pct => 0.0, round_style => round_style_opt), u_sat); u_sat := resize(to_ufixed(abs(constants(i)), u_sat'high, round_to_bit_opt, round_style => round_style_opt), u_sat); s_sat := resize(to_sfixed(constants(i), max_error_pct => 0.0, round_style => round_style_opt), s_sat); s_sat := resize(to_sfixed(constants(i), s_sat'high, round_to_bit_opt, round_style => round_style_opt), s_sat); if is_signed then result(i) := sfixed_low(0, --irrelevant input_low, '', 0, --irrelevant find_rightmost(s_sat, '1') ); else result(i) := ufixed_low(0, --irrelevant input_low, '', 0, --irrelevant find_rightmost(u_sat, '1') ); end if; end loop; end if; return result; end function; function real_const_mult_OL( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_low : integer; is_signed : boolean) return integer is variable aux : integer_v(constants'range) := output_low(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); variable result : integer := integer'high; begin for i in aux'range loop if aux(i) < result then result := aux(i); end if; end loop; return result; end function; function output_high( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return integer_v is variable result : integer_v(constants'range); variable out_consants_low : integer_v(constants'range) := output_low(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); variable u_sat : u_ufixed(75 downto -75); variable s_sat : u_sfixed(75 downto -75); begin for i in constants'range loop u_sat := resize(to_ufixed(abs(constants(i))), u_sat); --convert with ~0% error s_sat := resize(to_sfixed(constants(i)), s_sat); --convert with ~0% error if is_signed then --(a downto b)(c downto d) = (a+c downto b+d), (with exception: see below) --example: -2(1,0)-3(2,0)=6(3,0) result(i) := input_high + find_leftmost(s_sat, ite(constants(i) < 0.0, '0', '1')) + 1; --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 10...0 we have a special case in signed: --the output will need 1 bit more than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = -4(100) . When the input is 100(-4), the result is 16, which in signed -- needs 6 bits (010000). Meanwhile, for a multiplicand = -3(101), the result (12) -- only needs 5 bits (01100) if constants(i) < 0.0 and find_leftmost(u_sat, '1') = find_rightmost(u_sat, '1') then result(i) := result(i) + 1; end if; --when the multiplicand is the same special case as in unsigned: --example: -2(1,0)2(2,0)=-4(2,0) if constants(i) > 0.0 and find_leftmost(u_sat, '1') = find_rightmost(u_sat, '1') then result(i) := result(i) - 1; end if; else --(a downto b)(c downto d) = (a+c downto b+d), (with exception: see below) --example: 2(1,0)3(1,0)=6(2,0) result(i) := input_high + find_leftmost(u_sat, '1'); --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 11...1 we have a special case in unsigned: --the output will need 1 bit less than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = 4(100) . When the input is 111(7), the result is 28, which in unsigned -- needs 5 bits (11100). Meanwhile, for a multiplicand = 7(111), the result (49) -- needs 6 bits (110001) if find_rightmost(resize(u_sat, u_sat'high, out_consants_low(i), round_style => round_style_opt), '0') = integer'high + 1 then result(i) := result(i) + 1; end if; end if; end loop; return result; end function; function real_const_mult_OH( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return integer is variable aux : integer_v(constants'range) := output_high(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_high, input_low, is_signed); variable result : integer := integer'low; begin for i in aux'range loop if aux(i) > result then result := aux(i); end if; end loop; return result; end function; function fixed_from_real_constants( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return u_ufixed_v is constant max_error_pct : real := ite(max_error_pct_opt = real'low, 0.0, max_error_pct_opt); constant individual_highs : integer_v := output_high(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_high, input_low, is_signed); constant individual_lows : integer_v := output_low(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); constant result_high : integer := real_const_mult_OH(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_high, input_low, is_signed); constant result_low : integer := real_const_mult_OL(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); variable result : u_ufixed_v(1 to constants'length)(result_high downto result_low); variable constant_high, constant_low : integer; begin for i in constants'range loop --the transformation to the desired size range constant_high := individual_highs(i) - input_high; constant_low := individual_lows(i) - input_low; --assert false -- report "constant_high: " & image(constant_high) -- severity warning; --assert false -- report "constant_low: " & image(constant_low) -- severity warning; result(i) := resize(to_ufixed(constants(i), constant_high, constant_low, round_style => round_style_opt), result_high, result_low); end loop; return result; end function; /********************************************************************************************** 3 / function all_positive( vector : boolean_v) return boolean is begin for i in vector'range loop if not vector(i) then return false; end if; end loop; return true; end function; function is_positive_vector_from_constants( constants : real_v) return boolean_v is variable result : boolean_v(constants'range); begin for i in constants'range loop result(i) := constants(i) >= 0.0; end loop; return result; end function; function calculate_pre_vp_shift( mult_fixed : u_ufixed_v) return integer_v is variable result : integer_v(mult_fixed'range); begin for i in mult_fixed'range loop result(i) := -find_rightmost(mult_fixed(i), '1'); end loop; return result; end function; function calculate_mult_fundamental( mult_fixed : u_ufixed_v; pre_vp_shift : integer_v) return positive_v is variable result : positive_v(1 to mult_fixed'length); begin for i in mult_fixed'range loop result(i) := positive(to_real(scalb(mult_fixed(i), pre_vp_shift(i)))); end loop; return result; end function; /********************************************************************************************* 4 / --string used as this function should be static to work when called in synthesis and thus cannot --contain line data types(which would more flexible as the size wouldn't need to be predefined) function generate_file_name( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : positive_v) return string is constant high : integer := 60; constant low : integer := -10; variable size_for_numeric_part, actual_numeric_part_size : positive; variable accumulative : u_ufixed(high downto low) := to_ufixed(1, high, low); variable aux : u_ufixed(high downto low) := to_ufixed(1, high, low); variable result : string(1 to FILE_NAME_LENGTH); variable temporal : positive; variable counter : positive := 1; begin case round_style_opt is when fixed_round => result(counter to counter+1) := "r_"; when fixed_truncate => result(counter to counter+1) := "t_"; end case; counter := counter + 2; if round_to_bit_opt = integer'low then result(counter to counter+1) := "0_"; counter := counter + 2; elsif round_to_bit_opt > 0 then result(counter) := 'p'; --positive counter := counter + 1; temporal := integer(ceil(log10(real(round_to_bit_opt)+1))); result(counter to counter+temporal-1) := image(round_to_bit_opt); counter := counter + temporal; result(counter) := '_'; --positive counter := counter + 1; else result(counter) := 'n'; --negative counter := counter + 1; temporal := integer(ceil(log10(abs(real(round_to_bit_opt))+1))); result(counter to counter+temporal-1) := image(abs(round_to_bit_opt)); counter := counter + temporal; result(counter) := '_'; --positive counter := counter + 1; end if; size_for_numeric_part := FILE_NAME_LENGTH - counter - 4; --the total length minus the already existing part minus 4 from ".txt" for i in constants'range loop if abs(constants(i))<1 then accumulative := resize(accumulative to_ufixed(1/abs(constants(i)), high, low), accumulative); else accumulative := resize(accumulative * to_ufixed(abs(constants(i)), high, low), accumulative); end if; end loop; if max_error_pct_opt /= real'low then accumulative := resize(accumulative + to_ufixed(1000max_error_pct_opt, high, low), accumulative); end if; accumulative := resize(accumulative2*10, accumulative); for i in 1 to size_for_numeric_part loop aux := resize(aux 10.0, aux); end loop; accumulative := modulo(accumulative, aux); actual_numeric_part_size := integer(ceil(log10(to_real(accumulative)+1))); if actual_numeric_part_size < size_for_numeric_part then result(counter to counter + (size_for_numeric_part-actual_numeric_part_size) - 1) := (others => '0'); counter := counter + (size_for_numeric_part-actual_numeric_part_size); end if; result(counter to counter + actual_numeric_part_size - 1):= image(integer(to_real(accumulative))); counter := counter + actual_numeric_part_size; result(counter to counter + 3) := string'(".txt"); return result; end function; end package body;	mit
ComputerArchitectureGroupPWr/SimulationCore	src/thermometersLogic.vhd	1	6186	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity thermometersLogic is generic( termNumber : natural := 128 ); port( rsTxBusy : in std_logic; rst : in std_logic; clk50Mhz : in std_logic; clk3kHz : in std_logic; rsDataOut : out std_logic_vector(7 downto 0); rsTxStart : out std_logic; led : out std_logic_vector(7 downto 0) ); end thermometersLogic; architecture Behavioral of thermometersLogic is component DummyRO port( clk : IN std_logic; osc_out : OUT std_logic ); end component; COMPONENT toplevel PORT( clk : IN std_logic; Vccint : OUT std_logic_vector(15 downto 0); temint : OUT std_logic_vector(15 downto 0); busy : OUT std_logic; alarm : OUT std_logic ); END COMPONENT; constant THERM_NUMBER_SYSMON_Temp : integer := 2; constant THERM_NUMBER_SYSMON_Vcc : integer := 3; signal chosenTermometr : integer range 0 to termNumber; signal termometrCounter : integer range 0 to 2**16-1; type state_type is (Start, Numer, Czekaj1, Wartosc1, Czekaj2, Wartosc0); signal state, next_state : state_type; signal rsTxStart_i : std_logic; signal rsDataOut_i : std_logic_vector(7 downto 0); signal termometrRegister : std_logic_vector(15 downto 0); signal termometr : std_logic_vector(termNumber downto 0); signal termometrEnable : std_logic_vector(termNumber downto 0); signal selectedTermometr : std_logic; signal nextTerm : std_logic; signal clk3kHzD : std_logic; signal clk3kHzD2 : std_logic; signal sysmon_vcc : std_logic_vector(15 downto 0); signal sysmon_tem : std_logic_vector(15 downto 0); attribute keep : string; attribute keep of termometr : signal is "true"; attribute keep of termometrEnable : signal is "true"; attribute keep of nextTerm : signal is "true"; attribute keep of termometrRegister : signal is "true"; attribute keep of selectedTermometr : signal is "true"; attribute keep_hierarchy : string; attribute keep_hierarchy of DummyRO: component is "true"; attribute s: string; attribute s of termometr: signal is "yes"; attribute s of termometrEnable: signal is "yes"; begin Inst_toplevel: toplevel PORT MAP( clk => clk50Mhz, Vccint => sysmon_vcc, temint => sysmon_tem, busy => open, alarm => open ); led <= X"55"; Termometers: for I in 1 to termNumber generate Inst_DummyRO: DummyRO PORT MAP( osc_out => termometr(I), clk => clk50Mhz ); end generate; Termometr_Counter: process (selectedTermometr, nextTerm, clk50Mhz) begin if nextTerm = '1' and clk50Mhz = '0' then termometrCounter <= 0; elsif selectedTermometr'event and selectedTermometr = '1' then termometrCounter <= termometrCounter + 1; end if; end process; process (chosenTermometr, termometr) begin selectedTermometr <= termometr(chosenTermometr); end process; process (nextTerm, rst) begin if rst='1' then termometrRegister <= (others => '0'); elsif nextTerm'event and nextTerm = '1' then termometrRegister <= std_logic_vector(to_unsigned(termometrCounter,16)); end if; end process; Chosen_Termometr: process (clk3kHz, rst, chosenTermometr) begin if rst='1' or chosenTermometr = termNumber then chosenTermometr <= 0; termometrEnable <= (others => '0'); elsif clk3kHz='1' and clk3kHz'event then chosenTermometr <= chosenTermometr + 1; for I in 1 to termNumber loop if I = chosenTermometr+1 then termometrEnable(I) <= '1'; else termometrEnable(I) <= '0'; end if; end loop; end if; end process; Next_Term1: process (clk50Mhz) begin if clk50Mhz'event and clk50Mhz='1' then clk3kHzD <= clk3kHz; end if; end process; Next_Term2: process (clk50Mhz) begin if clk50Mhz'event and clk50Mhz='1' then clk3kHzD2 <= clk3kHzD; end if; end process; nextTerm <= (not clk3kHzD2) and clk3kHzD; Synchro: process (clk50Mhz, rst) begin if (rst = '1') then state <= Start; rsDataOut <= X"00"; rsTxStart <= '0'; else if (clk50Mhz'event and clk50Mhz = '1') then state <= next_state; rsDataOut <= rsDataOut_i; rsTxStart <= rsTxStart_i; end if; end if; end process; Output: process (state, rsTxBusy, termometrRegister, chosenTermometr) begin if (state = Numer and rsTxBusy = '0') then rsDataOut_i <= std_logic_vector(to_unsigned(chosenTermometr - 1,8)); rsTxStart_i <= '1'; elsif (state = Wartosc1 and rsTxBusy = '0') then if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then rsDataOut_i <= sysmon_tem(15 downto 8); elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then rsDataOut_i <= sysmon_vcc(15 downto 8); else rsDataOut_i <= termometrRegister(15 downto 8); end if; rsTxStart_i <= '1'; elsif (state = Wartosc0 and rsTxBusy = '0') then if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then rsDataOut_i <= sysmon_tem(7 downto 0); elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then rsDataOut_i <= sysmon_vcc(7 downto 0); else rsDataOut_i <= termometrRegister(7 downto 0); end if; rsTxStart_i <= '1'; else rsDataOut_i <= X"00"; rsTxStart_i <= '0'; end if; end process; Next_stage: process (state, rsTxBusy, nextTerm) begin next_state <= state; case (state) is when Start => if nextTerm = '1' then next_state <= Numer; end if; when Numer => if rsTxBusy = '1' then next_state <= Czekaj1; end if; when Czekaj1 => if rsTxBusy = '0' then next_state <= Wartosc1; end if; when Wartosc1 => if rsTxBusy = '1' then next_state <= Czekaj2; end if; when Czekaj2 => if rsTxBusy = '0' then next_state <= Wartosc0; end if; when Wartosc0 => if rsTxBusy = '1' then next_state <= Start; end if; when others => next_state <= Start; end case; end process; end Behavioral;	mit
benjmarshall/hls_scratchpad	hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/sim_tb/vhdl/sin_taylor_series.autotb.vhd	2	39230	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity apatb_sin_taylor_series_top is generic ( AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns; AUTOTB_TVIN_x : STRING := "./c.sin_taylor_series.autotvin_x.dat"; AUTOTB_TVIN_x_out_wrapc : STRING := "./rtl.sin_taylor_series.autotvin_x.dat"; AUTOTB_TVOUT_ap_return : STRING := "./c.sin_taylor_series.autotvout_ap_return.dat"; AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "./impl_rtl.sin_taylor_series.autotvout_ap_return.dat"; AUTOTB_LAT_RESULT_FILE : STRING := "sin_taylor_series.result.lat.rb"; AUTOTB_PER_RESULT_TRANS_FILE : STRING := "sin_taylor_series.performance.result.transaction.xml"; LENGTH_x : INTEGER := 1; LENGTH_ap_return : INTEGER := 1; AUTOTB_TRANSACTION_NUM : INTEGER := 19 ); end apatb_sin_taylor_series_top; architecture behav of apatb_sin_taylor_series_top is signal AESL_clock : STD_LOGIC := '0'; signal rst : STD_LOGIC; signal start : STD_LOGIC := '0'; signal ce : STD_LOGIC; signal continue : STD_LOGIC := '0'; signal AESL_reset : STD_LOGIC := '0'; signal AESL_start : STD_LOGIC := '0'; signal AESL_ce : STD_LOGIC := '0'; signal AESL_continue : STD_LOGIC := '0'; signal AESL_ready : STD_LOGIC := '0'; signal AESL_idle : STD_LOGIC := '0'; signal AESL_done : STD_LOGIC := '0'; signal AESL_done_delay : STD_LOGIC := '0'; signal AESL_done_delay2 : STD_LOGIC := '0'; signal AESL_ready_delay : STD_LOGIC := '0'; signal ready : STD_LOGIC := '0'; signal ready_wire : STD_LOGIC := '0'; signal x : STD_LOGIC_VECTOR (63 DOWNTO 0); signal ap_clk : STD_LOGIC; signal ap_rst : STD_LOGIC; signal ap_return : STD_LOGIC_VECTOR (63 DOWNTO 0); signal ap_done : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_ready : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0); signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0); signal ready_initial : STD_LOGIC; signal ready_initial_n : STD_LOGIC; signal ready_last_n : STD_LOGIC; signal ready_delay_last_n : STD_LOGIC; signal done_delay_last_n : STD_LOGIC; signal interface_done : STD_LOGIC := '0'; -- Subtype for random state number, to prevent confusing it with true integers -- Top of range should be (2*31)-1 but this literal calculation causes overflow on 32-bit machines subtype T_RANDINT is integer range 1 to integer'high; type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER; shared variable AESL_mLatCnterIn : latency_record; shared variable AESL_mLatCnterOut : latency_record; shared variable AESL_mLatCnterIn_addr : INTEGER; shared variable AESL_mLatCnterOut_addr : INTEGER; shared variable AESL_clk_counter : INTEGER; signal reported_stuck : STD_LOGIC := '0'; shared variable reported_stuck_cnt : INTEGER := 0; component sin_taylor_series is port ( x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_return : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); ap_done : OUT STD_LOGIC; ap_start : IN STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC); end component; -- The signal of port x shared variable AESL_REG_x : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is variable whitespace : CHARACTER; variable i : INTEGER; variable ok: BOOLEAN; variable buff: STRING(1 to token'length); begin ok := false; i := 1; loop_main: while not endfile(textfile) loop if textline = null or textline'length = 0 then readline(textfile, textline); end if; loop_remove_whitespace: while textline'length > 0 loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then read(textline, whitespace); else exit loop_remove_whitespace; end if; end loop; loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then exit loop_aesl_read_token; else read(textline, buff(i)); i := i + 1; end if; ok := true; end loop; if ok = true then exit loop_main; end if; end loop; buff(i) := ' '; token := buff; token_len:= i-1; end procedure esl_read_token; procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING) is variable i : INTEGER; begin esl_read_token (textfile, textline, token, i); end procedure esl_read_token; function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0); variable idx : integer := 3; begin ret := (others => '0'); if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then report "Error! The format of hex number is not initialed by 0x"; end if; while true loop if (data_width > 4) then case RHS(idx) is when '0' => ret := ret(data_width - 5 downto 0) & "0000"; when '1' => ret := ret(data_width - 5 downto 0) & "0001"; when '2' => ret := ret(data_width - 5 downto 0) & "0010"; when '3' => ret := ret(data_width - 5 downto 0) & "0011"; when '4' => ret := ret(data_width - 5 downto 0) & "0100"; when '5' => ret := ret(data_width - 5 downto 0) & "0101"; when '6' => ret := ret(data_width - 5 downto 0) & "0110"; when '7' => ret := ret(data_width - 5 downto 0) & "0111"; when '8' => ret := ret(data_width - 5 downto 0) & "1000"; when '9' => ret := ret(data_width - 5 downto 0) & "1001"; when 'a' \| 'A' => ret := ret(data_width - 5 downto 0) & "1010"; when 'b' \| 'B' => ret := ret(data_width - 5 downto 0) & "1011"; when 'c' \| 'C' => ret := ret(data_width - 5 downto 0) & "1100"; when 'd' \| 'D' => ret := ret(data_width - 5 downto 0) & "1101"; when 'e' \| 'E' => ret := ret(data_width - 5 downto 0) & "1110"; when 'f' \| 'F' => ret := ret(data_width - 5 downto 0) & "1111"; when 'x' \| 'X' => ret := ret(data_width - 5 downto 0) & "XXXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 4) then case RHS(idx) is when '0' => ret := "0000"; when '1' => ret := "0001"; when '2' => ret := "0010"; when '3' => ret := "0011"; when '4' => ret := "0100"; when '5' => ret := "0101"; when '6' => ret := "0110"; when '7' => ret := "0111"; when '8' => ret := "1000"; when '9' => ret := "1001"; when 'a' \| 'A' => ret := "1010"; when 'b' \| 'B' => ret := "1011"; when 'c' \| 'C' => ret := "1100"; when 'd' \| 'D' => ret := "1101"; when 'e' \| 'E' => ret := "1110"; when 'f' \| 'F' => ret := "1111"; when 'x' \| 'X' => ret := "XXXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 3) then case RHS(idx) is when '0' => ret := "000"; when '1' => ret := "001"; when '2' => ret := "010"; when '3' => ret := "011"; when '4' => ret := "100"; when '5' => ret := "101"; when '6' => ret := "110"; when '7' => ret := "111"; when 'x' \| 'X' => ret := "XXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 2) then case RHS(idx) is when '0' => ret := "00"; when '1' => ret := "01"; when '2' => ret := "10"; when '3' => ret := "11"; when 'x' \| 'X' => ret := "XX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 1) then case RHS(idx) is when '0' => ret := "0"; when '1' => ret := "1"; when 'x' \| 'X' => ret := "X"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; else report string'("Wrong data_width."); return ret; end if; idx := idx + 1; end loop; return ret; end function; function esl_str_dec2int (RHS : STRING) return INTEGER is variable ret : integer; variable idx : integer := 1; begin ret := 0; while true loop case RHS(idx) is when '0' => ret := ret 10 + 0; when '1' => ret := ret * 10 + 1; when '2' => ret := ret * 10 + 2; when '3' => ret := ret * 10 + 3; when '4' => ret := ret * 10 + 4; when '5' => ret := ret * 10 + 5; when '6' => ret := ret * 10 + 6; when '7' => ret := ret * 10 + 7; when '8' => ret := ret * 10 + 8; when '9' => ret := ret * 10 + 9; when ' ' => return ret; when others => report "Wrong dec char " & RHS(idx); return ret; end case; idx := idx + 1; end loop; return ret; end esl_str_dec2int; function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is constant str_len : integer := (lv'length + 3)/4; variable ret : STRING (1 to str_len); variable i, tmp: INTEGER; variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0); variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0); begin normal_lv := lv; for i in 1 to str_len loop if(i = 1) then if((lv'length mod 4) = 3) then tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3); case tmp_lv(2 downto 0) is when "000" => ret(i) := '0'; when "001" => ret(i) := '1'; when "010" => ret(i) := '2'; when "011" => ret(i) := '3'; when "100" => ret(i) := '4'; when "101" => ret(i) := '5'; when "110" => ret(i) := '6'; when "111" => ret(i) := '7'; when others => ret(i) := 'X'; end case; elsif((lv'length mod 4) = 2) then tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2); case tmp_lv(1 downto 0) is when "00" => ret(i) := '0'; when "01" => ret(i) := '1'; when "10" => ret(i) := '2'; when "11" => ret(i) := '3'; when others => ret(i) := 'X'; end case; elsif((lv'length mod 4) = 1) then tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1); case tmp_lv(0 downto 0) is when "0" => ret(i) := '0'; when "1" => ret(i) := '1'; when others=> ret(i) := 'X'; end case; elsif((lv'length mod 4) = 0) then tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4); case tmp_lv(3 downto 0) is when "0000" => ret(i) := '0'; when "0001" => ret(i) := '1'; when "0010" => ret(i) := '2'; when "0011" => ret(i) := '3'; when "0100" => ret(i) := '4'; when "0101" => ret(i) := '5'; when "0110" => ret(i) := '6'; when "0111" => ret(i) := '7'; when "1000" => ret(i) := '8'; when "1001" => ret(i) := '9'; when "1010" => ret(i) := 'a'; when "1011" => ret(i) := 'b'; when "1100" => ret(i) := 'c'; when "1101" => ret(i) := 'd'; when "1110" => ret(i) := 'e'; when "1111" => ret(i) := 'f'; when others => ret(i) := 'X'; end case; end if; else tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4); case tmp_lv(3 downto 0) is when "0000" => ret(i) := '0'; when "0001" => ret(i) := '1'; when "0010" => ret(i) := '2'; when "0011" => ret(i) := '3'; when "0100" => ret(i) := '4'; when "0101" => ret(i) := '5'; when "0110" => ret(i) := '6'; when "0111" => ret(i) := '7'; when "1000" => ret(i) := '8'; when "1001" => ret(i) := '9'; when "1010" => ret(i) := 'a'; when "1011" => ret(i) := 'b'; when "1100" => ret(i) := 'c'; when "1101" => ret(i) := 'd'; when "1110" => ret(i) := 'e'; when "1111" => ret(i) := 'f'; when others => ret(i) := 'X'; end case; end if; end loop; return ret; end function; -- purpose: initialise the random state variable based on an integer seed function init_rand(seed : integer) return T_RANDINT is variable result : T_RANDINT; begin -- If the seed is smaller than the minimum value of the random state variable, use the minimum value if seed < T_RANDINT'low then result := T_RANDINT'low; -- If the seed is larger than the maximum value of the random state variable, use the maximum value elsif seed > T_RANDINT'high then result := T_RANDINT'high; -- If the seed is within the range of the random state variable, just use the seed else result := seed; end if; -- Return the result return result; end init_rand; -- purpose: generate a random integer between min and max limits procedure rand_int(variable rand : inout T_RANDINT; constant minval : in integer; constant maxval : in integer; variable result : out integer ) is variable k, q : integer; variable real_rand : real; variable res : integer; begin -- Create a new random integer in the range 1 to 2*31-1 and put it back into rand VARIABLE -- Based on an example from Numerical Recipes in C, 2nd Edition, page 279 k := rand/127773; q := 16807(rand-k127773)-2836k; if q < 0 then q := q + 2147483647; end if; rand := init_rand(q); -- Convert this integer to a real number in the range 0 to 1 real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low); -- Convert this real number to an integer in the range minval to maxval -- The +1 and -0.5 are to get equal probability of minval and maxval as other values res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval; -- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this if res < minval then res := minval; elsif res > maxval then res := maxval; end if; -- assign output result := res; end rand_int; function esl_equal_std_lv (lv1 : STD_LOGIC_VECTOR; lv2 : STD_LOGIC_VECTOR) return BOOLEAN is variable len : INTEGER; variable i : INTEGER; begin if (lv1'length > lv2'length) then len := lv2'length; for i in lv1'length - 1 downto lv2'length loop if(lv1(i) = '1') then return false; end if; end loop; else len := lv1'length; for i in lv2'length - 1 downto lv1'length loop if(lv2(i) = '1') then return false; end if; end loop; end if; for i in len - 1 downto 0 loop if (lv1(i) = '1' and lv2(i) /= '1') or (lv1(i) = '0' and lv2(i) /= '0') then return false; end if; end loop; return true; end function; procedure post_check (file fp1 : TEXT; file fp2 : TEXT) is variable token_line1 : LINE; variable token_line2 : LINE; variable token1 : STRING(1 to 152); variable token2 : STRING(1 to 152); variable golden : STD_LOGIC_VECTOR(151 downto 0); variable result : STD_LOGIC_VECTOR(151 downto 0); variable l1 : INTEGER; variable l2 : INTEGER; begin esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); if(token1(1 to 13) /= "[[[runtime]]]" or token2(1 to 13) /= "[[[runtime]]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); while(token1(1 to 14) /= "[[[/runtime]]]" and token2(1 to 14) /= "[[[/runtime]]]") loop if(token1(1 to 15) /= "[[transaction]]" and token2(1 to 15) /= "[[transaction]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp1, token_line1, token1); -- Skip transaction number esl_read_token(fp2, token_line2, token2); -- Skip transaction number esl_read_token(fp1, token_line1, token1, l1); esl_read_token(fp2, token_line2, token2, l2); while(token1(1 to 16) /= "[[/transaction]]" and token2(1 to 16) /= "[[/transaction]]") loop golden := esl_str2lv_hex(token1, 152 ); result := esl_str2lv_hex(token2, 152 ); if(esl_equal_std_lv(golden, result) = false) then report token1(1 to l1) & " (expected) vs. " & token2(1 to l2) & " (actual) - mismatch"; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); end loop; esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); end loop; end procedure post_check; begin AESL_inst_sin_taylor_series : sin_taylor_series port map ( x => x, ap_clk => ap_clk, ap_rst => ap_rst, ap_return => ap_return, ap_done => ap_done, ap_start => ap_start, ap_ready => ap_ready, ap_idle => ap_idle ); -- Assignment for control signal ap_clk <= AESL_clock; ap_rst <= AESL_reset; AESL_reset <= rst; AESL_done <= ap_done; ap_start <= AESL_start; AESL_start <= start; AESL_ready <= ap_ready; AESL_idle <= ap_idle; AESL_ce <= ce; AESL_continue <= continue; gen_check_strlSignal_AESL_done_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then NULL; else if ( AESL_done /= '1' and AESL_done /= '0' ) then assert false report "Control signal AESL_done is invalid!" severity failure; end if; end if; end if; end process; gen_check_strlSignal_AESL_ready_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then NULL; else if ( AESL_ready /= '1' and AESL_ready /= '0' ) then assert false report "Control signal AESL_ready is invalid!" severity failure; end if; end if; end if; end process; gen_assign_x_proc : process begin wait until (AESL_clock'event and AESL_clock = '1'); wait for 0.45 ns; x <= AESL_REG_x; end process; read_file_process_x : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 152); variable i : INTEGER; variable transaction_finish : INTEGER; variable transaction_idx : INTEGER:= 0; variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin wait until AESL_reset = '0'; file_open(fstatus, fp, AUTOTB_TVIN_x, READ_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVIN_x & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp, token_line, token); if(token(1 to 13) /= "[[[runtime]]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp, token_line, token); while(token(1 to 14) /= "[[[/runtime]]]") loop if(token(1 to 15) /= "[[transaction]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp, token_line, token); -- Skip transaction number esl_read_token(fp, token_line, token); wait for 0.2 ns; while(ready_wire /= '1') loop wait until AESL_clock'event and AESL_clock = '1'; wait for 0.2 ns; end loop; if(token(1 to 16) /= "[[/transaction]]") then AESL_REG_x := esl_str2lv_hex(token, 64 ); esl_read_token(fp, token_line, token); end if; wait until AESL_clock'event and AESL_clock = '1'; esl_read_token(fp, token_line, token); end loop; file_close(fp); wait; end process; write_file_process_ap_return : process file fp : TEXT; file fp_size : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 152); variable str : STRING(1 to 40); variable transaction_idx : INTEGER; variable ap_return_count : INTEGER; variable hls_stream_size : INTEGER; variable i : INTEGER; variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin wait until AESL_reset = '0'; file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); transaction_idx := 0; while (transaction_idx /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; while(AESL_done /= '1') loop wait until AESL_clock'event and AESL_clock = '1'; end loop; write(token_line, string'("[[transaction]] ") & integer'image(transaction_idx)); writeline(fp, token_line); write(token_line, "0x" & esl_conv_string_hex(ap_return)); writeline(fp, token_line); transaction_idx := transaction_idx + 1; write(token_line, string'("[[/transaction]]")); writeline(fp, token_line); end loop; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; generate_ready_cnt_proc : process(ready_initial, AESL_clock) begin if(AESL_clock'event and AESL_clock = '0') then if(ready_initial = '1') then ready_cnt <= conv_std_logic_vector(1, 32); end if; elsif(AESL_clock'event and AESL_clock = '1') then if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then if(AESL_ready = '1') then ready_cnt <= ready_cnt + 1; end if; end if; end if; end process; generate_done_cnt_proc : process(AESL_reset, AESL_clock) begin if(AESL_reset = '1') then done_cnt <= (others => '0'); elsif(AESL_clock'event and AESL_clock = '1') then if(done_cnt /= AUTOTB_TRANSACTION_NUM) then if(AESL_done = '1') then done_cnt <= done_cnt + 1; end if; end if; end if; end process; generate_sim_done_proc : process file fp1 : TEXT; file fp2 : TEXT; variable fstatus1 : FILE_OPEN_STATUS; variable fstatus2 : FILE_OPEN_STATUS; begin while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus1, fp1, "./rtl.sin_taylor_series.autotvout_ap_return.dat", READ_MODE); file_open(fstatus2, fp2, "./impl_rtl.sin_taylor_series.autotvout_ap_return.dat", READ_MODE); if(fstatus1 /= OPEN_OK) then assert false report string'("Open file rtl.sin_taylor_series.autotvout_ap_return.dat failed!!!") severity note; elsif(fstatus2 /= OPEN_OK) then assert false report string'("Open file impl_rtl.sin_taylor_series.autotvout_ap_return.dat failed!!!") severity note; else report string'("Comparing rtl.sin_taylor_series.autotvout_ap_return.dat with impl_rtl.sin_taylor_series.autotvout_ap_return.dat"); post_check(fp1, fp2); end if; file_close(fp1); file_close(fp2); report "Simulation Passed."; assert false report "simulation done!" severity note; assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure; wait; end process; gen_clock_proc : process begin AESL_clock <= '0'; while(true) loop wait for AUTOTB_CLOCK_PERIOD_DIV2; AESL_clock <= not AESL_clock; end loop; wait; end process; gen_reset_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin rst <= '1'; wait for 100 ns; for i in 1 to 3 loop wait until AESL_clock'event and AESL_clock = '1'; end loop; rst <= '0'; wait; end process; gen_start_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin start <= '0'; ce <= '1'; wait until AESL_reset = '0'; wait until (AESL_clock'event and AESL_clock = '1'); start <= '1'; while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop wait until (AESL_clock'event and AESL_clock = '1'); if(AESL_ready = '1') then start <= '0'; start <= '1'; end if; end loop; start <= '0'; wait; end process; gen_continue_proc : process(AESL_done) begin continue <= AESL_done; end process; gen_AESL_ready_delay_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_ready_delay <= '0'; else AESL_ready_delay <= AESL_ready; end if; end if; end process; gen_ready_initial_proc : process begin ready_initial <= '0'; wait until AESL_start = '1'; ready_initial <= '1'; wait until AESL_clock'event and AESL_clock = '1'; ready_initial <= '0'; wait; end process; ready_last_n_proc : process begin ready_last_n <= '1'; while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; end loop; ready_last_n <= '0'; wait; end process; gen_ready_delay_n_last_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then ready_delay_last_n <= '0'; else ready_delay_last_n <= ready_last_n; end if; end if; end process; ready <= (ready_initial or AESL_ready_delay); ready_wire <= ready_initial or AESL_ready_delay; done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1'; gen_done_delay_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_done_delay <= '0'; AESL_done_delay2 <= '0'; else AESL_done_delay <= AESL_done and done_delay_last_n; AESL_done_delay2 <= AESL_done_delay; end if; end if; end process; gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay) begin if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then interface_done <= AESL_ready_delay; elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then interface_done <= AESL_done_delay; else interface_done <= '0'; end if; end process; gen_clock_counter_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '0') then if(AESL_reset = '1') then AESL_clk_counter := 0; else AESL_clk_counter := AESL_clk_counter + 1; end if; end if; end process; gen_mLatcnterout_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_mLatCnterOut_addr := 0; AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ; reported_stuck_cnt := 0; else if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter; AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1; reported_stuck <= '0'; elsif (reported_stuck = '0' and reported_stuck_cnt < 4) then if ( AESL_mLatCnterIn_addr > AESL_mLatCnterOut_addr ) then if ( AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10000 and AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10 * 1156 ) then report "WARNING: The latency is much larger than expected. Simulation may stuck."; reported_stuck <= '1'; reported_stuck_cnt := reported_stuck_cnt + 1; end if; end if; end if; end if; end if; end process; gen_mLatcnterin_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_mLatCnterIn_addr := 0; else if (AESL_start = '1' and AESL_mLatCnterIn_addr = 0) then AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter; AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1; elsif (AESL_ready = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1 ) then AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter; AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1; end if; end if; end if; end process; gen_performance_check_proc : process variable transaction_counter : INTEGER; variable i : INTEGER; file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); variable latthistime : INTEGER; variable lattotal : INTEGER; variable latmax : INTEGER; variable latmin : INTEGER; variable thrthistime : INTEGER; variable thrtotal : INTEGER; variable thrmax : INTEGER; variable thrmin : INTEGER; variable lataver : INTEGER; variable thraver : INTEGER; type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER; variable lat_array : latency_record; variable thr_array : latency_record; begin i := 0; lattotal := 0; latmax := 0; latmin := 16#7fffffff#; lataver := 0; thrtotal := 0; thrmax := 0; thrmin := 16#7fffffff#; thraver := 0; wait until (AESL_clock'event and AESL_clock = '1'); wait until (AESL_reset = '0'); while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until (AESL_clock'event and AESL_clock = '1'); end loop; wait for 0.001 ns; for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i); lat_array(i) := latthistime; if (latthistime > latmax) then latmax := latthistime; end if; if (latthistime < latmin) then latmin := latthistime; end if; lattotal := lattotal + latthistime; if (AUTOTB_TRANSACTION_NUM = 1) then thrthistime := latthistime; else thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i); end if; thr_array(i) := thrthistime; if (thrthistime > thrmax) then thrmax := thrthistime; end if; if (thrthistime < thrmin) then thrmin := thrthistime; end if; thrtotal := thrtotal + thrthistime; end loop; lataver := lattotal / AUTOTB_TRANSACTION_NUM; thraver := thrtotal / AUTOTB_TRANSACTION_NUM; file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE); if (fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; if (AUTOTB_TRANSACTION_NUM = 1) then thrmax := 0; thrmin := 0; thraver := 0; write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"'); writeline(fp, token_line); write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"'); writeline(fp, token_line); else write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"'); writeline(fp, token_line); write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"'); writeline(fp, token_line); end if; file_close(fp); file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line,string'(" latency interval")); writeline(fp, token_line); if (AUTOTB_TRANSACTION_NUM = 1) then i := 0; thr_array(i) := 0; write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) ); writeline(fp, token_line); else for i in 0 to AESL_mLatCnterOut_addr - 1 loop write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) ); writeline(fp, token_line); end loop; end if; file_close(fp); wait; end process; end behav;	mit
APastorG/APG	adder/adder_u.vhd	1	4647	/************************************************************************************************* / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Vivado by Xilinx / A 3 space tab is used throughout the document / / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This is the interface between the instantiation of an adder an its core. It exists to make it / possible to use external std_ulogic_vector which contain the numeric values while having modules / which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed). / As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer / range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed / a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is / adopted where the integer indexes of the fixed point types are moved to the natural space with a / transformation. This consists in limiting the indexes of the fixed point data to +-230 and / adding 230 to obtain the std_ulogic_vector's indexes. [-230, 230]->[0, 231]. For example, / fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector / Additionally, the generics' consistency and correctness are checked in here. / *************************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.adder_pkg.all; use work.fixed_generic_pkg.all; /================================================================================================/ /================================================================================================/ /================================================================================================/ entity adder_u is generic( DATA_IMM_AFTER_START_opt : boolean := false; --default SPEED_opt : T_speed := t_min; --exception: value not set MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set S : positive --compulsory ); port( input : in u_ufixed_v; clk : in std_ulogic; start : in std_ulogic; valid_input : in std_ulogic; output : out u_ufixed; --unconstrained array valid_output : out std_ulogic ); end entity; /================================================================================================/ /================================================================================================/ /================================================================================================/ architecture adder_u1 of adder_u is constant P : positive := input'length(1); constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt, S, P, input(1)'high, input(1)'low); /================================================================================================/ /================================================================================================*/ begin adder_core_u_1: entity work.adder_core_u generic map( DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt, SPEED_opt => SPEED_opt, MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt, S => S, P => P, input_high => input(1)'high, input_low => input(1)'low ) port map( clk => clk, input => input, valid_input => valid_input, start => start, output => output, valid_output => valid_output ); end architecture;	mit
223323/lab2	HDL/source/coregen/dcm75MHz.vhd	1	6526	-- file: dcm75MHz.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- User entered comments ------------------------------------------------------------------------------ -- None -- ------------------------------------------------------------------------------ -- "Output Output Phase Duty Pk-to-Pk Phase" -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------ -- CLK_OUT1____75.000______0.000______50.0______466.666____150.000 -- ------------------------------------------------------------------------------ -- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------ -- __primary______________27____________0.010 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity dcm75MHz is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic; -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end dcm75MHz; architecture xilinx of dcm75MHz is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm75MHz,clk_wiz_v3_6,{component_name=dcm75MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering signal clkfb : std_logic; signal clk0 : std_logic; signal clkfx : std_logic; signal clkfbout : std_logic; signal locked_internal : std_logic; signal status_internal : std_logic_vector(7 downto 0); begin -- Input buffering -------------------------------------- clkin1_buf : IBUFG port map (O => clkin1, I => CLK_IN1); -- Clocking primitive -------------------------------------- -- Instantiation of the DCM primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused dcm_sp_inst: DCM_SP generic map (CLKDV_DIVIDE => 2.000, CLKFX_DIVIDE => 9, CLKFX_MULTIPLY => 25, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 37.037, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "1X", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map -- Input clock (CLKIN => clkin1, CLKFB => clkfb, -- Output clocks CLK0 => clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLKFX => clkfx, CLKFX180 => open, CLKDV => open, -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => open, -- Other control and status signals LOCKED => locked_internal, STATUS => status_internal, RST => RESET, -- Unused pin, tie low DSSEN => '0'); LOCKED <= locked_internal; -- Output buffering ------------------------------------- clkf_buf : BUFG port map (O => clkfb, I => clk0); clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkfx); end xilinx;	mit
APastorG/APG	adder/adder.vhd	1	7644	/************************************************************************************************* / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Vivado by Xilinx / A 3 space tab is used throughout the document / / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This is the interface between the instantiation of an adder an its core. It exists to make it / possible to use external std_ulogic_vector which contain the numeric values while having modules / which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed). / As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer / range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed / a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is / adopted where the integer indexes of the fixed point types are moved to the natural space with a / transformation. This consists in limiting the indexes of the fixed point data to +-230 and / adding 230 to obtain the std_ulogic_vector's indexes. [-230, 230]->[0, 231]. For example, / fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector / Additionally, the generics' consistency and correctness are checked in here. / *************************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.adder_pkg.all; use work.fixed_generic_pkg.all; /================================================================================================/ /================================================================================================/ /================================================================================================/ entity adder is generic( UNSIGNED_2COMP_opt : boolean := false; --default DATA_IMM_AFTER_START_opt : boolean := false; --default SPEED_opt : T_speed := t_min; --exception: value not set MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set S : positive --compulsory ); port( input : in sulv_v; --unconstrained array clk : in std_ulogic; start : in std_ulogic; valid_input : in std_ulogic; output : out std_ulogic_vector; --unconstrained array valid_output : out std_ulogic ); end entity; /================================================================================================/ /================================================================================================/ /================================================================================================/ architecture adder_1 of adder is constant P : positive := input'length(1); constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt, S, P, input(1)'high-SULV_NEW_ZERO, input(1)'low-SULV_NEW_ZERO); constant NORM_IN_HIGH : integer := input(1)'high-SULV_NEW_ZERO; constant NORM_IN_LOW : integer := input(1)'low-SULV_NEW_ZERO; constant NORM_OUT_HIGH : integer := adder_OH(MAX_POSSIBLE_BIT_opt, S, P, NORM_IN_HIGH); constant NORM_OUT_LOW : integer := adder_OL(TRUNCATE_TO_BIT_opt, NORM_IN_LOW); constant OUT_HIGH : natural := NORM_OUT_HIGH + SULV_NEW_ZERO; constant OUT_LOW : natural := NORM_OUT_LOW + SULV_NEW_ZERO; signal aux_input_s : u_sfixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW); signal aux_output_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW); signal aux_input_u : u_ufixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW); signal aux_output_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW); /================================================================================================/ /================================================================================================*/ begin msg_debug("adder_NORM_IN_HIGH: " & image(NORM_IN_HIGH)); msg_debug("adder_NORM_IN_LOW: " & image(NORM_IN_LOW)); msg_debug("adder_NORM_OUT_HIGH: " & image(NORM_OUT_HIGH)); msg_debug("adder_NORM_OUT_LOW: " & image(NORM_OUT_LOW)); msg_debug("adder_OUT_HIGH: " & image(OUT_HIGH)); msg_debug("adder_OUT_LOW: " & image(OUT_LOW)); msg_debug("adder_UNSIGNED_2COMP_opt: " & image(UNSIGNED_2COMP_opt)); adder_selection: if UNSIGNED_2COMP_opt generate begin generate_input: for i in 1 to P generate begin aux_input_u(i) <= to_ufixed(unsigned(input(i)), aux_input_u(i)); end; end generate; output(OUT_HIGH downto OUT_LOW) <= to_sulv(aux_output_u); adder_u_1: entity work.adder_u generic map( DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt, SPEED_opt => SPEED_opt, MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt, S => S ) port map( clk => clk, input => aux_input_u, valid_input => valid_input, start => start, output => aux_output_u, valid_output => valid_output ); end; else generate begin generate_input: for i in 1 to P generate begin aux_input_s(i) <= to_sfixed(signed(input(i)), aux_input_s(i)); end; end generate; output(OUT_HIGH downto OUT_LOW) <= to_sulv(aux_output_s); adder_s_1: entity work.adder_s generic map( DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt, SPEED_opt => SPEED_opt, MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt, S => S ) port map( clk => clk, input => aux_input_s, valid_input => valid_input, start => start, output => aux_output_s, valid_output => valid_output ); end; end generate; end architecture;	mit
benjmarshall/hls_scratchpad	hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_seriescud.vhd	4	2551	-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity sin_taylor_seriescud is generic ( ID : integer := 5; NUM_STAGE : integer := 6; din0_WIDTH : integer := 32; dout_WIDTH : integer := 64 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of sin_taylor_seriescud is --------------------- Component --------------------- component sin_taylor_series_ap_sitodp_4_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(63 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(63 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- sin_taylor_series_ap_sitodp_4_no_dsp_32_u : component sin_taylor_series_ap_sitodp_4_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; end if; end if; end process; end architecture;	mit
APastorG/APG	adder/adder_core_s.vhd	1	30691	/************************************************************************************************* / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Vivado by Xilinx / A 3 space tab is used throughout the document / / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This is a design of a parameterized adder which allows the addition of signed numbers / with high fexibility and control over the way data is introduced and the level of pipelining it / will be used / ┌ ┌───────┐ / │ │ i e a │ / input: P│ │ j f b │ _______ / │ │ k g c │ ----> \| adder \| ----> result / │ │ l h d │ ─────── / └ └───────┘ / └───────┘ / S / The clock cycles it takes to produce a result from the input can also be specified with the / SPEED_opt parameter. The higher this parameter, the shorter, in general, the delay path / between each register and thus, the higher the frequency the design is able to reach. / ***********************************************************************************************/ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.math_real.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.adder_pkg.all; use work.counter_pkg.all; use work.fixed_generic_pkg.all; /================================================================================================/ /================================================================================================/ /================================================================================================/ entity adder_core_s is generic( DATA_IMM_AFTER_START_opt : boolean := false; --default SPEED_opt : T_speed := t_min; --exception: value not set MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set S : positive; --compulsory P : positive; --compulsory input_high : integer; input_low : integer ); port( input : in u_sfixed_v(1 to P); --unconstrained array clk : in std_ulogic; start : in std_ulogic; valid_input : in std_ulogic; output : out u_sfixed(adder_OH(MAX_POSSIBLE_BIT_opt, S, P, input_high) downto adder_OL(TRUNCATE_TO_BIT_opt, input_low) ); valid_output : out std_ulogic ); end entity; /================================================================================================/ /================================================================================================/ /================================================================================================/ architecture adder_core_s_1 of adder_core_s is / corrected generics and internal/external ports' sizes / /************************************************************************************************/ constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt, S, P, input(1)'high, input(1)'low); constant DATA_WIDTH : positive := input(1)'length; constant DATA_HIGH : integer := input(1)'high; constant DATA_LOW : integer := input(1)'low; constant OUTPUT_HIGH : integer := adder_OH(MAX_POSSIBLE_BIT_opt, S, P, DATA_HIGH); constant OUTPUT_LOW : integer := adder_OL(TRUNCATE_TO_BIT_opt, DATA_LOW); constant DATA_IMM_AFTER_START : boolean := DATA_IMM_AFTER_START_opt; constant MAX_POSSIBLE_BIT : integer := ite(MAX_POSSIBLE_BIT_opt=integer'low, integer'high - SULV_NEW_ZERO, MAX_POSSIBLE_BIT_opt); constant ADD_LEVELS : positive := 1 + log2ceil(P); constant PIPELINE_POSITIONS : natural := ite(S = 1, ADD_LEVELS, ADD_LEVELS + 1); constant PIPELINES_2_INTRODUCE : natural := number_of_pipelines(PIPELINE_POSITIONS, SPEED_opt); constant CONDITION_EXC : boolean := (not DATA_IMM_AFTER_START) and ((S = 1 and PIPELINES_2_INTRODUCE=0) or PIPELINES_2_INTRODUCE < 2); function is_pipelines_exc( s : positive; pipeline_positions : natural) return boolean_v is variable result : boolean_v(1 to pipeline_positions) := (others => false); begin result(ite(s = 1, pipeline_positions, pipeline_positions-1)) := true; return result; end function; constant IS_PIPELINED_EXC : boolean_v := is_pipelines_exc(S, PIPELINE_POSITIONS); constant IS_PIPELINED : boolean_v := ite(CONDITION_EXC, IS_PIPELINED_EXC, generate_pipelines(PIPELINE_POSITIONS, SPEED_opt) ); constant OUTPUT_BUFFER : boolean := ite(S = 1, false, ite(CONDITION_EXC, false, IS_PIPELINED(PIPELINE_POSITIONS)) ); constant ACC_PIPELINES : natural := S - 1; constant ADD_PIPELINES : natural := ite(CONDITION_EXC, 1, PIPELINES_2_INTRODUCE - ite(OUTPUT_BUFFER, 1, 0) ); constant PIPELINES : natural := ADD_PIPELINES + ACC_PIPELINES + ite(OUTPUT_BUFFER, 1, 0); / other constants / /************************************************************************************************/ constant INTER_HIGH : integer := minimum(DATA_HIGH + log2ceil(P), MAX_POSSIBLE_BIT); / data signals / /************************************************************************************************/ signal input_resolved : sfixed_v(1 to P)(input(1)'range); --where the input is converted to resolved signal inter : u_sfixed(INTER_HIGH downto DATA_LOW); signal output_inter : u_sfixed(OUTPUT_HIGH downto DATA_LOW); signal start_sh : std_ulogic_vector(1 to ADD_PIPELINES); signal valid_input_sh : std_ulogic_vector(1 to ADD_PIPELINES); / control signals / /************************************************************************************************/ signal start_delayed : std_ulogic; signal valid_input_delayed : std_ulogic; signal counter_out : std_ulogic; / structures to store and manipulate data of the adder tree (ADD) / /************************************************************************************************/ function T_ADD_state_data_high( index : natural) return integer is begin if DATA_HIGH+index > MAX_POSSIBLE_BIT then return MAX_POSSIBLE_BIT; else return DATA_HIGH + index; end if; end function; type T_ADD_state is record level0 : sfixed_v(1 to signals_per_level(P, 0 ))(T_ADD_state_data_high(0) downto DATA_LOW); level1 : sfixed_v(1 to signals_per_level(P, 1 ))(T_ADD_state_data_high(1) downto DATA_LOW); level2 : sfixed_v(1 to signals_per_level(P, 2 ))(T_ADD_state_data_high(2) downto DATA_LOW); level3 : sfixed_v(1 to signals_per_level(P, 3 ))(T_ADD_state_data_high(3) downto DATA_LOW); level4 : sfixed_v(1 to signals_per_level(P, 4 ))(T_ADD_state_data_high(4) downto DATA_LOW); level5 : sfixed_v(1 to signals_per_level(P, 5 ))(T_ADD_state_data_high(5) downto DATA_LOW); level6 : sfixed_v(1 to signals_per_level(P, 6 ))(T_ADD_state_data_high(6) downto DATA_LOW); level7 : sfixed_v(1 to signals_per_level(P, 7 ))(T_ADD_state_data_high(7) downto DATA_LOW); level8 : sfixed_v(1 to signals_per_level(P, 8 ))(T_ADD_state_data_high(8) downto DATA_LOW); level9 : sfixed_v(1 to signals_per_level(P, 9 ))(T_ADD_state_data_high(9) downto DATA_LOW); level10 : sfixed_v(1 to signals_per_level(P, 10))(T_ADD_state_data_high(10)downto DATA_LOW); level11 : sfixed_v(1 to signals_per_level(P, 11))(T_ADD_state_data_high(11)downto DATA_LOW); end record; -- in Vivado and ModelSim -- this constant is used because even driving only one member of a structure implies driving the -- whole structure. So with resolved signals the analysis takes places without problems and the -- subsequent synthesis generates the desired structure. constant ADD_Z : T_ADD_state:=(level0 => (others=>(others=>'Z')), level1 => (others=>(others=>'Z')), level2 => (others=>(others=>'Z')), level3 => (others=>(others=>'Z')), level4 => (others=>(others=>'Z')), level5 => (others=>(others=>'Z')), level6 => (others=>(others=>'Z')), level7 => (others=>(others=>'Z')), level8 => (others=>(others=>'Z')), level9 => (others=>(others=>'Z')), level10 => (others=>(others=>'Z')), level11 => (others=>(others=>'Z'))); -- ADD_in stores the signals entering the levels of the adder tree -- ADD_out stores the signals leaving signal ADD_in : T_ADD_state := ADD_Z; signal ADD_out : T_ADD_state := ADD_Z; / functions to read and procedures to write from/to T_ADD_state / /************************************************************************************************/ function T_ADD_state_read( state : T_ADD_state; level : natural) return sfixed_v is begin case level is when 0 => return state.level0; when 1 => return state.level1; when 2 => return state.level2; when 3 => return state.level3; when 4 => return state.level4; when 5 => return state.level5; when 6 => return state.level6; when 7 => return state.level7; when 8 => return state.level8; when 9 => return state.level9; when 10 => return state.level10; when others => return state.level11; end case; end function; function T_ADD_state_read( state : T_ADD_state; level : natural; signal_number : integer) return u_sfixed is begin case level is when 0 => return state.level0(signal_number); when 1 => return state.level1(signal_number); when 2 => return state.level2(signal_number); when 3 => return state.level3(signal_number); when 4 => return state.level4(signal_number); when 5 => return state.level5(signal_number); when 6 => return state.level6(signal_number); when 7 => return state.level7(signal_number); when 8 => return state.level8(signal_number); when 9 => return state.level9(signal_number); when 10 => return state.level10(signal_number); when others => return state.level11(signal_number); end case; end function; procedure T_ADD_state_write( signal state : inout T_ADD_state; constant level : in natural; constant new_value : in sfixed_v) is begin --for loop introduced because of obscure error in Active-HDL: --Error DAGGEN_0700: Fatal error : INTERNAL CODE GENERATOR ERROR for i in new_value'range loop case level is when 0 => state.level0(i) <= new_value(i); when 1 => state.level1(i) <= new_value(i); when 2 => state.level2(i) <= new_value(i); when 3 => state.level3(i) <= new_value(i); when 4 => state.level4(i) <= new_value(i); when 5 => state.level5(i) <= new_value(i); when 6 => state.level6(i) <= new_value(i); when 7 => state.level7(i) <= new_value(i); when 8 => state.level8(i) <= new_value(i); when 9 => state.level9(i) <= new_value(i); when 10 => state.level10(i) <= new_value(i); when others => state.level11(i) <= new_value(i); end case; end loop; end procedure; procedure T_ADD_state_write( signal state : inout T_ADD_state; constant level : in natural; constant signal_number : in integer; constant new_value : in sfixed) is begin case level is when 0 => state.level0(signal_number) <= new_value; when 1 => state.level1(signal_number) <= new_value; when 2 => state.level2(signal_number) <= new_value; when 3 => state.level3(signal_number) <= new_value; when 4 => state.level4(signal_number) <= new_value; when 5 => state.level5(signal_number) <= new_value; when 6 => state.level6(signal_number) <= new_value; when 7 => state.level7(signal_number) <= new_value; when 8 => state.level8(signal_number) <= new_value; when 9 => state.level9(signal_number) <= new_value; when 10 => state.level10(signal_number) <= new_value; when others => state.level11(signal_number) <= new_value; end case; end procedure; procedure T_ADD_state_copy( signal from_state : in T_ADD_state; signal to_state : inout T_ADD_state; constant level : in natural) is begin case level is when 0 => to_state.level0 <= from_state.level0; when 1 => to_state.level1 <= from_state.level1; when 2 => to_state.level2 <= from_state.level2; when 3 => to_state.level3 <= from_state.level3; when 4 => to_state.level4 <= from_state.level4; when 5 => to_state.level5 <= from_state.level5; when 6 => to_state.level6 <= from_state.level6; when 7 => to_state.level7 <= from_state.level7; when 8 => to_state.level8 <= from_state.level8; when 9 => to_state.level9 <= from_state.level9; when 10 => to_state.level10 <= from_state.level10; when others => to_state.level11 <= from_state.level11; end case; end procedure; /================================================================================================/ /================================================================================================/ begin msg_debug("adder_core_s : OUTPUT_HIGH: " & image(OUTPUT_HIGH)); msg_debug("adder_core_s : OUTPUT_LOW: " & image(OUTPUT_LOW)); msg_debug("adder_core_s : DATA_HIGH: " & image(DATA_HIGH)); msg_debug("adder_core_s : DATA_LOW: " & image(DATA_LOW)); msg_debug("adder_core_s : MAX_POSSIBLE_BIT_opt: " & image(MAX_POSSIBLE_BIT_opt)); msg_debug("adder_core_s : MAX_POSSIBLE_BIT: " & image(MAX_POSSIBLE_BIT)); / Introduction of the input to the ADD structure, and extraction of the signal inter from it / /************************************************************************************************/ generate_input_resolved_signal: for i in 1 to P generate begin input_resolved(i) <= input(i); end; end generate; T_ADD_state_write(ADD_in, 0, input_resolved); inter <= T_ADD_state_read(ADD_out, ADD_LEVELS-1, 1); / Generation and management of the control signals / /************************************************************************************************/ generate_start_control: if ADD_PIPELINES>0 generate begin start_delayed <= start_sh(ADD_PIPELINES); process (clk) is begin if rising_edge(clk) then start_sh(1) <= start; if ADD_PIPELINES>1 then start_sh(2 to ADD_PIPELINES) <= start_sh(1 to ADD_PIPELINES-1); end if; end if; end process; end; else generate begin start_delayed <= start; end; end generate; generate_valid_input_control: if DATA_IMM_AFTER_START=false generate begin when_ADD_PIPELINES_is_0: if ADD_PIPELINES=0 generate begin valid_input_delayed<= valid_input; end; else generate begin valid_input_delayed <= valid_input_sh(ADD_PIPELINES); process (clk) is begin if rising_edge(clk) then valid_input_sh(1) <= valid_input; if ADD_PIPELINES>1 then valid_input_sh(2 to ADD_PIPELINES) <= valid_input_sh(1 to ADD_PIPELINES-1); end if; end if; end process; end; end generate; end; end generate; when_ACC_PIPELINES_greater_than_0: if S>1 generate begin generate_counter: if DATA_IMM_AFTER_START generate signal aux : std_ulogic; signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt, 0, --COUNTER_WIDTH_dep, true, --TARGET_MODE, ACC_PIPELINES, --TARGET_dep, true, --TARGET_WITH_COUNT_opt = t_true, true, --USE_SET, 1) --SET_TO_dep) downto 1); begin aux <= unsigned(count) ?/= 0; counter: entity work.counter generic map( UNSIGNED_2COMP_opt => true, OVERFLOW_BEHAVIOR_opt => t_wrap, --COUNT_MODE_opt => t_up, --COUNTER_WIDTH_dep => , TARGET_MODE => true, TARGET_dep => ACC_PIPELINES, TARGET_WITH_COUNT_opt => t_true, TARGET_BLOCKING_opt => t_false, USE_SET => true, SET_TO_dep => 1, USE_RESET => true, SET_RESET_PRIORITY_opt => t_set, USE_LOAD => false ) port map( clk => clk, enable => aux, set => start_delayed, reset => counter_out, --load => , --count_mode_signal => , --value_to_load => , count => count, count_is_TARGET(1) => counter_out ); end; else generate signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt, 0, --COUNTER_WIDTH_dep, true, --TARGET_MODE, ACC_PIPELINES, --TARGET_dep, false, --TARGET_WITH_COUNT_opt = t_true, true, --USE_SET, 1) --SET_TO_dep) downto 1); begin counter: entity work.counter generic map( UNSIGNED_2COMP_opt => true, OVERFLOW_BEHAVIOR_opt => t_saturate, --COUNT_MODE_opt => t_up, --COUNTER_WIDTH_dep => , TARGET_MODE => true, TARGET_dep => ACC_PIPELINES, TARGET_WITH_COUNT_opt => t_false, TARGET_BLOCKING_opt => t_true, USE_SET => true, SET_TO_dep => 1, USE_RESET => true, SET_RESET_PRIORITY_opt => t_set, USE_LOAD => false ) port map( clk => clk, enable => valid_input_delayed, set => start_delayed, reset => counter_out and valid_input_delayed, --load => , --count_mode_signal => , --value_to_load => , count => count, --not used count_is_TARGET(1) => counter_out ); end; end generate; end; elsif DATA_IMM_AFTER_START generate begin counter_out <= start_delayed; end; else generate begin counter_out <= valid_input_delayed; end; end generate; generate_valid_output: if OUTPUT_BUFFER generate begin process (clk) is begin if rising_edge(clk) then if DATA_IMM_AFTER_START then valid_output <= counter_out; else valid_output <= counter_out and valid_input_delayed; end if; end if; end process; end; elsif DATA_IMM_AFTER_START generate begin valid_output <= counter_out; end; else generate begin valid_output <= counter_out and valid_input_delayed; end; end generate; / Generation of the adder tree / /************************************************************************************************/ generate_ADD_PIPELINES: for level in 0 to ADD_LEVELS-1 generate begin except_in_first_level: if level > 0 generate begin when_more_than_two_signals: if signals_per_level(P, level-1) > 1 generate begin add_pairs: for i in 1 to integer(floor(real(signals_per_level(P, level-1))/2.0)) generate begin T_ADD_state_write(ADD_in, level, i, resize(T_ADD_state_read(ADD_out, level-1, 2i-1) + T_ADD_state_read(ADD_out, level-1, 2i), minimum(DATA_HIGH+level, MAX_POSSIBLE_BIT), DATA_LOW)); end; end generate; end; end generate; transport_last_signal_when_odd_number_of_signals: if (signals_per_level(P, level-1) mod 2)=1 generate begin T_ADD_state_write(ADD_in, level, signals_per_level(P, level), resize(T_ADD_state_read(ADD_out, level-1, signals_per_level(P, level-1)), minimum(DATA_HIGH+level, MAX_POSSIBLE_BIT), DATA_LOW)); end; end generate; end; end generate; generate_pipelines_or_connect_cables: if IS_PIPELINED(level+1) generate begin process (clk) is begin if rising_edge(clk) then T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level); end if; end process; end; else generate begin T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level); end; end generate; end; end generate; / Generation of the accumulator / /************************************************************************************************/ generate_accumulator: if S>1 generate signal previous_output_inter : u_sfixed(output_inter'range); signal inter_resized : u_sfixed(output_inter'range); signal addition : u_sfixed(output_inter'range); signal selector : std_ulogic; begin inter_resized <= resize(inter, output_inter); addition <= resize(previous_output_inter + inter_resized, addition); output_inter <= addition when selector='0' else inter_resized when selector='1' else (others => 'X'); selector <= start_delayed; process (clk) is begin if rising_edge(clk) then if DATA_IMM_AFTER_START=false then if valid_input_delayed = '1' then previous_output_inter <= output_inter; end if; else previous_output_inter <= output_inter; end if; end if; end process; end; else generate begin output_inter <= inter; end; end generate; / Generation of the output pipeline / /*************************************************************************************************/ generate_output_pipeline: if OUTPUT_BUFFER generate begin process (clk) begin if rising_edge(clk) then if OUTPUT_LOW<DATA_LOW then output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW); else output <= (OUTPUT_HIGH downto OUTPUT_LOW => output_inter(OUTPUT_HIGH downto OUTPUT_LOW)); end if; end if; end process; end; else generate begin generate_no_output_pipeline: if OUTPUT_LOW<DATA_LOW generate begin output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW); end; else generate begin output <= (OUTPUT_HIGH downto OUTPUT_LOW => output_inter(OUTPUT_HIGH downto OUTPUT_LOW)); end; end generate; end; end generate; end architecture;	mit
benjmarshall/hls_scratchpad	hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_dmul_4_max_dsp_64/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd	20	80739	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p8dF6db09p9oWm0lH/FzIYezvpS/HJnbKSgl5+PijtFHcZ7Ssq8w7noU0FlQ42fLxw1YKWGl+40U b42uF+Colw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block TTND60uSynLMGVurFpzkveZnvcg5nZBFY3TbcBHmeE+r8DMn33HCUnnIe7IJks7stVugYn38C741 P/2wQXJ9s0eRV+wWoCEWHxYennRkRWPeKBtwG0Z9OUg29bJ6c1er+L7C3X9h1HRRSK+X/FLPcDbO 6eJHumUz7qK8eSg2jNo= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block X8R/sm43wYbLCDYYUKPd8XRkX59OfY9C9rTS23YKJxcdg062qV6rrCVyUv9Qxv7bIyRZ6WoxTxZ4 xZI8yRb7BdDKTYm4XNo1b++4p0iZml9EAbipYPxcAd40nyZQvimzFHBhKl+RQrQAWxXWg9hdftro Gfz9IymBoqAAtxNZZ0s= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Wrw4XASblZbeOsghf4pAdnIDxO1DD510wb85kH1G2wiwlLl/s+xAfFnhwf75adpT8+aa+L4z9d1x zncnlp2y8KRs5SGiDdiTLfcUqiVuaFKkgI82FjxUg4LPFO/Ph/iv4jgOzUp2q3joC2/mrV3M8tdY TcZvlK3OoPjlhEVGydHIFhyq5z7040wx0ky2KzEYHDGvokK31GtvT7SRScIpU/pcIPYdqGu36LNs 4dMqU/tvF1NI2rJ8V0nXBo1HZx0OmIEDJPIYs4PGtLLqUDmlgHbIeASBS4Bjbe47cF1BgwRahdnT 7BLUYfKKyc85XBVo39QEnfsR1jbiP15K2YaISw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LlUwxwgrEnCHIxDi+H/Sv+Zihw3yFsl8/QAoOYEz68lrINnExF1txK0Xy9k5aBcRbCfGRkM2HY0A ybtS6HbV+quqzj7fj5xK5GCsvXFdmF17lzBoaDim8A5EQCHsx9jQNS6s2HurTctN1DvutOUtXNsC YQPAGRsh/vl/EBAf/CVlp8pQlAtc+NNIsmHdv3IlOmWtzj0j1BerJ1GiDGf1lI1wcXWusjXr5++q ralkJx9+6TQa92QDHYO+iLB/NE6P3Vg5aWQzlVlbV92oeQDfrhvSWtPj+b6H0U5RJaz0X0D4GS4i gLQ51uXmBDziJjJz8jDy7nB3s+tzXlCwmyhSwg== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block jSLJf6eKYoY2ZAgntmmz5FjSEJSLT3EsrDhA3xp7tCaFdq4nnT4/8ihvUzSKXb2prxWolk+ch+Nj ezCeldJp31FvLVz2gCyeV2aU5afhiA0ob1wQWQgkyXprEa48b83ZOZsVTGyPZRWr4ZCznsMlMu8o 5FhQe9+yOYmip2l1IdvoKaq3tzmcgKZ0R+4+Pu6P6r17FUkHVJ6htHcheLCoxXnTaMOiYmFT3fSa BzZSjbQgoS01lS28y1TQq+vgLK6i1C1dycLqGAG0d7NHSsmHR0VGdES/4JAu1k5RMJWlsKdIps+p ABCcf9qXJejOI0MwWmeygTJ3Xm3uzazjefeXSg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632) `protect data_block QCuLdQnOPKmgrfnyL3TzNGb9MmGOftaeWnZajruW4TIWVJZGVEgLgjSF5wLryqJ5txV4kNt11Y4N T9luiN6S0pJsXIWy/g2VK296Rfoj1ayr3yKXft4v1ZjlsJluD23Gb2S6V1ShQ8J/LaEsTVGhkky0 o2Xdjb4LQ+LH474rcEnHBQbmNAXCZ/+eNXbXEnVyUh2eCsmZjIiH7exgCiDVxzQSJ4nGdaDwuU+U 8hki04VxXXRlCsXSccZ3WHNP2J/z8ptWc7SD5wRJW1aWUWLitFpaX7aMDQPMHdjEdfmn+thQY9m3 bR2icjUJC3wV3SXRcv9eEY/11pVYqW967Hi+qv5q0LJLK99xwnveD7GLbHdmVKQGGl+CCC98F4y6 DEOL78vCIYE8TEcb66OUhCu/yscfhlG918dv2QyPkXsKYR5nMy60ZH58WCdTwEeb+fvAkTr247WW 8d2pPWBAQjMKt40XGNjL5ndFW9XYq3vnzeG9Z06CDKWaqouhUFwhPGsUHB4sEf+YuXfSCxJSVNlr 5jHYTyYlSGUtfkWaEdJLbSylPVQHho3u1+VLsR0lDadL51LfTHJSIOqvaH1+ZiVu87dxCQPT70eD jz33jbR98jlq3v7ZcMe1oP4bP36/GsrBoxcpy5cjFnxigzIAGkLKQZh3QChKHTErcBJqApage+CF m/3xWyKPMPDZUJTpQXu22ZZqKIXBiDGRId6QotUzjgMA+5BFttLK2/RIfZlGm+/x9x6tlOOBMW1x aMggi1wEBsAyvno2q9WP7FfwCePnaIKqcHUaQA/QW9yhkszaO9hm2J5GnQhWt8palmM0ggEoEAGh nQDpiBcDltI0cUm2nyc5I9xRtCBeoIUq1DExCrU4q7WFw6U0w31DGnwnJZRmgaoUC4En3CDRFW3p 1oE7BYvJobFZXHdbJ7cVGQTfWzuO5yBulZSAVBY6jbEvWTO+YpJaW6qfF/cPd+L+Gi+0AxZ68QlE U6/slXs8k5HGAb9yMqs6Uuex34l4paxkkxRz57/41gKgj3VAL1eliLWZkhkk1TkFgE6GO+ss8aRS uWwZ+SL01B2YMt3g8Fq+12zNG5Gx3f/m3Wc62x8o9yiS6kZ2rI6FwyNlyvVDMT7C7al2Sv6igUST 66Ot8NAL8bgb6LyAzb7PbjWXo1FwzxpmAgO8ctowDaIX/DVV5hC2SrcL0NdlflWjn28nRt7nGwZy NbBCm94U/FkX/IeRvrZwXqyhnm+sR3VI1DHqmd5fMV20MUjP3LK/zghF9M+3ZcbUdFlHfzjS+t7u WBWKzW3A9ifx7O5HqGG0FKlm11jvNl4WXyjoQhx3cbKxvocWQ3BUmh6V0XzCygyFEwaJFk+S8qoj DlNGHv2ctR6VaOceXZaboTjbc8n9Zm91WHamuUfx3aQK4G8mThjABQjpnDMlv5N6b37vyRU0ucOQ gH8BmlescyRaZsz+AOvr09daFTBxysHufsUlPlhrB2DuqviOEjBNYDR3BDh9ARbPnXhg/y4QpvjP U3e5LT/3EOZhdekKi2slwCvLl8NKbU8V0lqa26iyxFF9GDFhIAPrYUpWYGBk1a/sHL55IJDRi4md ZH3xaNDm0ADzTbFyIT7QSyH+PfR/9kzk8T3fNaiLxB6M+PPTA1h74bMz6YF4+Fn5t2qhMIFgZo4k xx/YE0/AdcrnlVh2yVEZEcp8lZ+9+cZ0Ylx4zniZiRnFixF2j9grh3AUbarGr/uEkIEeEte4bJ1Y 75bngb9j+cbSzPLy0xveS25L0yrcqzig3viI2M2jtT6EPmglY1dPM9zWKeBZNlj4xA5lveaghpNF Bd961Yw5C3LNJ/YgAj0ZM+U53bqeh7/WzehKdVFwnpvRXaKeL+7KXeAxvl5I9wwdTtfc9rGOOiVx SXSmawbhEp9TF2ov8k98VpnS5Mek1Fk3taacNR1cLVgDi6+e7TsT1DZT2IskZ6W03W5tW9Hx2MpE vM6bNt3wUpduKvMSHyBhbrK8ov6MCNsmKuDTEwGutno4JmWg0EbWhZn7a6EwfidvVpB+wHafceMK LKkhUmWSj/Gc1foDOaQFEJoCyMEXXHd1jiPtqN8JGUwcMo+CFmEz+xDS3YLf70DiYOY9X3lxfILo WZYGFpHYMOmaMaSBImsm8QcV4oYBmezWK2FizGt5f8CVsx7jup1yyeGOBVcuyBp2mFeu7X8NRvKs ZQNuG+GhukSiimjwen+q9GuEs1zSj7R1zKjBtqwv3AZPhXl9a3PrllXxJ5MFATeI4ixlSIbrPS/z ZPzrZIbxX5LsQ5NT8EXqZPyOkSXLPDmt3C2IstNt/LM2jNojO5sIHrdquV3GVWePscysl4Arey66 nCipX+5tLUTTWgnChcT+D0pwFX0yHVk1Mb7r4J5gT++elSQ1ypjfp9W4B/6ApL2XiXHzOHV/6Mfr taJa32zN3qUZRgq8G7U/QZ4nwjnarwwU6CwQ3bGcKpXajJCEwk34rM+D19UcLq+r7weIRU+4Kh4V xO5361lL1sZLu1CpkmYnNgf5c+CdODCDP6PZUad3LFPJalpY6NExU2KOGICqBYMDOCDu6wwnW5bv 7594EaT/YJfGQE1g9mlG0oargTipP/Oz3SY7qBSVRAowWUtD0JbHhJ0gNsSeY1nJ4qXGtZEPtexC b4cjO3DTFftzlgH/8WdmFzVbcTHf5BBipCIpOIXmG1oqI30MXUgQegL1ihceyABZSY2x9U/m5lbh I6hi0O+9l1uVPL44n86LQaFlW8RQO5C/pViIvQOU5+Uq9r4XMxtnZ3hgBXircUmbJkNEM4u1SFLZ faIhxy3shZejztHT71qWTYq+z12E3nAX4M/Y+2kmDotnsh7xjbTRN22f9ecARVGlenoK1SPaAHe3 pzzKliOwNoHz0CskWe+EflAoiEdR0jLvIX3thfvLFsGU3YXqyHi2qZglEhLbk3TytPC7ZPwU7lML CuMD9RCA0Wn3Gf18Hg/YuyB3OgTyyd8ZrPLVvZN6BblDq3PsZoJv8FzEMoi3xiUQ+Loa2vW0ba3O p90HjF/mNsYRgWgfcAhInfbZms7TOfGtVNGS+IAEcQRFQ2hn12p+VtQME5EX+QlIYgIT8Pe+wRg6 XZHzisskV2OHERI4QcgamenvILTAjSiwnQRLxXFr8OaHLV8lypUbCipVeGmw6twXj9u2geT3/WKM NoSqQMZO6V/aX1Ahf5bhd108NEHo3hc+VqhCAxbbT1nsr2Rb+HRNLW80wNF3XSMgbrU7TANyyvDv 6UX9Qm5/kVDxKa0+ZKTMcrqaxSkRCejdsZhtnwj20TaOzZRcticyCjdPuvVSFpJsclEd76BHZBbF s1Xzpw+o9vjCTQ9yFC1QZ4LtG7zGt9OejZHhZ9XqHDMtG71o9k7BHvUMgGXc5E1kLNIZuO1Vdc2e Hzyd6SbQZA9tkW/u2vnLB4FEGgopg5LBs5EJE5MeK6oJuUH9ApntbimhVa7m9VFLnS7MIYaaB+MJ brjIO/nHUyE/HwNagJzn0ym1eNb7Xa2obcgNl57QQXVfLSfpbpuQg8PyLus8UyrLnuX0DpRpmLeA 3abzxfFLWM6LvpAuY7U3KXgWjrCepxJ3H0aWxXbUgRyrOEpoNKD8b6+zaHbYQzPYvD4uiNJTWnFv 6f9AXmLROu+1AZLnK2YndtfFHpJTYCb3OtM4a/D/642j3WcYT03z4A5tgxwcuT0gIfJb7GSyvHco 6HUd+DROvv/MkACw0fGfUKt5lhWfQFOLqii+uXQFoO6o3GSdUyx6FCPjTF64e60wShUpu7+Hhdne zhkPYebGxVDlI73oQDlHr7Ba6AiZUmyfQ2TUdTgHRHU6gHmlQEXLSq1jg6CwHAEhCiW4J00H0sih XII3rDkKyWbrdEHmbHzFoFezVzb+YyyaBS2sVu3ktu3wXka/cLyOdTeCM/pWc7b7qKjEvL1HYNuv Hn9a0xjL2egeh42ZUKEAFltbVPFlEhE0yoX62GZdGJUequzEkxweKxJ2kKmmJlhihKLAiLApoAxH Zl+jeOFnGgPUq73mOORf5PApNo2f8Pyd8DD7flDdcyHR4KFn9McF3VabjJGvzF7tHTV9PYXAv7mF oTdGOJx4SEgCv2Mm9ZQN5oplTkO/6MNnTdYTTwiELwFmu8LpS6SwG7V1noVBVfpDZbgv18DThMnt 2wePKCXUBk7LHid7/9Iz2g3MBunpD/GSWNv80pbwbuysTwaW3RtV8tyj79klBHwwScrxFscXCEf3 HfDfEBr5PZ+2BY9eU28u227VKn+lIvBoJebvTE3P/hXKiqERKYAJj6qBAUFjItd9cXVZVdSaNdsg Q7eKEgBEUF7m2mv41fTZO90CAttvV2TA9WGjZtDfAiv8oeAnEDzaZLCKlfigMRIkbPkwbTHvwYY9 Cme7LCCNPmfi3uqPDq+8f3hl6FN+UAoPZDOCbvYd5qhUi+TcXAl/JtQjkb4dVXCBot0x0wi45P+G D+3LjcDSwH1eaW3IIzP018ILKzZfQgs9/R7LpwjyhUKH0/DpXh/qj1bOSPFhhCqx3OqvlJYtYk8m 4fYGJuaMLbuUvzKTS5V+Vnf8TNaRa9ywI/EYuNNo3iMbtsyM76ZX6g+wcpeiFbISN9xGB0QbhVDL OpJzxXbh/eeom3M2Z17jl2WS1mz/kfaPM0t1DPaX1AApTK8Z2i54e9noNA8Q3LW915/M8yPuRpbZ GNO9ah9yIkcRj8LgUpF+9TAhJRGAfjV24dRN+C1LKheLeMYSOUQtZTBEoTV0si5Z1R8o6Iy/wScA yiKhVOb5B8RDH4oDlxJ31v1n6UkOXYsScpOZuRE+uL6c8glZlzULnL60pZjzBXveCTbQDmR/EDVg KmzVLFrBX9S4sA4gDBpF3ldu0vId0n2Vu+PXBXYYwZMyW19mpjgjwAwt2g9WSdsspLB6F72ZK76E T67zxqHz1AE4bcHoYn5YaxjspTNjp5ZAHjv977WZ243wkAw1mKf1sKQTqE1WlI86BCYI0tOMo9XS kc3gZJC5z2C9aUuDfG7B7WSkh0b0Ql23aBZWCSWvIp3gXF5AxsnyM7OXuw0SLtpKIPnfUOIDuxRI EQ4Ji6CgxplGtYk/7s91lX9ywMoszY+CcDjeEs2InhwYzNQ9uLUQfZ5GCX2GuHFisL51ndzka/2l 6Bo+aEAIkPBBgNkQ2j+wnN29w2cwCID/dO2NCe2/6w3LF6H+7hQ9fdA0zrezBJnrCDVNH2CwdWY0 5M9F7ZnNpKu1a4kyOdMGV5C0NZ1XjAK8S5RhfAaeb/sJhIE/ILPOKlIn57QJ4WJcVLTzgqEcxtqb WrZqBak44Z0wzyNGXys8p7kC/++92Vo96GvlZCLfKfquDHMqY9sOSL98wvt/+T5jbRuExX76AlcE TEZmvX829FhTWBAw3VYmcHbc/Zwz2Ih52ZRg1Y6kK7HTE7QDSdZLLiXImH0CMAfAWjc63QnabWia 9q0sBSIATZGMl5lVfCgl/eyKcLexNcMzj1cNc1qK4NDDKMVw7Oe+wUTwvCgoZ17L09iqfnt/ay3K A3Vi9yVR/A23im8DNEFrR73dcL4orCA1yC5MN2Ma+RL7Xzbg9/9JWBpKzSWdTzgPIwawVSLWPhBa STf2xzAJu3MxEirc/F7O89dd5RYSnyRTlFtTnMFmKLryzh3CSuiEgmiIq8jna/WXweEzC+2hwPd/ ZfsPNzZk4AE9ydywDCkCrmVJzM9tB7MBtyrHmXykrW12HOM+Sw/XM9+bInUaEQgxDl/jXMlpDMnC dih0QjPRrPezl57FuJ43PzmYBv9ZF72xO8QsoJBZ27ACm6AxBNt+5CkIUCvQAhsQPcUb0BD2tU4O KVg7dpO9BblLyKpvtyL/JGZYMqq33VB/v4z8trSTKm7Rj0L5btDqOkmb8xLNslsFRC0imdvAG7qH am30mxwj0Cdx2zjSaWicPNfRYiEPAKxwVS2LDa0OdeinRH7FkNUiSPicCjiQ60FysDxuw+Q15xw4 VnmmWYCeYGgmrAa/O2frlkE04C6MIrA+6gDs0LKgrA4GBViTHHSXs8V1YIw0oaKI02bR7CvvnfsF O56K5VVwxQYo8vhLNBb4nWX2YH2B67QoEHN13lyShL5xYQm2MUZB4aEnac546LJqeeAi5b4TB06p ZigiTbmVo1B0ka0OJc+vUa1K0Tg3ZuL310ENIa+sOYprrlUTP5HJniCf5LBJryy18V9fBL6tKarg aLFbC6VstIruz6SregKwO9BqkXlHjyhPIMwXLqAAU+fPEe+TROsCwjtf2aqmlQagAxTASzuo8aq/ 3BelBLhUsH86999EMqUns/n8US+l7HRyGY5u3hsujI9BZyo3OWNQziJZLAci/PMoIwNnTnokoCuE jmU6xchw5hHLsKYjdBfd8pWSorFaHTFWqVGRhNPiRRE20YPQhw1Cc1fuZaKVUuY9dyNmMB+WpkFp aCSuPIOkkAbOlkqgx3aLD+SnJwv9lCWtgNxun4FITuYMG42riPMG2eoPdNbC9mno989zaQbXmbm4 VWI/3yzvQ7XGVyfJ2TL0/sw8eRb2Yrx5Lz9IrIFCWJnlISSin8NwtTvVKl0434EflWuas41xcTT7 zGV+d1lqXyoOVVA/4R3NyqzTr0kbkrIv4LHYXCbIwaLV4p86TOy6TvOPuuof06vQLySNf5t7TWRs tBOgcRWSjJLRoJZVZyOc6j2Z4Zsrwkdc9ouviLiPv61FEPLgaZ/ab9ITsotfXb6XzVSYqhbZ/05J bPg5LBthd2PhFl9gz8YKczL3LUmTLEyuuXjK2ORfE1/8wwkjj2pBnE62d0vNI8qunp+vwjq+6v1c gBvog+2G7ShyF2DHdodJDllfe3g8KOh2nnDTIX8g1T+PJUsLuW1hjUR16wI+Jvk1FuUFnuhR/8fC 8VsVTtCI1wRG0gh0ru2P2EBISvliJB5QKwFxRGEhO2BZKISt6WzYv4bArSl6+J6bLrF/oz8L1Wxw pQDbFIGqiRvjP4Z7jtgBZMjTaKoheqP4C8Q4wDq43QHoCwScctT0B7fNPpD1SxYiIiH9WwSbe3Um 4teEj1G1IOdyBO/6YWG+/Zdjs06zuDboMB0NhtzfgePPKDIVRvMHYo6m6LQXCjCKa3qG83alhAes Y2GJMPCCn5ztcKBBZLRcXxXrpNjaOxKNimuR14gNaGVoNuCIkeMJm0PRu0ST7lHN3IjUr30IMhBI 3vzIGNpinAzFIPQU/GscTVBfuoArwMlzlbsNnUWT2Lwx8VNNLAAAFty4+kKnNMmqOM0kJIPlD2SO F7CU4XPprTL8Z035uuW+9gfbZsrQcVh+Ae1GJQg6zhYYaL1DrsLxz/E0y2VyU8O6eTCagl8flf1r t6Evat4JhNomT2HofNsyfKpuAx+qgMlPaz0zu4201BBdr+R/lhUl3NGLRsVSaxpc16tlGe1iflHw roJtyga319XCquurkR7UYr2QwOKg+8Xp8brB4n4aAQajK6Je8c9VQUXBfpPaxCE9YuUI/ZmBUkDg 5t09neD8QCBwJUhj0nr6wmgg4KCz425pM/oHFj47aaY3eEYNSnK5cs7ipI3964ta8NkVvIjjNNuW bMkpGijKAAWNxii5P+gyltNSGrpPVQaEg/G5l2aPCGWMX4KouSiBwfJcDeaUZjgTYeTxWW3KYq0N gtkVPODFMmnk34474GP6HnIBowad4V21ogiRck0a30IoW9stLjmwI3UCXTFDQCQWxSaPb+c11hqU uiRSasuPbDLjYDM4d086jBMzvTgbgZRk9m9FKzJ2BmAHP5H00GB7EH3D1n6kU0WZ8PKrKltGZ0kG 6w85I/4Xf7vdoY+GoIa/Vi4f7oIZVdUDTaQFw3nuZC/HxBvDvTuvMJQRQxJvt+pelmdNF7E2hjwd jHrsQKeEEKMqdOzIhbY0o8KKqQXg6cs0gujnjVjREMDsLyAZvoRoVZmdYX3PhMu+56caxFStPkGI Pxx/WPfLQWj8ae/OLxU0UxLGDIxa90tQN0jLaYFvfopLiwI5LOBA7RO1EFy8afCZgje/wR6Afjsa cm2wbjwOrCY0nB2uRCwSkmLvGOG0bm3CL2Lbgjsv9ijbSELrCYJZEG7dFsHsHiQ8OWgyjdjHLKDI xGeaBqTS65wFbu1ciUiyxC3DGjavxin2R7hoHtDkyEH3t9JxhnmVEEFnG5PiRH1/tkhOoj07Fu9x zpMnx4heiYx/LkunVY2tGikK6TZcNeqTYVkaMLiFSJuHHZ5B2NQ1cz9J5J9rgIw0g2lzo24FdSl4 7QI1IHvGDdvZpvDbRZJlp2ZxHNs7JZQAg7TqdgyMchDSDRnR9+vWEgPoUFf7SgbrpnCbSV2uSD99 AskxJsAiDnpAsQ0zaiupgrhyKWaiDVFaiV30aRnf+vl0r9Te1e6oC4Z8X6+kOvx2KOQJrJl3w8eL FoMd3Pt9Rnfl5JeGV7JmDHnsYpWV2rTGPx81B1BvHXIEccsGRFYMxUPQ3slrTXA65dm4RpluQXKw 1/r0NzxHZmdPa/gg08JaFbx/XWCk2gkvb4U1UWFAZle3qoIF0FI4Mpwz0jRjY2Vy++mH+4/3Zp7V yZ0OvbDMIyXEeuJm1lRwLFlY3RMJH5ghUeRO4f25l45EbU8LIw1aaZKqjBfsuSnEZII5iUu4B4ik KwO7QvMRTThTx0v7BveDo6F8HUrgd/QCOGgcvgK/z8Vzcyx9/0zLjMERKY2pT3zELXyPznKAObVW Lokdz8JusI9v9SyZNW3pUsD4rC4weDb1tb7VNurxhLoL6NEUPGC3VcD5HFpW8NMKjgCfGnhS4S1j Ntyv+BZRLn8mXiqXCnhaNQTvll5ijqb8AITHWPjaJz25GB9mO6tKIQ8nKlwWhPRcET1J2Y4C9O8Z qObETucJgLG+KWFHXKd+XGLJDDdgeJgBiLjkXOK074gnPle3CSNUzBGQGCO9u3/RauopBng2lVvP 8/tmiytFhO4bjS/hslob+iLHObbUJg0U7xPoIP1YyNDep92So+pOpS1uXEsqRZ032qeQct9+fiPe +DwKpDV8tMtUUT1hIOKiv/JXCT3Ebjj6n+r9raDEE2nJlpbH8p0cLgWsXCvIgxizyb3q+sa7NbUE jddJzle7EDsx/upKD5zjVK0fJi3SbCObHpUGMCOktwOSgWEDFhEEaPOY/HUhbXZio7M2gO14q2q6 cUgQ/xcLrNdbZRKwwGsb77UsvRxqdUttmNeM3MPByAxCI65NsYWJmG/QMmkf4JcFRTYVaGMYgMGL vh5eoTwVAzsB6iNBQzCG0bQ0NeRcuZk0W2e/SpG6taq5dBtjBdeYQqhGOIoI0uMyUsiNpcupnu1t VayfwWC61ZZXGY88ng4F2Ng95Nxr12D7nZTewi6hYeDVTKr1iEhkfv70XRXgn37pKTptcRNJKYKq cR8BUrPiMesdD8tqYQpxMd0SZpZVzTsFh+YnMWU9KdECCP3Hd/XJy9Pt4VqQThQehh+Fs+pV2Drv ozZCiWIDc/pdwg+zda/+EyEtyzcEIskumaareIyfbz9LjZ0x+oA2aVJWEJQYqBobm74bqA4u/R++ B623RDq0vCioj9I7syS5brazVgOBH3GfkSVc7WZ7j8JP4ulMqtvAj+k0B2OdwJkBauDvp6trwyUJ pCFfGYmi0R9F/NOtuu+hY8RTqjM16rtO9xQfI0S2kN55v6rSkA2FLox/c1KnaXue6JSmQzyKzHLC H+0aZP1ErVZ5A8Fab7+n1XE0HfE2rhU+qM1EvFROrm3SZ+hiQphqEV56Vpb/l03HvqJB6mXIuBUK qu8/dF6i11GKQrzBjqR8V/V1FwMaDXkzDlrh0gIS/ADRi0ilhC9D4U6VJ9+4D8e/39vJqw2A9ez8 mhg4AH1NU8i8QKv2okcaBzYPVPmPKOi1WaUqD8UZt7SBSsxPpDfW4HRr3/0Xq5r1Pg3mfzMLjJ2H N2iFPVYI42jDuEQPtNUPTm+CwTlinKRoppLfSLKjYsQXG7PZSKAuHuJ6ISasSIqcKeWDgKb+b5ly jkqW8Kfvuxj2AroUK32JMh48aLXdMOyTqXvoChDk4eegI9Gg1FZJ8a5BTQut62DU8kC5LtbFDmsv Q2feZdBD251a9p2C2XNPFJL0eYu2SEsOGMEMh6Wg6wAdYlCN4ZK/YxaZgzcPlAya6H1VRWqF1NnJ 2av9DNN9LBD2BTpqXAXVxr9U72aSmxjUImJTezuDB5EzmHauOMwXX2QxFgQIaI20N7QCq7MctQbA EIx4NybXrrOj6ly3sHeerRLRqGOnkeU4q6GDDETUY/OQX+JUNBUljrahvI//Dclp0o+dhuqPCGm2 JSXMWCE+wmAuwDB5QCbVffVT4w1rqh1ANjxLCFlwNlVXj86hF2xilwHLE23nn/f8+PgHuMSqiz4I l25Q7SmZLF8fApLmu5keYRR14QsiSl0hWb4SMstkWaWJ4DcXHvJRb5T6PeSd/9uk43Xq9sLNH0PU c4euO7Op1XZk3Y7XGwE2qdxWivQS5Y7ulnnSvTirHUuVsbFxRs70CwEy6RBSJAYNcQ+CKZu7V7ws g4P5RsPSxK91weCLL2NEmGgTpci6RIK7HL5QattccBSGqh015pkCIiq5BUew28FWIO81F8fjSII9 hGZXocDj8pMYmCzgUPd8LLQUiSfxGMS+zecrLSxFR8/4eSZGhNZXZBcglCmfMRkMjySEqx3ODi59 Jb6kfc0RPUmvLBrKhTPSOtoojM4A8fiSM9VBdxtZYUZfR+Qj/M1Ep+z2SmhzQkHPzXtxsGUDTbxF B2du0Uhb3G+GYcMVZ99lBw7nZ9jA5cCjtQu1jRHb3VjffvgQAMyg84X2PhwQp3yS8sTD7Ju/jxfR JZKspgWtk95OeVWqXbLO2QlKyay/lqhf3+esCtv162wj3eh1S0hyAk8cVhDb8i+bKKS58o4Z96D6 TDO2nIeWXtvkhrDpWzb6QFvuMGZljafCgtbpu6ZIrJVOXSqsobj4Ii5lc7uSRUo86yvvSndEaU7h eB3KaDVJSyTKmN0KubKjCgPuNRmXbXFOjKr+VezLSFcmBgbcAGhx+UeVfLe3kCAN1Bgu5NnqNyjT rTIxRz15j/z80nCeMINSmtxWD4ETt55w4OiQ6cUNErdN588rDzbOKEttbP73wzjnbtwdLdCHZBYI lIKlr+r1Y/o2x5eHHhgrlLHu2IM8zxwPWksmPpXDNPbnQtB+4golQ9Rf3SpoCE3zPJe3ukwtrhM2 DFFZCROkL62Jc21G7/QcjFTJAOkccZ7lPRAWMSSG0qGo/kY1eQJ2Gh5i/SZTx/NMH9n4xv3V0f+q ppAIAunPtms3viyemVCxeDW4aoaPSm2thb4nMXmLO1Mb/ocYm/QngooR+DBf4+J2F9Oc70r4BWZE nSSuZO5k9yVYhfXniGkHefpU8cWdNM43m4AN+sRvdmIrTvxrV8tYOuqcMhY3cB26CAvr00PYzjje JWVQ+YuQEzwBfFdT91FvMzJXaV+rgs3KtEwav5cPlAxgyVQjKeB4ZN5ylbZJvxNLCJ9h9UhAtxnG 7c47nSwTgMaxhxvJQFqRMWgn/8eoEHUDFvu7UGZk32Lq49dJ0J32mcnyPnBzQVg5ISiYRz0R+c3G yDfehRU01U8Yfe6glm4b3E3VSOq/kOWvvvwJMJgJzp/5D+DBwS4pYGo/PIKoL+Wb91DEbsY5CL5J Im4Bxmg9kn3jzvFeoq+aofiK9Zx6GAjDmcsQsRhRjPKSEuDbOL29HKj1oqLXdmxN/TzRGcrF5FoB cOte2gTeLUAWF9GCEXygSLBFzAGEz73Qs43LAJfsXAQRT685wjTCuaGVkocw5W/lzRfg4wvGJ1Nm Y2NuA96p0yTEbRXfSjj1MndjKYwE8WOWnJy3P8iWEPH6xx56qIRFCfSCNhU/YXm9WDCJBg28Vns2 CAV95gwfsN6BmT0v8AYGXb++PhL3qd2JRypQ+16DGMiJ1ZH0VR0YKStm3uKvWmU8CG4lzkyQ1Oaj 5OwcvOAZLXxYHkR8ST70PH0cbYc0ZKql1BSuGMiQpOiuZoejL8qizYASjvKtxKzknj2+tm7GRqcy c2JYV/+J0HYCLTwS2PraMGJUw7ZbeRBV3IDRwiYcnFUFSshCamlrYbvQ/Ps7u8/oMAmJnlXadHVl HpIANm4PB4sb/mLJhoaOBx6TihfRqym/pIWbWw4U6M6s9ztvgcECHFsMKU3sq5qFWKZXC7c4D2Gv Prnj5hk0KGoDFHc0zsoGeLivv8f7JKW7CI97OK3K8LOfP5+b2g/EpbhCQsHixqsIufN2NbBw7QHh QvTfxcZ3XsMdXiKZJn7ZGOD4Fbp7IH+cktfDvSbuV+sZgTpTwYj97a6GiN2HBbyOYhAiSEBupsfK ahCFd7WUdwMBnLWgQfs7JGYCSjyocLHkWGpBYDZfkAxujwfByhKhEI0/FokCjjBUQt1fj6cCRiyP ql0zDUdsNuwkG3P2P+tB5eCPracgIa7LTo/2Gj+jIW815F8BhJjqHVqhWfM45BGtdJkSQHKvBsob UYtDHcFrN256LRkv2NPaxSF64WcjwwK9WffZTE9yDOT2933DjH35zx8RrXeD1Qa9+F8RNoO4jdyv YlDhreC8ninvafSPUw9TrgEUf6S5z1iePMtYlxGIehbOWB5n3DGXvZdJgJwVhb6n9J4/v0XNGOsm JN0IEBs2pc4PphVSJ8SITStyIoZF3WmzpHVs/Wt/I+hho3hfgWHtFUQ/NNrCjRhymBUyp4tbpxRH DSiv9a4EKuvSfNX1xbaiLEPJG7ZWKvtdXD9GQY7bTOsaogv/AHQ5M9TgGeWeWrZgLBB4TIuqGvgw qGp7C07+2Bsmg8lTQMVMk2Kc04jPMvAIbKwneOMUU5PFnAHb1owwR9m1P5tOsMum4iAiTtGK6MKg HrI4gyRCNIe4eURSFwNf0NVhOIdOjhiszEfD6NAH5h2426ouTXjRQx3s/8EWkT6GOrntco60H+IG a1e0q+sUCrZMXx4Pkbxw0e91vBqjkvcAljJSWiyQXkJ0Yxlwf97NGt01jrF+YuZXKdtVpIflfEyd G7vnVeBmZqInzL9kmWZTdBWwFiZ/BLGfn0UJEeKzSvk+V85JQQMDBzixqFhinNXkaB+buL5iGKnH /poQBLJmXATwhkvywjLBti277m/dJqMV7SxFhRlqPgkwWNFPOiktPr8BEwR9LNZRqh1OWvkF710X J4vJA0ZBtpH7f1Hne6JipSPVnl5yo1MfPgVGEno0jIxRlgPPJRSYH9QOs7S80GT28G70gIg/iG25 /fIigR3iWBD1rzwnAVd9UKSEG1Onvq+JDHd5c8mxhmvl+jXznWYcPW4yRz1g7inw1Qq9F1Z+ozNs iIT36H4thvASbDRypvpR/2Srs6J0erEwrrV6gzYX40WcVe3OiwajpcZifr5po8lJFuNoqC+u2KUX nsKE/tqPT3v6WoaZ17/F+p4gXjvKVJ4jrSRL/wMGfBlz3jEJg3gUEoR7MkaOuv2dlaK8tYjaaOPu vTG9aYhr0q8sOl1a9FMfisWjTsUrVZPFjQTrMv/u9OwrMt2g7C8ha91leSVfYtgOnaMC9hrUB16L wKfUxHMlh2aOjaVT5sSrD8eWHWhVHnG9oqPcIBkClAbgALM9e20gvKzBcJ21hVmmEty5MhAAJhf7 t2swM89QKzFaHTxt+o8n9NtphK9erWxg+nUL7mtoUQMOb1G7tpyrkFrQ0fL4mdDASiYYomf36PwL CPF/IzoMXVztvdCwBbd1+LTz4G6YDhUl7PtybTOlRM5vm+GFianPOJ/uJ9zv1IO3PY0Zlv9FMlWV fh+gCxsS+rHI2CVuGAwlnSQgZKwhGJxVkXqXbE4SgHpQXaSuwjJNYGs7FhbMvvc8XCHqpZaN+6qc /CpbbeNkHruio3OamgsR1W+elCAEZ4nYSMIS67wQc49xZsBj2Y2j3zRtgeAPclT8x34gYNS6lkjp F/jkDY4k51h7MGxYgxWRJYliBKGruHbTvntOwEPZ3HqyIMEugnoi2/1PTYjBFNHPYf0u5MbSIN8j SiNb2xKTHfnM3BSjA3KOUZ9rg2gh3NF2QyoEnCKkI6qp1oyez55RtLUQRr9cZ0a4KRd26nhV4fnV bQOTXcGE6cHbXJ/zM0kIY1ZoujYbymkVO2OM4hpA867ngruvvSbFAfaFxHlV8+C3zMKzmaC/9Fbh psAKZWWb1mg9WQb+3Fw7rVqPqDUQRK+2nDZnSnrDG1Rx5P3KHrab3AySY7dL5mLY6M3uazYNZfa5 FdEYzOxtqERvBRI6eG1HGcyOepfcRQ8gSLm8AFi9K3Ncnx7M3K+rZ+3heQLi7giF4fzuXn3PVD0f TGb0kAbqUb0Ewa/QVqzZq+h1WSRrNkmosVbrgljqjb1FBdXEU0thaMtngDfwhCeyB/F14ty6Dut8 GbnURKIDzGPxBWOwT/T3orn/6mgErzmWCvk+3dpI1OQb3OP8+HhWZswP+SRT6eIMhw6EFF2exiIZ 6sP/WXZNEJf/p9L4rMoy7kjESUuv2pRlulPv/NLY6IHYAUM8odhnfIWh3U4Ec/B+kr5Q9jrE7j04 KxYDZtYWUrO7j6TFGwUAsnbh47ERQrcCvw/1yXoBjWL7gQ4/QGmwQmR1k3U/7+uTL4zYXPJJ1A66 eJYH6nkCeCb1wNWlplPKsDEds4rLYSo9EaVePour/A6r3BDJSInahapC1/NQvZEsPj20Fabu/ap2 u2QABxAEuCF9H7FZL3hSJig+qsTerVkjdu3egrtNi1L3kQA2rpsJ/gd5KBcT7p3xASfR76gof3PZ A+RYVCrAUH4A4YTB/33Zin836D7e3jQzsc0lvc7hEl4Jj/YCOD8BpXrwFsoTjW8S7WzDE1JEBURc MSIj1axKdGJEtQ99telLbHMEdPKUqJZ4FPC0en865AIdiONeIEFPuOdmvDkAx+VTzj3m6Z81a8eK Jnrzm0djcfsNNO/e0GwNhdg/ANDkUN0m4sSMLhA+FoaWdTypzuQ6lu4v9m3cptAHLNdB0z/AOU+S TAS9MtooH6kpVwo4WXOW7WDViGiWAcR2TCzuTxXV8qHPpVxO38fVXAV9+eITmc9kUEq8y2F39Avq 45oei62AzhSnudej7CdGqq9JSGTbS7GLZP/r+eTL43GYle73eLNjlGMzVCJNQIIKwGp2oX09ZflT vImHUE1u2ncCIVLHbcNEnsOnCllMKexyyuz/YGgiihErUfYbci3YyUbQW5KeWF5chJRnSJVerfFF IQnoQGmQDcHWDZBYU3amqc2Miohtn2431JBCOpsgLM7Ufo7zjqcteK60QLR/EeeUwBDTTUaUOHvs a/YYbD6lAXMFcwH/GK2Fu+unvI5Qlk8SktI9U7NYMw/LqP1TORKvc9E9AC7h/7EuKx7BTG/Y8T+w HR6emobOVm2TMQ5SGrgPACqk7/4xLBnDXfU3KBiUJAv/w5/shZsTpzLnXPTwM6bCUwkdGFrcNWdO e1YGWHB4gMyXNgvAYbJpGF4A5Tj08zrqgf4WRsPNJyvp0tWln2NWmZxbyluW7bsSmXdTAePTjejT tRyUDihqW9M8NXd9qflljZKNG6JVlYMVaGfgERVN80+Z80rSotSJ4Qo17LaAuaAwWQ983wvly3Pa chRu9C+4CUFLdKATEgprZZqZs01vmq568atvTl8wqigZ74EFfGgt80mMMCQfaKVFM4bNxVw9BoMX 3PYpm2uc+eoCwGukTqZkx+BBwTU1BwaILD2GBrMqmcsyy+Jzb5wTdCz7yy6zoqjIznZcfxsv1EbK zKGiSHVhxhYywHSRAfCSgZbic3ZXHSCLKpEPLmJlfaJXLmG/9lFF0HVP1y+6R92l7B+RyHyg+iPy u5yNGS0ECCAEHf1KdVHoktGSYw4oa2t6WxFcqtTf1lOcB5t1FiPEuu531/u4BV8bQzBMbjIU1x5y +R1zZWHjT7uHpJvBW6YPjs9HzDeBNIu9M/NwAXUoVBFMHzV1F244r6EBsfC31CID+CmHyc/bk/oF KzuAh6TKAqvejmoZYCz4ZXPt2h8e3fQVuySizRFLTygJ8HkycWIxHQp3U0H/UrVmwBc8orSmJBX4 gq4up/3NKL/VThnfqsYziqRS1h3XR56bv4LLiOgyFs93kMTqJQ3nVunt1b/0JkRRv92YMebMydhD IaExvFUl0mGAJ2oXvB7frs8z1U/Kj3bHMssA5OLxHN4dk7nbfIwCnM0HPoK40yjaxfndgOKoTUnO hzv/RaZyNZWcdr6DdXJNWs9RrMk7kMQ/CFEqlE01tqCs3Fy6Z8eXaFhlGUJ8CoSrbo4HIO7ZFlzH 7JEEsSFJlN2Q6RDuVHQcy7Wp+YI+6yeP0z1ssajXvX5okz3Ynm3/U8rAtJRVESzNxN+KUxmROynn 3/vyJkBEU6G8Vxpzi0Knu+ZiRnwtl+aM1oPziipPBJ8MduCExjDMn5DKdWOYVzGGBz0njAOycKV+ al1ro6ZnTjmieEsukC1yNq4kZmjlOvB6SgBkomwViKmTICYsu8oDohuJm5mUTugsJduueNotsvdH FR3jQQYx6k9/aBX2Ha2DP0Aii/nsyMNnJ6x87GKVvVR8aXofJI8fvuQQeaAcR65gnvUWN7fJL0aM VE8+mIh3d9fguuo8cWpQ/Bl17a7QU8Woh9fVvfN8+arYBP0W7jdtp0InRfE1ms3t2FeJZipnzTOo EgaOmLCkx1POzH8Yb2ixlS3DoHSr/Y6d+TKNhOqhiXjOwvmPlbLlG0b7mATnLkefZZfz07zAOj6B 9D2iYb1k1kRNmgn4JFZOFfw0F5/hbfD7a/h5dbKDl72ld7rTeNVwBxELFsOCoD958dVDwwXUvvBq VENZHdOUDzzt8hU6CPu0WvV5m8Ilqnsx6PzBlWPMzawOHxmh8EyzMUjo8XmiEffDTJqzJuxQv34T 55PLy8cxCapj0hzjd4s6/ldiqF5uMVImY+BDKOGtPe0VWioFqsRjbMi+n25HGZufFtQJ8GlI7Qae 3WbMC/V639laV8w44LJ9e5PqTiNe792En2h+SFEkLOfTaF3u8kZLqlNq9cQJlRhxmOqEe3tGJ10g M1jelMxIdqNP8B0N5NrAEreI9pzWntSw2Gax4tqjSUBy126FcjmcDL9GoZELPTS15q2ehmz/a3U0 3bVAgE7/KZy1Cw/ln2FkTBS4h8muDnhxC804OcZXMjKt1XZrrjtprTdfhq/zcFNJ3pWe5GWimdTM I4cqZmMrX9HlejqDfKGcV88NDFYcYBWshCu1TdlpNyxVNi9TtQDNEvNbKeKNJcClRgSzRUFQF3CC LJRWKa0o8ZgNL8UVzvknIh62bT6LxXYvEr8/mGgG4Nb8sSh7PAzJFS6Hd00EcneeZzEe3f6VQlNz rZANhQSHzxw4BhfkkvsFL4Nm9KSSZ1n7QVnt0kj7QnqcdA7qkgMh/I6QQ2X3h4QZ4JN1HwK+Zrdm YN959DVhXJJ0FKZUe0n90SyE0Ob7TTGjfHj7g6fP5QIk85xHV0kUytilMgi8IT1NYLCl0I26laZD ebXvh0d3X11WcqJ1IVZJOdQot7Kop7RTjYXswcBqXjriE6BZasyR3guOBppA/U8axsKZNZL8GwgB yBtWeL+XP1x7Ma8tJLgIDq09WQBryejNYVrxkdCG/KlXHx7zT8Ia8KbVGZ2OwI7dWMgwujgmT0t3 QCk80947ZZyuBGi/SNYvzzRcQulFKNZZYXQV5QewV1IF/WHUOxVa34uhSXHq6h+kScgKXK7j3Qua PkR93mtMyKIxJ1iqRrsUTVQDNvoysHLYBZ1lJQ/TxDicj6pqNur73+zhFmSXTQPpCnKQY+Kpu6pY LOErM6Vbadp5RmvgU4xpIBpYxZ806AF06kc2ilXQ7biJ6QkcyVSY5tH1TGceZZ7+kkWMcvlI1E6W KnYraCNplDjo7EG9hGSOpD1U+vGFo902P18VfMOLZd4pfKDepKAq38sibX6/xihW6pUrGc3xqg+M xLeylfjRCQ7+W87A8+soO0LlJzqzPRra7UobFcC238eakAZBpumeXO01cJFfBlceunDFmrWKIBR8 1N5zPbqYFhtR0XLWeJNvibbjuNh8lAAWxNcuVL+ohpnWyAWE1Snho8iuXzoqkaKNXjGaj9uSct+Z 4GHS0Nb0tppbrYEaYFZOP219qRwlz6EEZf1Fkx0hOPBLWi68u1PuFKVl5kjScabkwhISKVBG/i2U x9wxi/bYekkxLYOFtkZwzHIbNBDYGDXRG4O+qk9RCeWi33PWxSt4Bn4RJ4SJfXK5uvjXscyTms9V kAA7hslyhJsLUiCH38RQD9eO14GMNdM/fAgfJVHRtHfxf5A7Nqz4fM55+axHwIItHRlhl6QTWEEC Z9UBhKuTmcqszKqCnMOubgdwfSggqHfWXzD1EWRVPmLoBV3tKFzYLlLVZGh8bCABit6DEoAp8g9A 4oMI5DzL3T6DwuJ7BmO6EyIsLnb80tnrE0v0FEac6FybTZ/y82gA6VlmQ8+FLs4qZ0NtpDnW+nKr RYWeO16RfzfJmd/6nbJY+lbOC79Um4WOuFLrJvKtQCxQclRGhQB5lZS5vb2Xt3p80ebkX3tcevix kk41hRhxY3a++1DBicEKH1gEpQ27g8wBjtlJ0Kxqqx9ezJHW2qD/SeuXnyvirBqTOuY1wMzAgAOj 1ZO87vx2EFh0JsiwmAoLEfQ0e1JP1O5og1B+ybIA0oP3qipeVWBtNpdHpNLDUtzn2icMFheP0sEQ qG4DFmQGmKNQhGfTRIX9BIsirZliU78ZcY2amplohkBLkehAOuDw3DgetnZrio9NnBgxcDcVy5Q6 9QmKXJGWUJlSmvFsb3F5MfnoE1+czUE+mmwhnE5h21vbd/uBPKhcW7K7k1NEX5WLAYWN4lyOrEqz fd9J9UcX/zVxvx4iq75uoBZosD0FcJpam/gZfXF78imbbtuEQsEFq/y/b7YGIUlcOx5p3wG/KTaM pXHeVGk93wobopa6p7zQS5RqGGAg+qS4qa6atDqIfDLhVMTzbtXHnFEmuPrT1bhkNzn0GYmTdajD k6Qyk5JK19qo/+Gf8shPX+v0i0b4e21FxgtKD0lkMMIdRLwAhsxQ98VtvEmzpfRjncGRzpMpY63z QtIKkn8atSYntA5z0gmbp0tx+BhKE+F2GKt3ALFctA0o8yBhFG3Kd3sUTWRKfy81J1CVgyOX96o9 lHOHq1mvxcZ+BWq20KBXS3ZEvQWSr31YkSWAcyS99x3GWr8NvYkp1F1g5RaRGfzxuAuxeTebQt5O pzCfTFFOsKUm6+p6RNw7bWqxOxs2AZIPIOaixoT+jVRI0x+skQnkmHnYV7tyFDgyvbLQgMCpCZeg nBs1ZCAs9MBKu2tTZUVhDIWPi3ylgz8bfYGdPJBOyU2k4MSbMUApH65ZnG6sQVpqEgq255MXi3em JInjcVqbaJnSYpcukDWM7oVneDTq7sLEIfXSaoo8zFWzbWdeFHR5+RoQbPlwO3T0HpiHYv9RjaGf tJuKJyUEpxwUAoJfi+F/H5xDKKw6vXJW6+PYHRlf6ERPSZy8SAxSA1y0RAdKuEfNoiqiZW4ynoAl vfPtcNDSwjdcRGsoymiPDjLesn9wrw0/wZA6Wq7a1vhobl9HNVt4//btn/l0PhVGQ2eXQ7LPMayc 9pJaO9KFSp4WmKfPTZltNQpp0ncohp5AGEFhvJ6jFWiDobM2mQZpjg18cUrrNMTR7kFrJeQZTSyj GdrV1dIIhE2iiqt4D6kk9l/V1Wl6THRYr0cdrjIKQZvIHljr/uY/RFYSe7NXGIe1eayL8Ux2UBNY oc8127FT4bLswj29DEWh09no8afS0dXUOtJPu6BthICOl7AeByDraIAzeBz5wCnguVGAwn+jDoPX 7vqaHtuG004KoOwPtF3ZjJuMUAX1PW+rNbQqAMoOPO8pYINY7VV2XZ71Ux/QibI16YkDNM+c3qHi 1uun+TO7bFF5Sv9tC1Lu68x8cWKbSGePHSBXIS6s/HC2ZAFqahpeIrhx2uCs86yrCAuPfcmqyxDU yi9lGG+OrAwxFqb1tAth0XJPm3nv9c/8XU8Dyfc4JdXiv6Reqg5YmBTnPSRjei+MAalvy9Lq8m21 fjKWp82UNvlkEJT5E59ZJz76DgAxCyEgKaNwrnm5ASpou0aTz2VBXBU9ETCvt9uS4/Qkr/Q4ycT2 sOjPg4I7AEyBaom4hKKJEcJSGlMVGSRh6XZoH0sn8MReP1S9fxVa66h4NVkhmhiCtUZ6+2N6YCVL gYH/8rk5JaGB0w6/qxs9z8THInm5x/pn9jHj9TyqBEGx+HxVZNyfEJT3kkP3danLeLGzWb53SYKY HMOTavqTppuMCaD6hqwRQEZZOB8gvKbKlAR+pc2D1HSOMrGQHO001enXbce9ciTYwH2buTIwTUfk byvO0z/9RAT1SbRyhZOg/PfDC5D3G9Ai5vcnvyeYZvoAMsmr0xi55LLBPjoJWLb924prxAgz96Ig uW8bEd5Vu4rEeSbcljjuprSs3TpVPh7tLEQR/eOvWYphti6VvdIxeinPQIN1IQSSGS9RB9gDkmYS DosTtUw4CiTI2ayV57uC7gQ2zi/bpFA4UBFqhwmz/DsxAA+I4Wo+y2B/4SLxkVhcOZdFSb9PMdFE BKUdYatHrtsL/J4Q7uub1/P9Z+S7FuXKExMwIAgrIyQDe2+rTZFUxJLJykasGMBtWDDJNF5S1Jac cyzkBsDlumVzAuYiKdlklVWmQjikWkqCNCyM6kUPlB2RmpWspza97/YPw0uWrK9QrlNxSnZyrKr/ t4fFvA6CriNiXKD9oSEqvXaMDtSSFloQAT5DBNQJsZRWY1GhAuBG6STdQj8r9q/e8G5/DWjQam7L edAQ9saClHKhLE8DwQp6daApCZjX1kFXmQGPse3SF0nhV85GSwqqS5xZ2I26QII9tOEhT0Gi6dSO DOATpfEwSw0QO0H29hrGjdnLOAM9aC1X4bOhuibkkBc2viMEA6zauwJ/SWMQzYRuonfFYDqDohQN PLZ95RaglYerQA9TzPitZRaqum07JFWgOBlJxq1R32duaD4uzXLPRMRyp4OqwxqglVp/0RmAyvz/ suPjhPds6Rdpbzh51PYjyzTeGhS2N6RDneqpGWdJjWZ/LAkt9usCd93Ecj9oo+RdlG6istdrm0QX CSxA9gdO9O++p3GZpHyQ8JtDneizfFf29QIrwBerW+RhImUJM4VpsQhqFHfi5CBk9o5/Z6VcJcHw uxZ+qcMaUuBW4jvK0hG6p+6cr2RKGENWWPXTOlOHb06b0l4JIL4JBXHai45rNWu8ar7uCMLF6gyo JNyyeamkkAvv2AGPM8yMFgOcjhO7hLZvG11x29BlASJQUA0BMKpSITuj2y4V1zlTdCh3FI9e34nH qs4TWKAa6QQ/26J+wxTTD2QQqdHUOMBXkIOpFvBfw0EJoIgg8qsEVplavIXR3SioVVNHOW6jlMvD Y7VYL9+/qnYTDhrZiAfotNgm3dUaIkH5xKBKRLIY6w4FIYmbr3azQqL89tcOum7sFA+oOL1X1Sh1 CE0ySfecJhYTL5mhUh3xrU9v3iCygXcD7yWxBr4HrbogRebcCkLALsLuaZ3upW1TB93Cwts9nFDg MXKxP7/Z0MGNux9guVH10OtXXeeIBHuQQ6QHt23LMdJ01HC6ubgbFYXBIfoo0QvSQ7AoI/SpcgZa DlejtyLRCUlFd+/NS3hkVx14futmDH+kqzHgGfHwEDY2oV24Gg8LWvWPgV2P9L0TltdP6prGcFSr c0OXuJDnaLw7DTpYgoXKeVvtfai+ELLSG6XHEbRO1SUmOLHIENudOHT7XVWWxMzYaHvyyWQdv1MM gfPg5ntZLvbhlUdaK4LswU2GzH6Atumthgr2LRnz09ug1vJTZvMj35uixdAiUHuXZxObOHgrheax gIQtNExrJ4LFWYrnZW4yfdYkGAmB1HIz1bxyu+LkB2cv4aWENk5IcHvmzS84Cu8rSCFAEdsJCbau 66p5E0gwWrA9yr1TQmo1lttT2d5AKcyMtT7ErCrUbQMpx0JBUd9opDnXAg6WHOzo75bdmuxohdPo 0pn/nxn5mFWjqJfO/bd70ZfFSRVvUPfIQfgHHiYKAnYAd2Bwu/UedPGhZguXGWbfYlYGT7YFy/+u n2u+6cCPofh0ujdUTdOCQxwDIWQMu+nLRwUEU4k0C0yfrZ/92K1i+livMoAatmMKwtaqOPwFVzCd qpi2fENqpg1yhozrbf7A0uRa84vb5E3QzUz2M/K+6Q4xPlfzrFQqncCWHJbkRgqJm+desVZSFyTi 04GSF9Bib+Q1A6GESZwDSpy0H8VulyY7AZruWKiMprc+YuK0gR7F3ivekcPYRCGQQi2LC/Qfa4qB f7R37uR+qUC1xP/BYOI3OGLRI/61xe4topGoaU2AJyb64JNKacCrFru4Q1/4+w8eaWY11SUkDnR2 kInnR37pdBcuBbYDeBdVx57kcuq8wgBa6kLxyqR6IEZh4n+1cqZvixFI+2xqeSerLctZWcBp82os X23OtjJ6QABRFh1/sUuF+2S5R7TR6tBP10gPmqxQWXJT46H0I6d7vutcuB2tgKmLneBXJgF78Q2c eypNDiIblm8ghxcrY8WATLq7k43xs/X70kKrTSFga8nIL4bKezngvIlLjM4jXSNPEXmnoyiK15Lp RDuEUL0w3p7gODTkhOuLLrIWDpFTxP8aMM9kdg2jGY3hzPHJJZ/uvJ8UgnrTKC80v02DmyscAHk1 rm4nETv6c1bSV3LRfcOPLguBRuwlElGooU6VqgwzAFTk7Kg9gW8MVfiVGuUX1U6RsUbBMkQPDX95 Sc04Q0uTv9jnKN4j9libJ0oaOxb+9fx0q3Fd9TvSth2BhqgsenBAygnuqUGCWrJSG16dG4m5btbh 19IGiw10p1B/m66501vjtCqfP+gCy/+3+Lt1xNt3Pmnrlxiz4CJFUsTqmPcfCtqYT0Xut690uxh9 T5bBIbF77lm6un6Q8XF9Fc7ljzlloahTDBZZEGrcdi9A+im2Thz8KyTEdxAS/TSWDsHP9E+Gtz/x B65OD374uG5nlH17N/p9nJaMwkWe3SUR+3v8CKBB9AhMzaM3wACrhER730WahE+BFXoIa/Vac7Tg 1D7lnRBoV0qe/9rJQpQGCuevlOwF2u7mMMUtdudZMwtSGdTPZAosWFzEm1zWdSis0ZxBHzd2lXqH wmcHvycYzAO9n8A0+FivqPq27nPr/g9AbYitmoN82aUDrxQKKFIORgbttSL5TagZjlVEs/yCd3/K OYV2PRnkH2kRCyVCwGQB6y3ixiHB5ig2zhA4N709Ygl9cNeiShKiYUL7a3vTDeD8jVxY/p0kj2GB /I4B0A8W9tsfQ5Zu6HgXRj8cxm4tUzZjHYX314FG2SPZK3eS65vPXDMExqAeWC9JUVFnZ4qK16Ze 1T6HS+P5jLMWw6tfD4GPvHqffj2BQaU3ks8GLbwSiHLJ0YJH29TR8Za+OP5dol6H11iH5gcIIUIy c2NiA5vLW9KBwftffY2uZKz8TSJ9O3T9SNQf8wE4ulDRLxWulZvnbzPkIIE2AFjfVY1R+kwG8XOV YaKZF2RVM54hQRh0f5tBlsDaFMCcoZnHt+ObpbvM4Rl1hlaCRkyG+Or00PT/7VXZUbl74kfgf2pQ RYAuTJvcLx9ROvZs2OCRgeC3I8bAo8j2PzhtocgeipLWdv3sr4JajzTUQ0oDt/H/HKjWGJtQUP1c ajxMurWo99UehKWdvUODLjBNqecrbghpJiYXpsqvAaGdjAJwknbvLthjpLd3yf+GDyxxAMMy3GS7 G/uEvBpCdGbQZU1vRx7k5sZe3foAqNoB0cLZM7f/fuj7fKhiZtMwxjl8vCXyoIezNXLVUE8OCw1p FCkWon6dOlgMRm6f/I3uh5DrBVYZqZW0gr92OrQKj6j8/r2xg81Y+WXEwq36Jm6b8XJTpZopGv/Y I0O3n3fTajLu3GqTVfJMGdR7Bn/O7tPJYxbBsB9uVjZYsCP845hVDFEvsDu6Qg8o4AYt7iafcNcD iRGH9sN/Yrp/CvwdD68B32uiVtzH2PmcpMQYRwArgjSJ0w3dzfni3+gnWa21F9sewdtJ4gFY5xCN 0hHsd8t73G48Np+g4wiIc17xubz7nFMfGpiCGrEDrhMGQwSacHc+aplz78brK2tDuWIGBJ7is7dl zHXkkV1KpOinz/WbzIZCMei8M0mIaunj3yz/sxAjabFSjza91vW7TfOLduKhyqRDsngcFhZYfnZd ZDFunJkI7BckPw1VbxrzXEvrDtMgRNoBBonIG8pZF8XQOvhDUdgVNuXi61AGw+DHVtO8Ii9IMfkd JwR1Li/C90qnVaqnnGLS4lOOrz9aLMZ3W0SliGCDD619Md16IfW+ThvvlheeTwNs6cmWw4Qq11j1 LXgbeN2jmNX6d2lk8jkAdJ8+YUllQdXD/4tFBBuN8R7+CNGaql2yIlOUAAOVKLU/uXDo4ryG1w7w RApCptrObhIdmmPw+kSvQXzRxFaFUyXzUUnRdpfcO12vq4NevAMVT/T64MS6jNcmArTWwoeUxBI8 rtPFgAhFkKy6lFXytqiH3g9dBj9ZdxElEt4d02zImDYuU0+J64L1B83RFypr1dtoVheaxKi3Rb+6 i8WHq2zRqZ/R7PBe3VilzzJTaQn1A1Y18mlMTD+VJi/gqGAaMcB3JDc50l4bYUvnVlmn+eYYVjDX WKJ6l3kLbAIE5jxjpIFO5+AK/0tzMVhL2+2SGUZBWeAO8aEC8iW2TSWvGOTG9F6I1U03DMgWEq3J G/yK1KO/SXrPygKYn0vhtUXLVOwbMECmZ4uYkUNQOmDIB/1ooqU9minQc7RldgFRYsx8e3izfojE Gw4YxkfdTye5WARpBP5PMtCspNh18Qpaka9Vqtp4rfvObcXdZAhGR81axJg9l9oBJx7Hwj2LK76U ZIIDcsAgZbMGLOzs3sReKm6KAGmwNrncCqYhMNbTOqWroNphHG5riWFE1elSqOTN8aDCYOLktMf/ 3vpjzXO4geEOWL4R0OtDYM+VEJd6g6EM7mfhr8RXDRfMnVtGrvfcYGdy0ZyZzyrqgyTD9Ud1AIRg PSDT7lqerSNdj2mpfSgZ8QXINWEoX2sTR/D5YLQx7DgtEGppkGzl5Dcuq1UGHtvpLWlda/BhbG5N XQpmvL8Lg/fRj8xWp3WUBNWQnTLyNRp5IXnEhq6OozjhIYuCCDTyPz2wTw2/oU+A8G/eggqHuNnH 2XcT8tOJsUxuJZ1GGUA36YLDvNXyiXQYBFt4c10VcppWzrv0G4ynstiKbUWiHOc8Tv/dZVLzR+gs 6/yCzWaFZO4uPBJ9ifNor3n208+j89tOVDK3Rf5mUm924Pr7kjvUftlNDr/b10rP5eEOkqhOo33d ryvJ5er9i5C2S//cn/fmMyPURg5MRVqDTExuBE8i2+g0nRsvD8mbmgLreryGoQKz6kHVQ+t0pcKd ozkI71vNn0p3IzvR2lCpElVL8ROCW1JI82SFhvcXb+IdgzvRGy3NdhOjMs3iCVM93EkpvG6PsWkE J9Ft6kG5o7QX56ElhlJOPm3Kace5cUKkEktkydUyeDOdSJKK9cbelimmJ1NAfSRvlwLmF9kH6Dsz DddQtDozGXuQkfMeA+sHCJ+p5oWfvSdo5I3bXskcSEas2YYq92bg3200CkGxgsW41Kffd6z01Vxb 1U/pgPlTpUQdpXdCf/dj6DzOt49KtBLLnkw19+45NkeW/WzZBE6yPFHzqGs/gyO3ZhWnsBwOWOrQ kHkQ7UtHNsFhlVMAG/r9hjnES7ec594/y5Ugyee7C2NCFwBbgj74cL2C8HZZmG4j8vCCvtLhwNb+ DQ71/ZbyoW3mBeJyaGnqQQHD+9Bv2OCOKll2RKv0S8V5HdAeLcjPcLAMEy3mCFkRuvNBicvMAKSi DHzLxARGvFPDebG+MQCp3hDVO+KT8aYNnGpfEh7cBH40i3x6vMnt4GGNJk32zxfX/J4rwHUKVMoJ 0WhFV8xTr/SkNeuGSnH1e3yZvlUlmKPnVLPgQ2dAI6PmD1oVpJYFbj7SaFkor3C+PPK3TQ9aObPo aLkI6E70sdH1kPja9Z7O7+ajXp30I2VlXSW04SOUwiNXl6HqTJaTOLPDpbBbcegMGH+zUb0w2tfB ataLMFP9yPwY6bBar7BiANY6b6PRoImvD6tLjjUkUPIj9vM7S/mLXBt8HRz7VIFpy3iRvDAtbqXO aQkBOIGmxCTXKX/nn4B2iON/LAvA5cuaC7UK3lF0Bgazkjh0dBUcuj+BeBGOFBG2Slwq1qQG3/+a 9lwqDsEM22Wud4dHlgE8gvYtjPtvWlg9wddDI0gcyR6ADyGrw/OWF88S6z4v2Z4eu6FFHYjJUSqH 6eUBj1slM9Nqr+8A5UhKg/eP1Ul3DUyBkkkdDttEMB8Y0YNJejrNtBm7pW3AdDzs+kKh/aPysdXc Xzk7gAXA92ut/finoIulQE3Rd9nAMXBEOVwx5/VTTYAp7DBj2vU9vkYh3oBWgQH3zL1AGSk58M0K sbAJjVka6vSH3s5i69i8ntE5nUISxt8AMnAfgayAziqZoQjVX6YP2hXYxb/7pY2pQ4nX2M5gSC8S U6hidsMH322O2Zaq/A5M/zdW8ScWOX1K0msNk9BBbZByrQjPYStwiwOnofcaBGY0vW+p1n/FbyX7 TW1Th3UkiInDhOSqXJpUGOpVCBzfXyS4au4baso2dnCiBtQo5LvyJTyx1QQjXL1xIUStLzN1A6kZ BYxeIW2SJRCh85QV4mJ9yL2LnPhUSPWNlye2VFM4I6fJfbygOOoBqhSxq6Tqd5f523MFF3jexEbv Yh0PExk1Fzw3zZZaVJVUDxBi/UzvgqJpG1XFeUHKl1J298weB+faPzSxqYayAv9xC98vR3VkbFPf HPpBtR8ku8krYSOXszM5NKAOnxsWKxA5mr9CAKY0b6nwGh3m9EOUg+nrvXKeYxJ9Z3MLOFuFR0V4 cWHzsxQeIy/CCxiPPmdVJS8AlaleZW1Dm5ke6S/Mf/5Xv/uwOq7wU4EDPyxEGrWMtQ4bqR6I8Nwd 292c03zzdAtgEzVYe0yTiNY1UdR3Fue/jSan6+LhCdF5lqRxD5msFBloULNqXpzTWU8rGYZWh2nS I54C0YS2l7PR+zJT1flyWBAiUwXzpx8FjRGb9MzynmHkKlHAkHTQmwrfW8Xg7bGRdAwbeUNS/xxR aCydOaiVuqaCLueu0dW68J5PBDxJEB9U7VMfphrgcaaKLs8t6o6Gvh9ptBw8F3xksA832ZFy9aoz X8u8H9lYtFseil6T2ZoPkDHWZC8q4o2oboWYAmy1mi/uXtR+AuJNF/y3cRj8JWwRX7ho/LLVWjHt NiddH3PCKTCg8wOk19Z/AqKhX9rqRCkIz7C0H0HJp6B9pv6cQ+tAjsu4ygce27JrmdmVx+LKbESs DgKnZm0VKP+h/J3QqGODt4xhgREd+7+ZBrePu/A2oazku/XI7Sw0TS4jhyfRW221xWxmFfA279rm jLAcxAS536lcYhBFiHHqo65drTsrnM3odYum2gDqwGpjNdtLCu4whIsT8mLukF+hRCvohpC8edrq AiYqC9an/Eo0LRo2JYvSmgn3Aa4mqin8DT3lBWjbLSUR24fkjHFDWQTI/hqZ5lwFjDqnCbmQpr9k roCegdDPwi9V48W7wB9ChD8hdk6/wNpS33MQubcOBbRpHS37s4lnQSPg4SNm7FbRreccRypYDG0X eAw1WFcdjG5Uele35qIusq2Hz1hjdsGRD/R6t5oSaMEZ/bpwjaLipFabDZY7hYBSoukoFApu1EAE evckJ8H2yG4Nxo+PS0bRuqXWXW8cwH3GOOyCMnW8vZdHoggCMHyO7SY6nmNm7+tFWCk53OC50h1z GIAsCw60ZJ3NPpvHXTogqq6/XDCIS43FE81i2vIFyRqNRPRKiE5piKbnd8r8Y/YBRzBhJOoWtgqx uPxQQ8ADcppfSpIv7fjv1gRi7UNkhFtYaQJWWN6aCvanta468XJFxbX6llcPjpo9dAdvAtCI7iX1 cw5pmzw1Z8klWnTFHsQwW8zBCFB8YzIiXg8rvd11pkp7i2TxKpLuf1KUBQq4IaIOiB1kX+KhVaYt xkunoeOMQELn+iXRMpeG4cxeLbk1jxs4A5WbVABSKGbZMjICd+L8vaukEqEfMl0xgCV6ptbVlJoY TBs4h4Y8Vxu7zjGWri4zXILg01eNPOKhIrrIkNXcaXtldsdGjmH59vg6WVOnK5fj9Utw1R9T3NGJ XqdVHIM4MIbW7acEVQ45p3QxaWT9Ip8oNUkI3EWzD6w53f0an5s3Dol4Kvv47MoRcPy6BBOv751e g9V8W43PWDklWEqihUZp+fsdDkszkUNLR2g6peJVSgVEwVpnPn5IJKo3DEpk4893zBqt260omycE QUp6PCikoknrS2CJvGjJ5FzMRo7HrImMYu6cojB4ZWsyERJaZuRAJaCbdfQDZwQQtrPUvlboQUnE sXGe+pz70aWeLpmsjl7HnQney1uUF1nN18zj6/D4tD5Feu12DGncAGkSeRMl0c4ohVtaVjTzlp+I LDdFlM05AreGKOuuAPkp+/vEWaOjOK8T8zTB73PP5tYsYzOAwC182EnpCoEGmlfK2khQ+9X1ORwX 0Im+rXS2H2q63Jw+9BpFHugkLo/KEAdPkF9nddaTpGVNmvgYrpBlqDhcCZjPNRJhfj/YX/p7gW0c YT/9UuNUSRPiJ4S4HLb0BiH4pZFqwmsHk1hQ+anBIoGYqy+jV1qahhc3B6p/Ixex98Y1VuGurFlI 8vQ0yEKUKRKNAEuVWdWGd3TtPJnYtIZTw1kHOti90Zwa77fAmDlKFvkwHneHJxN1pjzdOxelysL0 UZqVYX21FBqg29z6ZmLF31ERWdoq8odGZkcukaOVv2kBouC/mOF8UE1/g3IHScvV/zHnrPKXipkg Gh8HzfK+rooHWvnijB5CyOl7dWYA1dbkGZeTfMmTDb/WWjBKswvHwsg6tjfU5PrUsQAqjRS3mcAx fVY221rdec2WKU7EedOCpsmLCWnPLMbRc6umdaZNrwBZ10aL3azU1wCd73iVZW7iDHUcSnHmEBHW Z2zgejlXbU+aPXuhK/rQIiZU1jEu/G5/zGEcf5jSmulK0mfIgMGLsWHXKVDT6ctT8WDxMvtr/q9d g6lz4ofKUB/UuvIZf5Z5V21ehly0AtOYGyW0lZ9vWv0HqdKjvHFVqEicSMEJCgE7TYC6ds2rP2iB u4Z4fK0cfMzrJZV4mi3QdsZBdalbg2UxMu9dsRskcJn/WLRbaQuYvNWrgU6PpjUSX0kYBTJi4A8w 08etq0XovC82T2PBrMZQJtNxA/DD/ZSdcqIzmnNMWfwqzYjKGqqCxRJX0c4+nd5lySOONPk2aP88 PDXKSSdnjNoin4uhBSs3i3B0E2utBNJZdGWcsHaMz7pgpo4i+9lyiDg8Q+YM+2WrKCm7bOyrQgVP 5UOlz5RWmYSCh4gOkSAETmbyeJhOMm8vGBkWny+hW8nnesdd6/d6u8ND+jKXU3Am/SFhE6OKs5EY lO6ISdE1PFQZVkIplyeEBUDWT2DLPt9wgdUoFq71Tu/kcvhK+PkurXuf1uFJIo/hrCkxDCmdr6/U urQVWSinegidDFmo5NeqAkO6a/lF4M/8fuxxVT91fwM/tkyVkRhIBmee9/MZHkRaFm0T2SM7P79i 6T4s7tSqg95COuLoUj61BS4kYnYRYnWQMErj9QJS1jjDnoTewIVzSLZyMsOF1tqOMdKnj4s9Nhg7 muizVa4dPEPYvPr8SMNstjqz8dfgAmKOYglNaasE5PcntghIOlF6bfhfl+wWO21knH4h8GgvLOJX WFGMQE56o/wIrXUUMjXTTK3IcEXg2UAfcjkiYyP+kUVRQfz94kse8BV5G0GxXHPvV0aEwq8doyQ6 bJa+ejFWqxBKdgz3MJF5T2b4zFyGDhzfGkBsWgLLER7EJpD5wpzFDX9aCtapCXeBSAUFeQaXtDCw 8XE/1ZBSJ39kDl1EOTr4i4Z6KStBnDaZkJeHkR4TH0iu9F7GVG/jwHJgbwRz1flK+rB/LZY1rpYI oumUOPMiRGzYLrvuyH2HO1eWqZVFLnpOuWR2c7PFjY2WyBqJI5XwC7AMTOHA0ZBsYX6dLdlWco9O opUvk8zTWSHlP6Fz/98rw265tk1lhdOmRYptudlMvYHTaVxeVjQxr7w1LoQsiYth5F/m29hLHePt qyEh29evZHjXoiOZVKtmgulNgdg+TTQ25MFQ7XLKl1x592re5AZC2NSQVNe6qTD/KG6ghH01YJeZ 8XW3FemUJjE0lcrpH8XC7VhbYv1uMtFwfCqYgBMIYgPFJktqz4yHBv3u0Qf0PRbyRwgbow/K2lb6 5EeBBE1fYaVG1NdYEqWJgIUWDxCCR3IunQbfzSrl+qcwERKbaxOQLCVzub0alp5BiyM9YGNdjnD+ Ll3Tt6NwkW8SC4LLS4pcDa59/sq/7zyPr0abEbUYZypLTGfAOOOERWdCo9LQM1oStBsvXDHyTFTd afyxLOTIuye8try+Bo0BJB7GGoy6vTeCy6Tbw+faqVcaK1Zqijr2XHI6iR9gusWvLyWJ/9ZyoUo4 6tB74OUU/QXG5CxFFVlsfDoHMOtXN2icTrs/yQtCFw3ZK+a9uM/S+RBoHStWLZKuVtkqI5nNYqCn PFu5mrWdQnFWiCW8tWcn3Bu28IDUuMoJRmVAT2VA+ri5cHz6avNp87uzj6vlTCZjGd/8Yl4bSL9Q MJq0bBN9mn1ONlU+d/dKQC4urkOPix7ag07phycD/zhPZDa625ZMVfb0nz88fNhL514tFF2bkNmr fOwwoBzDVG4Tu+O/RLOCr0+kLGcfsTaTYGMPuBCeCDMc5mdL0cr/KPc6ttDooWb36N3FcAGo8Oit hOgZ91QUvE0pUBBgE9KIJxxE+qZPgrSdOv31ELno/DSB9JZoJ8//Z0sm25fUpX3yfNf0znWBLK2B g4BjTCwTDuQ5jUTf7d9MCg5BLtyWvfjoJjsOt4wwR8o//bJEvmw7o/eHHvaiqVzbHcO3zggbTqqJ eAQo1dkY+LCOnBYqwUR/3ClK8JhVkTfeBvclXu0RH+8apevWBm7aCDWUkRwKdn5zUdAiO/jv8s55 iNi9ZPL0XbvVB5kAbBQYCv7CamzjYdZME1Le+oTPIPv5pV4F0a+ayRhCXCS2SPM85wxs0gW2++yV Rv5I6KJ/xtfYM9TCQI9AIvbmUzX/RQfHpCRMIkVZVZ2pZyfEB9h22goknt/CQ65Z0o+16hPe6kSl rpEjUmyO6+tISyOjfXHXULPaPsp408v0DmwQ8py7bGKThZvU70UkqXyvGoMXy7XHQX3Qe8K2fikF xunrxV1d5a6fCJ6T5vLA0y5CnJpUUuk3iyGmbnQi5QQ90EwSiTVxMmSZPcpsstggz+Bmmw11XxFT hiR71gWo+sFhr4VOMeQsOA92MquzXXJSBca3c2xkOLZGGRD8HmpQbUg0JTaDreI9VY4cheUm/YDd N5QQhBuGyZ8FJqdS2rts0W3beHD9fC7Qaj6+Sr2m/cyGGkvVc7lWtXb+9QK12qifczGWyCVkOjPc D0/Yk8saASson9+juW1leOY2JX1E/K3z6hpxLfI3bvFL4Uako4YWK2xkjMjAS96WRD5SSzGOtCNL KbRsXP0Yt8JhgUFZrmRb4Tz1JQalPkau+Aqz1Yj+SbX2DvfIKEdKzMloYD1qGNEhJKs4aLT3xDwD PSSL6axCNcm7dae7eDphTXHzo0/v1xi6rLm/hlMAmhdwgH4u9e7hNu8bH5a8QhIUQlK/5LujQcBZ BJrfIYDCzUfqCFzADN9+pJFpiZQfDjLucNruqwzGRf2lHAJhFmyIKZ9tSWbHbniR+/ISVvoIzIZb ioG73Ds8Wnye3ke2Pf5zRgYj4N4GuNn4CM8YRpZLNPsUTydDmJvZ3yCAeJteQ6f/0KFNpN1KPCWd w+XZVCisPMRmVeNZ2szcJNPFuovIB28RJeAapFovChjdWQSHuaFKH6XeV3hm4WSMG4P1sCIcsjkE G1XubQ3PXXMboJHusWwMGUBQ/EAbEirNJiu8wXklQADxMuZOhBzVbz6w3fF3szU0lkVhmrJgyQIh rRwEzbdhMKfEOStUutXocc/ljAi4H8iUzrFgrdVMT1F20160JBgbkVTIwETFaYLWmI3/We10NDJK hZZGQwVQJ89UHfKwUojvjKONg9UPmtlnt4bQYB0KXCbwJsiFKY/8IY/8Brm0XrTrNgVJxc+S1O6U fY4k54sN8NxW0aGfQx3km3tc6fuE4bX6XmNiPnc29U4gv/a5VJSPdR5JtRutJofhL3F4/Utx1P7M jcftnqvVt9m67SmLKYGsXN/hWAd4OgBFmrpYDWbHfMohN1IzLwMt9psFRjz++XuAedLuXq9q/S/L pm9D6biOebKOzizMnoxl6wx8pBwrj5gyjff/IvRuwHgXuaetReU0h4WnRdiNFcDbZim/jppa1Rc2 Fm7YeDSJe3ybf0xUNoQ5Er/40qv4dASBS4YIr8JxtTqKzMH5X2y/Zbil+NyWxh0AiLSwCiahUgLw jR0bO9/ZuQhfoBtL8AlWsvm2pCWvwYYa11Vn4Vq+JOFwNsy+bpzRUHEmK8wyeowEyWLMt6q8hvB3 CIeG5QxlBvqEg9K0q/BB6Apt20XxmyIF3Yc8ZCVV4j9uBVKMxtSxbYFBksaGX0Gr5qJHw0c7ulSf FPiwCuGNv1Ftnjod5pOYCGmLXmdNplOMMtkV1AOIlopJrY+sg8N1Wz3MSAaxErhbM3+7t+DH193g lyFgeIbQsJ64QLpplSfbxxEbkZsL6cgWAjkSrSH5hgYsJ2QGT1CJ+ZRPWruBrTPQ13JzKuP19ii3 bK81ihgWMkuM3+o3OdHnMeLJbubHFquyZe654QkA5sk8eAKizxXLExf0PcFqBdFWQWpuLzTbZDk3 LQXCJPRspVyiRlx+QRhKUsjxZFh2h9kQ1uvQ0e65fFa/Rm1ZRuKGWpVIxYEElRcA2PmplMaXIVV+ CxPv3x44hcPdWKZaU4X3hOlL8gUIvO4eVzvNZjoy0D1CApEZsdxqg6350N9ojjxxL5qEkbRAQ4Zd zd0U+NfU7DIoCfo0xC1kyeULz9cfoiiJGlJomKFsXpHobE/pJ/HPHl8V7rebd1a/05IlDroESxs/ AZTbIpyInOGayzGYhrH3p6ye/mteSdx0WuqX8QvRaVQ0qFqcSphV1/VjW4LbtPQtCnQyJUujVgc5 fV6gLN4fFbwcLzLNbcl/tELautwoMGsngn44ydenfYllURtmFaKuj90hNBpFgkIVwBQdErrXg44e fITmCN20oPuorvWPijVvSw3d+6RgBy4xiKUVFj2hCdGihFK0VgYWN/Dm+mZFz0VCgQEo0Vl56+jc D1LzOY1JLSx5AmdluJ7oyEcPEAlNWlYbK4xtmadJ1ijdhYGZFJ+AxPXsnukUGL+bhfhZ2vvncnjn 1F0j/yPpZO350QRo/gxZe4C/m9+AE6p335BZn8xDqWmxKw9z/XFUhA875GiTkp83le8UH+puc7sk yDR/dXksr0aBTivz//4HMN+0/NtBwuLZqY/58QnaihYcn43UVnw4oZ+QB3xXvvr3XQMkQEMF1mwQ M1xwSgNQRs4J39/70K3CVC9AOrjDS844gllVFSwZwlb9btM4y2wh+BvBy2uc5nngELA4shxuXma5 N90FX7JF0UWloETSxPQsKoxppGeLG8Gb/XDAeBv7dqYGBZhXxpGYYXgLn1dcQ0jqxYCH0MBBDxWk JuYDQAoqq8VKmnOIbDWm9nh21ekh6+EMAke0wnQQXFS3wX5ISyVEpmuutJJOlpQ2uY4kayH/ZEe7 0BAEFy2qt6aIpIfLA53LG6T4Fn/Ghi9i6wzmbiD8eamQxI/sWxT0PSuGaOoohooJko75btGaJvJq S4ahiYqwnn8fvhBnXKb7+ENa0Jn5TTzob8WOf8uMhu7prEJ6GRd7vQu5KCHZf/R3IR1jBHqYrrRo iVodnwDnySpODczgEx94r/T6N5a47LfIaJD8nf9BBPPtojue3yK/q7tzYxjtVz+30EaA8qg90MQf Yb3SxRYVyo/hC6uJSF8bYXj0si7hyRHUjzEji/qLbpsOQEz0M/CcEBf3GlcS1rw3VdiGmluvCAIA jjXS3zJAditOP9JSdszuFhulRqgzensgtnP9jyrw0OnSDx6cfRW0bR3RVF0AbSiv+Mdq1rgJlbr2 U5KyaMSRkNWQ7AfPnOfzOLpFDsbDUXYVSSbs9qSJipGmBPFRkbD/ctEYYSeQJLcKnmSn/gMPALcN rh5oHhDUnyh89DZgWH5t80lWjBooxQ28guKIIlOezsWZvP0v5UOT6gFGmBpHx7Nrn1HyCa35GEDv NKU8SFJrtE51W9RW8VbQXlBn4NnPEU7OHO5fbxieWm3zlWKbmlNoLDLUa+YQB4LFP9jICzI96PBU z4Bdnl3enM20GIEJ2CwGeA0hPwJ6xrTMp0EhyOXhjt5t2BNbKWCgLbaqwxsia0RmRCdDfp9HI7lP 94v4AwEnNHPgqJ13Vzfq39XwBLYQmwMOhgS5dJi5TpdJki6aldmvnrCXWaRDGP5Igzn3034oPOsa Vck/6DU8pJNUlATD1Dt0o9u5y/CXHa0O7GGspe81CKK+vVxq3YmiRhtEOAm38U0MMSJAZyGUeniO WSVv3LJXd1ssCgpCo7mV7N4/GJP37gosWE2ekr7mwaZvsUVaI0rgjHXIcLXTnpOq4xhJghRpnwkj 8LwsfxbNplLv2GH7ZAO2Q4vzvlXK95rRQ/cOTOR7i+Y80zQtjOZzX36WRPcMur+NxJHCuYIU1olW NSyJrxTU7pz4gm4sxu/mKwKbEvuaOFd3Q9bPuagoREIkGRNoFKIayPEyFd+DcC6DI3/BLVAVmOGy fDJwTm7Jcm0favyj7GDxdYjyfPX8T9/2ZnQ9rR596vNmHJD/sDKbYFHWBmZKUWtCaEEzBxUP1RHo KfFCPweQGplbTNleA9vV8BSZw/b/0Gfhai7G+4xGkLPSRpolqEn/afTWTJRB49dQZBMSlq7Ugjoq c1+vsVeqtkYxv6J3CIRyZxVFCBIpxsv1qiQlEUVcazLoKH6o8npcmt6lZe7RscMSz8fEA46CnthV mldD59Y/FqnH+3bboj7qPR24wRCAtfJTMTPgPu4W8napNYOE2sMYIV+FjM8JDkJI7Q4n3cM2m+PG WKS081kglXEXO4SPLzw8PcZe+Snz9I2ynveK+Z2cHElcdMLxtGdFlRnobgJolQurqYS4kaKF7fT3 FjeL+tKETrYzN8Lq+CmUBEZHxTzLF3Ir2z6dQO8yQlnhCL045jfiI9q+wISIl4HO4ldbyomRgOVc SIVozP8mQTd3YkPujwaWMHaCMGlvnf1akjT/MPQe3ipjgg77F2fYR6+Ta0koR6Z5vWNj7mxfuMix u+Yuch61NaPZZ53sJisv++uWpNXDSZY2bHDP3GiwUp4vs7VbDhxTDRiK8Bj9MVZ42iSUETcr/U2o qb/gaKZeo20f4B8hSyoul4zu1rKpRQ+NM0eM9OQ7zrwvn8zK4kThLmp8H5XQBfcsCYxa9RdBmkpG hkjOQu138BUKCwyShpH6qfm1Xm9e5ZsLabyEbfSBC6cjHHV7jrLYu225U+qfJ7G1KvrpoC5PpS6R 4ToM4rCtsC1PMb78LcLtHH54SQWOT+u+PXQXTiWQUsliB8U6N0DbQj4oKiY0m0xkx6ybRPyhd7on Euc0W8TCWTVk87Tkl05rKeQjAl3dk3wg7BTuz8eENp6CTBv5vVXbSUOSzPUyIXCoHL299jBCP2Uz ewnXl7vvnG82DjDD6w26MNWJP6fQQRpyKJL8mvCx/rG2MKsQmF0QG/b9w4FDtP4GH2nX2MGfzOlk 64J6LU82FDQMailF1ssNFGXCaiOJNLlF60BHmsBSDBG4IIzkrz8Wzl0a86wTRlbltWVDnkx/gdTZ e0KI/VuJ8pBeo7lVgpziLsNFTJeulnI5Z0CeL9FW1CTUFbb6x4a0mWUwrARDxhB8ksCohUIp+b3p 3mNaY4A8IJasQ2G66TwictRnYEM3Wz6IFx7JPuWHj3d6q1xj+OltfeAeypGr3E7aJyGGf9V+V6Mp J/01jyfRo7VG2g14MdfMrE5wETSARTMVKjaxSZSBdDdPbgzGTtBMUZWLVSwWq1D12BaVLfs8wB/g tXldZAnSIb9R/0iK/bwdELe2GKvquj7nEPx4iE+qQJ7KSD1Ou/RUKWKplZkT6uuH+Yk6lNAKbKA5 z98FYi4Rm1M18lCWG5mfGc/Q2pDbCPuFXeXa93t1N/1/3d8KsbQSQEyHa7Sc2GPguT38hHpbKE10 +i4ptRcMSeebrsys+HAF3RliyGzJsj5Dju+lsqMudZTcw077DiV1ak20gTShb6KxkBmX4jQvflUE AJVyD55b/7qcak3wbTIh4IW1Gt/P3x+TLXKjV4rphf/sKz6BexBxAMfKJFU1mgHV7AhVUREN0oND qAzxhF1R0DTJSxQeO0YXiKyggqK98qWyYpfY/2df9J3o62tU7gnUPiVWDe1sC0r4M8XyePK+VeqS iCZlnxOca79TaITTBlaoYqxr/3iktxzJbavVw2p/4mH5Wb8y36O9+MmR0z4T+2e5yrl3pffJFuQW dH1A4ubpGHfrkiC5Qxbf+VRxuHGZ8HAA0KkqRbjZEoVs7NXJni8EjADBnN1Y3qJVCG32iAwggoar mrrc8BhfoZOo8GQ4wVEUzghpM9r6cEL2fnTcmLKQpQmbpir5s6vZBPVL2o3dLTisi9KzJBoM7tTE 1xSU3iwlHBVu4ZykxaZYEq7wCAM/Xjwld5PX3yLKa0yImawpquPFhnqLcXsMFKe9vZ1/n9ZmjRt8 ssW6N3QfYmbMhV4pzMllXDcr0CYEBSoOvpSobzZaxseR9DF9nb3YhCKijhMLoBPonWxXGMmz1m6v 5GdtOKr+eKIDbwF0lNUQbwHTB28vnN5RxHssNR8t442PtlbsdZENzDBwM4i4Y1+6uAdYT5XfYqEN Y/rSgzNCkCYmvGEUjV8BQapX9rJkBg1SsG5WyXlNL2GqmmrAmku/h3m0Fo0NfFQ50J8bQg40lM4K 2Jq8hFvKsq8gJdnGKPS8ovz03/a2C1iqGVQZVTo1A5DBhQP1Y3o7/GLc6mqowcLSdmE0noo8SVQ7 CzmcZcUMrhoFYw4/uXjM/dZr5EclAzJVTfaXnYQgsmEJHHdUh3HZXoAwC7ZHnDRSrxzPTexuxWmR lNbi4hmfOn/zhgom6ta3F2QRqjsYGrl70E9DXItPCAa4DyxVhyi+OrYTB79Mf9Q+2wiKAN/zJ0Qc lOdsBQwdsGbLmBmX9IaNe3tGX/C4Sx1unG05PyiWe1Kb8jCbkDEQN81um2kQcEmonURYNU5P6xLg BXwtJ5V6iJREIFIxty7E7TGK2fFeVoddsvZq86n/IB+FrWxZzgHao8neMCnVtOegTYpPyafPdkgQ XNgPsM97ogkDThHm6QbXt/CtS7cdRezNIzecMq2qTCFu1R8kYZlG0iQI+kKY11q0P4/Ho9HvCgiH o+vo1clL33jR7XmiDgRMhydyopbQe/9p3SBhHFSb6kukHgRYameMw0i5PawFOXG8JL0xgi/CFimp 46w3cA0Edp+xPC/0VQrx7scRtw0LAx93FKOJPCyATXQNC7z6YfFxbyzevGqVZC2Q7S9AEm5E5XeI IJfAY8PQCBt2VV2AZRQeKudGUcFnBKjUNMk8YakKo/F+WvQ5A0rP/410wjmzKugtEQUPhPNnwSWy VRjY23Botqft9D95UaoIIAX0RIgMddy4O/4b2NXBRqi+7NzyCyqrTA6MVYrjXi8Ukpl75q4DUdyr W9UtrfjVcQoMUKJLNrubGgS7X6ccOMpEJpGYHTDurn7UpgPUtYP2xxkEZEMe2tst4vr3yE4+vEdk A5vk41B4tKjhoxqDWxdDB3y8JaBUjRDywbTpLo1vcv6E4n4vtYRhrN6tjX21SlW22WW04n/Ip8PB fylt4JYvcL/sfFaN2855F6c5Y7enbCpBn8scNvYrYXaNawthLWtZOHJPqmqChfCgzqpGusSSq3+G qZEP5G1JFsMeVojWfOvUTg0xKXLM/lXaiO9aY+F1jPSnZ7WrqisAxNASk9JH9qmF6ENzofkmbeT9 zFOgB+ntPft9L96my0taSt01k+d+vNJI5r519n5rBEMFIbHXHBu/vmE8u8zdv3HOsU/060MCtd06 R7xg2DkbDsAgDKP7CzUPtS4qx0yphY6L13krJhh8+Ucjsr71bHpNPhyrGdBXoP4QgTZ+knazTgOV +2ulyD8Ku9jCBQjDRAaLgozBLoDB2AfjdWo2PvO6T54Ou8FtYymOeBBPJ4BQ5+wiLbgECuxS3q/+ OSFu3zYvEzA3rAJcsWPJF0h4mn9zGk5JDAx1obpvyPkN7vg6MBfYHtl65XFaHpOEh3aKpLYiwGIl oKitCKsYeKbmF54ca9rspB69Koms+EPDP5diaZnaFJau544lWu6MTann8kWtRsWr59TnIhx9RYNq eH07TItb7dY9EvKaoHQBU7JF10ZKf4D0n3lGTKbA9/IR+IrGbKYBsJ7ounZ31j1PHQKNA/YcRG0t BV/8hCgeJiMKRJKQlCy9wac4hMvazbxdvOWZxi/MiOTCOoRWMQKqFaQasFPHCmFYL1Oi9CXsZzik NXB004MmVbzqhwCkatd+z4jhUq0bKsdmpk0PA1YOyUJNXqnrbn8K2a+DAWZ20CHzWlq5c+bOrg9h YzG1HOvy1w2Hh5Q1w3f1VmGzsfjEcS7CtUO7dq1wZjjtbVUKl39khjdnN5f+2bYGU5i422YKBH0j m/HkVlfxDyi7QE9JwvwH0YLKze6b78jH1w2QOs4rIEk8ZpXtyAE2mg9vbCyfTifEe3Rveb0wOt8J vhp2M9o2inPLGCeMIJ9Mmrf1zI2cX1g4pJ42d9qhd8wJaxpp5tJhNfbjCcNYY39r8N8eSX+gnmFG KBvs7+vTtvHjmmYsNbLxWF5GvikZywaIGnUCOW5CzvVxfMLRJavWdYm1zFTE3liMdTm3swoVgQjA Uk8xq5f4Yy68624ABozM8yrbAD7ysnDTbHe/HgpSK137Y7bozZcMUYUnrUCuG+iwYqvsGEDLCW/C w0B1W5KHSbsAsu2ggKy02AV1HRVoMUy1KiLvtKeejdk9DrGN0oyjp4M/qikPQTFB9yiPEhi5TcbL 6Ri+11lEujsgp8hvA/Kv5Qvk2+YuieFFSyAKrZvpJv58xeVknQZUVG9KNGUktD/HMv71TsHVcF+C eJm1c+jPvbPeENhCsrOyhdGTv7eQTQ+2QtxKZzeFOPJ7S9eK3rqyPiXTQKHLvBgNYICwHSlPsLNj X0L3/l2vvgcNv8UTZsJCzH3beUlchB19d7NdJ0ZeKVGgV9SPA94pfMlHTztuqq/aDKF6WhOzAu2s lH/phn4FGYBj9veD4DgBid5CCGctYGbreQATM6Usx8mKVFhXQARhBZPOdZCx4+me5wgi/WtcmbYt A6AVTJX11exygkqZ18xXqun0UhLWyY46v1EGiRlwCPTjmmXex11/TXVmzN3ZtC1TBEo88x/x17Nc 5Pk93cFT5vwh7lN1tVTh4/QkZeT5WaSqIZ/4+mzse2lhR4Esi+06/GtmcJYplGqPuBCDOs7yox85 RDLihjF4LJIiSaLbi8g2lj7chvu8UdoqCwTWWyV9mgax8YK0p95I73qIbD81yXNRSiqvv4CRdqzd 3jaeQmeJMJ37oQgjaTCHp/XibaYR0CaAoBOPnMl5wHpD5xIVgU2Qdwz+ItcIPd+b8f+5nOhk4skL 8kePg+adTPFZ/thlboe3R581OmoCyOsb+zw6wbNcBO4cq0Nl1uLeLUITnAE5rQCsexCo6ZZIjJ5E x0N7MOWcCmTTmU7XVLh96D25Cidr43v/wogHXaSDs3Iq3nLcqEGuOl28JeVhO+HT/WARr+4AEl23 DIHPyuDhf54VxCj2aXy0VNcOe2UIdemmuykAKUYu1e737z5r1SlTgWYNQOnkOo1Uid53Dg5ghzD1 b6LA2qNrnq1+pH9WKyPLB+6JWrrWu+kopOcdxKX//KpWitbiWog0ZD4DwlWVL0SiSm6YspAxTSnD +lb3f0onOsU+ECERmc514f4e1A5afiCVEqRVTYhbhV9swc/hId9uEhSkswIs3CRStDYOigYxtned eK97JypOvR/d9xOdlML+QeEXu482Z5dACo+xaWIfvJ8SP7ITeejNGDgfPc5Fh+Y+cqoSWIjJvo/Y Kl0yIzxFNL7OPRpiXwvmO1qxI1vtkFE55XZc24YevpUNuybZV7o7yNykNOarkv0pK9R8FG+pI1yg 0oAzliWm61OV6CEPaD0PnM+TYsefjwGRB+sOS3POhHSZ1DfmKuUR3sI791vvxKFPFaOom77kutmJ a8hJL13Ba637ngk2Y9UXivNnYUIBvUJAj6ljuErHV8CzmVxD+RZoAN+jAD8mqYKr5FpTnsM0bnVr K21iz1uIyWVBIxJ8/rTSzQE5/TdSla5RYJVtkdpJOw4AQfX9f51UBkapE3trtmKRkxfWk4BZOmEY unjM+WlfYX4utxUtr5g90nlf8NEs755njPpIFyM5oSCw0zdqotunfgKa8myAq94KE3syEugm8vZE rP88dWX13jOq7Zitcaw20IAI61XIv9WHc3OMl2i6pFrl5DyPo/u1K9xaS5zlOEDWqdbAXV//+kAD IwUoQzyI49WU6jGMpy82G8hR8BOEVQhE5ZM/E/iX1eUxL6UBpVAXfscgsEreaJMKt0I73y0GyKWl STkxCOcM+szyn71a07Ot4+Y/7AYcQ1+DTBpqznFzaMpPdV4b+cmd0yJC3UQnSBxqEaFrSsudLX7V tagcDkehpZlgz4ZxxR7dM0GvYsstqtHEepKHrI2TsR1pmcZ8PxRsQCAQW7URcf1HJE/vz4z6JE/X canzcak7qihbZT8V2prZ66uvWiC7d1cjoXwuLac6aceYbUGsXOrlPl8Lm3ZuUp2ra7rSbtwiCi1E so1kjIQNaxSokcFePZ/5vOGVIp+cjggIMAmbH0JDH1yfdx2AtDGZ16ZvXokqUGFL6gPT5L7OHb4z doPGJIgzxwEe3Gh8ETcn6FjPxw4DgU7l/GQOmTPtyDLZRIs18RpTbspzrcSyz9V5oTV162M0cxcZ D/3DOvJtgx2gEKQ8C9q+DVnKhuYb36kJTQwbCU2+V2NuCWHX7/ds98CQ3MBNOGvBT9b+zkFr+hKh BcYh13Jj3aD3AsIomEJRdq0Cbz/C7jTJs9sEdFnmOEQQYT6s9HIYWgW6gKkqrAug96G935gWzTkK eefCS7e6zJQlybzPo3qt/HOXdDafgg+eXHg/AE4OzMNfEZ3EF6ejrtiNjU4nas12J+6NBA8DnuN9 zgFgqmuTAI8AsY7GH5yJRKtJhh9V8QHpQzUXhJiFiBOcBNBOoE1lIS/veX7ERp4LczB6z4f6M78T +d7mYOLQ+9hQm9nRL0TB2cHeoSGc7pjvB+UENrk0n4G4dGca6PMDNJqxCzbsPmbX3aQsFbqx87H8 Y/tdcLQ7O7FOh9R1K0RSCTCoExOqlTsSIyD29YaSTeUW3/GKUCtrDfKcxBAV46WILFnN1VMk65Ws wkC/SH5eRvM+dEPbBzuY/SeKMCAlkkNcMvukIaAJHNvqmXtbKnEQKFEyQkrKNtvtygBPlY6yEyBo 9uCmY7MoJR3uJjORT1y2BfhPXqTgDx46zniwjspO0Ox+yZ25SOjxO/ZH0RKatwMmVynlD6QIPeg2 ajg3ZE/bf68pYXDggyHzTezt2DnEcIUxBkO4ajtiUdnomQxNaVkvMR6SPrF+cM/TWUh2aGykKMWu nWyATzrdlktYmBUvldvW9oGAjWHF5FLAQBs2RpGronGG0TJVZbrE75t0FNm5OUOF1d1hd4TDkXpN ZrmBLGqZZ0qy7mlKfOV+flDEcQrWEVq6jGjvW9bL0TsG9lg2enSTE+UmZLIXdzzqf4OcF9p3DK53 4U43FZXqgpZUJGyfumdQtHzzlgyuCIFYwt44LXyFk6YCnGx0/jQtcJfJpBe2QxipFwh1ZHWr5H1c vDVqx9ZJ4edQkRDQl52am8qdqy+apJEVDpmqGmcys5vcGfz2rB6IjqQfHdyc1QiDdCKtLTOhKjPO PlLbHNkF7VUkiP8zY5+oUnibJ3YJH9RKB8BYWyjxKoXmFkjp9uHkEbedDLben8vFT6q6v/v7FSMX +SIdEvfQxSgeITaxkBjfMjWAXik/zDy9zihnRQ3Pwu022U6VmQy1vY5wB+ebhtFwMNcyXawZ9qBY SNihMMMT17r+lcbUGgLD6ZwyaRCe123eoy4XpaflKCSaUYRfONh+WQgQzwcqdKw2nRG31ptfr4hJ du95zQFNlHmOETCdtEVyiODswszjxJzibBHfDs/uLqToodgiQ8hb45SYHUy/XLbZ0vT/ShD/VNPk y1e5zkQ10mNQeF6oQVmE7QniAP3wAVYZWd+pNSFipu0diDsWMMMEjmm5cwWX9FHNiz/Pzj2rTIvP GY7SMVZYo5pQO4LwI0N/5D/MhCQS+ImmZJLRXqziHxf62VeLhPZz6uumylsOkh99yIPZc3YvqBjo JfNw9TqR0noKUUKfHTrdwdoVCFWaPfewmCfwpcwCGpXV/g/iVmf2mm5EGScsrYnbuxqigIfLKodX a8jRn6eLRaowz8WsbhjKBA7waARizMFiePTE/dRm1VuXSjobWeu3SrD6FtA/xgnzygSEmRWVHQUP 6TGChOeeUnVrYyeBtRCEaV1tzroqDmNIuQvc1jJ1xQLbDlVFQkw5vTES9AC9HDqsLeMKbPqn38rG EVOg/8q3yACMzZgxu+hAUqeHEw7iXJ62FJmjqi00X+vmG5L6NFwebHoAExI3bjqAT631BYIPRJca mF7KBINGy49ZwSllLsNyJnHkH6qWk4q7/1iK2HbG2pOPgueW7iYljjTIZJHrIXZXjld2WyyxdjmK duvww7YVW/SWTKWBp3ECCYyMDg0nDjUnS67ehxdinwnmNgWrSyz5sAXk4hXgfrPhi8xdQJQKH9ld 8HOI+TMA4iFFdnYbnCf/VZsz3D7f5sAVI/lWeKojBo6bkw10b1g+yFolzQ+S5SxYDV2rSQKHKlzF IGqRu+ssIhE8ZZcbwenSaCKI7x5o4GRHcz77gJ8GNjGebL5wrX7uBL8iYUE9PmyTTeJTwmh+L2gC rsfbT9OcEUi6uVMgJJkvCmuEMJeL+/czUvvV/BaqYMjYxgdYtSuJk/zxdrpkZ3VzntDlCvc2lH4b Z3ttdsJIRd0rkDWHVnnvjOFW0ZwvRUQZZ9oklAG9+LG9IuWyS20/bfqEXKLLBp9sDb3if9HRUeNS U5gzYrLFM+ZWGuFA8+zIjcOl8uyWGBVcJwvup3BsYXHdRi8a9iNq0zZKpBTG0DPTMrG0Mhrvy398 sZ/acV9Aqa0z7b0CrkGjIL/gjRxjDRWQQHB/MByjHdNEAugXkXi3KC9ul+MNfPhcz4d8mmJ6gTdw oD+nfllutfmuYdwH55/+YSSMzoI0ErfDqrMqqIo258oPKuvnlOs1J8oopC1NF80TYv0pV0QZSViV Yhhx/PLta1e/iWRxQDDhfw50j+cjGlbM22utJIYvKPUvWufd7O6wFrQHILzzb91QDMQWGA7oPZz8 lcVjiUmXftlEXIhlpbHbCBTUHtNzBAVyTxRzr6v2IRaZGG0puEWWN91ac6cpp9qEw+sODJmFw8e/ TskElUoXADqBGtdVTfCS7ubeW6FpTYwOVtC6aK7JrIEfv4BHU/UFPdfze0dJaiIpEc4ZqZc/A5up 16rM6LlznncoOCAuHX3m1k7ljf9YbQYStBaT6kRrIcLJIqVGy6Kf3Rzpyvfgv3ObiC8EHoLVmnU3 /nVKpkOuW5OovXK1tVgQTaq3b2LPl8U3WzTrFhRRxWyzHRLoTktPr0U/RhpwVl+RFPjk7XJFx2as fJ7YBgw9z7NRGvSIPLSsIOcNcXfUTdU+HEE47TeOzBtvmPlF5lTBroIDiyga8m93NPoRZ+p+o8T0 zIm+oBmrlvh/WYiicWoUMQW6Sl9swjmWjpAaPm3unaDO8rXE6gpzndoxBt5h03nS0ob0MiaBA0O8 bQhY2yoL4OgIN2UlipttQVOcqDQ/GLgDqQYY+2rlDwd3J1Ek+szwZYkFSLiOYCNX5fPoqsCyNFlk tlp09Qwr2784+XPwZBrMBPIf19i0JTXSKoFFSC2n6D50Y+Q1QON+lZoIsF7nWObvgzVJr+JPXC6I ROHTgqf2tTKxSaREAGZmzd+o/5lL2Hx4UlC16El2Ibr1u/hhTsZq9j5mShJb/w1o1MNgMrI+kOS2 SJhr/yZGvcKx1/rccClzO9TWW8/+Z2h52fBsADGaU4BcsiarE+hMMRdLSrQkH1F5dUXBey2aMR9z GPcKNDLXNTgOdpft5ZKYTJAxhgiBAhqAFwWvZRcK7kyCKap2g1O8UfWU7bnzk4nDRx89c5UYTQSi 6y7diyVq93Y320D35QcyhYKw4FlsCai6VH1jwpbd9OyvYlaDO7GBhOKCiHbsRIzH4UtrdvtRcBLP aDs/ABuIZzuAXV/XWuBiY/pTb6NWUTAuF4aBLGDLne5cj+hih8IQ4HlSjgYdN7O3lEUY3jDG0fk1 lJ441ZcYFuy9osOBc/+DGEepv+sYg0JmljOI1tjh8sRt6uuZ63iD4UJzT+8tEDvdQrTZTb3HGf9o qFoUCTEP0cvgmt9hulnKvs5ujxjw+o+BIQm/uU8wT/wP9V+P+CSxYhhKpVGYjzdU+Il6sRNvleUu NAOjdohJzuJC25wWxuR9QZfGpzA0j+WXmWfp0Thhx1sCjfxZI3vCXWgk4jbSIwIMn0rn7r0SGRRY SlXUQI8JJHDzjqjZ7owUyXm5jk/V+M81Hu2Effy4ZE3zF2+UEbm+1OqWVYLskpW5E3h43Tj+eR4x NbFdVJDiLaZoTdrflRaEJlv4nu9OP+cgvw7I8HYrko1gA7FaBa3+7vOGUTsVLg2mKSL0VNhN7f3L 6QqZaoVjqO6X8bMfgL9hvRYnH+rKcKyO1zk6UR7eLa5U2vIyM/uP7lX40jwJjgS25yjw4fbtyCvV CCOPrWu9Ne2Cb5ySLuOVqviR1JQAzFMWeY+Rig3ml8uIiPBtPN8+uXu8IuB/DMTO8ePss8xXaYhh n2I7xfcgyd3xzQgZfa4u04XZxUOWsWlsJV1t+R6WfqQuHt3Kt5kASXUDklVex5OGqHNe3NgcO1vr 448jKRaB4jeCL5unE3xMdauvEERPIh+inR34Ivqbi7TumG9eptgG0N9syRqk+0s5nglU18+XOnnE BneGg0/ONOUizTCqzA2u4chnfxaXxHAPDtYgvdDZenUpx+8/naXi0gRyHoe8rVAPXXkKDfKhPusQ 4cgHjK1RP37CMa3668ADtFRVYXOUPnQNK0lN26SztRQb3ScTcLpDsy6xUZH+FrOl65W0K7eR2vS3 4/WxZZENLhaWkQiiSo7TU1lHacdAhDpRUfwOpy1OuvATP1+JrmSg2np4JRODEKJdWMB/nyFJ2RtS d6FC6g4aAAm9m2s1dcwsDlgRYa7JOyiFXfz54ju61fqoavCvQcePaTVqekzfz7yo1OKXPDPrIvzT JQMoc1Lq4aXSeEL0m3bhA3rWbJD4lsFFhYlYqqZe2HHnrub8pMUOc9FKnOAYEl+nqUHve8TReV9d Q1ysxbPQarPcbheU6qRjyBvCsp2xWSIfiVZmAS2e/EsGzZKkBBi5xHo8yIWMaqPqvYHmJ/JIfA/I TLuQEwGsYAxP3ywfYMpwMA3p+mtDQiXZHF27VZPTz2cJNAeH1PbO/ib2tot2ctQJeW3IIezW+9mt oguAvDt3fLeD1/E0BQqG9mdxxP/NcxcrYQMoyR7u19Dfa/dYzdt+aIqe3CGmTBM+GdK+7BEyTZ/K GKDo4vGwZk2ZRIziOjjUZMPAdUrcs4bNFmvBPLUSRVQ3ffCxkWaHw/VWBIvyyXqi3AQG3HSzGgFv Mm7kwwO/+VEBVzFa6OcgbbxkFWjEyaFY99+D/K5wOM7LL4QaVn9DSy7apQLVK8SgBaeaUgUQ0Wh8 rZrcxRdajHV4Soe+o3nOoEGnDOhClitoWYgIMQi8t6GsJENDZ99BjEIziUwIxDIZ58SxK7W9W+z3 zexKUNjGYVYMnhLGMRM0cGjFKrrfN7SBRQSL1Gy2MNOelavDtWaNgA9fGVdGm9KoKu/u9jPoJIx/ 4CWzRAm5SwyQdRleoAKMjf/qSXhQkYGf0QVjyMk9i4/VOmbc0XKGUHLSY7j3fEWwphc6c6MHN0rY vlpaBoQa0//QOFJX6HDdp1OZ2e2Gwl20jVXWDfNB9rIcfmcYriftYQn/ZnB8+JOGwnpdgqJulsrB X16+CTvIXWrG/N/bTIVlP6lcWDxRpWCQbA6PHR9yduJUbyyERFIBVy+zrdhV/w5fgA6gIusfcRLj JMaKBPs5lELHtQ6AeO78FVQnFXfxehTPclthC8EiNKa9VRbhvea/EsDxRAoyEg0f/akQfvdVs8Gv +2Yb9fQkke9d5RtxbjWViP+100E+H61e6ns98GVRX4w7RVDkVDOchpI8hREhxEITOWVxsTm5/RLe jbfbO9yjHGA//wSPUvPRjoFplsaEngDdCWbhfwaGdEg4hbzOgGFmBz+o7MUFR1VkWxvf2f2N9tvT SN/5rKeDKovk59tx8TonyUq4sJAoPC+YVyFP9UHDi8wWr4jiQnT/v77O0WSk1t4FJvhyVkAjz799 wOwWYpEI+J07+GUrKCptO7Wlw6jDBX/+oP5z7AxLbuqA0+zHvaNjlstpxw58sJ1u654u9Mo1TGdv DLPy3xyhFqX/wZN/oSG87o3O08YR73IU0DOrKPJCTTKYwT5c/FphO2touQOE4hxVjNfh8wQoSQas dHC/BN9okQJTVOHnJSK8zl//D6fcOqCn6es0jvCzHgMeCklqlVWAusFzyrgmhmBXKKmYRQzOs0aP ds7PpKGDC1kz2nKC8iuhwGqywmRS0JqNy0KJT008szL2UvonGL6nShf0pShVpwQt9tg6YCDgG6wN FgXILjuDWq63M6+dVy0D7jXlmswWQqiBnfFIbVtoZFfR1MBdHu5zO6xSmEBpbgfeXLUE0xXk5YhX HDlj9SFb2kEa4vyx+mqepcglvj74N2rpbPKxTAyRyZ7ZH4JrClGhFhGAOHtR5AdjIq7o0MRUH3zl C/11sOtciSpCJY3OZC1lHDAK9ziae4JZFecL3iSWcmLAGF4Q3HyfRIRK6YnRflpKBCPdzqlM+dbW Ik3PFbB8lgMpSnP9GydyOpI3oQhhJTyjQWBlT7T1T91Pp5FO8gV0OzzBJ8KqgdygtqOFG9j8TTy6 dSAuYM9//QjYAclTiR6cvtkytxi+CZppMQAru9OfY4KFDydvA8/aIagdXsSf2Zf1YUOfPoxpo+bt ukwNR0E9Ip3ufoGM/3g0Mq34XJx4rUppfl+n7BEfZ+hFKsUu6RH9WVlljlM57Wx4VrCEUOxmI8cr 7NLlUZ2SnDR/yJlW2F2L09KOGdglj8MhJ83CmLPB737i/vc4EF5VrbjpHfa5l6JB2jkfBrIOZmgr S6RCJnsY+tUVSXa9dkuIuYN2/PHuAhNAAuX+DwhbEuq13dHF14ZxXD8qUJxgNdquVoNcsNgQ5QUQ YWUYReDD5Fj7TxM2aRHdZRKCNa5PAEwd8i5drAg7jwV+O6KNL/CJ3j6sl9Rn0s3QSsu1+rkNGcbi oNSa4zn+2QnKx5kyLC61eojWkjXYUSwjp6kXxoKo9SPzaToVnhs8RlstcDErLObznK5zb5yj8I41 g9Nc1+I/5CrGhLOpz1n2J47/i3ohpMugB8/52FtIF+x2DRmZ2cVn8slfVRLiqiTwvCBmaXMr2n1F OxnTeR2Qxi85yDhszx1lRO6KZxQy2AZYmXmxQ83py+0xy9tWCblBdxE2EPqX388FaTfsrZ8RCgn6 W698bYdqTfGeQOIMAtaKF1rfsVolxtfDAu2K2o8v2XKtnrJq3d7MBCs6VnH/82PzNTVYKQLtC2aS sPMA46WBLsAyIL4EMSfASDtX1xx8un+yg/bndvTov6+mwzB6XTklZjopYU5D81hVpPA5DgnRM+kD Om+BEp2WhzQnaQ20Z884jjon2u2MtneUfneLB6BgbVU+BNEtG4VsmJefJFrf8oRds80a/n0ANB4Q yCz7vzqXpXSwSZPqINfQeHRVZ3CTDCVFsYKvqrB0dXv3rUVBZOHQiF79F82vvheehNKlL1bipw+4 zv0BWsS+0DkB6AAxJ/8iTiZN7pd9kKfT4PsK9WkDK3ECwpYJtmjruZ93g4c0E5huhAhQqFfaYHIP WpGVvMq2r/EoTSKUd6m/4iNmuGr3bo03kZxbDpMLefuqxMJMYsmDTn/zDmI8F9oeHrSF8alOZJ/B JVJeW1hXXErmX/RCtutjuQDESUlIPRaL44WfdNsZiTDJf8wQB8QEjQC1lfQbpjZDoYk6epsHarNn S+G3g1ECiBwWWNyjt+rBGycV45TaIKE2nC/gv0a730QDidr+ltyWC8DAtpVD8aW9uyL4/ImP5HMD gIigDc4U7d7QHNLbWXpNrKOXGq7/hpiUv4jRmXwWbReWpE//DHjUY5Njr+cEAgfe5cQGy9cIR3IM 1jkY9lqK2Aht48gs29HClx/+3k44zt+bfe+FRe7sXR9Ac8wt1lxZBA8AZ8nAOUGQiJb5gNvBMTFD WHtaN4t9kMVfmmTt1heRcCubhmjTJgmO7lhWxbMQBjfs7tZZmdQMNYanE/5l51YcYh/E3k7Kx0pW oHmAJ93T7uytFFL3LqorUxUtqNbUkcfZaeRnqoOZ8cUHCixnginmg26PBESc4vu1KXmFulwZjbH0 q7QmBJ2kwXP2SuErVDbNL7hzEjXealOzBrhJUoxoR3B/PxyE227HLSV3U9f1gKyvTXkj8lj2sP+6 rxAWFwADsNxZ4CDV6ZX+bQiBbKvKcsK6N93ddWGjLo4D5NrKU1eOhQ7ESPqGw3kPF619LgHg13B9 E/FJpDQkFueeUsuEHRXgqFBMQIqZSpAW7I0ggdus43YUgiiByJnUT4Yd4+7L+EfMcgLuVsbZ/fGK M4dMjAU6C+58kYvyJdbAGNWT4hKrwvJGvAXJcflQi2NJw8fcC/Ol8tEC1l9mYn+/eweBUhn70Dmv ++HzAVCuVXmRC/3AxIF1MOOqKbf1eqSi34YTmpOyhnNoZAMc9S/WpqKUYwOct4NXhHGuGQx9nRCd s16V/dsQ2sEbf49xWKwgtdbEFAtzVz9vet52oWFf/RFtPmv8ZgcKdIMAG9jmRKqkTCcLEn0Hrbds dl1A/5d/STVShDYV0Torz2GakWj/qXqOPceY4qfyWREduLwWZkUFD2oxFXFCls5l+g4jVnpweSoR gl2N712FCju+gFEDCX+JmSzkJq7YhCXM2zRcFoTx2u77Rte6WIwn5RSm8shX9lWF6dwqi8KNKK+J +Onz1itVNAqaAmrDkPOG8i+CCfBcTJApqcm2966QnsXN+iV7X0ZBjzZg+nP/GPnpSHcjmF5Wwu2m CoPzyNhu4RF+VwGmA0u+AAC4GVFaWmiVetIpN83WDvZwxR/6spVKvgcUHcEv3Bl1sO75L1+dmpw4 YlrAToj7iHr9YvVKa9mrcIcApeKTzZKbqfqKJgQ5a1YfMZ+SgbaDgMOS8ojW9siXDTOjvkm8nYLe NDky8nVEnzxSCvNJqGRmYKq/IQWWZ+RxtoaeUJp1RcaGtvnmO9klWPAs8cj5eDh7ynZwgvdFjeDn OBlURgPuIBuokcw/kE4Qcy9C5kuTzP99t5lMjrVDHQwn5tcTQ6UAsdTxIFYUGzcSJnqo504jVGEA pCedxqjXhCuwUZnHVqY16qR9KGWPkLNwg5fNLqN59l67vJEtrKsBwzYLZeJueCHPA7HOIXlwAd8T +eNCChbRoDlwdFTPpvLOZZ5fkJXDZ+vkFxiFY6GIvcri99uYlZNR9G3JNwkupjVcEzVn1X1vU66I HUX7GIu0hCmr57x2scq3U48xdYQ4a4wJulVrxJ6IfjV2f+rTcdUxVAMqnAP39lXadahK629mVl/h IE+6vATQZGcl6dF1eQrI+RvxZZuYW4duCAiGd6UWBSH6SNLVCQ6cz8XW2rZUatHhvJQ1yDPbUtYO IpCOVh/vVh7eTGINf2J2GEVZwGKA1ELD3dYkYTHa3unN6exaghBXmg1YOVIYIt4+83kEPmVsrxE/ ClQzsYE+MWVHugZ2Fq3okta3ihjunY9NTyvlH7boIFMnUTz9+2vXxhFRDT1uThsmf5L5uC1plmGw 4jdZrB+BKtKwibYak88FY6gNhwDd9gpSLh/egzddpFvxMefAr9wwidYVY8T4q8cGfEKn23YjMFWj QeW5A/N1gGqK41a0xDuhgjMXACfw/NHAWXHwi5BIOTLFRtVNaGqP6F3HPFUhDLSX/s4sqMSjVyRv S6BXU71KfHh3YycDe/Eh6RTU7ZwshSZ+gaPSeEvy8dGZbRSxSK2ekWk+XC5dnpbxP+2KyNwSFj1Y xx/Ht6jNoYku83ReSFIPeOlK9JfeGjFqSUjllEVZew4pjpoKqLQcIJd1vAA0CAx6CAahasiisy3t uI+ZQFj0RiS/zzuD0yRWPGGULBHdoUJGwJ8fB8FQgymRUH8MGBGPUs63KOruGHvozV/ui5rCMDuv qGD0sNJfodjUVJzIJVspAafiTCaV3T8sAmAKHhlA/dZj/1RnwdMB5Y8uoC9aLhShpJAjKwSlAFck aFHxqTi+Ur2slY6+3NLNMctbhqamVDBTuAK2McBExEBcNoRi2pftppuPr9IVfXeeRq0tIa1KdCLZ PGgnb7NhqueTp/876SSOwgSHOTi5xdcYfrWrjGhX1q6NN35+6Rdp2NRz+EHiVZoDnMrlysNhQjg0 okB81i4plRNcbyJ+0pj7KTzYpvSA9k6bG97rxu80zF6C4CU5AaKkw1mtJbCJ5s8HAF33jSY/RNrt BvziVxdwGlcddE9Zene87IEc0Gb/sYbreHJHLFLVyKG70K5wcDV8mGu1FzXrheHCjU9kgfYXwG0U BNinMExl7vXXPAsGSXfEt+9YcZDsUjgC283F1xnnGwiQkd05k8Z6YBjiRa9OTzQi8HhOLGPE0/nq E5in9Qf8fFBPyaJzUi/EUGyNwsXe01+sWqk15VANGwRzDfRi4U0FV6O5kvqWb1QY/Jw21UgzMXF3 xMZDI/gBuAsncjp8+Oe70QVtiTk/rljhPUv0ElUEZOMvU3SfWUCs+gotbz5QcoAHYh72oo3DXWlP 41Tve7ZS1pYPShd+p4by83TNNmH/mal+Nq6U1vFaLeD4Zo3ScvXvdwWsumcams8tfocxgusAMx7y qva+SjLt2qAV8BwshNgYXvbPHSWS2+bceWrAcn2iv2vmtwMz5nPI+bFgiY9cK1NIvM2oIMkmkMm8 YAqzjpsjz8eoIuQwQZvohUY55Td7Rdxkw6wDR/ONi/1TPmpUtJVCwVKPU+gWpGdgamBXcuCuw65I lx+0arubOte8q6b2dNKhLpZm2/Sj1aKnvozMsqKQjCFWPIJfmSiLp722ruQp0iDMSk2oLfpEaomq JuS0MlZlsk93xn6HNnhRGhhRR4uvp0lKbyENe5iVXPeWa1pSdPzM9u66ZxtN/XCjJA+jcWBrtPPe HlXM1/FPARwVf0aXvNx6pRTgDIiFbR9CtmXfTYx+X5ZXcsCx9Z0js1I1jAlj3NcCGxylKF+kV1Dq 0HpVwCVOrWkt8G0ulQLX0mJAjvbGGItAT5mHfVSb8R59L6Zl3uNWDNvYkm17wUvo2vVcb3Su65Wm 6BX+DekcUYL515wkEUumjwv+uL0suG9wJV+WKJ0kZBaikSm60ohwPvz1Q3kScB8TvDI95kyJR2UN 53JrvWwvvGQc39vCAkVAngT5P0JNAP+k8pKwASotYxXrq0IfcEukFsyeNGVmpXPbD87ix+qwW2jR 3qZ2WqxeKekZceU+2noVabrIxmE1J55ysozWGEmqnAa/wLt59WU++mQFqR1pXT4UsZZqxPRHQVaF pnDgM4B2nhy5wxgDCYr1ZYFY2NFSCGERZeyTuoKPx/akCCdEwxGUINIfUYAelVO/YF7xupPqc0U1 pl3JX//yR1PZ4tvgE58614Nw/Vi+47nnyrt5vQgdR2gFMdpppEyzoIwNfdeS9J58sWG/qYwA/6Fx wFrc7TANPeXCvksSr0gVQVR9XFrbeAOPSO2h3PQz25vKT83rP+75L1pMgxSsIWs8cF0q310ch/4i OFwRhoWGlI+lnYe/y6Swy66J0er/ncxbFO5uBwpFsk+si4P4tFCRYRgEt2HXpOD6j8p7tZ79Nahe QUfZFIsK1GwJGzLEFV8MpfiddDReeQKl7euRMxPmI97526lIO/YXazopRg6aA0fS/D1lddtKNn9o Q3tg0/lS5uH3TU1JJSp8TyP6UE9VUVufDEcZPyYtH+V+MuwibzoTzqPSqJ53TwV3lLJ5t5titmTS T8nXhRw0ahW3mjzhSNezH5IeTHKyzn9NKiyJMwrxLEzaCfk5faTFbL2mY1Lj7KJnLJXgQ43yrehK DyCTVd+VhzNvFTUDuPMFpgj3vRXMmILwDGbNB0+XzO1eT9QyDSeLhHlUGTqIJEWHoYPehPhHfRwv taCPD0ob8loMyUE3Glxsg/DxlRqcJtARkovTkOPjaGFbqq6H9hPeIwMVhoNATE4VjUr/8/XSe7xl GzpzisL9Aek6x3hppjmuyIEw4o/uBGsIatLT846sHXsvSLMnYgojGvtzl/Fjfd5F11LnMYhjhfvb 0fILR5xVD/is6AUrG+piykeBoe4tzpGjcp4bPZ/C0d5huyYvqlz/FJSPtTcs3Z8GyfgeoHBoGh79 Y3rh0G/BfLkSYx9FowpmTVKxcDJh8Xytpo8AYbBYTjlDeeenD513UOqhIwl2AbuzhoAhOE9wV9K8 5EpuuMbChANCJlD/NpPWHL2/G3gjF6BWH908/PfB5laO+AhfitbC2/U3uj2TBvqdMa0nHt+IFqhz /vV8RuwOnu27IfGEVP0OpttfSmLxpys42Ucq6IJ7/hvVxIo8rBIxP6Gy3EftVpxY8lJ3a8plnB6M GhuTlvGgpBuKnUc7XOohIIAMWf4Sz/UU0hhEj53XuKiwGl4fBpO7Drwh2cVpJanHsauUMDgVgVkK qUi9p7JhhQfpKPtyP2iraikU/qyKs52G2qz0rIrzj7mZ5vBP9buey/39eBKDa7DvyHOMRchyK6qT U9Kt2zXCFreKbuOg9vhFHxa4PFC95wMsMXEwf+1/55CB96aED4a+n7Mj8nUVeGEezit24DTbjucl 65B1zKZ2+RswQwpoZunpyL7ydQIalOVSI5ilQzHR+EJPUqOJjBGkeHp4wSLtcLKXTIx0HJjBXJYR cOccS2cJc/+is4LRK59H474OmeoaXLarBzEuDuVXAsPXMco5Pobi3mmf6XDYJoFUKwoMBor8CrLp DrGxHO45ioUc82ac2cDaOgjnebT7bfKZ8ITV+ReyLxRSgtfhSmrtpbbZDU9EtvTa3QNWTwq+L1KA /Y6PQA9Qn+7dB4qBGR6jOUr3I5cu/y4HYkkT969h/cB5NBOWquctYa9DKj+QoVndORDjHexOHalB KvA5iBWXB2M+lq+RQoQvvAUKRSiAudwZw3e5QbdIE1i2Kz1ydX1VzH1/DT6KlUob7Ntyd5gNndXT njRlguYkkhn2QdQZz0oP9H1rMczpv05Qnjl8PePMReRV7OHrdclnoiCyCVQ/+rLyql8CppPWaCSl RCD8lswbq4KqNGp3dbSvwcoiP+lh1SM7UN4fepomPxL7R0w6Q9Mcbwj+TGCBCdSfR8bfux5ODFiS dUDqp7RRESdT++LxOmS9Bnswz7tej9PdkfLDsYBZ/PslaTsiMJ/6geJ60nrHav46bacpE2pL3e/U 160aCEGiU3eSEX4eqMi1vQvxwCF+IqujAxP33hKLxEiBHLHMyclQdpwuic8uSwdf/8fY94EhUPku Y5uI/frh7nDKMvOcjzrGihD00g0JOKdzB7SvQS/kWW2ChorO8WWqAblStbEpJ1WoecAvjb7VU4sI +lv/282FQL9KS1k+1OqfLOVe8M6x7S+Fo7FJskjM3QC1ydqTrz8Y9tK7vojzhkbf/4RpawZTW+o8 x0zi9yUquZQOiuT0UbkxQ3C9FzmFaho6dHuqN8AyVJU5QZgH8CVHAQFWHuDMPlgypyrBtd89grwP 9hCK+WC70m6iOO9hzneyRzbkHyeh7nTWlPaljaREPTZocLYUINxGoGfH1NsEz2ccrkIs5fQoPKt4 ljAUlKZVAAm5hIOlG0pkeRPY58hOLaLOFyM8hvYoKGtq+kf/N8dTg/ZJZ6WmDbOBX81ZMOGnSAK5 TBOeo5Y3eoVkd1BNGszt4pBMv3C4qRz/jmNLztJMLtQsnSnQZ3CHELNqhenWz792KDD1JEksavG0 sEyQWkLcDISyWfna/DMoh1v6UUJLEFxSj3WLu61pdB+f3d3WOX1qP4i1WaWDjqW6G6pG5gqGeMV5 WixURS7IQwOcH7WGYm/lg7pS8aK0U+E5cXXMBFl/EQeqvUvizJseNhFgspfKJz/4q38dRyMJGxKq qpJptW5+jBteeiWWt2os9Zmx23/Pz1Vg+5eGV71y6cDXb/Us2PwT++0xGi8qsYtX/yP33+5h8umL ljLlKB+M0XBYU3m7+duDCltj84w3Sdg3IIeYP0IxYQSyCpb1ungUBPPy3O0aYuA4VlnGRL9JFfId SKkSUrSK2ENs7jxEb7/tCYelnKNbFx6lD18L/n0iEaxPoID4m+DKPc2Pm2oy1mQARUqKft1zD3wr Bs2WMGcCxHoaIboy6suuoH++bVtjSpUayrN3Y6h863YhdV9XeBvSMP4vCeOdy4A6rpFdzvtOCsMA lSQo6YPKHWQCAH52wcgWyNQCweZgPzqO2xBAzCOozHEA/K1UWQNcPWQehBim6TxkMe+T9bx8OZv1 SdLSOzK4ogii7UZCfGOcpfbtBjkAg1Q4jKPdXvl0dbDLukI3qmDoJEoKtICfsVD64LRGS+s/of8h qKbaKHqVXGiUXfnrhJa6P0/UHFfQyK9u5mHt32K8A4/Q81qOyNKm849uR9VkM5+q2vuvWbS2qxK9 e5XNx2fQgqzDHYox5R7bdHp2mv/CACBMcGjBZ6yNk+dZXijVJvWpep0IJMfbCHT7XdYUiKsrFsDD Q6e33/+fY3CI/YwWsV/ZeoA0dyBEjh855bl5EGS7Xk49eeIFrlDZL2RWzkU+n1nE92wAeKA+dI9J Lkdwi+RfbYJAtJO+uFHvdkNOm5BlYWARnGs7SxZk6ibTfceNvzjtfdCWRasfQJMXOsW1L9jWTlXD SQOum8FO51cqui1KiaAnzzulORaYpjIA7+jPLsr46jhff/okgT06+BGt5WGfQ1Htg4K1XYqBwtdl ovyx9Iawy5vGfvCQhXgX2/0d7bWbVU7iCZKBhOEy7FMJjw2ojZLL3wzpiqZxzHQGMZSTjvFXsn/J ermO0zZD5C4yybIHGMB7/dGEbcc/pPd9ul1/YpFAt8ixHiFskOCHnFwNCe1HutxcHKAYPgJ7kA0D dHDUGEgEttr9SiqXA9uP1Fv/GnqJ9/fojM+DZzaG6mUTsl1Rgy8/RYW29P0SFs7hvitW+kCgg5mi VUuGB+i4WPdQ4eN3QGN2iINP4p66r7OWnshspOa7ZdYwmS/46pRw6L3r2wDgbNKWAHW632L05UeE dTjKjGuotUHDO/YAcr8+1/XK4HLZuCCGQQo+yp4kV2lZBss1kJVw5LIMkg428g2EnSa/rRX3MQ9x EgU3pQSZD2eMA6zgzLNRyb+lAPl3U/4Yz3bO+3blHV1I/CktFw1aRV4hHwCyiQYwpKg5klC5S86P k5QCl3CGxWtWaEoIkEpuJ7GbjYfdwUouLeKXpY3ot/MKqRaF3WMobStTwXorl6t8rjxH5CZfF2z5 kg4MxUBnbWCaXghgz+V+BdJoxgB7FImtpIj6WTRQ9lUdegJGR27Vm95CH3PbU9zxWTpYn9Bv/wWd SwM/DbfmzTv7DeddGt3p5LgYTfuxRRH3yLv6Y19nmGHmCRO687eOeZWy3Zpd6Mn7h6WJnwDIvlXn p0f7veFErSZRebT+8dCt4l53j0QHEFTb1B3LZ97ueesA1hrgs1FDZWPWm8YSP541yKkDmDkO5wRj 7geHsxw1HJBsro23qVKx9TTxqmDzKaLc+UvpkUwVo4XRXC03r7o5mZhkcEmDzzWarHou84mdvMme hwrm3SMgrhHneYn0GIWEyTIPzcpRW2jPxeye3pdMwn5oB73MuJLUOnbhUyOYDmM3viJXi2trGJSi AdnNbePIJF7wdwQVt1KHb3yI5L056tx6a1rXEd9x0EpLDH7AdJ0ghKHx5qO+4UcXdCV5iQHhZrVc oJemLYnGeIhafVFvouQgfRIQuinf7h3YA6Vw5dfxNep8bYNgmbofPpIpSmdXK8aDaSDGDzRm+T04 TF0n7//chKcGdlQB/yp1ZJxiqQpK81w9xPxb8r2tVLWZ8X39Ip1fpL+mSoc1ooft4lbglpTwk5zE mYwNpTh84JnhrvnOFnzWaPXk+XlToUP5tZ9Rfe3BN8nP1omCclY97Sye6ilRhBTyB8Vk9DgUh1Gs +6VYq9EwGt4pQ5TNGOExmrI0/Jf8yC3xv8z+VPjMdQvdP76OYQb58XarrMQq0gOcdbaWnwX8PF6+ 5e2E7ThvjkLexiuFaOO24CWc8uJQjEbCpEVhEN7UdB6912+o8jxrY27hKqQchsTQ6tobJQ/sJ9Nz sm5g+w48izeq5v/mkWZsC21If0sSzrhYu1Sy9ovlVJIB39ItxY6fkRsIeQFiStB/Qj0ZZ3RCqPup ouKupMFL6QwWsRnJgZp5z7C4eB9bhZ4Mw/38AQnEyPCNIzOFV7Q1546HFLIoRycfhDP8fpZKS6sw 0+oJaNNg3B4P2hOHSvNffznS2FqICdOpLyUm9Xl/xfJ3M1W6n66yq50x594hUUoMZtGuEUvYjQC0 /ZbqPaFEL6U2vsJAXlxw8mL1EtoaFJyq5fiGyZpWEBl+VSYgONMVj2D9tLm/kdj3i1X0WYTbYEL+ zb0mAuO9IpDBo3din0JmjiKp/6tmrm8qY4UynGZ0ytUadCLIrRgWFLinLgcpcpN0AMom39SG/v+E OVrqBvg3AfbO15xDSHDwC6BDmruyJEX9AaLJ9ZsD6bxgQEA0hhDYiZC43rNOyrcWeBJbcTUfzIeS ybEAHdMgau5ozwOURMv85lJXtguGDUISiG7qdoj9UXXQ57pigLVH42JBlJzHzDuqrF0JCYeGnYbX DZ7CjNYiB487WUCZVnKRdIchL10nauTVQ1PFeo1oHREG5ldymINv3u1dhYS6YnnUX13Qp9cM5r9o 39TyBX2VOgIaBQsf8cRYEIXS+H9go9GcBTXdnljs2vnCkch2V0sLjjqwiul73M2amiW+nAi91P3w 0tapcjgIZ+Y4UXbV0RFQJbSjAjcD1YRRc50w5BOiYS0JiDO7OHv8LKDe+1Idi3w++AMUnCTvkUsM vqVJ3GzeL5OrLrufw/Y4hrIpO5+j6z6O2stTQfVvQ4d6fvnXKRkhxzU1NFVfgBaKoaRbIO5ZrG1/ Tx1uNKYhgnRe9nPZ71OjRAAscEHsOkpNWS2HCVz9ZabIyL76EzO8BT/P4Zx4jqTGrfMXKUszEfPm ZEfiY4cwijeWlR8WwkGkWjEYQ8QBpfXeYS/lRrWo9sycZyLt5jurB7wCRQw0UaxbUJqUbLJBzF9R 4T7LYVrPnDTk3YEUfdhm00S4ulQpm7GhunoPxo7zYqty7W1ImacUmrKnf4bM3f/xPn5MK5tdiPPv cnEx6a90O9g9bvnGBeuk8aiBiagMn0odQBuD3NJ4I7JFbpuLSPc5otGViSaUusvw9phCjhr2EMp6 QjLm5X7EW+VClc7icfKe/B2siBwPMIH7RDZ6AxoyZnyaMMhT8+j9ezajaWAoQDv8CgN6UF20wZRh nBwZqsBFNtTAVhkrFP7WdwZ9jd5luE+oKA2RYQ/maog7ixGl5XmiSDzGpJDoUYtU0nui5+XglZzM r2pTLiyImjnV9y10PnFonHBBlhd/2n4ppcPiPGL1rU5ROcz0CZ4SBIMzZgz1xP8zPAOVl5C3BPiL drhWVEZQBnpguHE7kQIFTFvUfcnAHMg8vzoFPLvum6+8BUSKL8SQneeRyL7LXHGP0phNBsOsYaqR hfY5w+GdzFOztKw89duyAMsBmEE2qINHCRkYcAY1xBWZVHzRxjDofdSbBYCq3AFzlQy+HhcLMu37 9uiJIPhyncceACvOmZyuI/Xhh8Bu6fHDpkCsjeloDDsZPTlp5LzgrOmuAzNMTFCvvbNOQqzB+9+2 xjggGFzGTigG1JLfiSJqf5al1gLB1X0cXe5XlsWMOhP+ZX2CGYPYuc3eiClxF8vYrDgKeJ7MGMXH apfxSMRLpWXMyiZ5DIy9/vitRobbs5CyY0UVNfysUg+b4HPCk0nwq6yNQy/+9lOtsWjlhpuShfz9 YWvcfawgAL2yaEXLZxPFo94CQcd8NRJpFemkaw/QXrYUT3P7Vg5RHvN35BrQIEZTk3Xwjc5Iei8f Rbvsgjbcjl4sLVC/ANLt8A/Xc2xrp8p6yhYx3qMQDI1L9XLrqqxryz8e+TIxSUaKxjls2hswwEBo PEWnnxlVqVVXqKxzvtnir+dSXHylBbqPGQw5MftMeN0/Wpgqh8zWxxiXLbT9tYwfL1SKyyiXVLke c6Yr/GQE7NyVKOoMDmzdQMVcbmvWnDYjzemRBVY4o3CmSJC02C8sPAUEnSFpRRBn53gQTrRah+LM jkQvINuqu9VF3otlpqkI+UDD7n2vRtCCpDLN3qI2gNzBILj/0b7KFJKprWOTOv71V/yXZmU0pgDx 7QRbMW2ojdpFVAgkRMB3JvZZ/HrpVv/vQIx7KX7n5AUHOw1cfaYA+EZXaq9njRzITW80HN8dLmrH MZTaPY6yvQEiKB6e4ESMkPgO5VetAtkVgViHMlhCheI8W8+oA34KeCcWSJZ9S4cQVG50+/dlw1PX bUCSoCc7RBtizmbFelYIT2/YJ7JcaZf8ZdIh2Otgnx5A3vL1X5gfDQghk/9eWdjfIiMjEorTS0e/ Jfs0Zq3Sf/gLtaSVh7bD81JzXu5EBHYj92MdpWmE4sFIOPsE5qM/MLY1NGelZQMc+YjANy5pYJ8o knFYKnsn04CJtnIN6uRsnczq4zPz0YPpGH48/4HSJMycBJ3dNmLXaVs/kGhHSyqqoZkJEDv0qhRw 70MrhVuK2sXmZ7Y1eQkHbHk+LduBV4gFQ7CVVY9vrJAWVf1lAv2MKIW4VgsmtWE606UENbo7GR1e 1t2okRKWxrCuzzQte+2ju0xUGpCsu3/ADVpJkLiUeEBYoYSyI+9xUqxsPWAuUa+WRjfqGjxViTVQ S7uMzYvOlFVtprRR0iodiFux1R24pwpMG8FzoAKW+9vJOsjLiZWT/Bbu8saqnq3oBZG2Of8cglcn gahkkKIkkfjWAu+gs2CILt3iv7H7by9ZWB4Rf71hvEbXNp1JrWo30Ykf/ld8uz9ohgZ2FjFdDirS g90UEvkiZZLF/JBkUIXKmG+A2vwVLgxnA8XiH2mG/LtGrrNvggEeeNpqzB1rmhajDyDye9f1Gb7m SsNb5FwF3MGR0XiWvIw00MY0JPCtJylwXhZrmiSU0VYSVrx10BalokYiHO/BHralhVwy4m5zeBpU FAq1bQslQ2eeDqCDhUH4RjFnAk2XjHRugFApspq9HDJ4WgpFW44rpaHfmuZCGcAJKJ0P7n+MXJ/5 8tb7pEgwSPuPLqlWg/b+PXuWJjBNakZT/zKcsP3C2xqM/kIeghP+1cLgjFRfbOVx7lZsdJYHtgcn F062AYxXn+8MxqBXDXDcInPdO+DECfqA/K+8/KxAkmHSXPC5mv0bHTtU2OAg/unZ9fJIsFqs3A32 GEDTGzNIVeeT2P2IX6E+CrBD3GFQOQKglLCVqa2aha6jP4VJ2IWF0nC+mq9ETkmaw2azOZiHosRr wWtCsYgB3tL7/tJWUdxS58HfMlt2wqqNKh/HvUeeEcgSwGPL+66N7iwQkRp+uT4QQSUHQhzBw92D BlG4WMIOoK7w1+LCwYdnmMp83mr/PyKbNHoXMlgxKwuvmbItvBt1uKGUsbXwokc7r5DAs60rrKmI hsS4wF4OPdZBBOug7owWGBm7cFB4JPFy1jXBSOSUZMQS0i0/oNroSmkGC20/UtaeW75gxIgv05Ka 4f5CIhpxXeELXV6g6cAm0dsmXY1v4j7lrvj9P74JRVF1mKi01C63qQnFyG7Ye0qPdIe6RiPlCW+W GLoshdIAo4MCDQpC1dTbJjAm5X6y/h7Oq2Gjg2Lt6UWacEuS8wmQp2dnj2QAWU7hHXdpfVsDU/kV C5oK/eHqTVADlNzDU4MdTIIOjZy9k0OLpzOx2Rl/YS8uPjX6IBak3Q/sHrAdvm1KvfT/EhcbURMT YcZoAMl9K3aNtpwKRe3RnPSRh5Ps/brNyB6H2Mzmcn6DECWYfdqjsYOOyTbIr0wB3Z1eVwnpBs5Y C38GggQ4Zn0uUg3bouRJGGVxCb/ExlqRyRivA3ytZDX1477w8eThqPhBAZ+/8R1GHq+eA0oHPg4+ prYUTTe4UTZd5PMwKyLdbRAvjzQ23x/+LwsX1cgdHCV1ex538JL1swJUb0/wCeoFqZ8Xm02osI6E utlRMjND0864EKdgwac7MQPdDvOg+DHhG2M2+gdKz00wjpLx6oJwUFZ4mFNRxeGawLHH4Kj/EO5z rzA15bCcdp8497O0DU/Lw5Kgq2oWUdx/sdeW6lrpFXygMAvTXFD0VXure2EPfuMWNFCTIxWJETIN FpTArvDL1p7qudSwRGzhsvmwM6M6mz6XintBx553vuJWF2D4K+6SL+H1MaEjAIo0m4W8AnO/dJt4 dmNwt2VvTc5eIoPKPA2SpNVxaeHN7G1+WDAb9KLoVRWuNJNYANER77+d20IzrNvmz4qqoCatrvC0 m7RouNJvFy9WpJaauhQP6Vee3k8IRpJG8+RONwUHnnBXlZyz0B1Q8o9/ZMHvbxsjgDoim5VM0x1J I7iPQlmpvTXAP5nsKBLV4HOoClNhC8/TxpU9K4R/gWpBhi5kZUss7/lgcySjp+PEGBQnOpLPfUQK fQuDg50sxwVMvIq74nAnQNUlYxA2FR4xIFHvnl3yO6aM/DBRNjf47VvKuMv3XzNeyfN8XNkM+SMp lt95ZfBvG9io33OzrS0xkXUXO6RnKZBAGff8DZo/pD1rqPTZvah9Sjhry9c5O+XJmq6/x23qFQon /if+g99gK/P9A1l8ruTFruxLq5iIpZ4gmypK2YV39wDyW/oBcz9U1p3ipLjtr9ZTt/0RfZKRI76C ZsTZX2tSe+Zaborzu8XhJJNl33S45d71K52++1pMJA/Uk8rcGJub/n7sxh4WONXqQicwb71YL1gE CLT6MnyvX+XxlqAePvSpF+7l2oMrrExUbgE6bjnXcL0kHjUGbzZr8oHQQ5ERYBSRk++4M7qqrmtr INzf15j7173lG0DJGMZ8d+tMMk4RrtVn1XDfIE8x1gD9ox7onUqgGR47PK3b6GqO+9bhw4rBiPdV xe22lfu5t2k+WYM7Lt+zDh3QqnLTuiSPz/xpxjeWtbDz9hvNibgeGx2SJgOMs2n/ofKNzBll7cEN kjUzES7QvVWQJ5gAMPXjTMBXkMZxqY3kwD1ZY232V9S7VBXs5S31FBNy/RuRy0kgmKC5a3sKK2UM NIos0EAWZa3zpXXqiwa9G2LwrzHW3OIBsSSSQja0tJrJnaU5oV3Q2uVwVJckpCoU3jYK10jNnwYD YkS6GzRVIpRWHhMrkHEpJnIG/Bu4S3Bb4RW3kA9TsKbk2SSQybVO3KmzIbZ2KmkBmmFJcXt4aADD eBnKMaR8ZJ4XocKu4hvaNmf/Afg7aTFahF3jqXNKsjzMRttaSYCVEI1lmVs3abiRY2I/IKcmUIJc spxW364zWIBoecFOZC6+GTZQ6OjtDhjhMJG9nUqxfmKDk+Kl6ETrlF77oL1N/AMDAKL52zSDB8Mi PCp6K0z0CDJb3zXGRCnfOiBq4tDN5tJkbTwJULj7fsOa9L/JjQpRPRCfluIQ+jEGEXskg7K3/U2+ yhcgzv+l0GtmxfYpLLQZ4IqYhp3Zmg5NDkReoktP4+p4uF3dKlDmnZtU7k7/SAtCMsDRPX5BtYat OgzEpfq/c6wOOu7rp9n1wMO7trb4P2F4sjXWoILgCcNWe1YKjvFDs7ZKmwhu6acotYv9ExRRfgZD DOe/GQRzeBBzMM1urpCTJ5LHacrQcMuHm61QfuqMCi288ReL2JRDcUS2c5brFsHgckWExX+WGdNu 2AmDEoHV7LLaUBMM6KK34ZSnOm0dsr9A5L4z66c7YdWaN3LuDPOD4j/ik1nurDuLbnGeQdjIVRjn J508iMN1QwI1eq74npyDaApgTfUFtNOnlAkWkPruyr3PobelPZ4fiqugKk/IpfizKR8THT/zAAu2 Dn2SsJr3m2jvfcKC9uRe2qksw4RHKa1GyQK9HeXv+ktwVNK5LSL4f9h2bM/HgeFAjvwWn2YMGgEv npz9sp5YnXGo4L7NizWd0NIzkH3FP846JLlNWu0ot2O+Yijo1o2dfQji0lAprGJt3P+M+yg0pVhe 8z7Qtw+o387qwS0umzEM7PVfBRBnPENFBQbqpqzM+S/blfRzaYjelDwc+rwrOTgiEkkxoFtUBc4x 6lbDegjE0SsuTuCZGIrAYbmaqsYQOHNcTE/GfJk5o1CXLYgfwN9s+7gIrJ/pvNshtwD/oz5r5AMG t1+v+m5R26SacMg+tXEjk2qQbn0lQj6AKomSMzfCTfJChaUPp+mKeFrNSEPY8AgsZtpKC91P3LJe 8E8uAu9tyqDXb6Ir5iDWoL2QSqHCtrGizGN1JUTLMXddhUolsLvmVsSmiSObk3BA4iEHicrC5juo TD0SskassgYWRO+9rYeVh+ObDYaOnb2Gaz7/46LKe6oYb387fiAqTE3v9IzGwcPIvePfoFKbkD7m pC8vuEQhUjt+UZJ6byCPDceMfd/sYt6Ep5dOzIuPAf12rO/U43ybb56/wPkmLX+TBxJFXoletHV3 ENQgiAQm8TXnF8oCNJTDhHyIesMEVKuSs0or0Y9bRGsfAGOTSg+6WIDY96dYcpbqBac6Zz6kgebD 7ySJu/kk4swws5nWSOWthTCLYbz++bbP6SGJeMKCO6EEXWNt5TZ3ixcbJz42P/HfjMcZdDVnGonn Qtyj3/9B7jWjNr0G8aIWuys4N/kBNqv/ULypz+5a+SyakuFFWEoJI099OBK/nE/DVhste+nWP4mk u1cfvhL4K97eQeqrAJ840gcZ4rzCRFPtmreoe3tSV29jrOrtcgAuAt+zU0Bcx4PRnPxgoLJqfeUP lU3IJS/F6l8yvFWUAQGL5uWGE/5DTZlKOGEis7mF0REFy9P3kTbMv6uSMTcOJjooE7wGZKN6NZJj ZO/Gvauhn8fnnyqsWZd9RlHuX6MwkGd+UYF/IQ8022B9kPJtP/3DyIJcMD2wwaQJe3xXBL6XZUZb 9wfPM4NVnG5yTwV1ULnkRAVOugTxE2wjVwkdF5Mltwh4Cg61PYqxMcbI0sh1yMBskzUQzjQ/GISw CfGpLrkb+HY6vB7uHNvTE52JncUnblYs60PPgnARMS5Q7ZORhtWDDXhm/Go4fJ205xNkd8KbOByx 4e53wHXQIzpEj+X1JMuinQ1ejPStRJByTWe5yHQykBRkcov01WUUDs191oTxCSWXiaATR4Pfbzow 21kwk8JVXZONAaqxFQR+f4qmYdN6MsPNFpizy+gQe16KvXGGtXmw36wkUifeCDx7iOo2SBcFLziZ AcLkkZ3pDIM8Nvz8f08D6CxKzSwxyE/xX8N1xiQVs+/g9LayrN3lJI4P83OTRQikzcMl0Vjaf49P bnh9Ii/1APWs1v3ZwujMqiBDqre85ihFpC1ubXGfpqmSCOC//gb07NOPLjqI+a4F8BXzADHWnfar Plibb00tV4MulY/hmUCp2PlkeDicVYQA1X+a0dTDyMTPZHwF4VO98nvdwhk0WVhmdGdEeOrsoS+N YmpD0nJRZAaxtdCVaLGz45f79bWFUvDFhiIdyQQfy3e2wc8e9cIWSiW5xE/OQ3TfwF/MAP2qujoq zQZcmQYNSvxNfmxmeloxBydZdx4gN2Q81eAt+GF7bgNtCEqMUL5Ud+fYyhlvZlIcghv2P28SOGKf c4LQemJz2aL5demxvKWhnaOx+1BuSJiQ0wNbgKfP2qhVFHcJHbcB2U1laRDEHUH74EFpRhFbKnIy G09FDdQNvzXYxJilbmR0d+F/4GwKiCDI1XuVYnY0GXuPzPgpV8Q+omsqs/kI4wD+7xDGehGqzshf xRyg/oXwI8JkIoZpx6T0pYhNt3md/Q9aEV3x05/dScbDgpMPJVKtEIxsJ90a8WJp+IAQcJCGpHDi 9AhRzOYaASGCfprUgxtsr0mgnPaoOLDhUNyP418LmRUdfFv8l1xUWN3LO1upUKUx7OuqQMJXwleZ IoMha9G21h0zN19LkgSYQo0efE1OpIT4oDSMCVCq+Drsi+y6cPUiXVSjmmm8PS2bxdLVC5odcxVm gPAUEkiXDWxDPMDShH9U3FuxfVRfgkMJNy9FQJfmgfSO9iGFfbPWOw59NpIAahxRVlpIIuE7J1j+ Bci8JwNOuw5mo1YVDwlVXVuQZ+NoAV4I3nzs8fu59yMCSBdAWjRtWjqLCAq9oWRUHthvaeTF2p9f aSN+Pb+1zb01egZNAdNwyPdM44hQRpMz+0SuM0MM4VxbWrKzzTeCQnQBBja+EJ4AhEyy737JvnYS tVGitUmtM25dUNQ9sqh/dSsnrAxMPv4VEozm2A1af50tGGOBDt5KO3KBtqG5stzrhPfAJB6b0oZq o6x7lL9FNgvjcNI+bePZB69uHOtrmRpkngTUMybQTIaJ8UA1Cu8VcxcRu26yQtql4nJvKNeDB4q+ smtItJWJwzODcSj9PwVzsiQTeVAqzkyLsXE1NhMIMKuN6tnDDkw9w3Zv5ByTxodeJk3iVCz0GMlb le/J0qMKqFikwbpWVgt1Uyce93houvqIeiz0WEnKPsA0t1BXf+zzI7KTUeqgr5gUGjkidhAN5XAo yw05OCPpeQJiOw67iZ3QX0/awTHsktF0T4399jHfc+KkQhYMO6sWLNM8nDwzp2PKmzHNW2kXn3J/ 8ehMDEJM5PAGddM6gZMbNd255xzyhR6unBGLa7IPA5/BvfBsxACnEx9TR6Xlu+G7tUeATyDK9y8y uMNueD9qkXx0jqEssbg0a80UMDWU1P64vcNLX8qlH5qHV2cDjWbdl3Vf6IJAUNOCe3C3NYO3zCRn nW50AwlxO1MsRB6nPDAjBTTodbjIMr6TFZMhZQcyc6PmXKumJMzUipjlhW8rHRM5tTpsP4nSP7Qj oHiqr1+aX6GIVTanKXMoi9uxmegxh00itjwtaztnHCj5Q5GHK3//w3W2/jBidsJwXNr1dhlK1ihf 5xcdDIViCyUjVCOdHZ+rIwRYsTC8m6xLY99wlsGEyhnWiHJaBw+o6P/XqlPUefwK01014U+u3YKX QUQFW2s/la+6LJw9WEk6d8ZflX2iI2K8vcFrpKgj9D2N7W80xnUGJbw7v8xeeowOf14ZGUciKvWB eJi0ghvFk6KIuKTQIpIrssZmIAAJpPpf9tDnIv7DnZbSkM4kjM+6rR9A5Q3StIxdvpu3EY4GjLW/ DatX8umkDPlicrqNnawBg1+emJ0lkjt6ttB2DrS1rNF5DXHJGWv2kOQspy72X6FT3GLRpWzZFRdS 9CDfWve5Zap4EufZW4OhU5/7WgaF6YvrLYIHXLPk+j0L+QHDy20ak07pZB8MnbCj4fQpxzCVZi32 fceZ4frMqp9L5BnHl8R1drwG+/V3VYn9DPnFMurF0/VO//+DFRfs+dObkp1kxcLpwOs0RkI/j48A S88BJew6yHjLZC1u7Cv65qJ+0H0i21QTrBAats6Pn3Mbgbr0khREb9lO66Qonaskdmfv0vgfyKb1 nGLu9YavvANl2+biXTmUBLYwlah7pqQlz7tONg+KYdDRcRv7QwdEtCBNbxo8C2AEHhitoU1jeuKz yil3MKmaj3jlR++1X/cjFDTjj2lzgAbXRx9ZF9p/tiWepZUmLDeLq8yb23B2ZOHJ7ltTwIZzrjh/ WPDHedMTtj6ua0UMehtZOahUJDuXoTugUIlnLN4HastAO7EuFCkeh5XG/DNaKCGuGjC+ZTfYQcU6 hTAPHTmUat1CAM5Oq+4SqA8YMkfIYO3MtF9fvN1f0cvZsurysZxcC2Q0lTs8Fb0TF0WC5PWMhC47 X3N0w1KhCc/Nkw2UQvzqR9vgiOI00cHWpzL/RI9tQDPu+WOSJ5W8fKRS1PCiHnxhQYLxhmMlGd86 zGIO7oe2fE/V5/MTiBEjMCnjnwg/4okYx5Rbc9G4w28u8u7ijOJfZUAy+sUFoIVJkEZk/Kq/922a SbH4fIHoA6U/1hX6fY0nuBcc1w1zYfdFo7pQQXgo875S8vB2QQP4ggp7ayoFMT8Vq33idI1lTs/f hJu3ndBLZv5SiNJwXU41KW5Kv0HodCBobncGfHMbP3rjsORkMIw7K9jbfdGOMAiGcqBS71CuLvHZ hWcUwPILa7YOJnLQ3RePLZWyAcd+B6NbOGqhZtQ2l9Dt9bU0y53CmnCljxOpYgo+KqUFc+wTBCWT Ubp/Ue5eHxUQ0O8S82vU1FnJhGGvUazBjdyL2cKFiGflNMK65rAO0klE25fr9DiXMecbfTolVhDN yHW40jgRE6i3M2kVi+rIT/UTv6harMs83yt9pXAkIn8kqf4XqlVFokKuM6d1LL9uuFl6VSz4esSP WhdC/i0CA3EusWnZBwSme9f25CvnaMVeVI47GFlnZnNq71jzvFzyNV6chBJ16mqpkRONbVGNaWRG VYq7f7G3rS7myJmdYKxD0Q9LDkBD2hTXw476ACEaXJREl5uVxXj90OZIswI+upLM3mVTCmqRr2Bg 4bzVh5nuOvuZHh0RHpk6m3h1FYtUwYkMVjGPIoq4dVxJ8/VCZWg53BjVOhFAwMnaN3fVJjkarNqf XPlYFj5myhRrWS9KeRjXi/e1OmH3o22sCESkhaoOjosQJIzdfB4F+4ygbHlDr6fsplao1jOCMiiH soB8Zqy3qGX3pnoSCGFi7mFcdYXqo5biW+eHWdK10jkyKv/xj2N7P2O8giBVvLI0jmzRt0kEfA22 z4039QLKB25/JNvHAsHubb9ERLBAVL9MwXhquK/PeVwe1OBo5vFiIZ4uW+9a6UemrvfwlrEsfXJw Xr/XkqbM2uyXE51uPXHqdV5UgkSuIyrhMg8UF2ScWAwWUndaN4vFb5Sj+41eJ3+lE5JRY6oW7oIa rYUBXgAyR4YGEaIKUFZ8gU9N8hmuxGXOd5Zkt4ECAqBkmTysqFmXt+Wf/WNZXuRpxqHXZyTU99rz 7HJf01jkeEdufTjOp3zup+eloF7+r58yh6VrVfLCJChl/WxSHPg2ihu2VajNSwkO1JmdSA40LcWa CS1IWh5Q4ob7+jmRqfq9b1bGVnUmjdremFH8MjJJmmjjPd6uFTV28vMj8J1bRcMTsOpckVSqtj38 hKHoT914ao5DuKAywFyc1Txk+vhfE3uViZo2cnS+76UGJskr8Q9TrdprkA77Ydidf1JTHw82R7Tt zWaNPBAdbG7CuTASonUMXS3Uhats9E7XehmIaf7DHPX3sNPuHIDgXxs+iRmZETO2LFvWNC5N7ac3 +237AFfUN5TRwFP5iplpOaz6P/+Kh+qvJ9g+wqIGWMET/fcZGa8o57lmhnJqVxxose4UfeAKaOzE R6zxcQUMDZXxLrUt0mKALMw4xaacNzckRComPYd5JEcCKtktqaCIDoWNjYbWo0eDItcEk0Bg/u4M JZd7Ro4hF+Bpx8+vpZFIol6J7GjZM1cWXXhf8mt7jcI+7uqb1X78x9bZfDUHTdjKnSgKTH5iwKKI mDslDXH7WKAQ6gcbcAZH0rFEQgj5LVa5syIT53uo66S2Fpi7UxtxiioySwaGc+301uDG1yERkb/8 sXIcIs6S/Km0zjMHsBbKzKvoM8Nrxq1yC1wQTJ/oI4R5QVuDLiYptFQ/7xiY06iuJzIHW4nZPM/u 6txUB5ZMa/maW0lvwC18VzcJfpntk+2bq3N0BiY+BVMkU2ixiiSbYAPGEDcfuY9Bjkcj+GHNdzQM vBDF+Cw7KKeC8FtQict3XiBrhYcYOyo/tA1LGtC9e7AbWa3c1zFTR3I3DD7WSKxOPmYfZ+LTyVJu dENZYYv6P1m+tYliUt1d0Qp66Oiqao8CUDbD6ZszKgLtQ14T/Vxyes+Q7xSEoL6yiyTESmxuY6iq 5mPAwmYccgDAhiwrZPOAvdfXlFBNbw4HWYujdf+eUwxisRU6tptTqgub96QfFqDKGP0yDjsBaE2g Z66lPKP28WkHj5+FxHAEwAsmEdrAvUBe6HoE/aFiSjrTaqJS2fsLftQYyKaS/xHQlMCgAEwZKNBa gJjZtgdQyhSHA5sfohTD4IMs5P2wDZogE/7wi4v0UY7nNx0SW+5o05WG3UIme97CJRTMa+OCX/Ja B/Tt56fhGx/4yQhBfzUEBRbjNMPWq4WgL+MO2XNiporfJMaU8S74b9RdiKME8S4tX3UJvrN6+zup Wact2DP9vwkQDm5EJZBjPk+K84tbGXEDMLbwXYzb62uzL+A982lUmo8stwZFFkeVotv4SKs13W69 9d3wCuEmwR3J/c9+Fj3eAQXlmcD3MOTz0KG8No6r9otaKYV2rmOulQKaQzfJYhcBJgihC9jWGlwE naFdcCAcms53ZIY6reAAw1WhPlGSdYt9ftUwEcPj34dfqnddgSpE7hIuz5C1IjyjmVNNWx89DdZ4 MA0SNSirdte4W0JdnrQMZiNe+i3cocaTQbNnJt2Yqn9Mxzc+Myaw9jZ+dyYpIioBHDjzHJcVRrae BIH5W/kcL+l5WYInzfHFvo0yH8IL3n25Ss49TQxBNLf0+SdGDhRJZexUrK8Fap9WQv6KuQCCU/ZG kUWS5kNGp47vrZG19R8s1kl7AhGJqxftQf/pY+L900HZPOe8m/3tPWq0+be/0rg8fkxHDjjgnU/h 0JD5yefd2wcjGrpLziEi+E10yExlrtIq4HgNXbqWeH4DtRQBNYIHHhf+ZvkwFfVBmyu255B6ol+q ej5EBwR9yMwyvK/cquERQkgL8jfMRe2C8HTYU9Evr93yh33rPZtbmha3TllYIHEC2a+MF5zdgDAQ dLUyZNNxme6efqQT5fJQm/McFsPogHm0QpP5H0+RAZuWquNWS4aceqwd1OMG2faaUPX77DWQ7DXl HuTn2PD7Z+VP4FDIVI5b1WGawMEa3lrUXM7srytgVMpTCj9gRApM+cyXAWKvIWjeiI34CwlPaiRb WgVe9J8Rs3Vmg+Z4lLJvWx9ianblLEEAPLRCi1V89D6ZLDXJZNTSHF1l8wrV15z+K1+5u2Nz4oQn JmPeSFSCvfvn2XJ5CgpCXN9xciFwsXPIyYseNM3OYqVGAn84CnD/Haafw+MoX1nH6R0rSr9bpLzD /o2k07xfjtUYtjrrh5OSzRt/0FtwQg7mHjDrllfL1lUZD5bRGwuM9mdYVz+P7UP/clkHTigiCj5o PPrSHZyo8fN2O5z1vA2oXixPYZDAAOhlqNG8MwgAmLqlDFqm3tjFUKvyv5REsVLDW0u1qKca4pOB 9rOklFw+/pSp+2MmwKuqDDrYgkwKenSLMOJUYimnrC4BC6ZhDyG15/vEdXWbdE7shQonypmEigcf FRGdzoi7ZbIMe+O4UiAHoYUbWf+F6c0Ya81GbpG5lQ+eC31HPPn3acCpwZIptMiN/MUOiW3w8Gus 5sNH7/yre14xihFFkwMDh/BLKuupf/LsiGvBMbjMvjwE9dELdDtKc+1yfPjooA77RamgDvP2MelN /uJxFYW4MEwuck2rASo/RD782AeRZNN5ioKMzcLzcY/Chd+GwrJ54dC/krMbbyss9kSNSgZER5jj QhZss7K84ldKiviv79VT5DjH8C0h0+UaTtjM5yvo4IZO8MJdh82Lz+J6jmf1MMEY21hE9TODoI6T ZmnWVr236/gY/pvwwIvCPL1av/1FGt3fdBnzmJj93/oEqcvV5MfZiTpyUJSjTYn3qa7LwPVKf7z4 NcicSdlvpeTHMqnWWSTkZ1R/YjbWXU0WiMaEYFbj48U0EoT9fkp4aiQzkCxJsx+ma9MyEoHAFMXM OSWWUH0yr4SeCzW5oMgFFdu0/MIfmW8vX4eNWDcLRpJ9awK23ATk9p7P6yq+rAdviMO3zIBS5bm/ hX2LkApmV0qxFxaCFFJsatRZJhtw7JS8NAitFxWnTbMcKd9nBx3LMsRM97F+fCEz6Ez44bXE59yG OA7+TGBH2HSRTDp9BzFs624SVYB7T6i3JRsfLUQtb022lUAXf18+vC9GZo7pg6S15C/sfq1b2qCV sQagcJkDUjaH3rMGaCxODSbtr/uEIYdO46Tb6uRVbFX3pv9oneICqQI1cWRQhAA3TPU5rHUJJQWL b4eKRD3mJlGLs6JnOXmRDR6Y5uI1MPI0QG94KbIhfJDjtX4wK81C1qG5h4HIeR7HdH8lGoWGePKl Cc1mau1YahC/T8jhLpAkrlzFLYeq47NDdye1LECZ+bgQZivWf8LIV6wtdjJgk3og1tGQMCtrtS4J wOQEKwoMO4n8AqV4snOdNOcBKbAgnvV+zJlvuTK5oT28NBCA1mcFlHoTg64IOPHdfKHf5M5jvM9m lX11BnoPxmDyPZbH3BT9VqX6nZrRmDnf8rbhEJVXsxXpj18PvgMhawRYFXfaZ0h6y54E9Tgpmt4v 8H9KOrjaGuWyxJjMUvPtbvDKwUgwhH7nhHxhFUnc+jhHf4veHBnokVuXW4CpGd3HvDlr42+gBdi3 CNyA9j3jaArgqQtwZBG8yoFFWLJkY9A9s97DiXE4z+V42PAQFftdbNUn8awvhpAnidha/CpWYGhz XcNmjFxT+VmGLGX3bDhujLiEbLxZVTb96ImFzPd/d1/z5D2kigxXcAI2DCjzNgtJ0Z9LiAJN1lzA dJg+XCyb2nhreuHbEjLPsSB/2HPZqMzsLJbHviURZj3k9mOHFvH725w0BjsKxRdMc8Oqz8vqe+DF p/pMpEoZJKk3zy3NLfDE1TEJ+/DuZVUFS7QbjMyKNRCa4NIuB12QExH4RdO+Dm+/X2mytBWOe1dV 9B8O0ZPrLggl5LTXKDaVMbeRiVV7W7rQBjVSFHdDB0iDjCYltZopFsALjftZiCChDqsiBclayoIF cFkdb+y8d10wgO3OpJsmZdImiL921C40Mg4SFUOymbcn+1apYZToB31RulGAoIN9yuhyKcfe+Fj+ JbihoP681v59jvlskXg6imlQpNPPAB8ohpdOfvaFvLPWXFdh7zMIV5FP31hAqH/tQ8+NEj5yVR29 ap+/VbaFB3rwdlcUWo8fDYqu6AOl9oFQTjOhwEVMpI3T5Br2HTqURIl6h9ZVS/z8NQfKWfDSUFcy rBrQavNCyI1TI+nTcNfL/vfWAmSN0IagyxhXnMBTsxNhJg6r7bh/tshfJHxatv4aRoO4Wa1ayhu2 JVgepJyWfXJV4oApSV9tnNqOL0iwPSKRKuYbRMrVQ9Ia/5Ze5UcZ7ZEiZYIhX5jg+2F7TiOpxEMz Q1RGwd+ASr0dB0Lb8TyHZKfCr0iJ8oKbXrA/2Wpbl6T3rAHMEnSSIaMMXtfdCdD7p92ekJVrghJP WupEf16ABdPZgJDrhrZi5Urz8fyKWJODcj1SjcAdlYj3pIaVChpyMVbzXDxeFZMWoBSTSa1pKPp8 kBTiGPCfgkBuiP5/ME9Piwi4hajBwB3fGcdNgK3HNmlGfckzAneVOv524fI/z4Nz0tJlYCHOb4qn 9OBBYm+W59Ouxe8i1GCuadhROrEWzR/zIPkcpMREm75SfYUumFfCc8DvbptGcbfmOOIHY8aiNzmD 3BAMXlD46MjcXWqwT+2IPWFJ56bBaSLllT6OMt7hixFRC5ceunBQJAg5qSeT2aaDAmdKRK6vYc21 z//qKJpDa9vhhqXYG0ZFjxENfQPhYIVHcoeoWYQY8ZqNOPjSov+7vcPVfGQBzE5bSZvCbprStBx6 PwOjsDlPKhgpWklWEa4ThXXdioYsSj9rSaYSSz6NsEORAq1vblG3NNv2QAqLk4SFi6wUCtacjUXh BYDe0RPbDP8TzpQVoYZNMjAExNafE8Xq6ZV4/EjTzVC0ZZWAEmFXFIPimBmX0Xo3VUWIJVPEKc0F 4DoiR3QqQh5IwtMUZtKjVHS/i3Mru+YtQ89aXDBfo1WxhMs56QuVXyQUtOkHRMJVG7j5m+4aYdb4 Nj+9ph0taUF1erd2s0vDZYgDmrKOhPbuXC/GNRv64Aqc6CTkTtymOymfia4rOp8/IJm8sUlD9KKU rJRE/zFpoODOBcHE01I185hBhEm2gSQi++Sg2rpLnjehQ4Cd39eeQsKvZXuUyly1gw18TZ6YLVOA zPAgnSNgTFbLJZagVyO0F8qMASiEdzuJL4KepQP7/mH6NbFkMKvzaITNwnbQIOrB31C9eIF//cj8 o8VcfT0ell9LDCyvxR1lMfg8wTUrKiyvLGtAqxP4Zz3SqphBwW1J/kPNUmuMxiCbVZ4g1dt2pegL U3AQQuf4GYMiygfmg4SrWACuVSBVhSScF8GmrNezLvdnDk2yDXNPSjzPWf4IH0TsCRs9OVaHuUd0 F4ZCoS6+v8MwiAHFXKnM1SZp9wj32A3FUYhw09tjMn8fWUdG2tXULE7weCkdHVWkY5RaP5DUFnOz VMXtnT8VVlcscFPITa+v5iwz7O6gbzMKF3p2KXN6HEsN3QH3Y8Iw1hh6dfr11Xa+3ZaJBPXzbVlm mDIQHdlzpqaZ4y6s2onrjo8C9v6YuBH41Behc8GNENiFtk7mQSofCRYp3XIhWW+kQZvyBZwXeFBS XJw28SAAvtjZc+Z0YSNwkzn41AFsWT6Tmn7rmC83yHCf9sy9AKGtCXHbIoFJOkEH32G6B2gFBQKk 6LM6uaZRP6IE1oMZg7SWqmpxtj5lBTv2xab94pwZ2F8Uct8P6nOn7mQparb4k1kj1FBw5ztNU6uF FMlpAhSN6ZCVfI7JlADo5YIeDrr8pEmMs0aIjQMTFxfBxqeFCB/EVoSREYvyC4Q1/EU9orPmIQbB Q4nq7Utu5/deDUjcQ1moHngwZeSkYLETjJJp7r4gYFu8t9rYOPh1StoTTm6h4MnvyfWhlsb6hN4s 0JDHLmW89fT7sDp/h9JX0TgTkEf6J+pkB7TP5ilKAJKCd881NPXG1NmEFTXv2JjLwUksv1s63dQe P3MVVY6bL4R3fDSMst95HuGrw3BXQyXj0uwMnHbKR74f/xA2GLhxrt3XnJEo/8jNOBwVTXh05RCW AxJ9fbLNYE1rsQTvZ3B1ibXTiIpfI1WDV6N1B7qqktl8kD/QzozHJj8yyCh/Dc51DVQh1WGYamnV eiCMw/vFqXNylnlM7eeoQgK4z1x8K6c9PPz0BRCWyLgobG7KbrhfWgro/FlHhk6vm4XoYdThPRwB Q5jwJlN7D5QiWqNvoLDe5kXJl4HVVfL6jFrzXkoZxq8upwsaqStKX3KcW0oKaigkdwv+dthfyP9a ccI6KpfMDmcpCcDYU1/Nziy7j99D5TyeC7rBVN2VBO9clgEZk6fMTAqLD3vyk9Yst55R1EP0oOfm 5Sy02D+blsmwfcAyeFjGYTgoF+/rxaXbnmfQU1RRiV+Vr1w6uO7tmDC9VjwPqp05RBGdhwqqHjju 7a5K2ZxntzKlRcpiLiJyZb9vH+hkVQ/J2Gt7OS0ap88Dan9+OLEobN78/dJ/9U3pZcluC36HB0Q7 2B+Tql+om9UlqHnMYHHLCi6AM5+PzdRqcOihNX+kTpW1ETGScvVgBdrePr7HkI5wZCzRbTvQUnb+ Kr2QSCfSuJ1M7LMNPvlFrpGihDDmALzLTN+dOTZeOZjIR0uJBFwEUO26qnpm+pTv6mh44JpCmDNr Za+7607WQf8zUUIOk9Cel7ZHsxFvXG+ZW9vnRGT+Bn1ESSjHWnuz2HMnNIUVFbs8F5yqsw5YzVEM 96Ve3vcvxLVT/fozwEjoSGMw9jcah4GenIcVnY0HaoLRav87BNYvZQbApEsxfiAX5siZN2wntEOG MX5OexoeWlnbjjsqeaonDfKxKmXNERntojUN8pj3SMnBzNAlpc5B0HWShDJbIlmjlnnSz9CYjkKp ZqWLrYvh5kGSGAURbrse6FPkiPMlpT6EeeB+19dYDs//EH3cYDTPD0jQUULWPtv42+09/oI27Lgq IwHtS7hPb8KtN1Jt6eI1scKQR25T5Pess2wxwIfUQ73e6+w2Oe4fP+xorokYGcyF8GOVNneMKMg6 TmBn5WlrGiPz1pcfWx21ip+UnGajDjj2cpustk9JlaEvWYtDNfW+0JZJrm7L3Fuz4AtMOJ9uS5OD zcsMzCL4c0k/xBz86cMikuHxfCjM6AM9MUSO8ee/0daLRBAKv0lcQSyVA0S0utFLx3w/QAIJjOgL zZP0HtQG4w4tmWMKj8Dsr4qooDxVOq1AWauvRrhHilwHDDKKyHjMI7+tc9X5UocwKNNDF+l12G3e EpHyXcmFfKannIEjLArBA08ZVKDixlwcgTbdphNhEp/gtW5eqbvpZZejAwFjj6WedAxRqSgVWAIO cOWvYO9HHMnY7oCBjVAd+J96o5/Ouu8aCo032o62TmQdckDw7Bfgr/s0STygaPQ4jIBhb3KZMyP3 CLusSvUT/wkhdA4+RPeeo8ciCHOmGmOW0a156aHTVaqiRi9YHh3JGgvwLdxl08xp2HKkaHqYR+Fp umMRLSBux27U55tioA93XS6mllS/vnEhhdaGy74JdV7Ug4zo8+hxWp1gdogfOZom9D0tUe2T7Z6N jN6sjQ0sdkq246N0rdrZ7O03BTRzEaeaJ+ZGReuoXcPpfOLZElbCiexNhUGB61suabksLdg4t0kp Z1rIc1UH0lt8khsdlXh/iguVf7XYiwRJfjzwlsfuBHX3fw4arTDpBUoT2KVv3GpieMQI0EP+iKLG MfgXZVK2UVwaoEYHW0NXLZUUGs7qW7qn6cuTL1CLn69g64PwmNhlemQcmV5Lr1YS1PND3NkWO40Q M/jFwfS0EkByZgIGFBVonEfcEWs+ADVCtOLYliPkcWAj2Zr8DnLAamYEyfQQibsgU/vOkc3y8RiH +4a8oDA9gZiWqmtDBPudVjQ32c4SATc1YyWVXpkcL0E3DTtkoPQAqZf2eYfTzVcC86IwipmFj8zG DMJfIngJ+fAns9Upi8iDb6tnpGfP38g+66jEcvYGIhAmtsAAiv8WJ/AaUSqZjV/XoGSagnMHx1tO uWoWioEHFnzW6KVsXax70rnP/VNENmE9rqV3gM99Bz2o70p1WWVF0591n0Oyq6Ig4nK56IkSc2ht uNMQlU0sQoXMMNTEArUQhAamhkyNKeEfOptOzJTKWhhGSELHoee/f7gqK5rUWcALFOSXC06I5ra4 LwOwzvRAUrykQeP717B5aVGj/x6NyfUpAowppbpSmnoq9zai6LoeIcyKZMYpmUa9nHRVzhIccy4Y WvoWAGjAV/N2wX/Rv5WL4S2a05HQG3CHU0fTGuPQQYmXqNQiZVi9U1ywPR6WcnOLtcrkNvAmL/ss RcWfBrkj2gZjW3Meilm0jw0+o12PeAGNo1Ejq5Yy84o9wwFOzcyGC6gyOdLVSgzV447JKQJZAvVN /C8xgxIYPRxeq5XDTUALgVE9BDq1irMclrVCoATiCqZYdfpm6fk4NuGvSVvzJLLmUDUlVNjIyzfb LnHCQr+/Nv0+4WN4RAJoI3mTC1AOXKCG1ou+1wPWe8XeYXtLvVoxwpZIMZ259Ur2tDukuOl+8f7T EFcn2pMUHf3lvyUlkKOmLIhLvaaQ2ZKHU3NglMmk52+GUbpB/4U/bYNCITUfHQglpQHqZHFVM7rY H2AQ9tATyaauEOcRQGiZikKYf2NMP9KXeY9Vt4Gc4Zt3KC2ZUCZN64uj/fdRurEmUq8m4/xMK+4f nyD8mBbyyEqfxoi1Dw53o+pZWXq69OV6j7eFbr7m/E7r3pRMd9TIybHm72H4q3KWbSCYgpx17ORe pcwjCWyBuRBejNjK/x6UQ6Fa3T1fHazoGf7W4/JMR/sAMdJ6FAY51WHz8zBun9gXV69qfvJcRGjP Vhu1io2xOp0cgi3mD7cEof5DjguQPOaSWGVC9dzzRAWbVjxnffZj+QUKtGnxwBX4e2PCrLTpFUMI NazqXmCJt1XLoguOa+A1Qo1c/6PuzFXdtPVPim82qLUKbGjiqF3Mj1VFp1vjA4071HBkC9S/D7y6 VYEsBss= `protect end_protected	mit
lasalvavida/Zybo-Open-Source-Video-IP-Toolbox	video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_4_lane_link.vhd	1	5662	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; --MIPI CSI-2 Rx 4 lane link layer --Copyright (C) 2016 David Shah --Licensed under the MIT License --This combines the clock and data PHYs; byte aligners and word aligner to --form the lower levels of the CSI Rx link layer entity csi_rx_4_lane_link is generic( fpga_series : string := "7SERIES"; dphy_term_en : boolean := true; d0_invert : boolean := false; d1_invert : boolean := false; d2_invert : boolean := false; d3_invert : boolean := false; d0_skew : natural := 0; d1_skew : natural := 0; d2_skew : natural := 0; d3_skew : natural := 0; generate_idelayctrl : boolean := false ); port( dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --clock lane (1 is P, 0 is N) dphy_d0 : in STD_LOGIC_VECTOR (1 downto 0); --data lanes (1 is P, 0 is N) dphy_d1 : in STD_LOGIC_VECTOR (1 downto 0); dphy_d2 : in STD_LOGIC_VECTOR (1 downto 0); dphy_d3 : in STD_LOGIC_VECTOR (1 downto 0); ref_clock : in STD_LOGIC; --reference clock for clock detection and IDELAYCTRLs (nominally ~200MHz) reset : in STD_LOGIC; --active high synchronous reset in enable : in STD_LOGIC; --active high enable out wait_for_sync : in STD_LOGIC; --sync wait signal from packet handler packet_done : in STD_LOGIC; --packet done signal from packet handler reset_out : out STD_LOGIC; --reset output based on clock detection word_clock : out STD_LOGIC; --divided word clock output word_data : out STD_LOGIC_VECTOR (31 downto 0); --aligned word data output word_valid : out STD_LOGIC --whether or not above data is synced and aligned ); end csi_rx_4_lane_link; architecture Behavioral of csi_rx_4_lane_link is signal ddr_bit_clock : std_logic; signal ddr_bit_clock_b : std_logic; signal word_clock_int : std_logic; signal serdes_reset : std_logic; signal deser_data : std_logic_vector(31 downto 0); signal deser_data_rev : std_logic_vector(31 downto 0); signal byte_align_data : std_logic_vector(31 downto 0); signal byte_valid : std_logic_vector(3 downto 0); signal word_align_data : std_logic_vector(31 downto 0); signal byte_packet_done : std_logic; begin clkphy : entity work.csi_rx_hs_clk_phy generic map( series => fpga_series, term_en => dphy_term_en) port map( dphy_clk => dphy_clk, reset => reset, ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int); clkdet : entity work.csi_rx_clock_det port map( ref_clock => ref_clock, ext_clock => word_clock_int, enable => enable, reset_in => reset, reset_out => serdes_reset); d0phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d0_invert, term_en => dphy_term_en, delay => d0_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d0, deser_out => deser_data(7 downto 0)); d1phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d1_invert, term_en => dphy_term_en, delay => d1_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d1, deser_out => deser_data(15 downto 8)); d2phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d2_invert, term_en => dphy_term_en, delay => d2_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d2, deser_out => deser_data(23 downto 16)); d3phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d3_invert, term_en => dphy_term_en, delay => d3_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d3, deser_out => deser_data(31 downto 24)); gen_bytealign : for i in 0 to 3 generate ba : entity work.csi_rx_byte_align port map ( clock => word_clock_int, reset => serdes_reset, enable => enable, deser_in => deser_data((8i) + 7 downto 8 i), wait_for_sync => wait_for_sync, packet_done => byte_packet_done, valid_data => byte_valid(i), data_out => byte_align_data((8i) + 7 downto 8 i)); end generate; wordalign : entity work.csi_rx_word_align port map ( word_clock => word_clock_int, reset => serdes_reset, enable => enable, packet_done => packet_done, wait_for_sync => wait_for_sync, packet_done_out => byte_packet_done, word_in => byte_align_data, valid_in => byte_valid, word_out => word_align_data, valid_out => word_valid); word_clock <= word_clock_int; word_data <= word_align_data; reset_out <= serdes_reset; gen_idctl : if generate_idelayctrl generate idctrl : entity work.csi_rx_idelayctrl_gen port map( ref_clock => ref_clock, reset => reset); end generate; end Behavioral;	mit
SoCdesign/inputboard	ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/axi_i2s_adi.vhd	3	18754	------------------------------------------------------------------------------ -- axi_i2s_adi.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- ************************************************************************* -- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -- -- Xilinx, Inc. -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" -- AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND -- SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, -- OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, -- APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION -- THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS -- FOR A PARTICULAR PURPOSE. -- -- ************************************************************************* -- ------------------------------------------------------------------------------ -- Filename: axi_i2s_adi.vhd -- Version: 1.00.a -- Description: Top level design, instantiates library components and user logic. -- Date: Thu Apr 26 17:49:16 2012 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_" -- user defined types: "_TYPE" -- state machine next state: "_ns" -- state machine current state: "_cs" -- combinatorial signals: "_com" -- pipelined or register delay signals: "_d#" -- counter signals: "cnt" -- clock enable signals: "_ce" -- internal version of output port: "_i" -- device pins: "_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#\|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; library axi_i2s_adi_v1_00_a; use axi_i2s_adi_v1_00_a.user_logic; Library UNISIM; use UNISIM.vcomponents.all; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_S_AXI_DATA_WIDTH -- -- C_S_AXI_ADDR_WIDTH -- -- C_S_AXI_MIN_SIZE -- -- C_USE_WSTRB -- -- C_DPHASE_TIMEOUT -- -- C_BASEADDR -- AXI4LITE slave: base address -- C_HIGHADDR -- AXI4LITE slave: high address -- C_FAMILY -- -- C_NUM_REG -- Number of software accessible registers -- C_NUM_MEM -- Number of address-ranges -- C_SLV_AWIDTH -- Slave interface address bus width -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- S_AXI_ACLK -- -- S_AXI_ARESETN -- -- S_AXI_AWADDR -- -- S_AXI_AWVALID -- -- S_AXI_WDATA -- -- S_AXI_WSTRB -- -- S_AXI_WVALID -- -- S_AXI_BREADY -- -- S_AXI_ARADDR -- -- S_AXI_ARVALID -- -- S_AXI_RREADY -- -- S_AXI_ARREADY -- -- S_AXI_RDATA -- -- S_AXI_RRESP -- -- S_AXI_RVALID -- -- S_AXI_WREADY -- -- S_AXI_BRESP -- -- S_AXI_BVALID -- -- S_AXI_AWREADY -- ------------------------------------------------------------------------------ entity axi_i2s_adi is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- C_DATA_WIDTH : integer := 24; C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first) C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode) C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer := 8; C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_FAMILY : string := "virtex6"; C_NUM_REG : integer := 1; C_NUM_MEM : integer := 1; C_SLV_AWIDTH : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ BCLK_O : out std_logic; LRCLK_O : out std_logic; SDATA_I : in std_logic; SDATA_O : out std_logic; -- MEM_RD_O for debugging MEM_RD_O : out std_logic; -- ACLK : in std_logic; ARESETN : in std_logic; S_AXIS_TREADY : out std_logic; S_AXIS_TDATA : in std_logic_vector(31 downto 0); S_AXIS_TLAST : in std_logic; S_AXIS_TVALID : in std_logic; M_AXIS_ACLK : in std_logic; M_AXIS_TREADY : in std_logic; M_AXIS_TDATA : out std_logic_vector(31 downto 0); M_AXIS_TLAST : out std_logic; M_AXIS_TVALID : out std_logic; M_AXIS_TKEEP : out std_logic_vector(3 downto 0); -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of ACLK : signal is "CLK"; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; attribute SIGIS of S_AXI_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; end entity axi_i2s_adi; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of axi_i2s_adi is constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address ); constant USER_SLV_NUM_REG : integer := 12; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant TOTAL_IPIF_CE : integer := USER_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space ); ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Resetn : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; -- bufg signal LRCLK_BUFG_I : std_logic; signal BCLK_BUFG_I : std_logic; begin ------------------------------------------ -- instantiate axi_lite_ipif ------------------------------------------ AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif generic map ( C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_RREADY => S_AXI_RREADY, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_AWREADY => S_AXI_AWREADY, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE, Bus2IP_Data => ipif_Bus2IP_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, IP2Bus_Data => ipif_IP2Bus_Data ); ------------------------------------------ -- instantiate User Logic ------------------------------------------ USER_LOGIC_I : entity axi_i2s_adi_v1_00_a.user_logic generic map ( C_MSB_POS => C_MSB_POS, C_FRM_SYNC => C_FRM_SYNC, C_LRCLK_POL => C_LRCLK_POL, C_BCLK_POL => C_BCLK_POL, -- MAP USER GENERICS ABOVE THIS LINE --------------- C_NUM_REG => USER_NUM_REG, C_SLV_DWIDTH => C_DATA_WIDTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ BCLK_O => BCLK_BUFG_I, LRCLK_O => LRCLK_BUFG_I, SDATA_I => SDATA_I, SDATA_O => SDATA_O, -- debug only MEM_RD_O => MEM_RD_O, -- Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error, S_AXIS_ACLK => ACLK, S_AXIS_TREADY => S_AXIS_TREADY, S_AXIS_TDATA => S_AXIS_TDATA, S_AXIS_TLAST => S_AXIS_TLAST, S_AXIS_TVALID => S_AXIS_TVALID, M_AXIS_ACLK => M_AXIS_ACLK, M_AXIS_TREADY => M_AXIS_TREADY, M_AXIS_TDATA => M_AXIS_TDATA, M_AXIS_TLAST => M_AXIS_TLAST, M_AXIS_TVALID => M_AXIS_TVALID, M_AXIS_TKEEP => M_AXIS_TKEEP ); ----- bufg BUFG_inst_BCLK : BUFG port map ( O => LRCLK_O, -- 1-bit Clock buffer output I => LRCLK_BUFG_I -- 1-bit Clock buffer input ); BUFG_inst_LRCLK : BUFG port map ( O => BCLK_O, -- 1-bit Clock buffer output I => BCLK_BUFG_I -- 1-bit Clock buffer input ); ------------------------------------------ -- connect internal signals ------------------------------------------ ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); end IMP;	mit
ObKo/USBCore	Test/usb_flasher_tb.vhdl	1	7582	-- -- USB Full-Speed/Hi-Speed Device Controller core - usb_flasher_tb.vhdl -- -- Copyright (c) 2015 Konstantin Oblaukhov -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.NUMERIC_STD.all; ENTITY usb_flasher_tb IS END usb_flasher_tb; architecture usb_flasher_tb of usb_flasher_tb is component usb_flasher port( clk : in std_logic; rst : in std_logic; ctl_xfer_endpoint : in std_logic_vector(3 downto 0); ctl_xfer_type : in std_logic_vector(7 downto 0); ctl_xfer_request : in std_logic_vector(7 downto 0); ctl_xfer_value : in std_logic_vector(15 downto 0); ctl_xfer_index : in std_logic_vector(15 downto 0); ctl_xfer_length : in std_logic_vector(15 downto 0); ctl_xfer_accept : out std_logic; ctl_xfer : in std_logic; ctl_xfer_done : out std_logic; ctl_xfer_data_out : in std_logic_vector(7 downto 0); ctl_xfer_data_out_valid : in std_logic; ctl_xfer_data_in : out std_logic_vector(7 downto 0); ctl_xfer_data_in_valid : out std_logic; ctl_xfer_data_in_last : out std_logic; ctl_xfer_data_in_ready : in std_logic; blk_xfer_endpoint : in std_logic_vector(3 downto 0); blk_in_xfer : in std_logic; blk_out_xfer : in std_logic; blk_xfer_in_has_data : out std_logic; blk_xfer_in_data : out std_logic_vector(7 downto 0); blk_xfer_in_data_valid : out std_logic; blk_xfer_in_data_ready : in std_logic; blk_xfer_in_data_last : out std_logic; blk_xfer_out_ready_read : out std_logic; blk_xfer_out_data : in std_logic_vector(7 downto 0); blk_xfer_out_data_valid : in std_logic; spi_cs : out std_logic; spi_sck : out std_logic; spi_mosi : out std_logic; spi_miso : in std_logic ); end component; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal ctl_xfer_endpoint : std_logic_vector(3 downto 0) := (others => '0'); signal ctl_xfer_type : std_logic_vector(7 downto 0) := (others => '0'); signal ctl_xfer_request : std_logic_vector(7 downto 0) := (others => '0'); signal ctl_xfer_value : std_logic_vector(15 downto 0) := (others => '0'); signal ctl_xfer_index : std_logic_vector(15 downto 0) := (others => '0'); signal ctl_xfer_length : std_logic_vector(15 downto 0) := (others => '0'); signal ctl_xfer : std_logic := '0'; signal ctl_xfer_data_out : std_logic_vector(7 downto 0) := (others => '0'); signal ctl_xfer_data_out_valid : std_logic := '0'; signal ctl_xfer_data_in_ready : std_logic := '0'; signal blk_xfer_endpoint : std_logic_vector(3 downto 0) := (others => '0'); signal blk_in_xfer : std_logic := '0'; signal blk_out_xfer : std_logic := '0'; signal blk_xfer_in_data_ready : std_logic := '0'; signal blk_xfer_out_data : std_logic_vector(7 downto 0) := (others => '0'); signal blk_xfer_out_data_valid : std_logic := '0'; signal spi_miso : std_logic := '0'; --Outputs signal ctl_xfer_accept : std_logic; signal ctl_xfer_done : std_logic; signal ctl_xfer_data_in : std_logic_vector(7 downto 0); signal ctl_xfer_data_in_valid : std_logic; signal ctl_xfer_data_in_last : std_logic; signal blk_xfer_in_has_data : std_logic; signal blk_xfer_in_data : std_logic_vector(7 downto 0); signal blk_xfer_in_data_valid : std_logic; signal blk_xfer_in_data_last : std_logic; signal blk_xfer_out_ready_read : std_logic; signal spi_cs : std_logic; signal spi_sck : std_logic; signal spi_mosi : std_logic; constant clk_period : time := 10 ns; BEGIN FLASHER: usb_flasher port map ( clk => clk, rst => rst, ctl_xfer_endpoint => ctl_xfer_endpoint, ctl_xfer_type => ctl_xfer_type, ctl_xfer_request => ctl_xfer_request, ctl_xfer_value => ctl_xfer_value, ctl_xfer_index => ctl_xfer_index, ctl_xfer_length => ctl_xfer_length, ctl_xfer_accept => ctl_xfer_accept, ctl_xfer => ctl_xfer, ctl_xfer_done => ctl_xfer_done, ctl_xfer_data_out => ctl_xfer_data_out, ctl_xfer_data_out_valid => ctl_xfer_data_out_valid, ctl_xfer_data_in => ctl_xfer_data_in, ctl_xfer_data_in_valid => ctl_xfer_data_in_valid, ctl_xfer_data_in_last => ctl_xfer_data_in_last, ctl_xfer_data_in_ready => ctl_xfer_data_in_ready, blk_xfer_endpoint => blk_xfer_endpoint, blk_in_xfer => blk_in_xfer, blk_out_xfer => blk_out_xfer, blk_xfer_in_has_data => blk_xfer_in_has_data, blk_xfer_in_data => blk_xfer_in_data, blk_xfer_in_data_valid => blk_xfer_in_data_valid, blk_xfer_in_data_ready => blk_xfer_in_data_ready, blk_xfer_in_data_last => blk_xfer_in_data_last, blk_xfer_out_ready_read => blk_xfer_out_ready_read, blk_xfer_out_data => blk_xfer_out_data, blk_xfer_out_data_valid => blk_xfer_out_data_valid, spi_cs => spi_cs, spi_sck => spi_sck, spi_mosi => spi_mosi, spi_miso => spi_miso ); ctl_xfer_endpoint <= X"0"; ctl_xfer_type <= X"C0"; ctl_xfer_request <= X"04"; ctl_xfer_value <= X"0085"; ctl_xfer_index <= (others => '0'); ctl_xfer_length <= X"0001"; ctl_xfer_data_in_ready <= '0'; ctl_xfer_data_out <= X"A5"; CLK_GEN: process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; STIM: process begin wait for 100 ns; rst <= '1'; wait for clk_period10; rst <= '0'; wait for clk_period; -- blk_out_xfer <= '1'; -- blk_xfer_out_data_valid <= '1'; -- blk_xfer_out_data <= X"A5"; -- -- wait for clk_period; -- blk_xfer_out_data <= X"88"; -- -- wait for clk_period255; -- blk_out_xfer <= '0'; -- blk_xfer_out_data_valid <= '0'; ctl_xfer <= '1'; ctl_xfer_data_out_valid <= '1'; wait for clk_period100; ctl_xfer <= '0'; --blk_in_xfer <= '1'; --blk_xfer_in_data_ready <= '1'; --wait for clk_period256; --blk_in_xfer <= '0'; --blk_xfer_in_data_ready <= '0'; wait; end process; end;	mit
ptracton/Picoblaze	Picoblaze/ROM_form_templates/ROM_form_JTAGLoader_3Mar11.vhd	1	96991	-- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- ROM_form.vhd Template for a KCPSM6 program memory. This template is primarily for use during code development including generic parameters for the convenient selection of device family, program memory size and the ability to include the JTAG Loader hardware for rapid software development. Kris Chaplin and Ken Chapman (Xilinx Ltd) 17th September 2010 - First Release 4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance. 3rd March 2011 - Minor adjustments to comments only. This is a VHDL template file for the KCPSM6 assembler. This VHDL file is not valid as input directly into a synthesis or a simulation tool. The assembler will read this template and insert the information required to complete the definition of program ROM and write it out to a new '.vhd' file that is ready for synthesis and simulation. This template can be modified to define alternative memory definitions. However, you are responsible for ensuring the template is correct as the assembler does not perform any checking of the VHDL. The assembler identifies all text enclosed by {} characters, and replaces these character strings. All templates should include these {} character strings for the assembler to work correctly. The next line is used to determine where the template actually starts. {begin template} -- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- -- -- Definition of a program memory for KCPSM6 including generic parameters for the -- convenient selection of device family, program memory size and the ability to include -- the JTAG Loader hardware for rapid software development. -- -- This file is primarily for use during code development and it is recommended that the -- appropriate simplified program memory definition be used in a final production design. -- -- Generic Values Comments -- Parameter Supported -- -- C_FAMILY "S6" or "V6" Specify Spartan-6 or Virtex-6 device -- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions -- '4' is only supported with 'V6'. -- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader -- -- Notes -- -- If your design contains MULTIPLE KCPSM6 instances then only one should have the -- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to -- '1' on one instance of the program memory). Advanced users may be interested to know -- that it is possible to connect JTAG Loader to multiple memories and then to use the -- JTAG Loader utility to specify which memory contents are to be modified. However, -- this scheme does require some effort to set up and the additional connectivity of the -- multiple BRAMs can impact the placement, routing and performance of the complete -- design. Please contact the author at Xilinx for more detailed information. -- -- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete -- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified -- without requiring changes to the fundamental hardware definition. However, when the -- program memory is 1K then only the lower 10-bits of the address are actually used and -- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower -- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex. -- -- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the -- size of the program and the device family. -- -- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program -- will require 2 BRAMs to be used. Whilst it is possible to implement a 4K program in a -- Spartan-6 device this is a less natural fit within the architecture and either requires -- 4 BRAMs and a small amount of logic resulting in a lower performance or 5 BRAMs when -- performance is a critical factor. Due to these additional considerations this file -- does not support the selection of 4K when using Spartan-6. It is also possible to -- divide a BRAM into 2 smaller memories and therefore support a program up to only 512 -- instructions. If one of these special cases is required then please contact the authors -- at Xilinx to discuss and request a specific 'ROM_form' template that will meet your -- requirements. -- -- In a Virtex-6 device a BRAM is capable of holding 2K instructions so obviously a 2K -- program requires only a single BRAM. Each BRAM can also be divided into 2 smaller -- memories supporting programs of 1K in half of a 36k-bit BRAM (generally reported -- as being an 18k-bit BRAM). For a program of 4K instructions 2 BRAMs are required. -- -- -- Program defined by '{psmname}.psm'. -- -- Generated by KCPSM6 Assembler: {timestamp}. -- -- Assembler used ROM_form template: 3rd March 2011 -- -- Standard IEEE libraries -- -- package jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer; end jtag_loader_pkg; -- package body jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer is begin if (size_in_k = 1) then return 10; elsif (size_in_k = 2) then return 11; elsif (size_in_k = 4) then return 12; else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE; end if; return 0; end function addr_width_calc; end package body; -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.jtag_loader_pkg.ALL; -- -- The Unisim Library is used to define Xilinx primitives. It is also used during -- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd -- library unisim; use unisim.vcomponents.all; -- -- entity {name} is generic( C_FAMILY : string := "S6"; C_RAM_SIZE_KWORDS : integer := 1; C_JTAG_LOADER_ENABLE : integer := 0); Port ( address : in std_logic_vector(11 downto 0); instruction : out std_logic_vector(17 downto 0); enable : in std_logic; rdl : out std_logic; clk : in std_logic); end {name}; -- architecture low_level_definition of {name} is -- signal address_a : std_logic_vector(15 downto 0); signal data_in_a : std_logic_vector(35 downto 0); signal data_out_a : std_logic_vector(35 downto 0); signal data_out_a_l : std_logic_vector(35 downto 0); signal data_out_a_h : std_logic_vector(35 downto 0); signal address_b : std_logic_vector(15 downto 0); signal data_in_b : std_logic_vector(35 downto 0); signal data_in_b_l : std_logic_vector(35 downto 0); signal data_out_b : std_logic_vector(35 downto 0); signal data_out_b_l : std_logic_vector(35 downto 0); signal data_in_b_h : std_logic_vector(35 downto 0); signal data_out_b_h : std_logic_vector(35 downto 0); signal enable_b : std_logic; signal clk_b : std_logic; signal we_b : std_logic_vector(7 downto 0); -- signal jtag_addr : std_logic_vector(11 downto 0); signal jtag_we : std_logic; signal jtag_clk : std_logic; signal jtag_din : std_logic_vector(17 downto 0); signal jtag_dout : std_logic_vector(17 downto 0); signal jtag_dout_1 : std_logic_vector(17 downto 0); signal jtag_en : std_logic_vector(0 downto 0); -- signal picoblaze_reset : std_logic_vector(0 downto 0); signal rdl_bus : std_logic_vector(0 downto 0); -- constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS); -- -- component jtag_loader_6 generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); jtag_clk : out std_logic; jtag_we : out std_logic; jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end component; -- begin -- -- ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB16BWER generic map ( DATA_WIDTH_A => 18, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 18, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a(31 downto 0), DOPA => data_out_a(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b(31 downto 0), DOPB => data_out_b(35 downto 32), DIB => data_in_b(31 downto 0), DIPB => data_in_b(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(17 downto 0); data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(17 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b(17 downto 0) <= data_out_b(17 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b(17 downto 0) <= jtag_din(17 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB18E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => "000000000000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}") port map( ADDRARDADDR => address_a(13 downto 0), ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(15 downto 0), DOPADOP => data_out_a(17 downto 16), DIADI => data_in_a(15 downto 0), DIPADIP => data_in_a(17 downto 16), WEA => "00", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b(13 downto 0), ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(15 downto 0), DOPBDOP => data_out_b(17 downto 16), DIBDI => data_in_b(15 downto 0), DIPBDIP => data_in_b(17 downto 16), WEBWE => we_b(3 downto 0), REGCEB => '0', RSTRAMB => '0', RSTREGB => '0'); -- end generate v6; -- end generate ram_1k_generate; -- -- -- ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate -- -- s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(10 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{[8:0]_INIT_00}", INIT_01 => X"{[8:0]_INIT_01}", INIT_02 => X"{[8:0]_INIT_02}", INIT_03 => X"{[8:0]_INIT_03}", INIT_04 => X"{[8:0]_INIT_04}", INIT_05 => X"{[8:0]_INIT_05}", INIT_06 => X"{[8:0]_INIT_06}", INIT_07 => X"{[8:0]_INIT_07}", INIT_08 => X"{[8:0]_INIT_08}", INIT_09 => X"{[8:0]_INIT_09}", INIT_0A => X"{[8:0]_INIT_0A}", INIT_0B => X"{[8:0]_INIT_0B}", INIT_0C => X"{[8:0]_INIT_0C}", INIT_0D => X"{[8:0]_INIT_0D}", INIT_0E => X"{[8:0]_INIT_0E}", INIT_0F => X"{[8:0]_INIT_0F}", INIT_10 => X"{[8:0]_INIT_10}", INIT_11 => X"{[8:0]_INIT_11}", INIT_12 => X"{[8:0]_INIT_12}", INIT_13 => X"{[8:0]_INIT_13}", INIT_14 => X"{[8:0]_INIT_14}", INIT_15 => X"{[8:0]_INIT_15}", INIT_16 => X"{[8:0]_INIT_16}", INIT_17 => X"{[8:0]_INIT_17}", INIT_18 => X"{[8:0]_INIT_18}", INIT_19 => X"{[8:0]_INIT_19}", INIT_1A => X"{[8:0]_INIT_1A}", INIT_1B => X"{[8:0]_INIT_1B}", INIT_1C => X"{[8:0]_INIT_1C}", INIT_1D => X"{[8:0]_INIT_1D}", INIT_1E => X"{[8:0]_INIT_1E}", INIT_1F => X"{[8:0]_INIT_1F}", INIT_20 => X"{[8:0]_INIT_20}", INIT_21 => X"{[8:0]_INIT_21}", INIT_22 => X"{[8:0]_INIT_22}", INIT_23 => X"{[8:0]_INIT_23}", INIT_24 => X"{[8:0]_INIT_24}", INIT_25 => X"{[8:0]_INIT_25}", INIT_26 => X"{[8:0]_INIT_26}", INIT_27 => X"{[8:0]_INIT_27}", INIT_28 => X"{[8:0]_INIT_28}", INIT_29 => X"{[8:0]_INIT_29}", INIT_2A => X"{[8:0]_INIT_2A}", INIT_2B => X"{[8:0]_INIT_2B}", INIT_2C => X"{[8:0]_INIT_2C}", INIT_2D => X"{[8:0]_INIT_2D}", INIT_2E => X"{[8:0]_INIT_2E}", INIT_2F => X"{[8:0]_INIT_2F}", INIT_30 => X"{[8:0]_INIT_30}", INIT_31 => X"{[8:0]_INIT_31}", INIT_32 => X"{[8:0]_INIT_32}", INIT_33 => X"{[8:0]_INIT_33}", INIT_34 => X"{[8:0]_INIT_34}", INIT_35 => X"{[8:0]_INIT_35}", INIT_36 => X"{[8:0]_INIT_36}", INIT_37 => X"{[8:0]_INIT_37}", INIT_38 => X"{[8:0]_INIT_38}", INIT_39 => X"{[8:0]_INIT_39}", INIT_3A => X"{[8:0]_INIT_3A}", INIT_3B => X"{[8:0]_INIT_3B}", INIT_3C => X"{[8:0]_INIT_3C}", INIT_3D => X"{[8:0]_INIT_3D}", INIT_3E => X"{[8:0]_INIT_3E}", INIT_3F => X"{[8:0]_INIT_3F}", INITP_00 => X"{[8:0]_INITP_00}", INITP_01 => X"{[8:0]_INITP_01}", INITP_02 => X"{[8:0]_INITP_02}", INITP_03 => X"{[8:0]_INITP_03}", INITP_04 => X"{[8:0]_INITP_04}", INITP_05 => X"{[8:0]_INITP_05}", INITP_06 => X"{[8:0]_INITP_06}", INITP_07 => X"{[8:0]_INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_l(31 downto 0), DOPA => data_out_a_l(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_l(31 downto 0), DOPB => data_out_b_l(35 downto 32), DIB => data_in_b_l(31 downto 0), DIPB => data_in_b_l(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- kcpsm6_rom_h: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{[17:9]_INIT_00}", INIT_01 => X"{[17:9]_INIT_01}", INIT_02 => X"{[17:9]_INIT_02}", INIT_03 => X"{[17:9]_INIT_03}", INIT_04 => X"{[17:9]_INIT_04}", INIT_05 => X"{[17:9]_INIT_05}", INIT_06 => X"{[17:9]_INIT_06}", INIT_07 => X"{[17:9]_INIT_07}", INIT_08 => X"{[17:9]_INIT_08}", INIT_09 => X"{[17:9]_INIT_09}", INIT_0A => X"{[17:9]_INIT_0A}", INIT_0B => X"{[17:9]_INIT_0B}", INIT_0C => X"{[17:9]_INIT_0C}", INIT_0D => X"{[17:9]_INIT_0D}", INIT_0E => X"{[17:9]_INIT_0E}", INIT_0F => X"{[17:9]_INIT_0F}", INIT_10 => X"{[17:9]_INIT_10}", INIT_11 => X"{[17:9]_INIT_11}", INIT_12 => X"{[17:9]_INIT_12}", INIT_13 => X"{[17:9]_INIT_13}", INIT_14 => X"{[17:9]_INIT_14}", INIT_15 => X"{[17:9]_INIT_15}", INIT_16 => X"{[17:9]_INIT_16}", INIT_17 => X"{[17:9]_INIT_17}", INIT_18 => X"{[17:9]_INIT_18}", INIT_19 => X"{[17:9]_INIT_19}", INIT_1A => X"{[17:9]_INIT_1A}", INIT_1B => X"{[17:9]_INIT_1B}", INIT_1C => X"{[17:9]_INIT_1C}", INIT_1D => X"{[17:9]_INIT_1D}", INIT_1E => X"{[17:9]_INIT_1E}", INIT_1F => X"{[17:9]_INIT_1F}", INIT_20 => X"{[17:9]_INIT_20}", INIT_21 => X"{[17:9]_INIT_21}", INIT_22 => X"{[17:9]_INIT_22}", INIT_23 => X"{[17:9]_INIT_23}", INIT_24 => X"{[17:9]_INIT_24}", INIT_25 => X"{[17:9]_INIT_25}", INIT_26 => X"{[17:9]_INIT_26}", INIT_27 => X"{[17:9]_INIT_27}", INIT_28 => X"{[17:9]_INIT_28}", INIT_29 => X"{[17:9]_INIT_29}", INIT_2A => X"{[17:9]_INIT_2A}", INIT_2B => X"{[17:9]_INIT_2B}", INIT_2C => X"{[17:9]_INIT_2C}", INIT_2D => X"{[17:9]_INIT_2D}", INIT_2E => X"{[17:9]_INIT_2E}", INIT_2F => X"{[17:9]_INIT_2F}", INIT_30 => X"{[17:9]_INIT_30}", INIT_31 => X"{[17:9]_INIT_31}", INIT_32 => X"{[17:9]_INIT_32}", INIT_33 => X"{[17:9]_INIT_33}", INIT_34 => X"{[17:9]_INIT_34}", INIT_35 => X"{[17:9]_INIT_35}", INIT_36 => X"{[17:9]_INIT_36}", INIT_37 => X"{[17:9]_INIT_37}", INIT_38 => X"{[17:9]_INIT_38}", INIT_39 => X"{[17:9]_INIT_39}", INIT_3A => X"{[17:9]_INIT_3A}", INIT_3B => X"{[17:9]_INIT_3B}", INIT_3C => X"{[17:9]_INIT_3C}", INIT_3D => X"{[17:9]_INIT_3D}", INIT_3E => X"{[17:9]_INIT_3E}", INIT_3F => X"{[17:9]_INIT_3F}", INITP_00 => X"{[17:9]_INITP_00}", INITP_01 => X"{[17:9]_INITP_01}", INITP_02 => X"{[17:9]_INITP_02}", INITP_03 => X"{[17:9]_INITP_03}", INITP_04 => X"{[17:9]_INITP_04}", INITP_05 => X"{[17:9]_INITP_05}", INITP_06 => X"{[17:9]_INITP_06}", INITP_07 => X"{[17:9]_INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_h(31 downto 0), DOPA => data_out_a_h(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_h(31 downto 0), DOPB => data_out_b_h(35 downto 32), DIB => data_in_b_h(31 downto 0), DIPB => data_in_b_h(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(10 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b <= '0' & jtag_addr(10 downto 0) & "0000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB36E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INIT_40 => X"{INIT_40}", INIT_41 => X"{INIT_41}", INIT_42 => X"{INIT_42}", INIT_43 => X"{INIT_43}", INIT_44 => X"{INIT_44}", INIT_45 => X"{INIT_45}", INIT_46 => X"{INIT_46}", INIT_47 => X"{INIT_47}", INIT_48 => X"{INIT_48}", INIT_49 => X"{INIT_49}", INIT_4A => X"{INIT_4A}", INIT_4B => X"{INIT_4B}", INIT_4C => X"{INIT_4C}", INIT_4D => X"{INIT_4D}", INIT_4E => X"{INIT_4E}", INIT_4F => X"{INIT_4F}", INIT_50 => X"{INIT_50}", INIT_51 => X"{INIT_51}", INIT_52 => X"{INIT_52}", INIT_53 => X"{INIT_53}", INIT_54 => X"{INIT_54}", INIT_55 => X"{INIT_55}", INIT_56 => X"{INIT_56}", INIT_57 => X"{INIT_57}", INIT_58 => X"{INIT_58}", INIT_59 => X"{INIT_59}", INIT_5A => X"{INIT_5A}", INIT_5B => X"{INIT_5B}", INIT_5C => X"{INIT_5C}", INIT_5D => X"{INIT_5D}", INIT_5E => X"{INIT_5E}", INIT_5F => X"{INIT_5F}", INIT_60 => X"{INIT_60}", INIT_61 => X"{INIT_61}", INIT_62 => X"{INIT_62}", INIT_63 => X"{INIT_63}", INIT_64 => X"{INIT_64}", INIT_65 => X"{INIT_65}", INIT_66 => X"{INIT_66}", INIT_67 => X"{INIT_67}", INIT_68 => X"{INIT_68}", INIT_69 => X"{INIT_69}", INIT_6A => X"{INIT_6A}", INIT_6B => X"{INIT_6B}", INIT_6C => X"{INIT_6C}", INIT_6D => X"{INIT_6D}", INIT_6E => X"{INIT_6E}", INIT_6F => X"{INIT_6F}", INIT_70 => X"{INIT_70}", INIT_71 => X"{INIT_71}", INIT_72 => X"{INIT_72}", INIT_73 => X"{INIT_73}", INIT_74 => X"{INIT_74}", INIT_75 => X"{INIT_75}", INIT_76 => X"{INIT_76}", INIT_77 => X"{INIT_77}", INIT_78 => X"{INIT_78}", INIT_79 => X"{INIT_79}", INIT_7A => X"{INIT_7A}", INIT_7B => X"{INIT_7B}", INIT_7C => X"{INIT_7C}", INIT_7D => X"{INIT_7D}", INIT_7E => X"{INIT_7E}", INIT_7F => X"{INIT_7F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}", INITP_08 => X"{INITP_08}", INITP_09 => X"{INITP_09}", INITP_0A => X"{INITP_0A}", INITP_0B => X"{INITP_0B}", INITP_0C => X"{INITP_0C}", INITP_0D => X"{INITP_0D}", INITP_0E => X"{INITP_0E}", INITP_0F => X"{INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(31 downto 0), DOPADOP => data_out_a(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(31 downto 0), DOPBDOP => data_out_b(35 downto 32), DIBDI => data_in_b(31 downto 0), DIPBDIP => data_in_b(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- end generate ram_2k_generate; -- -- ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate s6: if (C_FAMILY = "S6") generate assert(1=0) report "4K BRAM in Spartan-6 is a special case not supported by this template." severity FAILURE; end generate s6; -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(11 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "000000000000000000000000000000000000"; jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b <= '0' & jtag_addr(11 downto 0) & "000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{[8:0]_INIT_00}", INIT_01 => X"{[8:0]_INIT_01}", INIT_02 => X"{[8:0]_INIT_02}", INIT_03 => X"{[8:0]_INIT_03}", INIT_04 => X"{[8:0]_INIT_04}", INIT_05 => X"{[8:0]_INIT_05}", INIT_06 => X"{[8:0]_INIT_06}", INIT_07 => X"{[8:0]_INIT_07}", INIT_08 => X"{[8:0]_INIT_08}", INIT_09 => X"{[8:0]_INIT_09}", INIT_0A => X"{[8:0]_INIT_0A}", INIT_0B => X"{[8:0]_INIT_0B}", INIT_0C => X"{[8:0]_INIT_0C}", INIT_0D => X"{[8:0]_INIT_0D}", INIT_0E => X"{[8:0]_INIT_0E}", INIT_0F => X"{[8:0]_INIT_0F}", INIT_10 => X"{[8:0]_INIT_10}", INIT_11 => X"{[8:0]_INIT_11}", INIT_12 => X"{[8:0]_INIT_12}", INIT_13 => X"{[8:0]_INIT_13}", INIT_14 => X"{[8:0]_INIT_14}", INIT_15 => X"{[8:0]_INIT_15}", INIT_16 => X"{[8:0]_INIT_16}", INIT_17 => X"{[8:0]_INIT_17}", INIT_18 => X"{[8:0]_INIT_18}", INIT_19 => X"{[8:0]_INIT_19}", INIT_1A => X"{[8:0]_INIT_1A}", INIT_1B => X"{[8:0]_INIT_1B}", INIT_1C => X"{[8:0]_INIT_1C}", INIT_1D => X"{[8:0]_INIT_1D}", INIT_1E => X"{[8:0]_INIT_1E}", INIT_1F => X"{[8:0]_INIT_1F}", INIT_20 => X"{[8:0]_INIT_20}", INIT_21 => X"{[8:0]_INIT_21}", INIT_22 => X"{[8:0]_INIT_22}", INIT_23 => X"{[8:0]_INIT_23}", INIT_24 => X"{[8:0]_INIT_24}", INIT_25 => X"{[8:0]_INIT_25}", INIT_26 => X"{[8:0]_INIT_26}", INIT_27 => X"{[8:0]_INIT_27}", INIT_28 => X"{[8:0]_INIT_28}", INIT_29 => X"{[8:0]_INIT_29}", INIT_2A => X"{[8:0]_INIT_2A}", INIT_2B => X"{[8:0]_INIT_2B}", INIT_2C => X"{[8:0]_INIT_2C}", INIT_2D => X"{[8:0]_INIT_2D}", INIT_2E => X"{[8:0]_INIT_2E}", INIT_2F => X"{[8:0]_INIT_2F}", INIT_30 => X"{[8:0]_INIT_30}", INIT_31 => X"{[8:0]_INIT_31}", INIT_32 => X"{[8:0]_INIT_32}", INIT_33 => X"{[8:0]_INIT_33}", INIT_34 => X"{[8:0]_INIT_34}", INIT_35 => X"{[8:0]_INIT_35}", INIT_36 => X"{[8:0]_INIT_36}", INIT_37 => X"{[8:0]_INIT_37}", INIT_38 => X"{[8:0]_INIT_38}", INIT_39 => X"{[8:0]_INIT_39}", INIT_3A => X"{[8:0]_INIT_3A}", INIT_3B => X"{[8:0]_INIT_3B}", INIT_3C => X"{[8:0]_INIT_3C}", INIT_3D => X"{[8:0]_INIT_3D}", INIT_3E => X"{[8:0]_INIT_3E}", INIT_3F => X"{[8:0]_INIT_3F}", INIT_40 => X"{[8:0]_INIT_40}", INIT_41 => X"{[8:0]_INIT_41}", INIT_42 => X"{[8:0]_INIT_42}", INIT_43 => X"{[8:0]_INIT_43}", INIT_44 => X"{[8:0]_INIT_44}", INIT_45 => X"{[8:0]_INIT_45}", INIT_46 => X"{[8:0]_INIT_46}", INIT_47 => X"{[8:0]_INIT_47}", INIT_48 => X"{[8:0]_INIT_48}", INIT_49 => X"{[8:0]_INIT_49}", INIT_4A => X"{[8:0]_INIT_4A}", INIT_4B => X"{[8:0]_INIT_4B}", INIT_4C => X"{[8:0]_INIT_4C}", INIT_4D => X"{[8:0]_INIT_4D}", INIT_4E => X"{[8:0]_INIT_4E}", INIT_4F => X"{[8:0]_INIT_4F}", INIT_50 => X"{[8:0]_INIT_50}", INIT_51 => X"{[8:0]_INIT_51}", INIT_52 => X"{[8:0]_INIT_52}", INIT_53 => X"{[8:0]_INIT_53}", INIT_54 => X"{[8:0]_INIT_54}", INIT_55 => X"{[8:0]_INIT_55}", INIT_56 => X"{[8:0]_INIT_56}", INIT_57 => X"{[8:0]_INIT_57}", INIT_58 => X"{[8:0]_INIT_58}", INIT_59 => X"{[8:0]_INIT_59}", INIT_5A => X"{[8:0]_INIT_5A}", INIT_5B => X"{[8:0]_INIT_5B}", INIT_5C => X"{[8:0]_INIT_5C}", INIT_5D => X"{[8:0]_INIT_5D}", INIT_5E => X"{[8:0]_INIT_5E}", INIT_5F => X"{[8:0]_INIT_5F}", INIT_60 => X"{[8:0]_INIT_60}", INIT_61 => X"{[8:0]_INIT_61}", INIT_62 => X"{[8:0]_INIT_62}", INIT_63 => X"{[8:0]_INIT_63}", INIT_64 => X"{[8:0]_INIT_64}", INIT_65 => X"{[8:0]_INIT_65}", INIT_66 => X"{[8:0]_INIT_66}", INIT_67 => X"{[8:0]_INIT_67}", INIT_68 => X"{[8:0]_INIT_68}", INIT_69 => X"{[8:0]_INIT_69}", INIT_6A => X"{[8:0]_INIT_6A}", INIT_6B => X"{[8:0]_INIT_6B}", INIT_6C => X"{[8:0]_INIT_6C}", INIT_6D => X"{[8:0]_INIT_6D}", INIT_6E => X"{[8:0]_INIT_6E}", INIT_6F => X"{[8:0]_INIT_6F}", INIT_70 => X"{[8:0]_INIT_70}", INIT_71 => X"{[8:0]_INIT_71}", INIT_72 => X"{[8:0]_INIT_72}", INIT_73 => X"{[8:0]_INIT_73}", INIT_74 => X"{[8:0]_INIT_74}", INIT_75 => X"{[8:0]_INIT_75}", INIT_76 => X"{[8:0]_INIT_76}", INIT_77 => X"{[8:0]_INIT_77}", INIT_78 => X"{[8:0]_INIT_78}", INIT_79 => X"{[8:0]_INIT_79}", INIT_7A => X"{[8:0]_INIT_7A}", INIT_7B => X"{[8:0]_INIT_7B}", INIT_7C => X"{[8:0]_INIT_7C}", INIT_7D => X"{[8:0]_INIT_7D}", INIT_7E => X"{[8:0]_INIT_7E}", INIT_7F => X"{[8:0]_INIT_7F}", INITP_00 => X"{[8:0]_INITP_00}", INITP_01 => X"{[8:0]_INITP_01}", INITP_02 => X"{[8:0]_INITP_02}", INITP_03 => X"{[8:0]_INITP_03}", INITP_04 => X"{[8:0]_INITP_04}", INITP_05 => X"{[8:0]_INITP_05}", INITP_06 => X"{[8:0]_INITP_06}", INITP_07 => X"{[8:0]_INITP_07}", INITP_08 => X"{[8:0]_INITP_08}", INITP_09 => X"{[8:0]_INITP_09}", INITP_0A => X"{[8:0]_INITP_0A}", INITP_0B => X"{[8:0]_INITP_0B}", INITP_0C => X"{[8:0]_INITP_0C}", INITP_0D => X"{[8:0]_INITP_0D}", INITP_0E => X"{[8:0]_INITP_0E}", INITP_0F => X"{[8:0]_INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_l(31 downto 0), DOPADOP => data_out_a_l(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_l(31 downto 0), DOPBDOP => data_out_b_l(35 downto 32), DIBDI => data_in_b_l(31 downto 0), DIPBDIP => data_in_b_l(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- kcpsm6_rom_h: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{[17:9]_INIT_00}", INIT_01 => X"{[17:9]_INIT_01}", INIT_02 => X"{[17:9]_INIT_02}", INIT_03 => X"{[17:9]_INIT_03}", INIT_04 => X"{[17:9]_INIT_04}", INIT_05 => X"{[17:9]_INIT_05}", INIT_06 => X"{[17:9]_INIT_06}", INIT_07 => X"{[17:9]_INIT_07}", INIT_08 => X"{[17:9]_INIT_08}", INIT_09 => X"{[17:9]_INIT_09}", INIT_0A => X"{[17:9]_INIT_0A}", INIT_0B => X"{[17:9]_INIT_0B}", INIT_0C => X"{[17:9]_INIT_0C}", INIT_0D => X"{[17:9]_INIT_0D}", INIT_0E => X"{[17:9]_INIT_0E}", INIT_0F => X"{[17:9]_INIT_0F}", INIT_10 => X"{[17:9]_INIT_10}", INIT_11 => X"{[17:9]_INIT_11}", INIT_12 => X"{[17:9]_INIT_12}", INIT_13 => X"{[17:9]_INIT_13}", INIT_14 => X"{[17:9]_INIT_14}", INIT_15 => X"{[17:9]_INIT_15}", INIT_16 => X"{[17:9]_INIT_16}", INIT_17 => X"{[17:9]_INIT_17}", INIT_18 => X"{[17:9]_INIT_18}", INIT_19 => X"{[17:9]_INIT_19}", INIT_1A => X"{[17:9]_INIT_1A}", INIT_1B => X"{[17:9]_INIT_1B}", INIT_1C => X"{[17:9]_INIT_1C}", INIT_1D => X"{[17:9]_INIT_1D}", INIT_1E => X"{[17:9]_INIT_1E}", INIT_1F => X"{[17:9]_INIT_1F}", INIT_20 => X"{[17:9]_INIT_20}", INIT_21 => X"{[17:9]_INIT_21}", INIT_22 => X"{[17:9]_INIT_22}", INIT_23 => X"{[17:9]_INIT_23}", INIT_24 => X"{[17:9]_INIT_24}", INIT_25 => X"{[17:9]_INIT_25}", INIT_26 => X"{[17:9]_INIT_26}", INIT_27 => X"{[17:9]_INIT_27}", INIT_28 => X"{[17:9]_INIT_28}", INIT_29 => X"{[17:9]_INIT_29}", INIT_2A => X"{[17:9]_INIT_2A}", INIT_2B => X"{[17:9]_INIT_2B}", INIT_2C => X"{[17:9]_INIT_2C}", INIT_2D => X"{[17:9]_INIT_2D}", INIT_2E => X"{[17:9]_INIT_2E}", INIT_2F => X"{[17:9]_INIT_2F}", INIT_30 => X"{[17:9]_INIT_30}", INIT_31 => X"{[17:9]_INIT_31}", INIT_32 => X"{[17:9]_INIT_32}", INIT_33 => X"{[17:9]_INIT_33}", INIT_34 => X"{[17:9]_INIT_34}", INIT_35 => X"{[17:9]_INIT_35}", INIT_36 => X"{[17:9]_INIT_36}", INIT_37 => X"{[17:9]_INIT_37}", INIT_38 => X"{[17:9]_INIT_38}", INIT_39 => X"{[17:9]_INIT_39}", INIT_3A => X"{[17:9]_INIT_3A}", INIT_3B => X"{[17:9]_INIT_3B}", INIT_3C => X"{[17:9]_INIT_3C}", INIT_3D => X"{[17:9]_INIT_3D}", INIT_3E => X"{[17:9]_INIT_3E}", INIT_3F => X"{[17:9]_INIT_3F}", INIT_40 => X"{[17:9]_INIT_40}", INIT_41 => X"{[17:9]_INIT_41}", INIT_42 => X"{[17:9]_INIT_42}", INIT_43 => X"{[17:9]_INIT_43}", INIT_44 => X"{[17:9]_INIT_44}", INIT_45 => X"{[17:9]_INIT_45}", INIT_46 => X"{[17:9]_INIT_46}", INIT_47 => X"{[17:9]_INIT_47}", INIT_48 => X"{[17:9]_INIT_48}", INIT_49 => X"{[17:9]_INIT_49}", INIT_4A => X"{[17:9]_INIT_4A}", INIT_4B => X"{[17:9]_INIT_4B}", INIT_4C => X"{[17:9]_INIT_4C}", INIT_4D => X"{[17:9]_INIT_4D}", INIT_4E => X"{[17:9]_INIT_4E}", INIT_4F => X"{[17:9]_INIT_4F}", INIT_50 => X"{[17:9]_INIT_50}", INIT_51 => X"{[17:9]_INIT_51}", INIT_52 => X"{[17:9]_INIT_52}", INIT_53 => X"{[17:9]_INIT_53}", INIT_54 => X"{[17:9]_INIT_54}", INIT_55 => X"{[17:9]_INIT_55}", INIT_56 => X"{[17:9]_INIT_56}", INIT_57 => X"{[17:9]_INIT_57}", INIT_58 => X"{[17:9]_INIT_58}", INIT_59 => X"{[17:9]_INIT_59}", INIT_5A => X"{[17:9]_INIT_5A}", INIT_5B => X"{[17:9]_INIT_5B}", INIT_5C => X"{[17:9]_INIT_5C}", INIT_5D => X"{[17:9]_INIT_5D}", INIT_5E => X"{[17:9]_INIT_5E}", INIT_5F => X"{[17:9]_INIT_5F}", INIT_60 => X"{[17:9]_INIT_60}", INIT_61 => X"{[17:9]_INIT_61}", INIT_62 => X"{[17:9]_INIT_62}", INIT_63 => X"{[17:9]_INIT_63}", INIT_64 => X"{[17:9]_INIT_64}", INIT_65 => X"{[17:9]_INIT_65}", INIT_66 => X"{[17:9]_INIT_66}", INIT_67 => X"{[17:9]_INIT_67}", INIT_68 => X"{[17:9]_INIT_68}", INIT_69 => X"{[17:9]_INIT_69}", INIT_6A => X"{[17:9]_INIT_6A}", INIT_6B => X"{[17:9]_INIT_6B}", INIT_6C => X"{[17:9]_INIT_6C}", INIT_6D => X"{[17:9]_INIT_6D}", INIT_6E => X"{[17:9]_INIT_6E}", INIT_6F => X"{[17:9]_INIT_6F}", INIT_70 => X"{[17:9]_INIT_70}", INIT_71 => X"{[17:9]_INIT_71}", INIT_72 => X"{[17:9]_INIT_72}", INIT_73 => X"{[17:9]_INIT_73}", INIT_74 => X"{[17:9]_INIT_74}", INIT_75 => X"{[17:9]_INIT_75}", INIT_76 => X"{[17:9]_INIT_76}", INIT_77 => X"{[17:9]_INIT_77}", INIT_78 => X"{[17:9]_INIT_78}", INIT_79 => X"{[17:9]_INIT_79}", INIT_7A => X"{[17:9]_INIT_7A}", INIT_7B => X"{[17:9]_INIT_7B}", INIT_7C => X"{[17:9]_INIT_7C}", INIT_7D => X"{[17:9]_INIT_7D}", INIT_7E => X"{[17:9]_INIT_7E}", INIT_7F => X"{[17:9]_INIT_7F}", INITP_00 => X"{[17:9]_INITP_00}", INITP_01 => X"{[17:9]_INITP_01}", INITP_02 => X"{[17:9]_INITP_02}", INITP_03 => X"{[17:9]_INITP_03}", INITP_04 => X"{[17:9]_INITP_04}", INITP_05 => X"{[17:9]_INITP_05}", INITP_06 => X"{[17:9]_INITP_06}", INITP_07 => X"{[17:9]_INITP_07}", INITP_08 => X"{[17:9]_INITP_08}", INITP_09 => X"{[17:9]_INITP_09}", INITP_0A => X"{[17:9]_INITP_0A}", INITP_0B => X"{[17:9]_INITP_0B}", INITP_0C => X"{[17:9]_INITP_0C}", INITP_0D => X"{[17:9]_INITP_0D}", INITP_0E => X"{[17:9]_INITP_0E}", INITP_0F => X"{[17:9]_INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_h(31 downto 0), DOPADOP => data_out_a_h(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_h(31 downto 0), DOPBDOP => data_out_b_h(35 downto 32), DIBDI => data_in_b_h(31 downto 0), DIPBDIP => data_in_b_h(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- end generate ram_4k_generate; -- -- -- -- -- JTAG Loader -- instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate -- jtag_loader_6_inst : jtag_loader_6 generic map( C_FAMILY => C_FAMILY, C_NUM_PICOBLAZE => 1, C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE, C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH, C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH) port map( picoblaze_reset => rdl_bus, jtag_en => jtag_en, jtag_din => jtag_din, jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0), jtag_clk => jtag_clk, jtag_we => jtag_we, jtag_dout_0 => jtag_dout, jtag_dout_1 => jtag_dout, -- ports 1-7 are not used jtag_dout_2 => jtag_dout, -- in a 1 device debug jtag_dout_3 => jtag_dout, -- session. However, Synplify jtag_dout_4 => jtag_dout, -- etc require all ports to jtag_dout_5 => jtag_dout, -- be connected jtag_dout_6 => jtag_dout, jtag_dout_7 => jtag_dout); -- end generate instantiate_loader; -- end low_level_definition; -- -- -- JTAG Loader 6 - Version 6.00 -- Kris Chaplin 4 February 2010 -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- library unisim; use unisim.vcomponents.all; -- entity jtag_loader_6 is generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0'); jtag_clk : out std_logic := '0'; jtag_we : out std_logic := '0'; jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end jtag_loader_6; -- architecture Behavioral of jtag_loader_6 is -- component bscan_logic generic( C_JTAG_CHAIN : integer := 2; C_BUFFER_SHIFT_CLOCK : boolean := TRUE; C_FAMILY : string := "S6"); port( shift_dout : in std_logic; shift_clk : out std_logic; bram_en : out std_logic; shift_din : out std_logic; bram_strobe : out std_logic; capture : out std_logic; shift : out std_logic); end component; -- component jtag_shifter generic ( C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18); port( shift_clk : in std_logic; shift_din : in std_logic; shift : in std_logic; shift_dout : out std_logic; control_reg_ce : out std_logic; bram_ce : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); bram_a : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); din_load : in std_logic; din : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_d : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_we : out std_logic); end component; -- component control_registers generic ( C_NUM_PICOBLAZE : integer := 1; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10; C_BRAM_MAX_ADDR_WIDTH : integer := 10); port( en : in std_logic; ce : in std_logic; wnr : in std_logic; clk : in std_logic; a : in std_logic_vector(3 downto 0); din : in std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); dout : out std_logic_vector(7 downto 0); picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0)); end component; -- signal shift_clk : std_logic; signal shift_din : std_logic; signal shift_dout : std_logic; signal shift : std_logic; signal capture : std_logic; -- signal control_reg_ce : std_logic; signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0'); signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); signal jtag_we_int : std_logic; signal jtag_clk_int : std_logic; signal bram_ce_valid : std_logic; signal din_load : std_logic; -- signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); -- begin bus_zero <= (others => '0'); -- jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate -- Inst_bscan_logic: bscan_logic generic map ( C_JTAG_CHAIN => C_JTAG_CHAIN, C_BUFFER_SHIFT_CLOCK => TRUE, C_FAMILY => C_FAMILY ) port map( shift_dout => shift_dout, shift_clk => shift_clk, bram_en => bram_ce_valid, shift_din => shift_din, bram_strobe => jtag_clk_int, capture => capture, shift => shift ); -- Inst_jtag_shifter: jtag_shifter generic map( C_NUM_PICOBLAZE => C_NUM_PICOBLAZE, C_BRAM_MAX_ADDR_WIDTH => C_BRAM_MAX_ADDR_WIDTH, C_PICOBLAZE_INSTRUCTION_DATA_WIDTH => C_PICOBLAZE_INSTRUCTION_DATA_WIDTH ) port map( shift_clk => shift_clk, shift_din => shift_din, shift => shift, shift_dout => shift_dout, control_reg_ce => control_reg_ce, bram_ce => bram_ce, bram_a => jtag_addr_int, din_load => din_load, din => bram_dout_int, bram_d => jtag_din_int, bram_we => jtag_we_int ); -- process (bram_ce, din_load, capture, bus_zero, control_reg_ce) begin if ( bram_ce = bus_zero ) then din_load <= capture and control_reg_ce; else din_load <= capture; end if; end process; -- Inst_control_registers: control_registers generic map( C_NUM_PICOBLAZE => C_NUM_PICOBLAZE, C_PICOBLAZE_INSTRUCTION_DATA_WIDTH => C_PICOBLAZE_INSTRUCTION_DATA_WIDTH, C_ADDR_WIDTH_0 => C_ADDR_WIDTH_0, C_ADDR_WIDTH_1 => C_ADDR_WIDTH_1, C_ADDR_WIDTH_2 => C_ADDR_WIDTH_2, C_ADDR_WIDTH_3 => C_ADDR_WIDTH_3, C_ADDR_WIDTH_4 => C_ADDR_WIDTH_4, C_ADDR_WIDTH_5 => C_ADDR_WIDTH_5, C_ADDR_WIDTH_6 => C_ADDR_WIDTH_6, C_ADDR_WIDTH_7 => C_ADDR_WIDTH_7, C_BRAM_MAX_ADDR_WIDTH => C_BRAM_MAX_ADDR_WIDTH) port map( en => bram_ce_valid, ce => control_reg_ce, wnr => jtag_we_int, clk => jtag_clk_int, a => jtag_addr_int(3 downto 0), din => control_din(C_NUM_PICOBLAZE-1 downto 0), dout => control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8), picoblaze_reset => picoblaze_reset_int); -- control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8); -- -- Qualify the blockram CS signal with bscan select output jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0'); -- jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int; jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8); -- bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked; -- control_din <= jtag_din_int; -- jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0'); jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0'); jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0'); jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0'); jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0'); jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0'); jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0'); jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0'); -- end generate jtag_loader_gen; -- -- jtag_en <= jtag_en_int; jtag_din <= jtag_din_int; jtag_addr <= jtag_addr_int; jtag_clk <= jtag_clk_int; jtag_we <= jtag_we_int; picoblaze_reset <= picoblaze_reset_int; -- end Behavioral; -- -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity control_registers is generic ( C_NUM_PICOBLAZE : integer := 1; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10; C_BRAM_MAX_ADDR_WIDTH : integer := 10 ); Port ( en : in std_logic; ce : in std_logic; wnr : in std_logic; clk : in std_logic; a : in std_logic_vector (3 downto 0); din : in std_logic_vector (C_NUM_PICOBLAZE-1 downto 0); dout : out std_logic_vector (7 downto 0); picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) ); end control_registers; -- architecture Behavioral of control_registers is -- signal version : std_logic_vector(7 downto 0) := "00000001"; signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal picoblaze_wait_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal dout_int : std_logic_vector(7 downto 0) := (others => '0'); signal num_picoblaze : std_logic_vector(2 downto 0); signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0); -- begin -- num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3); picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5); -- process(clk) begin if (clk'event and clk = '1') then if (en = '1') and (wnr = '0') and (ce = '1') then case (a) is when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB -- and (3 downto 0) picoblaze instruction data width dout_int <= num_picoblaze & picoblaze_instruction_data_width; when "0001" => -- 1 = PicoBlaze 0 reset / status if (C_NUM_PICOBLAZE >= 1) then dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) ); else dout_int <= (others => '0'); end if; when "0010" => -- 2 = PicoBlaze 1 reset / status if (C_NUM_PICOBLAZE >= 2) then dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) ); else dout_int <= (others => '0'); end if; when "0011" => -- 3 = PicoBlaze 2 reset / status if (C_NUM_PICOBLAZE >= 3) then dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) ); else dout_int <= (others => '0'); end if; when "0100" => -- 4 = PicoBlaze 3 reset / status if (C_NUM_PICOBLAZE >= 4) then dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) ); else dout_int <= (others => '0'); end if; when "0101" => -- 5 = PicoBlaze 4 reset / status if (C_NUM_PICOBLAZE >= 5) then dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) ); else dout_int <= (others => '0'); end if; when "0110" => -- 6 = PicoBlaze 5 reset / status if (C_NUM_PICOBLAZE >= 6) then dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) ); else dout_int <= (others => '0'); end if; when "0111" => -- 7 = PicoBlaze 6 reset / status if (C_NUM_PICOBLAZE >= 7) then dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) ); else dout_int <= (others => '0'); end if; when "1000" => -- 8 = PicoBlaze 7 reset / status if (C_NUM_PICOBLAZE >= 8) then dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) ); else dout_int <= (others => '0'); end if; when "1111" => dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8); when others => dout_int <= (others => '1'); end case; else dout_int <= (others => '0'); end if; end if; end process; -- dout <= dout_int; -- process(clk) begin if (clk'event and clk = '1') then if (en = '1') and (wnr = '1') and (ce = '1') then picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= din(C_NUM_PICOBLAZE-1 downto 0); end if; end if; end process; -- picoblaze_reset <= picoblaze_reset_int; -- end Behavioral; -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity jtag_shifter is generic ( C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18); Port ( shift_clk : in std_logic; shift_din : in std_logic; shift : in std_logic; shift_dout : out std_logic; control_reg_ce : out std_logic; bram_ce : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); bram_a : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); din_load : in std_logic; din : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_d : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_we : out std_logic ); end jtag_shifter; -- architecture Behavioral of jtag_shifter is -- signal control_reg_ce_int : std_logic; signal bram_ce_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal bram_a_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_d_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); signal bram_we_int : std_logic := '0'; -- begin -- control_reg_ce_shift : process (shift_clk) begin if shift_clk'event and shift_clk = '1' then if (shift = '1') then control_reg_ce_int <= shift_din; end if; end if; end process; control_reg_ce <= control_reg_ce_int; -- bram_ce_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then if(C_NUM_PICOBLAZE > 1) then for i in 0 to C_NUM_PICOBLAZE-2 loop bram_ce_int(i+1) <= bram_ce_int(i); end loop; end if; bram_ce_int(0) <= control_reg_ce_int; end if; end if; end process; -- bram_we_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then bram_we_int <= bram_ce_int(C_NUM_PICOBLAZE-1); end if; end if; end process; -- bram_a_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop bram_a_int(i+1) <= bram_a_int(i); end loop; bram_a_int(0) <= bram_we_int; end if; end if; end process; -- bram_d_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (din_load = '1') then bram_d_int <= din; elsif (shift = '1') then for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop bram_d_int(i+1) <= bram_d_int(i); end loop; bram_d_int(0) <= bram_a_int(C_BRAM_MAX_ADDR_WIDTH-1); end if; end if; end process; -- bram_ce <= bram_ce_int; bram_we <= bram_we_int; bram_d <= bram_d_int; bram_a <= bram_a_int; shift_dout <= bram_d_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1); -- end Behavioral; -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; -- entity bscan_logic is generic( C_JTAG_CHAIN : integer :=2; C_BUFFER_SHIFT_CLOCK : boolean := TRUE; C_FAMILY : string := "S6" ); Port ( shift_dout : in std_logic; shift_clk : out std_logic; bram_en : out std_logic; shift_din : out std_logic; bram_strobe : out std_logic; capture : out std_logic; shift : out std_logic ); end bscan_logic; -- architecture low_level_definition of bscan_logic is -- signal drck : std_logic; -- begin -- BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate begin BSCAN_BLOCK_inst : BSCAN_SPARTAN6 generic map ( JTAG_CHAIN => C_JTAG_CHAIN) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_en, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => bram_strobe, TDO => shift_dout); end generate BSCAN_SPARTAN6_gen; -- BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate begin BSCAN_BLOCK_inst : BSCAN_VIRTEX6 generic map( JTAG_CHAIN => C_JTAG_CHAIN, DISABLE_JTAG => FALSE) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_en, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => bram_strobe, TDO => shift_dout); end generate BSCAN_VIRTEX6_gen; -- BUFG_SHIFT_CLOCK_gen: if (C_BUFFER_SHIFT_CLOCK = TRUE) generate begin -- upload_clock: BUFG port map( I => drck, O => shift_clk); -- end generate BUFG_SHIFT_CLOCK_gen; -- NO_BUFG_SHIFT_CLOCK_gen: if (C_BUFFER_SHIFT_CLOCK = FALSE) generate begin shift_clk <= drck; end generate NO_BUFG_SHIFT_CLOCK_gen; -- end low_level_definition; -- -- ------------------------------------------------------------------------------------ -- -- END OF FILE {name}.vhd -- ------------------------------------------------------------------------------------	mit
viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II	MaterialDeAuxilo/serial/serialinterface.vhd	2	10731	--############################################################################# -- -- Controlador de interface serial com autobaud - versão sem CTS nem RTS! -- -- Descrição: -- Trata-se de uma implementação full-duplex de um controlador de -- interface serial que pode se adaptar à velocidade de transmissão -- do periférico. Ele interage com um processador via handshake assíncrono -- de comunicação, também chamado aqui hospedeiro ou host. A interface -- com o host é de 8 bits, também full-duplex. -- Operação: -- Após a inicialização do controlador (via reset), o periférico deve -- mandar o dado 0x55 (equivalente a 01010101 em binário) na sua velocidade. -- Este valor habilita a interface a ajustar sua velocidade àquela do -- periférico. A velocidade do host não é controlada mas tipicamente deve -- ser bem mais alta que esta, tal como 30MHz/50MHz/100MHz ou até mais alta. -- A interface opera com o relógio do host. -- Assume-se aqui que a velocidade do periférico será tipicamente entre -- 1.200 e 115.200 bits por segundo (ou qualquer velocidade entre estas, -- em múltiplos de 1.200 bps) a faixa de velocidades de uma interface serial -- típica. -- Observações: -- Nada é assumido sobre a necessidade de sincronizar o relógio do host -- e do periférico. -- -- Sinais da Interface -- clock -- clock -- reset -- reset (ativo em 1) -- -- rxd -- envia dados pela serial -- txd -- dados vindos da serial -- -- tx_data -- barramento que contem o byte que vem do pc -- tx_av -- indica que existe um dado disponivel no tx_data -- -- rx_data -- byte a ser transmitido para o pc -- rx_start -- indica byte disponivel no rx_data (ativo em 1) -- rx_busy -- fica em '1' enquando envia ao PC (do rx_start ao fim) -- -- +------------------+ -- \| SERIAL \|<---- clock -- \| +--------+ \|<---- reset -- TXD \| \| \| \| -- --------->\| \|=========> tx_data (8bits) -- \| \| SENDER \| \| -- \| \| \|---------> tx_av -- \| \| \| \| -- Lado \| +--------+ \| Lado -- Periférico \| \| Hospedeiro -- \| +--------+ \| -- \| \| \| \| -- RXD \| \| \|<========== rx_data (8bits) -- <---------\|RECEIVER\|<---------- rx_start -- \| \| \|----------> rx_busy -- \| \| \| \| -- \| +--------+ \| -- +------------------+ -- -- Revisado por Fernando Moraes em 20/maio/2002 -- Alterado por Ney Calazans em Ago/2017 -- --############################################################################# --*************************************************************************** -- Módulo de interface com periférico serial --************************************************************************* library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity serialinterface is port( clock: in std_logic; reset: in std_logic; rxd: out std_logic; txd: in std_logic; rx_data: in std_logic_vector (7 downto 0); rx_start: in std_logic; rx_busy: out std_logic; tx_data: out std_logic_vector (7 downto 0); tx_av: out std_logic ); end serialinterface; architecture serialinterface of serialinterface is -- sinais do circuito autobaud type Sreg_type is (S1, S2, S3, S4, S5); signal Sreg : Sreg_type; -- Esta é a saída do registrador de estado da MEF autobaud signal ctr0 : STD_LOGIC_VECTOR(16 downto 0); -- conta o número de clocks do -- hospedeiro durante os 4 primeiros tempos em que txd está em 0 durante a -- transmissão de um dado de aferição (0x55) pelo periférico signal PUpEdgeCt : STD_LOGIC_VECTOR (1 downto 0); -- conta o número de bordas de subida -- durante a transmissão de um dado de aferição (0x55) pelo periférico -- sinais de geracao do clock da serial signal host_cycles : STD_LOGIC_VECTOR(13 downto 0); signal counter : STD_LOGIC_VECTOR(13 downto 0); signal serial_clk: STD_LOGIC; -- sinais de recepção signal word, busy: STD_LOGIC_VECTOR (8 downto 0); signal go : STD_LOGIC; -- sinais de transmissão signal regin : STD_LOGIC_VECTOR(9 downto 0); -- 10 bits: start/byte/stop signal resync, r : STD_LOGIC; begin --************************************************************************* -- MEF Autobaud: Inicialmente, o periférico deve enviar 55H (0101 0101) para -- esta MEF. Esta conta quantos pulsos de clock 'cabem' em cada '0'. -- Logo, conta-se 4 vezes. Para se obter o semi-período, divide-se a -- contagem obtida no estado S5 por 8 (oito). -- -- Atenção: Note-se que a ordem de envio dos bits é do bit menos significativo -- (bit 0 da palavra) para o mais significativo (bit 7). --************************************************************************* Autobaud_FSM: process (reset, clock) begin if Reset = '1' then Sreg <= S1; -- Estado inicial da máquina de autobaud é S1 PUpEdgeCt <= "00"; -- Contador de bordas de subida em txd inicia com 0 host_cycles <= (OTHERS=>'0'); -- host_cycles é calculado pelo autobaud ctr0 <=(OTHERS=>'0'); -- é o contador de clocks que cabem em quatro -- tempos de 0 bit elsif clock'event and clock = '1' then case Sreg is when S1 => if txd = '0' then -- a primeira descida de txd é o start bit, Sreg <= S2; -- que dispara o cálculo da MEF autobaud ctr0 <= (OTHERS=>'0'); end if; when S2 => ctr0 <= ctr0 + 1; -- Incrementa o número de pulsos de clock -- do host que vem do periférico durante a transmissão -- do dado de aferição (0x55) if txd = '1' then Sreg <= S3; PUpEdgeCt <= PUpEdgeCt + '1'; end if; when S3 => if PUpEdgeCt /= "00" and txd = '0' then Sreg <= S2; elsif PUpEdgeCt = "00" and txd = '0' then Sreg <= S4; end if; when S4 => if txd = '1' then -- espera em S4 até aparecer o stop bit (txd='1') Sreg <= S5; -- Quando isto acontece MEF autobaud concluiu. end if; when S5 => Sreg <= S5; -- Em S5, armazena o número de ciclos contados host_cycles <= ctr0(16 downto 3); -- dividido por 8 end case; end if; end process; --************************************************************************* -- SENDER --************************************************************************* -- Processo de envio de dados do periférico ao hospedeiro. -- Sinais: txd (periférico) e tx_data e tx_av (hospedeiro) -- Registrador de deslocamento de 10 bits que lê o dado vindo da serial. process (resync, serial_clk) begin if resync = '1' then regin <= (others=>'1'); -- inicializa todos os bits do registrador com '1' elsif serial_clk'event and serial_clk='1' then regin <= txd & regin(9 downto 1); -- bit vindo do periférico -- entra pela esquerda do registrador de deslocamento end if; end process; -- O processo abaixo detecta o start bit, gerando o sinal de resincronismo -- resync. O sinal host_cycles em 0 funciona como um reset do processo. process (clock, host_cycles) begin if host_cycles=0 then r <= '0'; resync <= '1'; tx_data <= (others=>'0'); -- zera os 8 bits de tx_data tx_av <= '0'; elsif clock'event and clock='1' then if r='0' and txd='0' then --- start bit r <= '1'; resync <= '1'; tx_av <= '0'; elsif r='1' and regin(0)='0' then --- start bit chegou no último bit r <= '0'; tx_data <= regin(8 downto 1); -- tx_data recebe os bits de dados recebidos tx_av <= '1'; -- ativa o sinal de dado discponível else resync <= '0'; tx_av <= '0'; end if; end if; end process; --************************************************************************* -- RECEIVER - Sinais rxd (periférico), rx_data, rx_start, rx_busy (hospedeiro) --*************************************************************************** -- Processo de geração do clock para a transmissão serial (serial_clk). -- De tempos em tempos este é resincronizado, para ajuste da recepção -- dos dados provenientes do hospedeiro. process(resync, clock) begin if resync='1' then counter <= (0=>'1', others=>'0'); -- escreve 1 em counter serial_clk <='0'; -- ressincroniza o clock da serial elsif clock'event and clock='0' then if counter = host_cycles then -- aguarda que se passem host_cycles serial_clk <= not serial_clk; -- gera borda sincronizada counter <= (0=>'1', others=>'0'); -- escreve 1 em counter else counter <= counter + 1; -- maior parte das vezes passa aqui end if; end if; end process; -- Registrador de deslocamento - fica colocando '1' na linha de dados. -- Quando o usuário requer dados (pulso em rx_start) coloca-se o start bit e o -- byte a ser transmitido process(rx_start, reset, serial_clk) begin if rx_start='1' or reset='1' then go <= rx_start ; rx_busy <= rx_start ; word <= (others=>'1'); -- todos os 9 bits em '1' inicialmente busy <= (others=>'0'); -- busy, inicialmente livre p/ receber 9 bits elsif serial_clk'event and serial_clk ='1' then go <= '0'; -- desce o go um ciclo depois if go='1' then word <= rx_data & '0'; -- armazena o byte que é enviado à serial busy <= (8=>'0', others=>'1'); else word <= '1' & word(8 downto 1); -- desloca para a esquerda word busy <= '0' & busy(8 downto 1); -- e busy rx_busy <= busy(0); -- rx_busy fica ocupado enquanto enviando start e bits -- de dados end if; end if; end process; rxd <= word(0); -- bit de saída, que vai para o periférico. Pode mudar a cada -- borda de serial_clk end serialinterface;	mit
Main-Project-MEC/Systolic-Processor-On-FPGA	Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/input_output.vhd	1	5838	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.cpu_pack.ALL; entity input_output is PORT ( CLK_I : in std_logic; T2 : in std_logic; SWITCH : in STD_LOGIC_VECTOR (9 downto 0); HALT : in STD_LOGIC; SER_IN : in STD_LOGIC; SER_OUT : out STD_LOGIC; -- temperature TEMP_SPO : in STD_LOGIC; TEMP_SPI : out STD_LOGIC; TEMP_CE : out STD_LOGIC; TEMP_SCLK : out STD_LOGIC; LED : out STD_LOGIC_VECTOR (7 downto 0); CLR : out STD_LOGIC; -- input/output IO_RD : in std_logic; IO_WR : in std_logic; IO_ADR : in std_logic_vector( 7 downto 0); IO_RDAT : out std_logic_vector( 7 downto 0); IO_WDAT : in std_logic_vector( 7 downto 0); INT : out STD_LOGIC ); end input_output; architecture Behavioral of input_output is COMPONENT temperature PORT( CLK_I : IN std_logic; T2 : IN std_logic; CLR : IN std_logic; TEMP_SPO : IN std_logic; DATA_OUT : OUT std_logic_vector(7 downto 0); TEMP_SPI : OUT std_logic; TEMP_CE : OUT std_logic; TEMP_SCLK : OUT std_logic ); END COMPONENT; COMPONENT uart_baudgen PORT( CLK_I : IN std_logic; T2 : IN std_logic; CLR : IN std_logic; RD : IN std_logic; WR : IN std_logic; TX_DATA : IN std_logic_vector(7 downto 0); RX_SERIN : IN std_logic; TX_SEROUT : OUT std_logic; RX_DATA : OUT std_logic_vector(7 downto 0); RX_READY : OUT std_logic; TX_BUSY : OUT std_logic ); END COMPONENT; signal L_IO_ADR : std_logic_vector(7 downto 0); signal IO_RD_SERIAL : std_logic; signal IO_WR_SERIAL : std_logic; signal RX_READY : std_logic; signal TX_BUSY : std_logic; signal RX_DATA : std_logic_vector(7 downto 0); signal TEMP_DO : std_logic_vector(7 downto 0); signal FLAG : std_logic; signal LCLR : std_logic; signal C1_N, C2_N : std_logic; -- switch debounce, active low signal RX_INT_ENABLED : std_logic; signal TX_INT_ENABLED : std_logic; signal TIM_INT_ENABLED : std_logic; signal TIMER_INT : std_logic; signal TIMER : std_logic_vector(14 downto 0); signal CLK_COUNT : std_logic_vector(15 downto 0); signal CLK_COUNT_EN : std_logic; signal CLK_HALT_MSK : std_logic; signal CLK_HALT_VAL : std_logic; begin tempr: temperature PORT MAP( CLK_I => CLK_I, T2 => T2, CLR => LCLR, DATA_OUT => TEMP_DO, TEMP_SPI => TEMP_SPI, TEMP_SPO => TEMP_SPO, TEMP_CE => TEMP_CE, TEMP_SCLK => TEMP_SCLK ); uart: uart_baudgen PORT MAP( CLK_I => CLK_I, T2 => T2, CLR => LCLR, RD => IO_RD_SERIAL, WR => IO_WR_SERIAL, TX_DATA => IO_WDAT, TX_SEROUT => SER_OUT, RX_SERIN => SER_IN, RX_DATA => RX_DATA, RX_READY => RX_READY, TX_BUSY => TX_BUSY ); CLR <= LCLR; INT <= (RX_INT_ENABLED and RX_READY) or (TX_INT_ENABLED and not TX_BUSY) or (TIM_INT_ENABLED and TIMER_INT); -- IO read process -- process(L_IO_ADR, IO_RD, IO_WR, RX_DATA, TEMP_DO, SWITCH, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY, RX_INT_ENABLED, RX_READY) begin IO_RD_SERIAL <= '0'; IO_WR_SERIAL <= '0'; case L_IO_ADR is when X"00" => IO_RDAT <= RX_DATA; IO_RD_SERIAL <= IO_RD; IO_WR_SERIAL <= IO_WR; when X"01" => IO_RDAT <= '0' & (TIM_INT_ENABLED and TIMER_INT) & (TX_INT_ENABLED and not TX_BUSY) & (RX_INT_ENABLED and RX_READY) & '0' & TIMER_INT & TX_BUSY & RX_READY; when X"02" => IO_RDAT <= TEMP_DO; when X"03" => IO_RDAT <= SWITCH(7 downto 0); when X"05" => IO_RDAT <= CLK_COUNT(7 downto 0); when others => IO_RDAT <= CLK_COUNT(15 downto 8); end case; end process; -- IO write and timer process -- process(CLK_I) begin if (rising_edge(CLK_I)) then if (T2 = '1') then L_IO_ADR <= IO_ADR; if (LCLR = '1') then LED <= X"00"; RX_INT_ENABLED <= '0'; TX_INT_ENABLED <= '0'; TIM_INT_ENABLED <= '0'; TIMER_INT <= '0'; TIMER <= "000" & X"000"; else if (IO_WR = '1') then case L_IO_ADR is when X"00" => -- handled by uart when X"01" => -- handled by uart when X"02" => LED <= IO_WDAT; when X"03" => RX_INT_ENABLED <= IO_WDAT(0); TX_INT_ENABLED <= IO_WDAT(1); TIM_INT_ENABLED <= IO_WDAT(2); when X"04" => TIMER_INT <= '0'; when X"05" => CLK_COUNT_EN <= '1'; CLK_COUNT <= X"0000"; CLK_HALT_VAL <= IO_WDAT(0); CLK_HALT_MSK <= IO_WDAT(1); when X"06" => CLK_COUNT_EN <= '0'; when others => end case; end if; TIMER <= TIMER + 1; if (TIMER = 19999) then -- 1 ms TIMER_INT <= '1'; TIMER <= "000" & X"000"; end if; if (CLK_COUNT_EN = '1' and (HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then CLK_COUNT <= CLK_COUNT + 1; end if; end if; end if; end if; end process; -- reset debounce process -- process(CLK_I) begin if (rising_edge(CLK_I)) then if (T2 = '1') then -- switch debounce if (SWITCH(8) = '1' or SWITCH(9) = '1') then LCLR <= '1'; C2_N <= '0'; C1_N <= '0'; else LCLR <= not C2_N; C2_N <= C1_N; C1_N <= '1'; end if; end if; end if; end process; end Behavioral;	mit
scarter93/RSA-Encryption	montgomery_multiplier.vhd	1	2891	-- Entity name: montgomery_multiplier -- Author: Stephen Carter -- Contact: [email protected] -- Date: March 10th, 2016 -- Description: Performs modular multiplication. See paper for more information. Designed for use with RSA Encryption. library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity montgomery_multiplier is Generic(WIDTH_IN : integer := 8 ); Port( A : in unsigned(WIDTH_IN-1 downto 0); B : in unsigned(WIDTH_IN-1 downto 0); N : in unsigned(WIDTH_IN-1 downto 0); latch : in std_logic; clk : in std_logic; reset : in std_logic; data_ready : out std_logic; M : out unsigned(WIDTH_IN-1 downto 0) ); end entity; architecture behavioral of montgomery_multiplier is -- Signals Signal M_temp : unsigned(WIDTH_IN+1 downto 0) := (others => '0'); Signal state : integer := 0; Signal count : integer := 0; Signal B_reg : unsigned(WIDTH_IN-1 downto 0) := (others => '0'); Signal A_reg : unsigned(WIDTH_IN-1 downto 0) := (others => '0'); Signal B_zeros : unsigned(WIDTH_IN-1 downto 0) := (others => '0'); Signal N_temp : unsigned(WIDTH_IN-1 downto 0); Begin -- Process to perform mod mult operation compute_M : Process(clk,latch,reset) Begin if reset = '0' and rising_edge(clk) then case state is when 0 => -- latch data when latch high if latch = '1' then data_ready <= '0'; M_temp <= (others => '0'); count <= 0; B_reg <= B; A_reg <= A; N_temp <= N; state <= 1; end if; when 1 => -- perform appropriate add and shift -- check to see if we add B or not if A_reg(0) = '1' then -- check to see if we add N and B if (M_temp(0) xor B_reg(0)) = '1' then M_temp <= unsigned(shift_right(unsigned(M_temp + B_reg + N), integer(1))); else M_temp <= unsigned(shift_right(unsigned(M_temp + B_reg), integer(1))); end if; else --check to see if we need to add modulus if M_temp(0) = '1' then M_temp <= unsigned(shift_right(unsigned(M_temp + N), integer(1))); else M_temp <= unsigned(shift_right(unsigned(M_temp), integer(1))); end if; end if; -- check to see if multiply is complete if N_temp = to_unsigned(integer(1), WIDTH_IN) then state <= 2; else state <= 1; end if; -- Update the A and N value used to update values N_temp <= unsigned(shift_right(unsigned(N_temp), integer(1))); A_reg <= unsigned(shift_right(unsigned(A_reg), integer(1))); when 2 => --update output values and return to default state if( M_temp > N) then M <= M_temp(WIDTH_IN-1 downto 0) - N; else M <= M_temp(WIDTH_IN-1 downto 0); end if; data_ready <= '1'; state <= 0; when others => state <= 0; end case; end if; end Process; end architecture;	mit
timtian090/Playground	UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/ovl_never_rtl.vhd	1	4229	-- Accellera Standard V2.3 Open Verification Library (OVL). -- Accellera Copyright (c) 2008. All rights reserved. library ieee; use ieee.std_logic_1164.all; use work.std_ovl.all; use work.std_ovl_procs.all; architecture rtl of ovl_never is constant assert_name : string := "OVL_NEVER"; constant path : string := rtl'path_name; signal reset_n : std_logic; signal clk : std_logic; signal fatal_sig : std_logic; signal test_expr_x01 : std_logic; shared variable error_count : natural; begin test_expr_x01 <= to_x01(test_expr); ------------------------------------------------------------------------------ -- Gating logic -- ------------------------------------------------------------------------------ reset_gating : entity work.std_ovl_reset_gating generic map (reset_polarity => reset_polarity, gating_type => gating_type, controls => controls) port map (reset => reset, enable => enable, reset_n => reset_n); clock_gating : entity work.std_ovl_clock_gating generic map (clock_edge => clock_edge, gating_type => gating_type, controls => controls) port map (clock => clock, enable => enable, clk => clk); ------------------------------------------------------------------------------ -- Initialization message -- ------------------------------------------------------------------------------ ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls); end generate ovl_init_msg_gen; ------------------------------------------------------------------------------ -- Assertion - 2-STATE -- ------------------------------------------------------------------------------ ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate ovl_assert_p : process (clk) begin if (rising_edge(clk)) then fatal_sig <= 'Z'; if (reset_n = '0') then fire(0) <= '0'; elsif (to_x01(test_expr_x01) = '1') then fire(0) <= '1'; ovl_error_proc("Test expression is not FALSE", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(0) <= '0'; end if; end if; end process ovl_assert_p; ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig); end generate ovl_assert_on_gen; ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate fire(0) <= '0'; end generate ovl_assert_off_gen; ------------------------------------------------------------------------------ -- Assertion - X-CHECK -- ------------------------------------------------------------------------------ ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate ovl_xcheck_p : process (clk) begin if (rising_edge(clk)) then fatal_sig <= 'Z'; if (reset_n = '0') then fire(1) <= '0'; elsif (ovl_is_x(test_expr_x01)) then fire(1) <= '1'; ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(1) <= '0'; end if; end if; end process ovl_xcheck_p; end generate ovl_xcheck_on_gen; ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate fire(1) <= '0'; end generate ovl_xcheck_off_gen; ------------------------------------------------------------------------------ -- Coverage -- ------------------------------------------------------------------------------ -- No coverage for this checker. fire(2) <= '0'; end architecture rtl;	mit
Main-Project-MEC/Systolic-Processor-On-FPGA	Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/uart.vhd	3	1641	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart is PORT( CLK_I : in std_logic; RST_I : in std_logic; CE_16 : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_FLAG : in std_logic; TX_SEROUT : out std_logic; TX_FLAGQ : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_FLAG : out std_logic ); end uart; architecture Behavioral of uart is COMPONENT uart_tx PORT( CLK_I : IN std_logic; RST_I : IN std_logic; CE_16 : IN std_logic; DATA : IN std_logic_vector(7 downto 0); DATA_FLAG : IN std_logic; SER_OUT : OUT std_logic; DATA_FLAGQ : OUT std_logic ); END COMPONENT; COMPONENT uart_rx PORT( CLK_I : IN std_logic; RST_I : IN std_logic; CE_16 : IN std_logic; SER_IN : IN std_logic; DATA : OUT std_logic_vector(7 downto 0); DATA_FLAG : OUT std_logic ); END COMPONENT; begin tx: uart_tx PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16, DATA => TX_DATA, DATA_FLAG => TX_FLAG, SER_OUT => TX_SEROUT, DATA_FLAGQ => TX_FLAGQ ); rx: uart_rx PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16, DATA => RX_DATA, SER_IN => RX_SERIN, DATA_FLAG => RX_FLAG ); end Behavioral;	mit
Main-Project-MEC/Systolic-Processor-On-FPGA	ISE Design Files/HAM/HAM.vhd	1	441	library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HAM is Port ( X : in STD_LOGIC; Y : in STD_LOGIC; B : in STD_LOGIC; Sout : out STD_LOGIC; Cout : out STD_LOGIC); end HAM; architecture HA_arch of HAM is component HA port(A,B: in STD_LOGIC;Sout,Cout: out STD_LOGIC); end component; signal A: STD_LOGIC; begin A <= X AND Y; H1: HA port map(A,B,Sout,Cout); end HA_arch;	mit
timtian090/Playground	UVM/UVMExamples/mod01_sv_for_vhdlers/SystemVerilog_for_VHDL_Engineers_Primer/primer_examples/processes/vhdl_adder.vhd	2	949	LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.STD_LOGIC_UNSIGNED.all; ENTITY adder IS PORT( A : IN std_logic_vector ( 7 DOWNTO 0 ); B : IN std_logic_vector ( 7 DOWNTO 0 ); clk : IN std_logic; rst_n : IN std_logic; carry : OUT std_logic; sum : OUT std_logic_vector ( 7 DOWNTO 0 ) ); END adder ; ARCHITECTURE rtl OF adder IS signal sum_int : std_logic_vector (8 downto 0); signal A8 : std_logic_vector (8 downto 0); signal B8 : std_logic_vector (8 downto 0); BEGIN A8 <= "0" & A; B8 <= "0" & B; sum_int <= A8 + B8; adder: process (clk, rst_n) begin if rst_n = '0' then carry <= '0'; sum <= "00000000"; elsif clk'event and clk = '1' then carry <= sum_int(8); sum <= sum_int(7 downto 0); end if; end process adder; END ARCHITECTURE rtl;	mit
Main-Project-MEC/Systolic-Processor-On-FPGA	ISE Design Files/DPU_array_matrix_multiplication_3/DPU_array_matrix_multiplication_3.vhd	1	2268	library ieee; use ieee.std_logic_1164.all; entity DPU_array_matrix_multiplication_3 is port ( A0 : in STD_LOGIC_VECTOR (3 downto 0); A1 : in STD_LOGIC_VECTOR (3 downto 0); A2 : in STD_LOGIC_VECTOR (3 downto 0); B0 : in STD_LOGIC_VECTOR (3 downto 0); B1 : in STD_LOGIC_VECTOR (3 downto 0); B2 : in STD_LOGIC_VECTOR (3 downto 0); CLK: in STD_LOGIC; clear: in STD_LOGIC; -- preset: in STD_LOGIC_VECTOR; O0 : out STD_LOGIC_VECTOR (9 downto 0); O1 : out STD_LOGIC_VECTOR (9 downto 0); O2 : out STD_LOGIC_VECTOR (9 downto 0); O3 : out STD_LOGIC_VECTOR (9 downto 0); O4 : out STD_LOGIC_VECTOR (9 downto 0); O5 : out STD_LOGIC_VECTOR (9 downto 0); O6 : out STD_LOGIC_VECTOR (9 downto 0); O7 : out STD_LOGIC_VECTOR (9 downto 0); O8 : out STD_LOGIC_VECTOR (9 downto 0)); end DPU_array_matrix_multiplication_3; architecture DPU_array_matrix_multiplication_3_arch of DPU_array_matrix_multiplication_3 is component DPU_matrix_multiplication port ( Ain : in STD_LOGIC_VECTOR (3 downto 0); Bin : in STD_LOGIC_VECTOR (3 downto 0); CLK : in STD_LOGIC; clear: in STD_LOGIC; Aout : out STD_LOGIC_VECTOR (3 downto 0); Bout : out STD_LOGIC_VECTOR (3 downto 0); Result : out STD_LOGIC_VECTOR (9 downto 0)); end component; signal S01,S12,S03,S14,S25,S34,S45,S36,S47,S58,S67,S78 : STD_LOGIC_VECTOR (3 downto 0); begin DPU0: DPU_matrix_multiplication port map(A0,B0,CLK,clear,S03,S01,O0); DPU1: DPU_matrix_multiplication port map(A1,S01,CLK,clear,S14,S12,O1); DPU2: DPU_matrix_multiplication port map(A2,S12,CLK,clear,S25,open,O2); DPU3: DPU_matrix_multiplication port map(S03,B1,CLK,clear,S36,S34,O3); DPU4: DPU_matrix_multiplication port map(S14,S34,CLK,clear,S47,S45,O4); DPU5: DPU_matrix_multiplication port map(S25,S45,CLK,clear,S58,open,O5); DPU6: DPU_matrix_multiplication port map(S36,B2,CLK,clear,open,S67,O6); DPU7: DPU_matrix_multiplication port map(S47,S67,CLK,clear,open,S78,O7); DPU8: DPU_matrix_multiplication port map(S58,S78,CLK,clear,open,open,O8); end DPU_array_matrix_multiplication_3_arch;	mit
Main-Project-MEC/Systolic-Processor-On-FPGA	ISE Design Files/FA/FA_tb.vhd	1	1780	library ieee; use ieee.std_logic_1164.all; entity FA_tb is end FA_tb; architecture tb of FA_tb is component FA is port( A, B, Cin : in std_logic; Sout, Cout : out std_logic); end component; signal A, B, Cin, Sout, Cout : std_logic; begin mapping: FA port map(A, B, Cin, Sout, Cout); --concurrent processes process begin Cin <= '0'; wait for 5 ns; Cin <= '1'; wait for 5 ns; end process; process variable errCnt : integer := 0; begin --TEST 1 A <= '0'; B <= '1'; wait for 10 ns; assert(Sout = '0') report "Sout error 1" severity error; assert(Cout = '1') report "Cout error 1" severity error; if(Sout /= '1' or Cout /= '0') then errCnt := errCnt + 1; end if; --TEST 2 A <= '1'; B <= '1'; wait for 10 ns; assert(Sout = '1') report "Sout error 2" severity error; assert(Cout = '1') report "Cout error 2" severity error; if(Sout /= '0' or Cout /= '1') then errCnt := errCnt + 1; end if; --TEST 3 A <= '1'; B <= '0'; wait for 10 ns; assert(Sout = '0') report "Sout error 3" severity error; assert(Cout = '1') report "Cout error 3" severity error; if(Sout /= '1' or Cout /= '0') then errCnt := errCnt + 1; end if; ---- SoutMARY ---- if(errCnt = 0) then assert false report "Success!" severity note; else assert false report "Faillure!" severity note; end if; end process; end tb; ------------------------------------------------------------- configuration cfg_tb of FA_tb is for tb end for; end cfg_tb; ----------------------------------------------------------END ----------------------------------------------------------END	mit
Main-Project-MEC/Systolic-Processor-On-FPGA	Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/select_yy.vhd	3	2763	library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.cpu_pack.ALL; entity select_yy is Port( SY : in std_logic_vector( 3 downto 0); IMM : in std_logic_vector(15 downto 0); QUICK : in std_logic_vector( 3 downto 0); RDAT : in std_logic_vector( 7 downto 0); RR : in std_logic_vector(15 downto 0); YY : out std_logic_vector(15 downto 0) ); end select_yy; architecture Behavioral of select_yy is function b4(A : std_logic) return std_logic_vector is begin return A & A & A & A; end; function b8(A : std_logic) return std_logic_vector is begin return b4(A) & b4(A); end; begin -- bits 1..0 -- s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), RDAT(1 downto 0), RR(1 downto 0)) begin case SY is when SY_I16 \| SY_SI8 \| SY_UI8 => YY(1 downto 0) <= IMM (1 downto 0); when SY_RR => YY(1 downto 0) <= RR (1 downto 0); when SY_SQ \| SY_UQ => YY(1 downto 0) <= QUICK(1 downto 0); when SY_SM \| SY_UM => YY(1 downto 0) <= RDAT (1 downto 0); when others => YY(1 downto 0) <= SY (1 downto 0); end case; end process; -- bits 3..2 -- s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), RDAT(3 downto 2), RR(3 downto 2)) begin case SY is when SY_I16 \| SY_SI8 \| SY_UI8 => YY(3 downto 2) <= IMM (3 downto 2); when SY_RR => YY(3 downto 2) <= RR (3 downto 2); when SY_SQ \| SY_UQ => YY(3 downto 2) <= QUICK(3 downto 2); when SY_SM \| SY_UM => YY(3 downto 2) <= RDAT (3 downto 2); when others => YY(3 downto 2) <= "00"; end case; end process; -- bits 7..4 -- s_7_4: process(SY, IMM(7 downto 4), QUICK(3), RDAT(7 downto 4), RR(7 downto 4)) begin case SY is when SY_I16 \| SY_SI8 \| SY_UI8 => YY(7 downto 4) <= IMM (7 downto 4); when SY_RR => YY(7 downto 4) <= RR (7 downto 4); when SY_SQ => YY(7 downto 4) <= b4(QUICK(3)); when SY_SM \| SY_UM => YY(7 downto 4) <= RDAT (7 downto 4); when others => YY(7 downto 4) <= "0000"; end case; end process; -- bits 15..8 -- s_15_8: process(SY, IMM(15 downto 7), QUICK(3), RDAT(7), RR(15 downto 8)) begin case SY is when SY_I16 => YY(15 downto 8) <= IMM (15 downto 8); when SY_SI8 => YY(15 downto 8) <= b8(IMM(7)); when SY_RR => YY(15 downto 8) <= RR(15 downto 8); when SY_SQ => YY(15 downto 8) <= b8(QUICK(3)); when SY_SM => YY(15 downto 8) <= b8(RDAT(7)); when others => YY(15 downto 8) <= "00000000"; end case; end process; end Behavioral;	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd	11	136312	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd	11	136312	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd	11	136312	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd	11	136312	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd	11	20893	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block fOPvHkkMeoG2YSxpdCiiaIsa6OukwnK1nUpGs+ws1Kzx3puslJ7iKn9T5myI9VkVUgRFFN1Xfit5 dX6F014IGg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block HgNCPi3QHpb8dW9RkjxoUGM5YOGOMgLiuLQefgSbCuez4Gs1lAiQxdxBQhTyXNRS4H89tPbEkHbH 4Kggyvl0Af9heeHWsTafUvqQuQWNgivzOk2qQ1liLSXiEJl1Fyiq4YsawJBYE511/GABOu1E9kTU pmHAixKjBq9m5/peLok= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ACyuBPaQ3cHp5s6xGUvo899vJ+G/MHO3F7Xaj7MR44qEHb8iz7UONlim1fw/l+q+pLsNBpoVE2XP zJRxKhGGODnlablcYtB85txWJY2O5wNxUYSePEkcSvh0aNjf+cMEMsQNe2HL2rZ4QpuBDEvwlv9s WW2rOSkOtnkb96LcOQBvhFfaOnMJ1hyH3fZjN7kEzqhyOzx1lZ7F40vGA4At8E6hirc5xMjqdEgS nhipIIHTzkenqLhApVGgUbafRQbG8ESyjA01uFRtZ25J8+Pr4cs+tPGobm0XSO8t3XwLVZapRDY7 SXW1qYkISFEa6NBGxO81MTbzFuTQYdh3r/X0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block JF/XJkMGoJfUihOS9R76tudD+YiVNpy3w5hfoZ0y9FCS+pWh3V2jVVw5cst7125I/hGyQ4cnB2Cm MpdAa/YBtj6yK0ds1YeuSU2Cxzm0w9QZ3nLSon/2jE9kx1d54bisjxRhEcKKKTSHuw6W+FSHffj0 JOZyc8RfIJ5IeOr+rqo= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block T1BVKuyJOlWV6bcI3uYrVButOZWbfA/40bEMumgKuFASXUB5EUZZP2K7kyzSOvm86sj9UL9ICrc7 AvTcJqoQYQhmFnASRJLODgvNhDHbAg2lnzfWs6NJAS/1X+/rmymQ74dE/PCMYJ57I9d++M5vjskf w0OpYjhlBVYSir/Tk9MztjSWYD+sQILHVjHe47WzcVPfaW+EotqO6HFgKqlaDo7HehG2c2e3vqSf vOR+wJbW5Wf5aDiFmC5wYka9JsKtHRwx6zm2OF25VJgE3xTsK+bAIDPdQfmE1j88uDe5XhfBnRre CJ9sWYXEWxeZpiUuR8hxlglo6dezNGJESHO9ow== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728) `protect data_block XOWtDNZRv4FbcK5HgglDAnuoXeeEtQzM+5dwtbTltQeOcgiGL0ldThovapKXwlYS6j3SjEpt1ctW l0HJEu5CZQbd72e/yXjziCbCs84D4Hl2Vork8+ulXUTominLbvkE4YkL+H3FyGOZakEzvv3vHoQi bGRSzkjeHwbXiPYH59tq7tQeJMQxgUe+oj3vs74AkG1R9+2YXPdoq+c0ike49CI+BgwG1ugOKpIs VgL02xZMnagJKOXiUgf6pQ6HJDu7a4cb6y+rbPzvCZD3U39xEI3Y25hhH1UhPljfkI5NOn8Vu/l1 pd47R931h0LHGQ9zMdTwFILbWSSgIXW+Ww2X6UYKBg6+XDIGfN9yLUc0j67yNx93C6w7mxcdUnEf d5XBmYrPp9/EcMoTf0aob/1TYF6e3buFL344aO7XizDEZRYc7KG+GUeDaZr1RZaf39ICNvcxuUup fPl6qYVf8bE9LBoHxQs5BKNxGe0s69ylsGwN9ne9Mu/voJBkPMqFF2/pXAkTAXy5CiAyNLz2D4Qj Kj4V0wZXh6DUewkdBgOgMdnG4/SHl1hzGU1DdVr1bgJrunH3p4DNx7ETzJJKPsKmU685dPc30nwz G1ysAPjxF4rsT7ysCwcKpFB5BSTTWnol85/tmFsSpvgHZbfkKPGr9PEQFg0S+Nth2MZL9N1sC+eV I65XtorUCbUU6VD3zsuk5T9ykchUyiijID+xcwuAAaH6QhEosv3sG3+v4M9FbpyXXU2dv+3hmD+Q 3qI1UDa8udQd8CyVOIu/DMs7GWf+DfuY5Neb07hYJcNC12Web7v6KPXVxOxGkE1kdqsK564hww9I 7if5qaA3BuMtfL3+lBhZn5GKYywMy60g2SdSoxO5GNEuBLToM97ulyb91wYTxuvvcJ1nyjBVlC90 mSw7nXfXJjhsbDlqix6aaMoQ5mq6WniCyO3s28BGiKiKbeuQhEmN97BgNY4qvZ3ZxA+oM8ipbDzv OypQL+vvEilICjXzp7hJBlgb4Cd1aCebECNJrqe/AMHC4+pHwAd7aC9eMinjkl0PDhteljDSS4SH SI0sNHQr6d0Jhzp4UrvhRDvfJ9nxbh/F6dtS/msNc+vgGt8T0wmN48DxMu93EAv6wTDclbebzZFe iYRCgpUN+wPNk1rZQ6OWwU4Q2uE51AjSfHdzUotLRFgcfVYCKBHfqqt1xlPe15VS1bRsW2tteYvo a8vf1a62LKECyibR5UbX0qp5OwFpQDxVEu7qWqv9DpXrjTpTPEnCw/er6wej0h9FGgxxiUC48PKt t5PRY2pjB6y6ZEO/wrO3MUfjlx0pLCSBOOfRrNwzJ2g20gkUckYsJhph8I8mBaprd6qd03rmM+H6 sZ1QapOO1+AgxxoWxm/JtLO4v87aI/k7apNcMnb3rtdyX+nQlkDh/zy/F27S7SK+sxIXnYkiVjHU 0c1Tz3ay5xtmN9oMRWyPcehQ+AtIS/aGm5mQxSTRqgGTlNmmXdUm7uwmk0LMAJMx9IEVKD/T4G/e VkFj1wXaHBAjrtCIsk4mpe4/9OLRtRTG8931GbjC7aEGAFl49pXz+gEjSXfgR7jKMASaaHekT0Lf VmubPldiz1uvAREwZStCTrNJ14kjJew2u6c/gzrPyRT7hLC8HmeJ22Cndh+eMAluZ3QjydEftzRl 6/swDB4j2FO6r9VquZv92LAKPVJyjPzR6/grSYjVkPbydBSE2qSkJW15/+UtzZWdDqgFKIUDi3MF WV80epAX0xaeQfJSwpx6bP0Ag8srHZhkfU+taAeA2JjCKfeyErzjt4fwajeMkrb+v6rTZqxZzovX flE/bvBh7zd5Hskf/4gONrf2kiudfSC8AqaVFxEXDwg1zvtUTwiOunUBT78AehfyhdJuv/e5xY4k L6VuYh3esIUF3ovizq2tAX/P3X0pgcgynUvLg1ctVuJKtgPHFs8vbCssvzK672RmPwALLBmR5uxy fNuRI7fWrXHd70jRFTnsQk/HEyuNyTQSDly2+AfxaQBNohUiWtZnKDqfAAy4feRld2qMQyPediJb a3r38TDceZ6AZNVhrpp/JrwZHbLR1zzBbkGL8BvLerH3VpGSRsZDmTOmw2+QRYQ9IlnPbNUAWBHi IxQXruHEObmJWgW7PRh+5qxIocXp9CZqjojH/49FnYhpbKVNQqVb0gnRtdyDz/nCusx/6WsjhECw pteSfnlYktSikI9/pRx0jEc/APbMNAwm1xHQzemGr0L/EC1m3m90wvcT7RBsEZlK6juw8QmMraoW l9ywXqdDXM7Pg8z8eSMiavXwmG7BPjFM5bcsr6ys/8raseJyod+8DRNSbRVLBMC+x1YrqEZBwnGr BuQ5FCnaCcl+NV/i8bIE4GCeSX0TO0z8GE+2vEfD6a3vN50uDN/0pOuyft4JxTshOCiTaDOT9cTK rMfsE9EGPuPUUfmss7tV45kYpD6MoYo6z/+7Ry5lcWcAwffYgxPD4K9BXBurqWafRoWP2l/+FSEQ V/hR3oiEHA7U3nvfM+NZCXR9pkKoH9ELa4D41lo435K9b4GK69JWNX8VDg87AOmjGLHh7SRlddfr En/wyvAS9aWef7b7diP9yLE5TQS2kVI7SlMBnvwJaXkSYLwMn9wnfpo5JhosST1yRkqHbgTB0gP4 mE0prXfcH/Myaf1KJFwdxXeIHCOp+eEyuXUgyemHz5wpwY6xrEJrd194Ew8tdENtoTXi9cfpQURr O5m7wA6I7ZQdifuT4d1NftZYNxu4fTB6P8j39JJpO0aaf4ByNs0KpySlCG9n/Mah8hzV+zq78tTt fdhAnZpTDEqolldjTIGsvJ0AudF35IGFvmA9myx76yXqXo7DZzaX2MghZ0eBnxzdNeojGuvL658w WyEi1jjwZqUnzjhY6j1EhaoDRXID0IL6kjlImg5/YdUvU+KkaqhrwA4mvrbUVsXFuWUBiYymIT8u ZR72/bSZ2qHIj8CCBvJ86gUNhkW32fwivTDIhUbEqVMtsy0sbpE6fHF+AZqieahom+MEXUbCBFYB 8rJfKF78d9GDHzrihX6cerqy5UKsuMDSle++UYgB/1HS+6hm07PjEATky/704K6x1LxyPII2d4Nh HTO0znYLeAJITj6X1zXFBLRxz/7JK7PAgPuH5N6hrfA7ZgH+q8VHdKgdS/c40obQLdFKTuI3AAud 2NltlIMYtdAkPBXf8U6iQkucHZ7orFA6XnpsBUn9oY42x6a1mFZJgxB9igPiKvmqsveCtojdMefY 2SibinbNAXb84FGbpehLb2PHZgD4pUe+Zhtvk2qWyHnsMRbDzaiDhnwPmHdXJ1zinBCvhJn95gre EE1L5i7hlB1a7Z3Lndas2Dff2v1Ylq1f3779VnPSdWh4gm3eRwasiwpx+wQpWIMHefNZ3ZFi3j9S yAJk+gdQT5iBsYHod3H9fc/o7oaXPdU9T9bqAhPpIUwWg9k9Nqwx03nWngl85fwsez5rvKsAMtcY 94oas6UDFJ3qfcEdxSu9ZY5e4XS8K5puZm35BnSWjLL7DNR60HoLRn7Rl3otax7kXiZGyojKx3xX AZ2F/XpnBxK0FBVxDOxXN0JuvSmccBTp0SE4qniOq1hobl7+J/xN6bvWvI8KJLUFXrWgayB8quDp wD5RAYL+hh8wKN6cWMn2Pp2Nyu/qBHFO/yTdNQ3ZieLTyFMdHinetRZGalL2tiXtn7vljDM1HSq2 TD3BZSJs4IdW71hbVUzsO7WwtaXHu1KnPlyV8WuQBQ6W/b3zRy8tJoJg54+SNYGo0nQvzH58D465 ZNHUMpvGUgBhmVr8u2wn6x4vTBOqeao+PGh2zcyNYYuNlQFnrrdjUkFNd2SsManO0dLjZkjFTJ4J 65PTBo9JmOnJj5Z6m6YRVsnnHN0YX9ZkUrHLEtSlRkc+VBKPPPQl9qh4Xw2ETE0QRNwMsmcAY6m3 Q6lPZEOxwJU29Izx8JpmnfMYBgF40jgLHevQNzkBquYTF5jUjwwxPD0nYmett0Sd0Z4TlKyCa2pr 7HCbXu+31aP8EzOufHPPn9n2NVHzCgK0mMDae2a7bjzHjpTjOM7EK1SdZp8U8mflFR1LVczaABvR m6LlwFuGPaqtAgV3qwJpGsditX+6iy1qdsDdTbO6Ncv3Nz39ozjMhuN+45Sz9LIi9SFhS5U4VY7B KB3jG1IFu0VmqTHZA39pxGSwlMMPi3sljSL2gGIc1/A3UWcuVPB7v4PqetKn6j56wA5V/7URLTBW surtCev4U5MKJGKG5Nu9zBf1+afWTuOUzeptlfYO00jidK5FexQ84gt0crgbR6IUWhEawmroqPhM vRNI5CMzDVmS8Jm57mgSXK0H/itUFURaTZrbEXoTMjblseGaZOt+frsgHrbbyZN7kziPaFdm2hZh /VH1a27IrOuSEiQnj8fGgRgIOZXxymHqEGWQtRR0/vg8pBaLKg8VbC+FAato9y5wi/V0ugT6IHQo pb6K5lA+T1nfglPc34nWxTroDt5/3S+b7fi5c8A91AYX15Jd8OI3UVXuvCDZv2yoMWisyhbnqrq6 ArxW4Un7mWWwqCT6z9EK/B3+B2mbIY+IjxVwk3BHTc2kL3DV9oOc3Z/INEzhAUXCTBHssWl+01ZZ oCkU7BQKf4ikm3RfoEr5VTO9WhwrLGhsH3nkr/chCRd9xdQHWTIqLKq6AgxHLA3Ljm6BcxZCSLyr tJFd8UqA71VO1VMpCQ9co7imT14HxQ9UvcDORi9WKuFeAjCAMW2ZTzoSuz4LDfwdcD9LSnRL2YiX VLV72Vx4eY/I1/CyQYu9lIF++jrljWkPyAYwWoJc9cheOagsxtpd2Vbyy9Re9RHw93ovsKMV5+W8 DtOy/MbMkBSvC3BeyZWdwFTM2s/fi6Dr8yfOeaJPlIslxU/WuMGyl85DAD3SW2bcLF+STvPbhAPN ZWAnU1jFPqCIYPcRlTYeTpa7OFz3VjcZ2K5s6qBzMDZhaqaYr/Tz3TL4m4vQDbCg8EQoCCASgjSL DP6OZrdtV/hUUtWk0fMhxXKfJdPavEFpNZunrOh61zReRo8pq/f8Yh3J06c6UhSKr6WR2gTgmczo V5MVXlDvDyQwl8XjZWQNZH6McAPu4x+gAG9JhdljE9kZDmDdeWDKu8K13OCT2hgMUsbIb5OFV5lq SUUpRsu7OX6QzVe5ljg6bCWaE6PCEt2nuC39ilO+DYbe/Pb/YE+/3xqUcNTNSqeWqY/2FU6KHNOI nV4Aa7LL2pEAb9Eg7vzHIO+83JG3CdIg3L8uS0u4C1iYAfj2nUFi9liiuHGNth741sk4N+u3BVLp cN74fqTs0d6Z522ewbQeUR5nRf6IUpusjxJ4BR/8FLYp+oRG7S4LAXqqhX/hdn3gYuVSfy4AUSHr AyVYX+HmvwTR0GjLtJO1I4dAxGxapz4maqia8GQbci7XniTgZvNiS+Kv6lRfopS3nfvl0dAZI+Yq Pb2Eu/4YImPUzzJPqC9bByJwLjoGJSqI5EaKjC7gEkqQlQHqQDeki6pIMF9k4B5XQQl5oLaE9lWl iH1eTpe8xbAC4SIxqceGwVuGF1RVVfwIkO56XhuY4lsClB4WDJRL5FZeWAogtAeatzJOexW1+VNp ESAknDB0K5AwIwCzWO8KaDyfcwvWkBUNrb8PDEhpj7HsVKgDgDwhB1etg4ZVVjM68EOSS/RMrWhW WyZD4pPwSDGDRmz3+lZYYp3NdlYfameAgA3HH6zXhdoxSuOzotOfNUYo5S37Hvo4Y++1J+2nSOxs 2gtu9EozusMtsVLu7jZYMBKmqwjIim0nuGe59PVkW4TcoHl/6iSWbE+yvTTqtRBu/xFlQN1Iju4n JaegefML4jqwM+Ecov6VU/EYqExp/swWPC8qThzaVt/5q1g7skIc6O/061HP1uU9mL7gl9fN0QMN pnwz6YDYJnP36w7D/5f13DAiQ7C2mcjTdiVOhtfgNtTDA5MAKBodIGz5zXZgwYaBwBJJRQ1cvqVi MjwErKt/3/U5/kQ8rzjQQeq7J3ssX1Nky+P6JWEQ/HlNtZDxKFD5KTns7n+ovEUKqyseJO24qbfZ sdJl/oXftTHG3I7Qqw4nlMLszeq2J4KGux9k1jzKDOar+qmEpR77NjgSTx2Ud5QjP6OjAjdS0dK2 Kt4HzKajY2r62FQqwLFnWz5M5dXAYfm2HZVsmV10JL39RsFKFofHH5dFPvbPhMhYAvyBaytYQ/59 2n1+oCG4Xgw74L2Yv+Yy/NFavTYZDsVlxGhnVIPCE+kGLD8m+zL0TaXtK5XOWfeEYiAZw77F3Zb8 d9HYYRKEGxHmNHuko/FYrnmGpwfl7qX7bEpkAJOrQDa5lTjyKDg6W58d6BUfMI7lBOqGblUy2B69 44th80thR5xfYL+qj/qtIjEQRb6oI4A1b4De5BvZSyxOsgCWfmcD+hEbGaQ8c100NkALjzxY3VE4 xX2sCOIZNpes747/xq/FSgNas6YhmaYpCCNvxFOFuZyQAWRRqn/W32hrg+50CE4kHz2N1QZpQDt7 AIdwAnt7nhf9EFUwvzQQbcaGA5i9+OZMWX1fSbM+TfmggFKMLZleugCack5qSQhsvAj9ItOc3joE /CGHE4l/pfTWtLvT27+pwLJaLk7VnxNPGysYS8k2443bvIj44/uJJETgkRcGAZfXBarJux0qJNum PNL/jMyzgmHV4ZrhiTjGDvHuVQoZDFhT+dbl4UOFs2u3OZMMCjzIp8IbNU1FN1RZepfnyz9b/Xo8 65X4wvFBbOIm38EVOeROS8DhqdnSkOQFyHuzLJE6e1Q7i+807FdxaM/QBeUCSZ3+QqO/oO8lp1BI l372/vfrlFyGW6h6EKF9LJaAIpGjU8uJpDl0zqsAJVeJsGiEbmqPoSfDCnDV/ubNdyAW5Y0nPlY6 Ixc9a/x0AfGS+NoyPwEIs3zPArevfTTFxBx/G/dXGpTZ/JoWAZhXrwlF6MaWjkfJXTi3sMR1b6A0 24TgYSofawStrJWTe6PqG7Je1X09BeN0RwltNOeOCjEdiko9cMqxRvdssPNtPHACvE8fsfJhzU5t RzojhSHQsatlFZQ0XpBUPwLxbg6nFgz0nJIjA3Aiv6yjfRFBAbJED3e49FaZoCi/E3xel6nYYWsw AbCkd1j0u4OaG+PxaEQlxOUXWHvnvjxiV9LiCmnFEWfHnQvUEoi1AIVWC8NIyMXXCapzBBb1KIwq vYIDqwU1ljZgGZ0KvG9pr1HdB7BBm8zvcjfi0cKHvdBdL4EIktAQPZyel5fZe9jO67tNmsQMCi6x ZPO61n8dHbRFSbtmFkbNcm+GHjvzhAnYnoqpYCQIIH03389hcOz51bFb2sWSScMm+abt+pKOwgTj NLPWeNPuQQbAbdY66UnMbm01h7oGMv0rqw+VZ3aUf1KkJtH7ec0SCKnGE0HWjLwiKDDV1l1q3RW5 KtaLFIrLIDQUEBr/z84R4cZb/CridLnlq1y4IHRLn+uOLo8kMOFKah0wypCBznwce0PBILrImQl+ i/70t2XsTWsAZYKUtRPfj+qJ/Jz05ly7FOgqGDbmb1zF04QQEKKGLj16RIjZJS7EuUknReM4U1R3 cBYdV4U7V9+jK3JKMOGchnzgU0skNaxY5G0XrdR1x/luHLxJhmDxjazpBbaXFjfVwUtFavdgviJh CMWndo6lU/i6/mTExKCdP5hZ2cYXHJ1/39hY1LpWawYEkpvBlOiCauFMea85wv/Xrfq2dkQyNjac VrvQHyMm1ZFyqp2UZLu6J6aDEkeLNN0tMY2+A9AndDetKMQNzxXJ7QiCsgMXpz4MIiGQB69bYtC9 muiyCPLe4qW0T+hptBlxmCwN6RMvDFyHszppMEDGcTTpDBz486h1mZEwBqRWgeRAT/jdwrA2FDMc bPlEW/oyHg4UVueX0IEKRCMq2ikeX6DaC86bbYICX/Jbq6PMyH5MONkAfiRFkvJJJmGbKu/tzT9V fPF+F33bOZUvdmUZoTFcPxDnJIHybNsSyaJXAtsS6ipzuqmxilssdKe7FvRBUC8m+KPJPFffWBjc WcMcRvyOMPl8nfREfUk4ppg/U4P+4bkvA0DebS54pAA5oebK44vIx7f0rFz/nmc7L+4J3990Toe9 iYTfxihECpab8G0tftQFR5bRkcipoX0nYwhCK+ShV6QiFlTasRTJsiuLYDX00Opw+oJNmIOq31SM clVuJ9WT6zgzLNSnjhg7r1pUO/ROE9M8zec9+GhcTEMbiKTEl1MrvwcHAb2GM5Oof7CMa7bZaTgi Mla/r+wgO4az9k7tisE2nYB9AXKPamKoB3gOS5MX7HhXlFl5q5WLllQYGkRCEUBisBFikG87Akqn oXh2vKamrv1nnxWkLEbtPkeU82KPU5lpYHwkjwSzXa/aaqjAOsaG7m8OFp0DjT1nfMw2xS8oeRqT KuTrEZ9KKMcv92HYRpO+AY2Myhhg3xTXngkvusqQkbXHms2+ZnrqNQZhHCnjiFXp8TaJt05TqXQz m8azVa+EAY0iDdf6qpRX/5dm3Ft7HzCj814+pqlA0MMXET5SD6YGYUIxRJabkbbsopPULhwV597x ouxRY0f74WUHRXhezjDkqMQTEj5qqGT1wmWcSvTkzGe4eaHAf9GLA/m+60WUiixLqRyaJQVJ9PxB eX6iTHsvavp7Ur8LrWv/EOk14PdYh3Lh/62TzqaSjnF8jC8wYUgM5vlM5hl2DBLlzps6AJT327yX 0DutuynuZYYot2DRFzK1ZzAkOS7qFEt6eRCjIZqSed9cbXbGve4LKu2t5bbTKn+HAVwek45FFnug HupFPoZuspncnlsvBtnhEuHWpviUKZNdxjYxCFWGC9ehytQ56O58AE4lGhit7WRFaPtNFKRvY9sW GTMnF7j4zyzgjH7k800ORzaorICJfQqNgUKzcF9zjFDjJ4DybBDOiE0LPJ8fLuL/d0BdD+UPdycJ RwV7HDDC7fFMYUGfC6RiF1sWczVmUEDWm2aQhfJ3RmjDMkCNZWlYKLJsemYeSw2f40WPPuT9Y1dI adsHQOBkM/W/9ZJBFFp0Vw2xFGczHguu6aAE2yX5k78V7nsMW71xOZFZ4Cb8R6nahNRqjrKK/vNL MXmQw64iHNcdowrUjSwpjyEQP2LpInn6NESlj0Ryxb22/pfdM6cdZ0b+bKd1uvYvprHC0u/mIg1B QY468d+PzwWHsSLKpe+t2nMFHo08V2UprhL0XItMtI+XIRnrlZcCOGRfxJcv+MT5pjMe5QTsZEkg tZnb2VdD1h2gNyBpPvKWSzy/nKtGRcNVY/UDwLz+p6S4SVPvsM+pi5RaVkmaWK5iUK8GrnCyu4HZ pXyhVetR1cTLUuyAu4a/GoijB2iF0aDHj0Hs4+4q8ihTeRi7i5pfBecCj76pmHULeKF4DSPGYoqB n5cEXFBoEiPULoAxet8UMalRUyc35As1pFR6m31V3K8IvjuvSqjk3vI6E+sf7OZ26ePWqr/2DH37 28qFQaIAOJg7L2W8GSnScxigbiO4FC0AgwLVZ0dYVRXcPIXiEEscewkwRTwgd2ny+jvyWfbeJ8un AiszR0g4ualmQN3M+GJ6U5IGlIbVzcQ3MoXwtA79Tgkz2GIAYVkSsPVurNgS27fnw7bVIDDtEmeH tz2ijpacJf6eIc7DuIwyRetPZUIjLrXOo2FRTm0IueiXIMB6/qwT7X5kfeDK/eNLe8aCeDu2+RVP 610dQKmznv4WzrmX9Bsx7faur+gUAYtuKtz1GahhWIdR2KBSbk6wv5kYifFUyPzsaHV9/OMUrBu7 XT+8Uj4cDXBfgrXzxAcf7d+Ew5gVbSnXA9UFwOtRm2Zb0TEWaNR0bClPIqvXzBWEWsqdYKQI2o2g sghie6oYQ1X8k+/QdElVgmAxb8/3eAtSvu4b0XltOGz40et8ofuvQJrMKlNPjmwBSziwLmgcby8M 9c2gBK2N3AcsV4C8A1pMSur/m6IS0GFd5QHXiuT61lr5q3BNCa21I6w9GwkZrpX27nkUXdlbghoC pvgKXMbDHQDFeYLORaTRpfrt4+nb8AA03V9HYiXuHJI7BAADWYUUF6ZDDzCls8uddz6upQGA/iR1 DHE+vHnb3amGx/SEngZez/60NokhxCL40RFOWBbOlBai4sUoZO1R9Z14e/3h5m7IdrfxQArF6oYu NwnbEkbOp4BS8B2s4LC45xqxdqklxwTsHJHlEuGkMEP09E1RBSo2dRm36takiq69045JQO2jlD/D ZL4IczKtrXydoMvO/p12KIR34FbGrFWMsU2PKRmQ1xhdYwQO45Ih2SF3YS2Pv6eqpUK/eKtr4o05 Cs6KkCuxqvlsPsxquXsM0uRhOB+aqxZV9InJNAkXnoc49YDtOooVJx2kjq5T47MKA3LfGTPFuVVl HJ0TnhE2xY075qP4sVoT9X18w5Y22BSq0Md4w+z7jXUG2w371uvuNK31tNMa69M2kSg+89acKdlz C2E/OAQ2pa3x26n/yK2zKJxTW9MToHCWsDv386tkn72QUmZ+E3Hu2LpFAzHGsBWCwkNCfU8rxXpR piXukjtkIVzhLHBlGbc4MlRexvFwP1chN7s34Czob+wmYZeCsdlyRZEkN9kNcQoAP4i+yhuyT/yc V/lC4tulnqfnoA7ZjTuotzO2kGUjIL37reUgA+NIXdusy6xNcV0RbZAR3yXmBpxrWshf2JMi0259 +nYjIIbYQEOTnXnZ4J0SMy0+/XWw69NRbTT04wa0U+qZ3pfVO8bx9KMHvgqug7wWEqyHIxeilslJ bmFK7NyDhjX2m/py1dnrzuDCSh9f71flOdcgtemyJXDsPVCTHgRAEPQ7v8VCqIpik5FL7Sm18I8k 2ydYUEbFTwLnHY8sIIXmd4FcQ9R3B+i283c08bEqggHpvpj2aULyzgkgSbxLi99oKLkH8lb1+waA XEiV63Th/rqHB7/nIDpu/lSYwgu861PoTFlexiE5ut++6ZdfN7C6o5AoR3bxNrio1nrQDsE/XoRA E+bvxUcoOonUlL6QfyMdetYFN8zjsEg3IciBGN84QfS6P92wGuQCB+rT07n3dbW5D5VgXgle2K8Q ELZ4RSg8kZCtySXh7GMShwOQOJN8jLjvRE+v/oZz9GVLL6teFijtDtyS/v7jac8dGMg87qDwyieE Os/6Iz92z9ktym3nz5sPR9N8ZsHF9AAJUC7iq0Y2qMUsYm1H5g4TWK/t9+D5q3Xj2GESKfziI84d fGJLSSW/ISzuIOPtyEDb4i2erVhtKO1SRIusRTQJzikuyJGiiLjlhwz3tvcWj9hWi5t//FMT5j9P gey4tkbJohzRWnYXNcc5Uk/ONivVrcsE022M5gZqPMxGgca8W0LXMLY06xk/EylY2lEFahBT9m4S 3B8YQa1wNIQHlSS5qDULnqNHiexOxKCI+kHCl0xvp0uW8eTdo4Iyk1LMO8npQzW9RzD74bYhi4mU 1xSwJ9a5m6gCaUJe4ngNElHBsw6IxJ2jXpXMBizLQEE9YIo0BdhTagO83asIdDh9/fcbh9G91iZV x77q0oBu9BYhrqs9EqvR/zWE2DPAjlLR0HbO+n6RRLOLmB8LB2fvsMOYMJU0l4vCO4uh3cF6uGYp 5oGgkoLro9AH57DiF4+6jjadIUMivBDp+Co7lLNulhmU4nmeCjBti0R0HwMvSzyF4L3wqj3rAGf0 dncmW3iN0OltcyRFMQo+XxORKO+bSDOZAVzAK8ZqVsh+UfgcjAboJ6hUC77/oNP8howK5F/i7G36 Sxgm5dwrok18WxFg1VH8ji0GrXzLpwMA7CCdCr0m7ZyHXwyVZ+kXXz4Ts0U8mQ4nAAu79BiMxVTl cFFAYTEv5tj0rCGck93XP7A2U6xEMJsdAvjtoAXN6jXjOgPF3StOAcXTsDNLI+QDRSwj/NqxbMih ZIVnuCmoOIktmVsfT9qdUHKGNX+E649k/TO/IqsG12kFzCelfNeBk6vq3Aqm6ZSNV6bR786/OxSC p5XkcpFsT5Jorf/UoJi+j3SEpypQFUhUfpFsWkWEQWWmaa1XC6D6+jzn5BmSI+D+lx0WNp7+oLkK bpOA58hLqbR9vpJ3gDqFqut2S99yS94rmfgwbYF92qnOHOQep4h1TEjgSSvnh0ApZLQjXp7uzxYu GjoW9ndJi/ppKmsxLfUItG4ctUWbYKVTej8/mpN/1rnvciFlwVjcWFP6J+l9UqoqzcwIL4iwAukj m5lchbhgF0FBAjq1zTidZ2U2GaLiEQEVmquz3P0XqGgXpiNf4dA8Nk/L7TZrOuJ2nM6mqzx7cEvP KRHLWOJkCZu2xKPSDwHDgaK91Sz9pzDB5ZviO8U+1m5Q/Xj4mKI7YA9Y0fH6eRiri5smiLEkCfD7 28u+uGtHZjAic26PQ0c53PN0IHdeDn7SsrUhWMbjP8u5sPxcBdUmTQvB+wb/Ya0KCoOgK1gKL2cY +TBRFDt9ACl2noFeudVV6EBk2AUj4otaRIPnGbi3cCrVhRF75VV69bpyzKmCC74kyvUXflIX+m85 ouJxK8iayCLSe5eROn+0kDJpmkTzMIl1vrJ6jnyIxcg1iQzul380xSWcC1z8zEOFc5K9vN6/6GMU rcKSIazZe9HmXX9S+YTdZ35AEaAX/RJ7RR3lOhtjIY8jyQhzPdUoghwmqOGyyWEgOMJMnaPt+J2C g9D9i4zwdd/xoOBq08FoXbG+ilCxYpCuHhpTjUw8hFw8eetqZsxy7CIkO3cUnROzWX6jJeckJKNZ IkekzPEUUeLMnNCwKsvY0TBg0g830zSTcFkD7J8zNBNQNgFi2oTH0iq4ZvSFpW/xTVJMQGu3ggZ1 hlGYNUTZiwf8q7m+OtikTnL/RuEn1OsBCoKf74TxHyDFcaWYyNNN9FWhL+QIphWi5gKt7/XtmXQE nOdyTqzNnFvjhnqlu6Xi6GOc4MqqRY6Hl9XBXpn5LkEvOf+cFikgnFvVPlU7sLjG2wbY+IlF41MQ sucGJODsmiRJNf7BX1wo8gJCeTmKbMuj9BFhw4IzcYtYZtUWZChBVW5PF4s6z0IK4qeWZUk6yjRD YcDxcvc2COnsalAVk6wYlVEudxuVusigUYIOTNGybC3o+7HRXY9vEtMD0ZH3wQlA6MoxoNwHDynl RJaiK5cVjj/8ruw8LXPOpqm4rZJ0Jk31zCKr3Ib9VRPGKkW0h0Ms17xFlF3tITEcAE44D2E31urU axXMqEWxT/HH9/Ba+FI1lOQDO8WlTXG/TOkPwKM7AIP6y2T0ZrN+43ckHp60NsfUIGHMOccBjUeO hWXcHl18KB00D313tCTaXwa8zZ//gwFqoN/0EPZWDa/k70q0KUzcsX7lbQPlzC2M9MAbLcL2o6ZV DYS1pV0geiTdicnQFohArY0zC702G839afiK3wlV3D3ydl367Yx+ssGDptp8RP/T+VopwRAs1O/Q LvVF9+T6JIA3zS6e0XPjBri4TlyXarDtr9q6NuiGyK5uXCMb+fHXRwaZ8Fvi7ALKET/XvhCvtiB+ tCEbf/Bogxl83Cih0Lv5nXuBCd9yu/BdsmkI0rvXp4CHUbDbCz0mtL65Vkeo3C2u3CGaORsO2+IS xmPPiTTyyArgns9C2OXPrUQF08EHYflVF2C7L0h5QBQ7zlWABlIE3FNge+0iJvurwcwCyUuurRvt xxaSdrK+rTsT0aWkGrhV9DPwYMv0GfhtE/cWTTtJHkYCz7ntzKqThRPvnHAT8HNxqrrJhdgwgiAc GmPuBoBybVi5TjooZNN1GgqU6gD4yuiUnwsjYkwNcyX0EpZFSS91ttvJ40Q9wHcoCkh5g+W72YuU WdIV1vRoJmzhcJmmD3/0abZbJg0m/GI+U9Ld0MuXQmsxkuZvVZcGm9YvilIkw/tVbBxHQzLFuuHe y83fCBHUrhX+5aVp0oQ/xKzv7SAgYjUUvVK54xCM9+f0I62rLzR0noXTXm8LhXK8g/AdIjo8dVxF LNNUsSzsv7e6C2r+u7LiO5mg8366ZeIQqfY30TZ9Porubd8h+fZBm+SrKf+k3OF5bLvzw2C9Xh1b DN1XgHAZobO5ESsWhdZfGwwFSKwNCb1SEpy1Xu61+4mDMtw9Nor3xMjVRQcFJDKfOfv3HEFrb8GG JtnOxre0swLsZ9a77m62ySn1w2Fc0NHL9BK1nL/g9UUBBfDj34PeEVLBor3RoPiOQtnciAVLAOjz aOC1Ke7Ef/8EC8Nxxje1WeXDIo1J8voygjyTpPm6HRH3sGm9Ua/w1B6ssTwrR2t6c+XIhbZx9D59 ZhX0MpGvxVDdpZGhn/D6qX2rgURptZQ6yPq9smFwarzpc26kG3ZJ1dA5rwzHlYex1Aq+I3/TOCqQ oSbwSffhhTGfWVL4d6alrt6lWnkgSz6SmYf0GoFLf1ArpaYsT1meT3Wlj8xN/qdsChbAoVNH5czw ipj4BVzziC04ELaLJCdbTGfaJ5g05+t+Obod01qF/hJ2Vh4xosD74zEBsom8RK+0rnYI79rqQljm 8jMrB/KiCGOHa6m/XvNEjSMDvYeRSLnKUNMvy4TJ1Heamzs174XWlP1uOyJr6U2srfB5zDaF01hT VU0gQXIRwtamaUPzlcwL50oK9DbaNq65g4vkvwTc0UA08GUGCqNXyqNvLHmg9KE+4dw5USswRN1x EBzJgKhdyoJuiWi39pZFtLIeWiB1vbbG9oA2TQQr99lJL/DwHrTV+aT9/ZzBSVA6yan0o8oVZnPI bDIxzxOp2Al1aKZDj2EBFk0e7qj4S4cb/gNOWSuUJD9p9eRe2P1LsYbuj5OowBsoo3//BV9mvd3p 4BgOuNhgDhkzuv7oFD/UmtZhnwsYPL6OLbG8gAqNR87UbEydaYjd0t1Sp0sX0aB/h5SlX9Ar/Cxc MJUQwJInMJ0rCFkFDRmzIKLtOIWYzEuGcdhIq9e/HNKBM5LpRal53roPGYgOLxMDYDkc+kQzI5FQ D9tLQBAPNFRBrphY5Sj6ChWnhc8aeDMR61NTbrONci65Noc6a2f5mZKkOd99g/IjMeSfeJCCytpG 7+2pPqYlXuej/U4GyeLDZtlFiEXXEMAjynY3lPmLXPmDERoh6Srs140pCLIaCPFdLkgK08CLjXU9 kWpOrKtO15UtWJ3RegGp9xNnitXspY9AqJJU6EGf7L41yVl8u5eIWe2qdUMU4RyMWqM3HIV/8GW/ +ZHrbUyTxmuaZEMYNgJNLfT66CtYXJRsY80BwvJINvyTU1K6cmudreU7xbE6+ywGT3Zq2uYq6KqK ZWAFwT3JRdYihXyb+9EMRy2DIBsWdHwvyaFb25OdB+QGj0XW75/3rNr+7pllg6ujkbTHt57/9SqZ SRJLvJ1QPtGT1F/RGoXfwpgd9rgsxqGOv9oEbM0gMiJA3QvI6IimF6X93Usgz9cqyQKQ4JfGue8L RUkM+HE5iewMYx1RPhkj5LRdP/oXccgatI4POJsnfvTY052IQm6ebgEK76HvyTO0YqFInlHYd/cj 7Wd4XMLkAjjWbfTravvDhJAQe35wvrF/Ltv4/ECS/vkDjCiRfCNRoW8sdU9Kcsk9j8Urgncb6oSn IA5Rei8sL6lCK9J5RlcswwhMs2LP+VcJQgnzimudafrauXRTn7h/4odY5A0Izo7ruO+PEMh/kjzk aDd6P5kINr1WOb0ZxGf8M5o/vmJEmrDPHff1qEWjudqaAsX8xBbLsnj7/Vce0oFM27w8T6W5wda5 Uj8kOOf5+6cMqnsMsOE2FNvmmmMQqV+UbWi0mTfoY47VmssCIWRA2GTOBdXnn08ivBrkMhwrK/bw j/mwxPFwrYZdfahfSeyHSYL0IkVFoL42Gew+lI8hajz20O+JykDtaXGuYEzDBO07HBWJVj4qywty WNKt6OFKBrk+QIeO/iY/iELeOPXvALgvrzK46fEhhFBrRgedPMMo7cX3RUweYvTYYWt8QErVaz1b YHd4SzH96qA+/vcAShkWAGdObyCMT5bdYGeDKIKqbdlZanUCWtJ9m7DuaGMhl/m49yOiyKQCeNnq DRS0UEH3mhpmKJUs5mYw5Ti8/RpPCf8NRGYD4ArFqdNafsJ4st5KW9SrpQDXzVtGi/ukdHATOLyk bGdzPU+aPCwXmELjUxOeiSAIZWRhsoI3Bhht670gtQTiFk+mxuBxfo1+VD/69WxKUpi7NQYzdbpj +SW87PdzXhL278diGJnbPivjaiG72mcKf/8cFgK4Z2ER7WTe/HyGnND/3vMTeP6r0SJ4KhusbArx 4HsQtxS4KKEHMTNr5AqRU57BxbLZyohF97aUfyfSOMcoMh1oo+uMf47DyBZpoZCz3Vyo1sH+AYH+ CqmEXlMT5JjHdyJ1jrkUgmgraZ6tRxY2Cjy1SoDGVwNK3BaSkTsDAzixOrqZ3qjY6F5z/FSCPhRu eRJ1cJ4rSxbXNDE6/9UXbIi8w4ayXbSZ9mSWT+Zkny9g3SbZuG1hhcqsbpHJyMc1g9HRdkbfMtYj Ce0nO4V2R98e60KBiP79DXREuxmCMYrC2Z+NLzWaAFoIvbtpsMa0wgjpgU91z9Ea9u5bUlGzGoom INTHJDMQVbjyYYgl70aWiOIy92yWFdkNVDwcI590eTUxllEtqpGb/kjJ4kRoZu6nHzBDhNeIz3AX 5c1liG0VWl7+vtXStNnAGnhK0w83J5P/iz+7zyF6PXYlvCGMEpMrTkVHFcsZgEiI7RUvL95zyzYb kMfQB4HRDfU1Ki98LfdDX4aHxu3ytB3xkoj4Tfe6EZomsY/vAnMMoEJyIQTYXLxykN753uKeUtMA 6icJzSnsRmSqmSOkY8z3L2YZcSDhOI1UeCd481Dh5Cux/qNcWWW1nRiR7Z7OcAkQBnD5DneWa+2C 5y7RVjWTuF5ICG/iPRgSpVuu2lIyVEGJpOKe+HJmmFoOBV1wxKRItNIUDbcnE3sQL/vrjfYWfZ3a 0o5qffEIhvunKnQ95NGXO40wFuXj1mnNCC2DMi8gV2R/xSn3vSXGxDPYVfM69vDTYbrkIrf8M7fF XqhqOZQRmZ+nFqcR9kIz0Yw1rWPliYfMyvnmxn2r7F7yzKjmaXma1SoYxw4E3WWEJAdByh69Jnph /4xfq+NBO1LUXgGDMo3n4htdcpTaH5Xt+Zsp3+hoHu9LPQAI+eLZgRmmPehuEuuCrpeg2tWDr3B3 Y1mk74Lvq9gIr7HSkIDZwr+UHwTiba8Db6HLV8KBsOR+afRvo4eCjZpC4CSG218nCQ8o8GztAP5l fZyqFSUCgyIyETZWGGQFhZQRZCo3puBXPrUkkxqBCnsAAVi9KD8LEHXuREb6AUX2T+zKacAAavL0 wpvBhyLcM3lsqWZ2g8DyDjbrMiqpO3FkVvJ+X9K7pFF2d4WDlUefP8Dyc5CZv6yz2s2WIyHMkL8w vRr62JX53ynYVYd2z2eiX9T6TxwIkPCyu2iLepF/QIKOpDAmUamh0YOLFKcLLlOYmSNXqGinlsWa 1Bm6nuu3jSHt/Sxmb32WM4YyvCmE30N/wuBZ/OswvWS5a3lCdoNMbC+d3Oky/snkZFms0MWdbTeF RddKs7/tbLYcgbtRyQJFZi4EZj5MmhZ2iVjvThwxdxRIrq7jUp7lFD6tS6krt6DqazvxELiXadZT NC5kOJJ9ErjZTcV6hoyANZb0WBx6LHbR2ZgxxOkcedH7DTzA8f2dCVwZVWlnrAXuKS5BjTe8RBrL G1jPAw/GtIILyY57KdFw24cpK6OG35xI8KfqtNGqFSqmSswxzSQmf84cOCrgIXlm3D9ZoCFKA69S eO998PM/dXqp1sk/ECqsaSN0IgaShVRII2/t/R9aqG/E2eayHrFvESZqWYmCBCu2PNLaZHy0WlGY /LWK7vusAphHgwxLh93S4psgDWyv7A1dhxii0HAbIvSo28RT1yCHxJHvH4jDuuMjEF3NL3Cvc7tq D8Me0fX+99xu1gN/djT4j8vMBIXX0UtmBZuLW7Q8rZYjxWDHEepie8dT2YN2EsUAF7cSFW18lVP+ ubtC04w+9IKN7njywZeEwhACtrZkxtnl8/LyHLdgu9HDv/jq1KFQrkvqbNt19UZOzVP0RYXwi3k3 HkPSxZ7m+6WwUK44sezKtdTuHMPQrfRy8VBA9kdc2z+dI2c3FDc0/B82Mnd5ZV/WOZ9rz6mfECFZ ZMTjWoVCODKQh0QEosKKF+LCyQ0bxpq107lHHO7Pq+F+dTfHdFOu4XGLe5inV21AqyPgYbqmlQFx adXbCnXfOBEokbmafWu7fF6tFCvndt+/kqkHqE9V5xspRjvrZ8pf5nrRoIkPP1b0 `protect end_protected	mit
Nic30/hwtHdlParsers	hwtHdlParsers/tests/vhdlCodesign/vhdl/interfaceArraySample.vhd	1	504	library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY InterfaceArraySample IS GENERIC( DATA_WIDTH : INTEGER := 8 ); PORT(a_data : IN STD_LOGIC_VECTOR(DATA_WIDTH * 3 - 1 DOWNTO 0); a_vld : IN STD_LOGIC_VECTOR(2 DOWNTO 0); b_data : OUT STD_LOGIC_VECTOR(DATA_WIDTH * 3 - 1 DOWNTO 0); b_vld : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END InterfaceArraySample; ARCHITECTURE rtl OF InterfaceArraySample IS BEGIN b_data <= a_data; b_vld <= a_vld; END ARCHITECTURE rtl;	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_pkg.vhd	11	123927	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Ccre/mo4iYR6ZSgOg1gk/7yavHm/Tab3ZkZcYFm6mHsK2rs8opjY2zm8CLFAxyKzM+XWqIQXr/Fc dQ62SDu8pQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYd7hG/1lw77JWK+H7uaCTBuAtJ0TBNBmyeEHZzKg+QBt3Cr/4H8z2MUPj6pZRjBIIMcBdDyWAg kFxba6x1wM6D0583UJ6utRg76JBTYn3hze0vwLk8TflbT8BIsLMY/07o7U9RQLj+Czrd4nu/GcB9 pJ+rlEp3a0iAZrf+WXM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block RfuO8rrKLN6nyJNR3MR3coxhKut1qVIAuEdjKuEt9/BtiGJZN+vho3sGPhnXGPXiGhQsomdebq5G ubnDKN4NlrU/K/1OyNtvkXiCQ0yq0PS2JdWUylqpjwB9ynBw5A57ADeaCo/udDuX1y5wHWGkhROQ fsJZ53VGKb1Op1Lb3r9BDB8N5YilEmUvvtSyFbdB+7psIBAUYyMVMn5URNhxA4cyzgpgQhfcULcK sD4UNIk4VWttF0vTTR6gUts3jmAIHyHf3d6WxdEAShshX6o4OKR2UxT4uLzQata959gMnHWV1u8z szCVxPR8xQQ0v799z81NPg3yNd9QbIa33NfW3w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vxmmKikWOvh/MtjVuTOdXUEizG5j31xAKxSiM9Xx8aixITyV/shFEvsvoImS9EU54TgPNBdxM8IR npEUXOOcVxO9WfGzwhZNQ/ZK0jBxGyrb28doc6RBBBRFSLq6zp6eRXW4db+xriK9oYHqwZlnFh+p +PrqAo/I9KP6sZv1oHU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kSh8dathlvrCSfMnDfy+H9hBRQczNUVPEe4uv9JEwCAa3/2S1CyBPGf5gqqXuNXvqHZolzJIX/7w pSnd9F19rFWLAuVfzyaIPlTZrAsax9Nea4XwtEczdmi61CkouLWxlFuVwoM1bzkNI5RFMcI3c+mY VVE9udu6in+oPKf4Zn+ElbHY3V+cc76JILBdVqpMZqtx0VT2JvmWZLAz3e78avyNNr3Xow0ywIGy OdX3dLU09soUoUFPZH3IK98LoelBpKnR1+HxTI22lPYimCTRIAx2buuEryXwBu5wfWWSCn3EPtF5 HiIi9rQ4DoAlkBvN4LqTfIdUNmzaJr1QCruccg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 90000) `protect data_block lvJgp9F4NgHfQyd0s9WfMj2NKmMmK+cVw75XRIANBEFXjAglUPymuokPQnOMfyJFPf8qKWlwo3Qe XrJHuaeX6LKfO/NZ4vjdMRky3qPb7KS1ZDXX1CP1z1s51WQ9aTQO6BiBoNW6ouNJWTZmvWcHc2Ln YVf6M5x28gNptT5WNP+UIgu92VricFgiOBR1gPIL7FV+IOzcJznZbjyvYSvlGJdvulnhubW2D3JW KH6ybsV2LnM8zlsz7L/FyejM4DfPUIqfzrVM08P0bR3I/cxLPH/mVg3BsSIMreRHxSyPg5oJgT7D cAJ41+YIDsrJkB5vf/CYBXpOcT06iQorhXtVQLq4DPxY3lzIXuYlbAqYKxPLcRzPrr0e2IB0CoQJ MDZdgW2WWv7T5W+8mJ8+hwnyhFhP9sv9oMmGA/gM9vaCyFFxsyh0ybR63XJXfPaR35uhG3lSunFE oaxRIYv6LaEaduqlH3ZgH2OHX9IkqqTK3tweKgRuAfXLoGkE/6+tYPmB5LuBmSif1yu6bzDGIATx rauJ16iPQRnnBIMEReZK8gv/30XfdrH9NmTDag9LOnv9SCeZv8slp6k1WjfEgPI4gQU6AiCI2TxT AcwN8eSlKJ6i98Rw2jb8N16ORwBUpupPRejyRA21l6dL14kBHeZODL0LuAcIalmoMdd2bw2YRzMP R+kO91ZduRRzsBM0mnr11LFV/OezvYwU3prAH0gWn95fyGniKpD68fYmccEtwa751Tce455rDm+l kexsscg5DWc4PRhHqYCHk4j61IISlAqaYbn+WU5gaGNFp7O8UcY+n4AUAQbemP8fT7swYLfGxjQ3 z1+SUbUzhrq2vGFr9yRKAIbW2YblXIshzH5T5ezD8kQu8/qP5FKtwRQ9PkYTv1DKVC4amA8/9NB2 gq8180MPsmlVTYaIvCso+6Ohy39QEZhX5f3WXf9pqnMDxipiq0DVnoWHET1wDzF0Rucv9T2wnf8U 2/ubcR/Cv8DE6gw38amZ4XlnaUux5M3T2ljijEPBWN1TFf1ofwQkRafL797wlcpsKVB/6twM1021 Tvi9zxbYU0jnqqeIjZnYCZB2+MpPO+CSkSSW7IzbF0Mx7mXmO8ytmUe36dFEMa3c1ehkk/V0a0OA BCp7bxRJoRiyzLi4z4cSvXPPjxp5aYGl/RG4Tf8XDj8R7BiwBl6TYf3uOHUrKUns2QTV+Tx2aRtn okV0HBSuheoJNBt4aKG7PUfmJ799ESS/o48TBZ7rcxWGj1Ln2oII3pBl0AQ5+zD4lzbM0kktTg/f c6Fhus0fkV0cdE2B+6awb8jenB2oo9At0esjmrCvn9ixhYQOItm2Mb9/t7MsDqThbhUx/E+9yXoz Iy3BuZyzVCITVuN+4k3d8BzMqIbvAp72Hqbbxcq/Oe86UYGbaALGa9UH2pMawdeidGIeeK6csm3y +KAMEhxzwHP2PBNr4aXiTId8+tIljBF/B2AOfDtV80SHz7lpSuj4kdbcSyfDdwZPsvXKoWnlRxLi AkOJfGgUVLnV/bRY2BnJ4uQ0ssX/gd33ANwScw4x+hHdeQjh+OuxYpfzwvLPUpeY1jqCROIGODl+ IaS1GWG73dhWFKgF41chiVZAHh1e8jJx/u8SNs7DjMot/I+CBJPylr620/R61C0c9BNMJv8DEYOo XM3gTNlCf/KXySjYIwqu5eax9GuRKHU4knBwJnqEgW+EA8gZQNRuryAyu8t7aze6YGgXv4fYn86U +/PFVHMO9HEjHWeAKBwwXiezGABUXEaHuwoTbzuIW9n7u7sfobAgnjX8GFqz/aKaoV3MEVI7Zv8+ kLREvGPymwmhxP3VTUcjjbnFhnrZG/pBECqS5eFgWKMR7nEYRNZBnzOqZSyxk9ovt9MVi5w2DTGL XyBTLyDfkljIPB20BerlXHMI6uuB71eWALT+IHAP/uPBZMvQFH1mktW5JQqQrqwNT+flWPDgedNN Mhn/bIyEVZww7yGFdOj1+qBEUC/Hx4vE82P1fjzQb2q18Vqg5+fhn5HVQjoR5na5YSc3NG3rmK8e ZYvGkBiuWXH9HlCUNtSSpru8h4idk7ZGLb73Ff1QzQ9WOqULWs1b326ghEp2pfrNAZbJmhzj5yxS YCWLlQZDYqkGQ9DXZfQnU8sDWp5eIQLieRWHpKVASY0ckHpv2lbWp+X8UvoURRhec8UFL+lXpvfy NV0Ht5J0ge93Y1Aq+h9+zMLaUIlwaGCex3HSyKfUpNOc7sgsBYY5bAGp5cp9hWQtz1IFdSIYPOFy UCyN3tsgQ4LnjgKsVMJasDyCwk7NTlpVRAId8nAdlDEJ5deRVpwm2BKbyURzbAzPtt32gZ8fhaNi 7RHtR1scsrYFDFdg5m0UaJaowk9y8khkPN8tHbbF9ClnVXe3r7Xa7VoJ8qqrfGLfbAWaG8Lp++fR wucf8SrgnSdZmbsCsCoVtN+Bf1z7I/I1NH25bIKlWfkulO0FkAgr24q0RMIgh/L95wrqKkYQ9mEk 9T3mnz59LUEoNBgxFai/PM7IK16By1hAUw1ufscArQjNEk5ndbzHqCQz2jzLOOsIGuIpqtDsJ8P9 S+eByrwbFio4v3GOvNtoG2T2aJpDUR5frWV9Wz48i32Y+dHb3Jl3DIfrGPFnPzKwi3vch7A+U9Dy Jx8RxBl3kAz53wsTI6ZwLRZ7nPPIMObnvo47rCCnnEkMLuy3CXUiZe26c+C/hgYNBG4waSnk2SiF 3lQ3+imjn4bO1njhwI5o6v4wJrsKwTkyCZyjY3AjzjJqxD1BvYbuO4Cak85fXwsdhDSUypcId37D kJYMgvtCMsMC801Uo2kET6q/zFFUjxHdR7XESXnNIp+KvfRA1kBF6CUXjDExyBTO+J5VLf8t/gWh tihxBHNNDD4Cel/IqM707uhZguir5/6/HeGNcOULBKU64JaUO8C74AMbsfHiNat/DVS9CAhXqYUl mxrphLZF480SScZ6o8qWXgAXl5k8Ogv2gDQxnn7/phON01yzwh9eedJSk9RWG+bxdNcO/01whxaL 1Hvp7+tzu+NHHjW1l3haurDqDVMmp/LLLPUE19eJUER8YdY4DqIJGgQvQjxPmqg/+tbbFbeFjTaD Wk9AvRzP+J5a1AoDGhRLpcBHpwfj+51UJUiTM67VwRC/BSYqF5nJGtDGAXRJ8v+bfcXhNbifszi3 yvdW4B8eNFe4H/lfgO8h+qXSEAOob4zre4UBdodfqaUzq1S+qtqZdGmnHio9rN/z/RUMl2YDT+ul nEIILSBI1xSVExKpHRkmLwGdyfNQtxwJJkRvnaoDa6yYejpEtRHJ4bfqL8caAbl7IEJgEtwUBTh8 MVjay/FT5USvbIGfU/KQX4ptft54iaF+5hIJ+eJE2ZT72SWFgy/tqGzKFT0sfSqcAl4uKiH/DSe7 9YoR7Wgga347T4L/swBR+5iguE8Cd257P90h4H7pG9S8wkuQJGzAPucvMaRLuKr7Jm7Cyms7rnxp kxh6G1pA88HHmIcmt4/MWaSkKyMYr0aMS99lg7JcQ7RbqE7LtKh0pKVthiUTzciWiXExcbnNPv5M 7QfSUtQtJSJiTrIu3P4mmnhxgPgcrl9BQZp3iETjJOk7eDfJCInOhMEwETT2P8pvT8RPUUSyRbzP WPssQ0OI1zqmP9jsOpHzyST9bN4xlF8OxmaLFFEddHelzKwXHLRgPqvH1+GDkTYzTZPIZYdELWW1 0d+CEtgda1eVep2JKkZpHjqmD2z5AZpQwKVkZ00T/1p73FoqvfHtbxBgIO7XKMAQWONuRktcTW5I 7lS4rkerJze9mrOnsIqX0mT9dRuY2ZBhALupbTvIg+4FfAXk303/KvnexK5GPJTVFo7ZuIC66LfX i1CxAOmvs9sj7iJaJy4B2MuztvDHL+Rdm+ga44q0QVqkBheTT+wLAcavq4uS4aqk8dcAayabtYkZ wRQf5uizuL2K90zpudVZMj9puR2DSOqW78ttFegLgOvQGhfHA/e2Vw/t/qlQrhRLGd6KuvIo6tVt q6BYNMI+xNyfV3l3n2EC1qMpzlnTUcutOyPkywXhUE1vsYoegO3OR77Icz5CP03FIb9bbKfjouoE bTCstTfet5CjURS5Jf4pBHH6bOvPKKjdeUyAJurr5ZHn0K+WgpQ0oPN+sMINyvTt2W45TxOcEWXh krsYMNYe+epYAAbOMWhRCKGVFfudZpOOD2WcqNvDsVOmDBzLtgaM30ljpOTA5a7+3qsvdzxe3pVC XvH+O5Hfr4le+Zy/+eu2PYwTysrmTKrnq7OcVNGMQPvPmuQdcY6+X8YVshGjkXnNtK5qzwMFeTZc 1j2JdpDoKsONbLJtiGaONZFLQunFo4aWXX1YO28V1TxyFgxGGgnGYzNuISiFE7av92Bmt+X8ex5s r4gTpwBQnVXlp7tK/0Hmqu3wJR7cjsbEVFOqKe8IwYqzL57/KsKb1f6hLaJ+aT+KRgauATiSKbF3 G5Zpbj+LwukERrhoXKrGeMFjFlaTfD5NV7RDQhW3brZu+4drh0hQe8jUhxPysVPH2G2hSrnpTr8i cwLKVay7ZX+IXFR38K+HHOTYAH4hMOrBLxu2Cpb3Yz+DIDxTDEkSyEiOkBt7X0aYSuxj3JD/J82K bjktME5B+v7eSmOucz+9Vtsec/uPCgj+BcUPQ2IqkIryNpZ5wRPUuRjiVGDu4zHncX8D4J4L/oEc LY94rzemfNaV/XMie8Nki/rls77rtdOXSgEsQrs+n5k6O6iEfLEc+SJl2OcvlRIbPjGGLmSv8Qbx Qu/9llVSFow0S0Q8cqOtNrUrRhROPd9tfGIbKlqdpdG9Zb00oPXXHtC5KeCjokIUYjC0VrdEj0nK pSRTdoi9EZ9JFVEcdnYvAo2AOZkSoXytlMFq89T5Qv5qLfybNZ8NDNGf6zb2YLAjuQ6QY7PKOCgQ egzmwLkYZlU4KcODH6HT63tpLfz97OPXiRnX9lwAFso1VSUyUCpGy4xxjs+kVIivqg/Ho9SbHnx2 jRPYOPopVcXQr9QUxnHYiEVeZt4h74VpLGTEFICsOOsLIK9eujhu6kdZyClRpsJHcmv6Gg0ZnmGr CLFBboFURI38IZAbpsc5p9T2fo+TXwcwGAqc8A0SkmPDoAziBBmEmmUg96em1zE9eGNzy/cJyb4S 6S80zn+i43Zr5qiE/ueCHjrusoJfCKGON0JBfQSCTAK75f+OXeauiTKyQX/PxvLnUU/Li5j3PqGN z0zsRW+k3kaw5PCK/QUDXYOTcFGAH7/s+XsGubgaRos7bOP6RyQemjtlKjWhfvWOz3xjvfAdby6V 5/fFxAOMFwjNfUkDHt/wLwVeHs/M0LdiTtIutNLphfIWq/d/lC08FcM1afEgnTuhnjIRQoULorIl tQUhekskQUVM3bHah8prXmR/N4qrhjlQJYcs7yPx3U15pG9U8IM3NDQiwKYjrNjxWiMIH5A2fmuT RGkU5/92rRXzBcC3COQQv5sqjV5QMv4HG0JWei++MuW1hCykWABG3oaJgUkAx7LT8EURA+ycsKh7 4vD4JGo1vLBJx2w1XBX9Ddkg6cYPlAHFAaUfGmP4fppXo674p0VjN/C0Uqn+HiWvcKjNmE6s7mvB MpB8clwkmImH+TpU9doOUKQxkvqjjZ+bE0kbhiYzXj+5N/bH6K1VPQFFvFgb6Izl3AbuM8OJgPAs wNbdBXDHOXo9V3GMu7GxxBA4jn/Y43/6HRPLPOrrgao/2VFs2i6V1KWzfFSsLXbGEF444GshAxuv 8Lbqd7rM09SyMcrYIfli2SBsbETLRUTeg7MdLMfV4SKPipLSZX4paPphh46oiJJtTFfShrM8h8eB 0cqvd1pwpKOwPPqX/nxBAPtZzTnztEhI4oX93whVR9+S7Se4ebLFOYhjVBFANHEr34UaYU7aFj4m /vrCLCp/E0CdMjwQ+kF1EDR5sMVQ4jEQgFzRn2DNFeE56OtoY3TobtA1LExfbvzBYBZwSiiMaZYe mIk6G8PDBLBL/YbXW/5IMPA7xK/hN2zjqDJSPoS9qYQrud+8BzlxFmV2O+fKLJY/PKwxX/MoJ5e4 35qAR+1jODCBlpuzT2Be+mJWJFt2/u60t/yYehLUZy2GNC/BpQ8TAslP1wqgrD0AZ/VftWRWB9wW h9yBQAzPdldRv+EgSTCXZxDXKKmbTHNseJRctPEN0GMWW3jL4FGXyR+MRBKq5kB8CYFPghT/FK4i Vaxv6FSv1roGWhXbh8vGvqr/K0b2/3TtLdIyTx+a1L7JFTC5l4fGVp8nBd/uFy93WIXQGwmhB7Gp zpEDN/hRi/9Loc6VDJc+HzncKQmgARUf3f9vvYjjzQY3u8KU7NYgWJ7cjCKM4DbVhmNvmEscfDOj TfEZu5HhB9q62Q1+qAOcIRwUr3PrniVoXa1klAxS6StyGvNzEDFkIfZNgYJSCLw+QKC4V4jrw7Df JG9DkAzqqYpyBWIoOugs7Bp9qgPY1XlV3ioRKMh/hYHO37W9ZiC4oxkGkAC8CqfCLr3dr1M1H2Ac yYyOFCJHCkhsrizfak3lGyuCrX333tcftcCQKacOqn8msrQka1bN/iCbAB4seqMaQBnuB3206/rW RCQKJMxoK3dqD4niSi7DirPcmkgHVkxoGpwD4a0leUc7VrDVSQ0Lmg+34XW5iCN+prjX75GpgVef l0lPkD/D83mbtJcqFWpzcqiIPzWSFBPtvDFNsFhMQ2gV35HrwR0DKR5Dw32jN/UA3aJfbeAL20Yz ijsLY8wRMUqHBZrKDZyEJkYoO6519tyzQu7aR9lvkWjs2vjusxsUBRmjMmGSZLYddGuvy2Im1mOS PwNbAadcSqpKSHpb3gFSw+hXtr8KX6kikUv3GggEe9vj1B+rXH9CGpZwFP6TOs042GoTvOddGCNl TGHM2ExiqnGsAaCAm4VF3KukzqbpFCaW1lCaV/s6UjO/Mfhk7SdmouttxUZArxC47lxewGB/+eDt eWWJnWNAM9RTdtCe6+2LgA22pcTpi2uZF5LAgW40SeoCJZYBTqE5BpKde4Rrg8BKE5RIu0A6W+j3 YZoXh/8kJ3Ugu/RfovALpbR3HGBvwL3bwZREJKmyYGaTTl1XscwUGyz/tMGn8FCBJsLdAyVA2+lB UxWJdUlSlt7lcLluSuyjLexiQsIxhCZ2vjYW1pEWVZomQggeOYu3W7tmdOXWXbpL3b3QOOsiv6Kr aVfI0g1MkkWF31fr3lklvg4Q02fK/+BWmoaRUysR0YnM7jsUmKOyfFFKhd3eCQ+ohqA4EqMVKRpE t+AIq9mCVv7tASWlEOExgBOkiR3UW9XMBq7M5MX7ddOH43niuKM+/zUxjvnRRpIDol5prLMZ9fBr UqnAAZmczr7CR6XfyPdeQn5vRgXFPkMeY27H0mLB2xBHpRnG4W3Dcu/CfGbbVEMgG9kTNYp38HCO 4t0V8IILAS8yJ5scVmeAsj9I1laZ+nXv6sKmhmHnhqhVrp1bszFbPLv8BYSUalHeWhCClTnSer93 zNYOd8JA9wOiNxIXidgzs2uuwYKPQTqS08pbnVBiyZYrkBUsHebT9pW6+me3hebo80grm1INYaK9 tWzdaA59YbhbRcoYja/K+KCT+YaMlZvrK0JVHdVQxnsR9X8QkWh/CTeGuPRiM0D2divRb3LxDfpV m5hf2Tji3hwH6plPKphfEn0WT57tBCES9uTEyJN1ET94gaCm6YY/w24aGxgffb9awF9+FFrRGLMe d99JbQ19WCI6nJwBMFJlxD/1VKRXF4TDI77LCTcNb8i6+L8LPVEb1uOnu1I18cGDX0lzvrD2kdF+ HLOjeCQphucECQRzTFt+BzscLKFzZE6B1JtGx6EVT8jaoXyz9hLsnfFsAmUnssw+CwdGxe6jUTMI NDcK8P+G+aSweCHlyN64K9oDlkdiIVzM9xLK+Ahfb45WGNkaTPdyskoKWThkAjc2ncupXz4y6/XS s/U/LKA3226yDpTsPjL/3oZ5hu4NWMDVHNxKiu8sercAxdYQd86UM3+it0/q7hEmN6CB5/Qwnc9W xIQfnaryCKvhFLu3Hf3+XvBTmtvImRxqfHj3brlsFacMUXPeUNZu2TCHxLWUp+nmLRm7t57pko8g HWLKbIesFqMp9HEsvGsl/Eo18R3+QQ3ROO5Dzp+/aRXmk+jJka8n9CVCWSVJfToZotS9Uyln3ZbW OAhEVpTVbXzUbo6rOgIMgohCBYOD9d3rzBHjHnI3tEzgnZzZnMh6Q2ZdEJMNr+lduN2SLwAENdBz n2dPsFMPfv+qC3kab/MGtYuah4utJAQfiINioDtuS8aek6akpE2BkpUOqjwhq5GTEL9TvLoun2zq Usw26kPN999H/3LvlKr3CPkN+Ztvs34IkREEONJEUqJCsnukHAMCmJXOCv+JkPhVHhIIXtMAieaN kys9LMf/5LdVLtRMBNXrnjOmHA4iT5bm5l4ylcNj+eOAHPLmq1xO2oCBAa041KsPR0A/X/4f1ogS fYPvxzDEHkeTmMzu6679hmRF0e8AFzs7kkmF1ooBVC1gCG9m+5+5OsRXTRKgEGrpfdYfrMGMhlWo JleGrs2+1VQFNinj5BJA8zc1FJVh2uePXh8+2xiqRJQkxu8eXkt1xOc49t0nP2Hyiw+Ez4F4umsy L8yYEWEsayXgMCvpufM0dtaKMgKgDLs9Njnmeh5KfaZSVsjcpTRYaCBMpKDTQJZ1N+vERWhs4dom dkLsrSacPwfvchMRDK3YzCURHvf40VngRgKjRi6UgVJoWFP385PrjBEtLarbCIHkch3sW/W1e5KD jp3FVXzcghgBYWPZYHSbcY1/SImnhw/bEmwFXTcAlmg9TbcWbLmxjKZDDQ1Mjih7pH1Sg8cOrY98 amGAw1yeRtQt4H+twmdbXuMwhfGCMtTK6Hylb4C1nB4V6MokBYhT9KAmAYdB0RihX7jY54g01v91 S47xpDPygGBt8lC8qODz8h3qMDjJHq6bqkqtQSIJ6HtBuF2aHRJcWD/AEGdtwc34Y1eQ4VuF2ir1 /4AYJZ1AI2ojRVel0AvgMyw7fN3ZXVoyGZ0Kzz2w0qINhPvpG1ibI4ulElnSngzK4S2irsiOGzK4 DscbatywJUfgsP7gj89FkOIEKp+stC742uXDJczZs6njfSCxLsq98evZIjfJadi1lfxf6PcmRz45 07MsvxnpkXNQztliaoaurcsyjhUeLeKmpCEyMCnOyh9mVwJ0Ym6XKOK6jQp7Gwv43GyAIqx+T3f3 x1vyFYtx0Ra29uWaltpeLLkigv4ol5ikuxIdzvcchM6eufLFy3IgdN9FOrCkUvC68rzFc597FzXb ODUwroV5cAEQyuxtdmjqo1GJwqTJ9R0f6yjP/mUAI52GAcnOHFu9TiOyKtKuhNjByuEIwHKnlE2B E/quFr5SSaxPURWtmHEW/3ePkow0cTGiRcpUBvGAqIlVRVdwqWn3HWGjDcL+1U7tb7Ly91WobxNN 8lcQfLBy3Sy2uMPzZ1X9s/bbVFA/ZAFlX9KjUSmxOgUHL5MPNnQ+jMFUecCUDtbcpiGHSuOcyxjq GqKpSyoac7jFV5gx0G7y4YTyGfhxIbZUht/0ooDAxHX0dUP8ba2XrI7YdE7b9u+HPNjP3hV3kY3m cYGkJCMEnqCwv+bzNKd1R1P3T3RTu41fYimwAtuGU/PR2TOkLJpgvXNOaohdDe4nuiprMk85s+8x cnx20fiCdlJz7qp2mLHH2BbvslY+Z+GBtHoZrJI/3lI2kdIsGEnPFd6cziV1EoyIFy5R3Cj65yxu Vb39GulT612eJKlb8Egx2Jcs9GaE46B3CujxeQNna3I10fSSzzF83jY8lVcYsXmfUnwMkwrA72al ZAL8feURABA3E8SnLBmTV6JPhI1lxpwlRzAXJtAMkeDgalkSpQb/utfxJCSTFfP6ZL+J4ZE4Y+SA eIdqlCpoN872rrWj1xpGA0TjR2FiteLRzoJ6iAoqJZU/9CVCqWOUrkXq1Y6oJkOSd/GjXLlb1Vee cKjhOxPNIE1Rv/Tsu0t7VWUOtWFEz3tLWhk71Uw0MnYS2coYADNkFFo6oBFZN02YczAMeP37NkgK EBujWtc25djZ2+6UheOX/dtl4y4/T8bIOYD1WQXTQ4SPBNKrYu00qizF6rkHlKK6TiiVGCUx+JpI tvhHxMqUzr5dp42iP4Nu/plUTJmSqjjzCwrvNU2vkfkA3qSZvHjzh4eC9Ye7ZMdvZBx4Klqybut0 14gukAFh5vdtg2uN9gP0dmiu9oh4PVB5BVI1EyW3JQ2mZrn4y49e3No2R7CDlggeM+UbSQalFpqA ZkcBDocyJvUi54qCUrXt3FrCW1sohJtxujAereE51MjGa2u/aXG5gEuKsZ0ZmqTl3y3yV6kGDNDJ 7yaz9mDiOrKG3er7hcMnGPFV4RPEljVZRJHZmpWvGan8Chx8l7vlFL26l8g91pA4d14B7Ts81fXT fgUS+PkebqqR+IxmDNXWdqniSFNJC/WK4McpBMJeshohk7EB1YfmfSMmnhzqPvz3L8RDgRJzKC7U Uatntfx5xXf83ba/dzZFZOVnvRzEVN42J9oCDVYR1xpUrGoR/PUJgz01Q5H4Cel9AEmT06VzTt4H jNbU+yQ0YZo70n3bNk9WNC7u9FarbFKUV3/EuOHB/1JxeCM8x1FXp/AZK2yHvs8hlQZPuR346Ujd dFX2y1FsH7FkIo1ursbnMeCgGWADXj0heaa1P++0OGSG0QypzR4+sByA23c3attfDeEKdzYWajPl WW/vc5KJei4GTiMFd5wY72ALGBJV9bX8GDQ8BEV2cTyW+vEt817D80Ehbr+GDfWOHpqgBvZGRgj/ Eo7Dn/+gy65Yd0frADJStWi8ZRWTYFMtot6xzwV+QiYcj9e1/X1LeQ1vHBDQTTgbn1CSDIhV2SHi 1k0MXJZWaThdO1tLLJNPQcKgRaSWgHaWo6G8Z5GhtgsJu9NIlGTffzTEL6j9UG5qK6umMcH1m7ir mG409fT/fiHlHDtf45gz1LjXu20SZZ7Jw69xIphzjo5L8bhi9X9HZkmZ4JoQELWayT4oJmgT0zdN HHDDSLJR9o5AF1EdE1RbPKj+FDUOoSa3hs+ljTtqQHdjPD2M+AlzyCmIGy9shKQ+SMCy4ASjIxBN BGvmnP3iWjy2kttgl52IgQs/9149HS8dzPgtyb4r+zXpGzVLOLYJTWzRrmt2F0loshZc/rTSLVpz LWcp+60mAwjDF6rqB64j4Kpf0VQOfSVsvxK23dRFsC2SaBJ8bbr5l0uUhLadw7GAM6Rz1LXgmJtD EVEiYeq2aqgN944SdaZ6kpG2VL8/REnGg7F8biP5BxhfCH47nmsnqPmMIPyrHmtpHNTrJ79J7op+ HFIqo50Igpjj8Oens6b8DSkmv+5zrAdMvbogA/eFXEyloQuMjh7B7pvH+boC6puEtGWtipfPAoeK f4pMK53rmWbln15vxBJJFpH8UbOyTGMpD9DpCGjjKNJm6G4ix7kDfTCCcS2yp/1fi9X7QrmudEFb R2sRAcyrLtGUrnP6nOlBtVGvut8biyZ+8AMZlEQI+TaEh2ZpyJ72Q+LrPuGG3c9SQzIaZT0ZIXSr EHX10/0UpoiQixDoudtUyVxhj5AHYBRuO12vHq6OE0R83KrzkvyZ5TV97CEyhKXljh2fTZ9Bs9ZY 7I8kZu60r85fhzZcKoNZHOcPPw30uv2EurU6ilxEd1FY6cEA3qtQJgjFd9X34vgsXMvXVF6iXNb4 Qywm4NdcSalsWZ0owrIQh+0/gVu5/AhTEM0rk+/rmXop+N+5ZNRFda+XGODFlUx7j3tXl5RKS00M yA3nio128kvLV3rhoVdSKcNs8+DjSuNvttTIwSbDlMkFBLLtgoNJzDWczw/yeD3pAnWR4bDOPhHT BZDdR5BGmavuQm8FYR70OzX0LsTiNbPgVlOSH7ijvKAnRd2O5RRWYDnUw5H97EV+JIqQ70iZA55m H/+k1dg939k7sN8t4ammWXFyo4cX+8DjjaCMC8BkUWttL5ExeDjpSzXAYMfIr32mfMtcrLB2UfJX WFM+3CPKRZxHqfVGV0X+Jmfyydc/T/9GCJuDV56QzDI5hmGlDclLbnjrkeIuoIQGVq0WhNUgerfq d5xFxNA2dJjhLkbA3SEFKo7R3ROg5QuZegpskTiAVYs6RA54unkQhrbJFZ+grsA0DI0eqpF18jL+ DOXQMnwUx8lHMl68T+fePgTMM9+voJjCXKv2BSRHu9lgiDSGa9AnwX7alVrxU62SB9ekpTQGrp1e niK1IaE16fNp7Z1J90PhF/WUR6+ZcSNB8i0gLce+oCBvt1rvaK26a2ZpESJaoO0QZ60kzoLNRvzz 1bNN6kUOFDMnJX8XT0IaEOolXyivopvOE8TdiTMOSI7b6Y64+5dd8Cnl5ecYMgjReBIIWRqvfxjm jGP7iwGYibm4iZ7YsPiKCvhBpusYbVwBrd9VW/mDUyUCwpPUTkM77ImYqRBEflKq1gYKBcgNpWvt UutSP/WyJz9tWIyYkMdvk+8uP91JCg0S8B2DKzPi2KnBtiVOVhMH1ovcl/qQHm0OiL+9jw1K51qc ikcxrRRQSlnAhQPckOZ1YsVPTXT5axylr3PcqDFjzydk1x3et5bNcveVT/eqhf1nVvnLKbjBfW82 LC9xBt/h1w0wkfrcERBUWUGR3CVR7FGZOZeB12jiRsbzsXsSmNcfdxGd3G4DrYiUYLm3y43Ycx1g k9i0l0NwwCR1a+te/xVGqh9soBeK4w6/kDPQf31TqUT9LvJOAnVDOBQ/ESuS09qshelzC8oDSUXm BnthkFpNcmEvAssr0H0kudLy1MgkvlhcloHacrPBXi7hXARlsodpP8LfphN0Kl7eUP00WYLcAyf7 RnNJv2h0EeFtnuUcafxsPyCGwbBzZmDd9CCtzIkRUckr6+i0vlIzNLO2sjxGDOhlQSCCQL0nsTA0 95UxC1M9Vhos8B/4/PJyIQNQDTDvTgOn7vigaSB7LLkjVMNiTFr1rGM6504hdHlMk0FrO5yNtkB4 fuKLQ1aeXnw0lEiCsRHkxKcxCJDFKSOQZtVbGrt3DRWqOr0AIgCpfDKn3PlJcR7UDmgCY8V4t3JM 9aajrLm9opy9qXM7pwXCDxAZnDxHX9NPhpojyU8iRbxUxXSjr5KEwadAUssNiwEt3/Acf7XH0eq3 qUgNVjwu6llQbLarHuUlVXRZrPZAQbL5jmJFPhDAUcvtonSf6frvm1Adeq/v9u3Jql78Qld16tX4 /vgfmPS/1qkdcKbCpWbc5PzrcdjN/L1aLKIynB7CsRvtIvUFbzRQ+wxMxTzjljwxrew5vBzkvXvF v0Bt/jxrsAuz9XEj0KciDaDr70M4S9b2sC5f7HVd/82bQ1HGX15n3dMPdMk2z97Ryjd3EC0ZkI8X 6mqlV3PV1MGt/k17LW/l+sn4pWe1C8+Dj2um57XNjElp4fjCumHKTqDKE+uPsGWR38OiyjqTdLge SzS1/JRQIlWq7S4dSdCDVMT7hTdwLQRSvim3z/y9Qt9Trn3Sh4DG3ZmgyPkZUoQkH4OJbySiTzBW Su9aJveU184sVYPAhmmYofmbNWt2dvmRq/y7tbbtyEDbdVVzeagAfUZMUWszxXrMKED6lY+OFSyc bxTvdOXYrO+EmhApTYd4CNy3UxPpbVcvqtZgnXJOccfjwVUi8H4MMDVUlv2x1SW8pFGohwusZENi Ke4ALQg0m27AhXCLVlh79Ge8VBsMQLAK3u/2a1jOybW6cXMQ/6bv76pCOsFOTfZKB1RMTzhzfv0a vgdxiLRK4MWIBjYqIFoX68ESxavhR8OZ0ETHoIDpPeOQmx9ww5I3or+KRQBVlRs2MSEyNHIEVX8z mqJfcbn6q6Vc1AqYyaBmmLYuOnxaC4fcBuOwLlZ/1iDq7wl7+OtNh49qPani4c7juV11Ojqd4IbG bfY47S8WmYlgtS4xwzXZ1oseIDHiFUahxGxoMDV3+0NMlM8O7WRy3w+wCwtkG+8O0lusXuOOnNII d2cHx7PJeBcRKd8XBi6xNGBvnos4sEQ91zZDVH78vFlFHBmXP54zMgA6yPFvd/K5bywma0BQt3Rx QkKMseQvUHnuI+FNcViAepoLtnDtnhOpcPAaM8X2y9OYZo/1M+FR4C7ohLpdQoHFJHkKKRFTmMeP Tzkw30NHbdpLTz+8XHwB3xOnB2mkPO1aVT86anNGt6csJ+EDaAZZ+dGtVvZeQ2ChTi1qm6izjibb 9m42q0Bn4pAPP6HiBjzVeTkUIjhZpmMhWyBPTzn/XeUr+A7DnVOCJzZY9UhRsuk+i/JKvhFL5FyV Bckrr5cXIPM8i6l+720T0v+ByogmSCkjkJIbVzICx7MCpwt/VsMypOqw+qv4TRUGjRH3D14BYI4f b+XQx+F358cA+a57r28Re9USKSAh8YweBV9zpY6a1RuXAWP6M3+YpjNKoXVMWvu7K7mSqzJ4cV02 J7GqFrX3637GsVv5lfNQ5OUv7TPQJtGVgWP69Qiq4RBoTZh/jUfZIIIFwNFXMIqrMPFtLTpYfymE /2Ok5qpw/NorvgS4bGm21sF1hqQ4wU1Nnw2qjeepgbGssRz9IQb92a53vyjvuRmV/jPvHSA4549+ gezYVVAbncKDOHsR2HoZBZepd9bUhZhIsNDFT/AFJH/GMc3ZlduG4KDXW4JEOk5wYvVB3Lku8WIS Qh7UsGqLKvmTDhDynDQHjANRSXPL43E/NiBtRsPjkG4GvVorsqQq+Wg6UZjWr6EPkPTDiJ5LhyLY 2V1y5aj4WepUbYV3dKRm5lh//wCQNsh3mXSp3nX0unfmWnnoZxmVS2dCLwf90awds1DbeP45JXJc /wF9mFe768H4kNkH1iVY/U6q8Z5y5F+r/C5xPp5+l5clhqI4b9ukfg+CKkuOdyBWNG00j8A5fl6K eyX8VY0e+8dZhCA97p/7BCqxHh43VRu4emn32ifFhkt99gDO4EY2CGc/xMP+IHQEoYB7acCiaiP3 JhHxqDNX3RBqYporY/+FHn1yj7mp+tTf/ROdRAADsnTZUhd4ducQhUnoRQtDM6C5SVN/NxEEa82c iAlgDZy3HhiqbsBTVaWxVFUVn3R0mdlkMYc+jQEJxI2QQUYKKPawYDEmUvrcpYNC7RMUjUVF0g6n HNQmoOO+WVftnZfy8pHPYHLQAerQMOFMRJB9p2+BGWtmPyBgrRVotIAKfTgzty4VFtfR3DoVP9gs 3ACIlLwIA1ae3ntQpEKYjeMpR7uMMwsaT5mMEwQ4IXj9Bj79/8va/l8HjiuoWZoot52gEWY2sQWy ZJEyaR1s1T1mb0zZqKh5PaXu39J5h3+ZZBXYpezjEMJoV07sFmOJgK2SSVVKcmrJal8jw60Bcpoj SaOmHWHo3E7gptzP4zyAdebLx3p0SXlgfnw7gvwUjuMO3SxUHKRvynXcMp9aTfJYKVqZByf6ioX/ n89m6uWIDpiecTME5rZomNHIGeoChTPxnwUYQsgKuzU2rohucmnQMdurjTxtdC/I3iKNsKMVamWG j7buNCvi7LlmxsWo+p/BkQADh1+AK2YpL9W0F8+6/EjS3rQSIi9ml2AkbacIx4HLR/VgRvSefm+0 DRrtcLNu6x1zz32Tyt73uj6XfyuV4zKQYo2SUhncAfqlGZCuj3wUMiySBNsK5BVIttY4FeigIg2y jk04B+cmhg2GMwMePnxHhDsYGXmlroyFWvQs351Qa6QoErf5uMMc+JZ2fMGOWO/lukhw7oIE0sVB TssXfkI7v3WohE0jft0WnxcsBtL/s7VhU0Oc6yE5772e1p2zEF93UHFI+zeoKfTMnIMw4haisPBI tODuBC9cj6Aiaxv0bmp7T/Q39S9eoDnlqPGOHeKEJfCoy2yEpcZ6x0F+jjQYV5/vav9x6M51oXLB Pzm5ppEUsWvVxasLTstqE0Zx7QNsz4vT+j3i+AQdyvEfiS5HOvHgGTmkJv4AsZL6jdrb8kooMFWT 1MOGEO6hAt3lCUHXo3SgreICtUtKdiAgfsuJ6ZisgenD2MC4gpJyTUWFauGIjFGVVoNjT/vPz6l+ ZovGiSMFZ4OMBSVjz7b2WWgR02ndKNPWCUEOWddZMr43o/yyv181qhBFb0K9q4vbi0XVJGNngAZ2 5kL4ais/DdBY4EY86SzeQvhVy70HiHgaUmRIbLEhjBmWrwxhBtrjmIcDYlKZMfngKMzQeymarmeI 8f6EgDbMiBR/1V86cmmXK3tambtMDcllp/ckJUr5lC9bRn9eDKnLpL1KPRZNGDFp/PtzTmvOWax5 lfj+sClOVv384EtFYtnSOEBwg2eGpFgZFOcYC47KqAFH8wsPgIPmX283NeooSHkwj8f+kSf9hXKF jJcE4c0Zh8dAK2ixTf8cwmIyEpA66YcQgmcO5zbn8bxVsi0vn0r+wNS+DQ+nvEGLWWyeP38zyyHu oTXZuYb01ViXtyMMAWV8uHKIApJHdPK5JdEROL9ogfnqv+IVcoywAOxPw79jIRX9rir806R7wocG JHjyeG3OjDe3NagmWBWEAelmtXp+witAAlBTtYUa3kt58LbY2CdEwFTs9V/ZBXl+sr980WyI45Z4 4YIBlaJSVZaART1E6/J9CeUGOKPTMXfHaXvIOADORfJnmLFrKS35p6FrlfNWkPTE7NHu9S3sd696 Viw/f7y38qQp70vQmaYSfKFIqehSLLuJnZACcL9wtzB4BNj2vnEenum5sDtViE9mWTmN/B/c5utn 9EKbkwgnEhYANKBiG7LdvzHOLkcAdvCcEQy6WcZpma1R/T/0gkjHYjjUl0MdzVzOlNGYFH/16S+V +l4cFPC4aznB5HmQAWHay5l5dISw5P6KqvGtvXdRwBuN/0f6f0AwwPBbIjWGF9jKh9nZau6ZrxBx zmW3FEgl8sBAB2HrUWPGizxssba1ugHm3+UaH4rfO22s1gjAW11sPFhyluyIgF17BgHh+fSHmjtb 5JUyPa6N2nZhcAdHuYm3Mz2tDphOQPacuQj/TsLcCBwS1/jpblt+VJaXzPS0497rF7ErwYjJXe70 +Iqf0Z9I/tRg1Ep2/qq7C8nIjwN1lCm8mZI2cwHLbB+WdqILn19utqQHxgOLwj9HnYzf24fpWs+a Ublja8W6z0u3UQ6PCtSexi5X40rSON1p2ukMJ3+6nptqjDmX7ip0SIv3a0vZHx49RFKdw6amlyQ1 WHKDRcPN+h6CJbDYrhRo344fTu4Btc++OzDZFrD8GzULtciQfAK7Phr2PpgILmsWU1JSr4tUsWJN xZoz79J7zv+ommpZoIBfUi/GkRT9rJJ5Y6SslgGS8Zc8rAJUs0J38yNHwiOvHWeSXhf7jAqPz3Nw +5XEKfFKXwgtRGWrgXBpzad2LoqJdhLDXKwqDQSXMF1uwcpkAEe0BRd0GI9XCoyoIBgxN/OoFZGv IYuc2MHLs37CMJjDGsVEgy8HbaV3oT5IH+cZrbqHh9KLosurX2FuwGEjUyZD+5jWYDIrCi/uI8/O SbTMYYWorfmrFnFAd5UUo5dobbvuZT5xRFW7TUnMcO8zKPlRdT0ZDGSut6nPBjpzRgz4prc/e1g7 Qk36acSHaTmnzF72huOAsqYcFLklD6Q5ebofz+1navGAsOpfSOyvDamx1uRWediZ132xs0sD4rnh STzgdXpUZtL1tcNJ7vYwEGr385k2h8snG4RZOh3UrI8jAGxnLe0BrTVZFM6hXONaLGapeFST7aLk lQ0jSJ0VjSW5zIe6HwVRw9wZ2o6ETaStq/gzKhxVFa6/DJFFwN/LmU3aleWqFb8y2kVzZkBaSTyX 4GmoesKOfPRbaMVZm42irJoeKnA/4p5G45Bxo88w2TswgEIGmaJ0J0YWujdzUrKzZd+1QPgjXeUr KGdRMCl2AskNTiNEWNY81Zl8wZiL7Oyc9Q/B8PFI8m0wIxIXcFUzufQUo1ArWxgQTLvgGC2krtA+ 8a6jBTH0jr7XDzQAejuDffhMMuLhCQNkrDN3TrseDpxcovyM7dtKLXtPqjMc1xlGNkSQ/SIRcNmD hgAebhITxmfWfbdEk9JcxIR+BJx6RQHYUTTrNfVqv1FjquULS/+nTSvHwjf3MACVbAwfd+mV6dgF sEDjOwwHlCepOsmeWsG7bcrZHtmPnOY9ddJkpz/ZlQKqNEPlZmrQg0gnpPk2LcB7GITKG4omtFPT 4FTuktjdfP4lCYLdkDcMAX1gdqyrqxbMLnKZRTN9RiWzIMsQiECKRp84wO4UyaFtDp66ItOi1fTq TVypuDQhLMLTQo8iBAJcQJ6iYTFY4+IlVilKWPqlfUfRnU26SjbBohwuXMkzm7nC6MvCrddZ+Vhr I8esKh6skT16vqUvh6L9DOmorHzIiZ3g8eoo151G8aA2X6B8vTu/cp2f54y7s+JDD8mnc+b5JT7G gRQqwA1wHRrjiz8Re2bQLNsOyonMjvc5My8ZLImTrmun1l1i+wq21qJmJsYQstaLZDkBA97mfcm3 nLaeER29u74yzSy1MIlaCb6P00A+9ryFnS+MSuNwd1lHbyVGu70FjCeNbmJvUHfE+qFrauBriduy uHPetJrSy5yyzSxE8yzF3B5NTsn5vvd1JozlcB2zD5tVcmzzZ0xu12jwJDMEKIp108HwuJmA3ZHg IrZTpZOKVF6ON1JA1tLUWu2H+NqYiAKJfOzIvCFCZ8+CY0tVTAJrAtc9WQAg0uLt+C5RxgTTJZ8Y KMwbmhKprOn71xsRvVS9lpB9e+6CZne/J6wfQqNquLKqS4R3NA4c66xT0yQD9Hf8qQVO2mepnmhC UdYpfB+yB7VYikC61kAs7SlhWY27KQSqJEZPtbXrVIXzXAuJl69hnPsJ6bOhbKaF09ETurLhHbQN hf0QsG8rrOOkrTBQZa+2HVSOJ2pfLYYrtjaob++xuM3rFtqK0QUZ8D5/8/2WhueDSbVtmV4c2ZZP PrWNwoaKy8NiVectIHikGMEzeOY6J8gqO/lsIHqpsSRy1b8OkWaJhrWlDAtd6DiatPbqs0KTfwjw ylGjuLQlM6f71AdV8wtFHcJr6Oh4zKBiCkPT+y9fJJfDWOxmEcel9pKkpTE+zRprkeSpuzVhUFyE o0+XdiE/1+SnhwOaFLbU9RFeK6a4TLbTiXQjA6Bs8tydZyc5gEE90FxYm/39dmYZXFm6A2xgJdHv rSg0x0Nu3Dra+YaokKeTnzVTrYJHdEEW0VZnbKaoKSKBBWgrzHGQCqpllpqVsjWwMduln/o7kt4r l6eDAo/t59BgQGtkX2Er3l+tXawVdSFKPKs2C9D9/lQrHPa9qwRGV88LpvPg157YKLJWmAwKch9B Ir/Vi5td/28mACftDIlERjPcXJWzkphBSjw1t9kU2gO8scHaUoJ1FmfnnWxdjXsilfvRzRt/pWaW dAgue+/F7RVFRn115SOgBVF854qeBVqXJwUCx5rh5RvT6qY73AYsL5kDKmWH3idDem97mNT7wKXr RU+bTmT+N0J5UzdqCaen7elFVuLuK0cYgfkjiDrjttG482gweDe9poRVFYhwhzbd/Z8KbigNUXny E70CzG7gZAIjDmEUeHXFcr8tCyLh9FdIUf5mxpu3FbLrGuHPwr55U+tHeMBwBdjgtHLZVA6p5Lg2 wFYJ0n3lmjmVGTjV1lwRXjPO6WvpiESBRuFiKl1k5fIUM6KjsPoeNAL+RRaQNudl1uFDdt5ycgii 7/iafbU7c1gf3lU76gbKO9bribpP2NM8wqKYEne+0TRoTcvKIrGbNBf5dorx9S6BtJSpJklzQD/K WdLZ8NawpTiKTQ4C5rzKKV9HN4XKontaHv8I+McTRBSUG+57dbakTkjgYgjjWEq+Z8ZtL3UIxwCd SVYU7qcWKl1lIG9o/hHo6toWauxJUbUYKG5oCOIlqKVgktl+F89U8c1EMOILPnQte9aNe57GCck9 P9q3wrS6gT0oDZKzxpRxeHO2FrKHsX1RxzbQ1eSkKDZBQxoioEhWBcX9jCRi+B5/SFSC5h64PHs+ rtI4ICrXvuAFkV4rKbJ5Y5pKdCgiIOCEU6IejSKr3Y/R5azsUX7vApfgGBgER8qTKAuJMF6bmL/S 4RXEjmf2bvEq8FHb/4rMau45GCWz+K8mPOPX7wamynGV+GxJIt9JAkeP8b42Pm82IOTsnXXqstw8 iWCkcqtbWi/YRdfC7skPMLsYvvORfwrAuhmzxIA+fwr1menRedpzdI1jCa+mngfvGnHU0qwqLm7M I1GfvwHPjsFoVNV7kSUhSLPwQFmIZ5bk2rNnQ4nxWx5Vaqu5zNyrSIdsLtfgcqfbEXiTiwfJbsmY 63/mqFRW/nzcyRoh8M0FB8wO1oV9uy5VgUz4eKRYdPa32e9puUQJkenPTYPAZLRAOnV4rvQ+c4E3 hAOdGSY3qhRALtvPBNGYp42cwEiA5S0DHRP5pvJ7P2iXnm98FkDtdAWmV725tUybn7GZ4kxslONR he590ErT2jcVvmPrGWYRFAZwiCe/0dHwT5S0Zwd8a5J1KE9e22vKsYqeuM5+Y9BtWv4tZ4TnqMls 0joOV9NBMYzmL7lkZ3YX//g3e8Dv0NCwKwn9TEY1b3sOMj1CoGS2V5+jAJuQwtbAf3AoGK+EnC0Q LaPc2zA2G4G4qCgpE7glH/pCjn47PM/dw/IO80D3siE6K9LQjauc0R5UOV754fwT0o4Sbl9gWwUJ u3NsDkf7CF/nQWhPJNn84sA4Mfq2mmkZVJBRNHdm2rYha1WOUTUI6lnl1d4S/xBCyD64wLMe2Uvc JspAxIItBcykgTVKSPB4uMJbNxixfNHaiU0Q7po3l0Poy5igBNMk7If4Egyi2C7Mr6lG8Zwhol7T wedAJL/uWAJ8+ibN28uv0a4+juXUp9Kl7dX8K3jAn2qSARbZfBYaB/SKylEgjB7B/DpngoJ3JEKw Gjpkw+qDGgluuiH4h5IwKUD3GB2W7lwd3KvQUX6Y0Ep+9b8wJ+17kBD4RFyMRoABCfGRL0EzOrZu ZCpCmFweG4/HP8LaWQd4EXkeSwq/2lJty0T5OTy0JQJa3K0cZ8JthKUDdbmyJn2B345XGg23XoM/ vKjxIEQIDI0Wgs1Nhs2YH6AayHwH1MqsE/DkKkm5yZFoDE+HUQdF++u/4euC+nKa0W4JeiuaN8RO R9rZkkIK430m2OGkHsT5LOm1iQQJTbL8hqogDXnsP+3l0ETAIPH+u/5BKVBQeNU7nX50ZOmKl3se 0vvjXl4iq2/UkZIvt+CPB6F4NupkhaA8XoUdkAB1PuK9gJHT+DYlo1F4QtR/eSjturwvF8W2fVam 7zPv5J3zN0E7+nkgfxF6lp7/syzJBsSYghrrYcab9t/cpdarygz8Z/4+m/nDCW68lsLhUxhLTRY3 QDWjOLbnqtylmWy4ZwdLK6aCrybGpbkF142Qa9YmG6LQeAxX080KiVdiDUoIzedveSfjuNyU3jwu QVUZ+1RBGgjgBljj0zSweZE1sPlnfthscXihbcQkCiIgHQi73EruBdE9oGSNUFW6p+6qwYGgygv+ 55s4HaL+d3vkXOJZGbYLNM/FJcid0qzY2jr6MtnlgXy1zZ11//AD5lR/3XMW9iRBKLKmwP91jiKu ngfqUxks5+14clO6PORDspu1FKay4Op00n3Mba0gr8QUmpG1LXIuMgnPIiWRr3Wp/bnGgfYc1moH 7vYRNHYZfIKOM6UZThjoyVGct19H3JXBzKAoh5iVBFlXgPOsRpXPP+Zh53j+T5H7jKY2Xo6rGQYc dai5svb3GV90EIGT03i0efGgTfHEMvxJFZZMlXeNiIEFhP8zGT8nnissjggaQVSFwf6Um/ehhRiI yeXVLj3L7i2HlWpG3SOWNB4F32SQTfj1aoczJEQxah51FW92/aI0sU3A+6QadwIj4uFuaq///TnK pDy3PLVNuviQvSex9rv3ZO0Xe62v9ce+VUnHgZyCraoIc9EJyT8vV52YrehcSp6Ae83UgeKDukOr Z6WQR97GJ66zvehqigJSuaGQHvvMMiN4L3uM2N0k73wJwdWwBzJfL6AKFoyhqD56lErURMkNCxIw rAh9TzKdzJ7+zlgDF5M0FFJuhhP1dXwDHubFUPchq8/AO4i6R14Lf14SERWwRVTsozAfj0AWNxiT X/ByZbNs2RcIQpq3GIXD6LNowq9Ccllm+S1tR9E23EyUTZXfTwd6nUmsjsp3MHD3eE8I+WZpW868 pwU2WfPwWcAw2wrnBHQPkKN6gkfzZ7MlDJjb0iRJMqdd2aAhi58uSmVvbv0vMxtEcpceqfmofR/Z 5/Ugrs8w39LIILUndOCLB5zLd7qaqi0Teg9UZH1ZF7L2gXl1F8L/N9Llf3rNdwlPtjIcA4oAJ4Tw RANUQU3snwcfjEmEaLpJkIi0Wy/48jvZmV6EgVT0aOTvv616ueR2RHjmSxnrdakzz0pLpKhYcEWr VVWHlliGsA+v/6MAjLpLHtxsF3S+JBztWaGP/1dE1ZrKcvBzy31iIzZLc6aZ+dibygOfyd70VEKB We0q/gXCn/+jegFkU5OGZiAczI9lv1fxGchw8UabHgPHuGlqeEvflq/I/xkth2vqGAPzyxsUfHrP 1txSBPalibisHYfiN/8dJ/uTysFp1UA5wQphxCfEIddDrz3gFM+cyvbGu2rzz9a+DcntZL9uY3Od dH3HSUbbk3mfHxQK176tZs1iL/s7G7rrv3WvLSyX1muqmAT+aAwMgw4to+nnrgc0mJFQVF8nnjff 0Sa8FjZciTaqga6n5VBlzERbG+o4YaqtaIrwZGvd5S42ZPkPVb9QK27Nl4m3UHcDxU6Gh7tzCHI3 V0S/CSQ8ecBgIfyN8gu2JgNd1rjKq5yLiUFf1G1Sc+hDDQj2AyMuQHR8FB2rdnwMreo5576ckgSU fXR+L8+fhqX7WIO2e2BF3BpthIlmSbLOI88ajhTX7dVgJL3upNU6vYk3wm+3qM+CC5A4CuQ55ylY DN1FwK/AiyuwgArpujF57/3YprWws6vAgnAxe1VQu59Unq7nApIj9rqYauN7yVrY325SBDnlUki+ 6E1jcHfy8kBylNI30h1o51Vpa+q3PdEfOPuH9Zn1LY049JXAVXsY/YZcBBh5/Ofi4lFGhDogcaWN kNLHcpXo7puwbLXEnnuJZbJaLlP6znXq2vZ2nB+QUaUSHMRtmSSHboH7udIudkIVX1ZTa4S+zN5l FIWDdwoHDmNXcWJHOljta8lLQIJOQ5lP9LV/+9+D6ET4bz6pHs7u0o7862bJ8CP5U3Te4uZXQfWg S4i+d713rMvVeZ0sg4pLfI1CT6raGKfFlTkhhcoSq5Rc46vx8V0Es4xwokP0lPIWZAc4Nj3cqf0n AArsGjP154WkijhHn/Eo2xGIRE6CrL1v0EYe0t0Laq4o1KvAlswIl0AIsdN2MTOmWHX/Gws/ibO8 NC5O2uewlvVCZmFTcJTiGi9BkLQYeQ+zfnqTxx/A17mfg2iDjQVlyWJcKF3RP3woxlM+v5ny0kxW Usbu35vgr9tL/cpRJGtdn5qlWS4f800szS9EV6HZA7bZ2n+s6lfUqXyJ21D0m8ZWp9AQEuU702UM zBcqcBh8wVOJwi6kFJW92G7Q9DKJAcv2lobApgLV7SISHr/NQJ8iMxHh0g0rm4tY56QbHgP5HBiy DcvSXJS1M34RzIJ8CMLlFLJh/tEbbK5mvBMY2a37GZs90vbmvuq2mfIQTD2O3htj9phqsWLomKD8 D+ZH/QpQ4lmglturKbuU2iiJaVIgn8AdFXK91/PZwjoqV/05lJrgmtnGZZV6cpGVsek73EfeosTF maR8BFzOz2JQ/V26oEOML/DMa+hUt0poA0Jjy2gtzmoX/WY7Tgpin1vO81nX9KXw+HAulRzWVInx +C3hghW/4et05wJFlz0WIzSP45OnRLwsJ0Jg03kgLpte2s3dJkgrfzDfehNhCzBD/ehpOJTe6Iae 3af1/wu5EhZNdks9fEppzZBxbEFA41fSLCp6cAjeNtpspoOzflzJVDehM/QY0zS2dJPNX3ikiN8W wTcryqVl7A2oxFIbmyJLngeyiQ3xEkRc8or8xykgYq4T0BntX68smm113P56FyouR/XQAhTfS5cm 2luDRcWOUO1Hcs0UEvTT6P3WG/mZ8sA6eoYYaAjs4SndJnX2yarjzKbXf46EAqxJL1PK3YJI4Rc+ 7O503HppVgSQBHgZwhDMXJ+4R1l9Z2eWhpkuQCkd2xf0RMH9PP3uScCfenqFCeFKaZtgp+1zPIcb 4vDOFpOlMX2XhsO7Lyj6N7NotM6WQyB547i0pIlAYPHNAhtPsApLOcU7a2KWkLSdjk+SpyoOrUqD /xDI4hOk8Hqd0YsQuA1beqXQk7Yt+WPeSOkuWJCjSM3z9Tv/Q3lVQKi2D/I6aWF7pghl1/o9dRFd XVwtAU2s5Rf/gkwMfyKUN+deYyfsTPtfZWWhgkb8Qus4E5Lr0TPKqh8tSzNbqM2KQfnuYsQNdG7s 7xR/+YykXVVoynwBepRoiFqdjqPeWVjxRwh98mXXmsDycJKhZbMe/obxVcoVwFjKvVVAqDrIXXBi uplJNdLDpYNbwfNg8ZOpa583Mfv86tElrVPVvni1egA+aW1rnXzf3lm9LMB4FtM0Mhp0BfEshndo 8miHUSKyr2qVgWMLPkEQQrOObI5kH1t1qac4YtndBrOgSZah6pqnHDLQhfdI29Q/AqS9q4BBZDhW nPcDfUmnqdyP/rzgkA+HKPIxeGMzsLFuFUJQW3rRWKuXz3SZd4hZMsHgZoWPIV1ZwVZAcEQyjEOt ZdBovJTTuqGnz2zyaW3BpgvDb9HpJ6Q1LqVf8OYCxex3OL+bwEX8RcuyNRA9mpObCez0kOOrYouW 38eDQjLk6cMj9ps4SKJezn29kXr4jK19E/YF5t+LtD/W4P1zyRQygyv/exd9pCGKsFH5fUIGZ35W 8BWWgyMVXOsoAyLPAq68mioDKk5fAMTtUxQjjAmWbbABYc6czQ3u5nbEsX/FRsPKXItQolfODWev BfDxZ92xhFGKWJIhlesAqvy4Jycj0pBUWNgYuBjiw26U3NXbsl4mijbciyjM3GghJp9qUiOcUiXX iZtH10gMECJ9cM1WCLmUCzaiJJfLfSqRFT5k05MGlL8B5dhqybTxpf7ZMh2ybDXu4ohS4Gh39WrT kpjC8e10o3TClOhyKv9qqX5r2VO8634wvKfDjCyFKDNOxckqJG3Bzd3WxKESinhuI+l6kIQ2/ovq vA3e2R5GIDeTu0pE/vNV6xoHuuw8A3zt1rFetxI74JEWFEeDqV4+0csjD/fKkHV7rskUH7UXLAFg 5UKQVZYtrsLpnZ2QSl7QdVCqZQLCieFKtfF/ZXHyDU4GhDJlzaXEHgNCTsYQ6+ZnzT/Fw91YarZC sfpaie9hAgKugyoormbxuluE7IAN9MzFlhu+IqKPHMhE9B50MF5ozxVim6TCdVDKfxmBjVrE61qs 1vIhH15PgeMPi5OlU3ogFHItot1CJFiZEO3lUHx04tLLRoCPbQkC2tjXxWXmexojLe19DzNG16RT rI++UlD2TjcAtiA8j1Fcg/d7nUXjo+N/epvkWPuwmSS3J2tJm6ZqWB8eRj7Hl1NexZGe4JsLXSrA 29zlDsV0NsDEPRDsmcN2PUde3uReKYUMEUUB8Otq+zkyh+p92so2OkSAX1FIWHk/UnuwL+yxzXcE BpVqAEkmVYNG4jFzgEA6EVr0c5BICStrG7Fl/ME7iqE1RM6Qj4IvM5etyXQRBu2ZbAlixpR5EkNM 26keDSiIcgGaHttIhY6wB3SqjGZly+i0RzQyeTRRAPjFW2+JPCdneYH+WutsUKPpxn9PAxcPaIRz mZNUcu8cJ7B5dH4KAdjkV6r5a43hmhoHaOxDpKSH99sdsBBSOwCMcZkGLRlcg5PDNKb5W4o+kHXP jaZvc0w+leX4cfJEUkAIkob6STgVinFGYVDQrcGLlLOrWiacKrkl5qlFffEmNKdaTvrj4CWxC7nv cr9k+4mPc0Vg2adfoVH1Byk0f0CPIjMKgzqVs6zkw0I4mVD7fz6Fgo/z+hd/88iXTmxWvw+u1NrQ KWhu6KtSxMHEC9fdR+qo9e0yeeBW7pUhbbxhllWBL3aRbHOgTs6Ynji+ubCYqavHtti1YKqJGOA5 OiGEJ6+EuZ9btI1102d7hkpr1fXcEwiE57Mco7i3FaeXG3gc3vmSw8TFCNvewfuvqLMmEzMgDt5q R9o+A4OCwYuU3loXziey6V/f7Jc6xwCcfiK4ujXlGjkPtOCxBuouFlm+sWpUfwEPuWhiSpFPXfZk 0yATseOs34kMkui4wJqBhroBpMYglPx/vBRr4sRik7VPCWNqZLMYeju9KGNO2h8hrJGxOjjar0hR SglAJrw8CDCGwaL09n0hvjPkdOTR9qPR6t9F00CcepFzQGPNGULv9q0HE1cYCo9TS+HDo+r7DMW/ sJrgXFAwTayYxpRDsrz09dGGZbA7vgYj7wV1WfQdAO5ZJHcyxduI1EXBWiMYu5lY0ZCuJla8CIh6 d/1SZFfuArlP5dbWkMetQFPzsjBjSBdxC9do415t5R9OR8/kIzf3I/Xxl/MqWba6C8LRqlKpb/Aj eo1pePKuksh9Q+VnASLroRa4Vp4CCuhNWHbtyyEet9HZpPksPjepc/JjIVvPeQQas1SHmts6ZeAK EccZHVHxHy5FZ2C7AqOIc/oEQbWut8dGxpwH6kyTgFdYKKNakekDqYqFFrsKxlsCHWGSFw9HSIzl MFeMdO9/bRI/f/CCH8IdXh6ZFrjyb7OCuH+S+f5uMxSTV6QOwsRf9iBWowmJUj4KJBuLXgMa2rgM HNLkiTsLBvynRcwb1rLvJNWWA/JcvV/wKdEHwwiDORas0Ux8RxO+8+2y3k32XM58+vwJl7e8dB9Y hrCNMI9O0cHeLrJl7zP2RLCZkXO1s3pShur6XRpxl39e7j6cYvikKFK/hXsDSGBf2qkZbW8FEf89 aJfoSPYWtbjGx8EKiPl6mCgp2F4m8Po9rPnsvswMloPNshQUGzlC7Jv0ou0cnpUzgcTp2Gaa8nRM YiPOlMFtnZuLF3zoasodRi8FN+3RI6L1RlSaO11PTPMVxQhVVy4crkfYK7JxdwrfgflB4jzcOQKg jQSNQyaZYaveuNcYwTajiYGAjVPEmXJ+iT+wLIwcAl0mICyM5opiQtYEMV7upjHmS6G0/9pHDo3p OY4ypGZN607EAz5Pi83VveQjbJ+GvHTle6ju2yKs096tn57GyiPnu5BzzmO5ZjE3L9mW83RGBhSK V7KUVChRM5nPyMAhc8jpNagfSpRtbQ/PdnuUTE0q7HxNrTv0MYAiJzt73ppU3dUWjK5SlZCInL8L BskEjonN+s8KTCWbZgH96VGevfb0xDq/thxeBEHaBSfQIqh76x5BQPRblErWVn5kBEPvDuUSKGr7 Vd/oVRsrBl5zLm/yj5OwHD9r2DYKv/MzUQA2gMcRUV5Us5+nGlOVJs/5GtRIkvTr13ReiDDxy9du jSQ5EKQ6pCi96khxc+LU5NpHzRBVwOnSVjX0uPuNjvP/aqM9jWZ3nufifDM/36uj6WNeEEmYFtZm gfPhX2JA/zIpGqU1COSTfgikB/xGffZfBy6Qmyu0xi9ayC2kBsAOe6ZNQKUD1zoUtYGTyIvEdDiQ aNPcgI0wNRPfWGKBOdj4YU7R1DT7uNTVesNYghn5Q32rPKWIaKq7eLRG6Aku9Qtl/Ped2xfzJbHY uY8U5W4+xt7/3NrLFacWbH1+hecthjwvvTR5bRPMZGGPRCMtmLFD4KhF3yxRcpbJLo0ehum0H/Ar Ipnd2YdCjeUFgR19qRCkIQ7DefntxWZb3KtNwum6HKYT8e66heaRqm3zk7TgMl7zBgrRaCXT4AFp eWt/bt3MVlMYXRqLXPSCRzW/wvbRtB9IcW6GnNBKYiHrL/FyNzinULrLvtT6h//R6wShJznPLSLR pVnAxJ002dWD2/Lilb+cIlzot29CQkj/5vHuBrGIzD6w7YM7WeFP73d6Bwbv5wNctPF4CUv4u+7f Q/gLTI/LhBEUqtjL496Vczvm4nnS1awwkWPlI+xG5B+5Szw2zx8LbvZJUvv5AKb+JS3qjwY+kDNT 9kCL1EyXrI72jXQq7fvq1lPz5tnm7ITglpv2TJBjRx9l169f0/N5Ufc2Kccs96SJx251sM60eJ+x l1lqSQc5oOODny9LfrHZgGnSMlVda7/Ww4wURzvV98CzImQOXUJMbPm5gnDsHfTxLHsg726Bz84Y UlojlUMhblB7DBl55vryDG1jW8rN+kYr8Z6cd8MtVnKKKAYRV6VNaUOU61jKMDBQtN5NOA6iXWYC 85O3pGR+wwY8RJGZR9jpFOGzrnqp48S+Enbva06xEN+fgJM/V8tAsYzb/G+nocMhwD74Z13BNN+A 7uZdCUaMug6hKyo985jXpaygOPKlZAo4kFLkjAEC4FDmtq9jv5Nuo7yJQQIsd3+pfNaxsUyZTOQ/ QbNw7v94jqbnd/ObSJuVtIX5x4fdvD/gFWijSL8QA4SZu86bCgkX+p8zGPsVmnkJdwnU0BSn3/m/ AjsHy+8Gouu8ER7qfGZjOcIjt/8INwfKkmjWCKAMn01OoP6W/lau8v1yw3czjLBiFbYpFU/GhJAa W2AJn05b+UljsO8lYuhwSFGr+/zg7WdLW2j1EO4PB535Wqel9jFS/nXuUH2sHPc9UNdRLpTPK69Y yWSH9Tvv3XyQBWPo6NFmaRpNPqqVfhfQs0I/JJP2oD9g0BTmYa+4C+WWl2zo92PVD2ijqpE7gBMq z+au1ZVVkcw3Dbg8hr5U7d3zvhSY8wWW3TE7+Qx56uKr03UP309IcrrCPphTGr9TN35Jq9WLszGn HHD37hO0CRbiBSIAywbDKg80V7cuS6dvN+udrKt3L1LY0Ld1ANHi6sSqRvC6Np/yxMdZ9iKdvFRn uPYvS4tmbKVdJCzr/9DhCPPy7xy4LFYpJuvrC+uj7ggHhQhWECadGSGT59s3kruLrEVOVa4DKbrI b0pzKAazUViunPt5HwhDP5DRyPdILILLHXXWleHib0zRwHWOZTqnRfZwkL4b7IuiP6lBSEKIG3Xa 63B3WJfHdEaeU9+ynYr30vcZja5IggSqlB9oTcPdQPwr4V7wv4M/S5Z+JTvyaSUn7/0K6Ig02Dii lEhXGszyJ+WrTcwgPMAXO8PIodNp1kOiSbY0cUADdbcmHl4u1Th20t4Um7jdKGVEv7mZYqPdfr+p PYVKu0Up+cWTlXfFKOKONlvce9Rc/HfPJQwfhcGCaxKv9qe/J0AMfD2YalsT4eY6YRVbq7UQruwp hRQ1VgJVsxXbZqVoeZHb+DL/BJ7hvMVHqKbNfFH217zTCNsJy3seE6C05WSjgKltWgihhTWqMp1/ PYdfesm4ZzTVDYmI/AoTua+ikrpXTwaM+Wi7VtcpS56lEsbJ5uexZuJgO8HFUSbdq3hPoVrMu+bM AcaSoSDC1WCFI95ugHET5XQYd3llsnUmDwrvMaHVJ7tY0h8bYVO0QKv9D1e8YJz5WUiYoRHJJZq5 5Y8EdQIT+YpX7uEyylCbGfiWNwvxHz01Y8c8YUSuvMeq26XfH18qMHJMD9sSvSNNUrHDx0tbpEDI brMaqxScIDL5RNc+uzvFnnrr6yelTiSPLt3N6V0XkZKDXrGulrjUPmMAIp/IACJlO1fqUZ7dOPSp iEfKF3jRfBCFudXHYl8MJmJxmJa/lPi2+3KirS/GAHyIxm5yrUQidd0F7kjaM2qdbhcyFidf8GwJ 5LD1VsW8caZtyC/uAA/ReARWS6j9AMEMgNVw6GCpB095qDcigTdpxbLAu6Yy21Jpc7oTGgJmz6Bh wlXrCrP1rU3aQxyzZZJvQJEkoIIa9MyosUIUHowyOl6C+LWLWv0ELxNSwLaE+lmlIgnijvLnyR5E LRYW6a0ewSFjQ3IyZuQlMsNn5S9MfclS8d6eYom9995TSNCRnKe8QEA/LS62lduFb2+aWB3RC7xy XUqXBTCa/swpZZ3LVwBL97xASdH81KGdhx4PeC6WjvvnDDIAFnt2ydQ9GpPFw03YWMkqIDrOIaF1 SF2bQXrxYHgoPVY62Xom6R+8AHgBCyXcGDA4ElEhL4irEJH1P+iIv/ZW4IQk9EbglgrqcqIwaemm 0DJM30FAPnNVdG29H+FlWEOEVToNCIa7P6w0vfWWk0Wr8upGRTwwxIjq4b6zWIQYOrIsBkLbtC/+ kaWORDU84fcTAzz94QhOdZSlwfDDImanLKqs0ZsSmYQrD4r6pfFdG8BKTax0yuci9g9tMJ8jxAdW e4eRYoeNb0Ghp7ZdWtFRX46SJeDmpzUA7rMPS4EbCigizNUKJ5Np0ekupFKxCDU6EY3TG4dC+4pj W12XDuNfXeyyUMqFRCxAQpv9+FpeLygZZlRHY5L0PQOh5bDGlpcFlCgnNClQtgznu2vym4HuIm/I j9a2SOV2d5QdsTBReCbF6VOblN9SBiJk+T4nA0iMXiGkCgD9Y0KrOYiJSRH/7FFjtFZRYH3HRwAK 877Zy9Q7OytcKP24KL4ZvyEFRtQbnogkuJdGHPz4sSPW/vU5wM8bfya9yMJpyAYGMmUg5tIvdXX6 gfQyHKRUmoL3R+2D4o+rJcu4qPWJkXMcf56mCEuv6ALp+d+E3U9a2BY/zjcf2zYQkD23qjjBCbs0 nWvdEB4txrjeaV+XYYHI9IgwOvEwY7KCLDNXLeYZB28RacBzLHWP+u33BBfeTksQP5dIbr3sjql+ Pw4X/EBlMrCF4TIhwKokKZfRLCrrNSe9SeOsCHVa20FmNv7rJore0Z9w8J+3cJKa97AZ2xzNSxv7 3qoWQNi9njtjUkeYqYR5BzVT7I6HeHwvqzhYE/6peQodRI9Q1kG+BSPm5Mk4pOAm9BtdjhGxCcOY mlbVTkbcnY58vCi0IU+nhP2i3fANSSMkAnBYdydFqYV/O16GBBy0Uc8eFO/IcZledfRdkEBLEfFY Nf0HFk5G3VgV96Aox1ED4y1d8Z87Kb+R7hU6NkTe4NwE72t3/fFFoUBOxBB7VRXA/8ka3KpL7ALD QsQ9x1wkst7Bbsiwd1G1DKvAIhLDOUyW6zny/+TEarcZT3byIo8uShw4nFz1KJS3czhTMWWWaj9L i/YxiSZRtJz2DWJ7Pj9qq3/jRVoZG7IvqNjWNE0FRcSJaWAngQba24g8jflZLW+sp3hEMpex8oxL zDwi+gDFt9eExcjZ3mN1O0i+TmKwwtaCTojJeq5bPyjO3K9144cbQ76FmcQYGl/BdCr4XBLLhzON nUsHrK3YhHLEnsoDY0fibHVf6IjCh3IT+xJTe8osZD4Lay+/3KjvtJe58DYCLYHxBLFKZ5YVxEku 7mkRJS6ZzyRq1NXBGH35LF5PD7C3zgQVdWsBvorLDWDPKFZw8wwQTc8aUutVCrP5mQjqvdLqGmbl ts5WeCBzmBGSXl8C/MHNHlJuE+T7qIUYt6+xN7WfeMfhpX5R8aBXr2qrmYrDDs2ShtEpsk0y/ZeI xNt1PFNvBiCtSKxvwD10sqLCouunugIF4+80m2yKbJlMmpPxICffXHwmt6Rho1s/bQOBZa0nUs6w FfR88Et67MQqRA0C8jioQ0lOt9+LzzmsnI5AUeDikRWiQv8ohf6PP0p/WK3twms321PAMBlJaWuU UsT2rPjZWfIen2wg6vdL6ZwXKlI+EZxxAm9kI+5HOQ31M0a9Eom1Q8APS/yM5qZfIS9LP3ArVOBY eKa7SIOcJ8sfa1mehIFCsnl/sVBVNcCPHoaj/M8263g++r6KalGh/tPr6YoNhXS4rAJ0lHHbqDnB rAbye0hCB1zqfUzVcFzx6MI9BNPcsmju40k38fO6JoiQn5WlVOzHvpeNb+iKAqAe+teLYAQNQH5W hyCgIV+Yh1kugtfQgxzDSDx6rz0ov53OZ/xR+sMV8PKDko2WSNRn6QeyfYO/UrZ9+k/1N8T3iDJj /FDeWxuwI4zuEQ4DG9xbkM0x2xo0YZoFzXKcoCF+v/g9hSi5f6tvzcUhAM2wL+ydwG8nsBdZgy7a bnTzhy9rzq0AslumRDYwty0Kyps8gjSlcyXwWnqhDyqfi2ngROn4hKdhWijbJhAuV/L4JVK2rue7 N53m6gMJzugjgftr9yZSa+IHwUtImH5C2M6NZWY2YRUlVbP7W7w+avhpLdxDbS/vIveSmPkzuPr+ BmfPIe3z6jNziCxKeU7bd8VPWT4I8UDRpBZa2lFdeFrAPAZsXBihVQ3yZ240vPEWFdzkWytir2E+ fmN0mYF03+S5G7+FKOZSEGMpSClF4EYYJaJE82OHOcz1s0MwjZeCCtBlQwK9YvZxgKcJbXeATp/O OEf3U0VafhNUZsv3b+p8tf4r0srZ/LGhvgOhiO5ynEbeIHxCC/YFQuVgWP0IM76jlEo+Dij1xQDl 8QmpV8TLlbkg+mhxa1GvbbXpPmew7iZJpNGZ3Yzw1x0iRK3n96106yJUwdGNMj1DFo1oneE/qsLI MF3fQvmtbctzNjc5JRobcftPyg/HxK94lC7Vf9L6hYBljmJ41ad/zHktB65JmU1TzR/Z+U2/L83k IPX3H0gi541PZh1lfOFjNGsou4b6PubTXOJUPg7Vht+VBMk8zAetfVPETac+B+CAKqL05AZW5Ik6 i4JvL7nJ7hmD6J/Gg+Z2RJx31FjW8xYK6U31t/7u4hKMRBoKxLDAxrLPvpxlxf1FH2GbR2FaRIJc EYuQ7Ga+El1aQvqd3N9owdomAzgCypvRyCvofZuHW8cbZE/GUr4sG7E0BZR+eXmb8bn7dYgxd6BV GmTPdnTUQdPGbgmN9YBs4O/BAb4uXnXUXtHm/+DdDaoST3aoUkl2Wb8mjlvDBu8IbgaYWk9MibkX hXE5/oq+NpbtL4UQD1bqr0iHFt/mGQ20exerjQ4wpStw++L28wWdhahmLxm6u0l3CR6jDLUOffhM Be1nXvypoH/6FYX2cd9wzOcLejzNVXroj9KVwDxjCZ8oY28gK+zCYzHzTa3jYNT+0b1reipIvFG0 QawzYhrqpAdJr1EsLxbXhHH9HwVjbO8jeNI8rpWsqBRwO+Usunur+rHBeAyYBk1Sup5rfL+hWeDS LRhVB8uHzATQ+BAFwPEOdlyW16XV98hkjoXMSEJN3J+SfMfCQYEIX6uHbE3MSO/lCfF1nJaaK9wh +PmAP5dY2BOALUjsJtiO+0jBL+ss8Ho004O/GE0tXmHEVScdvJ2fjoLRpCuZIMbl7kZoCO6hnNEO WsApZZCm9sFSj9y1UrbPyUX87lPvANnFSxBMAm9pDAiN85934Z/78nxd38cBF5hnsSbtz0KPAa6S +c+5DS2mzHlLxLqNWFlj33br1xD0eqXKg/fU5/NoDTF3WDB6hlUmRcVLLNSCH5Iy+lmLon0cfjTw PQRK1MBRnvxBFYMXX7Cnt8VLEK0mgcqgZZzNJYwo0NcsIyIKb4ZD4mpybf7m7CaFPPUEwKUmMkDH 8VUwR37PdOUtYxxYXDaLkiRTe8tesJhnIYvVNwUzXXNcIs0ruw5xtjEEZdfEaZG7AmcHQ0Jsbvor RGkhObSTev71OcDUSUsuVw48mSykIpd4XXlUGbeQvMrP/BqHDcjbioEXaIOZxf2ar1LDS1zjIGfP MyqENIa54DaE7tdtyZV70b/50PMkfbMRvCOZRDMAmMS3A3B/0VQRhIN7UdeLhIzezHX9Nc7daLpB R80aGyvdBlWXQNIBkGYH3gOp7Jfm7/QxGgQcC/sbUamj6B6Xt9i+gS4DTwAyzY9tjFwSwnBZW89z PFUH7n5QotPDNWMmCdxS6KkiPsOGVfmELJGkKF7nrXfRWHes7WneKhQRtiwj4md2vQVTgSLDc0eD mA5Nh/WDzzehS73WrjbXYLsVZQVWZi7FsenoUOiYTx3qSNoqXbBSQI6DmRpjHVdTztsPuFcisEgo J7HxQVEG1t0kd6oA9W0hrZ0rxliYb8N+0A9b33m7CANUJxuUaSbUdbiyYKcPBcGVmRzL1r+JMaj2 vYeQ/y/eaBDZwILtuGTWNPuuCD1xlD4VwroXECXO4OzJ7lRPegfH4HCuMKlzzqYAkD7gMy0nMAXD 9pUUFQNURg2S+gfQJJ+2WFte/B9xPIbHTPP+ZHU1G5HRP1MmZdDF/spfvxium8wz2HQsV7hPN6XD TH++jgtZl0oHAyfqu94+sBxYYGEggydp5FaOkM3gSOuK2fzYLNf+t2HhKt1f1Um1bi5093fue7fQ GO53yXj3+90Cv44tTWSJ9MED6rtkyJpa0i9nLFOs6i1TkbIdZFDuJb1u0VMyJliMK25c0nPjxupq P03jNcn/c7HIFWDbx+E3pQabpi3X04f3qmpb3f9UHj4+uzM8iZFmPI5PVH9ICRjLebXqYCVO5uSE V0F4d66n0xDB8d59E5LwYrj+sjoqZ4/GMYnXWGXyu4DrNElzR9ibABO3t6+TKAGeu7RsZ1ByyXHc OiQj+4rG0bQn/+FGjmWZjthhz65+GV4jBxe58RbR4lT/1FmuXiNrCHjy1q1yVgJDTzYzHFftS4Gg +E1CJVbAYeSZMbf6eg0zCbznjGzTkZk7Q22hcEimfPwAXrf5hADoSuvGijJPLIEwDais8cX9uS1+ bOQIxef+Eb1tyd88t1jCTvqI2fHetjfqtIC1cAwPWNNamdvRtNtvG20G3bupme4/dFXEdXRTpE7b aShSx5Bv1FNxjYMnzsQ7C2OpdGQG39wifyR80mgi5JD4rpE82m8EVAKhP4l+n/YnCZ4wdLg3I+Qb ipuFwzDofbGOCstKIBeXtZz8EusE4JBLV8gf2781tFXJQNUEzD8eOq5CK+fAHF+l/LkgfEgVLpWw Vfn13ZNblZtD7wEJtja5rrv4/Nx9/Hf2kYSL++dxNfqBB53Yuef6LbBnMb83PFUh+qYEliOy+5tv 66TZYp2I0WAVKlx1CqunW7VxClptFW/S1gZ5jFSCcBDwpmB1a4omlblZa0yUbx951mtPtpTRorMp iSFtB2DjWO+XVUtxqKv7Rv061qIyF3P5+wA/B3BphKe7b8ZI184P96yIuoFLbZR6xDUko4ifJqCw r9UjBWAIC0Id5dRBbTA0HkRnWphfbr8WNyP6HiNUtVztJzPw4vIr25CU4dmghVDoeXx//l0ZCfRv j10jlfJL1gZMhO7ext9bSX7CN+qOpEhyXEpmns4qIwGME1chN5utw1vR03eLiYKSwNFeHehDdIxc WehCG3jUKiAAgmgUHShEIbKJLOPd6NYOfBjU9No9Ma2XSD7yRs9iCwV+7d/OE84nUea7rRe9kNJm bFodJMq9zVsVnAxe2h1DLouTKqhii8HkpQ9uZUpmONR5RsmarTs47FqZm3aXspM3vVyivPX+UlCT ii+cYuxEKwQOduWhu6h/2s63xeJc2sBGyQxKqfS3G/gbrOCjfBXArG07G4BG/W1t5SYY+PDy0WXo EGohr0Z13xFEcgEoL2FCoYQ7EzGPn2siRsWV46KwEVqiwcMHq11RbvjZwcukxi34bxEkP+IJYJzd XpsPIHuORK3dfdN9Pz9JozUGW2hakT5NOa7TvTGu3wwzSuEzUVdp5vNXXjmn+WEigUNdfTlnjVq5 1zHWIANT1BiD810Jzs2sJKbkiXrugnjpOaKTtU+SziHD88H62fCMDmNXcJP0ZUC3KOmyn4uMPz1H p/TmOvxv8XnNLQym0zwBgTDDzi2LIhzK15erh623i4VfPgrKM+I98IX+X0/YGlfFwFuz5UbJK5kS kVH17tIpZ1OAmxY5oN2jVUFB0IYwuRZ2fItxnUb9ktmrU+9cUAkS1DzL+b/ABgveA6ze2prLh818 eZzcP15mvBwKOSfUgimTp3VvKwEXbX1bhoGg31S5JepJUL/2QQpkh78B4SAMPtusGuJTpW89jpF8 xei4tMUM3qfayjNgSOfWb7Qypt9Xp9zAaHa6BYZbXrxclM1G5SROFbCB7ZWeh8roZ5DOXulym+Ra fYkG3g1EHftPtYM09+MnN2dSUeNXDnIbIvRqrDUCFdKQIUkl+35gugCIgnZviuH6yolcO6o+HcL2 M0Xr0FfREPB1gvpyBbqL/UQYfBphzO9ZCennWrrZPlgtSVJvOYAlSfe7lr46EksGWylOFbvnKBOh E7BBqcc6rAAdyoijSESaWkdTcqvxZ2YedZetqzL7AT/z8wZQoJ/TRObtqHohWXLH0x4jn8yYN4zD LkSdgFsSZcDWHSk6FR93TlNCcAY0mjn2XIhplIKZPyo1hgR/V7y898sf+bSysqs0JILBEq0sp8sb azjVRfGyxUBHNwf1j9mzRofVQ4S3TTtP3UO6N5PNjZxgQEpJcR1Iqgfb0x6GIHqIE0Ss9P6wgCvy hr6w9ufM9KYhVc/6H1gyF15Kz04ULGfXjJmxkucrF0OAegdAAaJcukHq1cBeLccY5souVGiTpRV6 vyW1yJjXDJSExVL3P47IYNE3ihmpG6x3YE3XxaTvNi7Ubcirpa5UeiMl8LA+29NWMDNOOZjo/DvZ zUccSskz8XJmkA7z9prCZIWfcLqc8/HXvMifdvGwULMNalcQyqVQBEYKJrMF8uB3N/36TUFK3HHx PS8BH96x7qMDl+eGcEtq6JkXg6luY8fE31h3m2YfoA1pdHhfh9Qai42UVK0Ui8zqTqz8asVRwISW 0LY1ogGFqjKSLpaSYh9Xl1XrNPe1euzFVjHrW3bEdkInrigPZ0RoIej2mN7xuLdomj/EpB/h/T+L +vI69wt3aNvBp+CwF4C/afgTao0EqQXME1+B+iS8zqJTTYLwI/QP10J0cOaLLWIHwMuR5dS4NepU BjxcxEKfx5Q6s8xuj9vlKL8kdHIAklGWM0/c9XPbfTFpDmfENmM17acbPs6sy1sFCFs1RHNzAwOP xBOYqNhI7B+Wc5eSB2GwPFjreKD0fdTJe1e0g9pq/Qa44ENOB2vO8JfhlAcCZ8jbdpCOtYvz4vrO qHQOBx+7rBSHhXrdJfrLXiYMzaIvRax+BYgC0SH0LH4PKBUJt4MTWbE+owg1Q4fsLDFivxxq7ZzZ f4nTKCUsX2x76Otbh9seznheaejr8oXGB8Lybntt9VqIYTF/N20kd30Q4IqrHQ8o80EY6bRShRao t1WY2nCrqO9TomvBecCsAl4SFonYRCf/o19UBiVfYec1k/sNKRGLxoytZUbkNc8z3yZvXH63GS9Y 8yEkIHq6u/kr4HiAs7p4KUwwRVI6pwDxne1zHMNi59CAUzEkQa9sa7G+Fmem1aWLCqAj6lg7K14/ 6z5nF3+KOziTvzYdp8fabg9tso+x6Hj7/qI/U/7kFC//fOEyHEPYmxyRrluDJKsxCtvWoa4y0X1P PUDsPNLRzx2wrVvmNaUXcUUh6/Xtp8BdG6XwVuizNqKrd2B//dThGvXplgPIASxHWgohXkKzfBqw dchrjr6jR9F8mdoXgj881ozsNuauNSsyk7Ba38hEMu8LFUTvktwRsIrJUDD6NmBTa+8CTNubrKiS bxKAwFQYa5woI7VRbbDn3fwQOUBrG/X7+Jioz+HvgE4sDICHHOyOc860lyofKEd/XO16SfJkgiuv dzwROv01FcC1LSEyQma2K6VVBXHcgsLU9h37AwQoFKpXjia/xD3ofTo7/3OUnAVGDf8ppjcqvTrJ i9s8jgEX8wl1vA8gBAGX6EATaa9bafvLPA4AUCwj3L4RzdxnOkK2DQBmd0KbX3keqeUYDO6muwQc PH6AO0ufb/YvhulFd3j5lQ1yxSTx/pS5SKeg0lQ1aCd+Uj8Eb0Pc9Be1fUCvuKxeZbyr3c6o87K5 4CwFj5hrVMMWDvEm68K2kRkl/Igv6MbfvCHtzPdz9LL+ZIlo+ZJn3VKYaX8X0/2xsAIMJVRMvZeI +QvIpXSXitd8Y1EjwVvsL1w0HrX8BdppUJBONDtHGdH8LaXSGo9bseTTJnESjSliDwhTpiF1QLZc pETz6aCqF8fHuwOhVUrU+8vL8tq4UnOfVLDBk47K0uYmZgVbZE7ebdlrwikuk3QZj6M0wakkc+oH tUQg7ROxX9tRbMmk3qIYFqzCpmhlvPeV0NvoVfE8CnXyDxjDHoFZhxpfSk34I0nc0zPrIszgotN4 tB6yKHVejy/B7jlNe0GVIR3Vo9VWG1ubvq/z6uqZcVc0C2N6LBGCmBdBDmjooN2AMn5vIoYxYa5G B0/oBUDAVKAQ8UvLBIFuGT33eq2QZxhkEviOArlnTE+eIqStv2jQrwoXJIu43evKnrd4MS5GDovU MMLdxj1ORxxorT1n+IWXkDo5fCHtiyuY2ZlbxFJJnVuIQw43diDlGWqI0vHHNxDGcizy21YQUlaD dDZKHDz2thGE11FehkUiEoh8kXEIblW20SLSOIMMpXE1yT5ydtzVa1dQClo95/IIrwARwoHjiDks ViawZqh98Q5LR1gLlxorhBC46QdsJf67gkx4dubGHftdTCSmpRB1uM0On4Ihvho/D8jL9UJEuuIG p/AfPCNXM8gUmQJNWmaaLmRWwW4S4prfTrnUcuqCmr6S7kUnaRkzLOhAXG4+0ov+4zvH7Y0gMeUI Z1CpOXfHliXI3ng0CK4gQLwrtNblVan4klRCuYGNrH8sl0NcM6/VH/qzFiCSM9Vd1C5sRrXioKaq M97TjeE9CchXaaLaI2S3yB4R7DjBLSwsnZwmJ915SyG9LatCaaxBn0QUzce6dCBkLlYgf2CXIprH JFtW7rUznMgmZ2tbbnT+jSqCdXdyzjS9uICGhk4gPECDMnwGQ6+a1kxZoN6zV3zkS/hqJNBJChWD MsnxbVMMFLh1g47JIP4AsECBG99fFhr523LzdVhFEI5jwXRcsytF+nGdaeocgZimV5jGeTA+DFtG HjJucWq+P8JXcaPHmHuGY4yuVDkpXARXWJQ54rINEebP3zXvoq/KxKpmR2f81aP9VSvQjR+2MvrU h+Tr8Y+rL0sM2qGWqVoBwlYwjV4SHfBvv+t3ogk6uP5XGrIfnHADjq8vocPowaux1d+e7HLFvtOv pIo88Sv7xAEVLt7Tdf1I8VJSdLQMsYAJ8lxI4V0UUdMd9hFCyxItmXpY65q99kJmR6VjXACJMFjt QfsGLT7Cq8vRyZNXGN0tTmJzqcBGJu82zx3BxKuxjO+8+BUWZnxOY/bVvvL0SW/pu9DulOXgbj45 VTKeTm0nXu/jFmQrnarXeI5KoZyZTBkFh17KA3dU6dgoiIz1FFI5FkRKJMKEZvkO9BwVTe7tnG8G 6UA00t3NvCuRJI5nRDASBeLbAbXjpbAbEw96HAmFYD8kilKUS7dkpMzRyr0de+fUB1jgmKao0I3j MFVXj5KxicJC9dIP9vmbCAHwiMbyt3MmzxMfdd8r3gm/SgV8wipx5kD6VOfstKb1n/g1Mcts0EIp ZiEzhoLFpLDTxbcFwOzIsHkhW3hTCtwWjHJ7xMNda1MenrGSBQe5ChWDmELoH7HZbWjwVE8PcSg0 VVYDCei1gzCvQw/2UGo3Cs2DVpXS3WVcJf1kzKhP55FCSXHLvBUK7/Tje+CXkz1r0rUjsgEEJysl V8O4Qbfp4xySjx/X9U52P/pJX15bmu9AI/gFNFeE56dXMYOJWxEMMUVMrNzKdWVQ5vEHwj4+sT1X 1Kne/OS85w9l587OFPQ3bFexVZswi4qWfqasjeVFbfQCaF77pFVCCGJACNxUFJuAxTPsqEM3JCI3 /uSo0A4wod9Vu+GL1X8gBt8+jlp3hO0nRKp5KkNflQAvTuWJKaZqFkFjmdNzCs5hoeZU3fSYodYt ghc5Wvu9jNxopyhLbwhRjCkTruIpKe4v9rIVDLQM2Lz4ds6FKFR8XC5lvul4X7jNVCyppQuY1CCU WAA3LEkIzhA8fAp3Z4iGX9uHT8+QLw5fRw+yrC6frfmalGP0kpJM7LmMKN/YHz1qLaXYdPEQ6UaK bKcXLVAD5qOJrSbl8R3eQ2MfH1Zf6UU8a4FsAAftU3WmMMLpQeLoDztmd/1ODa/qP/E92t2LMc58 DKQh681w3AR7Z3B53pcl0wV4/je51gOxtA4J8RWTdQaRHvGnNzLMn9Spe1CDQPeQQ6ES0hmrCEmc B5OwPest8gMRYFnXLj1zTmFqqz4w6zclDHEgywyEPReURYLuDlVK40xWCWqQP4y0VJFiT2/gHbP1 WXABv6BE9KbWGtyOq9fFipVccpp2Kb/BliSmTneKTS898cIRLAPn/xUVjABjhakoHMH34rDz1YNE NYjink33xhtuMDaGVq3Gx6QSgbWmP8FnYkwzEA9ih8GvH8Q4YhYG9V02tdT7EgSkzXLPgZlLwrOy i74Od5P54H469m0Q6UvQhwtTin/lmA+X74BomjAQOtlNM8CgtIUY4JmU2Z4yjZ8qS293FUS1RFaR hfe4uQqT9qrTGo7pxMm0rr1hTQGpUuERvL00Sl33YPnR9hqmIrvrmJwBNwnnQfaV6PBUYyLcOjRz /KL5+sEpbI+la0GR0ooXwmfpslF8Hp8cAa3nY+o+rMYouk5N7a33lA3h6anjb75JxvP9TxpzFR3D hDUGun1p4jM0BYWGbYvw8jbvDYIHkrAi2V0lqpA+x2QqolkyhxVi3CnHMOWB8Vau/LtVf5lH4JA9 QvX2pked0itbZeYQ+OlVDNMlvp3tfhWXa8XfOrobdaiLsUHmBipPp1LzcuqtU2zAmG1n59Nr/+XO aue4KlIsDbopte2I4iIi87zCT8oRXKMvhLVr4l64Fd9fX8jnuZ4KCJz01RD1iqJmPcKh7stUy5Ho IlhULiRmB7ONduOd988EtUqvvmwYvjgmG+w8TaeHFT+UqCgyP/Eed4g6zlabvTKhCxvCBK1ymu1g xlPyCKgJuQBKBUx/eS4NBt5BNB9joYTgkRwfGFp0PoLSoV8dOtSpFH1rOzn363Jo5kI8n+DNok3C RXUERNI0wyuHuuEi36jQeryBwQu+WDsmctx7uqAYxelNJSoj4CcIAgKsLZjzqKsGftIGqkSaxQ33 VONetDZyfMBB2MgeNmcE2ffUn0V7tovWCSFh34scxMOzjxpLOvoRuzGgA597t00unzV9yA7wgv6P NJUtWeA7LQtdT9anMVHLTqEhLZMkG+/F9i73/gyxe1lvYDohu/rvLcAgdjhXavD82ml9IM6AXw8r KPosTdyVuUH6YPxszvwbOiecDiFyjouGURPGyiogSrIYXPUZBeIzFiu09Fh6o2q8GCl2kxOHmoSd c6MrkPeOr1rJbg616E0EQsTYNES/XYNeon3Frv9qo7n6B6iGcVn01Y/q4DKKJ1oq9Ufh4y5eTf8U OgTEwIrOZ4WfBuYKfU6I//a82sM0ACXtClLWmhOxEO61QlQnzY2D2hrQ38fJ8N6WHi9g0njY7+Po ReOZgMoPkHgy9+Nk+mHgatIAqS1snPW90kzZyyiV5ARff2uCBUsVMVPA5oWAuaxp19uQLGWxB88f IA4DTeT5z0FAeTnqq2ol3E50i47TgZAURM6T6oyHA7QtCF5CjDuwxAiw5wjDETovgF8W19r0Mtf7 mPk5tECJDjgOCtV27Pnic3TxHSgQzofLgGCDMCqUgdJxSz1JlEQvprmvAfzNXvN6cMHzp4KzjzBG vPLjKtQoPFz+pfr1HsZY7UJQFMIyY0HKovP+NmT4dBwW9uY2Vz7JZPbIFxcydWqVIE3YuniQrRNh L1t6ltiiHkQXLj8UpHLA7FfSWxReIxqC4kP8HlCFIvNA2weUYwCq/Qhlt8yLPTXIMsI/InFcS2gv p5Bvu5MgoT04uz9m9d8aDC4CIgM5Xs1r+/7UC7/tSE/zO5T+grevkr4ISdNL/9Wz5z4KeNUxIIHd /Dgqz4xdZz+xR5U8bdH07jPwRPYFIEK25EMFbuBcnW2kcUWQdfExPiL2UKvIBNWwGlxZdzpsylgo jSRFRLD3AvdN2nrGYxssSJzY0NDMbRyBFLRVkDaDvzku5s8MoIU+ZrHWO+4+ANavk/Agp/nYyh9e AeHPaRhDscpRruPiEEQlsaTho26VZwlvFETU82siArGc5T3RmSDDGIzDWAxwLs1JjRAWNHwVXfv/ 510g+RlF50LDq/MKehgxLu91q1fk4HWe0FTkBi9t7YRzMeKHNp26okY4OeA2TDZwMCOXsJz529h1 hnWH/n6VlzeS7CVjWgddV/ECerEfZS+8FKP6l+LAPQV4urhmh4Cx3/8XjO072qIw5nWuio9jahDT 7YKLNvV3UZdSFUQle/MAX8U84un04+JGlu3WcifBQSg6zLnKaxTAwGeZLP2+lM0PBrSknHhKGpEE D0aTUgVfBn9Cj7PyiVddTF8vv4xuJb+23/Tm4UZQA3npdS3Fh2wrg368MQCea55LW4866QVkBJ44 B61EPD5cAXcPq/ciIyu+thGR/kHXcq2nnGEV7HOZ7f3taUfRYHeYMDOaoWh5mvP8wJK7tN59uBio qvwq3+/1yt5AiC7utCKXHg9wT1FhWK08RD34lrSt/UIHZnP+6OyXU2NSxX8PDBBkoc31Ar2E2s8r j5Y/JoE8RzTdmw0mlRjnOyRsUYGCjs4x36aVwd7sx9A3OBcqNHqFLoj2XMttYOE80Cop/LEL0Yaj /EB0QChzJMkGYVsRxv5Ri1uopEdG/HzdbpXq1D5605fc5EMLXqiXTORzL1IZHJ1KDwPcqBZv+5fO sfQ7YD+lRE/m89GTHH7QfCDnF7E4v2hrfCb93KaBIRSwoQit63ovV8fg1o4/6A7tNBwHsPI1QIXU WSe2wxxgRqzsJmDMfhZXaRGLiHNlaDf4rfTvXXxJijfpFm3q4zcJUqGG4RwkKvPCwu3Q8rXFGDQT qfOAyic+4w0QMLPTNiW3yl+OLn28P58nGUh8iarmzewl61PW7gKtTb9lC2C9s+EeIKx4A3twSt5k uKaVz6f06xfX0qMrrkU9ocF3OCk2YXqJzNyCkUBtLlJEM26RJsT8Q2+Apab4G3x3DT7FrZeWGTUw WFRMWdk80tlEMgoZPmjP7uR2Eq7R5p1q8LJ0rKhNnWs8EtdyxFvb/VnyqofLUPGjLrRNurrWLrnU H1cnh+CvgIJms0ykepfiSwj4GEN6Bpj9kDLN7h/8de8OhUgIbXmGjS3p2PMt97/SSBLqO5CnlAaL 2AfzOlmu03ubdAsqQAwPFCYRXTXdtyLewsvsbJu69E4MZWn8H6w008SxTVdL4PfxYPhW105ZXM0+ mY1XMEAw1mD1nrEIvPcUaqrKGw/j9FuzUju3X3hEUOoTFyQ84GLSTQ6wyY7EaPIRoDNsu68MoDej CHhC9wOkCnxK7eICuV9akH/Yxgvl1PiV3jqOBw2mbGW5E47bW226aJAjCvIajjvILCgTaAXyGAP9 F1zUXjfrM/RMHbLAzoGSq9cwxhNGYpdxlpxkRTpbqEI+H9aGfqP0NxHiL0eX0DZiDNT8rYRV6/e0 5lgerBGRzIylKAvJEiuQvB9hmY+W3e7ABwueRKHhbqD+RbMqUc6Fv1E3C1M9k1gKzkXcqGo9XOCa CAuEh36vVQFQT4N7LNxV8831H8dZsm9/XceHYJorEOo+h0Q1NgjQV9rzoKN4c7UViZghWK2EklBi f14XKsI8NGpCVmQUdXyDkCOJmBtxCabS+/hTmbX0ORVD/HdFovHUm+dQVRv5yiNB00kixMCxZfku JlHY7iVWXgQ3WgqrDJ31xVTsqIrK86uKnYUSvNgc0baTB4HEIVmupFluCbr1K7jM3BgpspBWC2Lj qmSo7fp15qsgk06ECCZByl62pbnVOKAFcRaOHw3LRDU/aGpizXrKlAjn/s5Jfx6yHhMkT3esMr4I 5zGRRHquCpfO/rGkX89Zcyt0ooEi0tFeHsQPLH5fSfN6Bu2nU14399RCXopPqj48uYk5No5J34mf RpphuwM6suYhugnPWNS3edDnLpGeH/BtoHv2A50/jTpc63AfydrT/jHznVA5Svxjf2dPcYMn6phG fFfDQFn012VYC8U8FbvramgJ+TRczuslyFG5WYYEIei15f0dgY+xCURieS/trFcYR10HJxk47rD4 q9QTuks25MnF4jXckx/9cLiSUU0vakam0DX7u6AMX02RJpWt+FS+JDxHaqX/kHAec6GczXmDAyAs Lm5232YKxlQ8ghEkRI1PCaO2YdVuF2mkpz11cp6y+D++lvRgV0mDWYitHRUcJF44QeWJaFqDcCOi 1OT6TWpXhbYS7AfzIY/8RdtbjfZO4G9YMMVXAKAUZnVTue30QjajAo4J7RtA5DBo7WueYv2e60QH 6Gx2BTiSaDQ1t7Ry96Yrc17xWGEE+YKkGf2304PHrKlKw88DhVZXuEz6CfnZoO2iZy2UoOxVYpCj 7+Hfb9MzbBBCm0ID/aYAa0UK8UT7R9dvILiVhah4TdOKSrPHaC949SiHehMmHh2KjaWjRmkcCe6U 5PYI3zCKKzKcEzDssXjkk4JMweu1EQG1kvDdUN8cw7tlPtrVbCXPyB9hnAUdePrK2hBbk4uayeo5 UB1jj/2nB4b5qNJQN8lOKzurpieKJwro79dY19PB06ZV5Xg5ZizL/TphoImWj/b2kHi+QGSsQoJ6 lW8+oSB9OGRP1gufoHHXOfg78zHjtAJ3nUub92tDZucmoYTf/iJR5OGADr94nsqOQirLvE1UlEd1 K2U4kjMQipXFBmC5g2rKMmfNUy5IX6dc+OqaskXUZtdCbstZvC/8vmJBXBtyBT+c+Bwg/tam3sOe wgx38YQgwRCeXh7cs10H6h7MleVBda8ajm+QW5faJAs3fSS6YjGjL8DFG7iCq509Z6kwZeVbIPig UWxm+021EjsO1aIhf0LauC656RmW52Leq8EECA5icLhSh+iC2ecfxu+HbtiRrKub5CPRanWXSM7W SEv0bfuEPTkFi91SxjZIxc7ybx0LOvMNg5SJRCJEDvHotZ+tnd0OkWVs39lJ75PIlgOsQsKMPE7T Ko+heNJrlLd10drkj+X1CzdZ3eZ/ygT/7MrXLRxLZr8466rzNYMAnRLptIrJObbyedjBDjtNd+Yr D04VAsDRtNCB67A+en3ToFjUlxfeo+C0tz9NMJe63b9oWtD91sxYGVDW4FRD7vmLtLYzBvhnoKZt iI0ZHRk+CSGsmugdBUn0jeTP5B5eAeejks0slgScbs602WyzCFdngWFvuH/CfD7ZWrT5VZcWCLKX 8o8OuIq7Rzrd51Jur4/C7C1tcXt/dA19v0Z/4K341YJnTtToBirF9opkQG1N4qgiR2DGMwurRijn NVDzKiMTO2eLOu8VW6FG3iVGB29aXNYR4caZAyiwBYj56pbshpJ4CTMtuXra6UrNESn7GbYwLqay Hzh88TN7eus9eJDiQ+/4Xp1ZZEz33ziwBID2DFCv4Ry5A+KjRDCPlFP/HgjNY2w+bww9JUYBr/ap Z0VoHyPzMom6MlLyi/u2cmfQ8iqFijMHPfS63yV2gdwbTy/Be4rYusxjHLe9oat/UgIaFcCIDpfQ qlhdFFQ8+6fO7KeLOXhmAdpkN84eQMAkBBHSbsdVpxAbk1IYFEfcHnHE1pj9GRH8jlRT5KVQtCjX OLoVD1Iwf7YwP0iMlRHp4URuz5z1XXNQOVN21V7+hcgfqz3c4pc3RGuNiLQZB6SnkJYbcjdiCYHJ bQGzr3kig0yqb5jPo01cVBPpnr4/5Wd4bl8glktxzWiYMpt3LYO+ZD2syeHFjn2PbknVaYqnl3ye yzFhdhTNnpi/pOX2RxC2CUa1fAuj3GKjRLS2tl8DCh2pXVxNZerz8jfII78CtWrqf1d7//sYsMAK p+8NXS1WFvHkV5InGQR5aWVricKSpPZavKUqC2VUyOY1kJqUFY1PQeOWhBYxYMUELVf/QZnUo4D+ 3o23ou2Jm9Zd9uvBq79Zn48du4BNhmEqeAhlC+C0e5ALWhzaHNqtCBGJZ2F+dyHbzRBI+aNKIQv5 SHRYttitRD/XkxlicSkbyoxEhArfBWn080XqPH0D9bHG1CdZeBn7SMcDPdZs7J3Ps8EGkf/hOIZ6 9yLV1DOjUuXdGQ0B1Zshux+LZmfdCh9ouw8xiYjhtx+AU6OMDDtvRL5hKPHYF0dPYoZRjOABMLB2 S7FtkZFegoQU7GJCNOD9eMz0E2xppZq6cWvLjfkLsHm/FT6zpWhqO7hxlEXSEfN0R7JOOYNP7VL8 s2WSquwbK4Ne4Wc4WAwnxh6KjdtQOS9+IV13xC2k/FoQZ/7aEvqNAqwC43s81UUmzXRrPS/AnJPW fuAHkIoSpxXiBy/7PqIou/zBZJgl2lnGNew/hUr6KXiRRlKTuq5+8Pv8GlNaeHzNJYdVQe9c67lL amfzb9LuGFBQVKw8AI24k2Yxtsg6V99kzDbMhSzCOIDcUVBMMZatnqXIwtpJK9ZnpurW9YomtPGO BhHx4S1DLkp1Vd2i8u4ZZoTkyO0yZbB5G3MhuYRhlK9Z+gcxfxNQpLxOc9ECNg/vcepauSV4fxaf i8YaPM72ZxbhiPhJwFNQrVMOFRju005YJpYv9kSCDM0qM6Z5bm68G19bkj7ObYzpojVZ6SWPQNps nJ/tmcfioffCjx2Lo6cu/9T2Pa32sHGXoDFF+S9kk6uTksOuPXcfEbcGL5UVR/Z4EG29PiS3n2hw hpm83GkWATA5+q5ZxYSKfQZV9ykZ460MHviFoQNXFHhYhVnrgxqhwxzFDVsqZx8vtp4A0ecK7Y8T kGi7o3OKT6SkBqxG0tv2qAsoL1HlkGFaRqvTYhGQvJtDuRKwt/1VgtaClhjA/3CuN57T/Lrxpd40 lIcZcmLu0oRolF+dd3M3SYPYQOa9HWAmwS4IA32oFkzsMejjxr575qAucA139aedXlA+PRl3ZiDg XPgkcik/9WbgyABGLt6xnBRUprrjHn+eMOYJwNulz9kBaxLw7UfAPuYGW6pbmnP6wZTzoLd+WaWm Dcg4SIvOrDsBZlrmkRw4rGY6oEQe8PlGPAg6BbmZ9BQIDEVH1DtQYQFx3lcIVAFG4iREw92cJi29 sbVWGRpKQ6yhYsWipJPGYnKegooyKH8a4KagE8LhewZ5yzNHf6g+rIllua6EupAtLns9z47qNhDw NmAWX82Hmg2nS6vXpa01R/U5j3jDQC/goI2TVwB1I0h+6zEfCeQGsmk+9MYV5MGQHEEkEVLKJROu bVqMPpKrfZQ5C8Dbji+PXLp76Uwo4HtKseER01EmpIAwiPBMshUzwyQuTeoaEuQ+4LGJzVqqjsS/ ObRrRjL78pMpAMT6crvFQFd6cpLTTF9iqfivuT1F4wBiHyEVNPnquQff9PEPZFmiWoFVjhAYf/Pu tU41DbJfbPlLrNAzdu2lzkn65pZlh6Kw5OQuyc4E3EpwZp+KjbQouBq410dbAjpaPOj3AFl9ZqWd qjbE3TkzA/0A8QPXdZ/VIxhbD9lyy2tim4SMA1KkjwmW8+ZlEvnlBw5NFV3r7tLoSIZyx63xXovr cbKI9IcUBInuWrrHZgDvOnIUM9q407zpA19EHjOrdCgrNFKFltfJZtb4V5ltiSsDF8AwzBcCVeht 2kGBnqP5Qp8rqv0Pk6b9PNRrTh8whNliPyHoeggiLdCReNqYR/zHX7gnS/ivqS/uqPz1ai9nn/lN aiSXN1TDDTctDCXAIgVXBBTO3iNRx7B1djYpm+z/5xG4b5WrEhwssFzHPC4LbiuTE8YGf85L29+d KVuFV6WT8tDNJtedqJhQ8u1VJZd0PPfSQLgcUUgN3RNcAOHSFqZTgxugvtP4n35NUjQpVQehWB2R tmye4heN4N0KBbrfT9r9850u57o/dpGFKSYcg3pzVIMxtRbem74newKPYcgEk6Xb5O8GCu81KXRw RK94yWaPNApHk/vsgEjypkXH8InfNKp3YcQ3N7WobzirpK3qqtqzh9R6TjKxo/KMp4lLeHiKAU5q IzaJx2nG+fczDmBuFcj1n83WyDmlr75oZKgJuDlTbX8Az7qe16CrAu+QUPwNEWO/1Ehcx3W9Ayts pvVM40BypwLg+6TeW5AB6rg8wizeVvBFuRKMRXpMRXxHMtYYKzKENdl0UJgvoD8JBpA/tUnae38+ ouisimSMe7tFqfM0QG577cIr/8EueNXNWLhBLxAQiUvnLmxVXuRJMwNSI8lxnhBfpC9DrnkC1i8J ZBk9CcjR6ucdOUZUIlqlqmmySJFDmu8kuXWtqZUb6fd7HOmXmr6gRkjvSOtMTmCtXXRDIkO+Uawh v7THskySx8lt6yUAjYUVv0IGH4KxkzMOz0Z1zrHyS/Tc8rjBRtYRfl0fRMg9JKWf8zsTvMpROWjG ZvxRgG6KTiRYZAqBvvspvGntBTcL0xAwhTZiCD2nqUw86GOwjstRCfP3wc0YkRzhBM2FkCedzBgL J0QRn/VtqRvKVtD1rOO9I0d7wgYez4ReWpozgmSNP2FvLNzqHNQ3tfGFSGWxFd+ClHttk9x3Ee3s 0zZxnCJzsAmQv0buHO9zmBBJ9mNLcgzlSjucKaFwzbSxgv/Ej3d/JwAjlINpNRHnvQjHd3NfaG7z 7RQDZEV3CEPOkYoIBqPiWHzOrFF46uMz3uqvKuO/ndMC2f0gWaRJOEQmqRbbDhtYXopk+raPAw3s Lg0dPMowrnyiKhloqzpHmMvQasAzUEQDjyQFKzQjotlULhjiz8fC2Q2sbe7DwgIxfqSm/KgYC9Al SF5/mYDnvcs/SdXf7S9asCtd59A4fvb4ykq5RX6m4pScyX2X6Z8grG7Um6eYrAzX/HlLz1zqRV7r WBLV2lq1VGFh+POTvZU7/32vDC4OwVNGSGIha5O+DeKQCSh+u9Z/bQo2TpLMLv9R+nI7lz6Xou0r 2Xno2aS6ccFviFBkGgFL7znIG1ggO7NIFV8F7w423Q9QHLgEarxQ+FyGIHrlZZtfN9rXrViwsV74 rooF7YjLbIHZO7EyZqOFcIGci1LR+fr66mx0m44LlBJ5KwoGohvE5WVRv3+weMVX4zvdJa7CeuPb 1l7IBd4LDxN7rT7lXJCqPXK8XoCiZlEtXQ8V9p+eKr/OzHO945+7JshuR01fp2eK7/goIaEmTe8B 2oLQnQtzJuP/rSaZtA470bNq7l2Y3KhUZ8oCe1tDPBExtm2eW+wBPuaG8j0IfofrvtHRFXxoyvPn CPbT+Rc9LIFTCxFczvZLaEdJ3kTRVyvepbl7tOSKByvuRt+NreEgmZoEQJMeV+YNJ4CJbd7g4LNs Mq+GK9WD0hUFwr+lEg1ogbQkrlr9MpMj3n9ZkEae9h/BkyNtX4NFD09VY6Wb2eIODMonNkslYFo5 BtcozrRq/EGlwCJsf+DkrsuP9a079zormgTtr0nDI0QnsU2BivHDOAhJoaQBI4IJZD8TpBCZ0iRo 0kqGRjuFTrq56RJMxFFE4W0c47wHlIgOtjeTZiWvipoYNqOi7/enYJHtLsWYPjU27ORbhg5fbYnl PLB3vym2FPkomcnCBdIbx2JJMecm/oXDrf7UG4jf/lMKqRb0wu6xW5vAwfXhCCNtPqM9lVnZEpAZ zf8BCjt8y8F04TWOjxYxIWTl1u1x4NtJYI+vekJ+KAzAW1s4dWd/iUjXXPBjsmbUoioKjnaWBhBu lHjd2vPfNha797Bxcrc7qZf7rCKBKMW5BTIUTO48Gc1Oe8FQvQ5uA4Sx88YBi83QqQkN0HaGlLPm E0ZqPz1EvwvdGS+Bs7ZHCuiIM2fJz2dhA7tjXzEvArznI2U5AFGYUsgoNc9qG4OD+XRB8mn7u3AO luDlyeBtmvNnyaeIaMo6gcGxcfAFZnN3weOyruaLgJbNbKcZ96f8zKz6HTJw8F7Upt2VpF899ULL DJINfp5XF3PJ9dEivYBWioXsR6Iq/DvnzIibNdrCFaekINwVQwCtlKGYzdhV6HDMOl49U/vWPT/u BeLhMODHXmVotdhdW0dGehO2iwmURKhRWiKPVu3QC51bKB4KP9t1NFIsNLYqCaV7wjbMloSm/LOa la9jTx5AnPHevF8seek66ggwc2WBNxrf01Kta7/Rev5P9APEMiAi4GhW6fXpgq7goxIONsUEOCYd SCETRkRm5KNYec1x+DVEcZJ5ZF/h1IlzXjrs23BU6iiV0gqCV3oVFDtJj0c9ZmXGQ3JrsOKLkvNi vLkdVn4hYF1F4PM4ZVsLcxK04GZ8KCx7eJKm57D0YEAFz6Ml2SM4DYWKGXcBixIlMHf2A3oCH5Wl W3UxSbXZnkV8bnpb9NUM5GVfx/RGoBeD7CtorWKX3s5fheBwC1dvVZBJk1lpsOrVtEtByAQLMA1r +muDqwqs31eNvfVROgnMjUkp3Jjo94JkGn6xmqZc6GsVGAGPH/WCynM0kxUl84VxdtxUxEG3JczN 4PikXfDvlaswhP56tB/fMzVARDGRJbiMBhygQCw5E7MkEiDiSJcOkTyNebVr1NfrwZ/1Ac27rgLe ajwLTIXFfGIySNHYAGX7XezE2tRpjSOtFpxRPqQTXJKQP5So3pE1jPSV6B5PRsDkonN2UJwr6cMj woL+9wgCAwUXnsybfkOO3MAkhhppAI6wOpXKKhG7HePgA2TNRq5lrdMFpRLC66jNLC5QU8rshCVO OFQr30Pg29xTn08lJY6rXmlaSmr4lM2btIMqWRyh6vjJqfw3qN/W1L/qltBfEYnaWi20qwjyfTy5 kU8NK6AqatHg7uRZPs0g8ulqQ7xKMa/RKUoStEwOFOj4lz52kiRSzcUFHIaLcP3jYq0QaTT2deOk fXEx7nXRKfSsdnwPXJNw42tt8Du/B372Sby7wmM1Nez/D4vIzcbMk1jlM3VeI9RY80NN+q8iuKeH CHArRrLVpBtHZG5lrRElEd8ZQoRZ00xpGTrWcrdyXG5G7F4LCgN6F875DPI5USZGVnpVg1S5DM/v +s3h8kjDVCOq2Wb+tdarIdohPMcLmOe3h+FGig8SSzc/0kwi8o23H4QYYUzYCFWdICtPz44vA7Di 8DOmYTJ8HK1I5d9GDRzFCeJKIgRd/6xVp329t8Kqql18UnWQKWXHrkidkBeURDzZkCFr6v6bINPr XNroX23msDzd2jRd8qq/TidjIraulkb1cslBCIHmxGC5u0UByzSt5X97li1ayzYnexbGdUYLtgd0 Z13ksC7kllUW2bITLWvfPKunRYCAyCy014LM2LR6MVJO8MTxraKplyJBC7/kjQnevz+3hP4AUgbw XR+GUdm68GvxAYEi6+R90aIiGVa19ijhtIfmzb5C6kg9xOzjE99u5qhkvxvfdwJLGBqea33I0ij9 /8KNRwnqIvTS/ONGFP3Cdd0aBM5ixPnPVkbzPhUazKEJjd2KSgvBmqrbDCEmp4LPQ8EchEGLmyVH Fe6GfqyoiDhpm/xpt7aPKq6kV6QQH76ToUrhw45WqO7I++rNOHoTXtyo7yivWDt39dcJA8U2WvDu D3e+C2COQcGVTLkb+VI4/CgQWO3AuH7uK0myTc8EkpUuDDRHTFtitBkv3CcZp13D5+5spmpRV8bk b6hnNbppSsX5+cd/8n0EOltgJeOdFQ8NEC7B8Q/L6uNXrnrSpd0J+BAG+cIF9aIOTu0S5BYKMWl6 eLfb0KCTFsLVUKaxMspWxn938NE92ynKz6AbQcKbCQOaN0+7wrbIS7Z7ggvbH1aW7oB6j8muHIE4 reYW+kJ1JVX5Dq82BZTKvyqSvGbi3tX1LisQbxdfnKAs1kQhC2N4d99zLl13agrQQ/w4sYG3nAai +6YYccYTmhMO0HR9KNgpZPsS1KrSXNz7JGDrACz3z6fDfEbCozLRmDOgb3M47cX69xT6hSjocf4V Qp5LFRGef7gQddN/0SM0u9N5clxgX/KkVC7wetLQekPy/WiONzJtrE4yn8EIHso8jWKFj4REVcD6 Q58pFHQbmHIwBKxGKbN7O/Y4CKKfIQIuT8PeAq/noFsUAaNN+4NsvoHqGx4wAcdN93XhAN88LmIR 5zwkzsEoXSZmNPRxg83LzLWQzlpP3xOMz67u2QMJKSSaNtpgcnuh2jPfdUzbiu/QTcMYNsIU4Y58 T3pKosQZx8RSpFozelAFSsStRzpNzY5r2YYcaEurkc0cOIXDd2gzJD7391kH1vuBLg+mJCT2bWm9 zKylEU9yIlDJZ9x80RJk5i8+o+Q1YeyisC54xf+b8GKwJOJ/s/PGVAP15nO5A538CadyH1KH9EHO d+Pjqpgh7ThjfjQg3s8C3enIBeNIEn5gEJqcywVVW4JRpCFfk34A1K9IaOIAp7bbNjX0WE96sn7R mC1vXqckofZoGPNkbB15t14u53LfFBdr7l5mpGBtIwztPw+RNi7Y9m0wRpT3hsT45x/LlvvmX16l ive49HDW4OuQ0/gsafBLldDkltzFRUGrYLB/RSYAQN3sCXX+OZPbI1vFcTx+OnNevLTWtxWipBxf 32iQEN8SzoFghyYgtR7+gunLR3tuRoQaNPTsH7cTdxwfyfRIu9Wv0WTsCjnN+Ymjk+eNsbsoLrvG 5JrF8Zacv/bFoN0JYpoAdJhMVlPPHOGk8xh88OKxvJi0SLp0uhfSInX5tcM20UwK1nKiddFKgOg4 q3XqXxiWDyt/WYSoEB5f3norTULjkOi08InyMYXkrjpzeUVGpvb1z6uxMmhvr65uAIyz7jihYjJA mHolv4UvwNlrGNkDrmYk5nuYHKv0CMNRLd67h09JHLtquYr/2sNUnU8suI/yb/htOqnBtAGyPlkm BpzOxaom7Hq65gfFbV3kkubYG8lXTkxvnYr4E62QRc7lEp/owfWd1ZiTFqBQ01+87ROSzPQtdOOp YAREJCKwRyLpXGrthz+oYW2QjYU0K5+CWbV/UMX/Zrb6v2lpgAeEx0OhtJp0E9ryVxUF3fpRL1R4 sMJj607FSRWi9fwM6mg7+kSYKnTIsc5YK+8tYfYdUyAXeSvBuGvkYvAw2OOTqrnt999P7KzPzD+D XqJTbXRwnVJ49vTZxb2d0hwfGevdFGGCLeAJC935PAKkO/5ala7b2I8qDs71xaVAP3EXk4DntMnh gqsVtLkZmelIush0yfRGyx7l7MGUFhQ4UJBgH2vIvNow9U3RYHWgdeBCzY4NXrzDU/8oPTKW5iaE e6tzlXlSzt0P5o9Pv1dzM41W5D4eXDPavbHr7wyYRDPfcllRG1NoL4KGCySaswEvq/AUWj/if+/H pYxJzTMV8PrDdsOwo2NQCw0+9TodOnOxXBDARqyXIekNjs8SeMb0+IibX7zB7y3qoCOQEUpSO9aM OVFpogTV0R5izrmgqQ5XuP43yEjjL4jSEkINT59ZOlBwfaiOsluFuqV70fmoc1SstIzn4xYO/ITd Df5LOvF9/RddqiDbOcLyahW2TrzeF6OfcfxPZIf/xbWM0Y7pxZyMjJ0TRpQDdTjor29HOIGzQu3E 8cL+8guqZWhfrt4w7D355EGB1jVf/SJGFRKIhZGtOSkrUjm8Xt1VvM8qyEu2GABnU6qjy+TV6gQc 4NlhP1HAcE6b5TqwHCnYYPxmxbuyATM2ztAoselh3hz34Jcz7LqQUeanOs+7Sx1G5ahUFHmuIRI3 OZDcPQI8N8LfFqg9JzSBMu50V27pUfIyC659MpTuulfwiw/N5myOYmpvRBHnaJMwhD7AGVquGOAd daR6PPrvLDdgMWakldNHZ+c5f79Tim434iq2ihq52xhnhUeoEoQkJF59/0BfVN6Jpj32xS+qTNxV o9dJn6ckzamKYHQNBDzYKfP7/JY0Jdk1CmZ0JHrJzJiVcP88FxnJm5BXL1I2IohVCcyYMRSQRYZv 2nIZkhmhYfudpZvp4ZKdmyXbReHR++wV0TbeXg8TOfztpp0sPXHRsRFhtFbiXznHi/PbYuKnpNjj vE25NjW8z8c4VuuEk9/tuAlfyQwtYmTweS/99cuaagz7nj6zZRLBGI0uoLjRdw83UeugCk3Q1Fmv 8z0i1v4lfKVVUQdHIv1ocH42/fC0HY4m2FAMYNBqtKJcA7D/HP+qmkGnnOP2Q87KVwPXSnbHYUnL S4isgMcZqm66LIi3hqwV7hrvvk2N7QRe0DJSwxCkF0yHbLgfu9DynUfeQ5SzGcSrwswwXubzbtZQ DRj/X28POsbaVRJ1x7xNSVDPxkSGoLtvJS7ZsNxuHzwgBBh0aUmVMLUJBA6Q6vrh1gpFYfDYNTGM 7vuFByAEXGAsvlAmuKNhjEZIrKDdib564lJ2E8/h5JJXIAfosYHXzisHg2iBTWhG4bBfuFwGpfnS aXdlFXblH2a4NpeVfWdxin5CK8f2Pbt/ZTJwY6qgd2yHfKhkG73KURd9fGmttaFHfFNfKrAGmivS q5m7K1DoiMA/COvqnY/I75F5JqZIao+S8g+PIG8nEFhZ8UIx3l1Qpcpg74VPUu0glUJrI6tmn29L YDzXXP3tC8oQMEfTNTHhiJPSJTppXQ2PU7Sn+bcORS5VPVOsx2GGAtSDqtvxEB0r/f11gZvnX4HA F2uE25KSp9zSzYytzJCJbTFBq6eIeQ/a1vBZt8sB0nBsuaW4ENFHUiCmwU0PClWFVf+VoEj3BD8u VTI3ZfCtjwRq6uDYR3Hr7ptCfNBcCCOa/grncQVyZfykZREHn0ymb0YuGThn8401ZHLRe14TDNIY hngZlFlzZgN5jlUHk3x8KqI0ye1G6Je4wEAyytK1+o1MUz6RQb8Fcpc4+SiCjeF525cXoRlNdecB MOKG5Wa3jMA1i2w48EcoEEuHwHLUuUePpg6A3BOkourp7qYaczxhSEwS8kuM36FeQD1QFDHKcJ95 RUm1AO6I08lt7STJiBotr4Z2sym579PSoKxIlZA6wkz3hef0ejfrQLCrtgoYjnChywc7hPUtRXD8 QFFIpGdmFDf8240WJZ2QjskcwkM/AwDucziGYLiJ/vnRHzE4AItc+9qV/WOKg54LANa2tP9MD9nm x6XYsmUGR27BKwDR23zA5wLpgq0WdpaQ0G/O5TZJwWwshoJq641SXtmirbPmovjYn8NTN7kqaChW OEu2t+Fog8A9gsBqteV03pX7mJPIcWacQFsr4Uir2ioMaf4DjOp9CLtR1xZ7qw9/PI2yd41I+IIW /FXyZnPEGg03JRLyKvFDek+IlN4JEAgkypdycHVUBbQuDDKDHJd5nNVyUw9UCCQ2kJ49X6vxbwWF KcbaotfSJDUL0mz7av9wmWVEppDrVLrrcZtwsqD8MHUHhgDE9Zt5VxoO0suL8jum3zh/1gz1J3pl 673oizi6xHY1ImIEs3I58A0JSr57baRXPJgEkajwD15Kk5Zd2D6+bv+2xev1ETQ+VKfITaq8Bzs/ Qw/5j45AG31rLkzPVh9nP7u9smKFso1IpJTbSmKcm4XY2ouI+34ZjQ/Y7onXQVuO6DzyXvypLDzw c6GoafBnar1lRBKBZZnJBJnz/FnAKUQ0eiwu8JNMnYfC7SVjCPux+KYEeKPxL3XCVUXOAcMMcoMa 6uYv+vG1XPhITWVVXvyRunp6n4sZPXiUUM/Pab2Vz7oXwCxxb1K4xVCTGuLtvxBqMoSpgM0CZq39 ETOsRfq/53Jhbc4dQ+jJaNFxBFxdrJ1qQzjdyRNpn2DpxXpQsGm60d/ivU51DQRo/R1vN7g1yQE5 rGhBg/Je9DaoDlTyJbTESvo4OjqqWwEYjpMrs2MPPPNtJ3z/1+dF7vuZ22f28oEnIYmMdd+Nlx0/ zzjO2BYWqPdOcfkuWnxlHbc2t72B5Co7SSSfr5fIxxW43yzXxNQhQ9Ies9z6F7TPpY0+/Uet1cmk RGIG6bD1/nKhl7V/V2uYM9yrsWAElQIOGrqph0sNCBuxecsRPxfrbepSyEWlv1XaNAc01d5+3xwP FiHfltRzqzVCWfw/u6NRYorP4j8FF0AiOY0iBQVRzCzgiMtYo/5ikAdtkw4Fy/mcTAWg9cvb6WIc TKwKJ23rVTxFyurWqbA5sji7/Yx8+b1Na2Jx0LNGNjn15wiowwBHtw2PYJGGQrq1g7vPCQBtL0/a LHwiUk0vd6H/GgFeDxMhgJQafV2oxip2y/uR44yYfG6V7TCiIRfCDOr3R0mPNLhSRRPnXOiyfwJQ 0qmvhUiehtSCDpiBWq6rUYgRmr6FP+UlyxA+WG3ApD4esYnsIZrs3mi4hqKg7HEIr8pUrIyRfs4x xZ8jxUrrf6prdRGXM5HWJrr23DeAQdriRGX0e7j1qWpR/5+n5/dilg04NqOaGCYYzFotS/Zbatc7 AxyntAOkoweO+yMaPsQLUuAG426bMwG5JHRAkDVBb2tfoEaZbsoeGW21+flszSvCEc91trnYz9DF Cfxb/6u59No+dov4483JzcA/o3VqJo1i1MAeXPpcPr5c6CjhK9RBga1YzKcl0jgieFvpsXrCRQF9 UsZ0MdehMAtiQgYT9OMFNR53dHp7/rhS0NF+00F8crGM7MWAqCdkZuwX5WKu2bbkQtKFzdWS8iS0 kmLYO3UlIrJzQQI9+wKis+vQzngrRYclbBhE6wm61llXfTDC1aVJXP71tEdW4bjQ+8ttGZjOwP0S LrwQwBJBPl0KmYQPkuqLAkiEwOCqjT7rAj1rLKHEr2aaUsOXnlcMwmM/rfXMIXIiTYeESk2vYOJe 5d0jXkyIhzyMvQ4fUSCkl9J5YNADFK1kXXkcpEJTEUWf8r2TEQ2KWIwzDBLxrdMstuR/OBv/gnbW qrIxzvGj+VUoCttuX3txP4v/3bKucUixCbv3wVRC80INJBOIQVgeXDRk4FMbUDjX1vNeBEknuZ5z 6S9eR3CTb8z313ZRfa+jtWdVdE76qbNs3shO8LBbwi5rxCimOFqVn9BUiRhYCL4lSAMaXrEEShS0 my4Rp4QdNn1Aak/ZYCiSyc+U5JNQj/Ou+W8iqAQnma271s6w5W0iY+0mPYP1UEq3WlF/WvsV7FG+ MKaqMqThgIRwt2Y56Vm4ajYFZCBR7X5bVr846i+be4iECdcONXsqP7kaDSFQO9Sfytld9Z8LbqJe DanH/kvCuEEC/4M2vm9WKiv7ReWXz5A0MAhfEDt/yREtUheQZbej8dWdW5Z96FAyrQK0znY+VhPD Txfn9hriYpMF/AQI3YP0HcPWzPmyGq+rR+ANr6up0QcQ9oDXscfGf2DPZmFwUugV9EBx4Bm8Bxk+ p1idC+fc6VjjHrUi8n7VYwt8PutJP323BUA+v8EAhYLfU2RChQ7Vaw1S0Fuazn/nS6VbW6LBro1I ODL7iwIxmR5KhfqL+FdEOnnkNCcEF5KiOneEu+b2a9oexboVCwTYuOQr2qK/qXJ++T3dQSsu8+fm mtGk3gIFME1cUzp4T2Q6gj7cZRzH543MsDGxRKw/Zmgg7rqBnuDucDc+WXtgPS786o+gmA8WFKjv lrxFm3nrOuB5ihM+5+vTT6qwLnfvuxdcrzRP2GGB85jcg3kihzwDNjI9ABwG/Ddef1S8khP5BwaY nTjxfxISIUQ4VYQajMbcygbht1rCrTF1N48cH7j94KZ6/mZrdvg1mosj06LM1K0HynRv509peCfr DMpSqUtlAndyuGHaNVW811OB8FYSKw2iDnhT25YuCzzlpJ+zslJq4RgbK7FX/QFEJUyh+g+MSjnW FpnyzC981DLQdgrcXtn1Sh1Mq4mQDR0+bgUVpYDEep7S44Rcl+E6w+s2WqIUqh3RRU4+QHr6lyHe lq/P9p5SNz/4pE5EuS+Zy/wqwCMIUX53dy5Mnpr/ZM/2QeiJl5vyTrcBwq1eDLNyiY3zGepCwP+d vFxI0eBLTIPCxkAj4pzNJ2QJaEjaFXAtzodLloNFA3FaVrxFZ3Ov2fxgFsEezxl3FFqTsKipmrYb N5kA8gGoBOHx2bpN76Qq2woBEiQgx1dAhiNiWnhAup4/DceMJgmOo76peshL7A0FfrUJKNHsdpg7 x3GQUG5h6HqKHOkQU1axAX3YzQEQoLM1coW6wRwVUfP3uNLfBpXntfVC3S/FgmIbFHawuBJ0mDfF gJjZn6/+bmOfjHusmNieN3X4JAkJLDwR0hdhWweqMwCduwDK7fikwTd3jxDZDMrHd93XXpWrPgcM nNYAXf6BCbGVujLivjOGtwK84lMu25VHbph8o/GCy73UhEtwU7HiBDrf9KlsmQapPjfOXIRQG/bC wm8kZOTRzOlxqyVzzL/3GjMX/8XrtrvGa6DLpcsQWIJ5+hJams8qYrhOhJozO54LdleoCLN1GFE5 9KLUjwzKTzFF3RGr7sFopSn2izMcWrcsnBlnQ6K48ZNwW0Xhj5sBs3IpvrPCqVB0jGhTg14rA36T SGjPJc6RmcKjPhSJh8v1odScp+LbHyw1WiBGXowh8V4m6VYgQg0h/QDTT/SCnEzuVeqM3mpWNSQw iFmNa1qdYqpTR6LUZh0gBUs1kntPk8jt7hwkUFhQZ9AXezeazoZXAXCRxIGdaeFk8a0XGUzOoqLg xUhOlYO1Ogj4h65NeYgCbUK4kMt1iP7HY0JghCtJNltIbY8lKMoADIPVzkgH1psPkvaK6SoJarbw mfKAWtMUpD4nDWA2RiRpBEQjTgTpXzz8pk0siNVDvNFX+qDiudIGPNr10R0FYOrHIPrT0Yfkdzuq 0RwrXRQF0kHYX04PeXekFuMRWA6ENTrqQtCJMkpb7z8Ek2ZnMuC3aOumLEgnw5c9iWJmLID1/3fT SPYhIisAkKznEaPKuoX/gfjr+JBirs2r56T+AoFoaFh24dprRJdyr+EupE+XjGN0HtENPU+KtWPt JXBH1/wEA8PQnUXRDeA/5FsiSurglewRba3zJR7HPDULLVz6ZcKLS/KIuDpsDZQA8GvKJuPE9pEm p1iHvnWPOr86rbPn2Yf/DkAsNR4RKr4Kz0UGNa6Pzl/QzZ6flBH4WmojwczIgocVZ4HENVJrINWy gXhQzKDZNcCcGcoax38DVHguFxfMOfyw7qIqvBq+7yBp/jo+w49r4+x2ULWCLE7Te+EVdtHJBB5m ym9pmfA+dw6qSGG+5zstw5hs9MYzDRHfJFeqkTADIEwk4AJG5Rl7WrVEpSfpfsWirjKAxXzuiOO9 hkZ1iLXBzjdhW1jEGnKI6JvyzU05dXoK+sDrYEcZT7mYRGvxeDmAAEMnJD8gj3Fk4h8iYo7sUvN7 9VndI5TqDjbm+su9WaUWf6eRlmB4Yv0XFjdTC3jffOroobRTgtPx3lLbVpQdoZeAlSMhRBzHqr8R Me+n1OQAIfuWGrSxIa2CgIDRGC6sUEPVMZqkp5o3FLUtaX0MdsVhcZDj5cdDcZIj3KogUxRoGnaL GATUAloF5K+8a/RdR51gw6nKEo+7peRBTgXXba9B9L3kMOBDb+sjbDA/5VgumPY2mrdZEWnoTcub idmjm3M3bV41NlZZ8EbTH2UkXNK1HnXfBQsDE5vfFkmhERGaj/wO5yVliR4AvoamYm5FTjUfNh4x hVkciYaRllFpsQtmXI6vgYCF254M6YtDNY9zNgf1mQI4HYkI0YcOLvnYMQJIw1rzs+0QKUc9Ex91 VUbDLhRc3ClrvofZFdIiY09sAcZLW4LAWgJpslsa/+0A5Mqu56dYYXTvbsITlE//VxvbokWLdwpO r6pFFS62/JEchLk8TiQB3I9W6a3GMgCCtyrl2bsB0XuZvjNU00zngcMm6dU3VxAQiy+dGXEzx+xO YG4tl7WAP3JYwV1s2l55pPXBk5QOOafxNGPlTPO0+89/eZOrpFkenOlpixLJ9D2SNIO2KPtsG+g1 YUGDTZ/FLpYpXCpxwBQhvuVvCVLtjiqhYiHG8SbZD48YBF9G2GF8HUhaYlJHXCGgRa3T/M4FLUZa ZnxMXR19p4G/XArSg3ZvVN3siTK+jdkGqfuo4pthurq40KDkiU1S2mrJ8EtNIuUfSaxxaHnvUxZq +zBGy+kTBO8LJWMnlpwit8mBDskDRKUiuMh1PV2K9Ea9c3KZTHkcS+IK+RHiBK2/gt/NSc9wGHWB JfoptUneYxqWQcPaLbDsK9GgVi6t7EwgMxPd8xQwDMeLtNivTbBCyi88AjaY/vegLZ7iJGpDqNXk yfTht+SMO+/onQ0eOKsGHU0QhaMbLPnj4fWHGHKZCY5cWnDD/GN9bh0ZerXz1YbFUxSk2siMwXXZ uP+xLFKat/q3VL/86vV0bk5fLBoKxU7T4/+ZX6zSbUkW1veCBMV+36czuoBUAIYEQdNnaBLdGmL3 pzbQ7UD0j1EJF6KFmxeAmHCbxSYM1rbWMvvGHCH6e+tUqf+giQmA3coaB3Ho6F0bbRsib84UqJL5 IFoY8JOLr1m/f8aEV6EuCL/2u+TgJE/KbyjRgLIouBpfK8o/0C3hcmooBMrPpCYF4pE6DLxJM5qq N8rjMNPoXE6Da3nPnklfSd7ihyophPqWHaLvgLcaN9PsMo2tT8308uoVZ6weaX8MnHkjY4YswtG1 LeVUAj38zYsNSe2DRsGWiWTcwDn4mbYkb8MudDQ2dTaufGzt60yn6qjsr7AoXJR7rcDtQEP2omLh IDBrQbc/AG7TpVu0B5TSs7MeZ6+Zp+w3G//j9TB7+e1qGWybr152h3L0oirta2HUHNIX4W61SIdE 3jgdStN4zIEXAx1kfXUf03MaIkK5kZbbXuwiWcv8l/bzIwl7EHG/qKRcNWf1vqmj6l9f6UpjMjdj qV9YT8jmla1VaNxdMJewLg3g9TZZHowCqJYz1Z/QPBdwYzi6El4UBhHjCsqGm7OF4H7CgEWKqHB2 TqOjeNCz76H1MsNX+ZyCRxj8xPYD5J4tA4z/Eac9ToFczzdex4iNQo0ET9PlHyLY1Lv6V5Fq0uLh ZhYjNoZ9zrYoqgJs4zmIvXHF+5pUYCDzCKkb0qYastX3ououQ3R4Jbhb1ZZ1MK9a38Ii88Iqr/ra SP9qeo0nCyiOG6iObpJVUEEi+qAFREgPBEnhARHyZpmphaDsC0T54InLmWDLDQUJcS8Zg9NxZPWr qS1Z6dr69GOz1ZKqmgNUXt7FnUVx/MWqjjhyxbdimv+trhPC+QdCRDbp2JzAsJUs+a9PBDpTa5lo xKP0KQOGd5CjXVRWYHXm6L5Cis62/3OqOVrrekMbxvqH54p4q4ba1UoAif4NUy+B4xA6tIjyFTZM 168C1soVdknTgIDQc/M24KDfosP8in+BshXp8Ee/0PUFknvM9TRrVIdFQKJBE2Zg+PT7UHGVFaqt 78g41qOwf/v6H9lebGi8VCqaRj0JV2t6a7FsJJBgDcFctg3CxPETygus5SrpY1hUG4ZiH13WTwOI eTfslOALnhz7cBR9M23hy5br123gZ06vkx544ZH2MJ1DKygDVy/BM1KUQVB8dUzlJoieYXK3Qsxd qvfrJKfnTcwf7myPEGoNaLWUCbRSqRZFKUTnqJ0IJ/rf1DSrJiihzgV1MIF6kYZgi8SXZ5mDkEUq 8BCY0aMXUnDEkSTrGNttuFSOmPoiD2uM/PvArM3ezn4SZ75s30TWXjrVbIj+GmYmulXY3utZwxJZ 911zB020uVtrOnQHmOb1HBfz9Tfja4jckXOS2vbD8+Gb6AF7GPVl6HUp99m1rMzelmZFH7jjga9u SxNWHS3MQ2ZeB4brWH9bvAd1QimFVqW1dTiiDB/bFOT1XuDWTGIzhSkXM1pDd0qpq2I0oABPjZOy Kf2iEdnVM48jf6nVsGCV0JuCrjfTSgGD3FxQ3vGUBRlVjhyC5lKfXR9tvyNQq+FVdG3VzsXKq0JN 138+dxEdB8yFAq2HbJ30dp4DO5XFhEfsZjexd9d6pUbgg3T8gmsikqIOLD+z8ZO4IyKoxbbBnhm5 ScGMoneTxvVUJ07MTeXrjaPeHoE+c++/Fdn0XKlV/oVPXMj3rFJbUxOhQDUjh9DuLxTp7Y88WPCV Ywui6KuKWz2u0r/aLsSVXPUtlADAgqwZSYqnSrfSnXutOOeZCMJo6p8hTIYe+k19K2cmHnnBqlA3 tRa4T1PXQcmHOGdRzlFN4JSeko7VT0I8IltLYro/0tm2ZFSq8HcVVP4GsaQi2nur+sedqFXjNDsB TwEybHgf160u2J8kTkmLWloECeUzFny4938GMMm1pso1GsrNEBI5OlGfqvRJNHwOsYYMwm5tujCw piz63hSaTcxyXLI6uJVyPMHyE06n/q9Yi3BoLV7kIeyDTLBhfz4siY5lD9P+tyiAbsyYkvrx9/Mw kykpSFp0sQv5LOkc57cPN6K6rKz5kTYyjyCEq1ncDMgQ6upkKmIDtp0CCCSSMMNpZV1qI5llTSbW 3882xlYp08/TxMdvZLYBFbUNPcrpSMUWOd00USkEbYkIz7EIgsi7JrDZx+udu6I2r2e0uQX8+ddb jAyVdfEuyqizTaoyPAvYkWGQleKL1mDKvTlQ45JQYRdZi3uslO6s32+bu9kyzhrGT4WVzgIKfSTF DQ+sfcA1mkW9ufBwfZWkxBQmYBZMTbgpa4wm4+i5Zh2AtYSzd7FCsPVy+hoFbLrmkoZK73Hc5O6b hwQh9jA224W3DDne7xQ9ha58DsnHNcEPBaICJVdDXN2UvDpOH26QrwqiKIVj4NVffKIUVTRqi8Ci wsT0dAR46h0MtS1YsMBqWqOWem5aw0xZM6icGSXvHXyLvyTNd1HoUJm2RM+6VMVXnpACn0qjYE0Q QiOyarcnCeXU5wH6ktLGj0bQV8vrZvLetOD6jMgVmnOMXtsziyMiut0KbQ7l5HpxrozYW6INXRif SXEvwg3MtuhQt3GwmDJDBOEZLHsK+bK18TOyzpAvpvupuMAm24DM2LaO/koTWy3W7L7NoPYxV8FZ EVFyy2zf+AUcNJQudnXplP1ezLEebVo8hHa9Gl1xjRgznmqxBe/TtEhDdNuVl0hVTB25i+3g4Ka7 bALkrmKnQGXwOkAqOvUMwEjPMXLzJ2P64mDKXGTogt2sgP1OzGy3pB/xIrBkHRtsxyoX82+rCrtl GrMvXpmBHJ16E46ay/TZA3M2EF/o++W11BNaJDOG/qDzni+QCzRxQypWo7d1kmok2cmax+ER7DNN lcuF+/io5k+7qawlCQQkb8gEk48O2KRsJ5srEMKkJ4dJOsrj8yLMJsVitTciUmdeaIlEAX5Q3Y3h XuTdI518+2oKFC+CYOxviHIONfA6j2ie9aWbCXGMr+dSZXUQldoDXHmLbppjBI2Yp5Gu/hrgvF8A d8+WJ2RtxZQrSCvUAElrFY6CtHQdmNZd5iamg8r+GDDwWEZQ2w9srZ2Dq+zG4I8HG0TUyFC6khjf oDxs5mrMlO6XYC8fydN+hbu7QJI4shNgXZVe36dr5uiU/QuddmtnnTt1VSdEKlBp6GXPtZpHp9es XGPR7S7JXuhfbkwERnNoi0IEWUl7G+bzHDESFqjYK96N9/xXBSh9P+A4HLfoPG0tO2DyUeJY5AMf 58fv8zcqj0ztKDiweKyvrEuFR9cPfuleULwuGNcQyo2sD20ptRYKHIAi4m1CluRlQCaMvq9W0V1j hD43Jq8ZWuewgNpS8nt19FDj7qa/4f1VcHJIX9f32WLIo4OoMEb62G3TtZEXMWlRgxCO8QDZ3jUl I3iPq9+nY9o77DQLuEFSxTVcZPe0aPMmIghg4OoOt8wNIjpSh/mvm0uhj5HCbY0WThqrY9himNE4 2gZV/PHLBF+ut1IIqzquMmNWUSTDpTfQxz5QqElWNVLBt1opvWJJb/YahQN0K4qRudMXs7b0lLxX /au+H3AyUdTpKsofeBGpwSKWn8JWHciGUoNr5rb2wEIlEYwpDHArmq9r1Omz6XA8mB4sd+BYdSHB u02nZ5fU6JQBBLmeSaPTGSEyBTVpKdFagf7uG75/SwiY6ibLnF2UeFHtlJepAX3Tf7N6kddy7ALS 6ttbUFby2nOYr0dg/8l1ZV51hx89qtC4qLk+LJwmV2vqiUyaNi93iorRy3zD2TSf3V1+qTtX+J1o 0RTqa32wUT+LzAasAPUxz/LeF+cK63ZfLepkcpTQydMtv807XX44jQrqJazQFIHnr05kXU85Jdim Ns5e7jpuPf4VWRUHMjDyBxePIhIKHCt3RZtaenRBtfskM8GjbK5nXoWFhgNR4wM5NVYzih8aiMTN +NN3W5qNGiHMcqsnLaNZf9QHQVY8kYEsdx5ne/PSlhAtUUPcGQTJkH8NlzdN97oWzZxY7vB+CKLc 5exlDE+nhjjrkSCakN4Xw4dSfBcFysHjQZg7kHWn2N9hqTs0pMBEC2zmpXTEtY/KTc5qztAF5fGq P7HvupkNC8MaAYNK0+jCrDbzGOpE0geq4xw4E+VO0ggwakMBqkr11GZ15yjwzBeCFG91/nRhAoHh WCyiSlwnSa0JRAoWVb6BnBD4xjBt9j0tgAINRraiNkWjCrSa3C+FkiHNahZDfNWIZN05B/TVArzQ bxfuH5e9EbgZz3yixPtidtcPrEvgubWCMzcXeh3kB0iPNox1kc19H08UyNE6AqW0bJoTg0X6v9v7 ZtlIFsEXdW8RJo0qWMS77O3RhongFxI3psfUxr3iCAz/ZgSQ9pHvhSyXpsfnVjTVFQ0PNYoLxJ0S 5PCWUKT0pLQGYpvEhFNLSBjsu4BtXhQ42QnrghbIl1ue4XPFaMgvrnp137b+d64eHU+0sR3SR9YK SMoDA0oNTguRkbnePgA+2otDMRJqz/0SKUUhJfmVvInuD5x11EIeFHsSurN5hj8Jmg/DY0aMl5J8 uK8E4JkyslcSvFcowY+eAvS2VMpWLEw/9aH2zRmuo7bpAYwgH/XNCJe8Q92dLm/PFBG69JfwC/3e 8TUkEg1bT6xIakF0iIlOrdnvL/HrITkLVNB4bK6PU9tFrJ6D88ugQfq0OcNp3yEpdFTwUwx7Ziq1 4PErhgTVMQfah6Fran7cCSgdasldVeFYzxm66m8c0G3p45Ke80wOgNphBPZ7+60PFNMnxHw7TD6j U0fPS50bkXOG9s3T+nqQe4gGjGqe967rrDasmaQ3tDrt8C1ep5/6/pUaimj/EiFdO9jacVHM3J0r xOzFkbBEOLQ3NHTydWfiauy8i30rbHYQJxTNUX9RC6FYdYv5ejXXOvAyUHyEEkMNArQMv8g3mnji J1oFW2D8oqeqseS9+ODFCOUvU4remVl+UoGFaboR7UKm6CfCcTLsQOWGNb1ezTJAV990INhGmiaF ejzyf2b1CzM5FSK8q2HCbe53eT+5wQ87F7ZFKlB8LzwM5SS8JE4fQgghQ2wfxSf6so/BMENQ9W+y BOulNj7hr1LBuBZDNhElICluu/I/5VjeP9JWmHPDbRZFt6qBrb/xgg4Dxdnxut7bhsGI94VS2nOI nmDyM9TuXM4Az21cymLLtKgVoBVW6wfQ+BX07/Cyo0eb2XweeOeUNkwBpi9T+/ezxzOPTx1ljXIr WtCrb+ExWqCVHTl1toACYy7IV7stCLpLwo8gCUytAm9JX1NwEDMSGipW5ljdtLe6rotHZaX5aq21 RF6IDkXqm0x4qN5jnnayebzCZPHTPUSBopKF77/nKPr8HGnLeJkGIiRQ3rN7va+TXWqh0puZrPj6 RyrHSKit/CX9HprPVZ6+fA3zmnv+vxZyptafPDogYCTzllmKm/zh9dAnv/dzDdPygE22pTmYu4R+ 12JQWFlaSy+NBQtA6MwaAJIC5ZV2/nal2g/qlvs5konSwwHqu5NcXE4vvXhf8ZXwp8ht/zCQ3/iI 7NRp47g/IxVFPXrRCNJEkR5yfsjkWSpXlR22s0ZgRF7h8gF6uYkOyWLo8K4FO4fvTtpTWOdi7jrY cTKiKfR+sRGGUsoh++C0tvOd/VtYv///DrLtrFYXk6J1gKXEe6l6TDHQSt11zgon2IDeCN2haCY/ 5GxD0hEkaQVF5mv4SQWj4D4GOex1GiTI7q2aA1DjSRYlUp7iDyjs03ZuCA+5dkEZ/K1Gdi44qfAI XWRl1U4XoFDZ6rq/lJU53h64WHsOTNFvMvzIFv1/nOKRMy+3UPKisk5pj1LVDICrVPyEsc3zNGUC cswuldipgvFIL4mD0Omt8z7Ro3VDq6baCArh8PZLec5yn3Gkwl0NePOFz1/A2QCxbWCo9xc27Nts BVhkwuaJ/9yezz/BnK2XSXOTqVjnYc7JCrVA4rpY5yFaqnKgKR2PIXmVjdCKY1vYHdFWakeAD2B8 8IVBWIOkv0RD1VbcgTAi40DxghZlrJzKLKmxe+OWiRQJn41HBQ5XNoUASPI2Ibny//U4fG2cWtau jXJ7hYcCbwnCldNhG4xgyC+JTHrHNGkSNNt5hogyOix11lETZKr4s+DQgFpzyqIKtGedIw3pFKIe F39I93TJyTz2xKYwt1xtqfzXtTwb9qyXX+W4wZeKewtbLbG2Wap3nFTQNubmXn7D4wZnkd8TTvj8 0kIXC/2OwAC2MUakB6AZONS7CM068yNCzgW4TclTobMA+sDL8XoObUUDndWW4bVR6G90JSryW6NK FXmxhQwp6Z8GwmQ1M0e6otoDjMtCQNpZsGSoWXkAxjrv7jgi7P53YJO5jFU5dDJTYFUpiyva/dQw jkZRxXn9JU8yt/AP8PDndjAHCfeivNEor47dfDcZBeiIYy57Uk1qnHx3vYCq+qQa3B9wb/f+Ojjl IDtjWbwYuHFUH2FQWcP6Cz1zMnTPO9yH02fr6I/6RL6enIjnH8bc1jSqy+k8G3O8qzazOsFb9P31 KeAZGqU4uLsP+nGas7bMjm+au4qZ2wFI9dhFF3eFDztnbsxH8rG59Q5Tm49dzZEUhk4zH06phk7k /p9pgFdXQ9kTDRbeXgBABgiGm4Par0edFyBwnY29F1+0S7oy9gorja9jhHLuBiWkCu7/s6i2wkIa F9hgQlhSx9m0zPEChwG1WBtQ3Dt7l+5iaVS5R6MzwWj00BaIJ2oTnKrCNozH/SFnIVw67x+hJcv9 qHVn4ls1u6TsR7e/Wkq504sOXB+1L82XkNDWWObxRUpvWEd/618k5dryT5lqtXYEeKZIvyLgoy39 0AXJfR6h/DbLELkSPu5Yo0mfNIPoiy7raYNCkKPNHFkEMASNyF5QPTdjX4mj37PgcsZSzP4dTM0h STW29ovkIXsCu237UHBztIUWS7gC3v8OMVYHkhnL1k7NKfjsrZ90nr/OcKY1U8yuSxG0iBT5OH6S m8wYTaFgah6af2VmF7KzhE8Fh8GbJa5Y1fnGU0jq35R4qGHzVHioM+O4oVFGG8qxP8JJbiR/rTCr C7CG4RMCs4GwNRjfkkEUfVWSBc6G5T+kz8Xrh9gnB6xylwT+Swx5nceRHaBwQYkHI/ZzpOYoNbhn JXoEgoAHa4BEWK3kj0v6e9NBFcJ9pXypfnLhONyj9bw190Fb2IfhWrSRkg0Z5jpt4/CNMFxUhymp 9LOoh29qnCuyk+K6EMx8nhnWrjkdZrNJBzBgSW53lfwRun5cBxsetfPEKd8VnQIPM/r56TtWNjQ3 IbD4TzjTdlxvAJck1IpmL1pVTZaujrhMXqwJazQNJBUWEXUKdBlyLaEeooT2qE4HygHAYZyvV1Jz fCCy5+0L51ynsvfBGy1NkRcvyuqKcliT7s0nwqOM43YSRti5xwjQfcmob2yRCALj4nh7zNHW4ojM OShYSDZB+C0EpzuMxRmhg1JszZXM0HW2G8urX8tyiFtS3i7JUGI2nSVLU9Nd2vMgTcOAE1xKKdzy 6E16hLcHmWzJ3UGVvyMtj7nCwz3VTjVCJKTp93nePJx+EDt0QUj4hgUz2mv0hX2gPf4pDAHintHR aduanv7VHwS1+pTnLg1IVmU0+l6hTUfaXi+KR6r9eI+bGV2Bn0vSNRRk0pii4Nd9aOsc0cqQ8Jz+ X443dQTyS54D4IjTI3Sd21mo1dtqXVhJo1H69Bzrl9rsWsx5zujRSQhWjU/R2T+GSipNCDwe2Im/ bTAeJ/5YDGzKlDPDC8XTVTcIwRHDDFsIBih0HCV8kAiickbMUeO2+5GsyUY1WWvKHhHyFfV6zA9v sO/kXXrH/WrRS/OAc+uQbF7JqEfWe1chC60/bwwomqQ2JhUB43Cw0zlU9Cc6MyaBkpSv3lGrC0fU TcuZsALa9urPZK4ouHxTkrOwNZAl/OchCTdWsv/QfMYUUOty0dAUAA67Zom+7h17iMXb4VXx3meu Y1JihxTTJ6darXK26+memPWcDAL77whnwWav7SQTdrUzcede8VA1TJ7PLrzwjuIHhBI+m+PSJPUG BA1L+9OOEOIONqAE2S6MrAAEMNyGoQJpG7G5kdB5pfjrTFKQroHaBaxHfWcK2AhDcZxE92QV84TR KMHJymSRuT1yyk/ciTSMQDSvAomvU2YRzo21Hge1pQcP5eimoQR4wslYWKm1vPmrQbbLe8Rhm21q IuV/c9zQ4JnjKGz1i68AuxKu3/nixs2z0FQPqMg91H3Hc+hLPzWlVL45jUrAX+LyXUqjfLWNFto1 4zVOfGGCR27XXn/qYeEUNN7kLshu/2t6Z91OILTJkLidNPZe57mXry/AEoORAhjL1/3tdyAtwGmj DbISNO+csOEQoy9piASoj95ul5N+NzOBSSMg4L+LY2KKfKULP6grdNQkjVqHW2bUJ6uvOSS4s9nz ZFesK2TrLVu5JBuGTUNgxey65NNOseFn1Ne+R+eFmkhYmSEjhiDrOtQPeAihoGiNxToWNoJoi0Q9 UzJMwjFRvI1vVcPelWA0CTv72Qx40nQpOH0YYnqLxshHB4ggjgKTn1oNgF92Prq96KE2jqROCH0/ jyGelFFDHTNoGG121plnL9lTz1dN/bpeAY0jPsGeQIvYMe27LQdNyhSUsHogpq/o+LLtCkOBKp4v mn103cHZ4Pyp6T8ryfq5N+JcxHw7NqMiz+8Pkng7SoMCjlyRB2/IOEKHXHNzMGoca3REE1TuaQrM gjaAGPrG3jfZNK9z4wXnJK0Tki68kFQXmzWgpA3bnopx7WEHXEMoezUC0OyWd2IHkarrvdtnZqQT 8Y0Xjf3C5FTajx7ahzl6ZzlBBV0pUBLwNtnsZl79E6b8EFE2DnUdSGaqDAY5pH6Uw2Ktx5jwF+4R jrdSrqiygkOWP1Wcs/Y5NOvwlPhpfAsu/nCFwQE0KOwis8HCucm17h5u41KMKRqdXIYVLPVaZUnW dFQb+qzkrrlKHDfhSlwBPPwRqZQRE6Gk1MZ9rpaBXMXdMy3wt+y7JID34u8+OrKkolLzYRhUt40A AYaPbdn+3xNI/Idj7Nu81CfxQf00LFHFlzkIHhyyrsNP2K5gejTlDF6gq2Vmi2WHrDons/Kq+/i8 VTJp7CJUsk1a9sVfYTjQr5SIvbLJbwNCwpI/sfdRl3+0z3GAm3l5D47WNeQwk8a8mdSA5mBR9+eh c5XWX2Ut2sD3er5btOI1H5O4oVWtOxIUpMl3/zunr1MUAfNG3NBNZPCd6ik90wUXGbljFAlg9NuI AlLTo6fieAeKoCJ6CX4SC1Noa7HBQAsm+z9cb58m5njlYCD5kYIr9mx2STYtEGeo29BXkxvOIMNJ eY1qLq60o/8Tm27gVwBpa+qq7n7h4cbyEMEoxyu+U5KrcCaB+ZG+iTFtAO9Xodhtvi4DrNvzNvee MfRO+b5RyN3ZMFvHm2hmsFeXBDdQribx+SScOTZoYp0gH80P2iZpSkTyhj/lBBhV2afEpaP5eXSu bW/Vpa9sPEbpaVOLICY4xRRXplqnzNJ6Yo/YRYs4xGiCLwb3hOI54/OThubGlnmZPRBER6Osrf+U lE5SIEpCf8gjWq7n+esZTXBlxgECJ0CiuUzhT/l+EmqNDJbQa9wby4HLf6zY5jNKoxycVirICeXD +UGxXyWK7tyJsgX9pWOClqoYLn+08osZ5Uuoifo0agWszzQhxEEo4i/gztZJfi/Q+5T9YcdDhrZQ /Ywd5UJ02W3bFaL3mfjw8nDJzVH0SQmAyYcHIvlL3EKv0vUUx9POOe3kTn4JXxXboRU38HxOkOLe gD6E4Q/0FYZjXBSJpOG8yGx3K6n3OkbhoEEnz1FtJRCfOgBcab1BWDVqzTaLrcItCuBuddRxLkP1 HEiZilYT+Fmo01kn57rto8FyXyzR5Lt4A7Z/RSH97zN5bGqnlTDoG4mFB5yx82nM+7V3QBJF6mGm VXto3l5wj1bydZ2dmjbiA1VCtmBrPUn0MZGxY+ZlmeHMelD75Ol/MCGhNjz8taq71fxTu2YanCMT fgsQlrKJUmNtxMR7jS0R2QYSeTOk1IeCf+JMuEgb2MFmQHr7xAuE9ZQH3hjgsFbbgvgcQcSbeqGg fsHtZU0SGxQdkjaNez+2ZttzmCViSDGexQE7CGFsMs0/2FD9XCcXeOTWjk6vPxe6UWShaoOJ6p7o FoySuGx/nl5pwfUYFZx7cZk028yXeU/7ItaXpYvlP8zpuZ74qB9OrRlpP4Lc3RGu8DQzxbBRwdqg 5fbfmOfhsvMnKpqhbVd1FgwGx3nVzNd0tGPv9dPmeZQG7v5PbLF//ANksoj/6JqKeOgrLkYhs9Mq uUUbgJjwPETljklJSrD7MORVv9+CPD3X5+/how5DOSbm/RdG5gMyNj9SCJxVICDQjRvpeaNvdFAx yLwZTeP8bktiYTs9rweXoqXUyB/e0pe9mZdGZDms9R2sxxXrh7U3vmH42c25x0E/rW04gxfuNba/ 3IEuBZr9YI/1ifv+jZZjbDnyMNQUyjk67607v0KAya4KcpDXPyuRKFFC35PpDC5HGYBAp8X4PvzA y8rp/7vZMod0v0lBUTo4Hf38XoBlOM8xA/E48QX4eOPR2+FFDJnfEGR19sPsA2L38ZiSZNwZciqe Bvsm2ZFtiaHW6s3MER+04B/DFhP+1QejQt2c7jh9grfmEDQxTwQY5+NgxWt6TXodxybas4GhNVdZ f/JA+0W3sDdD9nzcB/1xjkrtx9VQMTjZNN5c3vkl+z6TzZGUCMdeLpDi9SN/51ZhfReOgeXTCa3E hubSRF/hiFHCMYKACiklzVrkhPe9kQYGLBYqgTFe3RvxZ8Zr/tJhs9N5J8S3Zs72eL3H6yKmbETN l3g2V5wMS6FOm4Rqrzu/JcNE7EhRlVHKLFIRxW6HL3FHl3my1pKmEqasGV/Sbnow4uMqkfq1tA1I 2dWmIfUcWatM9c3I+6abLrm5uaOB/3O1eUQ8SUWf8zHayf5FSCdUSeaD0G4J5PiniLQbs7s/ccLa GJi05e54PjBYEKNozCWZPGlBhwR8+oKQHqEClSZUjiYtIRUCJO8PIKpCEC0vZP9+Aanx1rW7gBEr YXYmB8w8uM9Amw8QLMEgRe6xxNfGyVXIgPr57uP88T34ehu2FjeqngSRAnOrmFq3wvLbwjnxTf0F vCXz76J1opGfvMYp1WYO4ccxzSgqdVnSQzNp1i/wO5XDFWVqN+bwRlQC4eKoWJsI/69nzqVJNBpU 9M1lEE0aG0eJUAcqM2GAKzPG6CM/6NAk3/u0jGywuECacFs8jrNTqDcULfyrGkUMxLrogxSPw3WB pJoAybkSFUX5EAg/YwJE0OC4l1ZEIfaj+cU6uOKnrrL3KKcaHcyxfpg3rBW51kde9DLNRnY4MD+p rNjwqY/zj3tQ8zEMnhH719OQYqJut11SPMguptEc2qmw7wMmjHnEatXhXTxhAK12rMr8Yay9tMk5 bmAxSEACUcEIvzLl5srSlZJVMCmv5jvmc+C/LvuAOkkdfpg9y/LF8Z0jYSU5A/FQARJAas+yL0LQ +qm5r0IFCZI/yAppzLW5dbn0y/n0v1rgnBA6ZfauAoFdZfMVtm5NzSOwPMG91EemHnJ53TPjl8Un dmOVkfRj1AhIJUZ/gNrNOk764HsJS0y9LB5b7eKkNDIYoEjC6MAaIbBPkzKOEATe6JvT3iJVfR1y pu11pYWj5Mq8UzZIlF1V1/JLlnM79swBRSPvIo+8tScGR8Z1AOYXh3rC1yTf5RDLNw5+Vta8dEkD BZg5WZlW+mHc6ITv5jBjFR0/0fhnxknzNlhtm+XFXpcygb0qBoaydZRGGtGRyHiOnwa1nZL0E3n3 FelQutibzH+zC3/yRGeRv6Kfx3HpGppkRNzn3Tkbl3X+WaiF45PLbUIVbnYRmDl3wsFtem75rCmP Jatk0d2XUeH+opCj9t3j23W623d6OTYTIRKGrlj0PbfIEJGfAHl9LBSnV6N/DV1YzEYOuxiW+ZhR iAqpFTA1eB8U5rYPr/x2WQR/j3x4iOWpaSxVBWt/FOryWLpmfv/oeXguxX9IZipDAu51Hun1nwud t/wE9eJwu2N06QPuE3BvC1vhbqKu+6rb2hl0F8XIae0bv4a0OTpT1Q6Nv/tB7tVIsZV+5wQ4kiML ScpUFLiJMwFttMp//QefN1QnW/SdllqxRaB6w91WKBX7YkIOkmBJ1gNGxcsaMQ1MTmmeONqHkBnk 71SiCoI+WtxWlCpe4fLGxLe0RualQxFwn+eDXganHpPZkWL4jZJydUjF5gEAiJ1iVlqLDZew57wr /fnk327Kn39Qlznw52csbkqUvE1/yyOdp/Ehit452vWATNhXmv85Fxx0L/c6KK3a8QHmo/BgIvzs mxF1mMHjWzyd2XaiqZSOhbrtPTR2XvG0qAUYCWp7oEvckrbEjU4Rz77ADCX9Bx1J1U7amS56QAzw 71IoE7AYQo+eB6XkYNnMYPmgl2bVlhNxB3W0r9TlWGIa1EztbGoEbRXAUNmWuIBrB3CK3IeORlpE Le/QvYJlcN0dbQoueIYEADbcMq/cRT3i8SZ2lUgmBCJetwM9a7JCB9k4Vkv63MJBkvW/OYb0VqVZ 6hvIZR4qYYfjsRf3WapwXtbrOqDmjF6wJ6jHuRDergovvImkx3on/YH3FGlo5PrlJJABBLVqlhiL tDbKbpPDx6w1cNfYbJ96nXJT84D2CF4XAtnLTUPggwwqJmXGAtGZfS4v2TLodUQOsudwa670hQA1 v61yxieJAbMbYQndF0sr0P3/AJ64ygakk/kGuzJUMXO2Iop99fi7TWYe9Q5HjKlXr/V3xu7/GqJe IdDcVt1/e4LndcnRw8o/iI4auMRaJuzrM/XoNvdyXWDU28okRc3xS830qM9Tty3e6Yuuqp6Hr4z0 PkCAAjPBxz/ELc3nDsLv4YvYyfMj3pfcR6e5/gF5YxeKA4MpLu+cQnY29ZjAN8jy3TifyNIREWVu 0hvdC4tea6vhHOUtu15uCMaoA/DRN7gkMYWet+IrNtOom+qwB7jsxHxWUz8VvrH6Vj1aw4o2lWWa 0mePHEkTublY/f8Pn8kseuTQEEAjRe7Fxlwv1QvNDmVqEUyxG9cweR032jPmNMBuaWYYcd4tL8Nf 0cy5yz4QiiSVvzqfPuLhr8yswKsSKCHZAw34K3kHck4gg1lPA2gwcjQmoA6u3MmtuUyfwlT6gcnW bBX9sh38u1/IIqjBzk31MmJa78ibuatUZfLDW9I43Te9mdmUEd1WESFaLD55f5vMLSj2VxRmunPZ eP2KGuWtoyeJHjSHcLb4+RQOofFI8kKcPe+NwH7Yrf36AfTPyecDCWWrAJaMLAIjYi1T4JibA6Je wKAMiYzm4W3DtCSqaRlKtcgmTC/BchQcA7EJ6TVNXkTSXTsI4rVko+HCOTmtnig9wQrMGwKd+WC7 S/Qzr3voHqRtcAu1Ee9AtziTBSKYlh5pUeXpB+cViEluUPmEXLI9znON37JTu6E3eesCyZdLpB1p ketOGNLePK+X7qrHf2H2lktj4qvcS887Rl1GBXIQW44oH1Uqq7B+9eQy0t3O0UzQ/lLvuAlKSaUI kSdozyKiTt0hj+eq073FTvxl5GzfvXbrRPrNB3kSarBgVmIbxqo+XG/AU44PsGvBpUqQR6WGFIXS XuakzZ2XEQpP9MYR9uKhuvquJj8uMiozW8Xyd1NfKqBT/UtRqtXuqytHln8F5iqIjkoALlezwymD mHmXENteFZZc8efJb2FRfibFO4f8TnXtmH/tLsmcm7ze5UVbejxlaOpVqUOpMsyM0irbxUFmEk9m IN9JS+MNBFtjjgk3nbHzi2AO0YSDxvX7pyYxmbToBj/RMaQ/bVSWVt23ufAlG7EM9z8m/aj1uC5p emgqJOLuOTfEs5A/xEkFeZ87U6Qc+6DLlDKDZXmqAZbgmfKQr3Upo63bSon665Sye/FTYSg1fWvG sZvCK3WCUT8GQK4bSV9WywwV5e2YF6tvX3whMKcV3t+iQG8fljekhRtUKE6oF6Ot574cHbG2WnoB S+XpGLOv4qXLUrXTSm6NR6U9/+/B2Yl5sJz8ZRVmBIyXFJ0+kWFqycfgZca7CCYN3ehZef4rRR1Z x5/vYe2AlDhn9alji8t9Nrgxk+pC+UhehEiwTDDeSs9Gp2VrF7hE9eA9JBUNd/S9iu4wTSXOCib6 13pW/WPMHYTR4VbXe91XRzr4zNUv4uckhRlqTgwX18GSBAHgEFQo0BEMI5hMWjjjlqR6r45keJne iUTc5jaKvm3UiTLoP9P4yJccxMSGL42gs7DWRCRgrpSyH/NxKYzhK9nCmVlBrb3TAq56DAiuE+N8 m3xmcFwMO/rRp95o7Qn3QbVKZiv2MPyqqNCTZmrqJZNC/nQSmeSgsVWHAZXpQHLqA35pGlYbrE8q msk2DYUJckxeHPhZ2kbam2O9xKusfAwh79iB1IrlWbF8+KaZjr4U89UyjKV6uUYytk/cPbj6JHIJ tEMyfBNCzQljph6xlSUklSFw+63dP/f3YdNIwegU5i7fU3x8Y7GV9kWYdal6a14Ix/V1VvxU3i36 34MjK7w/J6QhobYom0D3Xs7+umrDVJ0PQnZdDgqllTmbUR7sGXXNiJTSMSK5pAAf0idApFQ2eZbs Nv6ttHqAAMaP9pQykHIOrZONkwzPAe0EXfw8fo30vqxYe13FiJ2eJHk2W891ydZIzBci9Q2yhCpq DkQit/iVFEsupVj0302qmacdYM/kNVwjV3T6LOvp5ALGuAgXHGRIdL2q/VezIZ/lbfG27Zpo66+n EuLRBCMsL6Fov9C9t0RMFmlIf0/6zD3Zfyc3KXNKxTgm2j2uVa+BMQe20FQZ/XNsSLWbWMgu8wro vqZXP0ylT6Fz95w9Vm+NmspWingXElruk3PEGCIR71Oe9HoKthf5XWq5967tEV+RD1alp8Pns9KB SCQqzMPeOEdmcHq1Wcmu8w4juPN/Dxc/vn8risqbVJPKonVGXY0cRxkBquo+bcdtD48GLKHiTl4N mWZ6gWpwmDaRepgzWritvlQ10wZfcYu6Huw1pmEaTn8m0ZFWrUUITo4DVpWpiDW+SesiOO+kY6rn eRb9fZK7SajyMsjVeyUMqOB1fAtwMWVzoSyRv6MwOXzAyxnhEm9S7d6oFSvg8CutZcIwD9vE+1Pv qNM4W9v83V32rsnjuIiBL4YEsov+++3mixjOUHSQatVNdvlvDdHVbZWqMibKwQHJxGLLArqtt8Yv C8YvxxjLpnhZ/RI4471bSt77LpBDB+16qK/C1RE7Lpschk9kDhdjrFwkqqpH+7D8gMj7rrR6dQWG bioVnP7yRF5fskkLJ3ARoziPupW/2JeF9xWPX8QUDnjaG87xC5M0stkxPzxWb4u9Zwl5sOvcWGzD 0mQh5R3htt0GWu1uIAG3q8MXnw2mSAuPAEd9ub0SNHd0+QFRrC5pDVsfjtfGQqMb9ClaCgDjqpTq z4WnJYC0KVvCuPqwBEufOwFWhjXG+noAcgtZHhEXOI+f1MldiynFVPRSq1VZTGxuByozLs8wEFSt cfnbM7O8dqZzlQt241M5hkKdoDFZO2h7u9DgO4X04emyd1l49r9h5BwtXC5aAYzL5rTc4VsxC/8M nSVH0hFwtI45SZ9OetEtKIMbm1ec2ee9AdJuNZxFgtIkw90NW6lk0bc62kHU9+yrYFeplSApYfSr Vy1dJXQR6c/8LF/YEZer7U/GNOSMfjdbjmg0fHxW3azkkASXGeL3taqDAheAzkta2xN+RrTjS7CR Uu2WKXtg2j2lfKmm0rbwX80uRont69bim60ro/3TwKlu7TClZBcIYBdYRtfs/jCq9V3eKiDAESqm CPa/gqN9h4wOuanTZIH7XqiEB8ddTNJFoNRsB+2x7fbmgSVFtxqBNLAhSlhRLZiD1Afkj42ARTXw mFrw+ed2QmJlCkinwWBtc7ikK9baIm0rmQUivTXWvy6w1BLColMhOfvOKE36QZfUgZH2GxBmwMLj Nz+PvW9CAPIwBTbtEb+cE9ShOrlaAkoelo6o861S4UOmgqwLfnsZohTAUpGaPPOu6cvtIAOi/s1X znATiEJo7DoC5E9Iiz9BzfIlroRMVH+KB1GwXn3ir9XYYTyiYOB4rqk5pxKNB24q/4Ouhs7FbJx2 JUxb7loN8zPnHSZvJ3MbC6xWLLmR1fE9AFNke6lTT/2PQCIbkldo5jSOJAQODBPFsxE5ZosJU+Y2 aFcy8MRJyuqrbpGwPiG8uiItC+1DwxdHDdyUDewOt5fl6M58VrZrzCn7xo5oweWmYlM+vjE/NGUK suLf/E6cDB+5tQ5cDl00bNSvJzKp1k9AMgmUAil/K92EzVAs6eSoIjOztPGRxPxKs2dSgB+09bFG blJjzljRzkkx4nuyhWm5aKzc8/pt4oG0lg7q4WxpHtdquDbeTrUhHytwpvISwMK9R8aABizmkVB/ 8tzQ+xkKDBLBjErlnTug8wkzj4GmSr7LrtQA75AFpjDho3ANxkhZjGyvZNS8qPcrUXDreNqr1pTA MyOJVV4UI1dyAqtqUzoTWXoLaSB8ATrUMUb5PdlWl1xD+g0ZJBLgmdRj6kTbNrIz4VZArWnirKka GTlYn4KneWpAvG5bez4Pvwec49mhrRutgGZu7l/jfDZXr1dcemnDncCKriAC1m8F3Zn6W040X2HM YMVi3F1v/QrUHerMAz0qHyNEUdbJUClD3rQlI4ukWqpxtSS5IEEOmVZaVydkwELcIFRU4kMl4mqp ZJ8WgREMt1/Ryb7eLOKFQ7Lu4UCcIh0x98Ql/l5aWTennlOduxW/UrK/xDFN28MOoeHtt4mxSZh5 akM55AZz6l4R5ZReObSHE04mI45ff1a7aQwHo8mZ1jhpEYESKu1usWE99AbsvJl/7ak3BLFRLiO6 3LC+31xs6BiWfsJtnIaOOqAOMl/QYkUcslKxVsad8pg2X3gnEXdGwb1lxeAd5/eX9JOVhA8WDdyT pcAVR02tyW5UN0ScqRFSusUtB4fj6JT0xB+dl4As4+j3NIdRbxMYw1QNfEHVRZZK3G0RZxzlrry+ 5XpQxAiKOcT1nVxG0TLNCbAq4GxbVgaf1Bha/qpagw92VaJELAKH1xMIXQqRzWC1Tll2GH/yvaOw DT6SKJHR18RKNt/2B47cSIHTRLFR3QGWMYYWv0bpsOShDWRYz1dmAzxZhUG2xB1ht8vM1eyAY4SS e48F0C1L+G6GrzYPcgs+Kg+lU4ihFf1PZEswpdOdlHwXT3+hQ+52QbhQe+hImPKcdbvgY3J/50Sh ANFPuzA+UMPcsYDruWScgUyzjMnA5yH+L2iFkbVm9WDAfGCMqW0HMCA9QxgJ9n/lh23JdbkhCE7p vI2n8S4KgeaBM0Ojg0Co1/DPd+Muk7Ksy9sJ1QRTaqAJpt5K8twNlQMDIGndJ9UOgTLHz2PtQz7B Kjnzef+swbH9vJdVCVPx2oCIyv0rZddL4N8O8sLf2EG3iV7UTGKn+xCCN6WNf2P8KXzvlFkGh+2K uuKMrEmNKLh8AGrI9r7EUjuPRB4quqSsk+j2yEGBySLUWiei7IdfhOZVEBU4T4VKs8hO7of/LLHF KA9QQEUMKg7ag6q8lnYQIUSdS+vBX79zhuppKew2hX1GfZf7fTFulx7wUiU3q7ns4YvOejqDEs3/ SHg7kQVKE6ZPW+3QqdAf0KprWUw5aa3vJ2rflhEHOnZF+5YYRiAOAW2+wllg6Kdn6i+yGQ/dzoMS L6O1AO1baNev4SIpISRvMQQBO0axwaX7SbEq4gpLzg/N2jbUTxDI5FYFfLjcFFuEO+qDu/OnzZ6i U3PvNiGCPn7s4Q++5bATHg7wiAXfcGrOjYZ4BpvV/BvRKYspHQd09bOZO1rYhNGMKhWD+Hir7Cup wZp21kEfhJ7mk7Z7EZmkyqP+FGA6043y1NWCPf8A/cATWE33fWPJN96O7ctcHM3yT2tvsEmLOkKY 4/Xb0G978YXMMLimjLdBUJ8YOBEa5EYSTbjtjhK91NKGhjbHl91Onr2aCYcLE+DW9P3i5h6NvB1J EbwZAf/LA41YT25LYvdN4QhgsRyweIT/71sRlTZBTL7iDcXyYfGe0dRc1GKavgWIzbWTmXx2HqFQ RL9ociLoXWk3pnWLjJmWCZqNaPwRqAcMpToUSEL0VJ03cepIJ1PPrgMFTdFlLjDsgDt55lWEOIjZ nR0U8XreouB3wec/21/BRNg8kwPEjk2HuWS9huWUn+t3YhVZyJB4oqaUdMVnK2VyQCiqQgirl+/S uMbe1Q1FaL/vJXhZTOB6jWCnf45RNTc5qS/s+4Lk5UKYLek4iBpex97FpEXa3p//p3JsL2OkI9hy IfyeKyFB38MkHR5fDPDlIRgWPxp435i1wPaLcKZ/npLM8qe60gRf1vIck43WxKiP4doqLon3NqWE K6YSh7HEbRJFpmXBGW/3J2KT7idAqOTEXjS7+QxtwaO/efUAk202AN9rsO78B8g2BifWAt/vXsJ9 qIa4NMUH2mkbIJWoiqShbcBMowX5ealf3imjSWl32jJxP8g3SGWlMuIou5T5dcI17NRFTp8bx6kK 12sFQKe8e698G0URTT0jdONjjDpyM2iun5e0MK5NkFrmPlq3Z9PcP4YNA1L/Za3KGuc7t9Hpvpxw BbUGf/rJ/s+HYGSSFGYLtTuinHoyWKGT6EDbdLcnDGYGRRseA2THgeNrbY6WWj9oTGkAHfIbLAvs 7OxMGsMD2oiqGVWWjujnUxW7J+E6Pnu4Lg9wWj/y03a/mvaoSexi0lwgxA8ZWjCxS0Xs4mUp0UqR FD5T1v2es+XXhodBnnAW2eOJDQ2upvd384qr+Gba7AzVpfa3nanK1/7wDrjaQcAIy1gC3DuI573S IsAuR4AzdeWfjau81ai3EbRBLBRs3HWEvcctlu/V+T6zwaTbT7w2SATfnIslzEVFXNFxlwCDWE3I UF3c0+5NgiIsmmzkbR8z+eKRyByDE0yE23JMPLA24lrkoa3eEoa2sIr70gFDC4iQ738XYYQqK/R6 AyKSmjo/vIUb5zCLfBEdb5TFJ8owJ516lyLZZgyyriHoQGqeZaUkAfoZ1rSHLsbJTKgUAqByIlWf 7pIWXkzsHs4wl036SvaesqQjwhTfZKEVS25ONrbcnf37T/0FapolR1xwllP6C5dbTDYRBehbqoXl +5AQAz5idZzFc98sUQSfzX3uJvGkmN+7l8l3m1O986NbLiWA9F5oCJCLyLnBsXMi1TFJMva74hnn Bhx2XSqRwikYbZK2iVL6suHxvyy1LL26ESL1Oh3JoQaQCVyI6SF9LcToyhO7eszytrXTY+SuM50Z UyilimUKCEZNqL0H2K8KQBbkH6nQuNf/haGzjIQPmam60gX/EuVEg8G5LopDLI2vQWhW7zITmdAC Ow49+tZUNG8smXsXG9WKHHKu65JoPfPoKazLr5XCky5YwuJmAZ0pJ8JqHAZDXMBwihBWVD8S/DSW +cZpwQKVWQOf+NwrG9jGbePmbA9vUNSIZUyxPCoGdKWiILVb7T6WVrAD8kWHs5cBuYlssJ7Z3d3Y gKDzsxNbGbIYWZg1ZuyjCkeypSUN8LSP6yYt4SLmOpaZVJqTMyj5GolkUfG7WE4H9WAY9kwsx4ha DZmvqQbP1WjmfioTsxbShq6w+Sz/WLOqc/KfTkyDdRcOHfFrmLi/N/zt/0OwQq1Daq4mWJjkzHUd GufbUQnvM0shnxm8rzzwhXWWTAUdI2niRm7MAgjavUVkpFAb24V7sdExgzPaUZbqtfBHyrJRGRds hhXtICI2QN5QmLlnjWwUqZBS0yzHY81CFGvpXlcCeVifO6jEiGHaUvV8S3Kv7xEZ7En7mR1iI5wQ bX/fb4TT98lrOG10alxzxF9AHJslaRjpN153JnP1i7EnkS/NK0Cfl8N0MEg7z0X6kQSjJL97a9bL FFzxOSwEuXe/tllMxLWFFW2x+UTWMpRc28vLb/NQQz8j2WYzc2WsT+aXeX+6tj8cteg4pdsxVFwO Rbu/dfdYYDsQ9SalwrHGPSi/pEwfPQI0LS9GYA4O53QiVzFIdjVQeS99NSLYfOFVZakNzm7qditl HmXZbWIX+xtvh33q07XEmoDt0K4jZEj2PXJHMUqOm2ujOnvTwRAqkyKJR9hiylcfaW6i3XPkK4uk qUn9vJv6vAiXYDgLOJwhHj8KGjuDFUXZ9WaO+Mizijk1q9lQQ0oj7agjzJpzLoMjRKcpUMdkWBN4 Z2BiQdLRGlNP9a8ywPV+8sOFZQvBsORDbRHbnrGeDX7V0Z3LTYj/0Q2HcWvkiODtd86DbBtO2bb8 UcVsk0mKdub35Bu8rQaCQKl2cpobpVgFngvAFfcJir6CHZAup6V8mC1O2o7Iy/SzaMDIGUo7mbMb hPFuoCGmueJkMtmel0IY0pM89Uhts42diZhatR3+HSnRnp9KffpwHcfFMhbSiHv2CbUJ+qoIlk/g Hut4Ys2NMtEIlPQqhIsL7ZSnJDoHv75rrL3Nq429/ha9a/BjHRNmGBvrXlcz0PDc4/w7GYbMVlII WHyvEj2XbCMKN+p1KKsHyr+VwMgpiDAvDlRQj0oWuZwYAK4AjZ+QndraQ/g6E/2XhmNJKcUpb9Ib XabVh1ta37CT5qXwCzKvftSLktnDvfUW5KYSy5KMYCjtzA94ldbB0JAyDE6jytc39OMBEaOOOX1j ZT5GFN5BcKaF3bgK1hS1numkK+hrpKahqlQTB7wKF0pN/Bak8EG5V80U80j4UxIL3c3a7XzOXiTW mBr0WGHN8UgLt0q/eIpZ6OAbJfO2IjuS8vNAL2UyIrSmO5r8PXFXC/pyXWMV9kO3qJrGNLMNh1O6 0XhT+ur6hjkGAlYWSCN/cP/PlOMRMj/KPjaggSdCg3Xynn6DF4/khWGMtzJknISp7QZpT77HYTv8 Q9oFYqWsqLoqicmsZGy3e5qolo9kOsqjT1QFYBq1cSQocYplm4xfPedll6ZELnlnT5czR9ngjZQx epenG4Am3XuUnhiomws947dJZ6Gb/Wfg3XGwUFL1RCWNScjIDIg4ajv8wcy0Xzp42Y4LuzjjwgHu ISdmg3CudARDrwrHxKpIfmneYpkBmniSbri8XL7qTh0uQzESwowKWuzCoE30jBX7prRCoyoFCgCi qAUU17WQWEZcyt7C7ioub/mTc5GvGsYFc6KqhRZbn6q1VfAh7CDf/HCzktWZy7KI2ptCHdICrj0M EN4SaEG7MYJbsNd2cuU+/2F1OvOJ8SBwUt2mTMPEQLfW5Zq6u/d3YTq0n3pJERY1WmeYOibJfXR5 ysDQqIb/cZFcNVJ3wZiiMiYTFmf4kRXNU+5kDGeq7BZBk9UaOgC0O4ukEIePSVLk/UwiAQa4gInV 1Sua/ADwpUWB1xc8tSnXxzeGT9QrKMSoIaoyjKYzDW1Ijcbtg9K4OmUfu8ReTw2I6/LDTXB5f06p lTB12dL8qcJFOee/WsjU/4t9oW5tS02auJirD1/Z7i1lYO6zYY8axP5769c7YiYuitD200KTcP5t fYQg6LxHrPgXW7qkidjFcBD/MBEUynKM1T5oeIZF3GmhMEukSWjLnDo+lXTOWZFvueNHc167yu4j ZtVTaTHSDp3lfb1Tjiu+2RVm5fZlnFcuBULFAawyHDydCUQvXpHmV5sYbYe1+N5pwXv7E8uFE13B g5B2TU0sCq4heZuJmmZvgGuHwIMHcCHuHfhAcU1awkEk3XPGiTZaqaSQqfohrJ05g//AhfcDMkph U+CO8lCNFkE/mA2llowAMSg+Zn5/DAbTVwm0onqepAshZIMe05YG5LXIueRj3thihxPlAu6wieOx 8OLZTtWWF/gmfPQEO8ckaPPgRejDyyUY048YDKiCt+Bt/FybPw4b+m7ixqoplcjYNPQc9rAdQTbV gmPr+S5XHf4HffBids/de31zTfHgl94mFNhlT9exiSSZHDL7U5XbMspe2eyGOdGGQaa+1XNocq9E /sWPakwJyc9DwZGFMaS4XiygVSa9aUotFhyJNuyv1gaO5Gu5zw5Sj5J+7Xdbu58GyoIReeXiutnM yQk+B7XGQ5JfekHwU3pW5ZkxP+YCosLnVePNXcXIAmwGPbNaHTemeF0buMRPBDxwxrFt1ll77OOP BkRRGgzsEorppkBUdn8/E0NQm4gPnZagFPxsqMdnbjiQ/zO18Aqaqgw0P/A++0vRlPhb3N4O5Rmj kn/wufZPWrv7E4vqBwkh9BUIRAPsMNrisRXt6eK0j11o2m9uRcMCN8mwqdg+fTOVmHrvlz7+wfmX gdyh8vtPJpyjk14FSiWGoiYOlY2i8/4AmqGLchhSvMHCyPwyrVgCX23ROqFb4uKwICKf52p3Ll1N eOWD4JKoMLOA7w++rp4y4RJ8YQr84T+T5AtBGZkGyi9jLDJDf34CKc3G1UDernbYOcNqTScwOQs1 l0i5LyQOK58MPdCNijguVyBqm4HArwk/1ts0OKTzPdiZ8c3iDQfHLJRATXmLomj2glMiTTk5AHPu uJ1tTnZsN8NAB8ICUa5fbrEYLAwb/kKyeIks13WnlAIGMdHSHY6Bm7Qbk8ZQBM90B/hPLKEgMucn O1EWlqhWunoDqI6dz+qQXvteHXvCIpg/7T1qpPYpSn0qAOnRMgBZY6neiyXdshqwQZitfViycpiV CEEx7PuLxqj/S4wim2evW3LvCKRGbomIun2Zg9p3GdHjGTtC7dbFOSxbOCzdjydKnxR1Gjn6+yJI I4DGiWl7c4+kLeqHKdIqIzwtZ7Rq0mscrsDvMzHHB2TqGKBSgwp06BvRtYYzREO3aJE9Nu0jzVWZ K6geyekwtvK0jbq9N0b3bneg3kCY4JBuMLsfR7cbZvjr3CcTPclaZWU6kRyFiRuw5JQ3FZyrVmTo QIyeS395+mnpBb9dF+PkJVLPyzLbPKavuQD1GXUhT9Y8QiORKCNtFQxyWUyEBTPb9WrTI2jh4/Z1 rxVxHpuKyaGOH60WaXtH6ZBdEY/7omeJPl2BZ1717sfqCMCsf0qsbW2fyV/OeY0O9ZEpWT1wdYuz VQZZzfcCFE4nUUG4Rp0KBPfEiSp+5ID/8TBnVOXAqww2n7LxAicdoEvPf3RuzgrZaZSHiBKXKDNA I1pki5+KwQLwPVEGxBXLsKGbjkCN5OlZVPwXDbAVoMwrCeNC/nsaLHRYIV/NoFy+lje6Vc4A+Lf0 yp8IqY3jypBOrBn5W2yg65I95KoTFGo6lT08Vda376zizJe15AnYURZMwToV4XoR3WvDzIrkq0Ll WXWyCJw8E/vainK2uoOfgCWqSfsB24pc/odIKqwFiy+AAF/FYBV5z/jFmG5k7Ckod3XW3JGkYYDe SlRL5ZXR55R7i0Z9Ig3EUCyyKuRCeOfiye0b4RmwVmeeyHrnMz/rnC1vER3lHOBkhutxhrzRtgc2 +AwwaCSH822RRrfByFbszI0QZ5CUbiFx1riPZ+OgREL+uiSxtIlcgApevyDvBNQFy7WoTdNhNew9 y3dHnnPJ4igGSSQrpoq0FWra67OiFalrUBd8+CXi8luOCO8LlpHSlp482Ld4NJIoOo+HN9XMVG+d xHlTj1wLXplfuSSfe/nXM8ITLHRQYLhcbQT56jM6wdEV44/sf/wWrfzZcZ5itwIbA/Rni7wRybOh J/5hydXTcObwQC6K+LbhkVfM1TCa7A2CDhx3ZA3t7eLU+P9ITibxHKLpWQsrUY09BCWmfdb/C/ZJ Wmie/2maPsvLLhTrBsx8KhiuR4D7VDLUq1gfkJLS6kQOrMCEddyDYorTWxWnrkr74tD9E3y6RlTb jfJFMpzUQfdBvZ0bfAm6QVbvReptAYLtgQkbFCDbyq1N+38E8sWM0airFjjbpFQFFvA4pIpfxifK c7l8MWnu/3lsGX7dO/fbgoyL1l3OCKnMfuJ6yVSuYP7OYpjlGimILDDk3EvqMNQwOvVS0Onnhh6A 11PQPhv6q+VJ+THkBt1QoBWRK83Wl9OQ2h8ZdeF9QTa/t13fENXCI+ULoDWPSfLZbXrbgANAhmJd kN+8UYpk1AajN5mNUEXI6jnb4d4DXVPKQKHE/LKj3FhZmz8s6mGjhbc4xywiwLWkbMFeoWwEmy46 hL7n0lU1eupPDkAVOdLJokCFmsZkgv+QpQYxFX0xNBoHoXzUbHWJyJZWphzeYvEY6sr4YVeC1eGw /bAsUSJzETYwLRcuIWLpLj+oOpjCbm3/HyfKmAcKDa9hPv75BDpk3cHJ/Gs3ZlSgxxkhjLu/B08L V3jyna2A3H9NtR0xrcw9ZI9HI2gDoCdGIQVU0akrO2CewhJg8/+KLbSGCcrfSbbg0TVT0YbaQoDq nePZutjHAZALIVMVQeLs8xXfK3+D1Tu3a/iwcxcr6Wi5n72grxdFML43tCVDFIECfHcj4R3dKNJo B0qWTIUoa5wwyauZSh7xrx0cSAbFsVLp7OHXF820dr4GIxnXjPcBdK0I1frG5YREcSi9VIRPn07H v98UGlNxS7PEHEaoMxGdpIiRt9u/WqKSuVRvgtVgwcxMX7dht1LcoulpNkuSl8CsdNfEBIaWiemk 4uE0WujPRjFDniqyMJ7WEwUlDfYQUYHsqvTUvpdGM4rI10Qm0QwpvVU6do85jz23wkmuJjRaoJWC hAB+Xi5lx60/3b5H5vF4gXGA8L7jZ1SQ6Xy7j8i93cfkEprFRf34bLiS9NrvXSbOVjaQ4Wvo1kwe BJl6wpg3JfKUHuzcOLtACOmUf0PzUAkPqbJMpk5pva/cnV6+JlwLweG50KFKMyrvxHyyVOiqsh0s XvkP70CBxBVK2fHcE7i53Y93bOOG5kf7sNqTziVFkn6YUeAHr/PVmcBfapyjppdyMIJqDFc9tl5O 8RW4oXd//QIAgQVKvh1jFkQzsTwNjS9uOD8z2FT8Px046GtjR4JPqZQX1v+ONmIqA5UMFNXh0139 sU5l5k5PHpModVpvfoF+nSpVpCqhtPFbMq8zBqykzHH9ttvGB3efkImvlsB7Txn57WdyyK5Ox+Fo wr7fG2693SFKdzpZ6lMhlUQeYD7ABoIiwYYa4DSH354153fxCIb0K552tDUYVpAuvPk3J4SfNxCh WUSlK2AcX29yOevNIJKfUpBeF3rb+EVscYBitCwLeITDkfiXDYlJBSY8Ts4EOrVQ0lduvwfrZ8ut IViPd9Bfv05ZSKtMjNy8X8EobKDmv7bJmwzCf8GtQNlVUQqbkS413i00LqmhgHNLVX5q7MgDDSGr XPPf3eKyBP7lMbSf/q3B+aT3Tv8sqZEWp2gHGhfuIxteO4Yhtcnk0fFm6y8s/M3RpIggHoD22V98 mYTZvGNSl1RXNNPtQ+7uuHgd2UQeLRKsNLSV9l/cKnALBUpCFYMa2KJM98xjxO9kr7KFAa1d0TkD 2VhVp/WZUFke+sdIT9W15rk7qsgHMVZa2UNPi2QcImOBq7K8xAKK+YUy74dlxeKKHN1vhDGzQSAp kr4rqmo7lo7uJ3LJdIK8DTngvBovU6Fl8mC+uQ6/PiPPQzfHylZpUTEqmLf+y7W5etGXbBtoRus2 BCRyyj9TDs8JNV8QPCuRsv4qIwLia2nijsED+97IIZLTVxkbbSn48NaJZm+8tCp+DfoBFfWnqU+A 46Oa4UP9IlFCT5MExKFlQWq0mkKwkBemPFF16rVr9RqrfiBqJshUXCM3XucyOr2T7L0378D7cVfo WeI3IbuQz8rSAw0181kgkQHBawGc9noH+93SHK5awJeu6naX15UZU1BijAOfsrDwqCoXawgm2dCy RRXHIE3dMEvZQRZ6SDoCDprRqfo+W2izFlyvDLSrnrUKkHyFXEHkiSHKkNDm1yqkHCnTf921+9G7 +nXPt1o0K2Egz0HdLZzcwGIWLMccEiO209RIzbAdTMGkUcveNlA1uuOkaAllvJfEXlUpMxB/VXhY AIo+kjwncFHKvB7fsEnvKoJ18QDRkwGL8zjGBjPZjOcJFD8aNHVoyA0FM28PgYIjG3XwJMfFYMfn U+Oui/3ql9T76aMgoAE2S24gyMVWn3ccq6sjv/7m2QPq/CGEmg5Q3gjj/NIeC9Jmb5A1lBC3XfSy t5gz7EIpwkMdKb9XN5u+ChR3ARDih5ugei7dPyurGKb91pNrRTJ2npXh4W0KyMgqrJ7Y19KWf5m0 q33b7HebmXbueFBWjt2uonA8eemU8F8MVEtuwD6UboWzFucWXoQ7opIwRJFkYV/QCJ07M/mEmBGg hQnA9n65+uzD4wJDWKGVOxjE4hlx1aYeCAl/1oIUX2ao8dDkFfp+HEqSDd2Yad/AIo9S6g6055oq 0XB33ApHaaGnNqpGRIc1eovn2a7lDcyHupZBzcUzdBMDITyO5Vr7S2Heqpe19imisdWXXwaYaQLQ mTAf+VpUba84X3DnmvWurif1UIzxSDQiVnk65JZYWNboLbGFfaRi8pwd8oXcmPBA4Nk5ISWLud/7 PI3n97uHLiAXH73p9C60bOqU/cOq3Z3bgdyAkyWa5TzSqSO01pyhxuF84iqsIbR06HcQogNoj+Ef CqO+rq7rn/TwKtTe8Q9k4flhzJ7DvRV2CdK7OK8eJiC2dNwFOda8xjgYkafTqxqbb3gctMVgnEh2 tWqxREWjnS0ZsB4uYbH3wsuJDNyPFsEma8stMXeAveskHjjZ9Olc5JZUPKa7Z1NifOb1dG4k7K1H 9IREgOAhUykbbSL1syV1U+SCYc4Rylafgpif4hqxQ3ey3SDXlyyP4YgMLsGe9TrCbS2u1jsl1WJG XC8yvIW/KYp6VvEZrNsS5wx484ZyI1XjHUIeXzR03/r2FkmHWPFnA0LogwGGXxgj0O3+XAIGPhED Zt40hYi3xpmqEPlf7ACH3kmlD3TjWbRT0ks3Y4aIkCJlm77Su2eaQ5rsrA4V+0r8RCkoDqNeFypq qt/oLcZSG5SFHXt7G9OaAGNZPpBdMZCeMfWamJd1449rKMazbcBqsSBKY+zuygHf/LTE0/3osMeW oJssvgUmbQCGfP6bWP7zKvhdQCsVnM9kMvBN6TPhie9AAnk0J6w9l6qcA4ebMIXc3CGHIbLkPu2o 3eIa84aXucTx1IWppqLSBo3ZXpNMZrIlPw3TgRAOutKNUNoC1lfLUvwEwBuQ7dzsX+GSMva1zwDl uBx243ZMow7wKAKiaoNuM+teSUNB09vP2oV1n11ySq5jkrpu6zTVvpiZLIBAya/DDWF6ZZOE0UPj gY6qtFlj3I/hXS/fFEi6q8l+nfJb0w/TaHNRSH0eYlFsf7Kl4hzCaM7nzHp8T2ZpIyjtI7AzgjGc vGySUlBCGAgV4HA5oJykBMqILt2m0HvyXeO4RCyt6HOpqeqpsuG5sDViD8CWWy4/EIdJYdAiZeek /Bezf/nR24Xh/BpdXATnUQ3tHe+fb0PMk+EF5AAsvzasq/OKzGo/YW/VjE1tav7kQcrRbpL5oVbx uOjqqW9lhvtj7/FtzjUALr7KKuJKtFuAwPaAUN98fYXwMWYVypvPCtVpMPy1kD86L73+jQ4VI12o YC/Zct3Ot+d5o6HiZ1azXDM//wLTKD1ujq8XaCw7f+sx5dP/OnQoDMMgdCrRlm4hwVRsAq3pESqB kDcYETrR3SnMnjz5+qTlNBu5NheP5f0DRNy2V4fGMgXwMLnZ3TZy79Rg2dNrUFpMmTL72YwXnIUK 78Z5OFAl6R6iUYnu5D7jd37zDA05b1OPIibz1sBC9gZMW1k8TOmxOwpD9oW77eEMRRJ2IpGZZu2X TBz1Saga2NBqJcJdDfSurcokXZ0QIt0yWF6q/ycKfZZCEMUzaHIa8RDpzlmpDTY2xnB7jRwOcq70 J2mkHWPjf8tc8/Bll5kRHPF7PtuCnAUTOrHGWHC9iRJFLKSB74MLABTxprxkQnZjLAF3Ji9HX7jQ +l1gVXmBhBZcU34IIrHSL65OdWu/gniSE+kyNRICzvgvb8sILEukkOiKDyw+ZW1xHTssajziYS0c C4D4p52N3X57cSAIveuu/Zu6iZm5eYiuDfWijCLRcm37xvDZBHH0tecIi5qENutBiI4Nm8C2g7vD +wKVU8Wf41rtNf5p5RcXKbOWaKdyy+/xFMhhd5oR6eFdM4f+RkB4RDlYPckNAF/z4DKoRlN0urpD 6bfs2tRBbHRsJ7AJqeDxR1epiR6NlAmQx5q2tMr8k5hzjrLj0EZ6WTYaC/82YObNxydvVJaXVkG4 93s3Hur/7sCTEMTVL9TiaOubiqdWkNTzb6m8w5Unyjml5gi9/egFolxvk2TO83D7Ee8rk8W9Ult3 4c4PSBh5u7g/fZeFzu42zU1Vrl+oIFgY0CqUkaM1QI1AgyjJLC8ts0AiD+T4JM9YGhYBtN1FGNkd 4SK1oI51x2ek99SevzRvtfXskK6yiyh4zN5dNScdEZi+FmiE9wWjwyxqL3Tsl32xzguLbXhuqGiI jF3WPFxhNE2DUSu9hYhwPsrlEAnU1R07A8X0hLXXOUQY5AI734aIlvVokRZP5iyCRttGTIibs2Kc aQFo+0aiu2YSox5mrVMAKK0fQH7zPITKnkYmRoY3xq0JzrnH4Kv8mutw57YtrmvrEuQ7JlPNid7h QcKlFXqYz55dc+5eEr6+gIEV0iS/4bK4RKsrrMKI4pHxq4etC/bLnkYAKC1vhQOEGAceB+HyEE9a wBCnB34DvnGHD2Lhd0wIcc/qdjoew4hnSYO+r2xKPgPqFAbcgmH/4NqsYpD6RB94lv5RUXx/E6ib pfxYXL8VAjFD9P7gFXAu385ufbmFEHIwni6YF7PpXmSfNfVBjoFymda4HIuEptls/h8uHPXFKNrk 9sWOq3poJ7Q44l4esNuFSCCCf4kYAcF1lap8XjpT+dc6VLiOlf/rFGiitvXkx9CzOqinBAJfvK3e ykJKn1CGgyZcm23iTivU3BUOeQ7uhA/+yyBGG3L/IVmNbU0tJ7iJ9pvVypFK+FsYlalsKiHxZNO0 xcsCl9h0NN2LmKqHhndedieskQ5Po3zGLr4JKvywL9+uf3J7r0zt8Hd+NRkB5mkUkDCm/GoBtkSZ sa5jrEU2CMhLNaG0VRyIIkTiEh/dZ3VXwr0+NLhgDbeMy/KBtdrTwHvwLwhAEQNYT1Xa/PBCnmlA ln848IQSkfeiDo99o6qEofLENBaZ/s3F7WyaxaTK3jKR2QA/GDvPtH5j/o8b90WcDGDq0p+QORbM FzlB4wj6lFYJO/Sqhdw3RkBkeD2fd4PGiv68MOFZULi1A7OuUabA9glBJ3zT8PskyXk2aaBb6ikX 16VLqs+RbtQsVc7V+Cfs9fzC7AwuY8a1nX1iU80zb1QheQkBpV/58GnayQrUTtYFOdaRo8/AzLg1 ZS0+XTNcbRIsy5HNeeTi9Hn8J0TDOAdgKrpc4hTFQvvaBsq0bpPWB+f23B59OclbY+5ZqajwN6gR BjcD7LPGXioi1fxHviha6DHtVuI9/K96LJ/84xE8U5ePj51+vlGWFoHqzy6xIFb7MJa7ZhwzZjRM ndrNW2ED7B1oEk42xsApsGMmU3vN8lTiSSHfjBzzfw+MnJyvkOndDDRpFR51Wf1fBOyk2a+SP3S9 QCkBTG6Wg23gG0/zpw9yoH7VgkcUGfkU4ZfIOL35i3YqkU2ZrL4WG1XDQXza9BynAwWqroYpPkPA HWn+g+36PFG+mhOLNyQboyhGYVtGlS+PXSu3MQhDiRVEtMinHADmbz39lWPwYZxG/zGWRs1MWIW7 GCBTeJ1qw60+ED6UqbVm1jSsl46i4Nr1Zzpu1FALW2BLpjoSHZ4QrasmLnE8ltuQEfkRWfV5vZ0o cP+HpCuKujtFTB4NYAU7GCV+KmVfUxGvEN5uSSo/hWSJ9ksDSrTJYonOEy56ve2Ads+lfH5PpfDp wItdQWSbAr8LPqGaOlpDwQ6shiR5XRwl1ri8puevJstHLXy97xNjDBxRS7I7S7I2VAUB+RQHYuhs qsU0wxHa3MzNURKRio7K6LFKF7lel9VF5fVxwTG4LTTwuABr2kv8ghsIUomBV9N9XomWaiodfEOZ BDgxzWTe0/15uwD46IBjuGj+MrpnZhz43+6Wb4sMhOOu5qgLi18XyLyLyIbHVr7gu/5TQIVCBL7b pbBnbUlsfywaEa9jPuedJdVW974Fqb8sXa4/bvvaEjEqXt5MHZSa8Sd7zEiXDPwNbemkwOfRk4V3 boo2RjirS0vL+UHFDegRZ9hysXPLHzWVHbBwM4XvkQGrd8vDZOPs4avelniozltQMhAahZBj7u1N B7dNcTO8fku5Lg76E8+PI0pD6B0BDIAYdCGSviYQrVDjTpXxbgkvyQDFKIHlgniJ6LKWia3wDMg4 fN/PECY1A1v9mhfYMTGMzldjt8AWtvxUnnT9oacS042bmHQbqx8kXs0FUT3IKllxInrbcevJ2t8n nHw71p/56UkIc1iYH2M6Vd0B78pLd+OloN8CyhHg/032eRDy2uLSUhF8tzqxPfnGX6U9QC7cYcyJ 6/4fQrlgzxQ24JHLfDKmSq5EfyZhgklnh6AAuxSDe3pELyBi+UGR1oka6PjcZsdq7a5sxA9v/frt dec4ShQNN6npqGKn3z7ah0LprRfcxg4bk7Lpg5ZMzix/JsHSh8iG2rapjkXD1KkQ75A3QbhU+ZwL fjb3l1ZRPWSamDeF8USP1FTfCsVUi2Pab/Av3W+u8ackOSWv+81f4YBgu91yYcJDQ1xoUf6fF6jH XJC7LtnNTitLgjpmMzAb2elpsz/6nY3utGkARKQz1nQf0GOLfPlwgIcO+HBYE7Llg7u39N1PIpD0 lgNcmCKRLbAbZD0FfrVzp6GJqKNYQMCnYL7grYGuTVJnZi7GytgC1/aqKknkJDo0bwC8lJTrz/YY vn5AIfWRSzvZSAQ45PlltAOmFvuYNPA5tapvzLLKg/9lFTNrGxCa5hSEkxz3672MtZ6FuV1sjoef bpftme7RY68cfGaUecyPbEQjxAdLOEHeiLs0RRtkR9Ym2CF7jZUNfmtxLtw9HAf2KgUxD0DzYs/C v7eyT8PaXFQm7gj7M3hkqRY9IzgUGImZia4oLiqTqjcjOwdLYWdukh0YoKsBoigzW+ldhvx3Tw/M qK7pkGZG+ctPW+C3ldH09CEF7rvspiBBsdd9PB7OWyznkWJhZFVgy04qXj+2kneztNbXgT3MkV5o fTAmkgNY6i078RWgvrERIYl11SGjmA0/CbQZUo/URCmC+ptN3NZ3kQI55uU9f8qm4tYiQCZVUGO8 Dq3X5axa1GiHr8UV2APdXgwFofteegoqybyHZY89YXZ3Xn/p4oBxVXWTTXfMRveooisqkGWB5HpQ q0W/T4jJJ2UVFNvgfp4wQ/WojopLDXpeNqw9d/63jRP2Dk1cVYvZfQMuTjXr0ZiQIF9jIMsnpl8P Cjm9OsdOWFzVrWrGNUnbaTT5h01ngu8z2z7UfD9oO1XxzUIR0ldGA4w6dt2BgyXEfMzGM2oWlxwD eERmL1X0kry9h95eIYaXIngnihFD3DkDrRvVNCjIQHqPVAl3tDLPtyMTPxmdXhKihlFIBH+VhjBk 6SZgo9UQ/d/qCoP7BcF8qvf5Hmd9VRNsF5qkDmwJg5hYhLJT9DmQeEPePMKnvboFe7p3x/peNNyi REWxoLiLkpakZ61mLmy+SGJCgJ4QcklTNgDp2bu49aXegtuGh8dUU+lCeEJjcyjxNCOGltUSjE8P 4eR9XGyUleydCY3ls2E0gXkNgzslHLemDA8y9+pkUzgs0oOPBanDYZlDB8SmLv20Va/ZcjpRPSEL SreBa+tWuZY1fRxI/LbsevPz3nDNe6rFeQLgViiw4MiKkiE0cpXbjJtGGy3+Ck7S0GdlFO2wpYdV YynNbq4BsI1C6KJ4DMFX45ZOIC5Ybu40ty2BOWTCGr2eoLI3r0yv8WZvJCEGFN+Fjdq26QzHZPf3 awBPRnDgOvz9F15DKsHsh9sbab14r8G2vR99f4yfWH7UIvGv7T9ho6qnIJkHfNnNXOh6RUJZQfDo Z0gZ5XAUOeWDVtJp/TMbRxgWWYIk8dmpUPZtV33WT/bqHB7f1n4l7lzra7VwJd+/y3Co1j77pTlW 5PVeTEMmMfqU55wI04618tW1LufaI0pg1KIEV9BpdA9aSzDKHpPGI8zftDhMRvt7B7gTfTBzXp9t fjLYYucTFkJW9vZWtBqSdWC85/ov2rW7FoWX7eFAtfqcjweKGBDdlrTMhkqOnWBnrdseWX/XO16e PVocqkOoE8UQUu34A1OAnZIFxn3Llw/X//qOuzezmHje1zDU3M6pXybXdlZ4ZwuZVi/VoZa6EuIP xvyIg7L8ogKwI2RK3GYAQ/NTQLm4ccpjmHH90FvBnds3IOhUXDLQYRZ92r8fO+jBLB8Ym84g08Db OmujSFDifCkGLygeteeGqGKyVN+VRXZoqKHfCK1gFI/iGA58renhpyo2Bau7noWMKNwAcJCJmQhu 4BSwtAq4L+35FNSbMWhtupUFCXT2xSBbcYLIGDoVlAlCNOM/+9cskv0r/RJ6Kjum45x53FZEBuj2 gf/U1E07tlPyA9QJFnzbqa9dk/WF//qItf/y8ruLgK8xqEBDCKRuBppZmtDx0wOgkHXjS8VjiziE SPIT/7FoC6Mm5yUCfCO6EyytwR0OJiJ2Nw+XTzB/NDyj7+AA27TQ72lJirPYhG3zgxzFzLghm0MD wn0w6A1vDumuz10uCrKzkemyOxi8ofK7PkCQ02XAkEUKUbL9bt2fK4eZLrdp4r/LwL2mRwllMJ5I HR1M0C70c8G3GuUjRHxGNAah/7VkDMYbtDB/hSgqP27vHuYuBm/ki/4igV1QcRKExEvzG7iNr3fb XY2+Gk1N/1ULQSP0TE3khAeFOBJUG2kFu5vplzM/NnWeweRPGYgjWBWPl2e3YxiqmphyvwMrCVym +E3G6GFMCl36+pQgZVwvz1ryJNsre4DQsy0zyxGVNHfgizKDVMUx2dhHz/5ACP9fn/LqXRw1yCI/ bGvvx4zB/7oqt8tmTk7WFRUYVrEktUUkoGLi80lGxt+BGqLJd1eldO5ZGZN0IF54ud+DVAFgeuS3 /HsPww+mz00WjXztH/v13bzjfSpjvFELjjfN2XGBKzjyByOSyL7RvCtHEmQxDY+Vio8nTDU2eja4 GxMJjG4t0pn+V3PzYuRQcQUABBfeLzgnMaqMmdsEMSMIHyfmdJiUIinBNmBChLqEGk8bcB8shO4S U7y5BeNePZP6/mrZoU704jfvYjYpcycUphKHssPYEGtNHA3CLj6i4hKJ3mWQ785gxSLyfCsQiy6j fm/7BYgLKb765BMexVx4AVR3H3/jz4HKcYLV/2PRBmuvCaGcXHY+k0DcVP44SdZm76rZg50B3JB7 9+s5m0yVWs7k+TjAyGKa1AMoKzYkGWh4n9CAiLbCqFLsGgVpVog2+gIEZVC9knO/hJw7Kd8Cu57L 7hrXcZwey3pKOYZEM2o5jEaUOHdCfefzX/JogwWIB2mBTYuE4ATa+AwxUrrHOxKDleCAbLq33I8K 6cGFCJt7a3eMuKfcYDn0wL9VXcvJgg2ImGLKRCD1epULykR79BPEEGX3A98jOe/LpmS42A21V095 ULJwMbUQdvm/oqAWKUX8kVW8l1z1DNdg8ls1t/Hm7nkGej++VpSbhnEjWLbp8jK8uoYsHiCuXJVI Cb16kzOo1vuMin1PqQUkDGY/bfh3if3BqgPE7oA4x0cai0QThucdHGh6cjs7V5fAPQ6dkujDoJqK J479G1+gdOJ+sOob0YGWwCH+2s7iRx7RfdxTGmMzgoDJvZMthWjWP+6ql05s9ylftwFP18zGIg+C 9h5FidmRX26Yx0Iru4eGS/nKhoN4weLPSBsXBKbNbblUZCe/GIvvAu7A3SZAKuYXpvMKYy8zA88J wqa2NGT5pybtR3p+4uCL1R8FoyZ5o5FCehLckxsSFGxlo+Vdo+ky50hU6xXYkDl/gGQdPXDXPmBh ywWumxQtx5ruEdy1MCE6KrgD1sBR+ep9KC6bbrxDWZhtOIuROdBelN7GTKt8YS4/tyEIquc6u5yG S64Em6I44Jnn+Xk1azaHZZMbdiUuyw9ZUIaetf+ekCl5RQ+AxNiOAuj+ADirbO8xs2GaoqOzzuOa ybehbU+g6NV9fH8loDBb5vaQIP2gk9HUjRzfSa2HGkn07sJiBIpHnYVmywOJV81icnh5F9BYW7Pd eytpIqWgkvaqSO3pKI4AsJAKR5/E/4SCOZMNex2pr8kq5Ox4jpcmq1+FEcSTi8lQl9L3BkPVlvbB 63dQQn2UskymlLus/pIo9b5fMh6OTc2qPJqvia5vGqODpetgZIjRpf9pdqh/EitRtC1deYMFj7i/ zh5QlcVQGzv51Z61GYEO3MQdBqLgXS3UjrU5pbcU33CpqD6WthwIsKCUOJV6StZHhoOk1RxQKHOx 9qoNNyz7tWw4pxnqX50liLhB5SK0kGcU51zuHK0VWnzXpiCdZ2H8PKxWW3y+SmS7jqSA9Yv6ZKH+ KOZ5X2oLLoWMtp/EHT5HmdRr4HlXn1sJ0diWE5a7X3IALelqDrn1977saIyeRa59Au7ZBsbdM44G QgRbbxEmD4y6eXezRrNkollOsNC1AYi1S6oWCHc58MQWYQ9iQ//vgISRuHEKwe4uBj/Db/dVzThh AV0LA4YIJ7lzHN8rYSqL4pnHyw7v6Bl1GMGjQkAROT7CXJS+F6K3994QDucfyQIDVBfE9Fix6J/X Z7VX8tY5bVgqoHyItY6op/IqXCCmP0XDfcOu/JXiarA9BCehxxKjxp0HQrifmvVcrW9viMt8hqIs yg2rqggTElNoolLgd5aM1IKaFHQAkleoyAmTI5OVjHmM8Uog/8Ej2AnKWvciszUw771kwJQEnkzG io5Q8fvCD53RBB8PBUJhrKGGBHXkWHwXJV5jhLlP7FCzlrSrITp9SVggePC+gqqWm89+xujsL9iC DOGgNxRjOFkrGleMTsMKkb8+qXaklk+uj+D0wanaC48lJUzCB590L4R/XRsZ6HpofWA9oCSDqOY2 e4yv3kTCbfFvn+HD5tKyWcnMO+d3eSltEk7Gc2d9mtHOHyJb1p9tYWohMEx95o4+l/YiDEuLOt2x GC8HH+sSTYIxQxnYwJD4Tz7BQJL8PbY30N60uzg6U4I5AWjuhAEc5xMuFwohdEHXGOEOvM2l0pe2 dyR/Q/oCPLyMzKI6pWzIQpAIcG5bcXZeMFSlCE/tBS31DhMY+DPTjjWn+6+rLRg7FR9Bsy5eQYWf 3qODGVzgJfc5vhpYIAtR6ubNfftdYkVVGwFeCWEjhF54X6JyXii6S0dXfE5fmJ/BAcpL3fCm2EOX us2YWYkKalc+pSGgFjRWK0S8MrceAGDd5x0CDYZ9EzmuXdNnmQui6h6TnKjBCVDsKax9EC+JXXkF FgpoDtlYQRmH+47jOBCWOaGPByy+woALj5Pq/2niB9FupnelaKUK8383c5kWD98wwJwtoE4zlkGr Q0ip6teTJf+P50Hr2B0DCbpluaRw2E+uWNx9kYr8gCA/mhZdqc53U2QV+V4Sr9Oqsp45SOmE/IzV L5b8L7Go0ztXDGIpw/56/hG62/N2B8YdmPDYdVIorOxVmv1F0nqVGFbFfV5D4FxqzE/i2is4VAXF 3BAp7VBBTjqhLKo6Hbs9Dmvb3JxOhn+HK48QrJna+Ix3xD7HfKDltOb1afcPVo5lEFPo5/5F9GUA CeJQsQa6Lx+1xcGjcObWf+3XFXOFijvq3U6YqGFv5jpx1IVCJ0MVrVBSdWm/EVdQ1QqVqKGMh3WM BE1Ts5cUvOdul3iTyCcHGe41Txh0pYPHeh2Zj4KeUVtCOoFvdWranDmli9f0N3cVZbkGVmOPi8Rl PyeUEkKkgwUZEwdTRi9lCzhEkeC9QzcgC0gGCzHwEMPA5I9So3V4lEgmsPQz0iiBJf2VsaGf0WfW iSBrlrGD2F0bZup4TDsN5rQA85+afmg3OMcw0uKJJMSpMKeyLFFt8DNENi8jmrnoGt8YI/8oxq/Z Gg31ACcK62qRWhF1U7+WfKEwc0bPyDRUwL16QCKN+o10FPGiNhQOVNiWCvKwUTnLlphk1mG8xinw +bv7YJkr04QvZylfmEaNNdMS4pZaWEt59/2arVbzLlBbVR5xbwBJp3gDycrQG9Mo+OqHEktDfvqM jGw+rcNtlehhFLGNrqePf38+gRJcwYbQTZzzrfz/EXwfT9ExF22ULnAUgMkMgMn/Ap9qVCLGq0XT A6j/EXJueEDfiBuYzVAu4voYWoVgb1elBYXTbm76NGAont/P/TtZR/SkM1l1in7UpuzgOtPncqgl JWzrB3vLjzvJseQqGGP5ouEdKkjTIQQ1y1XJLGeX1STNveOJtciVjgDiMOF2WbZArbq2f23eodVk 29udrf4i9klI4fw9p4gQgCUNtSX8nqUJothrwpleM7BtW+cJRWu3C8r0SoI7W6ySkicAso+MLTiL Ig4yaqrfboQUyuEi4imKrTZ8kXqSjfsrahRy9psft2EAmzb9C9HDdCOdJTcedEzj0A6K6YGKVM8R KgU9T0XqLc8D8pmKWPyxvdVhvtfS1o+LNpPnhGtD4sbKMhEs8nR3//9x1h3anwSxpOBux36Ku5sH 81ZX1/jz41iSDwNOswqvKuEw0IShVNBkd103K0V6ZmtMmvKPnHQPSgz2bQCBdYVhTB2xJfuHe2G2 +6kaCBN0aSEneRhYfMcEOAiMJmpwOjslR5OXeqA9FNelMbjIB8OeAfmQ15/HgJ9af40X93O77dKp JLIeV4r2TXdpETHk3554cKwtZed/G9jLdcUVaA08ZWnPYA87m2cwUncI6OREr0WdVyXsmVLd9Xtj JtbbCBGLDkaib9TvHLDcrdGZBI5Z/25DopNE3eFrFCBpyYcdHpppBK7q2MWZSJTONYxSmXEC3uDM NyIuYWunFFg0CPNCV8awN4IPiJQvBfgQPtF+tRXEAoKfkv7Hu4HlyPrmeY2/S/C5XPXXrGp/aZk6 vQZ9w4VsK3G6JjJzH/jQiy7+eICzB76w0CZcXst0v/yDjp8ext60FVwW1DqDm/ghb3ZV7lAd33pI 9YW2TCmNXUwLsOVQ1cGkX5LeBZymthtGi4zWJN1JNdA+2EDQgZTeP2g7/h1Cnr7n3/he2isC42x+ hpNhctygT/Tl244a0TgACMy5bU4dxFT4b/UUJ4u9Tlb75+4H91i120d8AqQWT9Duo4iFrsm85LNI jo2En9FfTMgHqzEgNilCufs+yHk9XJiN/gLemjqdps5oaEB4FKczLBwn9oydcg4pk+lxMpzoqdUT BHzn4/P/3oZUhRrPoKCaXbNCIVInDXXpaF8VWH2ijZ/Fg2Eq2m1EDWuxMaKryQE/4PjigiLTlVr2 xlCgRWdIxM6MFa+3X/ZAuAA9Q9aqa8elZ3RcwqYdsuVTTFRzBXEJ1qHeR/yGKR06m+Ot/y5V3JTZ vKttVAO/IeJbylClEOrC0H6evQCx1wPpyw8gk+MhxkdE2C0SfLva0IxjFSbBN1ayeRUQHIbFyUCy 1Ydgj2taD/SlgL7SvlOohbtKYKu5DrfJIfkDXfiaiza9SgyL+KrfdG8nJL2iZWiZts9rBavIZvdc xFwMy9xvBvZb9cAEkYyBxvendyOrseoFRmj2EwzL4crYcexmnyP2KS+8KpSDVDTq8HhbVzyoqlD5 Hy9GrFfsuIkuTtKwsbAZVj6Y3T5CrAvcRQOw/9tPYHkfAgJMse8Mm4gKkOM2WOqBOlPJlsJUdWlN QXobyjl8l4YUZzlIUULyW5S8tgScfmkolIQ2kzjlW6ZJk33CVWzmU8nWWbPvUK3CBOL8K035QcdM W9wmXq4YdJMDhAqWu8k9Y+4FsLASq7fhUpiKXXMzUdUeKfQMKjI+Pv9OpO0ysGoq+oWbd9/vUL+E iTuDCdi8t68EJFR5yuUhyRjfrMlklc2bcSROfAcE5wSt4pvN9rvxuBaIGCqzCKSDiVZdjZAKB06J TrmF9XKh7G79IpUmA0LIZmX3u+Fxw7y8RF1cu9N1ptxUuSKxHb8BExeID5XzRVL5nKWFDmUiwYVH BY4lfsPdUJ4UZGNARlIsTR4K7MmmlciRNYiuHhO3aMHk44u/aGFHxSYlB0q1FrfTANE7/mtpWMza 3jev9LUGD+Gr/Rso+CBtB6TP2h/+REoG0fXfSoWTj0MkhngexWYYvXMh7lQQ5WlFTzOBl4yJy2p0 zm5kXyCMc1tL/0NkzfGzslAcJ1GaFotS2xJOG3N+2SPIlGxKOkQhXW/UvhzjrOZ4WXGeWgbwvWr8 K9YT4XNYjiYYh99VRPWR81aweDVHISSLZKLwJHfnSDWURybx4HZ8QQbmBNOfntFtWSOvn7AmAYhF OxnfLIHmHFOd03SO+zMzC583Mo96+WF+xRVZLE40DudaOa3QgbMkFUoT4ggXdbZqZVzQnL6kXN21 7yu7QOrAe1BuV08TC8fInPMoTQKWc6bABh/FEMxBH7b/CX4y0k7JcOegu1vlnY+VA8FypOrBdwH6 uf3Z2isZLqbSsucdZ6NNyLobxsTNo0IYll1TVyyNi3cOfDt8tmh0d7krPPAZlJhaXKE3lOnwxAZt gmCjL3Pn82rS0/bvyZMRHCbwfEiAIA6lPKZcO0nGA404PmGGFLgUknYW5vW+ElMypHIGZkIh3W50 oli1eRleAjswYFiIa73Biq/5ZJzEdhD0J5qSmkNWbRtLCaUnjTB6P/nmVr+fT2il2wfKk/1unkp7 y5F/QTi/Cu64ObgoBQ8mNNpLW6FcuOencupQPBeiuh3EerTTljb82jUjeZ7zlk2QY6XfuwAmb66j 1xFjnv3fj0WJHfob83lSIyMbgSv7Kdp1ufX8oV7MLlQj3z06yKQ5eOXxmzus53bI2XSd1Wpnbe8H 5a+Q9X8SucAmGQB6TuCA+ieyoDzk5nfN3s+uCNMDuZ0KEAKayHCxvp0ZvJLEXgm20Y6YnqusHKAx j1o7O7jvcFazyIvzhiMX/jRk4vMB83rI5jCcsr6O9EkYSJ83NM4Mr8q0ZNiyjpc+Ni3QDodoiE/V cEHvDRr6T8ZZOGjsMjcSt5Jb0B8NsEph0ZBeCA8ZlChJEmS4qPogLBExjC6gQk2EIwGaZeYtA+h+ OJTdbyuuvR7vdtxvXpyZaKP1piXB4Dzw2E9aCjCDR8FDhSwHWAgURC5vmv27rGNM/PwHQsVUx76I Eie8xSJd1aY5KnqAzEypRRcfi/ENOCsRehYhHo46hw1d4IVVg921GxsYrNQiANQheLZpij26cDha GhmyXQf8zKPLinvDsdc2Uu4SymeXUVllJXbSGO9RkplSI6HUoRAOurzhj3IM4pNowHBgU8BXYSjM ENXJbUzRPWR0kfYUos15MYKQHDHLPqccsSSU/waDwJnRkY1eu0Ps6dh/7+wN49YwYJYRsJdoVPu+ i8JfeXLm9zSdJtiJogMPCiQQ070x2lXYxeKFnY9YDwD66MFodv1EGGVQc5wAQq6Iu2vD8FmyFXWa /TR+o6M5FskQlcoC4O0lkCY1b9SlznAC5OC55AE7BKPAa2RVQBVkaBjIqmZwxPw+EX0EME2KKAq7 7vBbxPlBLwdey/WFmpjdZAdCry8jEYe//s6sAAT5XVcySrcUB5BPhA8eZHYD6y6fE1m09qwxvhCy OIVF3fVS5bCdHVStQPcdZJyaaNkx1mkhkuI45T0w8tazVqDX7V/R8sLTk0Hom3fo50K5+WTx6Mak XqixAc2sG8y/uDjtQZ5HtnHVnurOq65tqpDTGlI7s4JHNJ+7gthJeq2vjBGS1FhF/fi/SfZApHUF me0k0pmE64bzCGNFMckTsfeo+yANY/1ysfHOTcbRTftVe8n4+DW6tKfVsr0YAal3vEaUaGKhM0nm Sh7p4OUGbFZft+jKFdoxhxXIY3doGWEsrxqjkamYmbwlL30GRX5iKy4vS0mJYBkrE30AkfcJBP2R QkNmLYHSj2bSQquHDXaJZ6oNyTMX1wiTsbdnG5FaGOC74tFZ9dfWwjU7Yz/tKGW2WT1SgG1DvmQo de39CaiO0OnkK0C5TlEVRVhdCVBq/WWe4GBtEj1lYgBi4eHKIRdimaGsXdY2ExpM2E0o4Za2nQzS fX27T+sX2KgVxKgYGIONQm9+SEDvRLbIpckPB4T7HiLb5pgATPLcf514tICLfxcr+ljoWV7ooAFu 2vKMUAosCTJrmtitlnUgPCo3jX7YpzeCB/uVIgIGNLZbw9EvoeqkS4CMfwbyPE4D5+ioh2fq/UBa 65S63YDxcV4sZW0zV9CyE9CIhFPpeMXWLfy60EWnmLqCGAEhSwBThdPaJ4vZpioWp4qWfUzUgjHb htUa1LGt55mCX2gP8TK7jXQRh6izE3GlE/s5iP6dHwT9gmNWc+HVRQC6c2dHL+LKB/N9cj9AJtFF Jts+rDnyVnJyX9ntPJTXd1DDgfeqeT6YXkiQkpaTC6A9mtVjYvKKwz9CZWE8t3MGFJlHisuBP4dZ 3/RoP7g/QBlL2V3PrMLC9yWJhP3WqNNCCNwolHu9Vqdoft1uHv/6AUTb2h28hytGwYdzs4TmpyXg PN3bQvEcRenicVUmLQVIduTBNXjrr9/bCmzepMS15J7mC5REbRLEI9KBl/mDGARUWVUdTNnftppY BkqrXaGQhtSPb8l+9t2hKJoKAL3Od9l4yX7IABqTICPJg9sg+p29hPa9/uquHjwHYtwXJLfAzUrj F27/4NQfI2Msq8NeOvRTNqU3Xsbl1dpYgzCcA11OQAOUEpmGV/iN16LW8dOctD2zd6h6b/h/ACOb U6wXhu3GqmFAmIujwIZ++jM36mAzV3R0tNfP7Us7Zn/tG6gZxXyh1OHpK0JVlKaUpKh3+XBbucl1 Ms8lt2eOaEIcFacn8cHN9u4gTECtTHx7+JKICnN9e2rOyl7EDp+6o6F2k87kZA+CgvN+osMgwUlw QPjL9xzpFNazBfrC+pLhIxQyvQVUExMhWnlHrcAtjJ4hdY+PxRlXQ+un26JNK3IHBgRbew1gg64y EY68elc0Vq+vWeChtunXfBQA6ERkyVTEYf6MvwUnM74A6mWDEHEJ8VvQvRgmP6AGnVaCu8L6po7J U43h6ef3P69rqQI9aIt/KQjBA6v/j6H5T6i2Fx7Rhgz5OlmIO9wyBzsUEQLYwONg1JtQrbQWsj38 JMTxIwIsoD+PdaaCr4QafW7WZ7+3uqK1qM8EBGSS2qfIYg6ig47xtDc/BCEdCFplaaBnrhwcihkv czJeJqcaWECpVKaPPXmKWzwq4b3xJyorfjDLdikw11YonQgfPvx2OEVyQMswPZcLg1Eg7xJBuJz3 p6DGlxMf4qeEy6U0REoELzQZbAVfUB6rvMoOfO8LawztAaeot8skOMrvwoHL6YI6QhJInDy/koPm Nz56uWa/A3o5n7++fPRYC8jk7b07plPWQvz1Xiq7FgX+F6J1p+P81h/WV9L8atss3fy4yVnUhBVV CZW1JzdCC0d1hLA63zYo9g+DZhU+OAEMxjrs7zew36VvGn9buTFp7CfiQLsg/LYXFOKfmGgWRF7I ePKaGD0xoiZKA1+EC8ORGmQC68IZYToPlaQGAavx6Fqh7cBjOHU1w2n3+0+hTd/WWVf6Ig6yT/K3 WdLRqNx72zSHgpRxRqusKB2AiGatCONXFeJt9B1HFhHL28oeO5to7/jt2CtmlxtnwHSC5bjCwD6X VcJMjpZN+Uth6RgnTQr++y8I3Nn2rtdO0xH38UvON27D6ADlT1kVoTUseU+G8v4pqbuJJfN5UoZx efXV0m4euZgk4nhzDGvFFoyiLtN6V8kotGQMRc0JEHgOH/gYevjovb9BNOotEuK8W2+8i5dxSuVL wRC8avUtJPe0xS0oQfPYSvTRoCZNtCEODOlswSkA/yApNtyadS2cTCHW08jjGdB7xvtwwR5JFTC2 +DYS7ozYI3wt2QQ21CgeFzBZ4yGtDNRwssbyXWQkHhwRG07FkicEwueOhNBH5suOoaE15XY9g+Y+ X8Bt+ZXQhC1DM1ec8A9uAruDXw0Mr7KGyrgxu2N/Zx4qUrpBtoz5NSBkJzdNhaAYwWMNH8H+Pf2g w6uydlFW7892OJTUsqcBPeDXaQPlaw0mDRnedSI23cfb21V2Bnm0tj958jXkA1oEWFnfmdTu27RJ p0vbUJIufqMmnqzCKfNWtzeRGY5sIYcP+9litKjzsRRSpAHg5xDHajuHnYa+fjq6/PizNnwe0djz ukYP9AAnD0cL7MUFbtSvaTOVQr7i47hyvlOI8+KAdR9GnzQRwxGazVmVkC5Elf0jHhh3usmPvkPS CaNnV4Px0hnDkfYgJKj524u/Ka9At9zIgw9WB7ldjV1BEe40xDD0gEf/CMgf+OWkhcrfeZZ/FDAv 1z/dKl3V5VPtl2E10JKr/5HB6hB23kRimIwB7nYvNQfNQyvFWuerQIc2CijyHgdN6iLZkdVFDLlM FZ4G6rswtlWM37Qx9IkVNOGy5OptN7OA4sjB8AYnT2DRrdcmZjgojBtwsAAwxWxRGIcrxNndZOu0 pHVJ4v4SsgbDptq1eeXaSkHmlg5xYIPTAz1YQlaaradiFb9vDOKLV054Byt5QKPbOSmeV3bIR+Mz zCHX5LHgq+4Vo3tgwZkDA/zn+GPwScWn7jY/2G639+5ovdX0a/T2nyvRcG3/whljrcjAm/SJJ3ZL UFWgSwwwRrcrKWcBGapnWoeHTNjqUwe+n+8ebw7wxBtbUFysDXrK8OYU5mRbbMpW60Qioap0KVPT RAD6uZIhRxHv3iWGnp9LBYuc2E2ApMk2+1Vh8KZMSixv4la9bqu/FHgbDuYdMLUMbD/wX7+ZEFjC W+F/3H+HZ5tQmDu6CLxJ6a5EWJbsJphOikYCXaPeKhqq5rtMsw0Wwa24xfIG3jjKJmrTYd4OaT+5 FkI/MOSihSClrjv10ShdfZ9rtY8fckibXv1uj+6HizhwCcY6wfgZC+3efrl3vVjvBuxO5BszyXl5 JOAlO79VZHfuXo+iNzYAcpkIZ+tswVHu2+SGF2QwwloeTr3bgeBv5CshDYTxikR97jgHRa0wwC57 tZxsPIdDX8Z40IhFjwk7Nu/8Ut5lKCbr5Qnl+M49wZy/bLvIQFp3mt5LQsHNIH9+YpUTOJ4to9N6 ylCvxUbyJjAy5NOdropoTAsFgTvxZ+sE7aOTHX1pushejA2nVHkqXGbbfo12Pa8XTUkecyIaudru pBmy9OP0pxx0uJcOrgVvsJQUlGlvm2M3UDpzc9FcXFJ4LMVRafJXKX/jurIl6VZN0SUwBptZrw55 5YKTmfowlLYDu+saLy5Nu2j1QljpyxL846zzYsBzI8qCe1GS1plOmuSYXVGVHj/gzs71rEwMJLUa WJWPWKAGM5V85BdTEnVF2xRdhmAYxRoD/dG+5Y1HO3Lm+9Mfc58uQvaxUjKQaGSG+XDiOGq4ixnq F7HbbduGm49moossVXutDtdq+3niz5HNfaega9FGIVZG6VwpLRg+1fyNP6b6R0AMkw3nKkFHVNVi zOcVf8BNyzDSCRxDVhfo6v2j/NJkGl8pWLCB6G/FgQKOfmPphA9qCyt7F2Q5ewv4wobj5zZSRceA HMp6crt0zPkBGdEmXN4doug7wOv0IJ/AwByeMvE9jc6KlvSgBPV2y4sC+wPMz7pw2yxl7+MOQeeY SyOCNspT37GHhsgqgQce3BNA6KV+DEXtAhIuBMp0zDwYHQDaO8P+RljzUFRhrOA4ai8nkiuh0U4+ 2wRyamtZfSbAhPlu+6H7RYVKTQlJUTUrJ4lKUOTC5+BydLTCdJwUqSUYLnZHvxjGAXM5aiWLWTXr MdPTslph9E+4AsV4aaIzgMDvybOVJ7VD78q4hQ+pO2InMZGxN7vqQKkM0plZ+08eQDuUjNqoXCo0 lPTkZnR5qxjzAgHZCjhWDPR+gpW3Ehxv/0oIdgFrCQH4fSNjPRTvbUclB8hus0v5Z9K1Nhwbym5D E+2ntzgAP5aBkrz8lXEH+2sngHnVMjYTwWptp66snNbhKKaw9HcZiqd1LoIorrgmEaFnHwav7ecC 51vweb3l+sheuV1b2EJwd5W+FyYHU5ImecCKBCZlyPPwwFzmibGiBlZUk5X5l9JqMa5CMkDnroi2 qJT457nzrHqf5SXUwf2Ia+7PQO/oKYepxF1Lc0bpG6P/VJhGZIZwwtsQl4SMYjyRA0vfzeBtsrO+ /SsXxbxGBiI/prlCSVLAPv39LyaZdsrkkeOBGRlWIzJiMG2lBIvNJ1EELyEWxLV5SVoBMG1UL3gl Km8u5tjEVkp+EOgsTBbTEi8hjUDg/Ng7fd/lmGWU0sToholw1CHVuHlhQxf3x5ZXrhrrFTpIgOA+ Ia7hk/jCC993v3LJlRWrukFcWjYeWOW4g1xh7GPurNy2gb55rdrM94D+9I7CAcdgl6PmalQF8AIj 4CIt3d71sKX2vN58I2Af4R+Z41qtdj5IcI+fjP2jF7onz8FOeIhC6d9ESQTBrAMIpaGOHPe3XjIh sGtKuOuHabrIKmjSw7N2+jOrrNikQ45h7doIlXOfjP8FfJVRM3P3iILCcpR4bmKhIV/3A6lZPqVD hrLmjkTrNk+aHi0xKTQMd0iCwMBqxBRzYxs2HPfVCOFILeub/r06Ic52jiuBOl8cGMOIcjD1bhkW 6SQXrlRDm/Q7AtFctYm13pS97kR05v+EBeaDPBi5EcyNTZfRAyafnHVn4mfKDixLPHZHO7dvLVKP LIndrnjPR2NbRHRES3hUV8BAri6/UkYTbx2O99FnKe1L/f0o9WfOCdcQRPyrHe7lHjq39jZM5u61 Fq5IXw15aI8sj/lUraaTxEhYGMX9H6QAbCDEWqedidK4WvuXz5Q1nojYSZ3YDBVMLKQuphIpkUZ6 iiCHSHfVpLAf07mtZWD+Q/teSQEn/I7bew1e2+SFDBHDtC9r/HJTJtf3I8EYcg0LNsJJjra1hl0/ 7oVvhZWXhQJiJ89j+JWCPIjyGCDlED7H7HqF/DZKcJkziK7VOv91YuWjT94oD9EwCNx3BSP2yGJ/ n0f0dnqj1qxbWZRu20/LaLvxilsLT+S0bHq6Y6QS4qlHguU+iWRHFsT4xXDCjkFNihhftW2soEHE fzPIKxGsz25EK/c3HkCidM9Oz/rexahllf88BSC+uVclozpjWjDNYJZ5RYpeOuo81ecIKT3CvHNx HYIoz1z3H2YMfVIl46ZpTqxgx8MW4OSLFc6on83/4APxWmtrCW67YxMk39z8K8OrKvbzqR0LSG73 hAGxjzylUuOmRo8GZcZClLo/24/zOqbAN7PFGtfUgvJLGlkURT7iQCzMpsGT1pARV5n2/v/qFuUK 9i7qsfSQRs3x/0vy57TY4Of0JWIrV8bQlXlWsdgJckW/bIeWdl5fwBwzSWYe1+82ug6C07F3w7Wh sWBKgrLI2FJHxjx38OsUjDu9ywZUXZoXULJmMRCmYc79feJHT9EWAO84AnBrBS37Inhpnjt9XOvd I2HqhFkdKhGwUiWN4XT7L0gGq3jFX9FupLdgySlGq59en332oi/KKRCwkIeFUd5EF9wBXIqgTvOJ TWcEseAJHdKwUzmCy8JNgu3ZIK/fNOxQ0wOQXEsSPGQslnPYBNI4yhNyg6N18pDwzjemx8FBo4LX I1ccG7KVKMZtiGl2i3+Pf12ozU3WhQub70h7n1MN77EdjdZoz6kpJAVWvvP/iRV9EKJ2mBLXtVpR OKrt3koS1t2I9B2nqT9O4A1y/l/XqNjOf5jDlQxbiRZune/tTzSFjxhEFXO4zPz1JGrdslx/++f0 3lSLu5emSTfHN+altvTq8Tct9RYcOU976zaB8OIIv+/AMAoTgtTTEZUuXcZY9KRikeZz+cXAQIRK Vz5ibx3IyUlzKvsF3wtVzstbczFrFMIXDILezMY84+q1C3FP9qq+ZW2dmiBybqhcL9Ippt7giA3e 4rsVKmc0e7W7lhbf9/uAkgbR7q9WLD415y1XaXGtsjkXk4pICk+MMFKKjhJ5N2WYywsCT5wiKU5m cuJi5oipVhvh+B093i8GoJoKe1EyVVi3C//8xIKoCSVUQsgUOBhfmIn70+Hh3wtTmOgW6nL/56Vn TPwn8DNRwdWU06kGjBgAJHD4qhKUfIKSVj+MLM7bfL2ZC8ijtc3tIc0h5KJCF8WBLgk2BOTz6ICr 2HmxvJ3+x/XNbPIbs4bg1zrVxtJmfR5zPpCQnQwVOdFOdV0GBloE1VYnzyIe5PRC10wcenqq99FV nUzQbmKS4de4v7q4UNcGa+ctSYiMiIgTt4E16KxRMho8MFoq+YI6djOo+Npjxbs8s+/ST+CTGt7E IxJUnTQDOmsDMM2uu8K+KAF0jIo+2uA/lcFQv3ezdR9dcQA5Abpl6KUx1FhGkqEJOSAgWl2RAYal t52tnHLur+Wj7zgybzU1R/6LVW7GNU/wsvQQr4FAhrpgrHcnOk58EB34VLCyUVsY3SDIkrTyIGh/ S2NnPDQvHEmkFfeBmWk2rWOnVrXLcWfHASFfQdfhv/U/6/MQahdBIUHp6DNKVgYEo56MxYvavXEU PaC5l7KwW8r3aa95UCMGia38H3mMjcqUjYWNdKDbMyFSv57m3IOuwDVILiGjfduZ0BBxNOZGF0gy cwFrc90ndHM0HHvbE0Pgl9gyErsD7eq/nDeVajS+9u1CK0Mc6k9Es+ykRxD36BWpfQfGMuttn9UF 8/rR3NGbAL/Vw/bV8fo62vSC7It2T4qAZ76t+4/TqoEeC+7KktNTFX89x8A6jL6OkPNkaW+QyicJ RMX70byK0O5aBCj0iiLv17wIiVUGoNy2RggtKXM2Z8WMOIhy3fCUhXtmwrT5fl373YgawRX7bJt/ A3blgyhyH+nTcRQ+7+mZt/XYbnnKDaFWQTV6wHane7EJq83Z4huJX0X99SCPADQzHjesUw9ON5Uf YNDOYBv8l5/2hJ/d/KnC9erNxCpMALxu4h5P1BKJymApbucudjssrEsFkYVSIPsGe1R/EsTD1RVa NQA2h5Jyckr19sUlr3j6nJwh1S0X6KyVQT5HEWtx1LHz8FDTfzmimpbMADykRxbcof8PAB/OY8LC 7AYje9ix+IKQ+27VW6vHxRdlpvP4vACHNoJVV/dmQMxPnK1awTuomVZIfU97KWJ2UnmTXYz61oSw sNl9+t0G+dl5qJ+bBmPvndDtHcIldv9cvZsdd6XmYQDRPCQl/H5tM+DJ8WK/mylo8oKZ7dGV3FrS Xf6nYsaxUY74IqnBvH6PS468U2PkO887ROj+6mMSHJigSn4BnqtBgYwqAsfa0iab9jd8bG5qw99c vOLUzZLzWQ0Ckc22vvapGOHlZUHG0tXZmyN3qEQifaXpZM0MHp/VLibFg97sorSiwPRvW/Xr+a3R zEo7krjpAfk/bvJbZRLxS1oBakd/aQxdG8mlI/K7vV/VNOVpwJl2/aAq2v5Zn2B9PuVrLkkRg2xd 2wBhOHxi7PBaBFR/+6jFjTvFwAtxdPS2lWK80Z4OUAc5mRCkPPIuj4PbnfRp6THaqyle4sJKUEXU XBimkBraQzdoA3I5SuZfwywy19nmc+8TTT8DfvodyGoy0DCb/L4GxYd9jZalTxVr1nUSqnwKXZ6P 1cClWVTkPcIN/d9lL0aiQAplkNce4vIKUFh+eVR7+39zaguRuzMcHkhgM2a7ieahfNvNoKH8zyJw Pwu1p369WqAF4DJ0omtwQEmflOvG4UXkT5sruKrKUxY+qJEc6lkQSxm6BCV2Vv2De+wj+/gWZcMt EuhSr6SD2IZ2pwXXDzSPkqSkyF6Xu01JG7+46JiZIbsgMI4muTf89EsOOyNtOb0j/6AcH2Vfid4n asauLY7xWL/1Z+mNvSWZZJ0gQ/OAVqbfSXz695NofY+cVibN74V1SEHPGbbJT/Z4ZhKahhlQZFTW sYHBk1npFbzNZZnQtmZek+P4YpMYVQ7Hip/I7cfOpgzz9uCzcQRcnFo7qFngpGVxMv/shYDYCzKy dXZ1x3Zot5RGf4AwMl2aOPBNhIbpein78hqqkhSeNdeYGapRy58xtdp6N9ZQk0Gj4vpVg0F64eTl viMaygSdbiZPyqE97kRFsqMifTs6guJhq28TB7ptKKKMQuNyuX2bS/uuCr+zglzo5RvNiH8ZcPfM 3hvjLIeEWtOd+s+x2FXRhv+WhzSvcfrbbR3qDHwsW7rKkcEca99NDH/vfTf4oEWKz9O7tuyIm0qx rw438l6xTjTrqVcJNEJk1jmk4zYc/G+t0BonS8D/8ORClBUQY+127YOvgskwc0oqhTUAn0RaW4A/ oW38Ojjz/5Rl5DybuFRGMvzOkdeO+wklkCliDQOet3mqqh0LAZwkljOXXVPWYWBn1+ru3L70VPSv DHUeIgzKyQfW6CD6hB9golwIq7SO2asH6quO3uzAMnSUZy0FQVk+HYD1fWFunH3XRV99aTXCTu/F zfF0bj0bljTqbuXbecj8pxsC96HLo7i31RrKQx745O+TOXycSyu7Xi/2/+Uwa7IoDNOwb6T03NvP O1hO8aXAep6e+UsNu3RHystzneU9c+jhK0UZGdW9g8pI/lHgq0UyKgCiDAcmnor0xDutnNHs5Rlg 4JaPf/Oy7ZB55gfw4o22OBd9yT1qwBulPznjS0dylrKbi1t/5RwjF7CdFaywLp1DVlt4TlEZBNdQ uNVCzqtvFQWy0cU7qu13vA6w5tI9OCvWtmenFE2f2kgxvRaG51wSkZH9d8MlGgo3wjDglPJR1rev HQd43zAAUoNJonPAZ5ciwQEkw889M+ufqY8gDTUedQuTREqPP1T+0tkAV4oyI9gEF7r5gqV5kkQV Rhv3gs1HlohfY50H5jNvRmNV8so8Fb9BtY2joHAnM7vakd7DUqNfIcaOLhCGGx4ZdJ18R92N54Ov PE3OsYxQjN6CAIWhJlGyZJMc/rbPpWLtbhFtpRUTl0uivo+kpISXhbPNXhRoa6oiVHsSupZuRNcv j45Ed3vBvypuUTrMwqpy5KFHGk5T0d1FqAG6DMpZHB2mOJyrVDUwcgjw2PRAo+LL5nbFBL/RDRpq 8aCa2rAtd6nTUPwqrJEVkFeumUOPE7BVSTzuKcL9YcM445MKGlLlpkARMgzHh5hgvjUDnbDetQPP lsAEi3DKk0L/3DAQ0iK8LDxYOvIxAzXtj6J0vTIjCHPGrTDQzSPkvEAEjF4HnEGiZM6WLnnmkM/O 4NpJZDTcG9VgwYsn99eh6Kc8Mlr8s3J444U5dxN+jdpwV3COJfAB6ClmYAIFyyLeHwycVmLC4uNZ H/APncnEVXN/i1zbyTTcoJV6dIgWjrCcYagXLfm9SLAwMJhvjg+HDDFK5FErsEZhKZ3LaBQ4sddd eBKjuf+rSP8gXQmrXV7gFm385nn+uNldsBM6PhgMjZgCtqh3ugrEvmW8hdwptWrU577rvLuSUTCF Hnvdf+vgPQlOI43GQ9sKgoUVlcoq7bn8zi8wKNlFKa0la8fwAP1k7qHHc1ffONjzrI5qXkjoOTf1 DWsjfwEKuQ9a5ols9DqDpuU2X/w7VKd/eb5yPtNDDLV7yz64WhBoPRa+ESAGo+7nvuTISztg3vc0 kF1N897DVCMM9i9LrvDofXFRQquRe4lT2QV2Ck1I/ThkfThmXLwsR8n3/EjH4V79+v5o0pbbk6EO UQfHKuUPsfYvpDIpYhPA7Kq3CGIdIs0PkCIWnghviUsBnvgHfXAtiGztQNC5JKFAs8QEkHRwvgBd liwg+kwEQO1JWbd3xUOUXGTWXr8dY4bo2/W6+43u6RcBT8VlSimrq771G7OvslqwsUdLiuNqSlXV y5FJdHVsQJvYUhlpSoHwb8ZL+IUORHOLwP+Kr3jhg+d2iOLVVyJkhINMip2Afo3jrURZkUaremU+ Im8o3hgBWhkZ2R8oGx5V9VVJlCsGMQDaRY3ylrwsbFiQTgMQw0CY+EgYRrUPjGMtNoReV50XsCvK t98DE2rf8Q07O2u6eti6IwQzX7WT1aY0QYU2AIwziEfKcBgGJ6WeCmebQQnqFOsQJOCmvsrMiLCM pEFWB5J1OWHyxdZx0XnnynA3mWK7kaZxYonwApZ4ZZdniul0boJ8FGawV1PjvTiiszWzK854z+pX 4mJzOxBusaOY55TKRriEEGv54IJgx0jmd1mA3jvgsk2Tqyvvdpy82+bOzLgWCWMHpUeaVr5KUEAP 1RHbA6Fjbej0SOaD/ghFYZJhHEJ0yODgY8yUU64/aXtRxYzoUeddIzuoAyCdi7sEESMu3LEKzsRy yrIlAlxuecPBvIZgB/+WtToxAph+x4cgOZMlKvkjzvLxvr3NxDRrjM+0CYPBpDMrgSDOOCiGkIl1 zArL4Wp5vXcioZjH00AbzMeRKl97bA05dwxafLHEJ6nicDmdodduIfJRmMNgZ7GJpK+tCEIJBd1X u7JQlMwDOEvxrRD9tIx2QClcgwpJnXUcTlZ4DvWJZ/XLTPwaAq/JDP3Z/2Ria46+X9bizkdly7ao fE9YulN6pcr+ZOZg6LsUGIHRqSVvJHBbrT30lE9SZm7HzwAQ/ZvRVLX8Wz2SoP8TzhfQkZg7dwnQ 7xPMG1w+x2gkBVLqSnVmLQa0Mp/IdI1SZ6R5qO8fHMc46FcuVmAqH0Y7xJI3qXKKGTANwVW/miK8 Kj33J/QuLYud6aCNTSL1QRU3JV5TvgKC7B+HIsgkCAUAAQhSiYWGEY2nINWFS1m/3HTeBxMsVrf4 V8B3HZ83WMarEjL15OXE+t2w2MGOQrkVJmRH8RLNMVJjRqDEmR80yXnx/7DV1NZmhzZLXm4CW5AJ 4J8BGDwXuKhuvyNJqNd3uSAIIaU6j2a7FN0+W5RezTeUXdEWhf7Ks6iUqnVGIXO2N7VpyTIAcqMs bMUu4ZxGXv79qrX/rgzoFz7xkMP5VXE5OwXo4V0MYZnnlnbN9oL7AtxWvib3AP4ByHX977yfb4lS a/R+cz3BY0kR4MmPIOPPebj0q+zODJ+1A4OirAhtReLL4DKngVkiWvLSPl4XYLcySH0VA4jvcNrB iiKV4qI5wCvu+O9tM/nhJNqyiRfU8bPBaUlLYI76HeNXCrP4zma7qH7nBn2mqh2lfrBLYtD1xapy LyfJQUJcDrb/61z5gwsdcUVIfi9br3IjNDu7Qn0QAXoYExBgskBnSdCUYDftcXAb9L+O1J0aQBXm dVBWnrfEz5tTVoCWNFB7A+k/k7B7yddpNIB1Eqq10rID8fr87o8kQcoUi+5uezKsAQ5LciWdZ5jh UPwsdmPilnyn9k0ROxV4aTUPq/PLKNBr5Gzqbqg/zadGT6N/1K5oDsANyaH0YPxY5jAKbXrzCmmf xumUwWHTsKEquGW0mMpGkj+i9CQC1JPp2XM45dTqwyw5V9TzOiUJ7e5xr6yTKgifA3CMEDy1jWx+ 3iI/b/wAQipnqkbrUp2H/P3ibA3Vl5K09Tgil3G38FAKLgOvVeSbS7KCAdxaHg94MRzqFgjCiEz/ jv4wMjVUoN8FxEVzsenb0AjUH8ENu4ANSVHgf8swNk3Y8+049Qp2dDuV1QuP4q3P89CrGwSlH6Fr bAnQbe/c1lv54j+hfkGy2SAgu6sZgJ4G+ZJ3aQvdT+XZUdH9RvCVRlWfFzeYvIu6GHqTzce4N7D1 Vs63jf3M0Z5SHFfwxAZOqdWIf9dmQgmc+YPCgll8uczrQSZw6u3W3e3WgbjCu1UUbWYFQuKYlzhy 8F2VadrqdrfZMZGvmuJUkmRc2iHPdMaXg6Xqy587jTp7moI3E9jEg3XmGmuUc81cBf+es3omOB9D EAGWX0AH6TnLBZMihZ3ifKz+IAB9+0jXtyF3i1pUxuWp/kyff7QSWPDm3ALvJgFKvfnToaFwft+t o+MgGb6rdjJUNnhaF6ZkSSoI/z11k11uxBQKhi3ByIgslaz7OI2kshTQZuX+bA2zeoiCOrvJNYQM ZWsB4GeG+7gNfG5V/PYrXgS0EJjbnLxWR+yjCqVoumvSu+WrSHdkRSgXx8+iN/fka/t4LCCxtNl5 jQFbdjZUGMKXZbk6trZdxlRSdv9pq05cBNyPQIwlD9UWKCh3Au0Apyjf1UfKuNoD8LrlW/u0rhQm 44RfdKgb/YopMxdeGZfQslnbM23m2PzOpFRWPgr8JPAfrZebpWunrQduvz9d/WXWneXufOR5y6Gj Mnjy5XYhQFI59o+lE5A5lap/x3LZeTqLJ7ZMD2bThXURXufHhLXZPrpKJbCpAg5DUcb5CUHVvN8/ GYrhmvi9w5mzYAKUNRv19CnUrYVKVo+p6ebEuEl/7U6kvueF5+unAEJdlZYHVGIJYmzqM/Bycmep Wk1T5QMf6sJj8FTXMl2rBeCBbMEes5kEbTEjBPsVjYrSj7ZWOVLqeR8Vp4gIAxSndEeG2BPdnSAq B4tE7SJ27fCbC9ED+Sgklvt2QzhtBWCfFZ1Z2L8KlMmnE5LgM+i6xlIbG7OHQ+a/zsaq95CsoOCV /EBiADMF7F7Qp1HyPAR0Nk/ZhOMcR5jPOa+5ZoUrHyPUqi4ASgYhwj44QBiH4QY8FfAHfVdyHUcQ GJFjwR87EEug2ET7YbwRIjOz8H+D+wCt4+7p0NMVu8DEK+SvoXi5rCqCcVF4chjJN+IcxKO/RLn1 uWIfnU5+ADOcEdlqw2zlkgLi2bjD95BYIV8EtZU8UGlbtPrccmfU59N+jr5Qw6/sxAsC9WatXIRu s+2WhaTmcewEat5dfFxW22W63Ht9CFsNOOYUnTXTpPbJxV401KYBAyg2XLbUobs7f44fK1vX18Lp WeT0MQVcelUpHh8wYUWIC+T3e76a6fcbxU4In0dvEWOlDAftQWEUKbZ4aBlQy0gL0hF5NLH573jS JC/l3l01aZsJ0HjvotzVi+SeKjZMbQB3HRQArkf9k4VcqihYI38AVOfIaUHfA+A2EHTeNe1zKkKZ oYaaZiI3DJScrdkWkAXFKaVzFahIwtNWan0y4a8O+SLIGVELqJ+QIcD4HlLy9dWtdZhh9bCpkX3r EuBlFinFeu63ikoEaneJp5QLJS+E6hTC8+Cm5Y9Wds1YegQL9o9ajRlSL7+YiTvDWZYRkDEPqNUK beksgfboc9bffeaW12I6JcsX0TRr1y4M2umMSdwEq62jBNw2Bl6j/bz2PQz2bSj1+9M+DiwUzq32 lqSyhzFcSAYCkxSShu/Fc3gNh9dkmF2+gRRZ/iXEPxtCbowOBSwMZqB8ZiMK0rELUszkV76rTxd3 Lcgfx0zMJ4qa62v0Jv2oQdP73cAD6+BAtaEAk7M1t5GV9mq6rAoEnb7bbGTWd042khtsP/G7MR5w kgTZs4U1Wf9U3iCl1mGKQZIBH+401UTK91JzlNjB+QcMXZXDevB+hAGmYfyIiceiqJwjxbnAxYMP 8EOGTMmDSYti5gx0xCLi+3YmJpzHLskdBtRzi2p/H0oBxjSBqGOOlCojezyUSPDOGjb+hxPahhDP J0UiiEfX7TiDy9/D/tfw1oyit4Ie6EVesdRnmpspEx39OohY1BpK06LF5VIvLqmIh1VWJLWJyI2q U4zp5x1/hiLKY58wyZ9hsvmLZkmLa4MEpTpaVNKnVyJIMidJNsTt6PFE7f+jbPVcFlpsTsAzjJ+s mUAwK18foGNPU8DcrYNA/3lEzrAYa8uf1+kFzvqz5bJn4uCT/HE7yLww7PNT6FBaoyXcA0AkQerx DiN5etS/P9/ED+G1g8rDoZrkfnYtsCqHAI3mOyGAez70ptanWayKYF+00hWhd1GCNJW5ez0+jJ7x abCr31xO+7aGgdGL/2OAkNCpzpv9sDL+bRsOh23bIN6GOSogvxOKGHpnF1d9ziWH98uboBbHxeLh PnCktnmOsLMe1kY7jS7/HQC2hA5HeQFmVmMDAkh9grgzmDk+lDcLC4X5o84Q4KQBPz0M2T/fuAAv BkM7FNgAyad+nriH+Dk2dKW0Zj2Py9R+beKvsuQweVkE8wlBM6nCgFNqPjqHBdWObtI229lI8Pve mqW8vQIx0pUoPI7dZA6RbUqaNfQKQEJ9w4Bg8QMCGlRxiNTn4dg5e2sbbuglJKjt3+p5okAzUkel MBvYgjmt02YXPoWjvzfTALFe96UR5pyuvjPRJKI/aYQhCUgoKnfVTYAPK/9cxKikrqKCnjjGgH1Z 9wlT+m815bEloxTgLDMA45A7cDsNxaWelrZH28UOz/V4YhH/Skm31hk5lXw1ZpJ5loirjiPKOWyN Rkl5qaWoSIAiYv7kQ/JymUiDp5vGLfbd4W88p0aqia088/oa95qTh7MV5Y4/pYoXJe8ZxNow+hbT aNd7EmQP3p+GhjvMlBgm/EH103syTKGBlSY1WuKf2eQsqx8Bse4Ks9g3IfMbQ1WJgurYktzrB64Z L+zIvPWGLslsanNRwBsOT/FHTgLd9YDKpHw59uccM89OKwbFWTLZQa0g9wQRnk05/pZJsp1gqPSJ rAAuAmXUB5RAeYeIiZHeUPqy4YXQY/5PTIRJVIEFcImVJGvAlhIkKGaVFZu9ulw/obyNoGyrBSHW 0uIfWnCho5OuXeTtnfLXUjD56mBCuj9+6PDCt2OaMlEIWPxEnPsQSbR3vT2hRuTp7EOtcMo4TOh+ pJe5oUGMT87AX8TN9pIj5m0geAuviRYOThvHoTr9SiH+BTg6DFgg7w9l7j8vvvIXW1aCvlsvpcQn 6Z7Bw7R2u8RhplZjVmL824sIhlVR7sQehLeSNubPe39+bkkP/qY+2DbbmfCbuiYAqdt7X7rh4f3x uIf/fFEO8q95WTVF4uvh6IErWWGRdM7Enml4d3hG/Id5BTVuBI9g9kho8oTny6R4GlMBnjh3MSpM itVnMKv2Rs/O3NcdlAVJUvc88GSfIG4Tl7bFM3Hi/DFsQSZM9oT4mtWRijbFJJs8JjYEhZtp0s/D D6YEz1fToU4R7ROTAjYUKXVjjf9VfLNXUIbYrcIIbie4YCVKnw0O+obbPH0UXDMRZr8NgMgMDHKA P6w0Uj8jnVHWUcH22XklfsAR19kjIWvtzptvvrx1QKnncW3zlS0/tVdIwvFOLYJfWz6TQoCKNzOP P77E5uFz6mNHvk+0yx84ySnakDMWvphba9VmxcDfRteS1Bpx9vZ7LHbCPk4rIe9/JUiUCQyt76CY SOdZCHygOSwAdGzone5+l2f18G8kNEqwy0FresC5ARMEwF25dRdSs9DzTuWR3ZKKZJcFkUBkfCSm 9umH8akkvlj1w5sl79SwdTMYzGfSUvDAHIFFUgZzGXJgEeL9T9MbkB2S4ifOuxHl/d5jCD5PI+xC 2ZNTPnQbxN7mZ72cgE9kQqyy4LvGq2LuNlbF6FWVvFw9UCcCyUHRSrCvJAJHt+30j31zTxLvDEf1 3T6dW+aGwBozQRNEubhfwhVfF4wpiR02haYKhJRvEtAPQ+qsFmS2aiKSiO+fyMKF3UIOvf/YoA/i U6tim9CAzNEUfDSU6PBD4boYm1kDSmeOy2rb76TR2FeUXkKZTkmGszJuw9N7po+ssgM4RuOBYAMW uXDnMJMxJylJIixWuIdiP8YkxZd36Oy3p7AzBx86gHL4us5EgDf2iyRykqsYz6uQbE2Jk4IcZ7jy xklIgvowo8ITZMdcK2r6z+fUxQ5Mro8+1R47FyIdBYAHPgcsPaavZdJ4vypQ3Bc/XisPY8br5ERr f5lTPEqE0vh2CTebHepko446GZtNvsjJ1dIRBp5wJk8m6a5ynfZLoYQ42+1QPakwCksLwq1woSb+ bf/Qi2Cbn4WsCVBKc+hKw60KETToVj4vKFlMBBhPgxUMgg4Dzc0VneDRHNacGii7db/EOtkOa7OA Sg1LIRgXzQjHnRNgref9daxwJBfoXJQIuLN27G6jXkrlVH2Yq/QDUfJomSlhRnmvM16LllpgkibL p41+2b4Ro9BKNd9l8EbFTi5qcgTZb7r6K+QSluZQ5kk1LAp4+Qz8WKAeE+AG32+gwl5GPFPHomgm xi1fWhVjY6vo5AZXdxhlbfHPNTcHHnZGPHa5diWvYUdpgz4sMUrl/VsN/F/HhMmV9A9TjrmY9wCd kUj3kP1mvMgywps+Dzp6enApMgd02rKz2tKTvLLkfcofUT9V2cCt59ws9pRZZsmanbW8QZ4/Vge5 Y8DTu3KX2cBEUKbTKpSqffUNK9VFinqYbpsysMlZAFKN4rGuJvVLeySYDxuXFdojDI/J57LVZLcX uIkJVtIst8LoNLcijVsB49138gc9//2Nhi3UUgx0A1HeM5fbX1EceB7NGwLiiZ9JmY59Jou6DPk4 0ykzjImH5GYBGbn8ogjuXXiI6V/V3mpUT3+qI4HO7AtZkRolzZMy1TM0Oe56fYjZL3QRaDlF4zbS t0pIdKxoc2DfLnQKxFMdMp3IbzZ6HxMTbjP60clZ9kueRxvRnI2naEY6tbncr5bXcQixtHGTij3R MhIb4jKNoptisLPRGn2xDjHvjbxQTLLTsP2bv8RZaUOwySXfArjpo/img06qPTdAORPk8iW5GTAv 9G+32ZA8v2C8Ni8x3bYvkQM7F6fLn7DQVRwHF8W3JxQAUGjrYmGfLrv1zhBwXrv/tfixKyvBu57J 633sBNP0cjDnuuTZvAI1OtKVKHPciuUj6EkKxxnFHRAbA7GMj2n4GXLqnqC3Ggc61C6Ugxv8+zbJ DWN6bbncofoiSea7AVan2SlCm32AFeHNWi1GHfTEEFPUgIOp/fiC9NPxpKC56Cczh40DNiqXbL0m VnJxncs5rbSoa13hOjA/9xYxTQEd7vwLjgySH3Suo1GuFKmCCUezEPYf37S7mNIyaPIkPaBigMla veSU5PeZZdpTUVmGNqHBhwhk57hTkbjiJZ/QFsB2LQYArcSjHLdGuJf1dSoQnKjBblxXmoCwFZ+p hzv9vFZ78fiDLrxRbLkt6B/3TgINzWHaEu1xwBj3elAUlzjIfXJSQQeT5zqs5rIfWlyy90aca9Hs CEDl5uB3agLTo1OXTq8aFOONslWbyl5voOcVsJ2jlE0J6g2xljZTCZfGHArB5IxflhzvZGsyCbqk bCDqeud1sYUMPE1Nm/sbN4RrYvPsvPfQj9JTXLJjKMte4n20E8q/lrZOCJ3pPB6vTz06ZN1MVDwa 904yFczexOWituu97t/RcSRFRn792qbu0R+1SETnbWHSmlRgUx0ELVO6hSqAdh34C2+WykTrOBzJ oRCC8Jy47b+CcnujdbBOUyd7SbqzBM+Esmxn6bsIQc30y2/C403MubcN7n9Ed1xPHk2LhF540pZv 4EX/phj7Mr1QA/I6bvhm3bi5UR7hqbkasSxwAxFWuhFJd46mYIey+5/te6p4HlMAaCnWD94VKDAa /QJWQk7u6qLNfsLPSW/bUWt043fM7onhy3U5D0so0d7iQJVAJmC7/gruqKqIflj9z7w6gwULk8ro X0cj1EjlrvP51IrMGG07djJT9XVorvxdM8YWcKTaEZsksj+1rLd1A6+/5m29wb7uJiiVmj2u/ofM UYyKXsxY76o9qyX68MVHA8sNnjNrGRi0YgCf7xCj5eymPhJ0wlx2PfsyqvWcnaaT5eBdZ6Jl910J uwYf9DbI047QQskLxNKRXMlrlpUj1fYAYk6hbZ6f0q5TzoxfsaAPQNkl0zfShQV1oAmKGUMOTz6W WzVgDkj60LT63q61/Jr6sFE8U8nuEF11+jURvVnSnW15PrommwPylJp/1BKv/acWvMJ0IVcNgg2i q8gAmcUXd4UV23C+rHy8weNghXvcn11piX3M7GXZ57tw1pVkGUdcx6AS8MB7s5BO51VsBJJNgoWr 5qUIlkztOmEcV9zRZDP0ZFbw1gdf3J8UxzBQvYJJq1q6LxaW5gcmcaaVlYOHlo+whEnL+Bthr/X3 UIOlCgYK7PothK7e6p1EW4AXOrwY3BE+5wqtxYGtzc5IKOes33mvHFGGMvbaTNG0K/nPk0NkzKpG d1Z44qPhkb6qEb0TbrnDC2itkE14zxrdJKoy7+27OtsdUrFcXZjatFZNEMbDu4wDnxCvK+WI2Ndz dRqVV0QlfbHwc+fzf5bGVgjBsqxm4gD/qCuqaBu9rh0IUUSCzoxv0PxtSN61yugLgFbIFlntHimD JODOnAc+wM+7vpBv+cPuw5Tq+ukkNxC/Zx9cwTGhBBu8jTR1uZNS7ASuHvCCeE0XzNvRoeIgdy2c Ct5noSHUfYusJjZHlpFZI+/Qo6LTihwYLAYja5nAlPBZ2b7YogzCsbv44uxzcKj8yiVVi0Fi8s+2 OusdWQmGB80mZeO1XN7NOHmwEQ0NGQyMcormtEeKCE0gG7AJXaHgmZIWUJOQP1puB98aXoAZ561C lj/Dl136qFypFal6h2858Ew+nnv4L3TSLglfuQWYQJ9SlBx53U0ZhXxWUwb3D1rtNrtcGosdnvdb yaTuMhNRUVNcL4r3pc1i7sb8x/I+9cf7ojNcJSPbG/LXSKA5I5C+B6u0fyIf+RaMg3yVgnWWXOS4 0pdUPDKg/XUV3ih88X3cOJ6j2Xc17D7jUqy/hAQPahBb+DRAm84FUTa1g8kfqFTKwXOnjG8eN+h/ D/H4HeklTGe/oYvUnqFwgXBxQEI2qnW9RDd5wdM3e8e657kHLFXSDYgAWrHuH8vtcnsr1NeTTh+8 jmKlX4Og+dm650RgQDsa3xaK8CHtE8fFOYOAsEfNJgfb3RiSBGRYmQKFgz6PbX2ywpA0FhwYXEt7 OjKIf2T8G15iTDz9jnJnu8qy6klrtDvKMvfn6Yt3tAs3BQVPWoYHJoAy2YAmWJzCmT+4fVG+2t9t vLbYVNbC8ezWaDca77qrZmX8WwKmxmCTtY/H5dhnGhZDpp79C7Digv6/1RLj2xmLt+AnY8E0nS8C gwQlgDOHrVPUM8cAXrsj14zVxV18FlHVRP3QBWv/U6kl4fzKczrkQ+DI6ri2u1N+5FSzGHYsORz2 +T7Ed/al0dbTXkfHrUUv0nKUHy7W3NwE3ExObMvvL/yiIe8FNcTGIpC5fzL+rKJmmZ3i0+JYPik4 yiyK6qKOxZA7CKaEvBPhmmuN7xaJOaQEhy8Yx7LBdB3NG22K0aKK+VNaYEQD8sjwKDoeH+KodAhQ N8jUpEBigEPtnkAtTOSTdaXA5sIvOSMo7uDGowpOz66FiVo5Lapv8JKp/vPU7fiskjd+HQuE8W/i yuqKnSlErzoXcEB1IvYMlkop/QQ17AYJ/Xqs9QMtGEgXRl+LwaTA8pD67Ra/SBU6se1kUN6HbWuw 2327gQtid35mMBG2dOq88LvmYiTmltICswMtYo2qIzJ96OdyAL+deXaE8f2v+7VbcrO3W9+tqzGX 8CD1j4mi3e9r99mDafhY1AXYb52ZDAtOIlBU1df6tD4B8J1VpHMwEcF16Qt8q4afPk9vJ4j+8aFe 3BeJrjrTYBQa/rkzwT6mYZBI/cg0mWEq7uYroiW3iTYi4HAcZKKb5GQzJnvartWuepavHSA7mXGA +pzdogexTIK8nHsvX7Qek9VyJwLkHr4z3xfbMb/E6RhR4vZ4W3O6XpppLz2Jke3dHJwyUzZz0Df1 xvwemhUnTpg5IYcrvWJXb7rBqlEfI2pbjJ6vOarUYRoGgfKHNTM6GivZnAcFlOnwXJI6GPwiJ0D/ sgvhnysDCK9RrczmuwkhMf0qIkJt1rZ7NKbJ62qvpoRZcyZYbOz4npqTWze6wZOi8oTLVx1c `protect end_protected	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/ramfifo/wr_handshaking_flags.vhd	5	12657	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block l9qS3t+34Adw3J7tzEF6mdxJrAFan02fIUr/4xjQbFxJztYO8Ss8efJfcKuFdSM+KgMwDxzut0r7 7wUKes/G3A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block D0xSMGVp1kA364gfEeBgZ2Tu6iS7kfQ4zOA/16+EvBEEf9d4urc39zBLLeFYyI+kO+GefLswguDl LrFagcSf5vM8HJcQXy6nYClvbBVol6lGSl6JttTC7gD4/KAPOJ9yJjmDse6Pp0VQLeNYVJxO2de1 Qg6YvPIP0TmB27TZpAk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block pa3K+4uLLYd/JDdKM4dKTIzHVhp55BgjObW0d2aXf8oi+A6zi0d9p/h9InG96DGGV6OGmaF63M5r D/ZvbKf4SK4g2ygA+6wzuS6HnosV8Mhi9DEghG41GRMMmBiZ50GzzC8q6+Zqvd36tXHRGp/XJ5OG 9UuHwOAfHyJYfZW+670RVCanD8JOUK3zfJGORgc738FPH2ObEHJqWarl+/7UazVnUXaAqPgtVZKX AUGFmiTmYaBHnHOBTywp1a2T3SOGrs0lMoktS5ia63W+4QHt5bQNGaWhQyyYf2qW3xwAe3RcZYhz iarzMT5YkN3/AiuDsWYW1nyJQFQ8RsGMhksSMA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSCz+VtGXT44NsvPvXV/l048m+nIHbFkEqlytyRY56VQ5UwFwh0Hq7ptMEPECN4YBKpjlQaTv9fX VPkJAqzm6fQ35ymXEJsK91Rt7JTjNeSC54vRUR3yaSVnwF5gCDaisyPpXt2LhaTTxLVX3QW7Tq5X ATruKUzAJXwuE8GFWg0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Zg+/is1koS4fIUk7L++MHC6v5WLMmMP8ErlAst+jLhMPnoUEx9yPd8id58awwI/b626nA22mGWMY Kl+7LuXpSSz33I6sf6J668LCCwgloJXoM4d88YCwfHS3jBFOxAnx0N3jjSieb2lxDgO//zri8e0G RJTduyYmXbdelOjUXLV13VxxOTYMxwoHAYlRD0p3dozFYgddWp2OHVngKhVWR/jpijxUT+A/buTi lmKCpTNllXIQAjIBAPMlQYJfCDaSSPZyvRWbfgPgNqAzGuNReZ3Bjjpk2Zx5yZV+xTXQJlwo1q/L JL/5jIhwY21gO5b/QHaYV4ciSjKfcSuU2KDxBA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7632) `protect data_block 0/4fBZsdE2xh9wJ13KHLYL1nla34IpfgL55KmCEOb9cRaM8gVmfCmm8qKh9im4zapCjdIoJBUeA9 DwAid7OwQCw+x6NopLmry2GP2Wf82NgpOIFSHF0Qo8mrm/q0ZXr6H/gDHn78Ix755tuLis8xbM5R 9IjVtYqSkk8Bg7/k4lN3h7AUca05+D1VgUQH9mQUt4HttTLkJUAnZ82nmhfkWKqPSbMI0GxWopoO 3h5Yfem/9zWYtMcWAv/SpoAjtFOJKeLvvVMR8KBpHdxr+fGgoQV5c+RxxUaaggS6BhnAL4/b+yRD ELClaYyFMVj1YKAYs2WGi4WjVnGue/XiHhkr+njtzb8nCPOrC1m3n8WTNTld3xpJ95CD7ywTtBzs neLoBBQ3Fh3xxuQ2IOQNPPEmOR3bhkApOYmlxL/TD9VuB6zdbo8CreHf7tOg7YdN0DfemrMEbZ/j PMVMA1RmA+jRnvXOeRhAV4pCg2QoQoElKTBOP4sfN6v4aQMjvEm0wCr267mAl2xCR4+ghpblsXIU WKEERhY9k/UQExwSmoDXUj1ACD5EyhAto3tTG1OUplpgqS0t08Zoq8ypxhuzk+l6tc7+KRxDU464 pNBxcASlDHXYpNX/qzZMb96i05kbnSyaeRljOtUaY+7uAmjC362VRrlIbQahVTAVyLKpxbZ38pHd LMZAu2pBnGAmuXxEzHMfY76uBChwab4S4pQPzgjhw412OYZfl8xJTieYa38xZV43R2Lr3A+ZKvbK KV+San71V3TnREFagiWONdmB4LEjAR+3ql6Bcv3h2YpHfgc3i3hs/D2LnlJdM4EhZVIOi6RVdRvo A1gFSMmjOIQ/4GOzJtOEd4unQvTD42IyydLylohgADyKNFzUP51hHsWKec0BtsAW52LBd3z58Wel WpI8ExcSryyqPQ3GObRuxSa46sYLI6tZrMul1Gjig1JEzpUY/L1vnVGFqulbBRaxLMgR/AL6382r UgC4t+1Tdmfjv3DMoPWQUQl1ebVAGcAZotSi2W9Bn7W2hhz/bNCIKlLlKfh03cl5Gkn19D2ogHgM FZe/Cr5p7DDlsl9RlvoAkXalQKDSRCNNUkGltiPI/4dFHuEqGRM6qs20cRtq+CW8fFGT5C9wKtwL rRFD9TSVBD3JrfRQv3KUBPDbuZr+rCwH/yZQOhGiyrN1DbyOiltxvtfMoRtMeas7UxcPV2eD/jl2 o4QngUu3M/+0yppDeFg4YKd2kcmwCCVa3Y2AoBdifqF0E1C3Dj7OyRb/EwRO8gEcrVDU4dBYc4AL ns8TG5uFg18uxQHuITF72pkJZFApZDfrCV1FSPxn/b/eAf8lbR0yzYWJoMgBMuOd7nRxqHI5Qln7 u+ancQRDvFeVOvOZzYJuZ8qwtCMnfEsOM+6UBVDduOG5gKcLLTb/nPP06+kja01gBZZ/vhY3xFNH FubvmWA3xfzUmD/ppM8M+GcAfiWjvC2XK21fKxqps2gHZCeKTheATKC2afbIB3RbAWtzaH95cEae QR/Neq8uf4OYBmzh7MXSrBWxlsxw4llA3YT/OnbKVoyVkXzM7YaMQ+ZBtiP4sBMby4vJ4S2FTa8g D1Ms8PXZn9+3nIlJQX51WeU68ciV2O+3y4p9u0D6E0da8o1bvfGt0mHkEPVNhaKMDFm67K5uQKBL 6dlgkOmqeI5bzkoHUeHt2wTwWx0EPFtvPM4TWAX3buTRLkmXyACU/zZGwx9RToKQnkHTi8Z03nWb Tdfp3VgmZ7Jj+gpnOiBnqVTkdOoqmGWDICS9+mme+AZgpeh0XV7hy9Vjzr6Cw9tM9lST/JV941Yh CixtC6gbXqfq6KfA0q7tpfogQb5Zeu9PKUFh//odw1jOFS2VspMwHSUbrFn8wsXdlnNUwYvvjU2W LyyUhsc+IFeZnn49Fs8wgtHa5Zo6ZUjbMqg05tl4qaSeTYTeXOeq0IE+22DI+YbK6XFF2UUt+34M rNVSJ8svykfjMBXloUwNWDB8VI5JCaujpYcSzNy4vPYPDOBRiV3EXhnX7sN0vRAK7NwNF3of32zU 7Sgf2GJ/DMvzbZ2TZqMET/2E2+3p3R/HpRbpjR/6HIvt+fnmAVUf9KKSIazFCFTOXKhyLy7E+7zl gcLss3iNx/VeoeySUNVQNpi6rKTQpLAEXNm/r9ZWj1YTXPscX/WY1xsTdlOXpa5Wk6pVSZhrGjt+ MP3zfm983DAC6kMmZExI5nak5ax6UZDrxfM2pU7ncwnzFlVFvPJYZ/0WFQ4G6rjZy6o7D66/SVei B2Jdx/xOaHqcLBYfkipDB5j9IX7V8qbxRx/RJjunIdbduTzejOalqbT9hJUgk+ebvTos6gK6rLhY Hg/e4Dn/gYzWiXbwtpsXlXTsz6dS8qFmGfOnBff8CYlkTG4lyfpguWn0W2+qDf/I38QlDw/OLlRa m1flLIztcuOQfWLuL2dllpqqB0OURG5BgmEXOk3prELxrhAjPsqbQefV+eXhXLyn3m1GB9V8lhqd RBaFbv/DFNDAM7WR2uoCSzJfE5962EFilbeet+JTbz4W/WtcjDTt0d/g124lRtYj9IXhR/fgk0sp 7Z3PNKE4lIi8tnzY6tbzTzWkwVDhaZITSz7I0nyt9elBM6FE7nLRVwFmGPur/xu4XRZnOErkaztk 3EH+p/Jg1A9iHQLz66yjuYISw9aXLM4d8MnvIr9rjfwcIyEukWmIWDlhLFZ7/aGYY4EuK0A6WmxX y2CGboa2V2UeCgYjoNnosAp33Xu2W/y6YWUR71RgNuhtPTofRrhCTVazp9tx55YgmOM0OQ1Z/dJQ 8DgSZLqhArXmItX2gnJqT7EteSPeYxzOUReLg3Gvvwr3c2hsOSaaXbiDPeuXpGCJVgepwm9s6QIQ ZXly9IprSgAP+27IzFR/CMN672Tsy1MlWnoS068Ur3kmvYMQgCfjKN+/8Z15uAaFly72+iJUaub+ 2+b2ntm+oxem4W0wuciEPHIKWNX1iFVHcTv08Sdn6K2mAV8P3/uVSLesiK898UbV2EIY9z6I86xG VqwWJmqE4NCzRO1/NFxDYgWcc38W94PDVg6AgYCrIdAeCPt79UsLv68jZrJTfZ569n12l2gDefTJ QO8/u7lCt8Jj4Ia8QciIC8eyNgljEUmgsGk4GaJVJ8sUkKZbfeshm6/m+e87zQqbWjecTl94rI43 Uil1rSHdJUFOCVGXN6Ip0rdMB4sAiSHf7WxaUFESLN8ftklVsCWXdRolXZ/LTiCvQwjjzcZ3jdHd LcGssCvCIySyTntgkaw+DMlZfafoHWgaDDQwG3+Z7109G4/JoTI3Gv424xKJ6IO0GnL7568il26g OVfsfBMQnPKySJfDO9U72qzHxaFZveg3a0qJZQjpYGCMrhENl9ogGOuFZEGUwMQk9hz5O9Z60GKi WOskm995mnbPubKlv8BrN6xiRg6rTs+eljhCcolpyqTeqLxQ8mP1SsjFU7e+EOcQdgbf4ZPTOxgA g/QWT/EPF9Af0yLnLXiwsnKYq6du+2B0AooyoPFj3l+enDcBAVr4WCOJTTqTu+yhKxv9QqsF2ENn 9GfJ1du9MC0qQeHvD2rfKEQ4rqRYmVCtgxnHxdg2QxrqUPTCSFwpWJNq4h411gnMK6VBNYOUcdFt Pyegg9xzaF+1K0coXtDObOh01I/Jg1DgeZ780u2BwQacQQ/xEUj5zcQsgwxIrUb9fx5XGxzmaj9s N6T/Q2YA1v25A5N4jbR3LkLuTgR5P7cU4cB9s4YwPLyuSQ3CJaaAXaqesZo10u3MWbl7RTCCO2/s F0/xSwL9cUxPWxkp9VTXdfrrV9WaVHX9SBrXjICHzhgRCCxeAeYAJki7fsa+9TBDN12beaKUI+XX GttForFuhecDJwahltq8d057sCS5QVtFIMgdk1qLycgoRW2IbTDlNaSmySYvlCmFr//mifvessZs uI/POjXCI8fW4nc4SfuUeoIhe6zL3+DLFp7CfQC8zV63X2kt6agORy1jz0HH5lInEXJgqtuLnTlk W/5+zDla63ZRhFziAoWFZrVfPi6vsmwmJOXyhCFRJnyEka4YzGc7Y8CjmBJP2Xibm+NQ5IOLyvMe JVn43X+DwCE1NfWNpfLcmO7/ocG4x3CWOAUyb7xs4LWhiXnwWmooxGhrWeya449x82ihXlPDLmKG rm+Hz8M7Jyk9kSzpAoyvFNvhsh0JBVDi2wAalkHwe7bNyYe20CbO8gynr82DxsDbXuOsXIOrwKb7 0OC2kIN75LlHnkwp4keQy1teduP//JCjXXVzDcUvPHVec6Ar3iNPqCcxKxVMqh67gtIqYI4WyURh quUxVOF4J2xcJ70ker78ual2EUTqDsCBM3E3sgYNiFe6YePg33zkqThnweYd60ddyWU6fZxRmwZZ BBk/vDQQTMiJazOhbFjeh4sIEvfuDfwJIGaa//0NYbwnd6DhurlSF/JRv2Vvp8qG8g1hi+1BwDVE zJtt621NoNR5ZWMQq+x3cS6euZl193Uizo1veAoYg3AhY+MJfVirneis2l0XPEqFRKXL2j/My9aC UTvrZVykl+PGrEi8/t7c1831+kv1L9dNUtCR85migT9/hT/y+f+2TMW2RFf2ZTSHnM7t0DzL3vg5 71K8QjIEp2jCgTV4TiEsOeXTX0x9hqvkM0n7Tefg/mI2/ikqrELZSlsCkVVtRu4PERg3GCgsuv26 CjI0kBXg7/IN9JatsTiybRWknpx0dGZIs3eiyDmDp5Mev1NVlqLN8JxcPsSagA4N+GD5TGe29bX9 1dDvsghZIID1n3GKDI7B+aRMvlSei1xiqfPejpKq40r5R+Xj1bdhUcZXGRU6pLl3ZkRtH6yjSQah +o3MM65kcHynYs010/rW0U5pxRoqcFAOBj0xrLQj4RmxbXOAoMyn9kl6dIYTU3pW3t3Amm6PKdtz z4BT17ckoVDuW8RArUn7Gd//dxMVbNFUVrWZ0jSL7+3GhNayPb1dvZD1eHvtdkrsi9k1G2Y7yp89 y1iPYy/BkTotxx3p3aEgLmYtVcuFdN7ZuYNqyhbdYeGJk5qyB4AAdC7pTDl26hgrbRSzQfaruznr fcfOSOFkSIjm3UqCCcrzFwFtaYnpgqPMvVOyME0Kmxczf0V6yXW10SDN2z69PE2lvpAlAJV11oMd MNNTb4bqUH7b6DNv/K2rfy6TtTVahFINhFRG/BwoIoJk1Kxn1ovqCKNyfTPpzgn+dtnbbCwp+U/U 13WOvIjJdnz9qXtYrOlBhzG2TLpSW8Q03iTvvqfQ84oRg3ZS6i38zD0sUXbgrM4gnkKYwz5TyIf0 OfwJgR9vqi92BV92YVGs6w/7RCeHzXNFpVsc/cHVlkTufV+RxpuOgiZvwOV5mlrzQ2UpBn7owsSg w6jNg2CB8pAInwvPaBRc07jZrYEu68ZS4INFSEcZUTBAxNlitJQ/kvpBJPMHjVASbCjhCMnZqa9s nfQ3JDdY5KZtltqDuROmzRgcDMIbTVGJvp5YW+VTaxHSQVjzqaoY/JKNEG+SLvp9WGIKsLaJ6brb 7nDKsm/b3wDE423jEgev2RwZcOi/3+9BO4P8GllUmnAcpi/f2grKKbZQnzfhglbvUzBVsFvDNyoH Jj55Ce1EVpqiv2U/da/D0qeAnU+/8pq3TGzhL2uw1Q6GadsIifMo1h0j+UVJuX/Zhy2NUAcCzq9D ttjM+3LDGnY8C/ieYZc32QBA/cwvlsXcH3Lk5eirYD2y0q7LxcRJePTNTPA+LPTdgGDtWTOL+0Qc pnzMZ31a5K5DQbOhkx+uSxCdiamH5/6HYn14zuaYQPnsNvxEJLFvA0l9eJ3Y5nkIKdTnUx+wlEJo AocnodJiPYxFU2To086NvVi/vN39JtPf6QoGaL/ekQDEQwXawkUzAvxtzKKFV9zFVjl4IOEBtTqv MU2J+gZlw9zJ/Ciw4DYMkoPxcjYAVPO1o6qGi+NAidlse8HJ7k4LGXDb80xIulWA7UQDsj4Uo9WP Byh1OVTBIoBIcVNOLqh4ic3swAQ+LJXNHsMuJMkx44SYpYejYkxW0q8D2/DFobsBYiqgfxNDJLdJ ygadg4urUF7sdEdwPpmTjfBRkkO0jZBt3xB8NaAanfbBuEzE9Av5oAQumt0E2CZJw8QVM79kXAsU QfruUp+41SzymaiBCoq4W//zTImn6ZpRv2a67S9CC2TV2Th8Rtgw3MeN8xsEP0glZaJpy3bN1WbW kpitPqdYwtbetBk/GwkocQCs3K1V+PwGXPNco+PXSRSXByixFVQDUI7asBfQcTBd7rO4ZqMXuN39 BOgUZtMEEu0bkxaSJTd4xfYdauZpn2SZ1PSFV0ighih5xbov6ExbHeOqvz5mVDkTd0eOzAWUfTTg UMeHDtDzmYkUqJIKuw5Pke7OQ0xG6LTcrUYG8FR9ctjKmqUrrjOZK8p/sNtCqjQg3IAjHWtqOxLv FDafuu4g4fwgGeHp6YsMxuANnlx3dRgNaCMzmpzDNaLhKBaEym8FIHi1MSHaRTQEYZq47dmUvz9s po6ySRfBREcdh0PC4t+5Pw3CBSgpvMepZivY3XCye+tURCkxCDazUG8cJm/5GSwF53cgs5ecjeR1 tGGgLWNkAWJvem4Yu5mgsqgXOsSzK/3hPnvVgW5KM+de0k0jvfiwLeMB4/FiZFg1g18FwLXtK1Jy GNiX/sSS1/KZSo3jwnTwU4tkHd8WXZdLx2JBe0eHupOB8T9fiTJGUhxFRAjKgKW/ol7RGS8Cvjc7 plpAncerS234vrEe8FoIKFefTp8AycTKkyfL1QJq2gHR1V5vEFCb5c28Tdwk8kGKBHX6C5DRSzNF bS7283gAchNGFlKRaA0SU0yoDfB+l3Uo3oECoCEIhCnY1g8NM1h5iuYW/G/O7Cbkizr8XHX6NA2W uPZjliHj5ud/DgR+6Ul4LSDiy2kfeUsfhpKxms4+d8T8v2lXgkhZxlVvp2SBXh+NiePAt54MiwB8 fkNnQthsYbnpJo/Nu/81Hz97bD3GDkoyUoEz9Q7Sm2o84cSJA3YG/oSvnb3uJD+8uznTJxcr5pta RMqGsdt4QU6gzewf4Amwhjwuxt37vLy7/sZRkLqLKAhhk5T/uM+Aa9CU1vKwY9ZLH8M2iJAm/oev nNlTHEi1diT2Yfmr3hjmDjQ66+HzXxZEsU56AW18R+xv2a4yun0QWZ3xW0rIM1SVGrQWwpuuGTSx EWgkTrP2Ma7KTStmRfoh8nawLBOv28gCCK6PHXw07OwVHWtpsG59CXbCSTFpF/eiru6i4IWKH1Mj FjIu36xXnD1ixm7wvm1m1l/8i2AIoh0GjcvovTLSjVEEVLvYHfRl8xVHegTbtjOMeIX2QSO+1fRH JbVBpv1JjgLvIDWsE0JhGJBK+aCV/2ZoHB0gmSCDxVo5jrM6pimpJo2h6RcfBfs01769eJeT9+US X1wXdJuo4IT6mw7Ii2oCf8YFRwVzx3UVZdUMP16m+OWe7m07x63z4nA+0xCeHTEddRm1DkBO8tuR 7D2haQva49eZpWayEAZIBzJLQHzZIeKM7G+sbslsiTZihDQdVQ2TQEIqkgqTWrR5BguW/ANmNmlp eBeoIzsXERru3Gq282aheOPXmaKOmxQvPzWYFL7dPUetOf3tUQ8OAQ3U+j7Eg0ZkDOI9bRywY6gw zEbr0grM2xcFVgfjX+vo0pqbjbcKSJltg4NM36Lf/WLosuzqlUmuOgfYkP3RabYXJ4fPxAHLYOiI Ts/GjGbiSWuQs279M844yTMohOzrvzyVbLeyiVMCL5kRFrzILzEyRBL+cpBOBP1FxFCU1f7rRraq NqmKB0hxPuEn8ecN54BoU4Z50EWg32dbHUZEZB0qUJGyfjIqv/+6cwepBT1xg1lrmijD4FffhcPa uD4EZJA2pE1dZ5ENdXp4H6IdwRhLUWRzb0DE7XXjh+yykLeyYFrTfOSpR+upSnQKfvBtWc8eZTaC rOhQCgdqPOn3hXQHVx20zeypJ6b14bRcAt4pT54shQibcAIK9z74CprmkYTzMUfQRNDFaMsegQFD EvfvGOdQE40PFbGM4JL/ZvY9vgHvSPiSUDTHb2XQ9Xb3srEFu+O3I5PHUZxtYSJT+ebd95InQqbd BYrfdwnTWXdD418LFYAw4P8r9Umy0MMZNse7g9lhPy8gRPDJcYCz737rA+xB9N3kfGY4YRcnzzwn Se4cSGGprVMBPZuycvUBawEdsRZO9Ceqh8aellAAHE8DvSClqnPD4Rim+wwDq7J0yu9lklJMNuNO poheM678wvAW0FBemZiapBk8rzGDT5TseMgbb0VIaIwvbQLIYNlDs9lyx3YxIzfopd6FBJ3SaK/P xHTSNqQJA+pcIi9Z6GBVKAEm0svdsU74B6+QnzjtyQNpMCB3yGzDLu6j0Zj8TcH+SkI4hCVCKcV8 MG9D0dIKHpdgbwwcpEMVMJxAyNaz26ltUf9jmQ/ORDSFz4M4itsAy0Lhsue34vG6ITPIzmUen7UB aKVdSVz2MjQ6G4gytOr3vvhcAQNj1IMroPvT0I7APfhqWcRJeNwkzLRX+UWKWXWO1O47ZUbPktIc 1eS8KUMEv1OCsssAeG2et60qSb4GnPMGmgIU55x+DRPMkVCd9sK5+zy77PyQAb9NcQjp96WOolo4 9IHcS6ix/9Acx5cYG9YwVje/Ovc6KxsJGUlbOODg2VIFE45BcjOVDIgQL/BBQbXzrN+AYu4YFrZt gYkwRo8EYIGoZG8bDCPrJmIs4RUAvbtAJmLFNbq+/XajW8lC3sMUSEQ/PhKvoOPt5KhS7b/f4euQ Pj1Rp2JlSzLxw4zFA3JjeNarb+RBKfpFCSLcvwnOr/wrlDjG/pV3lwHWMWB23ETVYDqOsvnwtsMI /eniKO8s0/VYlcrwsYw0gS2xRI4KzyFs/J9ss4scMR17OtQgGwIYR+w3wGCg5vN4Vc8euUTiVl2Q Fmp6BwvSDiF7mgxY7EuplpApMLXr7k9ilTYejm6MMNlI8rQsZ3Rzt+w6pAEDrdlP9C8J+xij2hbL TutPg/DyjVJQbh6OseEMynbIzoMX0PNbfn2G+zzjqFKGk+2rpf1nKTJPfOqXFlERDDK8l/poi1JP HraRciYnlFzMdDkHYah7YW704VUtK5L3A6+liTszgEPElKePGSKhavGY1CP9NUTLkt1/I0TIUEKl Frh36JsjPZZCRpTZUswxc2QgmR1VuoK8V/vdRid6kY1M+40WXWKKZK/QyQXjgqCM34X1kZgQwrEF bb9feQTN0E+ycSuixVDhoNdfNVXoNtabyLoEkPC+JxpE+QiJxDcDxQSLeTRItpoq7c49XxGb+y3D 04r87zBdacfWKemxqL2mctftFU0aJDFOU76t2FjvlfI+NoQ1rHpGUU8MwaEM9qEOb8c/DLe2lHXh XEnjSMEIcCPoCgzBc/l26VzGS71xJHrGyCYn2cJ5vtGpnypBoCUHZADZTHaqE/d9FUMBSz3e6jOl f7wx0qlme2kY3gr9gR1m+Ad7iJMFj0KqyAq9v29KJj2Mm5Bqe4iN+k61gnjvHt9cX4IaS7SJzfJC JCQJbHkuJYvcruJ5mJSJA04yw7ex2NKL4FtQ/yacK2fAjc8saMV+3Fmb+Xl7iJ0IozLf/fdQOqeh JmsKZdtjuyz6RioTkXlqtPtPzxlQC1ykdmI3BdhTmawjgDwuDDPU1dFaC9kVvxyrz81qhgeR2ah5 LpAIps3FllYgvPrc/Mpy6MXAj1KKTaueCylOOGcVYdrsaMcjvVXVogWeG/TeuLLAvtW5Uotq8pP4 6YE44gLISwjzVma3rxWh7riMgnBXGGn256DYjr/ZYtKRn0nSl82onXh33VotmpZfisRwwekiqtuc bWrWOy+olboD3F6J9sWUIJhAzy/85xcS0IxmKyX9xPwcjWmuY/QuckofLEfp7B+WcNIlj8LX7lI7 rAiPVZZUlv0B5AkNOeWf4WgCnibLOqpqQgdwZqHplFx9VK0iHWLtQovB7XqlVR/5tYLesNcBWdNz EzZfWSWm9jxVqhF1Q4bP3eu7WR6dexHptydqPIf0sF2XJEMezWZ8Vpsk2IKYjsBQvMEVa12zLC2N q1T3C0dNBWqz3rzrn1LyJ8CuypW8mEEe12VRWxzizfr3I6XmSB7a1LdloFFen7o3pMne `protect end_protected	mit
camsoupa/cc3000	cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@h@b/_primary.vhd	3	10201	library verilog; use verilog.vl_types.all; entity MSS_AHB is generic( ACT_CONFIG : integer := 0; ACT_FCLK : integer := 0; ACT_DIE : string := ""; ACT_PKG : string := ""; VECTFILE : string := "test.vec" ); port( MSSHADDR : out vl_logic_vector(19 downto 0); MSSHWDATA : out vl_logic_vector(31 downto 0); MSSHTRANS : out vl_logic_vector(1 downto 0); MSSHSIZE : out vl_logic_vector(1 downto 0); MSSHLOCK : out vl_logic; MSSHWRITE : out vl_logic; MSSHRDATA : in vl_logic_vector(31 downto 0); MSSHREADY : in vl_logic; MSSHRESP : in vl_logic; FABHADDR : in vl_logic_vector(31 downto 0); FABHWDATA : in vl_logic_vector(31 downto 0); FABHTRANS : in vl_logic_vector(1 downto 0); FABHSIZE : in vl_logic_vector(1 downto 0); FABHMASTLOCK : in vl_logic; FABHWRITE : in vl_logic; FABHSEL : in vl_logic; FABHREADY : in vl_logic; FABHRDATA : out vl_logic_vector(31 downto 0); FABHREADYOUT : out vl_logic; FABHRESP : out vl_logic; SYNCCLKFDBK : in vl_logic; CALIBOUT : out vl_logic; CALIBIN : in vl_logic; FABINT : in vl_logic; MSSINT : out vl_logic_vector(7 downto 0); WDINT : out vl_logic; F2MRESETn : in vl_logic; DMAREADY : in vl_logic_vector(1 downto 0); RXEV : in vl_logic; VRON : in vl_logic; M2FRESETn : out vl_logic; DEEPSLEEP : out vl_logic; SLEEP : out vl_logic; TXEV : out vl_logic; UART0CTSn : in vl_logic; UART0DSRn : in vl_logic; UART0RIn : in vl_logic; UART0DCDn : in vl_logic; UART0RTSn : out vl_logic; UART0DTRn : out vl_logic; UART1CTSn : in vl_logic; UART1DSRn : in vl_logic; UART1RIn : in vl_logic; UART1DCDn : in vl_logic; UART1RTSn : out vl_logic; UART1DTRn : out vl_logic; I2C0SMBUSNI : in vl_logic; I2C0SMBALERTNI : in vl_logic; I2C0BCLK : in vl_logic; I2C0SMBUSNO : out vl_logic; I2C0SMBALERTNO : out vl_logic; I2C1SMBUSNI : in vl_logic; I2C1SMBALERTNI : in vl_logic; I2C1BCLK : in vl_logic; I2C1SMBUSNO : out vl_logic; I2C1SMBALERTNO : out vl_logic; MACM2FTXD : out vl_logic_vector(1 downto 0); MACF2MRXD : in vl_logic_vector(1 downto 0); MACM2FTXEN : out vl_logic; MACF2MCRSDV : in vl_logic; MACF2MRXER : in vl_logic; MACF2MMDI : in vl_logic; MACM2FMDO : out vl_logic; MACM2FMDEN : out vl_logic; MACM2FMDC : out vl_logic; FABSDD0D : in vl_logic; FABSDD1D : in vl_logic; FABSDD2D : in vl_logic; FABSDD0CLK : in vl_logic; FABSDD1CLK : in vl_logic; FABSDD2CLK : in vl_logic; FABACETRIG : in vl_logic; ACEFLAGS : out vl_logic_vector(31 downto 0); CMP0 : out vl_logic; CMP1 : out vl_logic; CMP2 : out vl_logic; CMP3 : out vl_logic; CMP4 : out vl_logic; CMP5 : out vl_logic; CMP6 : out vl_logic; CMP7 : out vl_logic; CMP8 : out vl_logic; CMP9 : out vl_logic; CMP10 : out vl_logic; CMP11 : out vl_logic; LVTTL0EN : in vl_logic; LVTTL1EN : in vl_logic; LVTTL2EN : in vl_logic; LVTTL3EN : in vl_logic; LVTTL4EN : in vl_logic; LVTTL5EN : in vl_logic; LVTTL6EN : in vl_logic; LVTTL7EN : in vl_logic; LVTTL8EN : in vl_logic; LVTTL9EN : in vl_logic; LVTTL10EN : in vl_logic; LVTTL11EN : in vl_logic; LVTTL0 : out vl_logic; LVTTL1 : out vl_logic; LVTTL2 : out vl_logic; LVTTL3 : out vl_logic; LVTTL4 : out vl_logic; LVTTL5 : out vl_logic; LVTTL6 : out vl_logic; LVTTL7 : out vl_logic; LVTTL8 : out vl_logic; LVTTL9 : out vl_logic; LVTTL10 : out vl_logic; LVTTL11 : out vl_logic; PUFABn : out vl_logic; VCC15GOOD : out vl_logic; VCC33GOOD : out vl_logic; FCLK : in vl_logic; MACCLKCCC : in vl_logic; RCOSC : in vl_logic; MACCLK : in vl_logic; PLLLOCK : in vl_logic; MSSRESETn : in vl_logic; GPI : in vl_logic_vector(31 downto 0); GPO : out vl_logic_vector(31 downto 0); GPOE : out vl_logic_vector(31 downto 0); SPI0DO : out vl_logic; SPI0DOE : out vl_logic; SPI0DI : in vl_logic; SPI0CLKI : in vl_logic; SPI0CLKO : out vl_logic; SPI0MODE : out vl_logic; SPI0SSI : in vl_logic; SPI0SSO : out vl_logic_vector(7 downto 0); UART0TXD : out vl_logic; UART0RXD : in vl_logic; I2C0SDAI : in vl_logic; I2C0SDAO : out vl_logic; I2C0SCLI : in vl_logic; I2C0SCLO : out vl_logic; SPI1DO : out vl_logic; SPI1DOE : out vl_logic; SPI1DI : in vl_logic; SPI1CLKI : in vl_logic; SPI1CLKO : out vl_logic; SPI1MODE : out vl_logic; SPI1SSI : in vl_logic; SPI1SSO : out vl_logic_vector(7 downto 0); UART1TXD : out vl_logic; UART1RXD : in vl_logic; I2C1SDAI : in vl_logic; I2C1SDAO : out vl_logic; I2C1SCLI : in vl_logic; I2C1SCLO : out vl_logic; MACTXD : out vl_logic_vector(1 downto 0); MACRXD : in vl_logic_vector(1 downto 0); MACTXEN : out vl_logic; MACCRSDV : in vl_logic; MACRXER : in vl_logic; MACMDI : in vl_logic; MACMDO : out vl_logic; MACMDEN : out vl_logic; MACMDC : out vl_logic; EMCCLK : out vl_logic; EMCCLKRTN : in vl_logic; EMCRDB : in vl_logic_vector(15 downto 0); EMCAB : out vl_logic_vector(25 downto 0); EMCWDB : out vl_logic_vector(15 downto 0); EMCRWn : out vl_logic; EMCCS0n : out vl_logic; EMCCS1n : out vl_logic; EMCOEN0n : out vl_logic; EMCOEN1n : out vl_logic; EMCBYTEN : out vl_logic_vector(1 downto 0); EMCDBOE : out vl_logic; ADC0 : in vl_logic; ADC1 : in vl_logic; ADC2 : in vl_logic; ADC3 : in vl_logic; ADC4 : in vl_logic; ADC5 : in vl_logic; ADC6 : in vl_logic; ADC7 : in vl_logic; ADC8 : in vl_logic; ADC9 : in vl_logic; ADC10 : in vl_logic; ADC11 : in vl_logic; SDD0 : out vl_logic; SDD1 : out vl_logic; SDD2 : out vl_logic; ABPS0 : in vl_logic; ABPS1 : in vl_logic; ABPS2 : in vl_logic; ABPS3 : in vl_logic; ABPS4 : in vl_logic; ABPS5 : in vl_logic; ABPS6 : in vl_logic; ABPS7 : in vl_logic; ABPS8 : in vl_logic; ABPS9 : in vl_logic; ABPS10 : in vl_logic; ABPS11 : in vl_logic; TM0 : in vl_logic; TM1 : in vl_logic; TM2 : in vl_logic; TM3 : in vl_logic; TM4 : in vl_logic; TM5 : in vl_logic; CM0 : in vl_logic; CM1 : in vl_logic; CM2 : in vl_logic; CM3 : in vl_logic; CM4 : in vl_logic; CM5 : in vl_logic; GNDTM0 : in vl_logic; GNDTM1 : in vl_logic; GNDTM2 : in vl_logic; VAREF0 : in vl_logic; VAREF1 : in vl_logic; VAREF2 : in vl_logic; VAREFOUT : out vl_logic; GNDVAREF : in vl_logic; PUn : in vl_logic ); end MSS_AHB;	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd	11	17242	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block W9ikAzfkNAB9r6UjwYkkLbO7xSa6Pa5uk+WdU1HnuyZEhmVth9jtplxOjM44FNqSQvXccO8yxQi/ NOIWOqyRuQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hEuem1/oUd4/OEXkW2OvYqIxpyUbHGfY7GOC6MYHG11DUK95IJjyjs7VGLCJVTSk7aMQu8m0Up8B V7A2i5Ur1C/MGpffEfJZxWT9TmFVFogk48CVrfRqfUf+EY/RnTok8AxbPM/CybW1sngqZ0CjEdAR WFwF2WmA9kANp7DyS9Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block YvMHbfeLoNrrdjK8MzZ3wyAsEds/aUUU1qihbPDmGwW2kx85UhHj3XK9rxLVtguq6gNEFC6HhSRq ElvLoh05rPkMnw6WFsbKYG4H4bGxyS47kd8q3QuXnE6sCz6iwiKIv3dpxTb7XlMwEgrVo5qwxGVL s9GGRvYTehzL7krjc0uS4aFXrE0IozDVS75JoLN8e6buKPj0LqKxI7eJDZG7nEfNSuwPJgV9jjsn hBN7sE/TpmRuBxik41OE9HAXgcn8nnK+V1lhlH0VRFNNoFpqAT/MO7xuOSQjqp+eRafuukS3cAC0 2Sj1JyG5X2zzvgGRtR4WAzC70VggYtvYSDr4fA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block odYDbVugJa4zsNoidrU3zfx00EVw1f1F4ZM7PMiUD5vBKIyGujE3/2kpootoEODrHYYL5BLfkUxF BOQX5PSqpPgaDdiSWs2KCidYq7PHZN3L6Rfg3lupSDrgIHrKR+n/0uxrr/QGDaV+/KOkCbB4EmF3 NyOLBbCEbB/cyic67Z4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block eIzvt2wVqO3FcBIgfe/d1GrO8xAJyZ1wgW6um6UoZcItt2tjAa8e4PowdMaz78drHioWBIt7t7sB imWtFcP0XMZDfFZ2wKw3JJinSToIdJDnmZ+SigbxdzjvPvdZmXqc/soqccpjzaBwx0DzDM+jpCRD sdcRaQP44+rEYmGdQzUtkX5LMZ/ySPHZt7L2ejRcX1NR7tjsbb6iftGBFtOOKIolJXES4o+D0lFM w4plD0zfXEeIpYzOx/B+7FZQ8lYPkEeG3Q4nhVL4OPIVDrnnmCTdbedEddsMjHf/oddTYPxyD/Ra iW41N9W4EeySOPEdcOEovPgHrZ+ZDykNGAE4tg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11024) `protect data_block wCi1EGWEcepbgW5uOEPN0evgYS9XZMSzJsF/EcLsBFhCvSD1oOzqmP8fJeDLmEdNQF/7YfTTGwOG s/wOi78uIdGAW8EknbP1v8GZ5t6AckJ+EAbHX2Fw5Pv9eiMTrctGH8sk1YlZDCuPnfV55Q2O0zud +0ZgXnZlrc7F/yyZf/0sL5RdhKarwiOYPkVaXJQy9vCiCznzitdbynS2yKkF1aLC3vIZhryEd2L6 6bsXkgm7ee4SOk169T8++p+1X37L+DO43l3b6H/OI1+62kC4OMfxcvL1jRl+vSBIkdl3HUEXQrCw BmWHZcuGnpe/iwZc1V6oVxIxWi4cGY3ejnO6+VJ5a4rzjl4OlufiZr9qpgclLk1fxBa6TbGihHi9 RDMs4KeyGEvpcjzh6tGhCG/gvV3VK3M7wp9uT7YEPNHxQO3EM7PlrsX/DYSZ9PzM4RJjzCocSe/3 XiNKaR345NJXRC+Wex8XcPYAGljr9J9w5GUwlC2iu4yMn3fsLiDyiN15qNEGr0Tl4Xth4CG1sfYc glnF3CpxdEWH4FnY86Et46HYGX+ezVvSVjzWPfQII4x4TuqPCdxM4hq53UY9L8QnDPjkJidKkAYJ A9SVIQVaSdUJb/fJsTc5rdQBFybAaNUc3RWW//Q/aegz6j9UZTB4EY+Fq0UzFmtB/D263K+5m5R2 k1jVDCHI37Mw5Q3mIzezR7HEVX5NJGQP30WUpwf5n0QmslBWheGmAaBdXi1VQAj2oDgSvzK4Roj1 oqpd3mMkX30De+pToc2HoY/rZUV73JMlIMw0KCIskkPCTA7ip+VF1+MO5EsiF0xIZ8p/FkZhkGPo Gi5RbLu1rEg2F05pIat444Nyyr3Pej93fE8aJc67F+/NYr9AVk21O3C5g7oFX+l2Nce1AuajhKwK 0zB93kklzSo7mCDRBC8q7PEMADV7fFxZucBy3aK8WU++rS6aGKvHQYo+2p75y3i4EMMBkH1Rcqoz CBDgAyuUqGwrEfY65q2fL/2jRGPjSuml/rXDYuZlu0e8j0ReNOjghdJSehSVOXHCyHM/xw1qBYIo uu0QnGqCpTsM4q4RdHu9HlYeb7yCMqSkjYeM1+X3xYu8J8+p5KKY2mUE4eWgHtP8CE1KaM/Tb0Ow M2P2+liiXliBjWMtM85usfHCJ7fmmm1r3P8jk9iuggYxmEjXFC63ULsDz6owyUT1VfVXpAIp9/ZJ u7uajzC8LEbqWkwqWgryamL21YBZNwlyNfVdbSiclHupKmo3pNGFhYwOmYlqS352zcow2F7u9+xi hUqZH7C4inw9SAFF63DmJqxhVE1mQjcWzRkw85tY1KWM6B7udsNpoKEM1WTqI7qQ+53iDoEu5xYX 4TWSLv2MSWK+djqLm37+GWvOwVSDkIkJhLGlxOienriYDND0QfWDwNcyTjeD15JdJMZTVEYtmU8y IQISw1STkXPechQz3a1Rh5jWVUyLi0HTzdHo52FenD9MVRpYD0qxoBH+H2Sj536fFfKbTI2ikQPG z8jiimt1UA4pRXwRZ2SdUFdLHp++REwX+6F3gnZbDjjJfhP1j1akVyqDtJiJOsDEaC1xx6PwaQWV 1lFxpoiRpTgQGBwDj4H6zqpUJELMM9xoQdNcVawIlV8H4xSQNp0KFquOdMjw7gk43HAvEoV52Ucx T8G0SOKKXyQmn+d6RoF4TZiPzLsGLI9JQ3fDOnU+ONTmPwIa97TF2/1jt5rEC3BoZlZl5J3iLjym +HwPiDdyxWmDVN8eh8YTbIUbx23sWRkXdO2OxFnLn7wNQKPAtPw2rVHbDty/enJJ05RyJrrLrsDT cucwoxxeBYKjwEAfjRZqkCDGUioTv3uC9+7XJvxjI1GNCyFTtLwCCL5ERtiC25hSec/rtw4U1PyC LFRTHU5FERCf0Uha12OzrTndcISwL0Q9nb5McAttt44W9asyyeSQXJmtjxx8vZhBBv3KDFEJVZYd NLNr3+KqXxd5e5EsUXiXu6JDrjgmjVcg4CY0fyKZ6AzWLIO23g+fLrmTjEjkaqg93g2rcxdibiC2 waVnqlSwtmaBJdGxdDlVJpgmHKE62H9wO9fM9/uDkEfQQtfIlXIA+9k8PDVKueAwexRIhgb3mIFN uptop6MXrrb4kSu4iuxMzbCT6fl+/NgFz1AXVItp8SH1h/Trer8XpdiXcvO778r+66DugCLXYS/s OIRR25AD48R1w2GP0649sZpXLfBz7F0HqCLmdgVn8gMNQ5eKsWdXOnpcQIiP6hX/l1FOLdMdceNP gaatnO4SVC+162i9QswQXO7OlN+epuzGKmPSiTLYygv85pACrYF/KnSZm/x2tlWh+wVZkReOksgQ 2N+D0z0RXeDWwtyHcsOM61s5kuGRbNgEf8K1bhCo2G9Gfv31XQMTLNupQOTuFm3oVLClNt5WhDm/ mrV8YpxXM9JhQP8wV2zVAO45sV6/pqZGkqOOB4nSI4nsbD2ISQn2325dzZ25uZMmUGVvlbQ19cAz LLV+EzYlV9c8Br9KeG8BGUrxR8dFCunXrnTGyVRQeszGYBJaBtJm69UpBBxF3Jh5mGvmr0n0sJFo F7Mgz5IglCO4mIUfOPRMsWmb8JPB6yUX9MaCvjILyawpazflhCDi8aAjE07GCW7VaERKnY1hAVIA Re6UzqWdTIOWz8miNNWoJWor/+ScvfzOwPaGhPVALiP4pZVERb7JIDgUDeR/6EBJ6grJjM8Bu3Ll 9m7bsjxFoSJfwkkrkjkgjKlOL3fl1/FLFoL+aPfk9H87k9cQ6Bv9RFUGNLF/taOw+n8UT90Zlh3a /HmP4OyxGohsCGcc9FDhLDhdwKVIg4otoyF8/ZE0B6O8DE4K+o+CKG6MC8GPyEbnCgcQ8P21P/b1 wvydvR1ISUCwoSZmkgDtXFfnaL3UPnWHm/xsOWX+/MJLNsoXslawTgVjT25e8J8Yyflj5vyKiHNI 5lpNEPTvrBzidpYSoQ9+v62kKOyKwT9V00ne8rXZxXK5/Ei9h0wc0DJAzRVX5C9/CL53uulh/Xvu Q8yU76t3lpZGujaqWf3XCHi+TEqjxkrVubny3pUuBw9GoclaqlYCeV8OAdkce7C535FnNXlfZfn6 vqF1Kbti+iAFI2TGU8NDv1O1+2ns05P9++TRXeyKJUYBVnhUswAg5xZ6nkar8fcORx98ziNa6fwZ 1uuPktpyjrXFSq64UbVTERIA6TwHImc3el1+hKsFQRS+nWfZDvKLqngq31yEjkFttrJBfI+hCaDl JnQNOpuFklfg4bYw5L3P46b97uKq9uNmAHy0ezNU9BSoVI4xvVG8thF+tC/UnN353/LZ/u/2nr7T VFX4x9doWaEtMnpADsz6lxQZNSKjh2DEIA4GztQ9ix6GamPsINzITUnvzGBzpScLm5VseBy2PMQi SSDhcsdX2aymtT8K0SOkIIT0ImnjqK6nuq4qx89cCQqIIXMlmESMbhcJjA+iinWl9iy1f8uF2Z7l dVk3fVcJtcPlnVjOCYj2Rc9cspPF9v+Nt7csYxadnwcAkr2LHGzme4309qjdh4Af847tlVAbuid8 CYV4eMBbTaBkI6WpVeU0vBd53e4j2L4e/i2AwhY/o9BdtONqeLM8QjbYOGN8H+Hhuj3Qm+8Qs9EX emAmIvxoh8nFtlOxwCOVtRNuj7sMWjAZdt3x6+MLm6NOas7DYqopXWOrpT2oOtZvHQ5p/GuEgDSe 6Uw6Jju9Zq3Q7WrP+++YfW/Rg4F+M2f8EPRLBPXQ3ofmID2MNsBOrOTPT9lP0P6/LO0/lVfnTRnf UODpU4GJtAqQ0Zb5Ckwa/7idPRN716prGurD8uY8lxZuoKcXPZ4sRnt21SGZvXSZAneSnLHkrFfP Q2XwfJI/ilsUgxf7cwQF3IJq/xpvVUzYguPYt9UHGukSNgxiECvXWdWxVJS/UHX0s+RPz8Cxrrxm 6GUQQZ2VHelxubUgbVemoZVBSr/50f+GDFmYocgabwl3XFQna4WZVtmx0j2Djr0ZMvlghtlFCDbH 26xgqSUWD0lF4rs2yDcfpJMuK7p6NBC8yTqo7PJ+wi4JaypSPQrUv8AsuqYO2mS2BD5wN3gM55MR uJGpM5PoRnNDYCe5okDEzh+vfVBtd1vmewSCfzqbtKrQvw0AN/2b3iSF2wKsd6elS/JBbvDJeXR0 vcaLurJt73FtjHzMvDVWwBjs2XZVAkRy2g/6ax3EJel+aSsxrCLdVwUg//cF+dNP8O57BZ4taE7y LClTQL0stTDosvi8b4DMpWvMEU/y+/EAf7Gooh55Bth3hcWzU+Z++HciBWGJVnZA3w041qkK7F7k nrcpXABgxCSW05l0Am2jQOHdm9gqrsG0jOHBSWvpIeQZ/6cgotjsCH2T6a0cAFG+D0FyJ1h3pY/w QEc4gvHNhj1vUxt4LHVcEXZ7d9PUdjLY80iZNaT6XAq2OvwGoBkGZ0EIA+jaTFbMwc5M++i5MHxw AtbcGVZ/DvSV2A6ZfjMB0BJ910HgMsHkFPk8gpx09xssqKyoickNmqbOTRzKkApmOtpCKkV4XYxL OjvRP7hQIcHhmu9808MLz4C7gYfHiMl79EhttiWyB3PrPvxavHXmfa1dnEJLVOIGncRBk50GIIGg HrO+kb3YjNpx46IT2NY+/VCTXNJ3mBRkkUGyUMD/LxnONccqZ/D0+eVoVT4wL+cmeCsUTMt3HbLI yLAGCdPejK16Jw9Q1FR4JhYK8pgHUvJyHi8zEkKe1g2ajfMWGBgTLk1I6uuSvnXJLLxbddK2gJfK JDMgtlc8E+h4laKrZA2jBiTH2mweBeZNzsaBtO95Vg8jqXNI4BgwovJzk4O3Zcg0UYiuyq9E+iCM 8MVkTxPuWYPh8tuVMSY3TrwQmGJt50A7CjAKalLx44K8UN3L4zZtpzNJRuOuKU5dg1ssAUaCiVjj zhtIhRJh8MphYXXxi35HSuWRlQ12KRrpsXefBadtqgrfoNpmBtFxwZR8vrBc1uaS9NwPWnbBk63M daE2DGX07+agz5imV+o3DM60yc2/40St3Fp0EuGGYBF/RiHJyhRfENOrQf1Zlk5xNCqyhR+RmXOF EDdWJYA5+eLQICqMCN/ZK+ImITU4xnsdpr2lLhCS1q9I4ivLjGy6VY/8CoVwpScON+33WdsOHqU+ HiQl4sAd2n05aFi/kCKfnGBY9Dwo7+MuVH3/A3SwyPcIYHMEdAngKYbdq7+OETPEAvPnukxPeQo8 WvjZsG+kvu1ngllQBwYYjnEAF5HhiZP0MnadKUS6o0C2t13rOEPB0qaBsYB9ELEcy+KRWX0Y4k0Y CKch2/HMoaSNrgolSVp9Uj78ko+cpf2hO/7Ap4CedHfgv/qo9TNjNBbBicnW6pqgvMZgLmEjzBGg J7WOrMNNDvIrA8gBP3FHAbAXOr8Gs699EQPkQCi4+1P+j3tvsZ7z3gBCyUPHXvkD+StxtnA3BZq5 dlA0EKVU5E3QNPqHTqDFiJgnrGKz1uvgOp/MLkPwbAnfv+k+Cb3P+4Blg0qHdKaLX1okmpODaSa8 JvKQoLJbgl8gGklvGrlORf+OAdO6wEs0mA681HnRhFvkzHCB8CtpZnMkj+XtBexkeEUYZHvOh3pL yOfBF1a6qizc/RNu2+FannoWoR96t1fPF8eklFf+cedAWEfaPK3nWGej8ukaMXjIKbg9fVT6KyDf wLQrQL4LdRFWB6Y/9kBiMxDuWdP0gE397ePL+HOLP6bsGjqN9zWsntcqkBRmqO2CMVVGS3Y8148S gU4iPECb6FwXbwc3yjcu4DxPuJ6YETrlybH/nb+kZsFNms0XKO6ND2xTUixnwzyr1N3vv6F0CWe1 1UacUML6Dk2ndWa+E3zqOBVwFSpRIHGZwb9syoT9PMvJXmNM11cc6WEzzhZpbQJB8SW4rNqe4f0L n1fRwmvHyQefdv1eZKvQr0EL2i4CEGAdh+8pKR5QgI04d57PCoJQJjvXiR2JfYNd89BWMtGK6zd2 +UWaNp9uXCurzNVgXb7Q5XctS1Bl7fqnhGkifP9GBi0sOaLzlYrOWUreezuC/Wm/i80zm3HIxrbh CphcYYEUwf+scO/1cCTYZWeOt64nPlNZC/I+ONWyG1/iUfpT4pLH6NLZysqRDlZRDML3VUQNUxDr XOujCaTRinuglfapVDRf7ZVegPTnWssuG+QXNuur50QuDW3K6WkBWx7bDiKH2h9rvNc7ktkERk38 heGQygaO0qeo+uB4twoVBNfyNKfO2Nd5pwVIaLKHxTmNNb3NvaJZ3dctvoC4viNP4WaaK4Q2cmTD aym+cyLi3OUq7Pd3kQQPWaxZXbAIojzcBRS0HAryuzXScnsbL9493fqEe7di3jS+qWizMjlx9aGD 3+8RQEb50X34FqOjMHFadbS0Smz9vqgi88BXX1tA1m0cBYYdZ97ZIBEj06txiK+MTHDQdxhxNWAg 3orony6RMm+lKifnHDZZWReSVW4x4aHjASJMMCSVAmk6sjjmrzAdL/QO7Bx9+UgElmvLlpmMZPpD m0X1c7KJJ7VqDsT5QmKXCnwd5X8BDxE2155esUsxOsx8q+rDw0MzXZwCf1U2Jb6Dw8xEbwOZ40jz ttetB2fjsJIbDrJZe4ZwWhtTPwIFI5A4w21PmugJtsBDNw6M73CEoy4+PgYYxT+VLBuzc0VSG+gN qYJ4lwrkBzxFmgU5kYhvkkLV5o7UXPHq+Dn2BwVK6J3Kbd2pGu8Dzhc4Cpit5kDLuwWfA3gt4TGD rykl0ClqIG0HYJZynx8FUtv5DfHrwLhaJZ33418ifEQqrJuGR27CkXR5v3zsElLqcpM6y5jglrxN JP4k1npi+7jM6E0i8wEU71eOm95QD6BUd4aZij7R7vjD/02R9l/7L3j/HHpgjPFi78CfpwLhfuyB H5OPlCC1tPAbtWVsNtcXN8Ab0HWNuPsPIiDtLwvIe5F0SzXnX1tjbXzJuKUOZwPqTeCJJWOELJdk wdvUfjCTcB1FcGoLeUfdmuIFE+RKyS7zbt2FqcRIUzgzRzB2bDZ/uL8A1diLwS/IRfEo07STqm5v NFdVn/tcWfWws8udUK+rDuF8r60p+oeUEoj7LsrOpT0dIkIISxjGpuPjh4Pr4RfDnFyIsGK6o1YG GGI7bo0D486P0n1B+zNqE/Y0t54PzRLzgNeDYmLPRSoXWQsVMNkuHQRQrlCEYY5y/FwoHy4yc+/o T/mBxinOwAM+S8jDUnG18R9HmgohJk5o+s8+L5v3GxxKkSkpXFZAmUrVEOfoqnKMwxsiwsiyDE4z ogdndONAvMG7y2pWm/kdTpLY+tYkdoatms8zlAZMPX2N8wWD/GhYzIwd27BaEdmeeFDhzY7bB/I5 LTo5U9yM3sYxUOCqSuUf/VG7yiNIvmRVehgNk/s1G1ewwZCEr8gi9gOLTePLF9aQUhNMJS+VU6AW qrh6xlsbGVUYk2oHtGWBlw40/Wqe1okdkZUKvlMxUUMxkHBMCphMyuCjhF3uwRkdH3nD0cKJI6cd MzAADauO/m9767UuQvlgltNUk9HJbpvnt/67xQA5vu67/GTyZGu60uToCuEMImMsBzZaiUo1NGIS vdpfVnGfM0nAe0EM+kGVQSdP1QLgkqCW/5UYzPtibyMA+A0KAr3T8dEHBnkO1JMntrE8arM8VP6P M9klHAIXIb4Pnzt5IunE5leV7dy6WPepP+F9uyv4O2oPDA1PTL6BWj61uKlUg0xPO8KCtWEW2lAT IRLjFdJJvXslKd84Tne5jvwRQAQMg2WocmHiwk7TYyWihN0odqKNtmSdqYcauD2QDzTT3ihBnBjJ 6ltHjrCfFwe5NeWOnqUMypMPtZXxjH17d1nIPpdm+zqa79/nSB95FS4FG9vAprWvmwr5X8RcJojD 5vkOmoQtpYaKgWYJz28RekldLSfNPb4H8mYjUxOmizCSgbfo45l+6b/hTwFCCgPG1W89qgOhlrYf HECCi9tEPk5XYM/WHVBty3A8vxcms7TF4e5f5u0rxRnM8JnwYuosVCmJpfjo7myfsexQkF/BhyLx ewQbT1k0UWHWV3B6a7yO8G+DLz+kOt71BICmvR3AeQFVwyaX4ldNbsaJeUZu4jOkyx7IpDFpSLa7 z90EvaHOShqu4nlPI95Ke8kgKOaQ3GukwILrFwz4w+0NvWcGNFH37ozx3QxCsQlKpdgt+Ib0iBBg h7iL7B5oYOeHm1Lc0fKIspVm0GvHXamYCK1xaqQKpuC1qd/sHrc33ACYzcDxNDeaVS89wgDfh2vc 3R3sO4PsurtD8zXuIUcptEfgUpJnUTRWgKmD0P7H8pg5PPHlvoq0B0xXOZj2lhAvr0pSwputKXLb Wv4M8F/+aWXf7HL7bonuqT2EHCOe+qWEOdGOr6e7YYOkUULd+c54YnAtaPBkI5pWIWSzy5U3b9nJ /p8+zVgoXXBkUo36PMqQjoppaKHP8xGwMY9IjndFt4XtXwpbAHxExUQCyLRRcvPDJnswjxNGD8Cx c3kJa74PjFdAzbejqNdOFviT/EFkwyO1pLxLs5BoK6dRgiqQbc1ZphImlMG5wiB3DU1d2QQSTMn3 fVkF2YXM4/i9WO7bFT+jDzCPPD2INmiF2wjzr2d1cOGoKU/ROPAxk6ZFyhCJ74czt/CIdy9oUWPm ZIALnrzH/+RdOMKIk7NO1XHj2xU855YLuPUBu7GJgfdCNsSdKuCQgWaeUINi2YLbiXtRKZqSkKB9 o7h463WBwWTKeX2hiYlr0c1BnMW6kgqSbEFx75kLUaTUMm2+UI/+lw+1x2BHBP9TB+jvx112YtyW udDOW7g/7aAlDYIyYZQAqYZUWI2n5SKHrZH+aMUz6oz0jy7yTczjEHocXFu9s1uzEu9/awHX4161 qlL97LWPVkGWhLx2cTevjlDrpoukUEBE+RHXXfm+XP9jkd0QA3+1rUoGGoabbWpmhkUl1yeDWm/2 iUa4y9s931hkHMfw7/DeqyX+H0WjGthxkHOvBLEIuv1bd02/1vXlZcKAtgK+yApXUvn/XqqWEZI1 jGzM9Rugp+rMb4Vca042m2SrTg+k0ip+8NbQGbHFK98uEjPBb2NqWw30qxEIvxYlcirlImi8osGq QKigQVTuoiJz1z4MS9C6nZmj+6bWZUuzZm8b44kJMuyF3YFgXjWRE2VjYUGSWDb4Zlr6830oflJb FvmFbe3ZPaJiXqTQETeXuI6fSSkDZpTw+XJbdMLOD62UHG06clgTHF9NZwR4yyHPB0jWQ5TLPDjf I57V8jTs0lYVDnHL34BguNJJXtkU1a48C5BbuOlwheBO6Ir5E1Jo7HEaShY0wA77rMAgWqg9MV1k doND6yGLaoudGXQll9HmIROFWe4NG//FKhdqGOqv20sm5/Gts9vhjdulxNfOw9mepUUamVYl7olU XpwPjoWjBx7zYiOTrirUqH96iTccpCIb7ickww6IbM6QQjOgbX3Rz5sTqTa9xAVx/IPxBAS7FXOq GuSPD4sXIjXpZIQ98cQLdQnnrGGl/lltEa5B6B1wjrf4JHb+07V+K0kX4qf1rzMaxcY3QIuc+V7B XV4GrgBD/97DWOFOV22elPnURolVFxUr7AV1QVdcAwklf9h9Br4gHxQ9Wf0u05AfKT6EQMpkJwwa P47sjB5PWc4/NWzuMxyFv5X3mGnugwrpGt7nbD59Nbv0r2P2FENy8zjXXZ80KMK87YKyn3LXPmb2 q6dOWAgaWrEZrFR50Qev5aS5Pnf36DgKNvU5E+J0/BwjjShVU8XwgAI9G4Ur3/GRez0Pe8izzQG6 xQV5+nn5WgdnvnxJvKyYvUfcqtqXLv/OZ+EK0dmadT0eKPoCPyQUzywwlI7FNjn319Di4YIcdxXq K7q2IdPuXb76sT2MjAEJArApz1hGIYIYkVwPxAFrwzMCDbyl8EIuG3oIeUqyDjPZTK6+kLxt47ba 8G2R0/udH+CHwRW8JZ7ap15J0LCVLVa/n+gamRuaNCO86/BAObtCNuixubfs8vQImjkefo1SMY5Q B6fB0iVbcdbxEc0bQ72a9RKFnMJzkICcdiNv4Qpty8ShgBcTGEkvuMLDARtmOjBRIoMuKwcPYmLn JvsfGm5Re5EAAJYFC3FviXp+6ps4bdWu2t2NyvWXZ1ajaV4uwXLe9lgSgyTY+MKDY3US3b6+8HM0 BVkvIpSkeaDwua4C9nlm7JoOIEoDL2Ll3V+ABi0ki3BPa3Ye+s0iXZVbMgLPhBrDgQwdTeNWY2iZ 9kydxvCQpPagovce5+KpCINv1RaYyWqzep7grGyfVccfitrc3vC6NPpJnPuLwfudK/4+OM6/J+PG rXkhzDxVq9/NmqvRCR3Bh8Tv3BmxiZmLJKlvADm86eI7sYs0QF0Cq+PG7SI221Z8aWx08vo0RYLJ 5Shm1keaQFbDw+1jS+1Bvamj+L4K407vmquZwMfK2dM0zQrkgCWq4Yfed0lurnkb7mej17T46+vO uSI9luoSWTWZCYymqz+hKcEzOrIQS5yvn9HrXXbveQhUxyROqHtxRpJqnbl0wZ3DJgVYmbXCSS7W k7lDnduuW4kyvzKoL+6/UNTRED/rVGJnqwBB+NMCg1wJTdZ2Xi3GIVucxZRx2hzWZXkQ1YF6TxA9 lymDZjAh9psFClQxxpWOmfL0F7e5viWzjSKFim+aRUwdaPWHIdYSbBSkv4faJEbmC2QToilLjNkM +icgBYlr34gshG/BhzLW00QTvhA+UdvLMRC24SPGPVsokbrMVSWSAM60gjljTdBUFbJDm50wkm6s HMg6t4IHvdsXH8TvyInwyZ8JN2aVyOwab5jx7Byf0mjgQx6ZzKlo4XDCffHTWiSfOhYc58C7e6JK QHxD/QAJGit0pCrdy6LA00ZynR6tfTiUpd2x0OcXYIg82ChjvQ2TbtxSFx8EAd+/yPwnn83fJd5W fvZp8MWz098AMUWTUPo4helY+FA9tYpczfEgTIqCs4ptE+WE4gA/rneEEPwqkoOgWzgMYO43F6lf f4TD4M0AK5uWR/lxD89GTjQYnHILNoG9ci4E1kQsxVtXyGZlIr12gSpdDKWXexuJ42YPaqddbyNi ymODEWI6bxyQCAAsF83994oadmIyxeAg2RjqXpN37mhroY6FHN8SkLIS9FOTZl8VTSgv1fp9vjiA Jx/h0b303s7xNZ7hHMwwOgMwGYxYTHJzxnbAMf8GTXtcirnBEHvH+HGawnsC6quCcVpapJBSwH3Q 1SSFJThAkI5R+eLRK0nstV/nzKLcAqFlH3XujpVZ8+jNTBqlK4GxBRFLt4Aw7S4V7F+6ujg+dZ53 SCMMt2KA1AMK0CRiv/G3phXD0atibwKb0wSjaHVnfGa3idHdIxGI1Fog981FdLEcTBer1rs4zymB Z14gb7YkIFI8aYUBz7CtECXwOcBw+jABdqGmQuMPoNJnGkXV431I14MZRJpuqfcD0b5jbHkp14DN wzbom/0YYjAJPzAwXr/58oQWpPCczxq8ZC09sztQw00hmgMErYIEysWFjpNTqCMRLjuY9tmrceWM PJa/qWDr6yCSOduTZ/gEenngtXm2orzroHdOPGKKzHz490U36HVEKNr3Pt/XQU6AUVvQ3GLs88y5 cTDrZ4SgmiNf0UfEQDYFzwG3wHL4p8Tnl2nmuxrAVRQ0nNSst+3ydz19l/QN7x/fZmoC4YLyB6J4 ndKKDCgwb94G1LR6PCLZYh9olBov2fv3h8H2rtQMBZdBVLPMj6E2a2KHr9NahH/amAQNL/ZBgUqI z7K2myNcHxZ8ABBf9yKc0c/Shb+xrhI+ysMFLE/3qOKFc9qrMOylDYZcvaq5z07Fgl+9WpHpNnGB D49l2Un42iL4EeofMpBuYYEZ7/++bYP6o96ldaxcehGkbb1F+NtMXwVQW/XgYVqFY9J2SF5BujnE g6SuA26MsVpksJuD7vbxOzPtjPicuw1Fm+DD6IL+Bq90tgfrTAZMQW1IxCqcGKH4nSyqVHhKpTjs Ron4T9adljJYR7DsFNH6bjXm3ePk/snq7/D4WcWVkmY6Zsb88h5jZOV4Mp/QRnx2zaO0BoXebgAs HBCw/RqcD65HY8+/uGOqtudNS/tYd6hr/8llyel3dTB/xv5T3PXKIP2IuPLs33xKkJHRN7F4aJs4 Qt/dWv3iRG9cqvX8NyZMArBxAnDbD2ywVTGk6ZwRbzb4riv5frsaSnuO2Cbajiw7677Bxup0pd5V 5Io5QoTAkmIOd5uJ5FbziKKo+bghTpBE+4RXrq46GIC7iEVtAqEaursEsfNIWu0XecFEyHurmnwA T2z3iSMqF2WT00US5fdoE7oBAfCaCEJZqF3M2ywIvWHf3Bw1Ce3H8CZVdIKERaP/zWu+VN8a+D5A S/MfehnY3jfnvS+G2WA2jSHVyeWwjTxo7nCfQWPIbJDucHdJySiyiYQh1+15NhEwi5mRVR+bJ6Y4 eX2ndPdswspVL5y0+H0RsXZkoXmLodbG1mI7b/BL3DdEWg45Kp68QF3yuGw6iwvd1Q2fWce8/+IJ p7473UwrOkEvRWzP6aVC76E/hpJobCuXIASIlPfJIOoIt4R6WwCXNB4ZIIN3N5a5go5YfAANWYky tU5jxCxLyR/J0nF1eG47Krp0cTZ8Xnazpr3n/wbq1Y8hNUuGcdsel1RWleITOy0OWtQVctghqftx 0PFzNp/Vidh+/YHwUYA49cPon79VEjLEfQLS7lTt/jBDESAWnwEaLaK2TzQlknPHK/NiGqQRAVrU v13x33eL4ep0ZLtfQPNipieZ8qNnn3xmBt/+t1i4eVPhqKwTkw9rrU5pI1Q5Gsrz4ruaUvZq8A+f QpLBhoMnB3blMpzxQeqakg8X4WV5XQXT+KjqPEvyIovYcBNg1f970NRiJo7+AB/uMUpi0o0qlSOU Gz4cjwe4WEQ1YVgKDFpZlJimkuroij6Tm+avlzoxDqD3m/gpEhGbfyEddFfDBM5iCJ/3fF2i9BHw PX1ZIibfjGwFDbv62/FZjHBJuyQdEObKiWzY83GOOWy0chAqSfLf0NG0dmaHmKU08Fxf+TetX4O4 /AfLBiALQVWsyDm5ME01cmG/F0wGoIMJh3v8p2FyFLcxbuR/2wKD1Ki0fpHV54xw9yXhwDc1pwve T7mmWQ2uoqmVnCtn0WKsMu2dT2D4ShX4wzxEyg5y1mUQ/jbhUQ8tqpTp0YLW4RBu3pmSG82IpK4E lBrX2yZMFLy+5P1DC/hFvzS4qVLgXxVrqebDA/D3/oLt5nZ/Y4+Y0OtS8TlhFeVHlJyPSpAfbR7u wpPu/uMxl4BhF9CxwSlRsz1Zj3R7CfUvrbKqbnvIx6jRf/VUgEj0jHTKl5c7nZAWCmsQNoqU18V0 lE0hmaqSchE6dfhFV3OEDisMmT2UD3byoy76CavG5LbMjQyfpqFA/zcvCH4jogR3UybCKtXGd3zu JWjOAyCZ2EsISs9uVxqi6H9W4iZhnJS94o4+FkwUt9wtP5H4McFninSONxAz/P+H9EKIqt54ddce W3NxZ2g741cfWMXrTxT96NHVzuPqaCx8o0k5ACUiJEktWcaY3zgySVJYl78EC7UYbUAc6ugBCVdy k1+bImun3EC0iSvy7QJMo2iR0fJTdSNwWoCIlPXyChMZjazGrGdNYs+RBRoScNr1si7zsNNiyowh pTjVDUCHnaR+D0EpynL4gGGQVKovn8zRm5JcVMpJl+9/dNph0Cxr1ESdMpmk2FKrZKRdVYGj6fQ2 nG52LBZWAG2owBc16RlTG4naILE5Tbo6omsQ6u6xuT8nEqlvJctkzNiwbWOAiayZIMKWTFHr123Q hzzevdPgq+PLETWVpuqWVwABs2Zry5Cn8/1bY1ycLn979JIAWPZ+CWFYFNlN25pN+EsX/RHG6R5S KJiTZkoSVqcMgA0DpqLox75PBFPyJ7i1cvjK8YtTujok8e4VVhXsI/lNXWMTC/UbijxZwtH267Ce I4fMGbQQIMESXMd6WE9C3YnZ5MH6x2UpDFIkzWsQJQA7KZolxExV1s5ks4RNysoYkXVDzvo/mCmX k4oR9apqKxMCecmDlaBiNOoZiwzn5hqEyIJKPLKsH9nSDyj+JnoZMyQQvyMZlh+vPrf8rCFqY6hi RkbrD+u1Mq9vMeE7pidNai1Srz9yGef2OGgIq/L53Utc6vbDnICqYFW5f1xEB75dcUvzqG4rdo+T 5CggBverDRcHd0mfv6/cuCDA50UKoXchT7um7hrHO8Bpg+5LcmfN/Ih2pHLF3ljBEhcB0vXfOlcK Iy4D241vvk6g27GzhLpE8ygbJd5gdgAf46O7SwseHXBhsP9j8KWZt5BXtsTED+LI3kePgYlW+5RF uE2dDRAmi02Ick7uqMtVEvW0iPsXfaZBD4uIyTkVxJEl4PuvxkRMzxk9UpXqxzBED4LKQu9Xx0mO TDZWT/WXqCembv4/MjB+VKBed6NZzUIVa5hoa/RHKhjwueQLtiOCFeBXMECrtjcv66lhe7vfb9z6 +5/p/1CVftcsyrdAPnK0cRwNJDf1EAaYh7BPwK6H30ueXZtm0tsVo7VdSz/sYtSzIdG72vXqeyCt kntpF3Ak8hJmnt883z/0Lav6YRbzEKfW90EuPMm4AiewTM/zdWNHdUN23cJOcLrF77qEGEYDe8Sb Ridq1vEgTVRnwCYMu4+7sDFYg6jXRfk= `protect end_protected	mit
PhilippMundhenk/AutomotiveEthernetSwitch	aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/common/rd_pe_ss.vhd	5	46465	`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p9mk9oDYGr8pmZkWXbY2TLDcNbG5E8gje77Jb79LHblLzT6z9srp4YogxjZP3AdpB91kWPxyMOW6 yZ8yldjKJQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mVXEkppMj6g1IXjCy7VbBKs+xRMg53vy4CptQMu5kxBNHV1PdY2Z6vTMCczc46movp6tA+re7V/F HsTTtWCV8ZPfOv3mcdhM4UeGfFJKyzETnvTW+7FBhhQEC7rVDuHV/zQIpFu2woT92yIODVDJv0OJ d7TknpWbiizNGWwk/hI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kaEPvPGfpEJgQQGZTZXbF/2CvE4Ypzvh7RT2RT4lopARsSjuV2b5tLmuzYSb85Q5AFDGlfRWDwtx F2YZzMpA5KuWPN8p6nQWyhLNm/SzroKHii7qBz7lYa3mPULaNNzH3dQ4LQE55pFWYPOfv3yGdzz+ x0MEF1ydRO95dewin0KqN+iIoWFhfzxKJvwhtWiiI/X05UUfC8+LXpcJqGLxKw605Jlb+NeKbbhq fYieug+3ebVwrZawhJ1LjKOdIJ8rUBrE5RUDvZKfy1WLh7meweDSbRCQB5rPDK3OcggQilKZ2mNq 8WI66wOyhQxGZBLF65BiKY2T7DqYxJCp5hGwRQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CVvJhNJw6EHSDIQ731Kbkfkwh9Wl9VKmiOV38T/SVAU+kI3c+cxqP00ao5AoKfnBVtld7H9d2J6J kXhNjYdDnAvSRM/7oTsMkgQ3b7EgkwQVLR7bm4uQPlxcIXIdQ0tZoHzgZNTJUL7DL73vJLbed2E/ KzI+61P+AYGjXhbYkqY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ga5Bitt3CebGZAmuyISY0yRlSG9x1Tj+suj5BLHTSTSYidEbK8uW4qCTr6BxF0yV4Xp11LL0s44p pTF4j1DpdFDEchCdBhPTnweZZpfsgl1tF2onzxM6huOLdb8WUzx98iaDFlYXkwOae5tqfbg/QqYr LyzTmB6gN+UHIqqd0Nvja/wQ+C8qsyVXUotU7XSAyQnl09HX5VboIooc80WNwl7i2epmVdrXOo1U vnq8TH8TcTYxW0QC7SWveJRCbce/nT+MzP+z7RYjxYN8q+AXvkoPoJzcA3kTVwwvXpW3tNSYC/EL DULswVBWDYJoUSH86zvW8e9kh4GPJv6rviHyhg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 32656) `protect data_block GFUOlaXsp9nvniuf9Yj+35P3XFkM33Rly/Cql6L+SVOFmDHwBnnl311fReTRdQswrOQzkIK9mLV3 Y+dA2qHWprdNKpYEA/FKxgvP9cBaoJrnWYNV9lVLg0aeJ5CMyiLrZ8uLViaNWnQcGAEK1EVOh8UL zIePotyeAlUUm4fx4kAukivMG1+ioQAfnSS7NCTp9WoreSpneaw0J2BtIBwDvzO90Km6jK4nCxmL y6xUpkGHEkXeJVC9VJ4GfBtb3XU5LUPMW6BWuNVnTDodSW85M1IVYLcvA47nJsdjT74DatyIgYUs 9zipUpHjbhfo1guYIveV6AOOwzclevEJzodFZNIs6MDOl7Ue1k63UM6tOBgRCSAVpdTtX43KSdyi W8gSSE/xRO2zd6CEtdTMUECMgz+FM0B8rdhfvw1+PFgul8ga9w47Mlr58ZFW6w3gnvpHAXW1yzwo ZWlth4GrpB65EaNMZGfnnMeFy00Qa+ShgUUX0ogN1bQoXO+NyAmZbFFniUxaCvsyhRILviiQPiUM z9joSRDSoKam7aQ9M99HubxmB/uQcJHmoCEmfkeyXp699SJwCFc5BlI4cLWYSTmfbDOmGPqYAsGf Y11t8WlliSLcAjqgX9O7Az7cJvYB0B6F/fjcIl0Z4Qy8/c+9y9NSpts14y+eecL3o7CsTFGYCxts mcfvGzAD4jaRf3eE7U62zUK1740KMj8i1V+dUZ+H9pdT2BOhyQOWt30MzHy/bt1Hm74dX5t/TkQK OyB6pSWgm/eVnEz+sARa2+v04N2rJC5tA0HXAyR4AohGrMuxgbzhVutpRXQ0+dT7+puOzOnglslc 6GSUcdugLQRCDdC8vaeLrPZdyI6FFtxWl0V5XkM9sAVNDWc7rwo5goLkzYqMwdGfXwnmlDOD/qhg xQ59aZRzFo1TUwUktuFrnMqJpiYjES00iA8Cs4o928AIbanp39AgHKzL5g5CWLiDax+O0A0avJtm GDB1kQnIbMHXOKmoIxZZ/RkehaDc6r3UtRYqREaJId46EcNdYFHXUAnJATvu0utFCOcMPs2Bivo3 fTJrFGJboYO987BWLtP4TOQzrzqLQ3cghfIWGZuAAONScAf/4CqwqrC1PxzEPfNxgWLnoCvO1cAm 4v8mkhe6yEC54/HDXzbJIRAVexllKZnjw5FYIgnyzgkGpZv3pTQ8cP+BNMpwL+pre52bX7ZfHYFz Z/v3axxsmtz2XzyNPpHKB8n+yFlaYXt7yLwQLkdOs6xxFSL5bFf9VIlUullom31Lib5XsWh5bd5m VJuUKcG2wLmgcrlVtA0qACulzxVbgznOq3wKISC3nGZy7q4Y1CqKEVUuXvVdJQM4bdlAqUzKOnvF Z2llXnGXMHdNpJnBPYNzd/vdunDO21Zm4aghBDU1ZotyfIKNtiWvyyctK4cxUcJ6BipqhxtmjZAz +pOV1SBbqnBMr4WdvNmon242BUAMsiBhu/otZNFoydHK38NqIlAbXYS9d10/D2x/Cn9XnXEKLK4N hNtEEPDnCOg10GHtVARfC3toVhbWL3fK7jos7yBSsQxtGVzYZqBXvf8bd93J0eWP8eyHYpYeB24Z JUzjNn5s1C7uBNKYcw3OOGUI6iHLC95nJuaSljThX+O4j+HlwRUdpOCNgX2pws9WVa23bVvFFd/F NUwHsacvXufCrBQnFvn9082Y/2nCLZ/wST1gE7blYRsHouXCsHD+Ca+QksQcOl3XQ7PQRYeSM1do TjMAou110MAB3/b2SyIOb9Ue9/qDK4CCUZ7VCxxlfXKlT/ubgVHNJbG9rV+TyHntRFdZjt5IXYqi XzP7iq936Uc+LXXvZbOj2Tw4SK9gU895jH4b3BOwIyhXqrQpQjrAVTJuTuDZb7Z8mHDIhVtN/p+k 5RvZ9iFnh689QcqtGxMD9EHcAv+jkvE4fs3aChn9D8Qstg5dhXT5++NoKYNpEdiPYNYJXKPo2kU/ 1NkgyB1Alp+6af9pSiQF/cCpOF0YrAWGZoY+GRBdAU8IR31+r6Yv7Fe6gPHA9rTvhhUdOG4WWRiM U9nnPUfh4H37StBYotcgmCPEGaX+t+w8QZCsyi1gHKm5mt/AT3LWqhEamXTl/RAn2YitGOIi0bEK s3RrCofyxJJQ9yDD2mzb+GEmhfq6NpjokNr32lDB9S6aErABkdqPY6KDGvgAaimH3e9lkuXHW7/5 mdTDegHSn2eTA52aCNBl99m0Dj/5CNdH7yntyvZ7vDSvoq8uM3ouzvc1KZWwjAm+oWbpmh5bZ7Jr l9laaq7ij1rnk6BoAQJbRQ5hwwBlwi+GQr+yLtejWMG12aP5b1SdtGCFCqiGP5QxfD1irT5HqJst WMl4UWOeti1okuC8PDkPI9mwHRsIByul8KOhAn9Bn9HiG47sr7b/9A8oY9js/SS37agXjo3Fzjig b/R9i5J4Y38Uku4mwYUqjl/s/hNfUjOPnD4VwVFE4kEPoPTqM16rdESFfy6HCl6YiCNVo2sTQzUm wAX3yrUrLsDU357DXZ3n6q4s7BQX472RIkkuyLHyPlj5JoWt19KCqhuSxY+SKLAJ3gzQ7Gc+3xNY +UtvZxy/l9r35kvBExK2ZmMZTYkQIJDkB91/dRfp+HtjmH45UZo0Gv7Psi5JC5iXq5QHde6rNJvv 9Cl3E3gKlTZI346mD/dyJL44mJZ1WMLFAtCHDLRTHgY82n8vLRYvp9iLSa4XgWpnUCp+sphjdy5T OtjC23CERotVZflihiI8rJvJMfwlEM4z/fUqy+7Ii90jKsJJEr1GjQbbA0/EzLkFQrjRxuE348ma jqvx2vA7zKZYI1cJjrmaHEYjmy+0TdxMldLeaH15WM7sJ2Uz5om8ItqtmzMbWYt03QMPeCvWUmXv rxFzNpTCRtDC1hpMOtkX3EX3UsEXhggiit9pycCRvnQ4HbDSQ/4ugE4GObty5kZrpYAbyo9MEhYy L+mU2G6p92qHx9560fpesWTDTiFwrPksBy2i9KJp35q0Z2m3e4MxnV1L822Sb9o29PlIBESXPtTi 73PqX7GI9pUbJJGT4IDGg5pgkvdzJQwhnYcg4UyARnU1xiYdCaBHeSK+HPnzzor/0FNUVcshRV1Y fmM23qJlOfaNE4XKZTby7CLYkYYEDjBzZY3tscXRr8pSwI6zW4Pk9WMr90F0z40fS9bhzSEE6Om0 hG0Q+FBEJdf0Gl5y6fXOw1F6OGyBfvfGcAm8+cVY6gjCoDXLoCo3i64sHT8jRgNbfXCclqP+Mj/g 2UOnDMOhEPdHlu4VNxtHiu/zQvYBOzJobM7Z5fIjnYB1TQ1vsNMgcFQbRvMqYkIXA3WZ/4mBMf7H lfwRg5WlBgaWZOpDI1gLY8NlJxDtzwCQXAyBXos2x3QryjqD9N4FboB2Qz3MjPO/YlSUhtonp2CF uaa3Sja2XFk0qjZM7MEwzBbqt7cDnJiBQMukWgRxnxOKo4oA0WXNu3nFP2d+uko8bpiuvmJUesLC bjiwqELal6KrawqFPKLLIKipReChhx4cs2tM+4+cqHeIw8CYzqRlM8sj1Tc0n+TjtdHorDlkVZM0 1MVMOUrjO/HP2kOD/XKZ1OJajoLoWens7tG89ojmqQW2KtOIXS7h58vYTP/iU9wltq9Skc2xlq3L Byi1P3j50rjnU6/zUHJwiGNvzzFkg7nYkju55rd+JTKkBu5myRg+T8VOTtu9i3K7+PYmfuQBfqYU 7pGjQ9+rn98G+o3IEsgPv3z/lXf+S8npKA4NXWdAZwAHhSyaHZL4mNlJsxa0qCVvLhRlxlhH3QPu IOvTv8LlcjyGsoKziHALm53faD4Xd0YBcXvn4cHuQ1uw8jq9nvyxc4u5PyhK3+i31+rUb+XbM/Sv ewUi78bhNKcEFbFPt6FHYjp3G2kpcSm6HsfLDcn5mBoC+8p4d7BUMuGgJZZ/gmX/0/eOGmYGYjOx 7NNRik3UfdR/UA7ZN7ehnHi+9ld0iHUDziUhU39iEmpdF4Va0u0JW8F+M0bydAPS5+EEECuGpyjo 2JKNqXXAVkyxUXh52aeN1kAyFYTPV/Kz/ZBY3zkCBZBpTgyfYXjFZYq8iB9+drVZYwQrAaZTe8ty RqGi+5YHC6eqmXJxhyGf/I74xSRm+FQrje20QjAsE8NJq+72xoKs8zi5X05lUJ1nMPjWNqeB9MrE 2yL6BsR2P5DbhvYudxssOVPZINBUXvsxX+KRrH+kbr9gYq5+4yE25fPKqfZ/GzquTCC17UQ7ZaC6 wKy8Go/pUZDy9EtybH67LigexrJHrDrgkgXcc0c3t8/jJ3xCvEhZrgMQra21f0J8VtK9iD8+aKra FU5ImN4Usi+W5y8hlzuO+oq0TS8JOT3QpYZCzTGGlGJ1PR2tjkBEjegrdqH17q6TP6+zCBuhVegB 7QdKLx6m+jeup/gyBD+r570fsEX9MyHyIJulVpdz2Ltfwz6V63t/mUM9IR5OcljACsqkdqs1OLxZ 4hNBHsg/TtSeUtRoyBg0ZckTKTC7urRkGzygJV92J4T86ejueXXmy8SRCQVPm2FtIorgiUZPYNto onmMJGOPOlIXjoqGZz6qpu/M1iGybBxUYASxVBAPbogxGq+qC4ITbkudC2wICFBW77qOYyF7G6d2 dKjvMRJU8v2HuNWKAYrtrFLJPpzCVd6yffSOv3ZzXBDQXj5briW9/vQEAAwoGgvrUb1X56ZFBLFn K5LO099HTTUVbdgC8l8c5eZGVdZpDHUNMGi6EJYRVTqQ1SVvk1eJa8M2LGesV/xMLhliwQU+2Toz Rz7ARCL/sja5+LTLXFA8u5BWPxZelVHE70bIfj88Ng8i6t8sQZsC9Vgjmp/VjX+lWlILYPnTiNjv gxAld512KtZqgUHzExDG+u5cvDFJyUIUFx1CyavAzuX3rm9zU5d+5lUAVeNi7DythVQGGmZMy9Uy RLOXO0Ka58TAoN2WufFs/ZXUkrDTUh86XchCzvLMV7tpum5G3kPclfgYTNqtPt+WriS887hX/9pJ oz4ZErpyeNA59ysZEsszE3Gesn2w9UyxXQeVbFgp7+YV6vVBymfGdjoATMUJlPfF7ydF9HZ00fJV f+u0DcjVh57osxTbpkFH4mpoUSn/WSPHD+XGJxmpzupdVlwfqwFKemc6XyIwczMTF6jln7/giGkz 0YRGftw/OCEfWmvtnZQ8OIhG/XUpKyokAnPa0blQoNgY2ppcoSIE6ie1JmMGAy/QEN7NN3LghGs1 zwIdDKjzJjqL6eDc/+imDlYfSn5aHqLxAVLR6HNzKExTUaK30BqZtJjRUe36hTSmmBfh4CFd5Af6 EmO9Loy+myB7ksmZIg2v4JaWD0xoJNiroFAt9i7N4PPvI3g8q0iYNWHUmmAy2lQ49FOzsTjmXl6w RSGxChASJUr8vaUrWVabkzxdctrmIrRe057N47PLFt6GvPwHbsV5FGo9uWI1XnsFjxKTCkfDuZtp s9RsCGQ7NywBa2/JYvO/4bN4Td/Us0xf7ihaZaCtMbFRjWS7Wt+6IjLk5DoDfed+5HaV2A8ax5jX /WJgon3QWaCJ9aglMObF793Qx2q0pxKQ4Kl492tkrh+Lv1c20Eg72gbNNb5ciPVqcbePSco9+IEw MVCp89rCg1ec/vdhOurSrUH7FsbOdxphOcBPyXIR+D/73D9BtZM5w3ooZlAANdI6P37vbSRQs5c1 B4a3mCA47D4setXN5h7br2XUs0nlaqu9wyDR3ZqAfwHP0kewJxTlhvtgorm7JmCxDbanI/ccDA5o 0XP28j+zURJy0g15L6Nkn1FqrMuvVlS6xqA1HDtuIxR0x2IbueGIhRaYyEZj/F5N2rL31XoesIpr nE49CHIVX+EBwoOVoStdAyUMWxjy+cy1/PsBTAhWfeDfh4OPoRYKzsh8gZIVtiH3yU9QMLd2ujIe PddS1dAKC75RCQYCr5tEKbcDby8afrzrzZcB12qmbhsmMFTKspQb/LHAtE21qigRl2PZF9zBa5bp 427bK9Lgi5dcq0fbwZJVYrpVX2/XNkE0U5VzG7u4xxOOozLPrYXBChOY6xgqhFyrCTB3mxnghqgo cYw91pJ1o8lF5t2eKZl37TYLVxObYnV1sbMlG+ghQYEY+b2/gtsftczvyeI/qVdJwSVox9GpHmsH Go6M9zkod3xPTASLx3giE/yiJls7JqEQH5PFEcDvGB+YcsxrP/VIAe2qoDQSGpqwgfJaodL0Pp52 GuUf7BkUEburuFwWSV5URnWD0DVPMwHGUeuB5YgbUsRrOrYyPVlE2EHyMqIwtUV3gQNCj9xfNIcS fPd/VwAmHZg7i7Y19lWzWI7nqLTNzlW3QrGj6WKT6a7OMFDTb4mjGt0LNeoK0GI5M0pus1aLe5+z Njx21lflLewsuQ+T93vxaHIjXwYD7vWRIkAUHlk6+eYDn0E3IDDIicDs+0Sv3G4OSc/4FT3JJnSu n8JNBgGd/TDg4mClXg8Tz5ZtUWi+ievggz3kN0/JEQkflKY0PTZz1cd9XZOGkgLHyKKW5n7q65Tu aLKSIPpYNtLOAGfrJ6FyHTOI7jy/lYdmZUW4Y54S4WpOVEXSOZXNd7l/dZlfc2VhVRh0fofRmiRK m6j1bN/T0U0QWe1U3ARkYNUKeuHSCw5XecNlhe3KxcsGXgA5ptL40PsGLpHMWGV8xbbCb9ccfqx4 VZ73Dqq5usYtLEUKCSprRgvzfsCWk4HPUijC2BYMOTGX4AgP+DUAFTvSB8hs/qiuAtlRO/BJSNkT 0WxMFB2E8DLk8cZMvx5bXJ5zzuoQBPv9Pdv5bvkX3NqcSyQpLjRkkdYFXdDRg6wg45vRhhmblTTB XYecDVVOOU6HHYQyS83x71ytKTdBKiNgn4ght1t9Vr9N559XnGXxxwhARabbkGoTidKHKrD30Y6l 64xsRV7KArCmff8SaHGo4oxhpFxnluPZy7EnBCaiLJsCpmMvIRjsUtPHDsh8v7iOgKB7AHrxZif0 hRCogLUru9+NaeZigDbxg+yRhfFoB0h0xi9ukc7wMvdHUBFDkf9oU8OGMsd1daPn2HXLCZ1IuQJa SawiJc3XRPCaj0OF0AydmC8pI/eqW0ROPpDURY074TtqYUtF+GPFqofNur92/1K2BMhwzUIQ766Q zM3QKBiyPFlLrtuXArrHlaZJDQ1GCM83Bchy8tVAZE6lsVQHvMa6h/9tUIlU9g4ZMhWsk2EGmmTJ O3GhAUOqWArirRHw71JAj22mckaYZObVuk9L6/wWKwHDtHIhiAd1SXFwTeK4NCq2fxtWnhl1oiVG ty0YeDcnDro4zmK0nhIq8LWGGixtb4thV53+hsZBdBiHEx6iKc8/5djk0tFoQGFLvAq1IBo55QNS VkDYfZHt+h2hWKcvgOFzZmNvIbZF8/pLky1Yho624pak2W6Zg9lbWVyqrfhxqAxQ3kyhuHr/+XbL ONng/eLXF4De5VigdOcLKxiwrREvC5SiQLZe+4pxkFJMItqjUVdi3z6YhyZ3RwFHC3qvPhwk1qw+ w4NMtBUwC774HUuXRfft97peLjV4clkNFEqhZloC0BpBiKLqtG/qd3/nfTvxbwit0rB6R1AC30Jg ewu1+CJXvoTTecvDJw9YBhs5HSxUti/gsTeU6XRS3ZB0AKF8NTYL88Z2ot9O7Uwkzg8sTXU4bYAj iDr3JcmlvTIHgWyxGApizQG7OPX5ZlcwH1yihATZ84ieNXJKvbGFcGuxSc3iH0DuqLJlK+EvJ1r5 9T+Nd3JuVSl89jb0y66+XRUKhsDT8nAuoK9RnbYa6gQeyUYt7MTBlvcrLUOaFsxmMAgtyH8pTDth BfIYwHunDqFrgmWsfqEwfHvNr42qvwVhJFqZVr3BBl7CjTHy2bLFgvNMlJ8vqsVVlqqKJhqPYM0o +qZ4hyMfV7cIhZOPAQzYl3HR46yVqOpYUmJAEXjDU4VdvBrhHNLZ2bhqK/K3jcFkTfl1KkAkwbpR R6qbf2Y8T1smB3BqwS8NocdAUPHGePsHcdzfTLWRfnGzjMD++/hBi5k8ug6Yg7vLqfNeunCTU72c LVsune+VlwI8vQGSBoHeiwqAn+gaKdgAndHGIO8oZJTEaSoXVomTP15rDcfmbJ26llTpWNL8cjVm sEChKwgE5PyZe9fiUhbK0KIX+QWAlS2ChAgiXyo2jGvDAnNcwc9B/uZfuTQjE/wseDNPsuvukbuX TFWqyO8debMRjJpjFQcXwa680nTw73SHfFxLtk716fNUaGSJ4Gkq4wNtoHp6bU3IJC377ws+OCd+ qQ4oji9ekJKmzqs5tN07MMIOtizFj2+NRk4CnYEfCeLW+kmqV5sWPaICKnhJt/5D9Gf2SNCJ/fK3 LjP5urLBkIgkolTsjOYRMSjoLxSInDmKiZ2ZFPD4ejONDIOiQOdhhZr/9PBHBY7IOMEHpRbhZ8ZD +sSEUYKhWaGkXaI93odHHD6jHar5Qe7OVZf/CCYP8ykWGccYgkeJrxtrcMuYL+RqZlLZuuCB6Ljf cjTzL9l7j52yalOB0QaMkYymzd5u+hIXUJXtbfm39lEi7n4CQQclHrd0WuefYmwTep7R7Xs2SkJO Atrt8AEuduP4qDfIMa1O5u/pokQxDyCl92c0+EBBB7Fw1pXrEnad0rdh1SkRxn3miXoEZXWgONyL PpfrJYHaEkNWS1T7w8xA36trCdRTsFSq/rA/iRAWk1vITQAyx9xQiV71ZTbAg8ntw8d7wzfBkPbF rRMdBumHLc2WHAdcPEqePArGnzoGu47DoniekD0/WzZv9/NKM5HkTbsaZYPUc84suhWVVJ3zpSfV JS4rjQIiQGQcSEQbVstNoBHuNfiPPK8cMbX/NXiu+AKJV3bu9R7P9dmG7ir8GVnvmqvfjNg8lGhE HYV2V+UZlapgqWj/CLa01p1AWKZXSAVQuACWjn6xFULdUXJ8F7/ZwjjVKCp5N5UbJnjEZADGH1mZ Fy7KRGJKUtisC2i4PF+fCdZ9hA9mC+IXr/VrDKGqHgB6nr9/D/NlFDuKppdKfrmq35PCfiIkuxIl CgiZhOO8IhxAxur7VEILq+MWXYBnZ58B3dBBaHwPFGLRDjPkY+LQA9Rtm6T2o+hkLoXowt3BLX4G QV05tGmWlWQ8G33ltzwnSkjht+lvHo4bO9hE7Hha/1F8/70O+Mxt2TG8tpjo83S428Zc0pFJwaB9 et6zH7JpmYAFWMA9jy7dkGzCV6BB5QcK3RzEYL9kB8Ec1jWKoqhrwqF8OYfg43YYOxRzRF37dUbC /5kD6DZeHzwZyrW7288awpo7dUdBv1ecYPkfcmq6Z4PIx7M60mFVEoMtrygbA8zasM8qyaA4Kxvs 7CgALcC1/Y0yEvyBTHhnZ0J4lZBJHa88dDEtep2G/eFuaxeM2KBzRJQqBe+k10BrEWihCzMW/prM BAaa13grzc/v3R38zREzZ9q1Ezt1WxxrCpqDpd4B7gPTuLhowCl89wo0basrggcdk7cL67ShQcfp 1dRe/fzisiPr+PVlYq6+wMZpO00RsIuDYHMbpZlNL8i5ugpEKlbcWMrZkFAiMYfIEoSUBLLtb5jj Kg/RL96pyaXyTwDtn0ZUYQ+tn8QW8RVyLm9EVgKVSxEANY4LXTNuFvnR4ppEEEURyvimVq1ynnBn nAJ8FRLi7aQyOVYsUqbbF62ppxp11XQVNnCNi0iNzN0ZM+nBGwupJI40W6klrQOYMPaQu4GRXNXx nI/tdr24UVOCBVTUcL3CK3HYWAJW0IMn8uXnnFeni1cYntZelEHd/tL0PcvOfdd4F8Q1dmtr1NXg d6gYsW4itF3D4bU4CFqVYZTTLER6UhwUH2XuVnG/b/ezEgu5aim+QKjXnWTNTDz8FsPH3rhXLDlq CWQJxea5j7CN7sutc18JeplTvKnjAFXr1N7qEubtpHydsPBSLifBDE1WSX+w+hITwWGm7SbghkW3 YYPvb/VdI49G2BKyz7HpH1jQpwv8ZaQbhR9Etaang+elIjqBdywb9PYzz5ya/UX8J+rogpq35YdR DuQCdBafd/ITzev5gZBhfjAtiMEwSSwPvZAW8xt5Hcw1E3S0Tec1mfm5DSFzTDI5Je4G19yZEHai 16uNjvrN+A0Dvz2xIBOPUFwR8Lhjka4KlGECeYXll8CZVXyFsrSQu2fTwc1EtVzuil5cKeryNDvD DDtzroo215xVpPSxC78Mgdk+u2iYEA/N7wQCiNxRLpQdb0ib7D0hiQKRkfmpOdgOroscm5nbZqWG RjshSMLcbPZbSzU9hoo9WCTr3EaqJ4wXuJhmdjxCDet7F0kYlNeH+di3HYmNEU2TYA74/CtcXBIw sYrF+kAFdV9HcV+O1Mo0/JJJeBoZYlNbOxSoBnBj3wekPeixjCwt5XYH7JouqT5hR2opLW1T3/lU X0duslGOHqo592zKYQG4QLq/13N+4PjH12zrrcAZZmPvQw1Kfp81w2esG4rI5LFxssk7Zh+I8K/H XrKKPy4uBu971xpLmRoa7Fl0VmWappV0yLFdwbsyThhsifc+JYoJDRDfHODOXNqiW6MHTNG96nTe D4wBdJJQztmLxI8w5QejTwApT/Hiz+1+kCcymnqLN+7g0vE0ip1JY4T6OCkYvuTsimYwxwsP7Jxk frPIh8sJr69nrOIx8yjmmkTTpflptT+Huakp8Y9ESI57sCNS3zwqHt3caP8h0/gi8ov90tJAkfaE nZkL/J+CBrG2qegt5ub9gOnh2idXbPBbSRSqQFDY2E62ZsceQzIJWF7wP8DtZVLRAx4yffuZWeT/ lqfUM9EZg+vnxF1hxJUIKtVrvUwrKQ0oOgWPVwST0t6LlA13m+jmyRXFwqbQJNQXhpEzootLGNDG 23loWlsMy2g0Al2imdrQM4Vc2TLPOPwHiaGMA2a4VJlTiA2KuJ63qfh/FR17VOrRLpl1urwlAoWG CoYltSN0ozWhZE6bb/9lI7uliXFrZObBJzlDd5f3FP++kivfn/GjPFW34Z+KLPD515gnQMZTqWBe zem7y/lSgI0imG4c/sJjZoCkcrrMtq+RxwA7tZJLJSITpS67SvL7pN5caPs0x1t/b0FkeDEFq10c EgQC1rBW9Oy0LCLFIurbQ8YOmyUxSdT7iBGS7F4uf52i/BS8AdNJoGOsCWSoYFite1NSl3+ZEjd9 vGNKoLWBLfzPyt3O0c1eBfEJhhT7Db4j4Xmr/hPJlej2mFqy9j5ZcQ/TQHYXmMN+Y3lBDmWgGBNh sCjKRfXjTF6WaU2smy3SbrXsmEeftdOY0fey2kbZ2KTx6JNYXeB5SOQVXlya2BFqhg/gfCxzmBvk enudwKRE+dRjF9GSb31xPymydVh/+93sXe6wNMxPZlcweQWxt2cRWvtFqqGd522T9Qq1M9RWdTgB p8ozV5KjEl/J9DFBYod9zSyCOlAhHVAi+1XW8bzI97EqHSKIgI2DBc9uFKez4NL335fKNKafa5E9 BZ+yzlH9/tBe07UfX78xsmN8YkZ8eFP6eFY54x0pAA51egMW+8Qe0vkjoBSN/L6CvhiT+7xm14pB PjGPqGrMd81PNpJXeAgPZ2U9ukP1Ea2PYg+X/8x32512S7tqBVyHUD9kFmHT0jC7gPi6X2+6uGbk 9vzJLuy7kdqJkmGfHQ70VOzOpeZec7Ytn+JfLJJ3J+e30+julJUpfQunXXYPaQMVxYPq94RCtIcd HjimGr2f+h7Objl07fQ+RY9Dp6wL/A5u8uY9nnASyiNs0Z9xA/4VZU/g3b62hqwq7lxbHmvyyVNM TY8rINJ4MQC2rGG0Aj2zSmn0CAivZguyPwn45L+kkk7FO7uLoDP20mlEcvC7LED0k15+COV4rDzj FGFkM4gvkSWQcBgysEIp+lPL5sIk9eWkC51C97O4N/3cHyzyBgUu+5U5hqQsXJIN5dPpouUAwV+k nSfHnrtqXl/XWYySTCcA1xnqsCKdMrpVyzaEZIumlZjHpWmmkFlg7nj6lY8ShrwiVMLEsHOawODO YlvXUO/xHtKlHia+X0n1ZAw/1CzAS3+gNyCeWyDzgKhr06+nsFxqmOi1ioOdSh5Cj9w2EuyyCTgs 8q0XASW/wTbRVBWtpNtV0w0AgCWM2Czufys+uI5T9Fm88pX156Mplr7EUUPpjDYFRvEBo+uHUjHW lYnk84KcmMQaieMcXr72gzeBIg4HLdrfG6iGZhM2fy8Fj6r2oapsWat1y0yW9mi6NUeBA+Gh/JOp on+ZDmHgdfTW75wYLjyT5IPsyJNbyqoHk3O+x4iIrSwFOFjgr8+Umgw95kAOhsL3Kgmo+1M47lTu Do75wvyTtNPUlKxPqPRDtCtL+HiNipZfdXlbKwsndHV4t67uB+35AV5hSON0Ezc8wP42v1R8f5sW Da+QM70ukqd2GT9pNBLxp3mnpvbtGswuV7uhWJXfL3L6CpIe7cttNMScPRLf3q77PK6HPWYCDEL7 z509NgQr0ojk9kw9A44m6EKPpm42Ecf3KipMbFB4PNHsXCIM4YtClzSE1b4dlJZD+rJvjVnR7ahj k1IrSU6IOBlcUvOtK6JnCqVtcCAQdNcb7kW2C3Xe17dkfgXug2R7CSAdCwqzFrPnfTYIS8uJrobY S9ur/YTsqTdeQGNRLWdfB+vZvPgp/Qzmi2rOcWwxqg378559E4M/lGti446Yttn823g2s4lJDMQa FMPZX8eJ4RPwweUWY8ljA3ZfYVeeOgRc8JkBWjuuZwd9i9QZlJWbQQROkSh8ZyAk9qgwnGFpHB8j VpgViKNIVqIF1PowCE2dNKWDuAR9nhyIVR6mFWSGMZHbt5eEXugCVplwTvcHTIkbe0BOgqUuZjmF fqdVdH3gdOYCqZnqigmkvAY28/+CUPKlhBGzjSNLYOsretXbR5LnQ6o9qVNf95MYBHWLYg9Ko8Sr 44YODC/apcouJOiXqkHA/6gc0DOs1YeNomcvHdE9/v4zVMAwQ8BULQL+2KFaLjkVG8/eTtTyooqc mX67uU+Uu6V8vcGT25AgSAyCdud/rSU6PdEs7QOSaDcSZQaX42nzP9O6a2FHmTFaTv6dCSCoZsVi dxIYiHxWuV3vlyMYrCo/t16yazDd/klWmyDSuDrhhO5oUNEc8VRl0G8PYNyy+eNgkqv2BaZM98Ou Edokq0O+5rzI7DhVT+dxHLgJLwwarVgWP3O4mg8ayyPNbCLBbrto3E1kYExfd2LA+cQ6hh4pjFH3 VuUPbMc3toUAM7jU1t9b/KqyQZ680pI8s9PdHuQJwJFld/RCFSsORLmf8qJ7KL7an/dS7U94WgFr KhCo1pgViOeZMCyuTtclpK+b8HWrLT1VsJXpz+gFCBmkTD9gxVvmpchso1uc7R39IYPXX7inJzx4 Y4N4t7uCQ5kBmCPRGQAhAfcRblxqWlAyJwhUtxB/eqXox0R1/JthofmouAjKR/Vt6WYKzGQWGkf1 DxlFy6Id43Ay3pboD/k5jfsFeVLqV2LNuW2IE7Z8QQIsQN/5MIwbSgAa12sMdilD3wHvqNZJixDZ +6YvqkSUUTw6OVPOVBkQPqtAD5f/leGfX4zFMFg/qnyjMXvBbmYsL1515jyvrGjQWwLQNAF2Voep xNHkvFADx/eJE+DfhJGKjJK4/hd7V2vO28jTmq4z2JIjmcp/lS41dDhoweuJUJuERDIXH3Fh6mSU F3kjAlhR+/yOjTmpGucVzWUVjTXsh3iDaWau+u1cMKUvHaBCagpq+d2cHSCoB4Y292XnP+NSXxZj fxoXbC+lzEqHK5nNN6E3Yu/8XTP6sbZ6qbcvCWCgudXFoFukAH3jLjGkR0n+zkRS2D9o330ba2TS s+OLTd+o9E4rsWeB0rbTLacbHbQd86jDuBDpCCcQe077eymRWO5LIRKWsuaXtY010+TdgF9ENFRj LiUBSVjTjvC3J06RVPcfYTvzuftvo7Fwfc8PaRlyy7iYXlACAirB91tJsroGMc9+rP40IMiOcht2 6WiGRbKSw6NQoCFr3HP8pz7vkK/X5aYtu3orkpxj7rT+OSHGkuYaltfCnZZX+gx68p5kaepEOv+2 /tbP7+hEPQjXCfPhHWgC93w1ppVZTLWVsC9Xaa+cFS+Zn1QLANL5YymjvgtR8PUDzvnIifecM+N4 6O5KT9wIW+S/C/zSEB/3262DsaZaUKlxVr0HrkLLfa9Ytrh4FMbhbRrTUbt3UYCnOeXe3h+AwoeR rwkIbjPRQ4GRZaxFlXHeaRJSaaICEPoCmmamGWYUlVXhKk4Snc/28seJeAHAPWUDcbSNP11tGM6x USg4tWC1yne1Jd29OJkqIMBLUlpa0vClcG1jFjksPal6JgKK8TuDmUfWHA2pnlhunS4VFkPd4643 WOPS82eIasxIQ8g9wPio3Q/kzMSzUqh7BXHpttqX97nzy2c2F2WErxsX/Ip0mRBB/bizwr996qm6 HIk3VS5XcgeF3gi9DqMaKz4TpideGvxdxe0h+iguZMnKnBvVgSoG8hTQ9W5GbflkZ9GkiPx5//Uq 13XPzEj4K8WuY/IsfvAallxUyWiJprMF3vHzIXWaIfV+0WtG1qVFfmeAYzxitmVaWaIWbIiID9im qag8BWGzRJcyrNQHI69mCJJlnhtBnTkKKWDrN1ccTTaKu9rx7xen0pcxHMLR8pAxMprSiW+22NrJ TvWgPGBYr9UwXf1NB8s/DJ435ZooS0SwicjybVPNI0cpQ7OL3Gj6A1Zp3UTGs9eXwvrtPmeXEIeS 9ggjkIu6x693HsP0WShhz7UsMnIo7Buz5q6QcR1RLXGTCYWKXta3pS8cBDXYPKuFEzFObzva93gs j6J1vKnNzWiV8iGG5eyo4UGcYrP7eed6QAHX7Yw+6ttYqRJt+0TLDHRpuC60p3O5ePo/ekGuDVyG hItMSZuaPU9pLiBY6zS3jt4moYHoNb1pKQHk4S3feTaD3v+bi8wMQvVk/ONKscr3z/zS0VtIjsOR d6Dhcf2arPJSXdWBk5O3Se7ulG0l66S/jt8+Nl1g2w5L1ZAxsd0wvKcNO1pexCUM14/xZHF11t/U 4i/KYDyTmD2KWxmXTFhdni/HwC8qYDMw+WssfjpEdXP+cJczMDuHkQoiwJF8R3SdU2hV8wU5jM5c /ixvgOcxqZDMjpn5bhmRACXQpe9GAq8kceIh62n2pjpvSUIxXq0tlH9bORqarNOIGFXOp3uG1c+9 GGkbQWgHZDpqkM16RYR0nH14I7uXc7m175Zi0XLdAy61Gwg/SzugMl6aozcsyNy16QAnNT51wVtj V64QN1sCkpAOer3qSM167kgCULqGrhHCKD4b0U0ckc0h4m4lhYXsOjF2k0jCRfwctE+LlWkxAZpN 7lTPU48/1642DRlnbOh5+c+mAi6K8T7Zd4faltUtPGvCeU5vEgwNi4i2CkTpKiYm3X9vY9V1SsDE JNPEouQNPaACWx3LvV3I+tn0zJMoIDvYRlaNzlXJIkzQmHicMFDtdxe198R38B/mVYpaaCz1gKAy yAl0Hmn23xjyIXbcqZ/BcBo4CuMsGm3XlfTkNoaqowlZFBnzZTVao7dFcgK6Z0V8a8gQTNTGrsPy gotaWzCShbQToI5DZc7CAQpl2moxOv52dgf8LPyO/ivfdfPRCy8AfBORXOBAKTMDNXNMoAPn/LAy LjOEiqj1Kk4gRbond4byJajW0Lh4RoglpDvQ1bBAdXpfOUOqF0U6oNV3E27xMsW2pFESh6N6oyw8 XWpSz3yHHRnWXnHhnLAw798dBZCK+vB1rG1DCuu0X94Sbjv0Nj933c++H8dmEdwFmNTWf10ApEW5 cPEBnM1Rcg2aS/2YLKsOY8R38Omt5T8Ff+OEPmTOhh9F5Xw07Ysx6V6G7amjKhV14JsAD3wwaOiS gnHbv9es35KdH3YirE84/dEajcs46rvt/ZqJUgZWn6veoK8ioD8+Qz3l7yZM3OnJlYPJv3OcsMaz B6QW8sPKvjuxauc8CTEsLoZjrYbfEGFv+OhFDYtmKr75reds3+I8GyMHiG7KM7rjUsT6OOecq71C K6bR2K6AZNoFjuBfBXWVSZWXJbobGQtpomRz4/9iELHPqL0VyuAMfsNr0QMyYBJ1SxrQa8GqLdE+ Eripbq4ZbY1FO4ItwMs6zLwRg41hlXaCe9/7E6Qw7aT1WdzaH5FBwS/Qts4Yvno6igvgISNo5nzm LUGKotCuVwDuqyxS0c7zlN2JPG7lR9Bsg+XB83R2aDEhQym6GABLdOzNYDtwvcyVdMJ1Ko8KzhKF 50oB+PJhUz75BauAD0aahAAoYZd3DdNTIRsBFAp/F8Hn9r2vNAPRNar8lEMGTYhdeuSvAQTLetaA 79REFot1c/ikwoQScl8QANUfR5SK+8H8Qqd+Sp9TxgwQweX78hdL3YBFomG+j8nEAkFE/2XXbGJD BcbNCshiN0yEsE5Ebfax3lbdn6jB4eGfdsSfpW9SP25covyEvaWMb/nKOO3OKABsZyl90hEdgG+Q 0A1blQm6E9n1kpripgX87Ynvf75ND1t3kNrelCgDLj2ihFHw5BxWKaL5pR0uT5uhE1q5FvCN22Fi lD3wcA0Bm8NDBrAPNTncu9xikv1HT3adoRAeJkYf9HjXzUrsV4mwqw/g22eFw10ZBh3gW/oBh9Y1 Avlt6+d74318pvXIMebYnrDIsGDXQ7PBtXqTz9jFBGDuocfQlEgJwCP6CYc8DYSjEW5PwQ3b7KCO CSmKKmw6SsTakTjVHL2CV303/vwMPsiZ99FjIXzYM1zvSuHYMt5pmWftQjP0BvAg87Q6SFVwSGc6 hbUnctnYILcifEt044Zd6lm8v+Y/gg9tdtOzv/fFa/O3Rll7kDQ9BroHCj6Qln21I8+S4Rsx0oGv jhV4HjtQGrDoq0cf/KxWjnh9blXcW7rAUXiJ/MahVq7VGWakfj6oDgAvT4J22sZ6mXXkGCeStk0w isNQQ93P38201NuCZk3ha7Awe4Zu2keBm+K43Io+x9+yject7G0IwMQKO40KDiyjmixpSODYambf L5uGKIOxzLW8MH12M//wnThw5nzFy7vNfIiCzyqbFjML2y28z5ShVC2ZkUqjxtjTW2JFymd6ix+U Va2Dz6F4my/7xjQAr/bE6IUQn44nA++owGd95AH3XYwfGCaRSBi+Mm2v+alhLXTi+o7sF3YxO9vU JQbBFmdekFsgNQAfvinvs/u2tLCTzcy9GHPiySu9ngvb1yzCsCOPS10M8phaKCuAFYE3UsOCrp4w CHGrIxd58cRUgXrkDZ79cDIb6W2J5a25uQsaYmH+IFCbKWgi1szvYNroAZiey17hqsT7s8pd+4yF e57B9oIzu62Xbw673lj0YikDwAsrjhSQwpOyx5S7yC3BZVliJv2l7RtE2dMwqN206gBDAB3Qb+m9 VWmue4jW91LWPBW+hB1IcXM1GvxWUcdLVgTbuBevfyfaj8fe63hM4SG0xbuRTPomQ0WaMDNkdoHA IEvZbth6K8tf9PCgWEB1d+JkvMCdDxXJj2F2rEswkaI7/QLslLQs9EJVhDV33aOiiqeJ2nn64w30 YvLv3n1GDSjOpqmVQLn2btZkxJfVvX5abhwmyHRYjtoaMYNUd0g4AH52ywLS+0sDheK773yIb0Kk Wkj9BknZ4A/eAR2Kon6K55eAilHKFeBDfilrzizG9uKgTM4BV6k0Su/DRj5cCI8NwewtNQB1SgJY 7xIE116oqTA9hgoEHAaJ+UAARLyKY53GS2sk+kiPJqMb1d3AmmU0qQiozXG0hjso4jgkXqgEf29V puVbvz/vbCqqfb/nRUIvSCkhAjxYWMNJcPp1VZujY9tl6EJk2nxGDlwh4TsiFr4ErUT1j/y566ls uKB7g/xsr00+fG8B7+Pt1+MEdnbfzDTOJtohH25ZSsF/XwiWf6O7AbGUUAJmGx2Ltr8mb4o3QUwU WljsBT5d2NFT0dFd3A9BkWRzGPY6XsOv33tM5RRB2s9dviFq+obgEO9qs+Fuv9l4U9cvKcZ/16pX 5XuWANKDD25MHpGpGtObgh5WWAC61AS9RXuXLCAiLKHx3X2iE3JXDHrfL1ACK3Lf/8ZCnqnF0ShL 85Mg3qeuE1iIMWpYjTfqnF40zdFF4N7e22ybIXVZ8RIfif80NwDCFAvPA6xngtSnkDoanP4A/0G8 xn47CzPecoiHSC5HHIb8Dy82vGn2yQfsOQe6xYf/sAxsRPWt8sz7BKIGCv3ysrrQPm4uFDQuyCBH oTi+l4y/IXslruqkRvOcPkCUzpBHH0wy8N0wSxVKRaF6qGohzt4W4hewFdjgsmn0xf8k4VK97/23 e9KQBfVK4UbQGbQBwP2LUzVclV6F/HNG8BWcBp6nlh1iBwMa/5oGVU4CocEVgl9/HKWgQczdgrnz 8KWSHQLq6U4JEpl183tHYg2LGu58jzzzw5fgVVKCj5wi9RkMjdy/o5b/95sHwG4z0Ww6TfrR2LOH HTLDI0IQ/xwDSf+l+7Mb9v8uzDFaRYwzppostwuwRFVWQa7HA7fUGX4maIdXj+rmv2ijX3vCPvPr Uq4sYBuj+s0Tw1CbbV3fLIJ61yw4527eoXX0Syr7EnBvpqRYpbkjtji+04XI+cQ9VFFYAI2nySmE TrmeOe8VffrIXjX6kBB7d9JnLmX0gbaPPFoqpEX9PYdEzJnG8ncfjzioFtXbzerHUucjz78ibwbt ROeosKcJO9hYovz6Z+8xKuXA0onCeVrx7UrJa6SOQFLgp4BqD8O94XDxC0t+u6sQZWmQiVLKc5Fb YEElTOgzGgXgw807v0rslrfblJvQ7CJR6HyLceCca/6s2IEYy0dssJR5kmP19C/GQoCypxFt0wuG QDMM0dPZci9TfMfmtGdFzoGu+A3z/6LGdfIDjE/Af+2UcF3CBCGzukn9OWyL9SZrXWHTlFE0ReX9 RDwWR6tI3iimaiEPdvwm8eY5XeR4E19u4JfVc8rYTj3cZHHA2Sa+Y5y4lnAOYmgcnyjPOGaldEFX u++qfX9NC4k/gu52wXSweS8QxkEapUZUMlelOgxt3fedTjka5PkU56glnBHPq74YCpmVHCKslE9t 9WP9mFgJ3ZN7TkiVNRzVT/hCBH++QO/Kw/JToNvZAhcsyTYcuxBJmkO/Vkw1XVG3NiVMf+v0d5zI CulzFnpfzRwM8xwhGnh43MK/NV2tusY5eYXkr8vAnang6tl/skwwW4wdcjYPWQps39etOnb+GL3l M52Ha/6aFEw50tbX1Op022TnAuKm18SJSHMmDF7MJceoHKPSd4kuqkzUo7ss97FNUyZA383u5bHh kTczjd7RZDDDdaz53q4GGHOe6jpz1HArxaSTxtEqbdYbjvHrT+6LiUi3Czr4h9mckHeOHdgyYkXG j48yqF48ZKchEoISZclVbDZ8YPFUBry5ndhmV+ydRywGXi41sVbtj8V0lerV5XA38I98i0Rf9DFG AB/PtN7GQ+h/iyFW3TA+eNV4X8Vl9L20321mg1vEYVUJCkORpLWfzrX4q3wJYst9w/GLepI4LJxz nH6+TPe9MJGRm/izNpygvauFghAUrCLhmdekq2BJE4cCXB7BySfr5OvSw9M7NrMaBpgXZFZrZycA 1s/rA1WdF/g4C9bihiv3k4tFU3eMaIbPaSgMg58UGeWf23qXcVPWFY98jJcalPyLRh434lnzDSr+ pQfRAKulS5Fdcb5vZwV0Sje4VKuwaTF0aHvPxhX0D/Yxi4AIWJgCU01HparQ2002ahMbQWJ2sGxs /jOJHSWzj25EKK7Oa3WtMRAstGyWsPq51BJoMNMa46JR+8OAsaUCwgCAO/6RqGvwchB/UlSEvw8Q rwrpOMvMI3HiSc5OM3h5vIn/ERNVMgnteuuO/ORoA7/Dlw0JQpECMhEJNyn/nqXrEHXtfEN1CrLw rqpEQE8dU4mKQSU9TBSDx0bSsiZg3+zrGuaiRZCaphsaTWcEUUiw5QyGXVpPrnYZ2mMwp2M/u6Zf 5JByqUg7Vn9M15rvmNQ+H0T5/gSV+Fp0z7jRdBG+jVsHEvzy2s4utee9LMNaKNLSzgfVuJ/eXc7j ADa2u5XeLYrsrxmn0V1Nx/RDHVgwD62r3689PSlcEaOy8zIO5FHpFciP0uED1ZHhoMQ2jHuwS0bR G81n50Q/xJhE9oVWWh1VVqvlaXC4SQ08kMjRHu2gc7PxkTGkf1YExHs2pR+NpMZ5vrSHwNEYY/Ke /ahcMCCa/Atotp0Rty/fCrnrcyiJEZy19gOyRt79NVtP4Cw/m3cRmxiWsUZuaVKsfj1BUUkPgQ6j 56LN9u8ImmOUG8kh0DT8tuOvdLaP3QRtEKZ06AuV/A2zARXpWfP1GmhSkua755cAJX1F2hZn2ZnO DKv8w0Q7unNxWgGHvw/mGXWvujIIE6sDVEnzWDvgCeg3jtW6XCVyBjCkNLrGQgkHqF1Tw3Q4U2I4 R+fvcFYnMnm34qg7RSKkW6WEB6bk/I6/mf1YqIdxoHAUce0BjdcBMAGSbFp0CZAjMlkoX64Wpbzx KXAfYZR53bzj0xfiScwlggnUwiEqkKuIYmqqCC2asr4ySmUu+Auew1tzlDHTImLts+v3HqFBKayg W7NBHR8ypaCkBRfL78vX0RMW2PwTxQOIV5izOFSFpTfWx2NsUQRkRi2MkP4LcxjlcoPQz8YxS8Bb BHFs5ZBw6zO1rTKchQfQ4G3l6CU9fGRy+PeZlQIlYsR9JTnDUgweaYuB8XY5sbc81F9trDxOiiWR G5ip+aK9MBh8Ieh+jmmJKuvjUVpsNDO5+i6aB/4++iPW+yuX+Ws9buucz2zYw1EE9zJJeFhYhIbu aLw0yB4DN4FkyR9lR+MqW/lNsMJFvqzIl1KnNfQhiUX6T+v+lOexNUoH65bQ1BDxdzDtr4IzZg4S m9Ua51cjweFn3U+7alkR3v7RNAXNGoZYjvoxMGVRER0GQ3nitKprcLKZ3hkG3/2UuMIyOsJQwNID 6j+Q0CWApTqFtRA2zueCFmq7dW5gJCmHyCGqitZCcSdH9KyKugJrkzNi5sNja3os6KUCErlX/W3A Pzj/6qxbOEnuTCXY5NJqp4tjxZL++zfQ5PCQWUUP6yLS5JBo77SU6HTVCvVb3+oUY9xLeVv+JKD/ ENIgYUq0bbYbHEiqVWM655i4P8agto5Rd39Wc12q5Kg1qx41EJLzBqGmKn4vwOOu5dNporK3gHoa j2Lcj/e2Yra0Vk5h+dUIyikDfWLUMYcFLROM4zGj02N+fTa+RlGAXcaJAWb+oVanSqnGCo+JTljW 03w+4CA/va5FlBdkfLKkti8lCZD/sIHsWk1vjnJvVIpsxSxl6sNoaPT5e2LldOddgUnIWOCPPQG8 YEcxMxIasK+y6jYVc/burKncR0wq91Tzc0lwiZE7nr4cRZQwEG8But/AEkELayQdVAdlDgpIe4Yz SP1EzMD7q/O2yaLzsw0KJ8PwYcuF8jw4USH8vLTS3lNR3QL/wQS0yW0kb75CbZhWEqhUC/MlRjMF /pOVlDYsxgD8Jj6z/GxvRzS2ov1sWZmhs2s4XRuGe1Dprk4qZ0WlpOdTdO20xcIgFvdcmSUtvyVr urdaV9tt84QYCB28ZVdNwJGDF4mPWAn1NB8hwCqwSFizHucsn7QDScppH+6xF/7LsD6gRmU6DAcH Yri8CbWSEabKBN3mlhZ8uv1xE7SBIsdQzFd/mpU2jUzOYUwB4IhHsglOa6Krh0rJxpyhXjwhWz3I dzu4ehsXN2Vw5g5YqBsRda8eucQZDOCzkc19W+1lc63T0b8m0NxcvB3F0kVWnxjbl+vrleUtDG9/ dbSYrk5vyMBPOywynPlAmIizsr4JzziZ1k1jRZKIJZBWXAg5eq/aH+kdGdDOmG2i47xZMivxPxWB NZCpsqIqy+H6e+FRu1j8Kbu3unpuskd6H1s3IXHF9iZmRyZ3P94sX1m7Cwu7Idkp8czTbWj4NJsF UuSLSGTCfLSDJj+O5mdlRYwgfDirFu74KFoO1xZBxMhynJSg9dSKCatLrfd+NIHmyzNWeSP071uA V3zujN+EEj3mGyOvkerUMPd6JeQzhBS+EudJTVPU8AQWnpxAXQo1x2QEaNwBmvB+K4oIbZ5LYxbX lhkaDayLf7Il+9ay/lAUqaJoYk0dvkQLA+eFf0fP1cYoC5UWnZ1khE5ouEYn5uon1oNWGEqKWf+X eDD1NUOSnksU8taWSxjwbuN1vXU/xxTYAoUhnuP2vbswcCQLYpYC/8lsZy/yEd43r1+cbRbt617m WAmauE1I7gCQyEEe4tbp0py+q1Q1eJQ90N9n7lZxyCn9D7Nj7k6WdOBcgX69Tb9m1fmEWQM2Rcg1 L4BiSMmMF+BWjyZTaSNY5vEgquZQ48z69fnuf7aMHGZjZuONsinSIbzI7D9NvfgNR2VM35O+Rhpr 1C5GkTVABZa+BcPyrYIF237nvoPq0sEQlCukfL0pzEDmnV99EFQ+JOOpLcVmmchjkAc6nnxYic4X LW6PeY1MaNS+3OwA+xKHcOqDe6670XbDPJPha330K3ZjARShUtFJrWhi+7QL5l2JCJcSJAC5BXFG JW95hWYELLJQ6tydScMxAzpALLn1egNAcdvEIf9PMeE0iZRlB9IhuirHbjkdWdSDRcMSagBf+QRd OVZrnl7AYW8VM2/GEch3ND7Ygk9arJGmp2eRyy9hpG0NLc71WDEjF071pp3NdzVysQsuGhYgkJTm eXMHZ1wNlLR7fyb6gSlbBNbGvtOBYeJzS1kfWkNNZKSMGJbbVdE8XZP1dNtdHku6NsitSXFWAUoQ Tj8XzV1EEIESqMnaBXTK+69bn13Sr7XhhNcKeDcWZwjrjRmUsJ0RRfyyrdjscPrA5HcSaqCjpHIy mVvcHSFuDaoUYz6AIhQ0JGlcD9EclO2Q5Gnx+UZ+Ss8qUDdvf9o475V9YDJtVWCK+05hshGWsYaz ZY7r0yu1gDs+KS9HSl0VQJaeCxQwvUW18AhzXTxCMKrmGWe5xhGJw1y/qxPT6xgUx29g9EpGR0T6 5+HpfiC2bWilJSDNA6ZC7MaBXfPSQYs9yGIp1khJYR2Y6AniYqw8gjYCV3WeME5IKcVf14tJbnUr dUYI+9INlz6Cjpc6EeZYyOUF4V8fBGLJsnhTTi+/kMm5bquuzSPagOps664X5ibI8e0hhG9ioO9A /8NKInC72LhHJwJR3uzefSDLOl7Dg9AcB7HYjWFfEMHjRfJ8hXe5L/Ro71gMeXcod73/xDx6XBXQ pVG7p00WQnkKvfuXIDz5fDdfo1lmnSD3OfPDcqJ9Zx7CvBhomRLS0DsqtyA27fHFbjz/nze+JnaF oWNFUNZtZrckOFdyOSIo5c8RGK6lBt0NRfFCgMsweXhObAeAdVDTYnEmyrf5p2Izr/Gxcagm0dOZ IKMa07W5NKIEur9wamaIAEubgZNASLIvo+p5SuMcEAmodkerty9jUZuGhKbiWIYjS80BmS27QS9z jrHqOHIF5aPgjj/luBao86GQRxcBnF7CWwZPKdA0MDjbgHIuWyLS3tnvNkbW663wkm9ie/lBg+X9 l0Pbtp6Zxtg/U8CFcMc8hqI2y6hV3ou9qHaemym5Z9RwLGKU6qETFCq2hEYrQRt7Ftbef0MxQZQt ukwt7+VGn3OhTBDBTxmdcc+XvaF84OUdWee40ZwreOW0Ld/05RDeql6blwq9P4RNFnBjn8lT/ihv 9uHU07wJA+h2rC5IgTmrlr7n5/Ow5p8kt0iYdzEJvNZ7oS7JLpTwXzbjK2kdNzPMRL3+kWtLiOqT t/YtvJw36523wR8KgHj1zSsAzxMl4VIxt01drDtxjy1ScZ0c6VfpTGopo9dx+sRWzLPToXjFeHkI /lw6qLgud+FKeTJfH17IcQVtEzgVDGeqmYdUtVfpVwgPOZRriP2/cKCQgXNutWehzQg+XS6p9Spf WDD/vBZDgurQ1UDsfQ/2EKRCfELM4sZpjD6ilMShWamJDDLUScnWI/IDeYFHWPwH0bpHoaubO3hJ ckB6YRIP3OkmkF0jTjppfYTUrFKr+s6GL0NPSwmgdj9jemVGUfvEZaAdi0W1eCmRPV8F1sFpnbU4 FSxpMxp3asf34T1GbGMhitEWvjNN6MaWE6FQfB3+FaRkP/k+ywgVGbeOLSR8ba5xyYdTXixkGWED 5GZFzPIl4J5QTaDV9EMtU+3SUbF63zYQG5l4Fpf5MSIG6K4iHXfsJCSAIOIVSZgNxZAyBmfCgzGO 2acchpmqdt+9FsNvF/gRjVOtRQI6mhAI8k9wCUtIAXP2MP499EpMPI2+QXiOA5CEqfCGYbM71ldW UxXEHC2SI6A9dYtvQHLDjStg2JdLtmRzSknGl+v6nV3sOdkkRAnlgHdUmAUXfeSkI0c4Qjlo0LhY +KU83nt/TRFXkTaUCIqEgfgbRFD8MANqTnBW9yl244J9V0C1on2BRGpvQ3kg9D8GtoufR7bhECBY jEi/HuwJsLWKgnRMGjAixRJR/DgKCE1NwDRm17XCUQqT98JP33qzXIhjrNZBh+fcUEOIiZ48Cww6 YS+Kp34xBcHNtD6YEKV0hJG7qlCknixO/dACI9yjFSnuIqAin1MFYkHKchSvFjBLet6pYtj2f87C agYl0BBjoVomGKgKtjmDTzEQ4phwa+htxr+kKQT0SZe7fgmaT9RVU1ZPoZjpXdclzO71DtznnX3u cWopsJ6afm5xaagsXpKfmVc2MStMsh4rrqZG5j2rsfW6cuYya4ChkEShHy1dNi4VDXH8PAyoidmk cZVqgMri3mr4aL1X5M9ZkjuBfJr3GCZnfFRN8W8f0EftUieoz/VR+V5F6iRRseE8dHqqL1v8Lek1 ckPkabbXORP5H09uLiTBSn/Ac6RyUfIO3dFUiyK1VeHpM/OXC04VkqbCIUR1MVa3U8TrKYJ5tDe4 4mF3Olr30WBu0nAIUDPOZrGGo610ZgpiOmSe3GShE7X4acBUGeU3eS7sThxkA3f1hPMlGON5tZMp vG8wABxQzcGw6PdMjunGAryAIE1tkTuGUtkz8NvUtl+PAsj9YPBIGLv9XU48ARQOcQo2cNEOrAMv dVcPlH0zpUfo4mEt7avjgNA79sDftqkAkK7N1OWAVBC+a39XE5XglMjENczYAcl+O/QZwm80UaJV SPCtVl8c3ZITIZNryGMuL0Lpn1RjQFrPzpi2e/bxJj33+mbuISwC7cmFAFeTolG7NuNADL87WZDw s6dMC5pX6z4Tlo160tAPIfNO0o+ls0Hzjx1JiKIr43ScveY2lENC2+NirR4QgEcJ35XgGNGjLpYb pdrpoXKQ7TONLu/Zinaz5UF4cKynrqc36Zzo+BwNLc6adUoHeOoARkfzafeBQtCE+/ncSaVpKbQh 3VZrekcupyS1FldF/7Jb0SB+VX6Tg6jYNo4XscHIq2qrWpJHUkj2jqYrpe9wJQLquW/+Fz0hCM37 vILmJaDwLyqOYrICoheox+/GKBMNykuUgGusK00JRZ7tdDzGdRvDNSJKk5Mi9vpzJugwABQby3Xz BtvrWLUpJsfwukKIIRUxVxeVkJG7FRQEr8Vt03lLb9CjhxpFRk+ps5cid6URx2avtxRcd3/ky7E6 oUfIgC0NiISniNVNsxdQhBliDDSbAGKc+GR9ck4CJgDj59JyBpIY94hpKPWzXGgIChYWC/hjuFz8 eG4DVomHZ9P6Tz4cpwEt82HG8MvMEOFVj/uPG6bZPu1lfS9WMIMXhnb9OiZvvhyio3VRQaqHnN2U 9zedV1WQ7rwSceXs4441UB8liIqEmYwFTWs3IFwaPXRhMVZh7e7TouElacq0rv6PnbE90j+jMaLF rvsVwbjp0TJ4sL3X1JokZvn637AEfj++ybOBnHQFo37ig4tzel+psE+aRSf8FmB+nPrVXxbVqTpr 9w+YSfsvrdOGX0egG6556bdBFEspMXjlO/RUQL8UjAJpcWZ2cVWjtr04INiBLrgQORSZbMSjsQ8w nU/s4xu5deXzVQ8OAQANT5mL6Gmuq2Wm11BUeLRmCzMguBnLl0Ok6VIgvROuYIjrcyk838GCSl3b mr0+D19LskstHRgcdzfbBn4PcdVFQvnQ3CM3gbOByzpDZdSC8wtn6XTL38jafVFheF7ghahxEkZT uE0kJD/312YYpaYpGcqUxUjwazU5pN5kK8vj/HzUcgLs1i8fhiRD156Bq1BPVlYAUkSM8ANosc7S TglZ9fXuh2l0KeXNPrdFeifM5BJMLgPZ+1MdvPe9LHYdt8ryH5DMw5nieKwQdsyKSClD6VoXwDet uCFceCNhbD/YtpelyXCRh5e7I+WVSJM0YnIRd5FJTaWi5U2SMHTcd1Rad2PiOaBRzUj93MdH/Bt0 183CT6rg+SNdx3rFLsRUYBrFnjkLj7gxIxV9uoRQe0ptM84WAg8HK6ar9eZ5tkXdIZYzKno6ndlk 4zzs7HcXsZt0m0DCXFMyhehk1zA9MUTKFTlmK+fzf0JCHnmjjNQkcMDBWebUcuGhhtpmpUxdvID/ a0mzznaZQDpdx1fPpfMOGxlNOs0YC1rXqp7GvRnmBVtCoO7GaHH1ZoO1PfgHlBGj8UgXFGavVQGY BE1rVnFSUa7lABa2EBeEhyDU/wgk+B6m2AUxhN9O9gl39E+qeaDCKSTx6SpbNGCx81I7M6E3IniT /Re8SWc+GTAjKxmugRnZsNIh5GgKy1OiFJ6YYyib7FldhOfaqUPIa2kds0WwnnzuoPm66NOAWDbN wXtl3J9sALO2FrfrDmQhCs4P9u/DTdGcu3NX1bQkRryglppX5cs59Nm5mGmdR88ihpGo3v1F4sAO Ap41lXSe3CWSkKydGqLBUFsF//egpZ/dLIcknq3Q1rQJiNgUiptd999CAC+YK72pMqqQ12xVz1Gg C3OmsDOSW3VdCPsSnXg2lgrfsJb8wKMccPioMptiqUkUyZFQcK+gsww69M1W2FcI7LQUs2/6A8f9 hJBaTFOW5Yxo7IddJ28QJaJ6k4oF5diUXjRgONJWBiC6j9Bm/6oD+7Qq+3G5FDcL55fDdPj8Wzu4 un60Jmb15baFUxy0Z9rhlQ6mnwIp2IWy5O9LAFdW82sMVhrJ54I+9MRa/l4Vw5br8GsRxI60hGLX sFxeCq4Ko4q9ZZPB4tDE9vnJWe9jr4BDg1SWshsjJULNzANMlwKI0EfUhS8J4W195jcWVuJNgHV7 d6D0q20jRmxp2FwXhsu6CgLfxZNQco6+YuXgowQFVcUOkGM9SHb/8f3eKEQkV5F7KbM0ehiN3BN4 T/PuDSdqYpXWErlNf7wQSdJrC2k8X4gXmwSVqjmw2ggx/PF3NVJUl3H3xTXYghOabSQREgph5Jy5 LFvmCfBdkOd7U6/Um9Z8UfspPNIkW7Sh2lnF2Jhw3okoQ0LVBjxeUVHApAlQSm48QyN1Yrhs0xw7 RDYWUN5ZA07uYxBrJuPibNxfCBa+czfQeBDG1DGtPHm7wxXmY9M/5SVeSprVl3dqsQrr2gCphI1n +LHhJexN1PIm53Gd4ULcGAxubGL/S+mfDnyj1bV5LP5/FweaghKpvJYaeco/Du/ToRbDn7EsQf0S 2hlvV+Iv2RnBEDtCsfBLczQRxQLPTxP3yeqrHHUIfTCLr4IkEvE5mkALVjw0P737dM6iFKCHQMvc 1a8JLOyP7oFzWHYXmyDDGpqs1R17FOTMYyrMwQu/EcIGDy01/zH1ewF3vGFBFsErorcjOzPHMyPA 4bz3B/3bS2oFj4B4XPHdJFgJ8Vh3yiWuv3bZQq/Fm6e44vlr8YWALVzSu4tXj1Qhx26elmqoE+Kj ZFr/8DL6iDVUXxIn0ujJJdRE3Yh1VXlBRiWq08cuYxm4OpbLevE3qcTFfU5bTadh0VNSDqcF4VQj NcpMu2y3wKdM6wDvtQ8YEnkQVtHeb0pxYZz61a3xPg1mZB/ux9XmT7LPaqA4EVfYYOSZxt93/Uo+ 5NX1N64yiyEmNk0tp9KAdCJs7QeqQ8WwzgSglqT2skZdlxwkB3w6Vtq4NtmvZen3ulSHLJ3aUEZs 9UEQjukIv/vzBKNhtwpjw1f1eMZdpD/0WgJNwESEBjOcIQ30bNrWZ2qcDqIuPTGjf3grZ/mA4VHl T0buC+P4PKEB3lxzh96dXPFPfRtpCgKDn0aO4l66hZINDqZg0aPLtJ9JW1KJmJiqIJla72rrOtAr UfI95nKMNrU4GUlIpbJT4Ru5dNushZ8wQFfHNnOWzX6ptPD0kwwhzq5Ho7k7h9idLMCPPibb3KDY 7X1sZYqUuctuSiy5a2ByBXJ68GdPqqA9EO+coGF6GTMQ6VOgsfWHTWYOs2BQy8Bf8xR6f/6CWGGj OesMGNDuUoUlRIwZjjWSVVSX803yPauWAYWuYNPPFXUKxu7+uSm+GJlOAbyVp9RNwlkm9NRr0YTD MrkTZRgajj0hnYgyEIVSgjbBAGbx6/EklJRXxJ8Iz7m5Zgfc3rQvmF8xJgmFu0I3/nx4IDtgtq9d iJWYbD0CpTYaSEy/YNMwa2gQC9NJsOLmHlXnunR/QSnQOfw7nn2JpcUF5vRa2Sjo9m+nYnZxepO+ zmn3WpNKjVA54x4duOaVvG2xKWIQMh7wEPMpOtbGEhlcIcTBeFz7Az8UzSPuY+hL35Vw7CXCx0bW VA6xFJ40KGMvgMFOmaPXmztXHbkIUfkdzTwBmeHq70J5BQpU7rjWiqKFitAzUXX1pB+Z91j1yvEk YkgjsP/4kjPknl3W+eczONV6dtJE4pGxifOV2ZqrAr2r9Zn+PVVs1NogynOZBF46sjXs2CmqDs6+ QtuZ2c6JDZPNq8ZGtss4TTdK/L4n8VckGehee9bgBD6oqOyFZ1+wNthiA924cA2WJ5JBTrBqr+1O BFUXq0EIKEATAYPhMw5W+QJaLlxT3ZchOHFygqHp+yTH6EbralrHfQCcknda0p3mugku3TiRFbPC 3LTioRaQaEZY3i9CuxRVJ8ppcPt5zr3ek79BaMfg87VnBSsPEcK/uWifDyuZImt0xTob23swyxkf Yx22/p0dot+TqGV91dPdFhreSao9aGRDYn6F8AJKRHUrSNLC5cX5Fyqn8fcqB2aIj+F9iCsv2Jo0 u1xwek+0GaNcxV/ZppMJhHGCWlh8w856VaQzqUfRkN9bqicnfSo1zCwbNEPXQnPN6deaNL+dJLFk mwqOemNfVYeQLRgL13PcXfUjf8GMzEGVaRtgJcLHRDPjftDxflmZ4JTcUdGG/RRllz6n+7APyNAt c/LluWO4CnNKv194pv3twb6QXuTnsLoD1lG7q0gGXfOP6mHYF+W994JiSblhfvQ8MRbIWTVwcKVn kO0yKQfObTs7OSPjKNGgMBwUYaTwiszTkPxkpOYOtMHXTIOIDp3XtfGHX1mgide8OciGBnsNWshG fvYqw0GD/sH7gKO1IMeYoPD+xzkREDUMG3caOSrVe+Wf7NUb57QQ+yPxO2vinFEmbI+snnNX70su UYG5wy49DgaDjPmHwKZ7l9PKVwYUFpUWeFVG1GDXOx0brNFiWlxJMgqpn/wIoEUQZqls2j0NgOcH u388Oz+JBlQbEuuvOUmdS0wGVbqVpNetMCOvSIcIh4S0QJ+d/M0OnjWTUCBHLBKV8i1AYjAVz+GZ pV7rY3sFyW13lpEKat9K2HIcLz5pkuiE6VOsqQyy4LVgP6CiNRgdXi+FHRz0D1gs1mPbsBt4n8yP yelt3oal2+gfTV+kshaf9Nf953ErX0z0HFVGY7Vr62odvMDUBaG1rFPDYnrSjHDX1kxgFa37m1Vz cgL05AiOwt332bBY/FC+Ym8NKs/QwTXBqAlRP+lpTwA8qYmfSkeYXHA/4FeZTb+LGlG46NXcv+8X VXg8EMerb92hTWYfI69dHPonmzEYLXPile2dN43VKMiyH5B4wCnTrdZNsJ8OOv9D4qrJkIT8ulS8 GtpB/1LYrS6aZta0oZg4PDI/9C9gtCnafLBYs8tpDU6j2YMMfyW19PfEV1GPs6RX9UTjRuzuOs22 wVwfK80SJLRDqHGSfuHlrv7+yPHA4KTqNMapytLjPsaTWWsrh6m33KmnL6MXtSFejOc/kudIz8IQ SfN7LJSM5W2sGTZrR9mxc4dDFPd7QJg0VEqzzZgpvBYQZ3B/GIhROsTTsyp3mINJbJIAnPA1nUST Zs3upQKkFSLKk959ccdoLxDaKXIpIORm0RbzrRAb2Pgs+022uQaSgQQqrPgf6rZ6vinzjqeEcS3h +43y3mciwPf4W9CBTG/30MFzwMMVP65mSk/GtWPJV/Tv+xc83VoV/A0Qvy4OUVG0SaDPFifk3ksO LnFSM6UbxobQJK+V2E8Dz0qGmMHueS+fkCmvuFZFhy159n2mgo69eo9odM3pFr3MlMAxJGELvsLN 6oyuBQYBEMTtTe8yQ7Q/Gv2rVS0FBcUlVqwaiq4VUlWJCc3N7U+9/C1iwgml93JpbtQc20Vgg7Dy cmw29fP5fRqhHNvPtF+e6SPAEugQ8fUYumFJn5zjMWjY8DEU+YoKWsFhKEj8TghFm2GeMztynpke /cUY/HxoX/T6FoXmZvb3Af0ZlP6m3p4oagFHREOYdyElGfOEukBxkHhDRuXhGtp0ssjtJ69a2zYP gA8NpF8AtJVdZuu57o1Xt5P3331mVTP4gMILgitlL+/mLiQo6LolaoqK/oUcbpcXMOxK2Diif+lF YpH/z6vvLMtf5QV7VRFcz6tEt3LwZ+bXQ6AiH1mT+3O4zFo+1Zu0hWGkos4EM8uU0Gf0XlMBLoou Iac0bsWVBYopmfbpLYcBNdkSoCsCZ7ToMCZ1sWYP3spgSJPCg24whYgu3rLfWT8RKE8I+62H1hvZ BmY18HKGxrOcqycQTxX1x2O7FP3ZYy5XuZXLZLxUzkIbxqmRSf56NsA6pwB15ss8xBn7avNK4omp s7cRqyT7Ik7mM8Q7taFJs7gys3STCqMhvTx8CJB0eMbS1cmbmdvM+kEv/y0yhvwcyK/iIoZ0dqBO sKYHNTyOUHf6xlbDMsClUShhJ9tqZhEZHTu8eI7uHgcLp+NEdrPxr34W+ERn13MFpRWTPWue5Tif /Os0Jsv09u/K666JAmSj+83WDgfIt1SkgXpUKIZ7G0VxM9Y8W9OFfI4cayj14MJWmrY6EQbKb0Gu p6TPaypchGSuJu/D8Dfsg60WrmlAnNBkcUdlIp0yvzJksofFS+Y39fdfLXckh4GHENfqbn8LCcHy 8XnwuaHUtGXBxdgutXXLn0X8vvacxvXiY40QgONU+W2R/HPbVhGijN3OVC+9bb/Om+AQYNb0Ybsi gYHRkmu607e+JQFjN972t7a7IXqYVGkbR4m4HENdKy6YMV7Gr6bjYEGnn4lk5c2eSRmH8Caf/7AH TKZrrny5MQwqn9Bk8CtOk7iGDh8/Q2qXpPK9+wZJMVh/9QMhc8O2Z8l/AfJGwDyA2LfBf4QPhvw6 e6UqAqyJNnIGX/0t1PT1fdw2laYrSxgUsFElOpvZRqjmx2vXvHC0R7DO/BfJnUQ4I1fWHoAT3uG9 h2f9hsKyegovRteavYDZTVdqOQoFAGUKJ5JIdAneduFf4uEbR6pJaraMo5Z1Ws59YlUVaZbVMRqI KvF+TXkTXJ7El/DeLcBE/o7Ai67lR3+YK2KoNSDRZZmwf0X/3UzO7FIPExuQop5Hxmk3mQCM2oHb 6dFgiQjGxCvkeSN1V2fB4R/bz8BkezfNKBgL0lEM/PnkhdHefAfs8cgZs1ZNUDk0R2laLUqX2EdY ZJjstGWCg461biBhT/mBxXxa4iPJIX+qkhEIAEM9Uj3g6/BNbYdYZjUN2zxX6CwyaRqV6K2/wqiF 8DA+ZdH526WdsbPwhAY5bessQoFtZUJ3AcsBkGqdgVi5aJB8EBTTuHc5sZ50fAH+uXE77VHrx2Gc 5dnsNfTLwd6SL3XYdeSyh936Qhxxwty79/tNCX/o80CrkXM3B3vHMZ/UUXT1OXxk+o2uJd9Xo+JA GOWoVJyOXRhlexl3UZUmG5tvj5BoKxz7bcrdZ50Vws4llU1OGDVpF3u6c6viGhqlmQg2SMGmJsOE jV2D70s7wf4NzuUEIXCfCTkRTBI51I419ckc+mNVB9udf8co2sXzZnWHUYXk4Dsuj/fKGpO8m9SW o8TetB1vGzX0QhZcE4PZPFcgSwZ7Cp4dhBOs4NR1E58v8awbBQEWo6rYeU1lDAXiXn63lfhjPv1x KakrqnDTB30O0tVwR8tnTFrRrbpnoNGZGzGQcHd3IQfL4vsJ9uJAULaUBraA6DDRNK6JvPdKvAzs Aspvk1uMqpKiZKQNrKfA3mJ/v260StH3qu6c3RH6fTpSBBK7lPYnL0HMDa4krD+YORbLbfVoL2Ni qzmLaV+chAJz5UY7xcPqaUsl0iC2pRIT8esBH7IKlB3E3AOBubaBILQYHJfD2oVnlqPQHiTuQCzR Dt2kxqR0AEjuIf3cBCubEG2oE9bdilaPieizBUeoOhpWgdRYShugnn92YJdaJYTZNKT4PuhYNoUC BqWzMzf3tsHoTMVYOg5gEz+ijh99CSjkDFkVuAVjxPqmbUVsQJ6VBx21M5sfbUG5tqGS+nr2VKjp wF0dv9ONvCGHWhyDE3gqM5cHn1SeclhVe2dIBjDoL1OHDzV8xZJSKzDDNfRt2uiZIjRyc6myp8Wb GRkJoGFsqGMNSC+fhHBXAD/xtzUdYl+Tw12doHVyju3VwufBlk9eNnkUgpZpMslcLV83cQC1vU3n ngw1npoi9ZHCFSeopN+7CLmcvLVvAyb9xg/DcO3DS9P7FABsDHDrgflwZDGeIlVfsjACfiEKExwW RZb2FcG4mlQ0xOjj8A3Yj9tvqbkHV3vNhy4V8W79Uqd4Kf1xrD8CtPk//jxvLY2bQGVbh/EdlTV/ 1bd9PvhVGxQ6T2q/Dwva8i2sfW9dJyoJOEioI3OZQWAc9Axr9LZbyMO0Zraeai/1l5p8/BT8ffrG zU1cWpfCUR9Ka1O5DqB5L6IDwt+kfWe9FqyalD3v+jMeK4V3uXPKY34I+QFhQ0XgzVJaFmilLGfn RN3JXgfgGMeRWbgeqFFKF0duBLdeI+QhJaOUY0mIbRG2A/C+roT56vG0oWAvEjWp1tpmpzeowAbf MX9UOkA3ppgyTSHExaMRqtSPW9boY5mhEtL6J2rlZZ6g6uqJG/vi0bWBudJWqgEMSw/s+gl6TwSm zw2eafu2W0dCeQPAGjIo6ugs4UJHZ+1HUE0uq2Frw8T+NJul4zBFdhxiTcuUzKgysHHnMsVth5HR 3ieQKVZL4rA0obtY28Ivp+ndgDRHEah4PXDf1S3Wy3vi7xqMFCJrLJzGy2VKXyoMd2U900s5jr6m YEWwz4C6877610Y0ZhPFw35UC61JUI1gg9SasUGJC8KCnV5pnHMrBPaaY4VCjTrs2ZkQ9gortswI xopyqG/NQ2kSDPvmnniGcvi3p5W67O+HsHB9B0a630Xwt/0NMNifJAdITDJ/3NctS3FcyB8WJVds PvldVBqgUq6oayKvGtcbeDOFwoRQYBlKB4iVIQDawquENIcJXetL9k0iw96IovXVsVeUTz9Rzldz D267XNKZm2fq4nNnBwropr2FDvnYFUPssgOYXJ4uxjgV9IWvP8d/ILYhaoIjMCMxKnRMYXGx23Jc /5JOd4WKnDSuwaU60o5OJhdsjN15YiCqPwM5ARHCddFPzcuyed0a3qH8UJ93765+SoYAGnNuO9LQ H42ZLImeTZbWgwamXcYa3ELeOWJdyP57wmhlfuFSei5nds1vktleXQM85InB3eH/gHwJpnHA16y1 eMsx+NANuFrCRZ9JzmlapiTUr4l+XfycC83K3UQKSZr1YvGngSgpSsBu6tMwl8s+ZhMqrrlfGJ/N c3FiG9ANlrJIuU4pisHZs2UgjdORiwVL4IPWkfOQSk+09tN1WHToc6BSwUEdP7+cDCI/kXvv6oCm 4vuPPKScEFv0cFvwg/C62PxvGipEnC6nkPpaW6lsMWoXjar9OHXeIgGGVOtyvuOLLjPlbWIDK8n+ pqZnWTRwUig10EC3CPSYtRk+6srwGhhHe4P2hgBLdb91KVweayoCF/rYT7ra0KiXQIqsz8LGlWzx O5xuI5/aaO6cNy0NURJDayX2Agd0aVB8NMMjqrGI3594Rhj+LoQZ5F4lb5ugQDgqDsK4pT6f36b4 cxeKCe2exvQ04F80ivNHuO5ywPIn+n26mRbOrIs6blx7Bcr1XsnYfSJnzeWaBpmm3spDuorEF4jk Uj9bUKMZGm/2pWDLZNwQTcqo2CcqgP4ZJDvYkZuEQl0ubefintDn7YTUwra3/6lFHv9CJ0ZLJdvK VXMQ9PnsbqcbQMKQQsANXpR1hmn2/rcX+OK5mG1v7oeg2JXgSGOTi+WNPz8Iw7Zl/sq4yJoyKgMe FEvPsQwLeCDoEbTLK7LmUUZjbw+ycISUNU/0Er9rEFA9Ax3635xgddBu4gKR3aeaaOLJpIVa7X+J zyJtJLWlW54XMpeMnuKrg0IaEKMeR8N0nCeC+DVOO1QeZjycyevjg/SLNP0bauqwacULCc5ccGUD fLQYcL3fKeppkijfeo5nR3jkU1ab+1exr07Oljs4QnO8kaE6Fk+/5HKDi39yGXY7xyi4IqKkB/FR fT9Vv+ZPi4HvqdaqQI+AsorFskkff60DGFWxAULsuiVX+rIHqQQZggwT21jus8gCbHYpZpw+Pg/y Az95NYjgjOlf4N/TfoMw3j3Gvsa6HflUPYDPjek7Pyaf/cRWKEd5Pr5hZIKlMzl5NHUx3sR0ga5x MyvSnVZGkZfEgC0A8IamHgc3UNup6N6XRk1g2BLYndonKg6oTrALIZ/2fAw1NND8JVYWx6h+HxFN uD8DlZJEwfKAm2tmWVb3iGj2fNg6OSRHWOjKzCN6Dlk/l7v+n3gEGpkxWWUcHY9PX8HyulNpwJbU M7+9DK+n4iOM4atss6sdh76ehEkJaM1/4VszkvIRLFWiFefkwUaeHzqBLSP+pewNKm5baAd5Rigv I37H/tIKvv0BwtnCK5+/GrcP/NGk02r7msbtINSsP16Ig/Ey4dH8Ydhtpab9cQ0YNt1QAiEOQIhq B7y8ZCc6TUwWYsqRHKa3QgcO79Mz5qcsmMaO5Mco8NBnkNQ4j+pBnrHHsUStaQNC65OncP8rsTFX +lNuUfSi0nIk54ONAXse3sq3j4xS2dOK7/1w0fBLglNlVDGzU+AIAiAQxPP2ftwr5won6Nn2HeZN ZLnA6eKVWZGz3GYpRd/wyI5SSZ/+PJh9NK1nBr4O6oua951K0ruaa4ufOkzEbKiEY7vUXwbGLAvk abRXlIxt4S90miymWfORxegVYSqFqSiXGbGKzNLvYvNdQO0k4o4LgD2T6H5+figPwidihXHFJRCk UPAUOD3xrMgNTHR/y/eugZG8/lLzKhWNpUkHA+O0O8x0MTLak4kAesYvnZVqA955KoilOROgcGIn I2tUEQ3xmoF92r2sLyYlSlMwWVHLBj33Ps/Np7ngI2ebgI4+JbAnlPHRm5LB0WH53XyDNgLaNjUf qBd2FKO856qKqz7uZbmSocWthsJyePdP9tcb2Ps2vDwJgIC2qZ7eGyD4kUCZOIi4QCmPyiXMEcxm Eqav2r4+pdb6e2J4ZaoQ2Xzeh9akIxxl906YoLwPum+Sblx5vsMqktGPnLeNDnVm7BP2ZB44IYd5 SxWtWXHTuspwrdX2JlITZ9QKIazykfLVh3HjnwmYROh0rxv0qXnNZuX4fEK/wdnEz/uyd8a0WmGO OZeEmZ/nYGWMIFlpBVAQWANuOyQkktBO1DkKZEZTVFaFaPZXqipdaG2lDCsTauvWBAiU4jMaD03+ VFgUvwgtvCNYuxRyJcShO4MA8kTkNQi/J8Xnuj+eQlAQ/VeUTAJ+5m0gC+xU6k2aAoZ8J/OlBwiK wT/FkuLADHLRQTYip0flCVrlB/urySFdaArRAGKFZPNFQCWmuMLWu2oP3ERAcxFnl+cQNFjzNza3 lwv7F7v11D1qgdSPwl91A8VnB9piVWZm93UCGdqvx9R9IYOXJ6y94NUZq+byTQOD0dZNCj+ir/Ps vfNE2y83Y4IN59HSY54aC8Lj5K/MRXJYwvUgmWdbpu0FY9RSPhvD9TF1zkfn99+3E5rm34qhP4Xc tYzg6VRAPyxaWKOavHj92IuhLxFC7axapIjS2oRfMqp4TG8YIuAJffRH9A38Yrmc5B5C1gRBXMP3 KQMwvTIiviF53mi+UwQPf7jSvzxtsFXxEgEWDoVdVZUUjq2CRMNpjf7uN5qyS86eaSxEErBwPphb M3jh59q9t4hBIg92EC0GO/NLQbdAPQhrpXxrwMXLPPCd6x+kkAN/a6WxUgLc3Vi4E6jjvoVoFa1H 3UZxy75d87JDQlq1eJrZjpxao2H6FpuHrc0HjkG2cbqtIRHGNRAeBNIqKU8UfGOgGnmp0QKle1Gp +wQuHBYDDMecuC7O+u8OjnBTWPqouq8cC4TkfpklpEzxYFGGRf2k9aEU6LUEEbu+lZNKx1TnSeDP UtEeoMkupnZsImkdKDFNDvZdGSPCqjyVOfQjWcNu4W5G+Lhk9Dy0taI/bNCSl6MBAt9aGMizR5Jg nLV5r1f6yK45uNgHuIJxHJ6EdCkHlxJHbndgMycBaWcBeQMyLvkPqqSsjYWyn03qd2u7dtI36JUO Dw3jZpHW4XXoYL+HmxQsYMROFk8M2eM9wTo7cwVE2AFZZReC4QDLiuS5daEdspE4Ofh+NNw8ulMq mi8ZVptmQ7Sk2TcE0qlRLI3miqeR5V3VaHXkwa39uErBQxo6LZuPbS9DJCF3tSaWgOCLOkznSRmM TjDsLsmEb81+YcTaAp33leQ4RKQuYOlThNdabG4sq4YsutJil24QhQft24zKBwciyE6Smk0kAS8i akCcRHbSagVg2fixaeRgaXUtjd5yBafnbuwwo94zW9AarMPTFnw6pLNEfhlWXibriMeKPgwuoaCC JQryXsIhi1pG/ohrDOI+uCDEeZGcF5sBfE0ogPYmc+PZeJHZs2Mmeq6FFzGCWUluyW3DYedY/IgH 0SRGDj3vncD0UcrD6hdJ3UPqHt4edeu/n/JczYUfKYWqN/dKMkLtiupbWsAMfVqEGhkGdxb3EFfw RoisfhlcPB0a+nYoYPdNl3EThL0QRpzaWm1Sk+iv0aPMGgX7CAoKtB7PWK88SF8KD6emrh3m4PTt y5pCDjdvr0ceq6LcRPQqS93qLV78JwU/IP3R57rPHz3l0q7s+KrPial4XAabtj0jJsMx/iJAPD3G EzFw5sLt85Wfz6Iij/wWmCD4W21QvLPv/UKumpe3yOjH7cF6AWNbXnXsDxLsQWPb+CYLR1m0diEn K7lQRloL2wBxne0DdGYTY2jrRskXUWGvTkkTnq0OmIDamr2fXWqQ4fgs0trZBWEgIIxwe+sJHs/6 31aIwQTf/1Gcb0hzVfbkADWNDVQisn9BzAgk5l9A5W4mXoL5kMWOqwrk3FgPFai3xKmWA8wqi9xD EWaUhmAvzuH+iB17inrxW4tmdMiSEC7j/MkiqN0tklwpd2wcmD6QzjUZhZB5f/W1oQdxbL1YswyJ rjsxtdYKQhQ6XQAsMtAcF/vRqlyBnVgT9nZnNjf+mlZnEz5X23k5df4oTq8vwI9Vn3Fn9JjZxOU5 U/R/bRSN/9KMp8A+qGbwkGkBADU4lK0FmEb3pPTLlc2YzCncGJUY5N+RJbgpXzI4SSrPilWehQA0 +vO6Xu/no3tH9pVwn0ms7/vmQB3FizmlcpbyDyRkUP+aCuq8qFTc1EHGN5y6e0c7nMC3uMU/tkV3 KeUBJvCKSBqGH74i0SruFhvGtNObYK0bNqZsjrdfP2JnUUMVgVbWWbviml1ESTw1vR2RXOq11zY2 8aFBut2cI/MjG1eBKuI/joEbNdd+v6yBWJ5EbVJszArzRfaG7aQatnvCRuhws8zVICochza7trcc upF1GnbDDBSZGHiMIeak7uKkVNdWXFLqRsRZc0BKBYyLn7SuW1GcTJaYXm6WyOpIRbDaqIOPibhO zN82IebEK1FeGTrnKODf+o1Rpyx19Jdre+q5SRZiimyFJW6BhlpmxJKKUtPYCija7CWWJp8UeZDZ mbfwDVUm5W8OvRCUjYMTyTRaCXKSZtg3iyEClbBBLbuT7abgaN2ZqXiTx1G26vO42l3qdHmXPE0I mOKOIHm0sSAUQuEaF4ilwwbQumHOUlbxXxbQrdZBVyo/QhiwEB9/WlCrpDU1XeT2oenh53+8pfx+ XE1XCrwJS9uc6hs7Svx+SR7lcveY3luVqun0VEEHc96K5MNUpWtqb1SJ2bdSuz/VK4c8szgTBBvv e1rbW/vJYRv1eX/JAgp0DmUdF0HlpFAHBvDcmRbWG/EH7nw2EbKmYrtwcRABHKKJfu5Adxc1SoVu RHDDeX2BXUFvwhQavw87XPmxnbonN4JS9uu36tPUX3HMDmS9FiF4+/vPifNpOMrF83M4aceuSiD9 2MeVpqO0rPr/TRaQEhugICfJpI5K4uFfhhheiE0HxqVdZoTsDnZAz2USwRaX/zxRS2n+BHmywe7W Biu6OtNV71MniyRrzeM5xyLJDOODQRf7xSX40okDfuTVgXCeP8kiDSZuYG2xuv+Ok0t3N5+293NC +gWEoFvO9pIN2R2oP+uvxBZRGA1MUlRy2jLXKNkjRnsfewW+DwUN/Mgcnfua13ylDO8mYUUxFrgE rukjmMaYKNzgGdC2KgTMeBUWCwNkRS5qQzeG96anMp/vpb5PgYnvBEmJp0xcdzwT7T0aJZE9JK4f cTzB/wb/2f1Hyvt5RaQpPutcerC+yrbtcOKhPvaXkhr2uqt/L9vs+8NDSqvM+zTpT5E16x5m1U6p U2l/HTCP3/r57oyJ0CKPUWwdN8WuAFWAQaOLdveqjFAQL67nfn5OWfxgAB7u000EdsX6VSSErglH Bx3uE9PbeKnDqBtkAgdhDRVnKbXLGtELyRjqY1wBcAjQU4vSrItPOVySabH5W2k67z5nckGLsh+V onik+UjuDf/AaY1TwiaiRxqCZVhk+HQDlvKJNYhzsooeM4kMEyWy8QcHid8YERYAb+ds5GgTjJfE ZldmerEgQN9dKYCMFhKvAN3q2EpqHHFqoGkoHT0+k075jF2G8yCKy5nDKFvhwnCbcgDG01Rkne0d tHfH4iE3DWj0ec2d+0n6P5RE54YKi1b2TpqXvlA3sLm+sq7yimjajzHH3NwsCnJk1nE4PM8v7JhU rumVlxs7gT/7ueiCgExITcJUFOl0vfsybo0rikjS18kEMzcvKJyfr3Dmrztz9xHNjVsXNP0Q151M NAJ52mRQl/lLBJHz4GcFdub7bM7AlCgfs3/V+keRqR7X+NcZYBSrYRQQkzMOcKMYpUK9yVP1iaZK /DdyVVnhIEraI3gm89qTXjMMyzirxZTUL41nAZh1mjOKIcJm17gYSdDnKMeY8e7SFvFbi82sSoUd tejbVSGgJY5Xi/m/rfW3OORThdtqnk500DzIpAXGpHL76/2VoUDQJZd+lRT9uNvJ0q3IRgbvsydK HnbbR0hoeya2HBThdJvmmS7Izl88I0Jfe/BvA9ho+n7ekzx0dC6tBPB3aPF7o9h60ONeJR7s6jPE yjUcZyrpkqbcRPOqXl3/6JuFFA2QY6Jr4Rm3aT8zcJHnnW4Kc2O1tA4ph8QQ2V2b2NiPobF/y7L9 yPcN9c53Awou1LASbU9bybG7/vieNSRUzLain1BO12jgknDjGfz/iRChHzE0+b1Y9Tqjk8AeYDTL hn+3z4ozvfS28UW1oh8iPENmNuJ3auPVwyd7iVuk+Lst5jPYEDTRBOcEye7kBEUybjYguX0+PEMt e3sbDcaM8JNQBJTuvebM8zr8oXlPNuH4qOY4F4cN9poj9RTt7NYsN5FBbo2d+R6IwfPkBG4NPY8z Ksoc0ThhERynlR03PdXmW/Z5eEcnHdfeSSAFC1OXtqRm+DHcZcDFVfudVPnX08iH6kIld5L/Kt0l 34gLMgh23ch8XGkEwuWs6m4IMe+fvhYHk03CUuhVZDy/UibHjjI8Xgb38by4qK3YiV1dUIF86I55 yhdKdYeO4pFsEsv+ZOr3IBcr35/D80E3SGghZheBxy1PUyLonnI91CrNOuMHwcnGVeOFwr56FxRE 6fnYB9+7IrH0byfFs/g6Jh0/XObamX3oXnGy1EStagl+dLw0nkcFPPQ+wqOfuUzZ7y0u+ryi7/Mv GpvFu23AcXpTm4CboDDNC0CJ/cx1s98ico2YK1YFKO1vX8yNGHR9fhdCCZrh9Pn6zgnbdMgRHUoj qVzg+DAZD+jSWUsSOSPrMYWFoZ5WJu0WIQCrDaO+dEkw+W4EQBTYGm44szr7drSfXUyXbDuv/W1i 47qJ8TwH9YWOs8Nk7UPtljwO97Oae95mjBWGzLn4SVwSrBEnxxwWuZLDLxLbCmbWVEPy174KNZHp R8S/mHSyc7PvWDjOjYetXi4b8GjdI0FJdP0Su8KepkPtMfR3K8NAGyDVBMWZZDqWJJ9IAqq8mof3 cK9NW60p28ljapPGHcTWDiWjjLFAKa+baUBlBjqMFi6CjrXLbmNdkFT3vi/2gzfKdspSNGMOuG/k Uawu732u9g/kZMH4SKsAyyqUTvEDdXnOZ0mEDM9Tanov/5pr6y/nS1dErkSg3P4mcGNveFjAiI8D wDjuNI3chGR8TXEJSL8Ei84HWRUw2TdZslB+bypmZUOhBhGRwr6BoWlmOgBuvYK1fzB+3fa9S6cK 4BA/RrL8dKOjbyJpj+8hnbq3fCPasv76mdEX5T4lvg7qTEC7LeJtklMF4Qenb8VrITIKNgMKpEJd RdaB3YPqaapOC2yoCi5c2H7BPmwie4Spkdd8Hm6u2kkbvEgxkAQd0WjjwCizTUNCxl39a9KN0AP/ KSIj2RRZrAQiflHCzeDtcn8CZSfSetr+CoCE+viheBImLOMhfYKEaxtQ5vMHfhtWQsb1r0ma7Lal pVfqkn4NCfEqjxWPfcPWXr0k3tKpMu4MjVyNARdzsbyDslfwqLrbUvcjoK7pFV8RES9+gZvbKUb3 UGzAMalwNH+QoHyTjZ1y0IPNH3/JonvSr+vC1OiTsa0TYZvxi5sEGGyANKOiLUCwP5tVByrQtLMg PJBYaAlCmegS5ncUxaNwEFTeZO9YtB4kdPZyAcHyivMGS7j5JpiNiH0BwlNhPg+dN66T8UjiggBE vEAnfpEhHiNmVjLe18lre7I3Ru1qMEhJjjeHN6BNP4fpHUJhn+F0EEyEb9zM2BiEltzTJdajIVko xLkFSQeBa4gF6OzquOCQfbhiFxo4fFvvIpBHXk0yg5aRw+cbZb6Qk7crr5YgNJ5D5D1VLtprnFtL Qr0ZJ6KtbQlZWbYXOFtDUeu46WdTSCASMvnkJyyNMbUlJxePqtzAZOU+QZ9kDe1JhT3LtpZsPB0r AZA6gvYlvf92JZARYVat0TfvnewSnk60zpr7kMQco18Y2yGrhmUFmvPsFtI7ZwDiQ2boTKYB34T+ SqVupvX5EO5MTDvJHJ0tneSLB1yYTbjNDfKTSaBpqGkRGrZfBywKGjn9H7m+BJlHqBqDRrBGs+2P 5ltocpVG6JSCjbLxORw0q4/j3xZaAS70gq7HUzgAqdzHLx/LtWn93xaZyOWChQO3+GUXiObWC7kB q1Qws7842QIbOrAl5w6NE9iHhNf1pQl6iSHSonsxAA5i780Zpeo8G8SUZtDNsbfmV5H8QaeYd4bD eyVlixmdN1cZ2e7XNdgw9m0OLmJgg/lyPN5PWVVc41ASGb/57DZNHdBh4iqOPmupx6PDtd9z5lii 6SDTLXUY47QCHsebnsuE8UixphBK6M9jmF2IE9lqI9LBxBccQPXWXuGNEv5hYGxUmmMpNZP4ikmt 3U+a4eWiagMCrwwpJtbvw6ueWhT6X3prkQQMyhf/F4+Ug9az5WkiuavEDEMxHWHCQjnol/puuRsB e+ghlOfVgmoMedcLqB0diPA+Y9XyqbeVfwDBb2Ewpd8kv+vTXzXqwEu+jngpiRvvXfaFfDR59PyB PXKlsqLJ1yo1CuEqHsSA/XSLKhH+sksPYp/Q+typpKfmHSKksZXvHkX2elAr5VhtSLPOzF1us/f0 e/kJhSnhK3ijgU4byuGgsRaO0GahHq1iqj4VeAuwE4W+9I3ICRC1Fr68dRcwBX3WWyfG/VoQ4reB +53JuWDrN22m5GOh9z3iQ21jc/oIJ/rLBxT8EnMXrEVa78/W3kGQrq8Z3riEdZtLFqHOLlW34964 ruGwj8qzWxSvmT9G87wfOnDM8vsSSYo/R6UHg9Y8o6GpkWisxxcXexi6dSq7DY1pD2v9slVbqCWl FC+BuKaoHcFjA8gEdpYIudnQUIYFyJrsfkPh+rACguBzvnL/ORQ7UXP3ryAAWpVNzH+kaXdazCDz ry7xFyBHMYwPB5XShZAzvJzt4+K9wgb8rrpv3B5un5zVHi833E0zH696zNsAzaCabMDQCVq7LdWD Zksl85thw9drK1j0yT6eIfCCiEeeN6+mdvsYPcr41uPPTOQkmpnDgeKFKmlkQNQ1c6pnxVMhOxdE dJDGqNL5J7aHSrHsqUCQfJdG6/sz15m4AaOSNSWgf3HxbY81FG4ymPFrhFtnXnu70z49pWa3vG7c +Y9JM4pfz/Va+cYxA+OYpinLh2jpGzNcsgJmMtfegfJJRmH634Z7Bh7WU8ACTxAIWkzjp7BK5w96 hWNdTZ+uhie5Z8E7l8ukFI2YyBjpv43Rbe2vxVZrl8wI/bpfW6szMSztwspxewzoSmkEBbursz4O 2qknI5SiONYDfUdMQdHKPlslq8lA8mySsshmb9H0jh/NQZVGr+pfdEqnbup6IFZ2O+XiouifrXOi jkRgq2zhdm5IfyhgXu+4vEXfW5o8OFZjzJ8Os6B7XFYFzrvBb+ozYvp9nv//dKQykHEv2XHbciXh +EzIs6YzqJ3KQXD2tfrxfKDTEfixz6cX7qQ1I/4thokmKZZQDib41iEiDmOW3vKNKovmVRsyLOW+ ktfJbFxsiyig8Cymqbnq4miUmxjzosso33+cr6cDP1ELmhDDiZOJPV4WUcxgpCCCZaGInHUcoYlm bvFU1Sk1jBOeFl/u4KaXh8DiivWAH/bHQNJaVuumBrom0k31Nc7kv/hxOq5mXwnbY+QqDq6KkCo8 bLdjb6rBbT1oK144x2r9NFRvl58OB3QBT0GWj1AIYMgn8o7WqxeH1ADEWvVIGxsu2RiNCU4Q1Hys Z6fnuwo7pGX/J2gv0azltitQWT6+BfeAwanmWQcYE/jSdtB8Ju1S3ZEGKiC4wFvZNEgPDHUqBCSp Yrgygi3OahV2z6NeRMsZChb4H0rp3a/LKybIqn4a/7/cSuHeH7pgx90wCEY163PNWof8oyofaE2v q0MZNUvDWs8rmtTkp8e6OaRGp3UVQXzWW+fS8Ni55LgX4xaSw8XU0LHYcL/U5TP6p+AEsw== `protect end_protected	mit

Bjay1435/capstone

Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover.vhd

5

74551

------------------------------------------------------------------------------- -- axi_datamover.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover.vhd -- -- Description: -- Top level VHDL wrapper for the AXI DataMover -- -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_11; use axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap ; use axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap ; use axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap; use axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap ; use axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap ; use axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap; ------------------------------------------------------------------------------- entity axi_datamover is generic ( C_INCLUDE_MM2S : Integer range 0 to 2 := 2; -- Specifies the type of MM2S function to include -- 0 = Omit MM2S functionality -- 1 = Full MM2S Functionality -- 2 = Basic MM2S functionality C_M_AXI_MM2S_ARID : Integer range 0 to 255 := 0; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_MM2S_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the MM2S ID port C_M_AXI_MM2S_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_MM2S_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_M_AXIS_MM2S_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the MM2S Master Stream Data -- Channel data bus C_INCLUDE_MM2S_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit MM2S Status FIFO -- 1 = Include MM2S Status FIFO C_MM2S_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the MM2S Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_MM2S_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_MM2S_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the MM2S function -- 0 = Omit DRE -- 1 = Include DRE C_MM2S_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the MM2S function C_MM2S_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the MM2S Command Interface C_MM2S_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the MM2S internal -- child command queues in the Read Address Controller and -- the Read Data Controller. Increasing this value will -- allow more Read Addresses to be issued to the AXI4 Read -- Address Channel before receipt of the associated read -- data on the Read Data Channel. C_MM2S_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- MM2S (Read) Store and Forward function -- 0 = Omit MM2S Store and Forward -- 1 = Include MM2S Store and Forward C_INCLUDE_S2MM : Integer range 0 to 4 := 2; -- Specifies the type of S2MM function to include -- 0 = Omit S2MM functionality -- 1 = Full S2MM Functionality -- 2 = Basic S2MM functionality C_M_AXI_S2MM_AWID : Integer range 0 to 255 := 1; -- Specifies the constant value to output on -- the ARID output port C_M_AXI_S2MM_ID_WIDTH : Integer range 1 to 8 := 4; -- Specifies the width of the S2MM ID port C_M_AXI_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32; -- Specifies the width of the MMap Read Address Channel -- Address bus C_M_AXI_S2MM_DATA_WIDTH : Integer range 32 to 1024 := 32; -- Specifies the width of the MMap Read Data Channel -- data bus C_S_AXIS_S2MM_TDATA_WIDTH : Integer range 8 to 1024 := 32; -- Specifies the width of the S2MM Master Stream Data -- Channel data bus C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 1; -- Specifies if a Status FIFO is to be implemented -- 0 = Omit S2MM Status FIFO -- 1 = Include S2MM Status FIFO C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4; -- Specifies the depth of the S2MM Command FIFO and the -- optional Status FIFO -- Valid values are 1,4,8,16 C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0; -- Specifies if the Status and Command interfaces need to -- be asynchronous to the primary data path clocking -- 0 = Use same clocking as data path -- 1 = Use special Status/Command clock for the interfaces C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 1; -- Specifies if DRE is to be included in the S2MM function -- 0 = Omit DRE -- 1 = Include DRE C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16; -- Specifies the max number of databeats to use for MMap -- burst transfers by the S2MM function C_S2MM_BTT_USED : Integer range 8 to 23 := 16; -- Specifies the number of bits used from the BTT field -- of the input Command Word of the S2MM Command Interface C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0; -- Specifies if support for indeterminate packet lengths -- are to be received on the input Stream interface -- 0 = Omit support (User MUST transfer the exact number of -- bytes on the Stream interface as specified in the BTT -- field of the Corresponding DataMover Command) -- 1 = Include support for indeterminate packet lengths -- This causes FIFOs to be added and "Store and Forward" -- behavior of the S2MM function C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 3; -- This parameter specifies the depth of the S2MM internal -- address pipeline queues in the Write Address Controller -- and the Write Data Controller. Increasing this value will -- allow more Write Addresses to be issued to the AXI4 Write -- Address Channel before transmission of the associated -- write data on the Write Data Channel. C_S2MM_INCLUDE_SF : Integer range 0 to 1 := 1 ; -- This parameter specifies the inclusion/omission of the -- S2MM (Write) Store and Forward function -- 0 = Omit S2MM Store and Forward -- 1 = Include S2MM Store and Forward C_ENABLE_CACHE_USER : integer range 0 to 1 := 0; C_ENABLE_SKID_BUF : string := "11111"; C_ENABLE_MM2S_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_TKEEP : integer range 0 to 1 := 1; C_ENABLE_S2MM_ADV_SIG : integer range 0 to 1 := 0; C_ENABLE_MM2S_ADV_SIG : integer range 0 to 1 := 0; C_MICRO_DMA : integer range 0 to 1 := 0; C_CMD_WIDTH : integer range 72 to 112 := 72; C_FAMILY : String := "virtex7" -- Specifies the target FPGA family type ); port ( -- MM2S Primary Clock input ---------------------------------- m_axi_mm2s_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- MM2S Primary Reset input -- m_axi_mm2s_aresetn : in std_logic; -- -- Reset used for the internal master logic -- -------------------------------------------------------------- -- MM2S Halt request input control -------------------- mm2s_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- MM2S Halt Complete status flag -- mm2s_halt_cmplt : Out std_logic; -- -- Active high soft shutdown complete status -- ------------------------------------------------------- -- Error discrete output ------------------------- mm2s_err : Out std_logic; -- -- Composite Error indication -- -------------------------------------------------- -- Memory Map to Stream Command FIFO and Status FIFO I/O --------- m_axis_mm2s_cmdsts_aclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_mm2s_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- ------------------------------------------------------------------ -- User Command Interface Ports (AXI Stream) ------------------------------------------------- s_axis_mm2s_cmd_tvalid : in std_logic; -- s_axis_mm2s_cmd_tready : out std_logic; -- s_axis_mm2s_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- ---------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ------------------------ m_axis_mm2s_sts_tvalid : out std_logic; -- m_axis_mm2s_sts_tready : in std_logic; -- m_axis_mm2s_sts_tdata : out std_logic_vector(7 downto 0); -- m_axis_mm2s_sts_tkeep : out std_logic_vector(0 downto 0); -- m_axis_mm2s_sts_tlast : out std_logic; -- -------------------------------------------------------------------- -- Address Posting contols ----------------------- mm2s_allow_addr_req : in std_logic; -- mm2s_addr_req_posted : out std_logic; -- mm2s_rd_xfer_cmplt : out std_logic; -- -------------------------------------------------- -- MM2S AXI Address Channel I/O -------------------------------------------------- m_axi_mm2s_arid : out std_logic_vector(C_M_AXI_MM2S_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_mm2s_araddr : out std_logic_vector(C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_mm2s_arlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_mm2s_arsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_mm2s_arburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_mm2s_arprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_mm2s_arcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_mm2s_aruser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_mm2s_arvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_mm2s_arready : in std_logic; -- -- AXI Address Channel READY input -- ----------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_mm2s_alock : out std_logic_vector(2 downto 0); -- -- m_axi_mm2s_acache : out std_logic_vector(4 downto 0); -- -- m_axi_mm2s_aqos : out std_logic_vector(3 downto 0); -- -- m_axi_mm2s_aregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- MM2S AXI MMap Read Data Channel I/O ------------------------------------------------ m_axi_mm2s_rdata : In std_logic_vector(C_M_AXI_MM2S_DATA_WIDTH-1 downto 0); -- m_axi_mm2s_rresp : In std_logic_vector(1 downto 0); -- m_axi_mm2s_rlast : In std_logic; -- m_axi_mm2s_rvalid : In std_logic; -- m_axi_mm2s_rready : Out std_logic; -- ---------------------------------------------------------------------------------------- -- MM2S AXI Master Stream Channel I/O ------------------------------------------------------- m_axis_mm2s_tdata : Out std_logic_vector(C_M_AXIS_MM2S_TDATA_WIDTH-1 downto 0); -- m_axis_mm2s_tkeep : Out std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0); -- m_axis_mm2s_tlast : Out std_logic; -- m_axis_mm2s_tvalid : Out std_logic; -- m_axis_mm2s_tready : In std_logic; -- ---------------------------------------------------------------------------------------------- -- Testing Support I/O -------------------------------------------------------- mm2s_dbg_sel : in std_logic_vector( 3 downto 0); -- mm2s_dbg_data : out std_logic_vector(31 downto 0) ; -- ------------------------------------------------------------------------------- -- S2MM Primary Clock input --------------------------------- m_axi_s2mm_aclk : in std_logic; -- -- Primary synchronization clock for the Master side -- -- interface and internal logic. It is also used -- -- for the User interface synchronization when -- -- C_STSCMD_IS_ASYNC = 0. -- -- -- S2MM Primary Reset input -- m_axi_s2mm_aresetn : in std_logic; -- -- Reset used for the internal master logic -- ------------------------------------------------------------- -- S2MM Halt request input control ------------------ s2mm_halt : in std_logic; -- -- Active high soft shutdown request -- -- -- S2MM Halt Complete status flag -- s2mm_halt_cmplt : out std_logic; -- -- Active high soft shutdown complete status -- ----------------------------------------------------- -- S2MM Error discrete output ------------------ s2mm_err : Out std_logic; -- -- Composite Error indication -- ------------------------------------------------ -- Memory Map to Stream Command FIFO and Status FIFO I/O ----------------- m_axis_s2mm_cmdsts_awclk : in std_logic; -- -- Secondary Clock input for async CMD/Status interface -- -- m_axis_s2mm_cmdsts_aresetn : in std_logic; -- -- Secondary Reset input for async CMD/Status interface -- -------------------------------------------------------------------------- -- User Command Interface Ports (AXI Stream) -------------------------------------------------- s_axis_s2mm_cmd_tvalid : in std_logic; -- s_axis_s2mm_cmd_tready : out std_logic; -- s_axis_s2mm_cmd_tdata : in std_logic_vector(C_CMD_WIDTH-1 downto 0); -- ----------------------------------------------------------------------------------------------- -- User Status Interface Ports (AXI Stream) ----------------------------------------------------------- m_axis_s2mm_sts_tvalid : out std_logic; -- m_axis_s2mm_sts_tready : in std_logic; -- m_axis_s2mm_sts_tdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); -- m_axis_s2mm_sts_tkeep : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); -- m_axis_s2mm_sts_tlast : out std_logic; -- ------------------------------------------------------------------------------------------------------- -- Address posting controls ----------------------------------------- s2mm_allow_addr_req : in std_logic; -- s2mm_addr_req_posted : out std_logic; -- s2mm_wr_xfer_cmplt : out std_logic; -- s2mm_ld_nxt_len : out std_logic; -- s2mm_wr_len : out std_logic_vector(7 downto 0); -- --------------------------------------------------------------------- -- S2MM AXI Address Channel I/O ---------------------------------------------------- m_axi_s2mm_awid : out std_logic_vector(C_M_AXI_S2MM_ID_WIDTH-1 downto 0); -- -- AXI Address Channel ID output -- -- m_axi_s2mm_awaddr : out std_logic_vector(C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); -- -- AXI Address Channel Address output -- -- m_axi_s2mm_awlen : out std_logic_vector(7 downto 0); -- -- AXI Address Channel LEN output -- -- Sized to support 256 data beat bursts -- -- m_axi_s2mm_awsize : out std_logic_vector(2 downto 0); -- -- AXI Address Channel SIZE output -- -- m_axi_s2mm_awburst : out std_logic_vector(1 downto 0); -- -- AXI Address Channel BURST output -- -- m_axi_s2mm_awprot : out std_logic_vector(2 downto 0); -- -- AXI Address Channel PROT output -- -- m_axi_s2mm_awcache : out std_logic_vector(3 downto 0); -- -- AXI Address Channel CACHE output -- m_axi_s2mm_awuser : out std_logic_vector(3 downto 0); -- -- AXI Address Channel USER output -- -- m_axi_s2mm_awvalid : out std_logic; -- -- AXI Address Channel VALID output -- -- m_axi_s2mm_awready : in std_logic; -- -- AXI Address Channel READY input -- ------------------------------------------------------------------------------------- -- Currently unsupported AXI Address Channel output signals ------- -- m_axi_s2mm__awlock : out std_logic_vector(2 downto 0); -- -- m_axi_s2mm__awcache : out std_logic_vector(4 downto 0); -- -- m_axi_s2mm__awqos : out std_logic_vector(3 downto 0); -- -- m_axi_s2mm__awregion : out std_logic_vector(3 downto 0); -- ------------------------------------------------------------------- -- S2MM AXI MMap Write Data Channel I/O -------------------------------------------------- m_axi_s2mm_wdata : Out std_logic_vector(C_M_AXI_S2MM_DATA_WIDTH-1 downto 0); -- m_axi_s2mm_wstrb : Out std_logic_vector((C_M_AXI_S2MM_DATA_WIDTH/8)-1 downto 0); -- m_axi_s2mm_wlast : Out std_logic; -- m_axi_s2mm_wvalid : Out std_logic; -- m_axi_s2mm_wready : In std_logic; -- ------------------------------------------------------------------------------------------- -- S2MM AXI MMap Write response Channel I/O ------------------------- m_axi_s2mm_bresp : In std_logic_vector(1 downto 0); -- m_axi_s2mm_bvalid : In std_logic; -- m_axi_s2mm_bready : Out std_logic; -- ---------------------------------------------------------------------- -- S2MM AXI Slave Stream Channel I/O ------------------------------------------------------- s_axis_s2mm_tdata : In std_logic_vector(C_S_AXIS_S2MM_TDATA_WIDTH-1 downto 0); -- s_axis_s2mm_tkeep : In std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0); -- s_axis_s2mm_tlast : In std_logic; -- s_axis_s2mm_tvalid : In std_logic; -- s_axis_s2mm_tready : Out std_logic; -- --------------------------------------------------------------------------------------------- -- Testing Support I/O ------------------------------------------------ s2mm_dbg_sel : in std_logic_vector( 3 downto 0); -- s2mm_dbg_data : out std_logic_vector(31 downto 0) -- ------------------------------------------------------------------------ ); end entity axi_datamover; architecture implementation of axi_datamover is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Declarations ------------------------------------------------------------------- -- Function -- -- Function Name: funct_clip_brst_len -- -- Function Description: -- This function is used to limit the parameterized max burst -- databeats when the tranfer data width is 256 bits or greater. -- This is required to keep from crossing the 4K byte xfer -- boundary required by AXI. This process is further complicated -- by the inclusion/omission of upsizers or downsizers in the -- data path. -- ------------------------------------------------------------------- function funct_clip_brst_len (param_burst_beats : integer; mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is constant FCONST_SIZERS_ENABLED : boolean := (down_up_sizers_enabled > 0); Variable fvar_max_burst_dbeats : Integer; begin if (FCONST_SIZERS_ENABLED) then -- use MMap dwidth for calc If (mmap_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (mmap_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (mmap_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit mmap width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; else -- use stream dwidth for calc If (stream_transfer_bit_width <= 128) Then -- allowed fvar_max_burst_dbeats := param_burst_beats; Elsif (stream_transfer_bit_width <= 256) Then If (param_burst_beats <= 128) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 128; End if; Elsif (stream_transfer_bit_width <= 512) Then If (param_burst_beats <= 64) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 64; End if; Else -- 1024 bit stream width case If (param_burst_beats <= 32) Then fvar_max_burst_dbeats := param_burst_beats; Else fvar_max_burst_dbeats := 32; End if; End if; end if; Return (fvar_max_burst_dbeats); end function funct_clip_brst_len; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_depth_16 -- -- Function Description: -- This function is used to fix the Command and Status FIFO depths to -- 16 entries when Async clocking mode is enabled. This is required -- due to the way the async_fifo_fg.vhd design in proc_common is -- implemented. ------------------------------------------------------------------- function funct_fix_depth_16 (async_clocking_mode : integer; requested_depth : integer) return integer is Variable fvar_depth_2_use : Integer; begin If (async_clocking_mode = 1) Then -- async mode so fix at 16 fvar_depth_2_use := 16; Elsif (requested_depth > 16) Then -- limit at 16 fvar_depth_2_use := 16; Else -- use requested depth fvar_depth_2_use := requested_depth; End if; Return (fvar_depth_2_use); end function funct_fix_depth_16; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_min_btt_width -- -- Function Description: -- This function calculates the minimum required value -- for the used width of the command BTT field. -- ------------------------------------------------------------------- function funct_get_min_btt_width (max_burst_beats : integer; bytes_per_beat : integer ) return integer is Variable var_min_btt_needed : Integer; Variable var_max_bytes_per_burst : Integer; begin var_max_bytes_per_burst := max_burst_beats*bytes_per_beat; if (var_max_bytes_per_burst <= 16) then var_min_btt_needed := 5; elsif (var_max_bytes_per_burst <= 32) then var_min_btt_needed := 6; elsif (var_max_bytes_per_burst <= 64) then var_min_btt_needed := 7; elsif (var_max_bytes_per_burst <= 128) then var_min_btt_needed := 8; elsif (var_max_bytes_per_burst <= 256) then var_min_btt_needed := 9; elsif (var_max_bytes_per_burst <= 512) then var_min_btt_needed := 10; elsif (var_max_bytes_per_burst <= 1024) then var_min_btt_needed := 11; elsif (var_max_bytes_per_burst <= 2048) then var_min_btt_needed := 12; elsif (var_max_bytes_per_burst <= 4096) then var_min_btt_needed := 13; else -- 8K byte range var_min_btt_needed := 14; end if; Return (var_min_btt_needed); end function funct_get_min_btt_width; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_get_xfer_bytes_per_dbeat -- -- Function Description: -- Calculates the nuber of bytes that will transfered per databeat -- on the AXI4 MMap Bus. -- ------------------------------------------------------------------- function funct_get_xfer_bytes_per_dbeat (mmap_transfer_bit_width : integer; stream_transfer_bit_width : integer; down_up_sizers_enabled : integer) return integer is Variable temp_bytes_per_dbeat : Integer := 4; begin if (down_up_sizers_enabled > 0) then -- down/up sizers are in use, use full mmap dwidth temp_bytes_per_dbeat := mmap_transfer_bit_width/8; else -- No down/up sizers so use Stream data width temp_bytes_per_dbeat := stream_transfer_bit_width/8; end if; Return (temp_bytes_per_dbeat); end function funct_get_xfer_bytes_per_dbeat; ------------------------------------------------------------------- -- Function -- -- Function Name: funct_fix_btt_used -- -- Function Description: -- THis function makes sure the BTT width used is at least the -- minimum needed. -- ------------------------------------------------------------------- function funct_fix_btt_used (requested_btt_width : integer; min_btt_width : integer) return integer is Variable var_corrected_btt_width : Integer; begin If (requested_btt_width < min_btt_width) Then var_corrected_btt_width := min_btt_width; else var_corrected_btt_width := requested_btt_width; End if; Return (var_corrected_btt_width); end function funct_fix_btt_used; function funct_fix_addr (in_addr_width : integer) return integer is Variable new_addr_width : Integer; begin If (in_addr_width <= 32) Then new_addr_width := 32; elsif (in_addr_width > 32 and in_addr_width <= 40) Then new_addr_width := 40; elsif (in_addr_width > 40 and in_addr_width <= 48) Then new_addr_width := 48; elsif (in_addr_width > 48 and in_addr_width <= 56) Then new_addr_width := 56; else new_addr_width := 64; End if; Return (new_addr_width); end function funct_fix_addr; ------------------------------------------------------------------- -- Constant Declarations ------------------------------------------------------------------- Constant MM2S_TAG_WIDTH : integer := 4; Constant S2MM_TAG_WIDTH : integer := 4; Constant MM2S_DOWNSIZER_ENABLED : integer := C_MM2S_INCLUDE_SF; Constant S2MM_UPSIZER_ENABLED : integer := C_S2MM_INCLUDE_SF + C_S2MM_SUPPORT_INDET_BTT; Constant MM2S_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_MM2S_BURST_SIZE, C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant S2MM_MAX_BURST_BEATS : integer := funct_clip_brst_len(C_S2MM_BURST_SIZE, C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant MM2S_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_MM2S_STSCMD_IS_ASYNC, C_MM2S_STSCMD_FIFO_DEPTH); Constant S2MM_CMDSTS_FIFO_DEPTH : integer := funct_fix_depth_16(C_S2MM_STSCMD_IS_ASYNC, C_S2MM_STSCMD_FIFO_DEPTH); Constant MM2S_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_MM2S_DATA_WIDTH, C_M_AXIS_MM2S_TDATA_WIDTH, MM2S_DOWNSIZER_ENABLED); Constant MM2S_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(MM2S_MAX_BURST_BEATS, MM2S_BYTES_PER_BEAT); Constant MM2S_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_MM2S_BTT_USED, MM2S_MIN_BTT_NEEDED); Constant S2MM_BYTES_PER_BEAT : integer := funct_get_xfer_bytes_per_dbeat(C_M_AXI_S2MM_DATA_WIDTH, C_S_AXIS_S2MM_TDATA_WIDTH, S2MM_UPSIZER_ENABLED); Constant S2MM_MIN_BTT_NEEDED : integer := funct_get_min_btt_width(S2MM_MAX_BURST_BEATS, S2MM_BYTES_PER_BEAT); Constant S2MM_CORRECTED_BTT_USED : integer := funct_fix_btt_used(C_S2MM_BTT_USED, S2MM_MIN_BTT_NEEDED); constant C_M_AXI_MM2S_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_MM2S_ADDR_WIDTH); constant C_M_AXI_S2MM_ADDR_WIDTH_int : integer := funct_fix_addr(C_M_AXI_S2MM_ADDR_WIDTH); -- Signals signal sig_mm2s_tstrb : std_logic_vector((C_M_AXIS_MM2S_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_mm2s_sts_tstrb : std_logic_vector(0 downto 0) := (others => '0'); signal sig_s2mm_tstrb : std_logic_vector((C_S_AXIS_S2MM_TDATA_WIDTH/8)-1 downto 0) := (others => '0'); signal sig_s2mm_sts_tstrb : std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0) := (others => '0'); signal m_axi_mm2s_araddr_int : std_logic_vector (C_M_AXI_MM2S_ADDR_WIDTH_int-1 downto 0) ; signal m_axi_s2mm_awaddr_int : std_logic_vector (C_M_AXI_S2MM_ADDR_WIDTH_int-1 downto 0) ; begin --(architecture implementation) ------------------------------------------------------------- -- Conversion to tkeep for external stream connnections ------------------------------------------------------------- -- MM2S Status Stream Output m_axis_mm2s_sts_tkeep <= sig_mm2s_sts_tstrb ; GEN_MM2S_TKEEP_ENABLE1 : if C_ENABLE_MM2S_TKEEP = 1 generate begin -- MM2S Stream Output m_axis_mm2s_tkeep <= sig_mm2s_tstrb ; end generate GEN_MM2S_TKEEP_ENABLE1; GEN_MM2S_TKEEP_DISABLE1 : if C_ENABLE_MM2S_TKEEP = 0 generate begin m_axis_mm2s_tkeep <= (others => '1'); end generate GEN_MM2S_TKEEP_DISABLE1; GEN_S2MM_TKEEP_ENABLE1 : if C_ENABLE_S2MM_TKEEP = 1 generate begin -- S2MM Stream Input sig_s2mm_tstrb <= s_axis_s2mm_tkeep ; end generate GEN_S2MM_TKEEP_ENABLE1; GEN_S2MM_TKEEP_DISABLE1 : if C_ENABLE_S2MM_TKEEP = 0 generate begin sig_s2mm_tstrb <= (others => '1'); end generate GEN_S2MM_TKEEP_DISABLE1; -- S2MM Status Stream Output m_axis_s2mm_sts_tkeep <= sig_s2mm_sts_tstrb ; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_OMIT -- -- If Generate Description: -- Instantiate the MM2S OMIT Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_OMIT : if (C_INCLUDE_MM2S = 0) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_OMIT_WRAPPER -- -- Description: -- Read omit Wrapper Instance -- ------------------------------------------------------------ I_MM2S_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_omit_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr_int , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_FULL -- -- If Generate Description: -- Instantiate the MM2S Full Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_FULL : if (C_INCLUDE_MM2S = 1) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_FULL_WRAPPER -- -- Description: -- Read Full Wrapper Instance -- ------------------------------------------------------------ I_MM2S_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_full_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_INCLUDE_MM2S_GP_SF => C_MM2S_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_MM2S_TKEEP => C_ENABLE_MM2S_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr_int , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_MM2S_BASIC -- -- If Generate Description: -- Instantiate the MM2S Basic Wrapper -- -- ------------------------------------------------------------ GEN_MM2S_BASIC : if (C_INCLUDE_MM2S = 2) generate begin ------------------------------------------------------------ -- Instance: I_MM2S_BASIC_WRAPPER -- -- Description: -- Read Basic Wrapper Instance -- ------------------------------------------------------------ I_MM2S_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_mm2s_basic_wrap generic map ( C_INCLUDE_MM2S => C_INCLUDE_MM2S , C_MM2S_ARID => C_M_AXI_MM2S_ARID , C_MM2S_ID_WIDTH => C_M_AXI_MM2S_ID_WIDTH , C_MM2S_ADDR_WIDTH => C_M_AXI_MM2S_ADDR_WIDTH_int , C_MM2S_MDATA_WIDTH => C_M_AXI_MM2S_DATA_WIDTH , C_MM2S_SDATA_WIDTH => C_M_AXIS_MM2S_TDATA_WIDTH , C_INCLUDE_MM2S_STSFIFO => C_INCLUDE_MM2S_STSFIFO , C_MM2S_STSCMD_FIFO_DEPTH => MM2S_CMDSTS_FIFO_DEPTH , C_MM2S_STSCMD_IS_ASYNC => C_MM2S_STSCMD_IS_ASYNC , C_INCLUDE_MM2S_DRE => C_INCLUDE_MM2S_DRE , C_MM2S_BURST_SIZE => MM2S_MAX_BURST_BEATS , C_MM2S_BTT_USED => MM2S_CORRECTED_BTT_USED , C_MM2S_ADDR_PIPE_DEPTH => C_MM2S_ADDR_PIPE_DEPTH , C_TAG_WIDTH => MM2S_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( mm2s_aclk => m_axi_mm2s_aclk , mm2s_aresetn => m_axi_mm2s_aresetn , mm2s_halt => mm2s_halt , mm2s_halt_cmplt => mm2s_halt_cmplt , mm2s_err => mm2s_err , mm2s_cmdsts_awclk => m_axis_mm2s_cmdsts_aclk , mm2s_cmdsts_aresetn => m_axis_mm2s_cmdsts_aresetn , mm2s_cmd_wvalid => s_axis_mm2s_cmd_tvalid , mm2s_cmd_wready => s_axis_mm2s_cmd_tready , mm2s_cmd_wdata => s_axis_mm2s_cmd_tdata , mm2s_sts_wvalid => m_axis_mm2s_sts_tvalid , mm2s_sts_wready => m_axis_mm2s_sts_tready , mm2s_sts_wdata => m_axis_mm2s_sts_tdata , mm2s_sts_wstrb => sig_mm2s_sts_tstrb , mm2s_sts_wlast => m_axis_mm2s_sts_tlast , mm2s_allow_addr_req => mm2s_allow_addr_req , mm2s_addr_req_posted => mm2s_addr_req_posted , mm2s_rd_xfer_cmplt => mm2s_rd_xfer_cmplt , mm2s_arid => m_axi_mm2s_arid , mm2s_araddr => m_axi_mm2s_araddr_int , mm2s_arlen => m_axi_mm2s_arlen , mm2s_arsize => m_axi_mm2s_arsize , mm2s_arburst => m_axi_mm2s_arburst , mm2s_arprot => m_axi_mm2s_arprot , mm2s_arcache => m_axi_mm2s_arcache , mm2s_aruser => m_axi_mm2s_aruser , mm2s_arvalid => m_axi_mm2s_arvalid , mm2s_arready => m_axi_mm2s_arready , mm2s_rdata => m_axi_mm2s_rdata , mm2s_rresp => m_axi_mm2s_rresp , mm2s_rlast => m_axi_mm2s_rlast , mm2s_rvalid => m_axi_mm2s_rvalid , mm2s_rready => m_axi_mm2s_rready , mm2s_strm_wdata => m_axis_mm2s_tdata , mm2s_strm_wstrb => sig_mm2s_tstrb , mm2s_strm_wlast => m_axis_mm2s_tlast , mm2s_strm_wvalid => m_axis_mm2s_tvalid , mm2s_strm_wready => m_axis_mm2s_tready , mm2s_dbg_sel => mm2s_dbg_sel , mm2s_dbg_data => mm2s_dbg_data ); end generate GEN_MM2S_BASIC; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_OMIT -- -- If Generate Description: -- Instantiate the S2MM OMIT Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_OMIT : if (C_INCLUDE_S2MM = 0) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_OMIT_WRAPPER -- -- Description: -- Write Omit Wrapper Instance -- ------------------------------------------------------------ I_S2MM_OMIT_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_omit_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr_int , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_OMIT; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_FULL -- -- If Generate Description: -- Instantiate the S2MM FULL Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_FULL : if (C_INCLUDE_S2MM = 1) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_FULL_WRAPPER -- -- Description: -- Write Full Wrapper Instance -- ------------------------------------------------------------ I_S2MM_FULL_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_full_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_BTT_USED => S2MM_CORRECTED_BTT_USED , C_S2MM_SUPPORT_INDET_BTT => C_S2MM_SUPPORT_INDET_BTT , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_INCLUDE_S2MM_GP_SF => C_S2MM_INCLUDE_SF , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_S2MM_TKEEP => C_ENABLE_S2MM_TKEEP , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr_int , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_FULL; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_S2MM_BASIC -- -- If Generate Description: -- Instantiate the S2MM Basic Wrapper -- -- ------------------------------------------------------------ GEN_S2MM_BASIC : if (C_INCLUDE_S2MM = 2) generate begin ------------------------------------------------------------ -- Instance: I_S2MM_BASIC_WRAPPER -- -- Description: -- Write Basic Wrapper Instance -- ------------------------------------------------------------ I_S2MM_BASIC_WRAPPER : entity axi_datamover_v5_1_11.axi_datamover_s2mm_basic_wrap generic map ( C_INCLUDE_S2MM => C_INCLUDE_S2MM , C_S2MM_AWID => C_M_AXI_S2MM_AWID , C_S2MM_ID_WIDTH => C_M_AXI_S2MM_ID_WIDTH , C_S2MM_ADDR_WIDTH => C_M_AXI_S2MM_ADDR_WIDTH_int , C_S2MM_MDATA_WIDTH => C_M_AXI_S2MM_DATA_WIDTH , C_S2MM_SDATA_WIDTH => C_S_AXIS_S2MM_TDATA_WIDTH , C_INCLUDE_S2MM_STSFIFO => C_INCLUDE_S2MM_STSFIFO , C_S2MM_STSCMD_FIFO_DEPTH => S2MM_CMDSTS_FIFO_DEPTH , C_S2MM_STSCMD_IS_ASYNC => C_S2MM_STSCMD_IS_ASYNC , C_INCLUDE_S2MM_DRE => C_INCLUDE_S2MM_DRE , C_S2MM_BURST_SIZE => S2MM_MAX_BURST_BEATS , C_S2MM_ADDR_PIPE_DEPTH => C_S2MM_ADDR_PIPE_DEPTH , C_TAG_WIDTH => S2MM_TAG_WIDTH , C_ENABLE_CACHE_USER => C_ENABLE_CACHE_USER , C_ENABLE_SKID_BUF => C_ENABLE_SKID_BUF , C_MICRO_DMA => C_MICRO_DMA , C_FAMILY => C_FAMILY ) port map ( s2mm_aclk => m_axi_s2mm_aclk , s2mm_aresetn => m_axi_s2mm_aresetn , s2mm_halt => s2mm_halt , s2mm_halt_cmplt => s2mm_halt_cmplt , s2mm_err => s2mm_err , s2mm_cmdsts_awclk => m_axis_s2mm_cmdsts_awclk , s2mm_cmdsts_aresetn => m_axis_s2mm_cmdsts_aresetn , s2mm_cmd_wvalid => s_axis_s2mm_cmd_tvalid , s2mm_cmd_wready => s_axis_s2mm_cmd_tready , s2mm_cmd_wdata => s_axis_s2mm_cmd_tdata , s2mm_sts_wvalid => m_axis_s2mm_sts_tvalid , s2mm_sts_wready => m_axis_s2mm_sts_tready , s2mm_sts_wdata => m_axis_s2mm_sts_tdata , s2mm_sts_wstrb => sig_s2mm_sts_tstrb , s2mm_sts_wlast => m_axis_s2mm_sts_tlast , s2mm_allow_addr_req => s2mm_allow_addr_req , s2mm_addr_req_posted => s2mm_addr_req_posted , s2mm_wr_xfer_cmplt => s2mm_wr_xfer_cmplt , s2mm_ld_nxt_len => s2mm_ld_nxt_len , s2mm_wr_len => s2mm_wr_len , s2mm_awid => m_axi_s2mm_awid , s2mm_awaddr => m_axi_s2mm_awaddr_int , s2mm_awlen => m_axi_s2mm_awlen , s2mm_awsize => m_axi_s2mm_awsize , s2mm_awburst => m_axi_s2mm_awburst , s2mm_awprot => m_axi_s2mm_awprot , s2mm_awcache => m_axi_s2mm_awcache , s2mm_awuser => m_axi_s2mm_awuser , s2mm_awvalid => m_axi_s2mm_awvalid , s2mm_awready => m_axi_s2mm_awready , s2mm_wdata => m_axi_s2mm_wdata , s2mm_wstrb => m_axi_s2mm_wstrb , s2mm_wlast => m_axi_s2mm_wlast , s2mm_wvalid => m_axi_s2mm_wvalid , s2mm_wready => m_axi_s2mm_wready , s2mm_bresp => m_axi_s2mm_bresp , s2mm_bvalid => m_axi_s2mm_bvalid , s2mm_bready => m_axi_s2mm_bready , s2mm_strm_wdata => s_axis_s2mm_tdata , s2mm_strm_wstrb => sig_s2mm_tstrb , s2mm_strm_wlast => s_axis_s2mm_tlast , s2mm_strm_wvalid => s_axis_s2mm_tvalid , s2mm_strm_wready => s_axis_s2mm_tready , s2mm_dbg_sel => s2mm_dbg_sel , s2mm_dbg_data => s2mm_dbg_data ); end generate GEN_S2MM_BASIC; m_axi_mm2s_araddr <= m_axi_mm2s_araddr_int (C_M_AXI_MM2S_ADDR_WIDTH-1 downto 0); m_axi_s2mm_awaddr <= m_axi_s2mm_awaddr_int (C_M_AXI_S2MM_ADDR_WIDTH-1 downto 0); end implementation;

mit

Bjay1435/capstone

Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_mssai_skid_buf.vhd

5

24689

------------------------------------------------------------------------------- -- axi_datamover_mssai_skid_buf.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_mssai_skid_buf.vhd -- -- Description: -- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode that -- also incorporates the MS Strobe Asserted detection function needed by the -- module. This provides a register isolation of the MS asserted strobe index -- Scatter needed to improve Fmax. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; library axi_datamover_v5_1_11; Use axi_datamover_v5_1_11.axi_datamover_ms_strb_set; ------------------------------------------------------------------------------- entity axi_datamover_mssai_skid_buf is generic ( C_WDATA_WIDTH : INTEGER range 8 to 1024 := 32 ; -- Width of the Stream Data bus (in bits) C_INDEX_WIDTH : Integer range 1 to 8 := 2 -- Sets the width of the MS asserted strobe index output value ); port ( -- Clock and Reset Ports ----------------------- aclk : In std_logic ; -- arst : In std_logic ; -- ------------------------------------------------ -- Shutdown control (assert for 1 clk pulse) --- skid_stop : In std_logic ; -- ------------------------------------------------ -- Slave Side (Stream Data Input) ------------------------------------ s_valid : In std_logic ; -- s_ready : Out std_logic ; -- s_data : In std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- s_strb : In std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- s_last : In std_logic ; -- ---------------------------------------------------------------------- -- Master Side (Stream Data Output ----------------------------------- m_valid : Out std_logic ; -- m_ready : In std_logic ; -- m_data : Out std_logic_vector(C_WDATA_WIDTH-1 downto 0); -- m_strb : Out std_logic_vector((C_WDATA_WIDTH/8)-1 downto 0); -- m_last : Out std_logic ; -- -- m_mssa_index : Out std_logic_vector(C_INDEX_WIDTH-1 downto 0); -- m_strb_error : Out std_logic -- ---------------------------------------------------------------------- ); end entity axi_datamover_mssai_skid_buf; architecture implementation of axi_datamover_mssai_skid_buf is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Constant declarations ------------------------- Constant STROBE_WIDTH : integer := C_WDATA_WIDTH/8; -- Signals declarations ------------------------- Signal sig_reset_reg : std_logic := '0'; signal sig_spcl_s_ready_set : std_logic := '0'; signal sig_data_skid_reg : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_reg : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_reg : std_logic := '0'; signal sig_skid_reg_en : std_logic := '0'; signal sig_data_skid_mux_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_skid_mux_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_skid_mux_out : std_logic := '0'; signal sig_data_reg_out : std_logic_vector(C_WDATA_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_reg_out : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_last_reg_out : std_logic := '0'; signal sig_data_reg_out_en : std_logic := '0'; signal sig_m_valid_out : std_logic := '0'; signal sig_m_valid_dup : std_logic := '0'; signal sig_m_valid_comb : std_logic := '0'; signal sig_s_ready_out : std_logic := '0'; signal sig_s_ready_comb : std_logic := '0'; signal sig_stop_request : std_logic := '0'; signal sig_stopped : std_logic := '0'; signal sig_sready_stop : std_logic := '0'; signal sig_sready_early_stop : std_logic := '0'; signal sig_sready_stop_set : std_logic := '0'; signal sig_sready_stop_reg : std_logic := '0'; signal sig_mvalid_stop_reg : std_logic := '0'; signal sig_mvalid_stop : std_logic := '0'; signal sig_mvalid_early_stop : std_logic := '0'; signal sig_mvalid_stop_set : std_logic := '0'; signal sig_slast_with_stop : std_logic := '0'; signal sig_sstrb_stop_mask : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_sstrb_with_stop : std_logic_vector(STROBE_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_mssa_index_reg_out : std_logic_vector(C_INDEX_WIDTH-1 downto 0) := (others => '0'); signal sig_strb_error : std_logic := '0'; signal sig_strb_error_reg_out : std_logic := '0'; -- Fmax improvements signal sig_s_ready_dup : std_logic := '0'; signal sig_s_ready_dup2 : std_logic := '0'; signal sig_s_ready_dup3 : std_logic := '0'; signal sig_s_ready_dup4 : std_logic := '0'; signal sig_skid_mux_sel : std_logic := '0'; signal sig_skid_mux_sel2 : std_logic := '0'; signal sig_skid_mux_sel3 : std_logic := '0'; signal sig_skid_mux_sel4 : std_logic := '0'; -- Register duplication attribute assignments to control fanout -- on handshake output signals Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup2 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup3 : signal is "TRUE"; -- definition Attribute KEEP of sig_s_ready_dup4 : signal is "TRUE"; -- definition Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup2 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup3 : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup4 : signal is "no"; begin --(architecture implementation) m_valid <= sig_m_valid_out; s_ready <= sig_s_ready_out; m_strb <= sig_strb_reg_out; m_last <= sig_last_reg_out; m_data <= sig_data_reg_out; m_mssa_index <= sig_mssa_index_reg_out; m_strb_error <= sig_strb_error_reg_out; -- Special shutdown logic version of Slast. -- A halt request forces a tlast through the skig buffer sig_slast_with_stop <= s_last or sig_stop_request; sig_sstrb_with_stop <= s_strb or sig_sstrb_stop_mask; -- Assign the special s_ready FLOP set signal sig_spcl_s_ready_set <= sig_reset_reg; -- Generate the ouput register load enable control sig_data_reg_out_en <= m_ready or not(sig_m_valid_dup); -- Generate the skid input register load enable control sig_skid_reg_en <= sig_s_ready_dup; -- Generate the skid mux select control sig_skid_mux_sel2 <= not(sig_s_ready_dup2); sig_skid_mux_sel3 <= not(sig_s_ready_dup3); sig_skid_mux_sel4 <= not(sig_s_ready_dup4); -- Skid Mux sig_data_skid_mux_out <= sig_data_skid_reg When (sig_skid_mux_sel2 = '1') Else s_data; sig_strb_skid_mux_out <= sig_strb_skid_reg When (sig_skid_mux_sel3 = '1') Else sig_sstrb_with_stop; sig_last_skid_mux_out <= sig_last_skid_reg When (sig_skid_mux_sel4 = '1') Else sig_slast_with_stop; -- m_valid combinational logic sig_m_valid_comb <= s_valid or (sig_m_valid_dup and (not(sig_s_ready_dup) or not(m_ready))); -- s_ready combinational logic sig_s_ready_comb <= m_ready or (sig_s_ready_dup and (not(sig_m_valid_dup) or not(s_valid))); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: REG_THE_RST -- -- Process Description: -- Register input reset -- ------------------------------------------------------------- REG_THE_RST : process (aclk) begin if (aclk'event and aclk = '1') then sig_reset_reg <= arst; end if; end process REG_THE_RST; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: S_READY_FLOP -- -- Process Description: -- Registers s_ready handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- S_READY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_sready_stop = '1' or sig_sready_early_stop = '1') then -- Special stop condition sig_s_ready_out <= '0'; sig_s_ready_dup <= '0'; sig_s_ready_dup2 <= '0'; sig_s_ready_dup3 <= '0'; sig_s_ready_dup4 <= '0'; Elsif (sig_spcl_s_ready_set = '1') Then sig_s_ready_out <= '1'; sig_s_ready_dup <= '1'; sig_s_ready_dup2 <= '1'; sig_s_ready_dup3 <= '1'; sig_s_ready_dup4 <= '1'; else sig_s_ready_out <= sig_s_ready_comb; sig_s_ready_dup <= sig_s_ready_comb; sig_s_ready_dup2 <= sig_s_ready_comb; sig_s_ready_dup3 <= sig_s_ready_comb; sig_s_ready_dup4 <= sig_s_ready_comb; end if; end if; end process S_READY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: M_VALID_FLOP -- -- Process Description: -- Registers m_valid handshake signals per Skid Buffer -- Option 2 scheme -- ------------------------------------------------------------- M_VALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_spcl_s_ready_set = '1' or -- Fix from AXI DMA sig_mvalid_stop = '1' or sig_mvalid_stop_set = '1') then -- Special stop condition sig_m_valid_out <= '0'; sig_m_valid_dup <= '0'; else sig_m_valid_out <= sig_m_valid_comb; sig_m_valid_dup <= sig_m_valid_comb; end if; end if; end process M_VALID_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_DATA_REG -- -- Process Description: -- This process implements the skid register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- SKID_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_skid_reg_en = '1') then sig_data_skid_reg <= s_data; else null; -- hold current state end if; end if; end process SKID_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: SKID_CNTL_REG -- -- Process Description: -- This process implements the skid registers for the -- Skid Buffer control signals -- ------------------------------------------------------------- SKID_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_strb_skid_reg <= (others => '0'); sig_last_skid_reg <= '0'; elsif (sig_skid_reg_en = '1') then sig_strb_skid_reg <= sig_sstrb_with_stop; sig_last_skid_reg <= sig_slast_with_stop; else null; -- hold current state end if; end if; end process SKID_CNTL_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_DATA_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer Data signals. Note that reset has been removed -- to reduce route of resets for very wide data buses. -- ------------------------------------------------------------- OUTPUT_DATA_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (sig_data_reg_out_en = '1') then sig_data_reg_out <= sig_data_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_DATA_REG; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: OUTPUT_CNTL_REG -- -- Process Description: -- This process implements the output registers for the -- Skid Buffer Control signals. -- ------------------------------------------------------------- OUTPUT_CNTL_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_strb_reg_out <= (others => '0'); sig_last_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_strb_reg_out <= sig_strb_skid_mux_out; sig_last_reg_out <= sig_last_skid_mux_out; else null; -- hold current state end if; end if; end process OUTPUT_CNTL_REG; -------- Special Stop Logic -------------------------------------- sig_sready_stop <= sig_sready_stop_reg; sig_sready_early_stop <= skid_stop; -- deassert S_READY immediately sig_sready_stop_set <= sig_sready_early_stop; sig_mvalid_stop <= sig_mvalid_stop_reg; sig_mvalid_early_stop <= sig_m_valid_dup and m_ready and skid_stop; sig_mvalid_stop_set <= sig_mvalid_early_stop or (sig_stop_request and not(sig_m_valid_dup)) or (sig_m_valid_dup and m_ready and sig_stop_request); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_STOP_REQ_FLOP -- -- Process Description: -- This process implements the Stop request flop. It is a -- sample and hold register that can only be cleared by reset. -- ------------------------------------------------------------- IMP_STOP_REQ_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_stop_request <= '0'; sig_sstrb_stop_mask <= (others => '0'); elsif (skid_stop = '1') then sig_stop_request <= '1'; sig_sstrb_stop_mask <= (others => '1'); else null; -- hold current state end if; end if; end process IMP_STOP_REQ_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_SREADY_FLOP -- -- Process Description: -- This process implements the flag to clear the s_ready -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_SREADY_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_sready_stop_reg <= '0'; elsif (sig_sready_stop_set = '1') then sig_sready_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_SREADY_FLOP; ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_CLR_MVALID_FLOP -- -- Process Description: -- This process implements the flag to clear the m_valid -- flop at a stop condition. -- ------------------------------------------------------------- IMP_CLR_MVALID_FLOP : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1') then sig_mvalid_stop_reg <= '0'; elsif (sig_mvalid_stop_set = '1') then sig_mvalid_stop_reg <= '1'; else null; -- hold current state end if; end if; end process IMP_CLR_MVALID_FLOP; ---------------------------------------------------------------------------- -- Logic for the detection of the most significant asserted strobe bit and -- the formulation of the index of that strobe bit. ---------------------------------------------------------------------------- ------------------------------------------------------------ -- Instance: I_MSSAI_DETECTION -- -- Description: -- This module detects the most significant asserted strobe -- and outputs the bit index of the strobe. -- ------------------------------------------------------------ I_MSSAI_DETECTION : entity axi_datamover_v5_1_11.axi_datamover_ms_strb_set generic map ( C_STRB_WIDTH => STROBE_WIDTH , C_INDEX_WIDTH => C_INDEX_WIDTH ) port map ( -- Input Stream Strobes strbs_in => sig_strb_skid_mux_out , -- Index of the most significant strobe asserted ms_strb_index => sig_mssa_index_out , -- Output flag for a detected error associated Strobe assertions strb_error => sig_strb_error ); ------------------------------------------------------------- -- Synchronous Process with Sync Reset -- -- Label: IMP_MSSAI_REG -- -- Process Description: -- This process implements the output register for the -- Skid Buffer's MSSAI value and the strobe error bit -- that is needed by the Scatter module. -- ------------------------------------------------------------- IMP_MSSAI_REG : process (aclk) begin if (aclk'event and aclk = '1') then if (arst = '1' or sig_mvalid_stop_reg = '1') then sig_mssa_index_reg_out <= (others => '0'); sig_strb_error_reg_out <= '0'; elsif (sig_data_reg_out_en = '1') then sig_mssa_index_reg_out <= sig_mssa_index_out; sig_strb_error_reg_out <= sig_strb_error; else null; -- hold current state end if; end if; end process IMP_MSSAI_REG; end implementation;

mit

Bjay1435/capstone

Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_datamover_v5_1/hdl/src/vhdl/axi_datamover_wr_demux.vhd

18

75691

------------------------------------------------------------------------------- -- axi_datamover_wr_demux.vhd ------------------------------------------------------------------------------- -- -- ************************************************************************* -- -- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- -- ************************************************************************* -- ------------------------------------------------------------------------------- -- Filename: axi_datamover_wr_demux.vhd -- -- Description: -- This file implements the DataMover Master Write Strobe De-Multiplexer. -- This is needed when the native data width of the DataMover is narrower -- than the AXI4 Write Data Channel. -- -- -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ------------------------------------------------------------------------------- entity axi_datamover_wr_demux is generic ( C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5; -- Sets the width of the select control bus C_MMAP_DWIDTH : Integer range 32 to 1024 := 32; -- Indicates the width of the AXI4 Write Data Channel C_STREAM_DWIDTH : Integer range 8 to 1024 := 32 -- Indicates the native data width of the DataMover S2MM. If -- S2MM Store and Forward with upsizer is enabled, the width is -- the AXi4 Write Data Channel, else it is the S2MM Stream data width. ); port ( -- AXI MMap Data Channel Input -------------------------------------------- -- wstrb_in : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0); -- -- data input -- ---------------------------------------------------------------------------- -- AXI Master Stream ------------------------------------------------------ -- demux_wstrb_out : Out std_logic_vector((C_MMAP_DWIDTH/8)-1 downto 0); -- --De-Mux strb output -- ---------------------------------------------------------------------------- -- Command Calculator Interface -------------------------------------------- -- debeat_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) -- -- The next command start address LSbs to use for the read data -- -- mux (only used if Stream data width is less than the MMap Data -- -- Width). -- ---------------------------------------------------------------------------- ); end entity axi_datamover_wr_demux; architecture implementation of axi_datamover_wr_demux is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; -- Function Decalarations ------------------------------------------------- ------------------------------------------------------------------- -- Function -- -- Function Name: func_mux_sel_width -- -- Function Description: -- Calculates the number of needed bits for the Mux Select control -- based on the number of input channels to the mux. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_mux_sel_width (num_channels : integer) return integer is Variable var_sel_width : integer := 0; begin case num_channels is --when 2 => -- var_sel_width := 1; when 4 => var_sel_width := 2; when 8 => var_sel_width := 3; when 16 => var_sel_width := 4; when 32 => var_sel_width := 5; when 64 => var_sel_width := 6; when 128 => var_sel_width := 7; when others => var_sel_width := 1; end case; Return (var_sel_width); end function func_mux_sel_width; ------------------------------------------------------------------- -- Function -- -- Function Name: func_sel_ls_index -- -- Function Description: -- Calculates the LS index of the select field to rip from the -- input select bus. -- -- Note that the number of input mux channels are always a -- power of 2. -- ------------------------------------------------------------------- function func_sel_ls_index (stream_width : integer) return integer is Variable var_sel_ls_index : integer := 0; begin case stream_width is when 8 => var_sel_ls_index := 0; when 16 => var_sel_ls_index := 1; when 32 => var_sel_ls_index := 2; when 64 => var_sel_ls_index := 3; when 128 => var_sel_ls_index := 4; when 256 => var_sel_ls_index := 5; when 512 => var_sel_ls_index := 6; when others => -- assume 1024 bit width var_sel_ls_index := 7; end case; Return (var_sel_ls_index); end function func_sel_ls_index; -- Constant Decalarations ------------------------------------------------- Constant OMIT_DEMUX : boolean := (C_STREAM_DWIDTH = C_MMAP_DWIDTH); Constant INCLUDE_DEMUX : boolean := not(OMIT_DEMUX); Constant STREAM_WSTB_WIDTH : integer := C_STREAM_DWIDTH/8; Constant MMAP_WSTB_WIDTH : integer := C_MMAP_DWIDTH/8; Constant NUM_MUX_CHANNELS : integer := MMAP_WSTB_WIDTH/STREAM_WSTB_WIDTH; Constant MUX_SEL_WIDTH : integer := func_mux_sel_width(NUM_MUX_CHANNELS); Constant MUX_SEL_LS_INDEX : integer := func_sel_ls_index(C_STREAM_DWIDTH); -- Signal Declarations -------------------------------------------- signal sig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin --(architecture implementation) -- Assign the Output data port demux_wstrb_out <= sig_demux_wstrb_out; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_STRM_EQ_MMAP -- -- If Generate Description: -- This IfGen implements the case where the Stream Data Width is -- the same as the Memeory Map read Data width. -- -- ------------------------------------------------------------ GEN_STRM_EQ_MMAP : if (OMIT_DEMUX) generate begin sig_demux_wstrb_out <= wstrb_in; end generate GEN_STRM_EQ_MMAP; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_2XN -- -- If Generate Description: -- 2 channel demux case -- -- ------------------------------------------------------------ GEN_2XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 2) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_2XN_DEMUX -- -- Process Description: -- Implement the 2XN DeMux -- ------------------------------------------------------------- DO_2XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when others => -- 1 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in; end case; end process DO_2XN_DEMUX; end generate GEN_2XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_4XN -- -- If Generate Description: -- 4 channel demux case -- -- ------------------------------------------------------------ GEN_4XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 4) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_4XN_DEMUX -- -- Process Description: -- Implement the 4XN DeMux -- ------------------------------------------------------------- DO_4XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in; when others => -- 3 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in; end case; end process DO_4XN_DEMUX; end generate GEN_4XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_8XN -- -- If Generate Description: -- 8 channel demux case -- -- ------------------------------------------------------------ GEN_8XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 8) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_8XN_DEMUX -- -- Process Description: -- Implement the 8XN DeMux -- ------------------------------------------------------------- DO_8XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in; when others => -- 7 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in; end case; end process DO_8XN_DEMUX; end generate GEN_8XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_16XN -- -- If Generate Description: -- 16 channel demux case -- -- ------------------------------------------------------------ GEN_16XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 16) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_16XN_DEMUX -- -- Process Description: -- Implement the 16XN DeMux -- ------------------------------------------------------------- DO_16XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in; when others => -- 15 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in; end case; end process DO_16XN_DEMUX; end generate GEN_16XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_32XN -- -- If Generate Description: -- 32 channel demux case -- -- ------------------------------------------------------------ GEN_32XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 32) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_32XN_DEMUX -- -- Process Description: -- Implement the 32XN DeMux -- ------------------------------------------------------------- DO_32XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in; when 15 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in; when 16 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in; when 17 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in; when 18 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in; when 19 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in; when 20 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in; when 21 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in; when 22 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in; when 23 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in; when 24 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in; when 25 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in; when 26 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in; when 27 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in; when 28 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in; when 29 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in; when 30 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in; when others => -- 31 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in; end case; end process DO_32XN_DEMUX; end generate GEN_32XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_64XN -- -- If Generate Description: -- 64 channel demux case -- -- ------------------------------------------------------------ GEN_64XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 64) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_64XN_DEMUX -- -- Process Description: -- Implement the 32XN DeMux -- ------------------------------------------------------------- DO_64XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in; when 15 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in; when 16 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in; when 17 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in; when 18 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in; when 19 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in; when 20 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in; when 21 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in; when 22 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in; when 23 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in; when 24 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in; when 25 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in; when 26 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in; when 27 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in; when 28 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in; when 29 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in; when 30 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in; when 31 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in; when 32 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in; when 33 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in; when 34 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in; when 35 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in; when 36 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in; when 37 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in; when 38 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in; when 39 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in; when 40 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in; when 41 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in; when 42 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in; when 43 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in; when 44 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in; when 45 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in; when 46 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in; when 47 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in; when 48 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in; when 49 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in; when 50 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in; when 51 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in; when 52 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in; when 53 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in; when 54 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in; when 55 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in; when 56 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in; when 57 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in; when 58 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in; when 59 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in; when 60 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in; when 61 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in; when 62 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in; when others => -- 63 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in; end case; end process DO_64XN_DEMUX; end generate GEN_64XN; ------------------------------------------------------------ -- If Generate -- -- Label: GEN_128XN -- -- If Generate Description: -- 128 channel demux case -- -- ------------------------------------------------------------ GEN_128XN : if (INCLUDE_DEMUX and NUM_MUX_CHANNELS = 128) generate -- local signals signal sig_demux_sel_slice : std_logic_vector(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_unsgnd : unsigned(MUX_SEL_WIDTH-1 downto 0) := (others => '0'); signal sig_demux_sel_int : integer := 0; signal lsig_demux_sel_int_local : integer := 0; signal lsig_demux_wstrb_out : std_logic_vector(MMAP_WSTB_WIDTH-1 downto 0) := (others => '0'); begin -- Rip the Mux Select bits needed for the Mux case from the input select bus sig_demux_sel_slice <= debeat_saddr_lsb((MUX_SEL_LS_INDEX + MUX_SEL_WIDTH)-1 downto MUX_SEL_LS_INDEX); sig_demux_sel_unsgnd <= UNSIGNED(sig_demux_sel_slice); -- convert to unsigned sig_demux_sel_int <= TO_INTEGER(sig_demux_sel_unsgnd); -- convert to integer for MTI compile issue -- with locally static subtype error in each of the -- Mux IfGens lsig_demux_sel_int_local <= sig_demux_sel_int; sig_demux_wstrb_out <= lsig_demux_wstrb_out; ------------------------------------------------------------- -- Combinational Process -- -- Label: DO_128XN_DEMUX -- -- Process Description: -- Implement the 32XN DeMux -- ------------------------------------------------------------- DO_128XN_DEMUX : process (lsig_demux_sel_int_local, wstrb_in) begin -- Set default value lsig_demux_wstrb_out <= (others => '0'); case lsig_demux_sel_int_local is when 0 => lsig_demux_wstrb_out(STREAM_WSTB_WIDTH-1 downto 0) <= wstrb_in; when 1 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*2)-1 downto STREAM_WSTB_WIDTH*1) <= wstrb_in; when 2 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*3)-1 downto STREAM_WSTB_WIDTH*2) <= wstrb_in; when 3 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*4)-1 downto STREAM_WSTB_WIDTH*3) <= wstrb_in; when 4 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*5)-1 downto STREAM_WSTB_WIDTH*4) <= wstrb_in; when 5 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*6)-1 downto STREAM_WSTB_WIDTH*5) <= wstrb_in; when 6 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*7)-1 downto STREAM_WSTB_WIDTH*6) <= wstrb_in; when 7 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*8)-1 downto STREAM_WSTB_WIDTH*7) <= wstrb_in; when 8 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*9)-1 downto STREAM_WSTB_WIDTH*8) <= wstrb_in; when 9 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*10)-1 downto STREAM_WSTB_WIDTH*9) <= wstrb_in; when 10 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*11)-1 downto STREAM_WSTB_WIDTH*10) <= wstrb_in; when 11 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*12)-1 downto STREAM_WSTB_WIDTH*11) <= wstrb_in; when 12 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*13)-1 downto STREAM_WSTB_WIDTH*12) <= wstrb_in; when 13 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*14)-1 downto STREAM_WSTB_WIDTH*13) <= wstrb_in; when 14 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*15)-1 downto STREAM_WSTB_WIDTH*14) <= wstrb_in; when 15 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*16)-1 downto STREAM_WSTB_WIDTH*15) <= wstrb_in; when 16 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*17)-1 downto STREAM_WSTB_WIDTH*16) <= wstrb_in; when 17 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*18)-1 downto STREAM_WSTB_WIDTH*17) <= wstrb_in; when 18 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*19)-1 downto STREAM_WSTB_WIDTH*18) <= wstrb_in; when 19 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*20)-1 downto STREAM_WSTB_WIDTH*19) <= wstrb_in; when 20 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*21)-1 downto STREAM_WSTB_WIDTH*20) <= wstrb_in; when 21 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*22)-1 downto STREAM_WSTB_WIDTH*21) <= wstrb_in; when 22 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*23)-1 downto STREAM_WSTB_WIDTH*22) <= wstrb_in; when 23 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*24)-1 downto STREAM_WSTB_WIDTH*23) <= wstrb_in; when 24 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*25)-1 downto STREAM_WSTB_WIDTH*24) <= wstrb_in; when 25 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*26)-1 downto STREAM_WSTB_WIDTH*25) <= wstrb_in; when 26 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*27)-1 downto STREAM_WSTB_WIDTH*26) <= wstrb_in; when 27 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*28)-1 downto STREAM_WSTB_WIDTH*27) <= wstrb_in; when 28 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*29)-1 downto STREAM_WSTB_WIDTH*28) <= wstrb_in; when 29 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*30)-1 downto STREAM_WSTB_WIDTH*29) <= wstrb_in; when 30 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*31)-1 downto STREAM_WSTB_WIDTH*30) <= wstrb_in; when 31 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*32)-1 downto STREAM_WSTB_WIDTH*31) <= wstrb_in; when 32 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*33)-1 downto STREAM_WSTB_WIDTH*32) <= wstrb_in; when 33 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*34)-1 downto STREAM_WSTB_WIDTH*33) <= wstrb_in; when 34 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*35)-1 downto STREAM_WSTB_WIDTH*34) <= wstrb_in; when 35 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*36)-1 downto STREAM_WSTB_WIDTH*35) <= wstrb_in; when 36 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*37)-1 downto STREAM_WSTB_WIDTH*36) <= wstrb_in; when 37 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*38)-1 downto STREAM_WSTB_WIDTH*37) <= wstrb_in; when 38 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*39)-1 downto STREAM_WSTB_WIDTH*38) <= wstrb_in; when 39 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*40)-1 downto STREAM_WSTB_WIDTH*39) <= wstrb_in; when 40 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*41)-1 downto STREAM_WSTB_WIDTH*40) <= wstrb_in; when 41 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*42)-1 downto STREAM_WSTB_WIDTH*41) <= wstrb_in; when 42 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*43)-1 downto STREAM_WSTB_WIDTH*42) <= wstrb_in; when 43 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*44)-1 downto STREAM_WSTB_WIDTH*43) <= wstrb_in; when 44 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*45)-1 downto STREAM_WSTB_WIDTH*44) <= wstrb_in; when 45 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*46)-1 downto STREAM_WSTB_WIDTH*45) <= wstrb_in; when 46 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*47)-1 downto STREAM_WSTB_WIDTH*46) <= wstrb_in; when 47 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*48)-1 downto STREAM_WSTB_WIDTH*47) <= wstrb_in; when 48 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*49)-1 downto STREAM_WSTB_WIDTH*48) <= wstrb_in; when 49 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*50)-1 downto STREAM_WSTB_WIDTH*49) <= wstrb_in; when 50 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*51)-1 downto STREAM_WSTB_WIDTH*50) <= wstrb_in; when 51 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*52)-1 downto STREAM_WSTB_WIDTH*51) <= wstrb_in; when 52 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*53)-1 downto STREAM_WSTB_WIDTH*52) <= wstrb_in; when 53 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*54)-1 downto STREAM_WSTB_WIDTH*53) <= wstrb_in; when 54 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*55)-1 downto STREAM_WSTB_WIDTH*54) <= wstrb_in; when 55 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*56)-1 downto STREAM_WSTB_WIDTH*55) <= wstrb_in; when 56 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*57)-1 downto STREAM_WSTB_WIDTH*56) <= wstrb_in; when 57 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*58)-1 downto STREAM_WSTB_WIDTH*57) <= wstrb_in; when 58 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*59)-1 downto STREAM_WSTB_WIDTH*58) <= wstrb_in; when 59 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*60)-1 downto STREAM_WSTB_WIDTH*59) <= wstrb_in; when 60 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*61)-1 downto STREAM_WSTB_WIDTH*60) <= wstrb_in; when 61 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*62)-1 downto STREAM_WSTB_WIDTH*61) <= wstrb_in; when 62 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*63)-1 downto STREAM_WSTB_WIDTH*62) <= wstrb_in; when 63 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*64)-1 downto STREAM_WSTB_WIDTH*63) <= wstrb_in; when 64 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*65)-1 downto STREAM_WSTB_WIDTH*64) <= wstrb_in; when 65 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*66)-1 downto STREAM_WSTB_WIDTH*65) <= wstrb_in; when 66 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*67)-1 downto STREAM_WSTB_WIDTH*66) <= wstrb_in; when 67 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*68)-1 downto STREAM_WSTB_WIDTH*67) <= wstrb_in; when 68 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*69)-1 downto STREAM_WSTB_WIDTH*68) <= wstrb_in; when 69 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*70)-1 downto STREAM_WSTB_WIDTH*69) <= wstrb_in; when 70 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*71)-1 downto STREAM_WSTB_WIDTH*70) <= wstrb_in; when 71 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*72)-1 downto STREAM_WSTB_WIDTH*71) <= wstrb_in; when 72 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*73)-1 downto STREAM_WSTB_WIDTH*72) <= wstrb_in; when 73 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*74)-1 downto STREAM_WSTB_WIDTH*73) <= wstrb_in; when 74 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*75)-1 downto STREAM_WSTB_WIDTH*74) <= wstrb_in; when 75 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*76)-1 downto STREAM_WSTB_WIDTH*75) <= wstrb_in; when 76 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*77)-1 downto STREAM_WSTB_WIDTH*76) <= wstrb_in; when 77 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*78)-1 downto STREAM_WSTB_WIDTH*77) <= wstrb_in; when 78 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*79)-1 downto STREAM_WSTB_WIDTH*78) <= wstrb_in; when 79 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*80)-1 downto STREAM_WSTB_WIDTH*79) <= wstrb_in; when 80 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*81)-1 downto STREAM_WSTB_WIDTH*80) <= wstrb_in; when 81 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*82)-1 downto STREAM_WSTB_WIDTH*81) <= wstrb_in; when 82 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*83)-1 downto STREAM_WSTB_WIDTH*82) <= wstrb_in; when 83 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*84)-1 downto STREAM_WSTB_WIDTH*83) <= wstrb_in; when 84 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*85)-1 downto STREAM_WSTB_WIDTH*84) <= wstrb_in; when 85 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*86)-1 downto STREAM_WSTB_WIDTH*85) <= wstrb_in; when 86 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*87)-1 downto STREAM_WSTB_WIDTH*86) <= wstrb_in; when 87 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*88)-1 downto STREAM_WSTB_WIDTH*87) <= wstrb_in; when 88 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*89)-1 downto STREAM_WSTB_WIDTH*88) <= wstrb_in; when 89 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*90)-1 downto STREAM_WSTB_WIDTH*89) <= wstrb_in; when 90 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*91)-1 downto STREAM_WSTB_WIDTH*90) <= wstrb_in; when 91 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*92)-1 downto STREAM_WSTB_WIDTH*91) <= wstrb_in; when 92 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*93)-1 downto STREAM_WSTB_WIDTH*92) <= wstrb_in; when 93 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*94)-1 downto STREAM_WSTB_WIDTH*93) <= wstrb_in; when 94 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*95)-1 downto STREAM_WSTB_WIDTH*94) <= wstrb_in; when 95 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*96)-1 downto STREAM_WSTB_WIDTH*95) <= wstrb_in; when 96 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*97 )-1 downto STREAM_WSTB_WIDTH*96 ) <= wstrb_in; when 97 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*98 )-1 downto STREAM_WSTB_WIDTH*97 ) <= wstrb_in; when 98 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*99 )-1 downto STREAM_WSTB_WIDTH*98 ) <= wstrb_in; when 99 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*100)-1 downto STREAM_WSTB_WIDTH*99 ) <= wstrb_in; when 100 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*101)-1 downto STREAM_WSTB_WIDTH*100) <= wstrb_in; when 101 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*102)-1 downto STREAM_WSTB_WIDTH*101) <= wstrb_in; when 102 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*103)-1 downto STREAM_WSTB_WIDTH*102) <= wstrb_in; when 103 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*104)-1 downto STREAM_WSTB_WIDTH*103) <= wstrb_in; when 104 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*105)-1 downto STREAM_WSTB_WIDTH*104) <= wstrb_in; when 105 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*106)-1 downto STREAM_WSTB_WIDTH*105) <= wstrb_in; when 106 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*107)-1 downto STREAM_WSTB_WIDTH*106) <= wstrb_in; when 107 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*108)-1 downto STREAM_WSTB_WIDTH*107) <= wstrb_in; when 108 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*109)-1 downto STREAM_WSTB_WIDTH*108) <= wstrb_in; when 109 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*110)-1 downto STREAM_WSTB_WIDTH*109) <= wstrb_in; when 110 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*111)-1 downto STREAM_WSTB_WIDTH*110) <= wstrb_in; when 111 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*112)-1 downto STREAM_WSTB_WIDTH*111) <= wstrb_in; when 112 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*113)-1 downto STREAM_WSTB_WIDTH*112) <= wstrb_in; when 113 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*114)-1 downto STREAM_WSTB_WIDTH*113) <= wstrb_in; when 114 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*115)-1 downto STREAM_WSTB_WIDTH*114) <= wstrb_in; when 115 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*116)-1 downto STREAM_WSTB_WIDTH*115) <= wstrb_in; when 116 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*117)-1 downto STREAM_WSTB_WIDTH*116) <= wstrb_in; when 117 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*118)-1 downto STREAM_WSTB_WIDTH*117) <= wstrb_in; when 118 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*119)-1 downto STREAM_WSTB_WIDTH*118) <= wstrb_in; when 119 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*120)-1 downto STREAM_WSTB_WIDTH*119) <= wstrb_in; when 120 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*121)-1 downto STREAM_WSTB_WIDTH*120) <= wstrb_in; when 121 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*122)-1 downto STREAM_WSTB_WIDTH*121) <= wstrb_in; when 122 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*123)-1 downto STREAM_WSTB_WIDTH*122) <= wstrb_in; when 123 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*124)-1 downto STREAM_WSTB_WIDTH*123) <= wstrb_in; when 124 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*125)-1 downto STREAM_WSTB_WIDTH*124) <= wstrb_in; when 125 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*126)-1 downto STREAM_WSTB_WIDTH*125) <= wstrb_in; when 126 => lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*127)-1 downto STREAM_WSTB_WIDTH*126) <= wstrb_in; when others => -- 127 case lsig_demux_wstrb_out((STREAM_WSTB_WIDTH*128)-1 downto STREAM_WSTB_WIDTH*127) <= wstrb_in; end case; end process DO_128XN_DEMUX; end generate GEN_128XN; end implementation;

mit

Bjay1435/capstone

Geoff/Geoff.srcs/sources_1/bd/dma_loopback/ipshared/xilinx.com/axi_dma_v7_1/hdl/src/vhdl/axi_dma_rst_module.vhd

1

24263

-- (c) Copyright 2012 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. ------------------------------------------------------------ ------------------------------------------------------------------------------- -- Filename: axi_dma_rst_module.vhd -- Description: This entity is the top level reset module entity for the -- AXI VDMA core. -- -- VHDL-Standard: VHDL'93 ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_misc.all; library unisim; use unisim.vcomponents.all; library axi_dma_v7_1_10; use axi_dma_v7_1_10.axi_dma_pkg.all; library lib_cdc_v1_0_2; ------------------------------------------------------------------------------- entity axi_dma_rst_module is generic( C_INCLUDE_MM2S : integer range 0 to 1 := 1; -- Include or exclude MM2S primary data path -- 0 = Exclude MM2S primary data path -- 1 = Include MM2S primary data path C_INCLUDE_S2MM : integer range 0 to 1 := 1; -- Include or exclude S2MM primary data path -- 0 = Exclude S2MM primary data path -- 1 = Include S2MM primary data path C_INCLUDE_SG : integer range 0 to 1 := 1; -- Include or Exclude the Scatter Gather Engine -- 0 = Exclude SG Engine - Enables Simple DMA Mode -- 1 = Include SG Engine - Enables Scatter Gather Mode C_SG_INCLUDE_STSCNTRL_STRM : integer range 0 to 1 := 1; -- Include or Exclude AXI Status and AXI Control Streams -- 0 = Exclude Status and Control Streams -- 1 = Include Status and Control Streams C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0; -- Primary MM2S/S2MM sync/async mode -- 0 = synchronous mode - all clocks are synchronous -- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM) -- run asynchronous to AXI Lite, DMA Control, -- and SG. C_M_AXI_MM2S_ACLK_FREQ_HZ : integer := 100000000; -- Primary clock frequency in hertz C_M_AXI_S2MM_ACLK_FREQ_HZ : integer := 100000000; -- Primary clock frequency in hertz C_M_AXI_SG_ACLK_FREQ_HZ : integer := 100000000 -- Scatter Gather clock frequency in hertz ); port ( ----------------------------------------------------------------------- -- Clock Sources ----------------------------------------------------------------------- s_axi_lite_aclk : in std_logic ; m_axi_sg_aclk : in std_logic ; -- m_axi_mm2s_aclk : in std_logic ; -- m_axi_s2mm_aclk : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- Hard Reset -- ----------------------------------------------------------------------- -- axi_resetn : in std_logic ; -- ----------------------------------------------------------------------- -- -- Soft Reset -- ----------------------------------------------------------------------- -- soft_reset : in std_logic ; -- soft_reset_clr : out std_logic := '0' ; -- -- ----------------------------------------------------------------------- -- -- MM2S Soft Reset Support -- ----------------------------------------------------------------------- -- mm2s_all_idle : in std_logic ; -- mm2s_stop : in std_logic ; -- mm2s_halt : out std_logic := '0' ; -- mm2s_halt_cmplt : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- S2MM Soft Reset Support -- ----------------------------------------------------------------------- -- s2mm_all_idle : in std_logic ; -- s2mm_stop : in std_logic ; -- s2mm_halt : out std_logic := '0' ; -- s2mm_halt_cmplt : in std_logic ; -- -- ----------------------------------------------------------------------- -- -- MM2S Distributed Reset Out -- ----------------------------------------------------------------------- -- -- AXI DataMover Primary Reset (Raw) -- dm_mm2s_prmry_resetn : out std_logic := '1' ; -- -- AXI DataMover Secondary Reset (Raw) -- dm_mm2s_scndry_resetn : out std_logic := '1' ; -- AXI Stream Primary Reset Outputs -- mm2s_prmry_reset_out_n : out std_logic := '1' ; -- -- AXI Stream Control Reset Outputs -- mm2s_cntrl_reset_out_n : out std_logic := '1' ; -- -- AXI Secondary reset mm2s_scndry_resetn : out std_logic := '1' ; -- -- AXI Upsizer and Line Buffer -- mm2s_prmry_resetn : out std_logic := '1' ; -- -- -- ----------------------------------------------------------------------- -- -- S2MM Distributed Reset Out -- ----------------------------------------------------------------------- -- -- AXI DataMover Primary Reset (Raw) -- dm_s2mm_prmry_resetn : out std_logic := '1' ; -- -- AXI DataMover Secondary Reset (Raw) -- dm_s2mm_scndry_resetn : out std_logic := '1' ; -- AXI Stream Primary Reset Outputs -- s2mm_prmry_reset_out_n : out std_logic := '1' ; -- -- AXI Stream Control Reset Outputs -- s2mm_sts_reset_out_n : out std_logic := '1' ; -- -- AXI Secondary reset s2mm_scndry_resetn : out std_logic := '1' ; -- -- AXI Upsizer and Line Buffer -- s2mm_prmry_resetn : out std_logic := '1' ; -- ----------------------------------------------------------------------- -- -- Scatter Gather Distributed Reset Out ----------------------------------------------------------------------- -- -- AXI Scatter Gather Reset Out m_axi_sg_aresetn : out std_logic := '1' ; -- -- AXI Scatter Gather Datamover Reset Out dm_m_axi_sg_aresetn : out std_logic := '1' ; -- ----------------------------------------------------------------------- -- -- Hard Reset Out -- ----------------------------------------------------------------------- -- m_axi_sg_hrdresetn : out std_logic := '1' ; -- s_axi_lite_resetn : out std_logic := '1' -- ); Attribute KEEP : string; -- declaration Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration Attribute KEEP of s_axi_lite_resetn : signal is "TRUE"; Attribute KEEP of m_axi_sg_hrdresetn : signal is "TRUE"; Attribute EQUIVALENT_REGISTER_REMOVAL of s_axi_lite_resetn : signal is "no"; Attribute EQUIVALENT_REGISTER_REMOVAL of m_axi_sg_hrdresetn : signal is "no"; end axi_dma_rst_module; ------------------------------------------------------------------------------- -- Architecture ------------------------------------------------------------------------------- architecture implementation of axi_dma_rst_module is attribute DowngradeIPIdentifiedWarnings: string; attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes"; ------------------------------------------------------------------------------- -- Functions ------------------------------------------------------------------------------- -- No Functions Declared ------------------------------------------------------------------------------- -- Constants Declarations ------------------------------------------------------------------------------- -- No Constants Declared ------------------------------------------------------------------------------- -- Signal / Type Declarations ------------------------------------------------------------------------------- ATTRIBUTE async_reg : STRING; signal hrd_resetn_i_cdc_tig : std_logic := '1'; signal hrd_resetn_i_d1_cdc_tig : std_logic := '1'; --ATTRIBUTE async_reg OF hrd_resetn_i_cdc_tig : SIGNAL IS "true"; --ATTRIBUTE async_reg OF hrd_resetn_i_d1_cdc_tig : SIGNAL IS "true"; -- Soft reset support signal mm2s_soft_reset_clr : std_logic := '0'; signal s2mm_soft_reset_clr : std_logic := '0'; signal soft_reset_clr_i : std_logic := '0'; signal mm2s_soft_reset_done : std_logic := '0'; signal s2mm_soft_reset_done : std_logic := '0'; signal mm2s_scndry_resetn_i : std_logic := '0'; signal s2mm_scndry_resetn_i : std_logic := '0'; signal dm_mm2s_scndry_resetn_i : std_logic := '0'; signal dm_s2mm_scndry_resetn_i : std_logic := '0'; signal sg_hard_reset : std_logic := '0'; ------------------------------------------------------------------------------- -- Begin architecture logic ------------------------------------------------------------------------------- begin -- Register hard reset in REG_HRD_RST : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => axi_resetn, prmry_vect_in => (others => '0'), scndry_aclk => m_axi_sg_aclk, scndry_resetn => '0', scndry_out => sg_hard_reset, scndry_vect_out => open ); m_axi_sg_hrdresetn <= sg_hard_reset; --REG_HRD_RST : process(m_axi_sg_aclk) -- begin -- if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then -- hrd_resetn_i_cdc_tig <= axi_resetn; -- m_axi_sg_hrdresetn <= hrd_resetn_i_cdc_tig; -- end if; -- end process REG_HRD_RST; -- Regsiter hard reset out for axi lite interface REG_HRD_RST_OUT : entity lib_cdc_v1_0_2.cdc_sync generic map ( C_CDC_TYPE => 1, C_RESET_STATE => 0, C_SINGLE_BIT => 1, C_VECTOR_WIDTH => 32, C_MTBF_STAGES => MTBF_STAGES ) port map ( prmry_aclk => '0', prmry_resetn => '0', prmry_in => axi_resetn, prmry_vect_in => (others => '0'), scndry_aclk => s_axi_lite_aclk, scndry_resetn => '0', scndry_out => s_axi_lite_resetn, scndry_vect_out => open ); --REG_HRD_RST_OUT : process(s_axi_lite_aclk) -- begin -- if(s_axi_lite_aclk'EVENT and s_axi_lite_aclk = '1')then -- hrd_resetn_i_d1_cdc_tig <= hrd_resetn_i_cdc_tig; -- s_axi_lite_resetn <= hrd_resetn_i_d1_cdc_tig; -- end if; -- end process REG_HRD_RST_OUT; dm_mm2s_scndry_resetn <= dm_mm2s_scndry_resetn_i; dm_s2mm_scndry_resetn <= dm_s2mm_scndry_resetn_i; -- mm2s channel included therefore map secondary resets to -- from mm2s reset module to scatter gather interface (default) MAP_SG_FOR_BOTH : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 1 generate begin -- both must be low before sg reset is asserted. m_axi_sg_aresetn <= mm2s_scndry_resetn_i or s2mm_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i or dm_s2mm_scndry_resetn_i; end generate MAP_SG_FOR_BOTH; -- Only s2mm channel included therefore map secondary resets to -- from s2mm reset module to scatter gather interface MAP_SG_FOR_S2MM : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 1 generate begin m_axi_sg_aresetn <= s2mm_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_s2mm_scndry_resetn_i; end generate MAP_SG_FOR_S2MM; -- Only mm2s channel included therefore map secondary resets to -- from mm2s reset module to scatter gather interface MAP_SG_FOR_MM2S : if C_INCLUDE_MM2S = 1 and C_INCLUDE_S2MM = 0 generate begin m_axi_sg_aresetn <= mm2s_scndry_resetn_i; dm_m_axi_sg_aresetn <= dm_mm2s_scndry_resetn_i; end generate MAP_SG_FOR_MM2S; -- Invalid configuration for axi dma - simply here for completeness MAP_NO_SG : if C_INCLUDE_MM2S = 0 and C_INCLUDE_S2MM = 0 generate begin m_axi_sg_aresetn <= '1'; dm_m_axi_sg_aresetn <= '1'; end generate MAP_NO_SG; s2mm_scndry_resetn <= s2mm_scndry_resetn_i; mm2s_scndry_resetn <= mm2s_scndry_resetn_i; -- Generate MM2S reset signals GEN_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 1 generate begin RESET_I : entity axi_dma_v7_1_10.axi_dma_reset generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_MM2S_ACLK_FREQ_HZ , C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_INCLUDE_SG => C_INCLUDE_SG ) port map( -- Clock Sources m_axi_sg_aclk => m_axi_sg_aclk , axi_prmry_aclk => m_axi_mm2s_aclk , -- Hard Reset axi_resetn => sg_hard_reset , -- Soft Reset soft_reset => soft_reset , soft_reset_clr => mm2s_soft_reset_clr , soft_reset_done => soft_reset_clr_i , all_idle => mm2s_all_idle , stop => mm2s_stop , halt => mm2s_halt , halt_cmplt => mm2s_halt_cmplt , -- Secondary Reset scndry_resetn => mm2s_scndry_resetn_i , -- AXI Upsizer and Line Buffer prmry_resetn => mm2s_prmry_resetn , -- AXI DataMover Primary Reset (Raw) dm_prmry_resetn => dm_mm2s_prmry_resetn , -- AXI DataMover Secondary Reset (Raw) dm_scndry_resetn => dm_mm2s_scndry_resetn_i , -- AXI Stream Primary Reset Outputs prmry_reset_out_n => mm2s_prmry_reset_out_n , -- AXI Stream Alternate Reset Outputs altrnt_reset_out_n => mm2s_cntrl_reset_out_n ); -- Sample an hold mm2s soft reset done to use in -- combined reset done to DMACR MM2S_SOFT_RST_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then mm2s_soft_reset_done <= '0'; elsif(mm2s_soft_reset_clr = '1')then mm2s_soft_reset_done <= '1'; end if; end if; end process MM2S_SOFT_RST_DONE; end generate GEN_RESET_FOR_MM2S; -- No MM2S therefore tie off mm2s reset signals GEN_NO_RESET_FOR_MM2S : if C_INCLUDE_MM2S = 0 generate begin mm2s_prmry_reset_out_n <= '1'; mm2s_cntrl_reset_out_n <= '1'; dm_mm2s_scndry_resetn_i <= '1'; dm_mm2s_prmry_resetn <= '1'; mm2s_prmry_resetn <= '1'; mm2s_scndry_resetn_i <= '1'; mm2s_halt <= '0'; mm2s_soft_reset_clr <= '0'; mm2s_soft_reset_done <= '1'; end generate GEN_NO_RESET_FOR_MM2S; -- Generate S2MM reset signals GEN_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 1 generate begin RESET_I : entity axi_dma_v7_1_10.axi_dma_reset generic map( C_PRMRY_IS_ACLK_ASYNC => C_PRMRY_IS_ACLK_ASYNC , C_AXI_PRMRY_ACLK_FREQ_HZ => C_M_AXI_S2MM_ACLK_FREQ_HZ , C_AXI_SCNDRY_ACLK_FREQ_HZ => C_M_AXI_SG_ACLK_FREQ_HZ , C_SG_INCLUDE_STSCNTRL_STRM => C_SG_INCLUDE_STSCNTRL_STRM , C_INCLUDE_SG => C_INCLUDE_SG ) port map( -- Clock Sources m_axi_sg_aclk => m_axi_sg_aclk , axi_prmry_aclk => m_axi_s2mm_aclk , -- Hard Reset axi_resetn => sg_hard_reset , -- Soft Reset soft_reset => soft_reset , soft_reset_clr => s2mm_soft_reset_clr , soft_reset_done => soft_reset_clr_i , all_idle => s2mm_all_idle , stop => s2mm_stop , halt => s2mm_halt , halt_cmplt => s2mm_halt_cmplt , -- Secondary Reset scndry_resetn => s2mm_scndry_resetn_i , -- AXI Upsizer and Line Buffer prmry_resetn => s2mm_prmry_resetn , -- AXI DataMover Primary Reset (Raw) dm_prmry_resetn => dm_s2mm_prmry_resetn , -- AXI DataMover Secondary Reset (Raw) dm_scndry_resetn => dm_s2mm_scndry_resetn_i , -- AXI Stream Primary Reset Outputs prmry_reset_out_n => s2mm_prmry_reset_out_n , -- AXI Stream Alternate Reset Outputs altrnt_reset_out_n => s2mm_sts_reset_out_n ); -- Sample an hold s2mm soft reset done to use in -- combined reset done to DMACR S2MM_SOFT_RST_DONE : process(m_axi_sg_aclk) begin if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then if(sg_hard_reset = '0' or soft_reset_clr_i = '1')then s2mm_soft_reset_done <= '0'; elsif(s2mm_soft_reset_clr = '1')then s2mm_soft_reset_done <= '1'; end if; end if; end process S2MM_SOFT_RST_DONE; end generate GEN_RESET_FOR_S2MM; -- No SsMM therefore tie off mm2s reset signals GEN_NO_RESET_FOR_S2MM : if C_INCLUDE_S2MM = 0 generate begin s2mm_prmry_reset_out_n <= '1'; dm_s2mm_scndry_resetn_i <= '1'; dm_s2mm_prmry_resetn <= '1'; s2mm_prmry_resetn <= '1'; s2mm_scndry_resetn_i <= '1'; s2mm_halt <= '0'; s2mm_soft_reset_clr <= '0'; s2mm_soft_reset_done <= '1'; end generate GEN_NO_RESET_FOR_S2MM; -- When both mm2s and s2mm are done then drive soft reset clear and -- also clear s_h registers above soft_reset_clr_i <= s2mm_soft_reset_done and mm2s_soft_reset_done; soft_reset_clr <= soft_reset_clr_i; end implementation;

mit

xiadz/oscilloscope

src/screen_position_gen.vhd

1

4551

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.types.all; entity screen_position_gen is port ( -- inputs nrst : in std_logic; clk108 : in std_logic; vblank : in std_logic; in_line_change : in std_logic; in_page_change : in std_logic; in_column : in integer range 0 to 1279; in_column_change : in std_logic; -- outputs segment : out integer range 0 to 15; segment_change : out std_logic; subsegment : out integer range 0 to 3; subsegment_change : out std_logic; line : out integer range 0 to 15; out_line_change : out std_logic; out_column : out integer range 0 to 1279; out_column_mod_8 : out integer range 0 to 7; out_column_div_8 : out integer range 0 to 159; out_column_change : out std_logic; out_page_change : out std_logic; active_pixgen_source : out PIXGEN_SOURCE_T ); end screen_position_gen; architecture behavioral of screen_position_gen is signal internal_segment : integer range 0 to 15; signal internal_subsegment : integer range 0 to 3; signal internal_line : integer range 0 to 15; signal next_segment : integer range 0 to 15; signal next_subsegment : integer range 0 to 3; signal next_line : integer range 0 to 15; begin segment <= internal_segment; subsegment <= internal_subsegment; line <= internal_line; -- This process calculates next_line, next_subsegment, next_segment signals process (in_line_change, in_page_change, internal_segment, internal_subsegment, internal_line) is begin if in_page_change = '1' then next_line <= 0; next_subsegment <= 0; next_segment <= 0; else if in_line_change = '1' then if internal_line = 15 then next_line <= 0; if internal_subsegment = 3 then next_subsegment <= 0; if internal_segment = 15 then next_segment <= 0; else next_segment <= internal_segment + 1; end if; else next_subsegment <= internal_subsegment + 1; next_segment <= internal_segment; end if; else next_line <= internal_line + 1; next_subsegment <= internal_subsegment; next_segment <= internal_segment; end if; else next_line <= internal_line; next_subsegment <= internal_subsegment; next_segment <= internal_segment; end if; end if; end process; -- This proces generates all output signals process (clk108, nrst) is begin if nrst = '0' then elsif rising_edge (clk108) then internal_line <= next_line; internal_subsegment <= next_subsegment; internal_segment <= next_segment; out_line_change <= in_line_change; if internal_subsegment /= next_subsegment then subsegment_change <= '1'; else subsegment_change <= '0'; end if; if internal_segment /= next_segment then segment_change <= '1'; else segment_change <= '0'; end if; out_column <= in_column; out_column_mod_8 <= in_column mod 8; out_column_div_8 <= in_column / 8; out_column_change <= in_column_change; out_page_change <= in_page_change; if vblank = '1' then active_pixgen_source <= BLANK_PIXGEN_T; elsif next_segment < 14 then if next_subsegment /= 3 then active_pixgen_source <= TRACE_PIXGEN_T; else active_pixgen_source <= TIME_BASE_PIXGEN_T; end if; else active_pixgen_source <= SETTINGS_PIXGEN_T; end if; end if; end process; end architecture behavioral;

mit

xiadz/oscilloscope

src/clock_divider.vhd

1

965

-- A simple frequency divider library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity divider is -- 1 -- f_out = f_in ----- -- 2 * n generic (n: natural range 1 to 2147483647); port ( clk_in : in std_logic; nrst : in std_logic; clk_out : out std_logic ); end entity divider; architecture counter of divider is signal cnt : integer range 0 to n - 1; signal internal_clk_out : std_logic := '0'; begin clk_out <= internal_clk_out; process (clk_in, nrst) begin if nrst = '0' then cnt <= 0; internal_clk_out <= '0'; elsif rising_edge (clk_in) then if cnt = n - 1 then cnt <= 0; internal_clk_out <= not internal_clk_out; else cnt <= cnt + 1; end if; end if; end process; end architecture counter;

mit

xiadz/oscilloscope

src/bits_aggregator.vhd

1

3657

---------------------------------------------------------------------------------- -- Author: Osowski Marcin -- Create Date: 19:43:33 05/27/2011 ---------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity bits_aggregator is port ( -- Inputs nrst : in std_logic; clk108 : in std_logic; flush_and_return_to_zero : in std_logic; write_enable : in std_logic; red_value : in std_logic; green_value : in std_logic; blue_value : in std_logic; -- Outputs wea : out std_logic; addra : out std_logic_vector (12 downto 0); dina : out std_logic_vector (8 downto 0) ); end bits_aggregator; architecture behavioral of bits_aggregator is signal mod3 : integer range 0 to 2 := 0; signal next_mod3 : integer range 0 to 2; signal mod3_overflow : std_logic := '0'; signal address : std_logic_vector (12 downto 0) := (others => '0'); signal next_address : std_logic_vector (12 downto 0); signal row_buffer : std_logic_vector (5 downto 0) := (others => '0'); signal next_row : std_logic_vector (8 downto 0) := (others => '0'); begin -- Process calculates next_mod3, mod3_overflow, next_address process (mod3, address) is begin if mod3 = 2 then next_mod3 <= 0; mod3_overflow <= '1'; next_address <= address + 1; else next_mod3 <= mod3 + 1; mod3_overflow <= '0'; next_address <= address; end if; end process; -- Process calculates next_row process (mod3, row_buffer, red_value, green_value, blue_value) is begin if mod3 = 0 then next_row (0) <= red_value; next_row (1) <= green_value; next_row (2) <= blue_value; next_row (8 downto 3) <= (others => '0'); elsif mod3 = 1 then next_row (2 downto 0) <= row_buffer (2 downto 0); next_row (3) <= red_value; next_row (4) <= green_value; next_row (5) <= blue_value; next_row (8 downto 6) <= (others => '0'); else next_row (5 downto 0) <= row_buffer (5 downto 0); next_row (6) <= red_value; next_row (7) <= green_value; next_row (8) <= blue_value; end if; end process; process (nrst, clk108) is begin if nrst = '0' then mod3 <= 0; address <= (others => '0'); wea <= '0'; addra <= (others => '0'); dina <= (others => '0'); elsif rising_edge (clk108) then if flush_and_return_to_zero = '1' then mod3 <= 0; address <= (others => '0'); row_buffer <= (others => '0'); addra <= address; dina <= next_row; wea <= '1'; elsif write_enable = '1' then mod3 <= next_mod3; address <= next_address; row_buffer <= next_row (5 downto 0); if mod3_overflow = '1' then addra <= address; dina <= next_row; wea <= '1'; else wea <= '0'; end if; else wea <= '0'; end if; end if; end process; end behavioral;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_arccospi_s5.vhd

10

713163

----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_arccospi_s5 -- VHDL created on Thu Feb 28 17:21:22 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_arccospi_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_arccospi_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstBiasM2_uid6_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal ooPi_uid9_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstBias_uid22_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q : std_logic_vector (12 downto 0); signal pi_uid94_acosX_uid8_fpArccosPiTest_q : std_logic_vector (27 downto 0); signal path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal pi2_uid111_acosX_uid8_fpArccosPiTest_q : std_logic_vector (26 downto 0); signal fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (9 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (10 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector (23 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid186_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (47 downto 0); signal roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (15 downto 0); signal rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (3 downto 0); signal rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (11 downto 0); signal rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (1 downto 0); signal rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (10 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector (23 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (47 downto 0); signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 : std_logic_vector (35 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr : SIGNED (36 downto 0); signal prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q : std_logic_vector (35 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b : std_logic_vector (23 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 : std_logic_vector (38 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr : SIGNED (39 downto 0); signal prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q : std_logic_vector (38 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0); signal prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0); signal prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid406_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0); signal memoryC1_uid407_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid408_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_reset0 : std_logic; signal memoryC0_uid550_arccosXO2TabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid550_arccosXO2TabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_reset0 : std_logic; signal memoryC1_uid551_arccosXO2TabGen_lutmem_ia : std_logic_vector (21 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_iq : std_logic_vector (21 downto 0); signal memoryC1_uid551_arccosXO2TabGen_lutmem_q : std_logic_vector (21 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_reset0 : std_logic; signal memoryC2_uid552_arccosXO2TabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid552_arccosXO2TabGen_lutmem_q : std_logic_vector (11 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid566_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0); signal memoryC0_uid566_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid567_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid567_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid568_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid568_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0); signal reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (2 downto 0); signal reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (36 downto 0); signal reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (36 downto 0); signal reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (36 downto 0); signal reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q : std_logic_vector (36 downto 0); signal reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (35 downto 0); signal reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (31 downto 0); signal reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (15 downto 0); signal reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (3 downto 0); signal reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (34 downto 0); signal reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (0 downto 0); signal reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (5 downto 0); signal reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (22 downto 0); signal reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0); signal reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (3 downto 0); signal reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0); signal reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0); signal reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0); signal reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (7 downto 0); signal reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0); signal reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q : std_logic_vector (23 downto 0); signal reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0); signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0); signal reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0); signal reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (22 downto 0); signal reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (23 downto 0); signal reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (11 downto 0); signal reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (2 downto 0); signal reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (22 downto 0); signal reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (23 downto 0); signal reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q : std_logic_vector (23 downto 0); signal reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (26 downto 0); signal reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q : std_logic_vector (11 downto 0); signal reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q : std_logic_vector (23 downto 0); signal reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q : std_logic_vector (27 downto 0); signal reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (26 downto 0); signal reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (22 downto 0); signal reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (22 downto 0); signal reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q : std_logic_vector (7 downto 0); signal reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (23 downto 0); signal reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (11 downto 0); signal reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q : std_logic_vector (2 downto 0); signal reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q : std_logic_vector (22 downto 0); signal reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q : std_logic_vector (7 downto 0); signal ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (23 downto 0); signal ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (31 downto 0); signal ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (22 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (1 downto 0); signal ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (7 downto 0); signal ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (8 downto 0); signal ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q : std_logic_vector (22 downto 0); signal ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (5 downto 0); signal ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (22 downto 0); signal ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (1 downto 0); signal ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (8 downto 0); signal ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q : std_logic_vector (22 downto 0); signal ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q : std_logic_vector (22 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q : std_logic_vector (7 downto 0); signal ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q : std_logic_vector (0 downto 0); signal ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q : std_logic_vector (11 downto 0); signal ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q : std_logic_vector (0 downto 0); signal ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q : std_logic_vector (7 downto 0); signal ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 : std_logic; signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i : unsigned(5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq : std_logic; signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q : std_logic_vector (6 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : signal is true; signal ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q : std_logic_vector (31 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic; signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i : unsigned(5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq : std_logic; signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q : std_logic_vector (6 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true; signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0 : std_logic; signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q : signal is true; signal ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q : signal is true; signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq : std_logic; signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true; signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q : signal is true; signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q : signal is true; signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q : signal is true; signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q : signal is true; signal ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0); signal ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 : std_logic; signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q : std_logic_vector (22 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq : std_logic; signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : signal is true; signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 : std_logic; signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q : signal is true; signal pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q : std_logic_vector (35 downto 0); signal pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q : std_logic_vector (27 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c : std_logic_vector (0 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal excSelBits_uid137_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal expX_uid15_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid15_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid16_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid16_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal singX_uid17_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal singX_uid17_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid38_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid38_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid38_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_a : std_logic_vector(10 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_b : std_logic_vector(10 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_o : std_logic_vector (10 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal expGT0_uid45_acosX_uid8_fpArccosPiTest_c : std_logic_vector (0 downto 0); signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expEQ0_uid46_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_a : std_logic_vector(11 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_b : std_logic_vector(11 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_o : std_logic_vector (11 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin : std_logic_vector (0 downto 0); signal shiftValue_uid52_acosX_uid8_fpArccosPiTest_n : std_logic_vector (0 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_a : std_logic_vector(36 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_b : std_logic_vector(36 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_o : std_logic_vector (36 downto 0); signal oMy_uid63_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expL_uid67_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal srVal_uid76_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a : std_logic_vector(28 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b : std_logic_vector(28 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o : std_logic_vector (28 downto 0); signal path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q : std_logic_vector (28 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_a : std_logic_vector(28 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_b : std_logic_vector(28 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_o : std_logic_vector (28 downto 0); signal path2Diff_uid112_acosX_uid8_fpArccosPiTest_q : std_logic_vector (28 downto 0); signal expRCalc_uid134_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRCalc_uid134_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (35 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (35 downto 0); signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q : std_logic_vector(0 downto 0); signal fracOOPi_uid10_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracOOPi_uid10_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal piF_uid128_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal piF_uid128_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in : std_logic_vector (35 downto 0); signal prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0); signal prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b : std_logic_vector (24 downto 0); signal prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in : std_logic_vector (15 downto 0); signal sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b : std_logic_vector (14 downto 0); signal fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal R_uid242_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (15 downto 0); signal FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a : std_logic_vector(6 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b : std_logic_vector(6 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a : std_logic_vector(6 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b : std_logic_vector(6 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a : std_logic_vector(5 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b : std_logic_vector(5 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b : std_logic_vector(0 downto 0); signal ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q : std_logic_vector(0 downto 0); signal oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in : std_logic_vector (5 downto 0); signal fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b : std_logic_vector (5 downto 0); signal l_uid65_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal l_uid65_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0); signal expLRange_uid69_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal expLRange_uid69_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal srValRange_uid77_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal srValRange_uid77_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0); signal path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in : std_logic_vector (27 downto 0); signal path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0); signal path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal normBit_uid114_acosX_uid8_fpArccosPiTest_in : std_logic_vector (27 downto 0); signal normBit_uid114_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0); signal path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal sR_uid141_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (11 downto 0); signal InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (35 downto 0); signal RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0); signal RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (33 downto 0); signal rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (18 downto 0); signal vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (18 downto 0); signal rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (26 downto 0); signal rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (32 downto 0); signal vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (32 downto 0); signal InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (8 downto 0); signal expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (8 downto 0); signal expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (11 downto 0); signal RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (19 downto 0); signal RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (17 downto 0); signal fpOOPi_uid11_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal lowRangeB_uid411_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid411_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid412_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid412_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid417_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid417_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid418_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0); signal highBBits_uid418_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0); signal lowRangeB_uid555_arccosXO2PolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid555_arccosXO2PolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid556_arccosXO2PolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid556_arccosXO2PolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid561_arccosXO2PolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid561_arccosXO2PolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid562_arccosXO2PolyEval_in : std_logic_vector (24 downto 0); signal highBBits_uid562_arccosXO2PolyEval_b : std_logic_vector (22 downto 0); signal lowRangeB_uid571_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid571_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid572_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal highBBits_uid572_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal lowRangeB_uid577_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid577_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid578_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal highBBits_uid578_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0); signal yT1_uid409_arcsinXO2XPolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid409_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal yT1_uid569_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0); signal yT1_uid569_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal exc_N_uid40_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid40_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid40_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal shiftValue_uid56_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal shiftValue_uid56_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0); signal vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (2 downto 0); signal fpL_uid70_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal expX_uid143_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid143_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signX_uid145_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signX_uid145_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal expY_uid144_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expY_uid144_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signY_uid146_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signY_uid146_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0); signal sumAHighB_uid413_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid419_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_a : std_logic_vector(22 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_b : std_logic_vector(22 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_o : std_logic_vector (22 downto 0); signal sumAHighB_uid557_arccosXO2PolyEval_q : std_logic_vector (22 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid563_arccosXO2PolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0); signal sumAHighB_uid573_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0); signal sumAHighB_uid579_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0); signal oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a : std_logic_vector(8 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b : std_logic_vector(8 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o : std_logic_vector (8 downto 0); signal srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q : std_logic_vector (8 downto 0); signal X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (20 downto 0); signal X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0); signal InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (5 downto 0); signal rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (3 downto 0); signal rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (1 downto 0); signal rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal signR_uid211_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal s1_uid411_uid414_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0); signal s2_uid417_uid420_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0); signal s1_uid555_uid558_arccosXO2PolyEval_q : std_logic_vector (23 downto 0); signal s2_uid561_uid564_arccosXO2PolyEval_q : std_logic_vector (32 downto 0); signal s1_uid571_uid574_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0); signal s2_uid577_uid580_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0); signal X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b : std_logic_vector (4 downto 0); signal rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid44_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0); signal expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (6 downto 0); signal InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (21 downto 0); signal RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (19 downto 0); signal RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (17 downto 0); signal Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal y_uid61_acosX_uid8_fpArccosPiTest_in : std_logic_vector (35 downto 0); signal y_uid61_acosX_uid8_fpArccosPiTest_b : std_logic_vector (34 downto 0); signal rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (30 downto 0); signal rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in : std_logic_vector (33 downto 0); signal vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector (33 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal sAddr_uid80_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal sAddr_uid80_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b : std_logic_vector (25 downto 0); signal fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b : std_logic_vector (26 downto 0); signal fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in : std_logic_vector (28 downto 0); signal fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid136_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (32 downto 0); signal RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (28 downto 0); signal RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in : std_logic_vector (36 downto 0); signal RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b : std_logic_vector (24 downto 0); signal expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal firstPath_uid62_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal firstPath_uid62_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal mAddr_uid107_acosX_uid8_fpArccosPiTest_in : std_logic_vector (34 downto 0); signal mAddr_uid107_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in : std_logic_vector (26 downto 0); signal mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b : std_logic_vector (14 downto 0); signal cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in : std_logic_vector (24 downto 0); signal fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in : std_logic_vector (25 downto 0); signal path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (22 downto 0); signal rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q : std_logic_vector (36 downto 0); signal pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal yT1_uid553_arccosXO2PolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid553_arccosXO2PolyEval_b : std_logic_vector (11 downto 0); signal vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q : std_logic_vector (5 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (31 downto 0); signal fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in : std_logic_vector (33 downto 0); signal fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (2 downto 0); signal pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q : std_logic_vector (26 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector (25 downto 0); signal roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (25 downto 0); signal expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in : std_logic_vector (22 downto 0); signal SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b : std_logic_vector (22 downto 0); signal SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in : std_logic_vector (30 downto 0); signal SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in : std_logic_vector (31 downto 0); signal signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector (0 downto 0); signal fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q : std_logic_vector (3 downto 0); signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (15 downto 0); signal X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in : std_logic_vector (23 downto 0); signal X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b : std_logic_vector (7 downto 0); signal rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q : std_logic_vector (23 downto 0); begin --xIn(GPIN,3)@0 --cstAllZWF_uid19_acosX_uid8_fpArccosPiTest(CONSTANT,18) cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000000"; --GND(CONSTANT,0) GND_q <= "0"; --cstAllOWE_uid18_acosX_uid8_fpArccosPiTest(CONSTANT,17) cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q <= "11111111"; --cstBiasP1_uid26_acosX_uid8_fpArccosPiTest(CONSTANT,25) cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q <= "10000000"; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable(LOGICAL,1457) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a <= en; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q <= not ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_a; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor(LOGICAL,1626) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q <= not (ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_a or ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_b); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top(CONSTANT,1609) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q <= "011001"; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp(LOGICAL,1610) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_mem_top_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q); ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q <= "1" when ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_a = ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_b else "0"; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg(REG,1611) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmp_q; END IF; END IF; END PROCESS; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena(REG,1627) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_nor_q = "1") THEN ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd(LOGICAL,1628) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b <= en; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a and ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b; --rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,271) rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "000"; --RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,270)@1 RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 3); --rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,272)@1 rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx3Pad3_uid272_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage136dto3_uid271_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,268) rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "00"; --RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,267)@1 RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 2); --rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,269)@1 rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage136dto2_uid268_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,264)@1 RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 1); --rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,266)@1 rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage136dto1_uid265_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,260) rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "000000000000"; --rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,250) rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000000000000000000000000000000000000"; --rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,248) rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000000000000000"; --X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,247)@0 X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q; X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 32); --rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,249)@0 rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X36dto32_uid248_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,245) rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000000000000000"; --X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,244)@0 X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q; X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 16); --rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,246)@0 rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X36dto16_uid245_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --fracX_uid16_acosX_uid8_fpArccosPiTest(BITSELECT,15)@0 fracX_uid16_acosX_uid8_fpArccosPiTest_in <= a(22 downto 0); fracX_uid16_acosX_uid8_fpArccosPiTest_b <= fracX_uid16_acosX_uid8_fpArccosPiTest_in(22 downto 0); --oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest(BITJOIN,50)@0 oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q <= VCC_q & fracX_uid16_acosX_uid8_fpArccosPiTest_b; --cst01pWShift_uid57_acosX_uid8_fpArccosPiTest(CONSTANT,56) cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q <= "0000000000000"; --oFracXExt_uid58_acosX_uid8_fpArccosPiTest(BITJOIN,57)@0 oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q <= oFracX_uid51_uid51_acosX_uid8_fpArccosPiTest_q & cst01pWShift_uid57_acosX_uid8_fpArccosPiTest_q; --shiftOutVal_uid54_acosX_uid8_fpArccosPiTest(CONSTANT,53) shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q <= "100100"; --expX_uid15_acosX_uid8_fpArccosPiTest(BITSELECT,14)@0 expX_uid15_acosX_uid8_fpArccosPiTest_in <= a(30 downto 0); expX_uid15_acosX_uid8_fpArccosPiTest_b <= expX_uid15_acosX_uid8_fpArccosPiTest_in(30 downto 23); --cstBias_uid22_acosX_uid8_fpArccosPiTest(CONSTANT,21) cstBias_uid22_acosX_uid8_fpArccosPiTest_q <= "01111111"; --shiftValuePre_uid53_acosX_uid8_fpArccosPiTest(SUB,52)@0 shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_acosX_uid8_fpArccosPiTest_b); shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_b)); shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q <= shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_o(8 downto 0); --fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest(BITSELECT,54)@0 fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in <= shiftValuePre_uid53_acosX_uid8_fpArccosPiTest_q(5 downto 0); fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b <= fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_in(5 downto 0); --cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest(CONSTANT,23) cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q <= "001011100"; --shiftValue_uid52_acosX_uid8_fpArccosPiTest(COMPARE,51)@0 shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin <= GND_q; shiftValue_uid52_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((10 downto 9 => cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q(8)) & cstBiasMwFMwShift_uid24_acosX_uid8_fpArccosPiTest_q) & '0'; shiftValue_uid52_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & expX_uid15_acosX_uid8_fpArccosPiTest_b) & shiftValue_uid52_acosX_uid8_fpArccosPiTest_cin(0); shiftValue_uid52_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValue_uid52_acosX_uid8_fpArccosPiTest_a) - SIGNED(shiftValue_uid52_acosX_uid8_fpArccosPiTest_b)); shiftValue_uid52_acosX_uid8_fpArccosPiTest_n(0) <= not shiftValue_uid52_acosX_uid8_fpArccosPiTest_o(11); --shiftValue_uid56_acosX_uid8_fpArccosPiTest(MUX,55)@0 shiftValue_uid56_acosX_uid8_fpArccosPiTest_s <= shiftValue_uid52_acosX_uid8_fpArccosPiTest_n; shiftValue_uid56_acosX_uid8_fpArccosPiTest: PROCESS (shiftValue_uid56_acosX_uid8_fpArccosPiTest_s, en, fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b, shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q) BEGIN CASE shiftValue_uid56_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= fxpShifterBits_uid55_acosX_uid8_fpArccosPiTest_b; WHEN "1" => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= shiftOutVal_uid54_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => shiftValue_uid56_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,251)@0 rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q; rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(5 downto 4); --rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,252)@0 rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= rightShiftStageSel5Dto4_uid252_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= oFracXExt_uid58_acosX_uid8_fpArccosPiTest_q; WHEN "01" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1_uid247_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "10" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx2_uid250_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "11" => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid251_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,259)@0 RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 12); --rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,261)@0 rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad12_uid261_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto12_uid260_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5(REG,613)@0 reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q <= rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,256)@0 RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 8); --rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,258)@0 rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto8_uid257_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4(REG,612)@0 reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest(CONSTANT,254) rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= "0000"; --RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,253)@0 RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(36 downto 4); --rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITJOIN,255)@0 rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage036dto4_uid254_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3(REG,611)@0 reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2(REG,610)@0 reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q <= rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,262)@0 rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q(3 downto 0); rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(3 downto 2); --reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1(REG,609)@0 reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,263)@1 rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel3Dto2_uid263_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q, reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q) BEGIN CASE rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0_uid253_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx1_uid256_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx2_uid259_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx3_uid262_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_5_q; WHEN OTHERS => rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest(BITSELECT,273)@0 rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in <= shiftValue_uid56_acosX_uid8_fpArccosPiTest_q(1 downto 0); rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_in(1 downto 0); --reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1(REG,614)@0 reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest(MUX,274)@1 rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel1Dto0_uid274_fxpX_uid59_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid264_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "01" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid267_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "10" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2_uid270_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN "11" => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx3_uid273_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid61_acosX_uid8_fpArccosPiTest(BITSELECT,60)@1 y_uid61_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q(35 downto 0); y_uid61_acosX_uid8_fpArccosPiTest_b <= y_uid61_acosX_uid8_fpArccosPiTest_in(35 downto 1); --mAddr_uid107_acosX_uid8_fpArccosPiTest(BITSELECT,106)@1 mAddr_uid107_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b; mAddr_uid107_acosX_uid8_fpArccosPiTest_b <= mAddr_uid107_acosX_uid8_fpArccosPiTest_in(34 downto 27); --reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0(REG,688)@1 reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q <= mAddr_uid107_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid552_arccosXO2TabGen_lutmem(DUALMEM,604)@2 memoryC2_uid552_arccosXO2TabGen_lutmem_reset0 <= areset; memoryC2_uid552_arccosXO2TabGen_lutmem_ia <= (others => '0'); memoryC2_uid552_arccosXO2TabGen_lutmem_aa <= (others => '0'); memoryC2_uid552_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q; memoryC2_uid552_arccosXO2TabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC2_uid552_arccosXO2TabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid552_arccosXO2TabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid552_arccosXO2TabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid552_arccosXO2TabGen_lutmem_iq, address_a => memoryC2_uid552_arccosXO2TabGen_lutmem_aa, data_a => memoryC2_uid552_arccosXO2TabGen_lutmem_ia ); memoryC2_uid552_arccosXO2TabGen_lutmem_q <= memoryC2_uid552_arccosXO2TabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1(REG,690)@4 reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q <= memoryC2_uid552_arccosXO2TabGen_lutmem_q; END IF; END IF; END PROCESS; --mPPolyEval_uid108_acosX_uid8_fpArccosPiTest(BITSELECT,107)@1 mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b(26 downto 0); mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_in(26 downto 12); --yT1_uid553_arccosXO2PolyEval(BITSELECT,552)@1 yT1_uid553_arccosXO2PolyEval_in <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b; yT1_uid553_arccosXO2PolyEval_b <= yT1_uid553_arccosXO2PolyEval_in(14 downto 3); --ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg(DELAY,1601) ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 12, depth => 1 ) PORT MAP ( xin => yT1_uid553_arccosXO2PolyEval_b, xout => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a(DELAY,1420)@1 ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a : dspba_delay GENERIC MAP ( width => 12, depth => 2 ) PORT MAP ( xin => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_inputreg_q, xout => ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0(REG,689)@4 reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q <= ld_yT1_uid553_arccosXO2PolyEval_b_to_reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_a_q; END IF; END IF; END PROCESS; --prodXY_uid588_pT1_uid554_arccosXO2PolyEval(MULT,587)@5 prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a),13)) * SIGNED(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b); prodXY_uid588_pT1_uid554_arccosXO2PolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a <= (others => '0'); prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b <= (others => '0'); prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_a <= reg_yT1_uid553_arccosXO2PolyEval_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_0_q; prodXY_uid588_pT1_uid554_arccosXO2PolyEval_b <= reg_memoryC2_uid552_arccosXO2TabGen_lutmem_0_to_prodXY_uid588_pT1_uid554_arccosXO2PolyEval_1_q; prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid588_pT1_uid554_arccosXO2PolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid588_pT1_uid554_arccosXO2PolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q <= prodXY_uid588_pT1_uid554_arccosXO2PolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval(BITSELECT,588)@8 prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in <= prodXY_uid588_pT1_uid554_arccosXO2PolyEval_q; prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_in(23 downto 11); --highBBits_uid556_arccosXO2PolyEval(BITSELECT,555)@8 highBBits_uid556_arccosXO2PolyEval_in <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b; highBBits_uid556_arccosXO2PolyEval_b <= highBBits_uid556_arccosXO2PolyEval_in(12 downto 1); --ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg(DELAY,1602) ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => mAddr_uid107_acosX_uid8_fpArccosPiTest_b, xout => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a(DELAY,1422)@1 ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_inputreg_q, xout => ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0(REG,691)@5 reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q <= ld_mAddr_uid107_acosX_uid8_fpArccosPiTest_b_to_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid551_arccosXO2TabGen_lutmem(DUALMEM,603)@6 memoryC1_uid551_arccosXO2TabGen_lutmem_reset0 <= areset; memoryC1_uid551_arccosXO2TabGen_lutmem_ia <= (others => '0'); memoryC1_uid551_arccosXO2TabGen_lutmem_aa <= (others => '0'); memoryC1_uid551_arccosXO2TabGen_lutmem_ab <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid551_arccosXO2TabGen_lutmem_0_q; memoryC1_uid551_arccosXO2TabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 22, widthad_a => 8, numwords_a => 256, width_b => 22, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC1_uid551_arccosXO2TabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid551_arccosXO2TabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid551_arccosXO2TabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid551_arccosXO2TabGen_lutmem_iq, address_a => memoryC1_uid551_arccosXO2TabGen_lutmem_aa, data_a => memoryC1_uid551_arccosXO2TabGen_lutmem_ia ); memoryC1_uid551_arccosXO2TabGen_lutmem_q <= memoryC1_uid551_arccosXO2TabGen_lutmem_iq(21 downto 0); --sumAHighB_uid557_arccosXO2PolyEval(ADD,556)@8 sumAHighB_uid557_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((22 downto 22 => memoryC1_uid551_arccosXO2TabGen_lutmem_q(21)) & memoryC1_uid551_arccosXO2TabGen_lutmem_q); sumAHighB_uid557_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((22 downto 12 => highBBits_uid556_arccosXO2PolyEval_b(11)) & highBBits_uid556_arccosXO2PolyEval_b); sumAHighB_uid557_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid557_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid557_arccosXO2PolyEval_b)); sumAHighB_uid557_arccosXO2PolyEval_q <= sumAHighB_uid557_arccosXO2PolyEval_o(22 downto 0); --lowRangeB_uid555_arccosXO2PolyEval(BITSELECT,554)@8 lowRangeB_uid555_arccosXO2PolyEval_in <= prodXYTruncFR_uid589_pT1_uid554_arccosXO2PolyEval_b(0 downto 0); lowRangeB_uid555_arccosXO2PolyEval_b <= lowRangeB_uid555_arccosXO2PolyEval_in(0 downto 0); --s1_uid555_uid558_arccosXO2PolyEval(BITJOIN,557)@8 s1_uid555_uid558_arccosXO2PolyEval_q <= sumAHighB_uid557_arccosXO2PolyEval_q & lowRangeB_uid555_arccosXO2PolyEval_b; --reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1(REG,693)@8 reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q <= s1_uid555_uid558_arccosXO2PolyEval_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor(LOGICAL,1535) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q <= not (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_a or ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_b); --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top(CONSTANT,1531) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q <= "0101"; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp(LOGICAL,1532) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_mem_top_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q); ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q <= "1" when ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_a = ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_b else "0"; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg(REG,1533) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena(REG,1536) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_nor_q = "1") THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd(LOGICAL,1537) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b <= en; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_a and ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_b; --reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0(REG,692)@1 reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q <= mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt(COUNTER,1527) -- every=1, low=0, high=5, step=1, init=1 ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i = 4 THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i - 5; ELSE ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_i,3)); --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg(REG,1528) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux(MUX,1529) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s <= en; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux: PROCESS (ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s, ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q, ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem(DUALMEM,1526) ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0 <= areset; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia <= reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 3, numwords_a => 6, width_b => 15, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq, address_a => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_aa, data_a => ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_ia ); ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_iq(14 downto 0); --prodXY_uid591_pT2_uid560_arccosXO2PolyEval(MULT,590)@9 prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a),16)) * SIGNED(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b); prodXY_uid591_pT2_uid560_arccosXO2PolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a <= (others => '0'); prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b <= (others => '0'); prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_mem_q; prodXY_uid591_pT2_uid560_arccosXO2PolyEval_b <= reg_s1_uid555_uid558_arccosXO2PolyEval_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_1_q; prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid591_pT2_uid560_arccosXO2PolyEval_pr,39)); END IF; END IF; END PROCESS; prodXY_uid591_pT2_uid560_arccosXO2PolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q <= prodXY_uid591_pT2_uid560_arccosXO2PolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval(BITSELECT,591)@12 prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in <= prodXY_uid591_pT2_uid560_arccosXO2PolyEval_q; prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_in(38 downto 14); --highBBits_uid562_arccosXO2PolyEval(BITSELECT,561)@12 highBBits_uid562_arccosXO2PolyEval_in <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b; highBBits_uid562_arccosXO2PolyEval_b <= highBBits_uid562_arccosXO2PolyEval_in(24 downto 2); --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor(LOGICAL,1548) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q <= not (ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_a or ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_b); --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena(REG,1549) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_nor_q = "1") THEN ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd(LOGICAL,1550) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_sticky_ena_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b <= en; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_a and ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_b; --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem(DUALMEM,1539) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia <= reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid552_arccosXO2TabGen_lutmem_0_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_ia ); ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_iq(7 downto 0); --ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg(DELAY,1538) ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_replace_mem_q, xout => ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC0_uid550_arccosXO2TabGen_lutmem(DUALMEM,602)@10 memoryC0_uid550_arccosXO2TabGen_lutmem_reset0 <= areset; memoryC0_uid550_arccosXO2TabGen_lutmem_ia <= (others => '0'); memoryC0_uid550_arccosXO2TabGen_lutmem_aa <= (others => '0'); memoryC0_uid550_arccosXO2TabGen_lutmem_ab <= ld_reg_mAddr_uid107_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid550_arccosXO2TabGen_lutmem_0_q_to_memoryC0_uid550_arccosXO2TabGen_lutmem_a_outputreg_q; memoryC0_uid550_arccosXO2TabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC0_uid550_arccosXO2TabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid550_arccosXO2TabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid550_arccosXO2TabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid550_arccosXO2TabGen_lutmem_iq, address_a => memoryC0_uid550_arccosXO2TabGen_lutmem_aa, data_a => memoryC0_uid550_arccosXO2TabGen_lutmem_ia ); memoryC0_uid550_arccosXO2TabGen_lutmem_q <= memoryC0_uid550_arccosXO2TabGen_lutmem_iq(29 downto 0); --sumAHighB_uid563_arccosXO2PolyEval(ADD,562)@12 sumAHighB_uid563_arccosXO2PolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid550_arccosXO2TabGen_lutmem_q(29)) & memoryC0_uid550_arccosXO2TabGen_lutmem_q); sumAHighB_uid563_arccosXO2PolyEval_b <= STD_LOGIC_VECTOR((30 downto 23 => highBBits_uid562_arccosXO2PolyEval_b(22)) & highBBits_uid562_arccosXO2PolyEval_b); sumAHighB_uid563_arccosXO2PolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid563_arccosXO2PolyEval_a) + SIGNED(sumAHighB_uid563_arccosXO2PolyEval_b)); sumAHighB_uid563_arccosXO2PolyEval_q <= sumAHighB_uid563_arccosXO2PolyEval_o(30 downto 0); --lowRangeB_uid561_arccosXO2PolyEval(BITSELECT,560)@12 lowRangeB_uid561_arccosXO2PolyEval_in <= prodXYTruncFR_uid592_pT2_uid560_arccosXO2PolyEval_b(1 downto 0); lowRangeB_uid561_arccosXO2PolyEval_b <= lowRangeB_uid561_arccosXO2PolyEval_in(1 downto 0); --s2_uid561_uid564_arccosXO2PolyEval(BITJOIN,563)@12 s2_uid561_uid564_arccosXO2PolyEval_q <= sumAHighB_uid563_arccosXO2PolyEval_q & lowRangeB_uid561_arccosXO2PolyEval_b; --fxpArccosX_uid110_acosX_uid8_fpArccosPiTest(BITSELECT,109)@12 fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in <= s2_uid561_uid564_arccosXO2PolyEval_q(30 downto 0); fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_in(30 downto 4); --reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1(REG,696)@12 reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --pi2_uid111_acosX_uid8_fpArccosPiTest(CONSTANT,110) pi2_uid111_acosX_uid8_fpArccosPiTest_q <= "110010010000111111011010101"; --pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest(BITJOIN,111)@12 pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q <= pi2_uid111_acosX_uid8_fpArccosPiTest_q & GND_q; --reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0(REG,695)@12 reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q <= "0000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q <= pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --path2Diff_uid112_acosX_uid8_fpArccosPiTest(SUB,112)@13 path2Diff_uid112_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_pi2_uid111_uid112_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_0_q); path2Diff_uid112_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_0_to_path2Diff_uid112_acosX_uid8_fpArccosPiTest_1_q); path2Diff_uid112_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid112_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(path2Diff_uid112_acosX_uid8_fpArccosPiTest_b)); path2Diff_uid112_acosX_uid8_fpArccosPiTest_q <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_o(28 downto 0); --path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest(BITSELECT,114)@13 path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(26 downto 0); path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b <= path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_in(26 downto 4); --path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest(BITJOIN,115)@13 path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q & path2NegCaseFPFrac_uid115_acosX_uid8_fpArccosPiTest_b; --path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest(BITSELECT,117)@13 path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(25 downto 0); path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b <= path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_in(25 downto 3); --path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest(BITJOIN,118)@13 path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBias_uid22_acosX_uid8_fpArccosPiTest_q & path2NegCaseFPFrac_uid118_acosX_uid8_fpArccosPiTest_b; --normBit_uid114_acosX_uid8_fpArccosPiTest(BITSELECT,113)@13 normBit_uid114_acosX_uid8_fpArccosPiTest_in <= path2Diff_uid112_acosX_uid8_fpArccosPiTest_q(27 downto 0); normBit_uid114_acosX_uid8_fpArccosPiTest_b <= normBit_uid114_acosX_uid8_fpArccosPiTest_in(27 downto 27); --path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest(MUX,120)@13 path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s <= normBit_uid114_acosX_uid8_fpArccosPiTest_b; path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest: PROCESS (path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s, en, path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q, path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q) BEGIN CASE path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFPS_uid119_acosX_uid8_fpArccosPiTest_q; WHEN "1" => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFPL_uid116_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest(BITSELECT,121)@12 path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in <= fxpArccosX_uid110_acosX_uid8_fpArccosPiTest_b(25 downto 0); path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b <= path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_in(25 downto 3); --ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a(DELAY,806)@12 ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b, xout => ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest(BITJOIN,122)@13 path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBias_uid22_acosX_uid8_fpArccosPiTest_q & ld_path2PosCaseFPFraction_uid122_acosX_uid8_fpArccosPiTest_b_to_path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_a_q; --singX_uid17_acosX_uid8_fpArccosPiTest(BITSELECT,16)@0 singX_uid17_acosX_uid8_fpArccosPiTest_in <= a; singX_uid17_acosX_uid8_fpArccosPiTest_b <= singX_uid17_acosX_uid8_fpArccosPiTest_in(31 downto 31); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b(DELAY,807)@0 ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => singX_uid17_acosX_uid8_fpArccosPiTest_b, xout => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --path2ResFP_uid125_acosX_uid8_fpArccosPiTest(MUX,124)@13 path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path2ResFP_uid125_acosX_uid8_fpArccosPiTest_b_q; path2ResFP_uid125_acosX_uid8_fpArccosPiTest: PROCESS (path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s, en, path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q, path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q) BEGIN CASE path2ResFP_uid125_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= path2PosCaseFP_uid123_acosX_uid8_fpArccosPiTest_q; WHEN "1" => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= path2NegCaseFP_uid121_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest(BITSELECT,131)@13 Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in <= path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q(30 downto 0); Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b <= Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_in(30 downto 23); --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg(DELAY,1616) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b, xout => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt(COUNTER,1605) -- every=1, low=0, high=25, step=1, init=1 ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i = 24 THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '1'; ELSE ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_eq = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i - 25; ELSE ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_i,5)); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg(REG,1606) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux(MUX,1607) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s <= en; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux: PROCESS (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s, ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q, ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q) BEGIN CASE ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_s IS WHEN "0" => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q; WHEN "1" => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdcnt_q; WHEN OTHERS => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem(DUALMEM,1617) ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 <= areset; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_inputreg_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q; ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 26, width_b => 8, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0, clock1 => clk, address_b => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq, address_a => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa, data_a => ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia ); ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq(7 downto 0); --reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3(REG,700)@41 reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q <= ld_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q; END IF; END IF; END PROCESS; --RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,543)@39 RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 1); --rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,545)@39 rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage123dto1_uid544_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(CONSTANT,395) rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= "000000"; --RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,538)@39 RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 6); --rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,540)@39 rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto6_uid539_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,535)@39 RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 4); --rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,537)@39 rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto4_uid536_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,532)@39 RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 2); --rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,534)@39 rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto2_uid533_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(CONSTANT,385) rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= "000000000000000000000000"; --maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(CONSTANT,319) maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "100011"; --reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1(REG,616)@1 reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q <= y_uid61_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest(BITJOIN,62)@1 pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q); --reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0(REG,615)@1 reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q <= "000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q <= pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --oMy_uid63_acosX_uid8_fpArccosPiTest(SUB,63)@2 oMy_uid63_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_o_uid27_uid63_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_0_q); oMy_uid63_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid61_acosX_uid8_fpArccosPiTest_0_to_oMy_uid63_acosX_uid8_fpArccosPiTest_1_q); oMy_uid63_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid63_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(oMy_uid63_acosX_uid8_fpArccosPiTest_b)); oMy_uid63_acosX_uid8_fpArccosPiTest_q <= oMy_uid63_acosX_uid8_fpArccosPiTest_o(36 downto 0); --l_uid65_acosX_uid8_fpArccosPiTest(BITSELECT,64)@2 l_uid65_acosX_uid8_fpArccosPiTest_in <= oMy_uid63_acosX_uid8_fpArccosPiTest_q(34 downto 0); l_uid65_acosX_uid8_fpArccosPiTest_b <= l_uid65_acosX_uid8_fpArccosPiTest_in(34 downto 0); --rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,277)@2 rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= l_uid65_acosX_uid8_fpArccosPiTest_b; rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 3); --reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,617)@2 reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,278)@3 vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid278_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q; vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f(DELAY,1040)@3 ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,280)@2 vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= l_uid65_acosX_uid8_fpArccosPiTest_b(2 downto 0); vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(2 downto 0); --cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,281)@2 cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid281_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage0Idx2Pad32_uid249_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,619)@2 reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,618)@2 reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= l_uid65_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,282)@3 vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q) BEGIN CASE vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_l_uid65_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q; WHEN "1" => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid282_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q; WHEN OTHERS => vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,284)@3 rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 19); --reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,620)@3 reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,285)@4 vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid285_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q; vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e(DELAY,1039)@4 ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,287)@3 vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(18 downto 0); vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(18 downto 0); --cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,288)@3 cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid288_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,622)@3 reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,621)@3 reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,289)@4 vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q) BEGIN CASE vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_vStagei_uid283_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q; WHEN "1" => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid289_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q; WHEN OTHERS => vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,291)@4 rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 27); --vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,292)@4 vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid292_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,626)@4 reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,294)@4 vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(26 downto 0); vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(26 downto 0); --cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,295)@4 cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid295_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; --vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,296)@4 vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) BEGIN CASE vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid290_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN "1" => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid296_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,298)@4 rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 31); --reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,623)@4 reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,299)@5 vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= reg_rVStage_uid299_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q; vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,301)@4 vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(30 downto 0); vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(30 downto 0); --cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,302)@4 cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid302_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3(REG,625)@4 reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q <= cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2(REG,624)@4 reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q <= vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,303)@5 vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q, reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q) BEGIN CASE vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_vStagei_uid297_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_2_q; WHEN "1" => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= reg_cStage_uid303_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q; WHEN OTHERS => vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,305)@5 rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 33); --vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,306)@5 vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid306_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,308)@5 vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(32 downto 0); vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(32 downto 0); --cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,309)@5 cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid309_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; --vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,310)@5 vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) BEGIN CASE vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid304_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN "1" => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid310_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,312)@5 rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(34 downto 34); --vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(LOGICAL,313)@5 vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= rVStage_uid313_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b; vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= GND_q; vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= "1" when vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a = vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b else "0"; --vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,318)@5 vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= ld_vCount_uid279_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_f_q & ld_vCount_uid286_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_e_q & reg_vCount_uid293_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_3_q & vCount_uid300_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q & vCount_uid307_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q & vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; --ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c(DELAY,1043)@5 ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 6, depth => 1 ) PORT MAP ( xin => vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, xout => ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1(REG,627)@5 reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q <= vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(COMPARE,320)@6 vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin <= GND_q; vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) & '0'; vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_0_to_vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_1_q) & vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_cin(0); vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b)); vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c(0) <= vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_o(8); --vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,322)@6 vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCountBig_uid321_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c; vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= ld_vCount_uid319_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q_to_vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_c_q; WHEN "1" => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= maxCountVal_uid320_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --cstBiasM2_uid6_fpArccosPiTest(CONSTANT,5) cstBiasM2_uid6_fpArccosPiTest_q <= "01111101"; --expL_uid67_acosX_uid8_fpArccosPiTest(SUB,66)@7 expL_uid67_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid6_fpArccosPiTest_q); expL_uid67_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid323_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q); expL_uid67_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid67_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(expL_uid67_acosX_uid8_fpArccosPiTest_b)); expL_uid67_acosX_uid8_fpArccosPiTest_q <= expL_uid67_acosX_uid8_fpArccosPiTest_o(8 downto 0); --expLRange_uid69_acosX_uid8_fpArccosPiTest(BITSELECT,68)@7 expLRange_uid69_acosX_uid8_fpArccosPiTest_in <= expL_uid67_acosX_uid8_fpArccosPiTest_q(7 downto 0); expLRange_uid69_acosX_uid8_fpArccosPiTest_b <= expLRange_uid69_acosX_uid8_fpArccosPiTest_in(7 downto 0); --vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITSELECT,315)@5 vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(33 downto 0); vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b <= vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_in(33 downto 0); --cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(BITJOIN,316)@5 cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStage_uid316_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_b & GND_q; --vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest(MUX,317)@5 vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s <= vCount_uid314_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest: PROCESS (vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s, en, vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q, cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q) BEGIN CASE vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= vStagei_uid311_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN "1" => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= cStage_uid317_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest(BITSELECT,67)@5 fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in <= vStagei_uid318_fpLOut1_uid66_acosX_uid8_fpArccosPiTest_q(33 downto 0); fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b <= fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_in(33 downto 11); --ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a(DELAY,1359)@5 ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b, xout => ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0(REG,628)@6 reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q <= ld_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_b_to_reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_a_q; END IF; END IF; END PROCESS; --fpL_uid70_acosX_uid8_fpArccosPiTest(BITJOIN,69)@7 fpL_uid70_acosX_uid8_fpArccosPiTest_q <= GND_q & expLRange_uid69_acosX_uid8_fpArccosPiTest_b & reg_fpLOutFrac_uid68_acosX_uid8_fpArccosPiTest_0_to_fpL_uid70_acosX_uid8_fpArccosPiTest_0_q; --signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,327)@7 signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q; signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(31 downto 31); --expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,325)@7 expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q(30 downto 0); expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(30 downto 23); --expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,332)@7 expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b else "0"; --negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,375)@7 negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; END IF; END PROCESS; --ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c(DELAY,1099)@8 ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor(LOGICAL,1499) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q <= not (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_a or ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_b); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top(CONSTANT,1495) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q <= "0110"; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp(LOGICAL,1496) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_mem_top_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q); ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_a = ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_b else "0"; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg(REG,1497) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena(REG,1500) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_nor_q = "1") THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd(LOGICAL,1501) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b <= en; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_a and ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_b; --cstBiasM1_uid23_acosX_uid8_fpArccosPiTest(CONSTANT,22) cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q <= "01111110"; --reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0(REG,638)@7 reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(ADD,348)@8 expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q); expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q); expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b)); expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o(8 downto 0); --expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,349)@8 expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expOddSig_uid349_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(8 downto 1); --expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(ADD,345)@8 expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q); expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b)); expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_o(8 downto 0); --expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,346)@8 expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expEvenSig_uid346_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(8 downto 1); --expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,350)@7 expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(0 downto 0); expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(0 downto 0); --expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,351)@7 expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX0_uid351_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1067)@7 ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,352)@8 expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= ld_expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expREven_uid347_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; WHEN "1" => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expROdd_uid350_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1079)@7 ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,340)@8 InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,326)@7 fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fpL_uid70_acosX_uid8_fpArccosPiTest_q(22 downto 0); fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1(REG,629)@7 reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,336)@8 fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= reg_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_1_q; fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b else "0"; --expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,334)@7 expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expX_uid326_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN IF (expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b) THEN expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "1"; ELSE expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "0"; END IF; END IF; END PROCESS; --exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,337)@8 exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,341)@8 InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,342)@7 InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; END IF; END PROCESS; --exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,343)@8 exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid343_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid342_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid341_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b and exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c; --minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,361)@8 minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_R_uid344_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,362)@8 minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,338)@8 InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid337_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,339)@8 exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid335_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid339_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,363)@8 excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_N_uid340_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= minInf_uid363_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c <= minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a or excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b or excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c; --InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,359)@7 InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= not InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a; --ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1077)@7 ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOGICAL,360)@8 inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a <= exc_I_uid338_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= ld_InvSignX_uid360_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a and inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a(DELAY,1085)@7 ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,364)@8 join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid364_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & inInfAndNotNeg_uid361_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & ld_expXIsZero_uid333_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q; --fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,365)@8 fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= ld_signX_uid328_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_minReg_uid362_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q & join_uid365_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; --reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0(REG,630)@8 reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q <= fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(LOOKUP,366)@9 fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_fracSelIn_uid366_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_q) IS WHEN "0000" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "0001" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "0010" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "0011" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "0100" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "0101" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "0110" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "0111" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "1000" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1001" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "1010" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1011" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1100" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1101" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1110" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "1111" => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN OTHERS => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,370)@9 expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expRMux_uid353_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; WHEN "10" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg(DELAY,1489) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt(COUNTER,1491) -- every=1, low=0, high=6, step=1, init=1 ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i = 5 THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i - 6; ELSE ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i,3)); --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg(REG,1492) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux(MUX,1493) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s <= en; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s, ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q, ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; WHEN "1" => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem(DUALMEM,1490) ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_inputreg_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q; ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 7, width_b => 8, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_ia ); ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q <= ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_iq(7 downto 0); --cstNaNWF_uid20_acosX_uid8_fpArccosPiTest(CONSTANT,19) cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q <= "00000000000000000000001"; --fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,354)@7 fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(22 downto 16); --addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,355)@7 addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= expOddSelect_uid352_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q & fracXAddr_uid355_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; --reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0(REG,631)@7 reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q <= addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --memoryC2_uid568_sqrtTableGenerator_lutmem(DUALMEM,607)@8 memoryC2_uid568_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid568_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid568_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid568_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q; memoryC2_uid568_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC2_uid568_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid568_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid568_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid568_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid568_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid568_sqrtTableGenerator_lutmem_ia ); memoryC2_uid568_sqrtTableGenerator_lutmem_q <= memoryC2_uid568_sqrtTableGenerator_lutmem_iq(11 downto 0); --reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1(REG,633)@10 reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q <= memoryC2_uid568_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1488) ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a(DELAY,1073)@7 ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_inputreg_q, xout => ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,356)@10 FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= ld_fracX_uid327_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_a_q(15 downto 0); FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(15 downto 0); --yT1_uid569_sqrtPolynomialEvaluator(BITSELECT,568)@10 yT1_uid569_sqrtPolynomialEvaluator_in <= FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; yT1_uid569_sqrtPolynomialEvaluator_b <= yT1_uid569_sqrtPolynomialEvaluator_in(15 downto 4); --reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0(REG,632)@10 reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q <= yT1_uid569_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator(MULT,593)@11 prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b); prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_a <= reg_yT1_uid569_sqrtPolynomialEvaluator_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_0_q; prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid568_sqrtTableGenerator_lutmem_0_to_prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_1_q; prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_pr,24)); END IF; END IF; END PROCESS; prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q <= prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator(BITSELECT,594)@14 prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in <= prodXY_uid594_pT1_uid570_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_in(23 downto 11); --highBBits_uid572_sqrtPolynomialEvaluator(BITSELECT,571)@14 highBBits_uid572_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b; highBBits_uid572_sqrtPolynomialEvaluator_b <= highBBits_uid572_sqrtPolynomialEvaluator_in(12 downto 1); --ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a(DELAY,1337)@8 ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid568_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1551) ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_q, xout => ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid567_sqrtTableGenerator_lutmem(DUALMEM,606)@12 memoryC1_uid567_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid567_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid567_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid567_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid567_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid567_sqrtTableGenerator_lutmem_a_outputreg_q; memoryC1_uid567_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC1_uid567_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid567_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid567_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid567_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid567_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid567_sqrtTableGenerator_lutmem_ia ); memoryC1_uid567_sqrtTableGenerator_lutmem_q <= memoryC1_uid567_sqrtTableGenerator_lutmem_iq(20 downto 0); --sumAHighB_uid573_sqrtPolynomialEvaluator(ADD,572)@14 sumAHighB_uid573_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid567_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid567_sqrtTableGenerator_lutmem_q); sumAHighB_uid573_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid572_sqrtPolynomialEvaluator_b(11)) & highBBits_uid572_sqrtPolynomialEvaluator_b); sumAHighB_uid573_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid573_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid573_sqrtPolynomialEvaluator_b)); sumAHighB_uid573_sqrtPolynomialEvaluator_q <= sumAHighB_uid573_sqrtPolynomialEvaluator_o(21 downto 0); --lowRangeB_uid571_sqrtPolynomialEvaluator(BITSELECT,570)@14 lowRangeB_uid571_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid595_pT1_uid570_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid571_sqrtPolynomialEvaluator_b <= lowRangeB_uid571_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid571_uid574_sqrtPolynomialEvaluator(BITJOIN,573)@14 s1_uid571_uid574_sqrtPolynomialEvaluator_q <= sumAHighB_uid573_sqrtPolynomialEvaluator_q & lowRangeB_uid571_sqrtPolynomialEvaluator_b; --reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1(REG,636)@14 reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q <= s1_uid571_uid574_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,1560) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_a or ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_b); --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg(REG,1558) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,1561) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,1562) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_b; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,1552) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, xout => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,1554) -- every=1, low=0, high=1, step=1, init=1 ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,1)); --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,1555) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,1556) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,1553) ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 16, widthad_a => 1, numwords_a => 2, width_b => 16, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_iq(15 downto 0); --reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0(REG,635)@14 reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator(MULT,596)@15 prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b); prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_a <= reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_q; prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_b <= reg_s1_uid571_uid574_sqrtPolynomialEvaluator_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_1_q; prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_pr,39)); END IF; END IF; END PROCESS; prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q <= prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator(BITSELECT,597)@18 prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in <= prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_in(38 downto 15); --highBBits_uid578_sqrtPolynomialEvaluator(BITSELECT,577)@18 highBBits_uid578_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b; highBBits_uid578_sqrtPolynomialEvaluator_b <= highBBits_uid578_sqrtPolynomialEvaluator_in(23 downto 2); --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,1573) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,1574) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1575) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1563) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1564) ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0(REG,637)@15 reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid566_sqrtTableGenerator_lutmem(DUALMEM,605)@16 memoryC0_uid566_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid566_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid566_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid566_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid356_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid566_sqrtTableGenerator_lutmem_0_q; memoryC0_uid566_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 29, widthad_a => 8, numwords_a => 256, width_b => 29, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC0_uid566_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid566_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid566_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid566_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid566_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid566_sqrtTableGenerator_lutmem_ia ); memoryC0_uid566_sqrtTableGenerator_lutmem_q <= memoryC0_uid566_sqrtTableGenerator_lutmem_iq(28 downto 0); --sumAHighB_uid579_sqrtPolynomialEvaluator(ADD,578)@18 sumAHighB_uid579_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid566_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid566_sqrtTableGenerator_lutmem_q); sumAHighB_uid579_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid578_sqrtPolynomialEvaluator_b(21)) & highBBits_uid578_sqrtPolynomialEvaluator_b); sumAHighB_uid579_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid579_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid579_sqrtPolynomialEvaluator_b)); sumAHighB_uid579_sqrtPolynomialEvaluator_q <= sumAHighB_uid579_sqrtPolynomialEvaluator_o(29 downto 0); --lowRangeB_uid577_sqrtPolynomialEvaluator(BITSELECT,576)@18 lowRangeB_uid577_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid598_pT2_uid576_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid577_sqrtPolynomialEvaluator_b <= lowRangeB_uid577_sqrtPolynomialEvaluator_in(1 downto 0); --s2_uid577_uid580_sqrtPolynomialEvaluator(BITJOIN,579)@18 s2_uid577_uid580_sqrtPolynomialEvaluator_q <= sumAHighB_uid579_sqrtPolynomialEvaluator_q & lowRangeB_uid577_sqrtPolynomialEvaluator_b; --fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITSELECT,358)@18 fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in <= s2_uid577_uid580_sqrtPolynomialEvaluator_q(28 downto 0); fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b <= fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_in(28 downto 6); --ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b(DELAY,1093)@9 ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 9 ) PORT MAP ( xin => fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q, xout => ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(MUX,374)@18 fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s <= ld_fracSel_uid367_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_q; fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= fracR_uid359_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b; WHEN "10" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest(BITJOIN,376)@18 RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q <= ld_negZero_uid376_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_c_q & ld_expRPostExc_uid371_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q_to_RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_replace_mem_q & fracRPostExc_uid375_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; --SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest(BITSELECT,72)@18 SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q(22 downto 0); SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b <= SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,662)@18 reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,437)@19 fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1149)@19 ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest(BITSELECT,74)@18 SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q(30 downto 0); SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b <= SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_in(30 downto 23); --reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,640)@18 reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,435)@19 expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1148)@19 ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,438)@31 exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,675)@31 reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,399)@20 RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 1); --rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,401)@20 rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= GND_q & RightShiftStage123dto1_uid400_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest(BITJOIN,73)@18 oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q <= VCC_q & SqrtFPL22dto0_uid73_acosX_uid8_fpArccosPiTest_b; --X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,382)@18 X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q; X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 16); --rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,384)@18 rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X23dto16_uid383_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4(REG,644)@18 reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,379)@18 X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q; X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 8); --rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,381)@18 rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & X23dto8_uid380_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3(REG,643)@18 reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2(REG,642)@18 reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --srVal_uid76_acosX_uid8_fpArccosPiTest(SUB,75)@19 srVal_uid76_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_acosX_uid8_fpArccosPiTest_q); srVal_uid76_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q); srVal_uid76_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid76_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(srVal_uid76_acosX_uid8_fpArccosPiTest_b)); srVal_uid76_acosX_uid8_fpArccosPiTest_q <= srVal_uid76_acosX_uid8_fpArccosPiTest_o(8 downto 0); --srValRange_uid77_acosX_uid8_fpArccosPiTest(BITSELECT,76)@19 srValRange_uid77_acosX_uid8_fpArccosPiTest_in <= srVal_uid76_acosX_uid8_fpArccosPiTest_q(4 downto 0); srValRange_uid77_acosX_uid8_fpArccosPiTest_b <= srValRange_uid77_acosX_uid8_fpArccosPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,386)@19 rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b; rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(4 downto 3); --rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,387)@19 rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= rightShiftStageSel4Dto3_uid387_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q, rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx1_uid382_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx2_uid385_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,394)@19 RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 6); --rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,396)@19 rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3Pad6_uid396_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto6_uid395_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5(REG,649)@19 reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q <= rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,391)@19 RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 4); --rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,393)@19 rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1Pad4_uid255_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto4_uid392_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4(REG,648)@19 reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,388)@19 RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(23 downto 2); --rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITJOIN,390)@19 rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx2Pad2_uid269_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & RightShiftStage023dto2_uid389_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3(REG,647)@19 reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2(REG,646)@19 reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q <= rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,397)@19 rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(2 downto 1); --reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1(REG,645)@19 reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,398)@20 rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel2Dto1_uid398_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q, reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q) BEGIN CASE rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx1_uid391_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx2_uid394_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage1Idx3_uid397_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_5_q; WHEN OTHERS => rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(BITSELECT,402)@19 rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in <= srValRange_uid77_acosX_uid8_fpArccosPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1(REG,650)@19 reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest(MUX,403)@20 rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel0Dto0_uid403_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid399_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN "1" => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid402_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --sAddr_uid80_acosX_uid8_fpArccosPiTest(BITSELECT,79)@20 sAddr_uid80_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; sAddr_uid80_acosX_uid8_fpArccosPiTest_b <= sAddr_uid80_acosX_uid8_fpArccosPiTest_in(23 downto 16); --reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0(REG,651)@20 reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q <= sAddr_uid80_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid408_arcsinXO2XTabGen_lutmem(DUALMEM,601)@21 memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_q; memoryC2_uid408_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC2_uid408_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid408_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid408_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC2_uid408_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC2_uid408_arcsinXO2XTabGen_lutmem_ia ); memoryC2_uid408_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid408_arcsinXO2XTabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1(REG,653)@23 reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q <= memoryC2_uid408_arcsinXO2XTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1448) ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q, xout => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a(DELAY,768)@20 ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 24, depth => 2 ) PORT MAP ( xin => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_inputreg_q, xout => ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --sPPolyEval_uid81_acosX_uid8_fpArccosPiTest(BITSELECT,80)@23 sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in <= ld_rightShiftStage2_uid404_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q_to_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_a_q(15 downto 0); sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b <= sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_in(15 downto 1); --yT1_uid409_arcsinXO2XPolyEval(BITSELECT,408)@23 yT1_uid409_arcsinXO2XPolyEval_in <= sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b; yT1_uid409_arcsinXO2XPolyEval_b <= yT1_uid409_arcsinXO2XPolyEval_in(14 downto 3); --reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0(REG,652)@23 reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q <= yT1_uid409_arcsinXO2XPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval(MULT,581)@24 prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b); prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_a <= reg_yT1_uid409_arcsinXO2XPolyEval_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_0_q; prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_b <= reg_memoryC2_uid408_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_1_q; prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q <= prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval(BITSELECT,582)@27 prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in <= prodXY_uid582_pT1_uid410_arcsinXO2XPolyEval_q; prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_in(23 downto 11); --highBBits_uid412_arcsinXO2XPolyEval(BITSELECT,411)@27 highBBits_uid412_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b; highBBits_uid412_arcsinXO2XPolyEval_b <= highBBits_uid412_arcsinXO2XPolyEval_in(12 downto 1); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1576) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => sAddr_uid80_acosX_uid8_fpArccosPiTest_b, xout => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a(DELAY,1385)@20 ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, xout => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0(REG,654)@24 reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid407_arcsinXO2XTabGen_lutmem(DUALMEM,600)@25 memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_q; memoryC1_uid407_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 19, widthad_a => 8, numwords_a => 256, width_b => 19, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC1_uid407_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid407_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid407_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC1_uid407_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC1_uid407_arcsinXO2XTabGen_lutmem_ia ); memoryC1_uid407_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid407_arcsinXO2XTabGen_lutmem_iq(18 downto 0); --sumAHighB_uid413_arcsinXO2XPolyEval(ADD,412)@27 sumAHighB_uid413_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid407_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid407_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid413_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid412_arcsinXO2XPolyEval_b(11)) & highBBits_uid412_arcsinXO2XPolyEval_b); sumAHighB_uid413_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid413_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid413_arcsinXO2XPolyEval_b)); sumAHighB_uid413_arcsinXO2XPolyEval_q <= sumAHighB_uid413_arcsinXO2XPolyEval_o(19 downto 0); --lowRangeB_uid411_arcsinXO2XPolyEval(BITSELECT,410)@27 lowRangeB_uid411_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid583_pT1_uid410_arcsinXO2XPolyEval_b(0 downto 0); lowRangeB_uid411_arcsinXO2XPolyEval_b <= lowRangeB_uid411_arcsinXO2XPolyEval_in(0 downto 0); --s1_uid411_uid414_arcsinXO2XPolyEval(BITJOIN,413)@27 s1_uid411_uid414_arcsinXO2XPolyEval_q <= sumAHighB_uid413_arcsinXO2XPolyEval_q & lowRangeB_uid411_arcsinXO2XPolyEval_b; --reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1(REG,656)@27 reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q <= s1_uid411_uid414_arcsinXO2XPolyEval_q; END IF; END IF; END PROCESS; --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor(LOGICAL,1585) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q <= not (ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_a or ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_b); --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena(REG,1586) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_nor_q = "1") THEN ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd(LOGICAL,1587) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_sticky_ena_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b <= en; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_a and ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_b; --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1577) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b, xout => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem(DUALMEM,1578) ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0 <= areset; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_inputreg_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab <= ld_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_b_to_reg_FracX15dto0_uid357_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid597_pT2_uid576_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 1, numwords_a => 2, width_b => 15, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq, address_a => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_aa, data_a => ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_ia ); ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_iq(14 downto 0); --reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0(REG,655)@27 reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q <= ld_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_b_to_reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval(MULT,584)@28 prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a),16)) * SIGNED(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b); prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_a <= reg_sPPolyEval_uid81_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_0_q; prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_b <= reg_s1_uid411_uid414_arcsinXO2XPolyEval_0_to_prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_1_q; prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_pr,36)); END IF; END IF; END PROCESS; prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q <= prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval(BITSELECT,585)@31 prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in <= prodXY_uid585_pT2_uid416_arcsinXO2XPolyEval_q; prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_in(35 downto 14); --highBBits_uid418_arcsinXO2XPolyEval(BITSELECT,417)@31 highBBits_uid418_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b; highBBits_uid418_arcsinXO2XPolyEval_b <= highBBits_uid418_arcsinXO2XPolyEval_in(21 downto 2); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor(LOGICAL,1598) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q <= not (ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_a or ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_b); --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena(REG,1599) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_nor_q = "1") THEN ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd(LOGICAL,1600) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_sticky_ena_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b <= en; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_a and ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_b; --ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem(DUALMEM,1589) ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0 <= areset; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC1_uid407_arcsinXO2XTabGen_lutmem_0_a_inputreg_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdreg_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_mPPolyEval_uid108_acosX_uid8_fpArccosPiTest_0_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_0_q_to_prodXY_uid591_pT2_uid560_arccosXO2PolyEval_a_replace_rdmux_q; ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq, address_a => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_aa, data_a => ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_ia ); ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0(REG,657)@28 reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q <= ld_sAddr_uid80_acosX_uid8_fpArccosPiTest_b_to_reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid406_arcsinXO2XTabGen_lutmem(DUALMEM,599)@29 memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab <= reg_sAddr_uid80_acosX_uid8_fpArccosPiTest_0_to_memoryC0_uid406_arcsinXO2XTabGen_lutmem_0_q; memoryC0_uid406_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arccospi_s5_memoryC0_uid406_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid406_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid406_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC0_uid406_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC0_uid406_arcsinXO2XTabGen_lutmem_ia ); memoryC0_uid406_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid406_arcsinXO2XTabGen_lutmem_iq(29 downto 0); --sumAHighB_uid419_arcsinXO2XPolyEval(ADD,418)@31 sumAHighB_uid419_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid406_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid406_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid419_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid418_arcsinXO2XPolyEval_b(19)) & highBBits_uid418_arcsinXO2XPolyEval_b); sumAHighB_uid419_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid419_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid419_arcsinXO2XPolyEval_b)); sumAHighB_uid419_arcsinXO2XPolyEval_q <= sumAHighB_uid419_arcsinXO2XPolyEval_o(30 downto 0); --lowRangeB_uid417_arcsinXO2XPolyEval(BITSELECT,416)@31 lowRangeB_uid417_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid586_pT2_uid416_arcsinXO2XPolyEval_b(1 downto 0); lowRangeB_uid417_arcsinXO2XPolyEval_b <= lowRangeB_uid417_arcsinXO2XPolyEval_in(1 downto 0); --s2_uid417_uid420_arcsinXO2XPolyEval(BITJOIN,419)@31 s2_uid417_uid420_arcsinXO2XPolyEval_q <= sumAHighB_uid419_arcsinXO2XPolyEval_q & lowRangeB_uid417_arcsinXO2XPolyEval_b; --fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest(BITSELECT,82)@31 fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in <= s2_uid417_uid420_arcsinXO2XPolyEval_q(30 downto 0); fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b <= fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_in(30 downto 5); --fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest(BITSELECT,83)@31 fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in <= fxpArcSinXO2XRes_uid83_acosX_uid8_fpArccosPiTest_b(24 downto 0); fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b <= fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_in(24 downto 2); --fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest(BITJOIN,84)@31 fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q <= GND_q & cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q & fxpArcsinXO2XResWFRange_uid84_acosX_uid8_fpArccosPiTest_b; --expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,422)@31 expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q(30 downto 0); expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(30 downto 23); --expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,449)@31 expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,659)@31 reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,503)@32 excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,427)@31 fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q(22 downto 0); fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,660)@31 reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,453)@32 fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,451)@31 expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN IF (expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b) THEN expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1"; ELSE expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "0"; END IF; END IF; END PROCESS; --exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,454)@32 exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,433)@19 expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1212)@19 ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,504)@32 excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,505)@32 ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= excXZAndExcYI_uid505_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= excYZAndExcXI_uid504_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,455)@32 InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid454_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,456)@32 exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid452_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid456_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,439)@19 InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid438_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,440)@19 exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid436_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid440_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1242)@19 ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,506)@32 excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ZeroTimesInf_uid506_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,518)@32 InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; END IF; END PROCESS; --signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,424)@31 signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fpArcsinXO2XRes_uid85_acosX_uid8_fpArccosPiTest_q; signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(31 downto 31); --signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,423)@18 signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= RSqrt_uid377_sqrtFPL_uid72_acosX_uid8_fpArccosPiTest_q; signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(31 downto 31); --ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a(DELAY,1410)@18 ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, xout => ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,679)@30 reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= ld_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_a_q; END IF; END IF; END PROCESS; --signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,489)@31 signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_signX_uid424_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= signY_uid425_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a xor signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END PROCESS; --ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1254)@32 ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,519)@33 signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_signR_uid490_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExcRNaN_uid519_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1258)@33 ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,428)@31 add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= VCC_q & fracY_uid428_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,666)@31 reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1523) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a or ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b); --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top(CONSTANT,1507) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q <= "01011"; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp(LOGICAL,1508) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_mem_top_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q); ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q <= "1" when ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_a = ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_b else "0"; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg(REG,1509) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1524) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1525) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt(COUNTER,1503) -- every=1, low=0, high=11, step=1, init=1 ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i = 10 THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i - 11; ELSE ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i,4)); --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg(REG,1504) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux(MUX,1505) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s <= en; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux: PROCESS (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s, ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q, ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q) BEGIN CASE ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s IS WHEN "0" => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; WHEN "1" => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1514) ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid388_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_2_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 4, numwords_a => 12, width_b => 24, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq, address_a => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa, data_a => ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia ); ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(23 downto 0); --prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MULT,464)@32 prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr <= UNSIGNED(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) * UNSIGNED(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b); prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= (others => '0'); prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= (others => '0'); prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_reg_oSqrtFPLFrac_uid74_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q; prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_add_one_fracY_uid428_uid429_uid429_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_pr); END IF; END IF; END PROCESS; prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,465)@35 normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(47 downto 47); --roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest(CONSTANT,200) roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q <= "010"; --fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,467)@35 fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(46 downto 0); fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(46 downto 23); --fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,468)@35 fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(45 downto 0); fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(45 downto 22); --fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,469)@35 fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b) BEGIN CASE fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= fracRPostNormLow_uid469_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; WHEN "1" => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= fracRPostNormHigh_uid468_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,477)@35 FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(1 downto 0); FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(1 downto 0); --Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,471)@35 Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(22 downto 0); Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(22 downto 22); --extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,472)@35 extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, GND_q, Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b) BEGIN CASE extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= Prod22_uid472_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,470)@35 stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= prod_uid465_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(21 downto 0); stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(21 downto 0); --stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,473)@35 stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= extraStickyBit_uid473_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & stickyRange_uid471_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,475)@35 stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= stickyExtendedRange_uid474_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,476)@35 sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= stickyRangeComparator_uid476_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,478)@35 lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= FracRPostNorm1dto0_uid478_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b & sticky_uid477_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,480)@35 roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= lrs_uid479_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q; roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "1" when roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a = roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b else "0"; --roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,481)@35 roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= roundBitDetectionPattern_uid481_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,484)@35 roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= GND_q & normalizeBit_uid466_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b & cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q & roundBit_uid482_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,670)@35 reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --biasInc_uid184_rAcosPi_uid13_fpArccosPiTest(CONSTANT,183) biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q <= "0001111111"; --reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,668)@31 reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1511) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_a or ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_b); --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1512) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1513) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_b; --ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1502) ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 12, width_b => 8, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq, address_a => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_aa, data_a => ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_ia ); ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(7 downto 0); --expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest(ADD,461)@32 expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & ld_reg_SqrtFPL30dto23_uid75_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_replace_mem_q); expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & reg_expY_uid423_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q); expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(8 downto 0); --ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1175)@33 ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest(SUB,463)@34 expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid462_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q); expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q(9)) & biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q); expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(10 downto 0); --expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,482)@35 expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expSumMBias_uid464_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & fracRPostNorm_uid470_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0(REG,669)@35 reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest(ADD,485)@36 expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q(34)) & reg_expFracPreRound_uid483_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q); expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid485_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q); expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) + SIGNED(expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(35 downto 0); --expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,487)@36 expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(35 downto 24); --expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,488)@36 expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(7 downto 0); expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(7 downto 0); --ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a(DELAY,1409)@36 ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b, xout => ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3(REG,678)@37 reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= ld_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_to_reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_a_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1247)@32 ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,671)@36 reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest(COMPARE,492)@37 expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin <= GND_q; expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q) & '0'; expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) & expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin(0); expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n(0) <= not expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(14); --InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,457)@32 InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_N_uid457_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,458)@32 InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,459)@31 InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; END IF; END PROCESS; --exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,460)@32 exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid460_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid459_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid458_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1217)@32 ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1153)@19 ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,441)@31 InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_N_uid441_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,442)@31 InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,443)@19 InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a; --ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1156)@19 ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,444)@31 exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_InvExpXIsZero_uid444_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid443_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid442_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1216)@31 ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 6 ) PORT MAP ( xin => exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,501)@37 ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= expOvf_uid493_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n; ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1223)@31 ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,500)@32 excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1234)@32 ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2(REG,664)@31 reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q <= exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,499)@32 excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1233)@32 ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,498)@32 excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_I_uid439_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_I_uid455_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1232)@32 ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,502)@37 excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_excXIAndExcYI_uid499_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_excXRAndExcYI_uid500_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ld_excYRAndExcXI_uid501_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d <= ExcROvfAndInReg_uid502_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c or excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d; --expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest(COMPARE,490)@37 expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin <= GND_q; expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid488_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q) & expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_cin(0); expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a) - SIGNED(expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b)); expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n(0) <= not expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_o(14); --excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,496)@37 excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= expUdf_uid491_arcsinL_uid87_acosX_uid8_fpArccosPiTest_n; excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b and excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c; --excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,495)@32 excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_exc_R_uid445_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c(DELAY,1221)@32 ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,494)@32 excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= exc_R_uid461_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b(DELAY,1220)@32 ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1(REG,658)@19 reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q <= expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1210)@20 ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q, xout => ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,493)@32 excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_reg_expXIsZero_uid434_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_1_q_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= reg_expXIsZero_uid450_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_2_q; excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a and excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; --ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a(DELAY,1219)@32 ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOGICAL,497)@37 excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a <= ld_excXZAndExcYZ_uid494_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= ld_excXZAndExcYR_uid495_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c <= ld_excYZAndExcXR_uid496_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d <= excZC3_uid497_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_a or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c or excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d; --concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,507)@37 concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_excRNaN_uid507_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q & excRInf_uid503_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & excRZero_uid498_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0(REG,676)@37 reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q <= concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest(LOOKUP,508)@38 excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid508_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_q) IS WHEN "000" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "001" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "010" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "011" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "100" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "101" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "110" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "111" => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN OTHERS => excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,517)@38 expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= reg_expRPreExc_uid489_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITSELECT,486)@36 fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in <= expFracRPostRounding_uid486_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(23 downto 0); fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b <= fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_in(23 downto 1); --reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3(REG,677)@36 reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q <= fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d(DELAY,1250)@37 ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q, xout => ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest(MUX,512)@38 fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s <= excREnc_uid509_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_reg_fracRPreExc_uid487_arcsinL_uid87_acosX_uid8_fpArccosPiTest_0_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_3_q_to_fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_d_q; WHEN "10" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest(BITJOIN,520)@38 R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q <= ld_signRPostExc_uid520_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_c_q & expRPostExc_uid518_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q & fracRPostExc_uid513_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q; --ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest(BITSELECT,87)@38 ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in <= R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(22 downto 0); ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b <= ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_in(22 downto 0); --oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest(BITJOIN,88)@38 oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q <= VCC_q & ArcsinL22dto0_uid88_acosX_uid8_fpArccosPiTest_b; --X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,526)@38 X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q; X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 16); --rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,528)@38 rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx1Pad16_uid246_fxpX_uid59_acosX_uid8_fpArccosPiTest_q & X23dto16_uid527_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4(REG,683)@38 reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q <= rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,523)@38 X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q; X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(23 downto 8); --rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITJOIN,525)@38 rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q & X23dto8_uid524_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; --reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3(REG,682)@38 reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q <= rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2(REG,681)@38 reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q <= oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest(BITSELECT,89)@38 ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in <= R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q(30 downto 0); ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b <= ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_in(30 downto 23); --srValArcsinL_uid91_acosX_uid8_fpArccosPiTest(SUB,90)@38 srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & ArcsinL30dto23_uid90_acosX_uid8_fpArccosPiTest_b); srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_b)); srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q <= srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_o(8 downto 0); --srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest(BITSELECT,91)@38 srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in <= srValArcsinL_uid91_acosX_uid8_fpArccosPiTest_q(4 downto 0); srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,530)@38 rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b; rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(4 downto 3); --reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,680)@38 reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,531)@39 rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel4Dto3_uid531_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q, reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q, reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q, rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_oFracArcsinL_uid89_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx1_uid526_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= reg_rightShiftStage0Idx2_uid529_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_4_q; WHEN "11" => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0Idx3_uid386_alignSqrt_uid78_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,541)@38 rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(2 downto 1); --reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,684)@38 reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,542)@39 rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel2Dto1_uid542_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage0_uid532_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "01" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx1_uid535_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "10" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx2_uid538_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "11" => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1Idx3_uid541_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(BITSELECT,546)@38 rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in <= srValArcsinLRange_uid92_acosX_uid8_fpArccosPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b <= rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1(REG,685)@38 reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q <= rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest(MUX,547)@39 rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s <= reg_rightShiftStageSel0Dto0_uid547_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_0_to_rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_1_q; rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest: PROCESS (rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s, en, rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q, rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q) BEGIN CASE rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage1_uid543_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN "1" => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2Idx1_uid546_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest(BITJOIN,94)@39 pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q <= rightShiftStage2_uid548_alignArcsinL_uid93_acosX_uid8_fpArccosPiTest_q & STD_LOGIC_VECTOR((2 downto 1 => GND_q(0)) & GND_q); --reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1(REG,686)@39 reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q <= pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --pi_uid94_acosX_uid8_fpArccosPiTest(CONSTANT,93) pi_uid94_acosX_uid8_fpArccosPiTest_q <= "1100100100001111110110101010"; --path1NegCase_uid95_acosX_uid8_fpArccosPiTest(SUB,95)@40 path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & pi_uid94_acosX_uid8_fpArccosPiTest_q); path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_pad_fxpArcsinL_uid94_uid95_acosX_uid8_fpArccosPiTest_0_to_path1NegCase_uid95_acosX_uid8_fpArccosPiTest_1_q); path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCase_uid95_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(path1NegCase_uid95_acosX_uid8_fpArccosPiTest_b)); path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_o(28 downto 0); --path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest(BITSELECT,96)@40 path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(27 downto 0); path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_in(27 downto 27); --reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1(REG,687)@40 reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest(ADD,100)@41 path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q); path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00000000" & reg_path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_0_to_path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_1_q); path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_a) + UNSIGNED(path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_b)); path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q <= path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_o(8 downto 0); --path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest(BITSELECT,101)@41 path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in <= path1NegCaseExp_uid101_acosX_uid8_fpArccosPiTest_q(7 downto 0); path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b <= path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_in(7 downto 0); --path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest(BITSELECT,97)@40 path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(26 downto 0); path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b <= path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_in(26 downto 4); --path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest(BITSELECT,98)@40 path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in <= path1NegCase_uid95_acosX_uid8_fpArccosPiTest_q(25 downto 0); path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b <= path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_in(25 downto 3); --path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest(MUX,99)@40 path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s <= path1NegCaseN_uid97_acosX_uid8_fpArccosPiTest_b; path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= path1NegCaseFracLow_uid99_acosX_uid8_fpArccosPiTest_b; WHEN "1" => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= path1NegCaseFracHigh_uid98_acosX_uid8_fpArccosPiTest_b; WHEN OTHERS => path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest(BITJOIN,102)@41 path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q <= GND_q & path1NegCaseExpRange_uid102_acosX_uid8_fpArccosPiTest_b & path1NegCaseFrac_uid100_acosX_uid8_fpArccosPiTest_q; --ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg(DELAY,1461) ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q, xout => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c(DELAY,790)@38 ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 2 ) PORT MAP ( xin => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_inputreg_q, xout => ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor(LOGICAL,1458) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q <= not (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_a or ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_b); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top(CONSTANT,1454) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q <= "0100111"; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp(LOGICAL,1455) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_mem_top_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q); ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q <= "1" when ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_a = ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_b else "0"; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg(REG,1456) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena(REG,1459) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_nor_q = "1") THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd(LOGICAL,1460) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_sticky_ena_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b <= en; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_a and ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_b; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt(COUNTER,1450) -- every=1, low=0, high=39, step=1, init=1 ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i = 38 THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_eq = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i - 39; ELSE ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_i,6)); --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg(REG,1451) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux(MUX,1452) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s <= en; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux: PROCESS (ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s, ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q, ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; WHEN "1" => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem(DUALMEM,1449) ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0 <= areset; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia <= singX_uid17_acosX_uid8_fpArccosPiTest_b; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdreg_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_rdmux_q; ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 40, width_b => 1, widthad_b => 6, numwords_b => 40, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq, address_a => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_aa, data_a => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_ia ); ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_iq(0 downto 0); --path1ResFP_uid105_acosX_uid8_fpArccosPiTest(MUX,104)@41 path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_replace_mem_q; path1ResFP_uid105_acosX_uid8_fpArccosPiTest: PROCESS (path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s, en, ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q, path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q) BEGIN CASE path1ResFP_uid105_acosX_uid8_fpArccosPiTest_s IS WHEN "0" => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= ld_R_uid521_arcsinL_uid87_acosX_uid8_fpArccosPiTest_q_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_c_q; WHEN "1" => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= path1NegCaseUR_uid103_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest(BITSELECT,132)@41 Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in <= path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q(30 downto 0); Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b <= Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_in(30 downto 23); --reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2(REG,699)@41 reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q <= Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor(LOGICAL,1472) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q <= not (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_a or ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_b); --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top(CONSTANT,1468) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q <= "0100101"; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp(LOGICAL,1469) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_mem_top_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q); ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q <= "1" when ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_a = ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_b else "0"; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg(REG,1470) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena(REG,1473) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_nor_q = "1") THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd(LOGICAL,1474) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_sticky_ena_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b <= en; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_a and ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_b; --ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c(DELAY,812)@0 ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => singX_uid17_acosX_uid8_fpArccosPiTest_b, xout => ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --inputIsMax_uid60_acosX_uid8_fpArccosPiTest(BITSELECT,59)@1 inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in <= rightShiftStage2_uid275_fxpX_uid59_acosX_uid8_fpArccosPiTest_q; inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b <= inputIsMax_uid60_acosX_uid8_fpArccosPiTest_in(36 downto 36); --firstPath_uid62_acosX_uid8_fpArccosPiTest(BITSELECT,61)@1 firstPath_uid62_acosX_uid8_fpArccosPiTest_in <= y_uid61_acosX_uid8_fpArccosPiTest_b; firstPath_uid62_acosX_uid8_fpArccosPiTest_b <= firstPath_uid62_acosX_uid8_fpArccosPiTest_in(34 downto 34); --pathSelBits_uid126_acosX_uid8_fpArccosPiTest(BITJOIN,125)@1 pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_c_q & inputIsMax_uid60_acosX_uid8_fpArccosPiTest_b & firstPath_uid62_acosX_uid8_fpArccosPiTest_b; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg(DELAY,1462) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q, xout => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt(COUNTER,1464) -- every=1, low=0, high=37, step=1, init=1 ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i = 36 THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_eq = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i - 37; ELSE ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_i,6)); --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg(REG,1465) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux(MUX,1466) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s <= en; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s, ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q, ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q) BEGIN CASE ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_s IS WHEN "0" => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; WHEN "1" => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem(DUALMEM,1463) ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0 <= areset; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_inputreg_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 6, numwords_a => 38, width_b => 3, widthad_b => 6, numwords_b => 38, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq, address_a => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_aa, data_a => ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_ia ); ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_iq(2 downto 0); --fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest(LOOKUP,126)@41 fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_mem_q) IS WHEN "000" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "001" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "010" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "011" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "100" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "101" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "110" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "111" => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN OTHERS => fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; END IF; END PROCESS; --expRCalc_uid134_acosX_uid8_fpArccosPiTest(MUX,133)@42 expRCalc_uid134_acosX_uid8_fpArccosPiTest_s <= fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q; expRCalc_uid134_acosX_uid8_fpArccosPiTest: PROCESS (expRCalc_uid134_acosX_uid8_fpArccosPiTest_s, en, reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q, reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q, cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRCalc_uid134_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= reg_Path1ResFP30dto23_uid133_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= reg_Path2ResFP30dto23_uid132_acosX_uid8_fpArccosPiTest_0_to_expRCalc_uid134_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= cstBiasP1_uid26_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRCalc_uid134_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --cstAllZWE_uid21_acosX_uid8_fpArccosPiTest(CONSTANT,20) cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q <= "00000000"; --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor(LOGICAL,1485) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q <= not (ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_a or ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_b); --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena(REG,1486) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_nor_q = "1") THEN ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd(LOGICAL,1487) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_sticky_ena_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b <= en; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_a and ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_b; --fracXIsZero_uid47_acosX_uid8_fpArccosPiTest(LOGICAL,46)@0 fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a <= fracX_uid16_acosX_uid8_fpArccosPiTest_b; fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q); fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_b else "0"; --InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest(LOGICAL,47)@0 InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid47_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_a; --expEQ0_uid46_acosX_uid8_fpArccosPiTest(LOGICAL,45)@0 expEQ0_uid46_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b; expEQ0_uid46_acosX_uid8_fpArccosPiTest_b <= cstBias_uid22_acosX_uid8_fpArccosPiTest_q; expEQ0_uid46_acosX_uid8_fpArccosPiTest_q <= "1" when expEQ0_uid46_acosX_uid8_fpArccosPiTest_a = expEQ0_uid46_acosX_uid8_fpArccosPiTest_b else "0"; --expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest(LOGICAL,48)@0 expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a <= expEQ0_uid46_acosX_uid8_fpArccosPiTest_q; expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid48_acosX_uid8_fpArccosPiTest_q; expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q <= expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_a and expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_b; --expGT0_uid45_acosX_uid8_fpArccosPiTest(COMPARE,44)@0 expGT0_uid45_acosX_uid8_fpArccosPiTest_cin <= GND_q; expGT0_uid45_acosX_uid8_fpArccosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid22_acosX_uid8_fpArccosPiTest_q) & '0'; expGT0_uid45_acosX_uid8_fpArccosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_acosX_uid8_fpArccosPiTest_b) & expGT0_uid45_acosX_uid8_fpArccosPiTest_cin(0); expGT0_uid45_acosX_uid8_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid45_acosX_uid8_fpArccosPiTest_a) - UNSIGNED(expGT0_uid45_acosX_uid8_fpArccosPiTest_b)); expGT0_uid45_acosX_uid8_fpArccosPiTest_c(0) <= expGT0_uid45_acosX_uid8_fpArccosPiTest_o(10); --inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest(LOGICAL,49)@0 inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a <= expGT0_uid45_acosX_uid8_fpArccosPiTest_c; inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b <= expXZFracNotZero_uid49_acosX_uid8_fpArccosPiTest_q; inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q <= inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_a or inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_b; --InvExc_N_uid41_acosX_uid8_fpArccosPiTest(LOGICAL,40)@0 InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a <= exc_N_uid40_acosX_uid8_fpArccosPiTest_q; InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q <= not InvExc_N_uid41_acosX_uid8_fpArccosPiTest_a; --InvExc_I_uid42_acosX_uid8_fpArccosPiTest(LOGICAL,41)@0 InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a <= exc_I_uid38_acosX_uid8_fpArccosPiTest_q; InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q <= not InvExc_I_uid42_acosX_uid8_fpArccosPiTest_a; --expXIsZero_uid33_acosX_uid8_fpArccosPiTest(LOGICAL,32)@0 expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b; expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsZero_uid33_acosX_uid8_fpArccosPiTest_a = expXIsZero_uid33_acosX_uid8_fpArccosPiTest_b else "0"; --InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest(LOGICAL,42)@0 InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a <= expXIsZero_uid33_acosX_uid8_fpArccosPiTest_q; InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q <= not InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_a; --exc_R_uid44_acosX_uid8_fpArccosPiTest(LOGICAL,43)@0 exc_R_uid44_acosX_uid8_fpArccosPiTest_a <= InvExpXIsZero_uid43_acosX_uid8_fpArccosPiTest_q; exc_R_uid44_acosX_uid8_fpArccosPiTest_b <= InvExc_I_uid42_acosX_uid8_fpArccosPiTest_q; exc_R_uid44_acosX_uid8_fpArccosPiTest_c <= InvExc_N_uid41_acosX_uid8_fpArccosPiTest_q; exc_R_uid44_acosX_uid8_fpArccosPiTest_q <= exc_R_uid44_acosX_uid8_fpArccosPiTest_a and exc_R_uid44_acosX_uid8_fpArccosPiTest_b and exc_R_uid44_acosX_uid8_fpArccosPiTest_c; --xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest(LOGICAL,134)@0 xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a <= exc_R_uid44_acosX_uid8_fpArccosPiTest_q; xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b <= inputOutOfRange_uid50_acosX_uid8_fpArccosPiTest_q; xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q <= xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_a and xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_b; --fracXIsZero_uid37_acosX_uid8_fpArccosPiTest(LOGICAL,36)@0 fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a <= fracX_uid16_acosX_uid8_fpArccosPiTest_b; fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q <= "1" when fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_a = fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_b else "0"; --expXIsMax_uid35_acosX_uid8_fpArccosPiTest(LOGICAL,34)@0 expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a <= expX_uid15_acosX_uid8_fpArccosPiTest_b; expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q <= "1" when expXIsMax_uid35_acosX_uid8_fpArccosPiTest_a = expXIsMax_uid35_acosX_uid8_fpArccosPiTest_b else "0"; --exc_I_uid38_acosX_uid8_fpArccosPiTest(LOGICAL,37)@0 exc_I_uid38_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q; exc_I_uid38_acosX_uid8_fpArccosPiTest_b <= fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q; exc_I_uid38_acosX_uid8_fpArccosPiTest_q <= exc_I_uid38_acosX_uid8_fpArccosPiTest_a and exc_I_uid38_acosX_uid8_fpArccosPiTest_b; --InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest(LOGICAL,38)@0 InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a <= fracXIsZero_uid37_acosX_uid8_fpArccosPiTest_q; InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q <= not InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_a; --exc_N_uid40_acosX_uid8_fpArccosPiTest(LOGICAL,39)@0 exc_N_uid40_acosX_uid8_fpArccosPiTest_a <= expXIsMax_uid35_acosX_uid8_fpArccosPiTest_q; exc_N_uid40_acosX_uid8_fpArccosPiTest_b <= InvFracXIsZero_uid39_acosX_uid8_fpArccosPiTest_q; exc_N_uid40_acosX_uid8_fpArccosPiTest_q <= exc_N_uid40_acosX_uid8_fpArccosPiTest_a and exc_N_uid40_acosX_uid8_fpArccosPiTest_b; --excRNaN_uid136_acosX_uid8_fpArccosPiTest(LOGICAL,135)@0 excRNaN_uid136_acosX_uid8_fpArccosPiTest_a <= exc_N_uid40_acosX_uid8_fpArccosPiTest_q; excRNaN_uid136_acosX_uid8_fpArccosPiTest_b <= exc_I_uid38_acosX_uid8_fpArccosPiTest_q; excRNaN_uid136_acosX_uid8_fpArccosPiTest_c <= xRegAndOutOfRange_uid135_acosX_uid8_fpArccosPiTest_q; excRNaN_uid136_acosX_uid8_fpArccosPiTest_q <= excRNaN_uid136_acosX_uid8_fpArccosPiTest_a or excRNaN_uid136_acosX_uid8_fpArccosPiTest_b or excRNaN_uid136_acosX_uid8_fpArccosPiTest_c; --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg(DELAY,1475) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => excRNaN_uid136_acosX_uid8_fpArccosPiTest_q, xout => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem(DUALMEM,1476) ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0 <= areset; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_inputreg_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdreg_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab <= ld_pathSelBits_uid126_acosX_uid8_fpArccosPiTest_q_to_fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_a_replace_rdmux_q; ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 38, width_b => 1, widthad_b => 6, numwords_b => 38, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq, address_a => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_aa, data_a => ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_ia ); ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_iq(0 downto 0); --excSelBits_uid137_acosX_uid8_fpArccosPiTest(BITJOIN,136)@40 excSelBits_uid137_acosX_uid8_fpArccosPiTest_q <= ld_excRNaN_uid136_acosX_uid8_fpArccosPiTest_q_to_excSelBits_uid137_acosX_uid8_fpArccosPiTest_c_replace_mem_q & GND_q & GND_q; --reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0(REG,608)@40 reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q <= excSelBits_uid137_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest(LOOKUP,137)@41 outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest: PROCESS (reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_excSelBits_uid137_acosX_uid8_fpArccosPiTest_0_to_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1(REG,701)@41 reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q <= outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q; END IF; END IF; END PROCESS; --expRPostExc_uid140_acosX_uid8_fpArccosPiTest(MUX,139)@42 expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s <= reg_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_0_to_expRPostExc_uid140_acosX_uid8_fpArccosPiTest_1_q; expRPostExc_uid140_acosX_uid8_fpArccosPiTest: PROCESS (expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, expRCalc_uid134_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid140_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= expRCalc_uid134_acosX_uid8_fpArccosPiTest_q; WHEN "10" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --piF_uid128_acosX_uid8_fpArccosPiTest(BITSELECT,127)@42 piF_uid128_acosX_uid8_fpArccosPiTest_in <= pi_uid94_acosX_uid8_fpArccosPiTest_q(26 downto 0); piF_uid128_acosX_uid8_fpArccosPiTest_b <= piF_uid128_acosX_uid8_fpArccosPiTest_in(26 downto 4); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor(LOGICAL,1613) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a <= ld_singX_uid17_acosX_uid8_fpArccosPiTest_b_to_path1ResFP_uid105_acosX_uid8_fpArccosPiTest_b_notEnable_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q <= not (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_a or ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_b); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena(REG,1614) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_nor_q = "1") THEN ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd(LOGICAL,1615) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_sticky_ena_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b <= en; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_a and ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_b; --Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest(BITSELECT,128)@13 Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in <= path2ResFP_uid125_acosX_uid8_fpArccosPiTest_q(22 downto 0); Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b <= Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_in(22 downto 0); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg(DELAY,1603) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b, xout => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem(DUALMEM,1604) ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0 <= areset; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_inputreg_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdreg_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_rdmux_q; ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 5, numwords_a => 26, width_b => 23, widthad_b => 5, numwords_b => 26, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_reset0, clock1 => clk, address_b => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq, address_a => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_aa, data_a => ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_ia ); ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_iq(22 downto 0); --reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3(REG,698)@41 reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q <= ld_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_b_to_reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_a_replace_mem_q; END IF; END IF; END PROCESS; --Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest(BITSELECT,129)@41 Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in <= path1ResFP_uid105_acosX_uid8_fpArccosPiTest_q(22 downto 0); Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b <= Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_in(22 downto 0); --reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2(REG,697)@41 reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q <= Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_b; END IF; END IF; END PROCESS; --fracRCalc_uid131_acosX_uid8_fpArccosPiTest(MUX,130)@42 fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s <= fracOutMuxSelEnc_uid127_acosX_uid8_fpArccosPiTest_q; fracRCalc_uid131_acosX_uid8_fpArccosPiTest: PROCESS (fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s, en, reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q, reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q, piF_uid128_acosX_uid8_fpArccosPiTest_b, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRCalc_uid131_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= reg_Path1ResFP22dto0_uid130_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_2_q; WHEN "01" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= reg_Path2ResFP22dto0_uid129_acosX_uid8_fpArccosPiTest_0_to_fracRCalc_uid131_acosX_uid8_fpArccosPiTest_3_q; WHEN "10" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= piF_uid128_acosX_uid8_fpArccosPiTest_b; WHEN "11" => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b(DELAY,832)@41 ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q, xout => ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid139_acosX_uid8_fpArccosPiTest(MUX,138)@42 fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s <= ld_outMuxSelEnc_uid138_acosX_uid8_fpArccosPiTest_q_to_fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_b_q; fracRPostExc_uid139_acosX_uid8_fpArccosPiTest: PROCESS (fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= fracRCalc_uid131_acosX_uid8_fpArccosPiTest_q; WHEN "10" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --sR_uid141_acosX_uid8_fpArccosPiTest(BITJOIN,140)@42 sR_uid141_acosX_uid8_fpArccosPiTest_q <= GND_q & expRPostExc_uid140_acosX_uid8_fpArccosPiTest_q & fracRPostExc_uid139_acosX_uid8_fpArccosPiTest_q; --fracX_uid147_rAcosPi_uid13_fpArccosPiTest(BITSELECT,146)@42 fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q(22 downto 0); fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b <= fracX_uid147_rAcosPi_uid13_fpArccosPiTest_in(22 downto 0); --fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest(LOGICAL,158)@42 fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a <= fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b; fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q <= "1" when fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_a = fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_b else "0"; --expX_uid143_rAcosPi_uid13_fpArccosPiTest(BITSELECT,142)@42 expX_uid143_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q(30 downto 0); expX_uid143_rAcosPi_uid13_fpArccosPiTest_b <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_in(30 downto 23); --expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest(LOGICAL,156)@42 expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_b; expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_a = expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_b else "0"; --exc_I_uid160_rAcosPi_uid13_fpArccosPiTest(LOGICAL,159)@42 exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b <= fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_a and exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_b; --ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a(DELAY,1442)@42 ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2(REG,711)@43 reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q <= ld_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q_to_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_a_q; END IF; END IF; END PROCESS; --ooPi_uid9_fpArccosPiTest(CONSTANT,8) ooPi_uid9_fpArccosPiTest_q <= "101000101111100110000011"; --fracOOPi_uid10_fpArccosPiTest(BITSELECT,9)@43 fracOOPi_uid10_fpArccosPiTest_in <= ooPi_uid9_fpArccosPiTest_q(22 downto 0); fracOOPi_uid10_fpArccosPiTest_b <= fracOOPi_uid10_fpArccosPiTest_in(22 downto 0); --fpOOPi_uid11_fpArccosPiTest(BITJOIN,10)@43 fpOOPi_uid11_fpArccosPiTest_q <= GND_q & cstBiasM2_uid6_fpArccosPiTest_q & fracOOPi_uid10_fpArccosPiTest_b; --expY_uid144_rAcosPi_uid13_fpArccosPiTest(BITSELECT,143)@43 expY_uid144_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q(30 downto 0); expY_uid144_rAcosPi_uid13_fpArccosPiTest_b <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_in(30 downto 23); --expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest(LOGICAL,170)@43 expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_b; expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_a = expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_b else "0"; --reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1(REG,710)@43 reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest(LOGICAL,224)@44 excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a <= reg_expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_1_q; excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b <= reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_2_q; excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q <= excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_a and excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_b; --fracY_uid149_rAcosPi_uid13_fpArccosPiTest(BITSELECT,148)@43 fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q(22 downto 0); fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b <= fracY_uid149_rAcosPi_uid13_fpArccosPiTest_in(22 downto 0); --fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest(LOGICAL,174)@43 fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a <= fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b; fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q <= "1" when fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_a = fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_b else "0"; --expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest(LOGICAL,172)@43 expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a <= expY_uid144_rAcosPi_uid13_fpArccosPiTest_b; expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_a = expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_b else "0"; --exc_I_uid176_rAcosPi_uid13_fpArccosPiTest(LOGICAL,175)@43 exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b <= fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q; exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_a and exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_b; --expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest(LOGICAL,154)@42 expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a <= expX_uid143_rAcosPi_uid13_fpArccosPiTest_b; expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q <= "1" when expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_a = expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_b else "0"; --ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a(DELAY,911)@42 ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest(LOGICAL,225)@43 excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q; excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_b; END IF; END PROCESS; --ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest(LOGICAL,226)@44 ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a <= excXZAndExcYI_uid226_rAcosPi_uid13_fpArccosPiTest_q; ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b <= excYZAndExcXI_uid225_rAcosPi_uid13_fpArccosPiTest_q; ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q <= ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_a or ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_b; --InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest(LOGICAL,176)@43 InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a <= fracXIsZero_uid175_rAcosPi_uid13_fpArccosPiTest_q; InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q <= not InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_a; --exc_N_uid178_rAcosPi_uid13_fpArccosPiTest(LOGICAL,177)@43 exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid173_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b <= InvFracXIsZero_uid177_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_a and exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_b; --reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2(REG,713)@43 reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest(LOGICAL,160)@42 InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a <= fracXIsZero_uid159_rAcosPi_uid13_fpArccosPiTest_q; InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q <= not InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_a; --exc_N_uid162_rAcosPi_uid13_fpArccosPiTest(LOGICAL,161)@42 exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a <= expXIsMax_uid157_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b <= InvFracXIsZero_uid161_rAcosPi_uid13_fpArccosPiTest_q; exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_a and exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_b; --reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1(REG,712)@42 reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a(DELAY,943)@43 ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q, xout => ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest(LOGICAL,227)@44 excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a <= ld_reg_exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_1_q_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a_q; excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b <= reg_exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_0_to_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_2_q; excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c <= ZeroTimesInf_uid227_rAcosPi_uid13_fpArccosPiTest_q; excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q <= excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_a or excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_b or excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_c; --VCC(CONSTANT,1) VCC_q <= "1"; --InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest(LOGICAL,239)@44 InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a <= excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q; InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q <= not InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_a; --signY_uid146_rAcosPi_uid13_fpArccosPiTest(BITSELECT,145)@43 signY_uid146_rAcosPi_uid13_fpArccosPiTest_in <= fpOOPi_uid11_fpArccosPiTest_q; signY_uid146_rAcosPi_uid13_fpArccosPiTest_b <= signY_uid146_rAcosPi_uid13_fpArccosPiTest_in(31 downto 31); --signX_uid145_rAcosPi_uid13_fpArccosPiTest(BITSELECT,144)@42 signX_uid145_rAcosPi_uid13_fpArccosPiTest_in <= sR_uid141_acosX_uid8_fpArccosPiTest_q; signX_uid145_rAcosPi_uid13_fpArccosPiTest_b <= signX_uid145_rAcosPi_uid13_fpArccosPiTest_in(31 downto 31); --ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a(DELAY,907)@42 ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid145_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signR_uid211_rAcosPi_uid13_fpArccosPiTest(LOGICAL,210)@43 signR_uid211_rAcosPi_uid13_fpArccosPiTest_a <= ld_signX_uid145_rAcosPi_uid13_fpArccosPiTest_b_to_signR_uid211_rAcosPi_uid13_fpArccosPiTest_a_q; signR_uid211_rAcosPi_uid13_fpArccosPiTest_b <= signY_uid146_rAcosPi_uid13_fpArccosPiTest_b; signR_uid211_rAcosPi_uid13_fpArccosPiTest_q <= signR_uid211_rAcosPi_uid13_fpArccosPiTest_a xor signR_uid211_rAcosPi_uid13_fpArccosPiTest_b; --ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a(DELAY,955)@43 ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid211_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest(LOGICAL,240)@44 signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a <= ld_signR_uid211_rAcosPi_uid13_fpArccosPiTest_q_to_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a_q; signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b <= InvExcRNaN_uid240_rAcosPi_uid13_fpArccosPiTest_q; signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q <= signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_a and signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_b; END IF; END PROCESS; --ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c(DELAY,959)@45 ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest(BITJOIN,149)@43 add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q <= VCC_q & fracY_uid149_rAcosPi_uid13_fpArccosPiTest_b; --add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest(BITJOIN,147)@42 add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q <= VCC_q & fracX_uid147_rAcosPi_uid13_fpArccosPiTest_b; --reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0(REG,702)@42 reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q <= add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --prod_uid186_rAcosPi_uid13_fpArccosPiTest(MULT,185)@43 prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr <= UNSIGNED(prod_uid186_rAcosPi_uid13_fpArccosPiTest_a) * UNSIGNED(prod_uid186_rAcosPi_uid13_fpArccosPiTest_b); prod_uid186_rAcosPi_uid13_fpArccosPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_a <= (others => '0'); prod_uid186_rAcosPi_uid13_fpArccosPiTest_b <= (others => '0'); prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_a <= reg_add_one_fracX_uid147_uid148_uid148_rAcosPi_uid13_fpArccosPiTest_0_to_prod_uid186_rAcosPi_uid13_fpArccosPiTest_0_q; prod_uid186_rAcosPi_uid13_fpArccosPiTest_b <= add_one_fracY_uid149_uid150_uid150_rAcosPi_uid13_fpArccosPiTest_q; prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid186_rAcosPi_uid13_fpArccosPiTest_pr); END IF; END IF; END PROCESS; prod_uid186_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid186_rAcosPi_uid13_fpArccosPiTest_q <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest(BITSELECT,186)@46 normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q; normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_in(47 downto 47); --fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest(BITSELECT,188)@46 fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(46 downto 0); fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b <= fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_in(46 downto 23); --fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest(BITSELECT,189)@46 fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(45 downto 0); fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b <= fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_in(45 downto 22); --fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest(MUX,190)@46 fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b; fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest: PROCESS (fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s, en, fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b, fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b) BEGIN CASE fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "0" => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= fracRPostNormLow_uid190_rAcosPi_uid13_fpArccosPiTest_b; WHEN "1" => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= fracRPostNormHigh_uid189_rAcosPi_uid13_fpArccosPiTest_b; WHEN OTHERS => fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest(BITSELECT,198)@46 FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in <= fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q(1 downto 0); FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b <= FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_in(1 downto 0); --Prod22_uid193_rAcosPi_uid13_fpArccosPiTest(BITSELECT,192)@46 Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(22 downto 0); Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b <= Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_in(22 downto 22); --extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest(MUX,193)@46 extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s <= normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b; extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest: PROCESS (extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s, en, GND_q, Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b) BEGIN CASE extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "0" => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= Prod22_uid193_rAcosPi_uid13_fpArccosPiTest_b; WHEN OTHERS => extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest(BITSELECT,191)@46 stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in <= prod_uid186_rAcosPi_uid13_fpArccosPiTest_q(21 downto 0); stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b <= stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_in(21 downto 0); --stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest(BITJOIN,194)@46 stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q <= extraStickyBit_uid194_rAcosPi_uid13_fpArccosPiTest_q & stickyRange_uid192_rAcosPi_uid13_fpArccosPiTest_b; --stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest(LOGICAL,196)@46 stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a <= stickyExtendedRange_uid195_rAcosPi_uid13_fpArccosPiTest_q; stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q <= "1" when stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_a = stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_b else "0"; --sticky_uid198_rAcosPi_uid13_fpArccosPiTest(LOGICAL,197)@46 sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a <= stickyRangeComparator_uid197_rAcosPi_uid13_fpArccosPiTest_q; sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q <= not sticky_uid198_rAcosPi_uid13_fpArccosPiTest_a; --lrs_uid200_rAcosPi_uid13_fpArccosPiTest(BITJOIN,199)@46 lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q <= FracRPostNorm1dto0_uid199_rAcosPi_uid13_fpArccosPiTest_b & sticky_uid198_rAcosPi_uid13_fpArccosPiTest_q; --roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest(LOGICAL,201)@46 roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a <= lrs_uid200_rAcosPi_uid13_fpArccosPiTest_q; roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b <= roundBitDetectionConstant_uid201_rAcosPi_uid13_fpArccosPiTest_q; roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q <= "1" when roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_a = roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_b else "0"; --roundBit_uid203_rAcosPi_uid13_fpArccosPiTest(LOGICAL,202)@46 roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a <= roundBitDetectionPattern_uid202_rAcosPi_uid13_fpArccosPiTest_q; roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q <= not roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_a; --roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest(BITJOIN,205)@46 roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q <= GND_q & normalizeBit_uid187_rAcosPi_uid13_fpArccosPiTest_b & cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q & roundBit_uid203_rAcosPi_uid13_fpArccosPiTest_q; --reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1(REG,704)@46 reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q <= roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a(DELAY,874)@42 ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expX_uid143_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSum_uid183_rAcosPi_uid13_fpArccosPiTest(ADD,182)@43 expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid143_rAcosPi_uid13_fpArccosPiTest_b_to_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a_q); expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR("0" & expY_uid144_rAcosPi_uid13_fpArccosPiTest_b); expSum_uid183_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid183_rAcosPi_uid13_fpArccosPiTest_a) + UNSIGNED(expSum_uid183_rAcosPi_uid13_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q <= expSum_uid183_rAcosPi_uid13_fpArccosPiTest_o(8 downto 0); --ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a(DELAY,876)@44 ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest(SUB,184)@45 expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid183_rAcosPi_uid13_fpArccosPiTest_q_to_expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a_q); expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q(9)) & biasInc_uid184_rAcosPi_uid13_fpArccosPiTest_q); expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q <= expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_o(10 downto 0); --expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest(BITJOIN,203)@46 expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q <= expSumMBias_uid185_rAcosPi_uid13_fpArccosPiTest_q & fracRPostNorm_uid191_rAcosPi_uid13_fpArccosPiTest_q; --reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0(REG,703)@46 reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q <= expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest(ADD,206)@47 expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q(34)) & reg_expFracPreRound_uid204_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_0_q); expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid206_rAcosPi_uid13_fpArccosPiTest_0_to_expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_1_q); expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_a) + SIGNED(expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_b)); expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_o(35 downto 0); --expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest(BITSELECT,208)@47 expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q; expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_in(35 downto 24); --expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest(BITSELECT,209)@47 expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b(7 downto 0); expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b <= expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_in(7 downto 0); --ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a(DELAY,1447)@47 ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b, xout => ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3(REG,716)@48 reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q <= ld_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_b_to_reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_a_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c(DELAY,948)@44 ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1(REG,705)@47 reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q <= expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid214_rAcosPi_uid13_fpArccosPiTest(COMPARE,213)@48 expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin <= GND_q; expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q) & '0'; expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) & expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_cin(0); expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_b)); expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n(0) <= not expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_o(14); --InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest(LOGICAL,178)@43 InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a <= exc_N_uid178_rAcosPi_uid13_fpArccosPiTest_q; InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_a; --InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest(LOGICAL,179)@43 InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_a; --InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest(LOGICAL,180)@43 InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q <= not InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_a; --exc_R_uid182_rAcosPi_uid13_fpArccosPiTest(LOGICAL,181)@43 exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a <= InvExpXIsZero_uid181_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b <= InvExc_I_uid180_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c <= InvExc_N_uid179_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_a and exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_b and exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_c; --ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b(DELAY,918)@43 ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest(LOGICAL,162)@42 InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a <= exc_N_uid162_rAcosPi_uid13_fpArccosPiTest_q; InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_a; END IF; END PROCESS; --InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest(LOGICAL,163)@42 InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q; InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q <= not InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_a; END IF; END PROCESS; --InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest(LOGICAL,164)@42 InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q; InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q <= not InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_a; END IF; END PROCESS; --exc_R_uid166_rAcosPi_uid13_fpArccosPiTest(LOGICAL,165)@43 exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a <= InvExpXIsZero_uid165_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b <= InvExc_I_uid164_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c <= InvExc_N_uid163_rAcosPi_uid13_fpArccosPiTest_q; exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_a and exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_b and exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_c; --ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a(DELAY,917)@43 ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest(LOGICAL,222)@48 ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a <= ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q; ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b <= ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q; ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c <= expOvf_uid214_rAcosPi_uid13_fpArccosPiTest_n; ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q <= ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_a and ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_b and ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_c; --reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1(REG,706)@42 reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b(DELAY,929)@43 ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q, xout => ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1(REG,707)@43 reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest(LOGICAL,221)@44 excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a <= reg_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_1_q; excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b <= ld_reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_2_q_to_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b_q; excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q <= excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_a and excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_b; --ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c(DELAY,935)@44 ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest(LOGICAL,220)@43 excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q; excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q <= excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_a and excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b(DELAY,934)@43 ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest(LOGICAL,219)@43 excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a <= reg_exc_I_uid160_rAcosPi_uid13_fpArccosPiTest_0_to_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_1_q; excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b <= exc_I_uid176_rAcosPi_uid13_fpArccosPiTest_q; excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q <= excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_a and excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a(DELAY,933)@43 ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid224_rAcosPi_uid13_fpArccosPiTest(LOGICAL,223)@48 excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a <= ld_excXIAndExcYI_uid220_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b <= ld_excXRAndExcYI_uid221_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c <= ld_excYRAndExcXI_uid222_rAcosPi_uid13_fpArccosPiTest_q_to_excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d <= ExcROvfAndInReg_uid223_rAcosPi_uid13_fpArccosPiTest_q; excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q <= excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_a or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_b or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_c or excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_d; --expUdf_uid212_rAcosPi_uid13_fpArccosPiTest(COMPARE,211)@48 expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin <= GND_q; expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q(11)) & reg_expRPreExcExt_uid209_rAcosPi_uid13_fpArccosPiTest_0_to_expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_1_q) & expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_cin(0); expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_a) - SIGNED(expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_b)); expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n(0) <= not expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_o(14); --excZC3_uid218_rAcosPi_uid13_fpArccosPiTest(LOGICAL,217)@48 excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a <= ld_exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a_q; excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b <= ld_exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q_to_excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b_q; excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c <= expUdf_uid212_rAcosPi_uid13_fpArccosPiTest_n; excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q <= excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_a and excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_b and excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_c; --excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest(LOGICAL,216)@43 excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b <= exc_R_uid166_rAcosPi_uid13_fpArccosPiTest_q; excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q <= excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_a and excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_b; --ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c(DELAY,922)@43 ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest(LOGICAL,215)@43 excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q; excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b <= exc_R_uid182_rAcosPi_uid13_fpArccosPiTest_q; excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b(DELAY,921)@43 ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest(LOGICAL,214)@43 excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a <= ld_expXIsZero_uid155_rAcosPi_uid13_fpArccosPiTest_q_to_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a_q; excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b <= expXIsZero_uid171_rAcosPi_uid13_fpArccosPiTest_q; excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q <= excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_a and excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_b; --ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a(DELAY,920)@43 ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q, xout => ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid219_rAcosPi_uid13_fpArccosPiTest(LOGICAL,218)@48 excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a <= ld_excXZAndExcYZ_uid215_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b <= ld_excXZAndExcYR_uid216_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c <= ld_excYZAndExcXR_uid217_rAcosPi_uid13_fpArccosPiTest_q_to_excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d <= excZC3_uid218_rAcosPi_uid13_fpArccosPiTest_q; excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q <= excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_a or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_b or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_c or excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_d; --concExc_uid229_rAcosPi_uid13_fpArccosPiTest(BITJOIN,228)@48 concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q <= ld_excRNaN_uid228_rAcosPi_uid13_fpArccosPiTest_q_to_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_c_q & excRInf_uid224_rAcosPi_uid13_fpArccosPiTest_q & excRZero_uid219_rAcosPi_uid13_fpArccosPiTest_q; --reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0(REG,714)@48 reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q <= concExc_uid229_rAcosPi_uid13_fpArccosPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid230_rAcosPi_uid13_fpArccosPiTest(LOOKUP,229)@49 excREnc_uid230_rAcosPi_uid13_fpArccosPiTest: PROCESS (reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid229_rAcosPi_uid13_fpArccosPiTest_0_to_excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_0_q) IS WHEN "000" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "01"; WHEN "001" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "010" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "10"; WHEN "011" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "100" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "11"; WHEN "101" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "110" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN "111" => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= "00"; WHEN OTHERS => excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest(MUX,238)@49 expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s <= excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q; expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest: PROCESS (expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s, en, cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q, reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q, cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q) BEGIN CASE expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "00" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWE_uid21_acosX_uid8_fpArccosPiTest_q; WHEN "01" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= reg_expRPreExc_uid210_rAcosPi_uid13_fpArccosPiTest_0_to_expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_3_q; WHEN "10" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN "11" => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= cstAllOWE_uid18_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest(BITSELECT,207)@47 fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in <= expFracRPostRounding_uid207_rAcosPi_uid13_fpArccosPiTest_q(23 downto 0); fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b <= fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_in(23 downto 1); --reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3(REG,715)@47 reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q <= fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d(DELAY,951)@48 ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q, xout => ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest(MUX,233)@49 fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s <= excREnc_uid230_rAcosPi_uid13_fpArccosPiTest_q; fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest: PROCESS (fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s, en, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q, cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q, cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q) BEGIN CASE fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_s IS WHEN "00" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "01" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= ld_reg_fracRPreExc_uid208_rAcosPi_uid13_fpArccosPiTest_0_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_3_q_to_fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_d_q; WHEN "10" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstAllZWF_uid19_acosX_uid8_fpArccosPiTest_q; WHEN "11" => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= cstNaNWF_uid20_acosX_uid8_fpArccosPiTest_q; WHEN OTHERS => fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid242_rAcosPi_uid13_fpArccosPiTest(BITJOIN,241)@49 R_uid242_rAcosPi_uid13_fpArccosPiTest_q <= ld_signRPostExc_uid241_rAcosPi_uid13_fpArccosPiTest_q_to_R_uid242_rAcosPi_uid13_fpArccosPiTest_c_q & expRPostExc_uid239_rAcosPi_uid13_fpArccosPiTest_q & fracRPostExc_uid234_rAcosPi_uid13_fpArccosPiTest_q; --xOut(GPOUT,4)@49 q <= R_uid242_rAcosPi_uid13_fpArccosPiTest_q; end normal;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_lsft36.vhd

10

4582

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_LSFT36.VHD *** --*** *** --*** Function: 36 bit Left Shift *** --*** *** --*** 22/12/09 ML *** --*** *** --*** (c) 2009 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_lsft36 IS PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); END fp_lsft36; ARCHITECTURE sft OF fp_lsft36 IS signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (36 DOWNTO 1); BEGIN levzip <= inbus; -- shift by 0,1,2,3 levone(1) <= (levzip(1) AND NOT(shift(2)) AND NOT(shift(1))); levone(2) <= (levzip(2) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(1) AND NOT(shift(2)) AND shift(1)); levone(3) <= (levzip(3) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(2) AND NOT(shift(2)) AND shift(1)) OR (levzip(1) AND shift(2) AND NOT(shift(1))); gaa: FOR k IN 4 TO 36 GENERATE levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(k-1) AND NOT(shift(2)) AND shift(1)) OR (levzip(k-2) AND shift(2) AND NOT(shift(1))) OR (levzip(k-3) AND shift(2) AND shift(1)); END GENERATE; -- shift by 0,4,8,12 gba: FOR k IN 1 TO 4 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))); END GENERATE; gbb: FOR k IN 5 TO 8 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k-4) AND NOT(shift(4)) AND shift(3)); END GENERATE; gbc: FOR k IN 9 TO 12 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k-4) AND NOT(shift(4)) AND shift(3)) OR (levone(k-8) AND shift(4) AND NOT(shift(3))); END GENERATE; gbd: FOR k IN 13 TO 36 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k-4) AND NOT(shift(4)) AND shift(3)) OR (levone(k-8) AND shift(4) AND NOT(shift(3))) OR (levone(k-12) AND shift(4) AND shift(3)); END GENERATE; -- shift by 0,16,32 gca: FOR k IN 1 TO 16 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))); END GENERATE; gcb: FOR k IN 17 TO 32 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k-16) AND NOT(shift(6)) AND shift(5)); END GENERATE; gcc: FOR k IN 33 TO 36 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k-16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(k-32) AND shift(6) AND NOT(shift(5))); END GENERATE; outbus <= levthr; END sft;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_ln_core.vhd

10

16472

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** SINGLE PRECISION LOG(e) - CORE *** --*** *** --*** FP_LN_CORE.VHD *** --*** *** --*** Function: Single Precision LOG (LN) Core *** --*** *** --*** 22/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** Notes: *** --*** Latency = 19 *** --*************************************************** ENTITY fp_ln_core IS GENERIC (synthesize : integer := 0); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aaman : IN STD_LOGIC_VECTOR (23 DOWNTO 1); aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); ccman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); ccsgn : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); END fp_ln_core; ARCHITECTURE rtl OF fp_ln_core IS signal zerovec : STD_LOGIC_VECTOR (32 DOWNTO 1); -- input signal aamanff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal aaexpff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal aaexppos, aaexpneg : STD_LOGIC_VECTOR (9 DOWNTO 1); signal aaexpabs, aaexpabsff : STD_LOGIC_VECTOR (7 DOWNTO 1); -- range reduction signal lutpowaddff : STD_LOGIC_VECTOR (7 DOWNTO 1); signal lutoneaddff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal lutpowmanff, lutonemanff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal lutpowexpff, lutoneexpff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal lutoneinvff : STD_LOGIC_VECTOR (11 DOWNTO 1); signal lutpowmannode, lutonemannode : STD_LOGIC_VECTOR (23 DOWNTO 1); signal lutpowexpnode, lutoneexpnode : STD_LOGIC_VECTOR (8 DOWNTO 1); signal lutoneinvnode : STD_LOGIC_VECTOR (11 DOWNTO 1); signal aanum, aanumdel : STD_LOGIC_VECTOR (24 DOWNTO 1); signal mulonenode : STD_LOGIC_VECTOR (35 DOWNTO 1); signal mulonenormff : STD_LOGIC_VECTOR (34 DOWNTO 1); -- series signal squared : STD_LOGIC_VECTOR (36 DOWNTO 1); signal cubed : STD_LOGIC_VECTOR (36 DOWNTO 1); signal scaled : STD_LOGIC_VECTOR (36 DOWNTO 1); signal onethird : STD_LOGIC_VECTOR (18 DOWNTO 1); signal mulonedel : STD_LOGIC_VECTOR (26 DOWNTO 1); signal oneterm, twoterm, thrterm : STD_LOGIC_VECTOR (32 DOWNTO 1); signal seriesoneff, seriesonedelff, seriestwoff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numtwo : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exptwo : STD_LOGIC_VECTOR (8 DOWNTO 1); -- addition signal zeroone, zeropow : STD_LOGIC; signal numberone, numberonedel : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numpow, numone : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numpowsigned : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exppow, expone : STD_LOGIC_VECTOR (8 DOWNTO 1); signal numpowone, numpowonedel : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exppowone, exppowonedel : STD_LOGIC_VECTOR (8 DOWNTO 1); signal numsum : STD_LOGIC_VECTOR (32 DOWNTO 1); signal numsumabs : STD_LOGIC_VECTOR (32 DOWNTO 1); signal expsum : STD_LOGIC_VECTOR (8 DOWNTO 1); signal ccmannode : STD_LOGIC_VECTOR (24 DOWNTO 1); signal ccexpnode : STD_LOGIC_VECTOR (8 DOWNTO 1); signal signff : STD_LOGIC_VECTOR (18 DOWNTO 1); component fp_lnlutpow PORT ( add : IN STD_LOGIC_VECTOR (7 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); end component; component fp_lnlut8 PORT ( add : IN STD_LOGIC_VECTOR (8 DOWNTO 1); inv : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); end component; component fp_del GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_fxmul GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_lnadd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aaman : IN STD_LOGIC_VECTOR (32 DOWNTO 1); aaexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); bbman : IN STD_LOGIC_VECTOR (32 DOWNTO 1); bbexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); ccman : OUT STD_LOGIC_VECTOR (32 DOWNTO 1); ccexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); end component; component fp_lnnorm PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inman : IN STD_LOGIC_VECTOR (32 DOWNTO 1); inexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); outman : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); outexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); zero : OUT STD_LOGIC ); end component; BEGIN gza: FOR k IN 1 TO 32 GENERATE zerovec(k) <= '0'; END GENERATE; --******************* --*** INPUT BLOCK *** --******************* ppin: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 23 LOOP aamanff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP aaexpff(k) <= '0'; END LOOP; FOR k IN 1 TO 7 LOOP aaexpabsff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aamanff <= aaman; -- level 1 aaexpff <= aaexp; -- level 1 aaexpabsff <= aaexpabs; -- level 2 END IF; END IF; END PROCESS; aaexppos <= ('0' & aaexpff) - "001111111"; aaexpneg <= "001111111" - ('0' & aaexpff); gaba: FOR k IN 1 TO 7 GENERATE aaexpabs(k) <= (aaexppos(k) AND NOT(aaexppos(9))) OR (aaexpneg(k) AND aaexppos(9)); END GENERATE; --****************************************** --*** RANGE REDUCTION THROUGH LUT SERIES *** --****************************************** plut: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 7 LOOP lutpowaddff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP lutoneaddff(k) <= '0'; END LOOP; FOR k IN 1 TO 23 LOOP lutpowmanff(k) <= '0'; lutonemanff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP lutpowexpff(k) <= '0'; lutoneexpff(k) <= '0'; END LOOP; FOR k IN 1 TO 11 LOOP lutoneinvff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN lutpowaddff <= aaexpabsff; -- level 3 lutoneaddff <= aamanff(23 DOWNTO 16); -- level 2 lutpowmanff <= lutpowmannode; -- level 4 lutpowexpff <= lutpowexpnode; -- level 4 lutoneinvff <= lutoneinvnode; -- level 3 lutonemanff <= lutonemannode; -- level 3 lutoneexpff <= lutoneexpnode; -- level 3 END IF; END IF; END PROCESS; lutpow: fp_lnlutpow PORT MAP (add=>lutpowaddff, logman=>lutpowmannode,logexp=>lutpowexpnode); lutone: fp_lnlut8 PORT MAP (add=>lutoneaddff, inv=>lutoneinvnode,logman=>lutonemannode,logexp=>lutoneexpnode); aanum <= '1' & aamanff; -- level 1 in, level 3 out delone: fp_del GENERIC MAP (width=>24,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aanum,cc=>aanumdel); --mulone <= aanum * invone; -- 24*11 = 35 -- level 3 in, level 6 out mulone: fp_fxmul GENERIC MAP (widthaa=>24,widthbb=>11,widthcc=>35, pipes=>3,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>aanumdel,databb=>lutoneinvff, result=>mulonenode); pmna: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 34 LOOP mulonenormff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN -- normalize in case input is 1.000000 and inv is 0.5 -- level 7 FOR k IN 1 TO 34 LOOP mulonenormff(k) <= (mulonenode(k+1) AND mulonenode(35)) OR (mulonenode(k) AND NOT(mulonenode(35))); END LOOP; END IF; END IF; END PROCESS; --*********************************************************** --*** taylor series expansion of subrange (15 bits) *** --*** x - x*x/2 *** --*** 7 leading bits, so x*x 7 bits down, +1 bit for 1/2 *** --*********************************************************** --square <= mulonenorm(25 DOWNTO 8) * mulonenorm(25 DOWNTO 8); --cubed <= square(36 DOWNTO 19) * mulonenorm(25 DOWNTO 8); --cubedscale <= cubed(36 DOWNTO 19) * onethird; onethird <= "010101010101010101"; -- level 7 in, level 9 out multwo: fp_fxmul GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36, pipes=>2,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>mulonenormff(26 DOWNTO 9),databb=>mulonenormff(26 DOWNTO 9), result=>squared); -- level 7 in, level 9 out multhr: fp_fxmul GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36, pipes=>2,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>mulonenormff(26 DOWNTO 9),databb=>onethird, result=>scaled); -- level 9 in, level 11 out mulfor: fp_fxmul GENERIC MAP (widthaa=>18,widthbb=>18,widthcc=>36, pipes=>2,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>squared(36 DOWNTO 19),databb=>scaled(36 DOWNTO 19), result=>cubed); oneterm <= mulonenormff(26 DOWNTO 1) & zerovec(6 DOWNTO 1); twoterm <= zerovec(7 DOWNTO 1) & squared(36 DOWNTO 12); thrterm <= zerovec(14 DOWNTO 1) & cubed(36 DOWNTO 19); --numtwo <= '0' & ((mulonenorm(25 DOWNTO 1) & zerovec(6 DOWNTO 1)) - -- (zerovec(9 DOWNTO 1) & square(36 DOWNTO 15)) + -- (zerovec(16 DOWNTO 1) & cubedscale(36 DOWNTO 22))); -- level 7 in, level 9 out deltwo: fp_del GENERIC MAP (width=>26,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>mulonenormff(26 DOWNTO 1),cc=>mulonedel); ptay: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 32 LOOP seriesoneff(k) <= '0'; seriesonedelff(k) <= '0'; seriestwoff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN -- level 10 seriesoneff <= (mulonedel & zerovec(6 DOWNTO 1)) - (zerovec(8 DOWNTO 1) & squared(36 DOWNTO 13)); seriesonedelff <= seriesoneff; -- level 12 seriestwoff <= seriesonedelff + (zerovec(14 DOWNTO 1) & cubed(36 DOWNTO 19)); END IF; END IF; END PROCESS; numtwo <= '0' & seriestwoff(32 DOWNTO 2); -- exponent for subrange 127-8 = 119 exptwo <= "01110111"; --*********************************************************** --*** add logarithm values *** --*********************************************************** zeroone <= lutoneexpff(8) OR lutoneexpff(7) OR lutoneexpff(6) OR lutoneexpff(5) OR lutoneexpff(4) OR lutoneexpff(3) OR lutoneexpff(2) OR lutoneexpff(1); numberone <= zeroone & lutonemanff & lutoneexpff; -- level 3 in, level 4 out delthr: fp_del GENERIC MAP (width=>32,pipes=>1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>numberone,cc=>numberonedel); numone <= '0' & numberonedel(32 DOWNTO 9) & zerovec(7 DOWNTO 1); expone <= numberonedel(8 DOWNTO 1); zeropow <= lutpowexpff(8) OR lutpowexpff(7) OR lutpowexpff(6) OR lutpowexpff(5) OR lutpowexpff(4) OR lutpowexpff(3) OR lutpowexpff(2) OR lutpowexpff(1); numpow <= '0' & zeropow & lutpowmanff & zerovec(7 DOWNTO 1); exppow <= lutpowexpff; gmpz: FOR k IN 1 TO 32 GENERATE numpowsigned(k) <= numpow(k) XOR signff(3); END GENERATE; -- level 4 in, level 8 out addone: fp_lnadd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aaman=>numpowsigned,aaexp=>exppow, bbman=>numone,bbexp=>expone, ccman=>numpowone,ccexp=>exppowone); -- level 8 in, level 12 out delfor: fp_del GENERIC MAP (width=>32,pipes=>4) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>numpowone,cc=>numpowonedel); delfiv: fp_del GENERIC MAP (width=>8,pipes=>4) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>exppowone,cc=>exppowonedel); -- level 12 in, level 16 out addtwo: fp_lnadd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aaman=>numpowonedel,aaexp=>exppowonedel, bbman=>numtwo,bbexp=>exptwo, ccman=>numsum,ccexp=>expsum); gmsa: FOR k IN 1 TO 32 GENERATE numsumabs(k) <= numsum(k) XOR signff(15); END GENERATE; -- level 16 in, level 19 out norm: fp_lnnorm PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inman=>numsumabs,inexp=>expsum, outman=>ccmannode,outexp=>ccexpnode, zero=>zeroout); psgna: PROCESS (sysclk) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 18 LOOP signff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN signff(1) <= aaexppos(9); FOR k IN 2 TO 18 LOOP signff(k) <= signff(k-1); END LOOP; END IF; END PROCESS; ccsgn <= signff(18); ccman <= ccmannode; ccexp <= ccexpnode; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/dp_inv.vhd

10

12634

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** DOUBLE PRECISION INVERSE - TOP LEVEL *** --*** *** --*** DP_INV.VHD *** --*** *** --*** Function: IEEE754 DP Inverse *** --*** (multiplicative iterative algorithm) *** --*** *** --*** 12/08/09 ML *** --*** *** --*** (c) 2009 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** Notes: *** --*** *** --*** Stratix II *** --*** Latency = 20 + 2*DoubleSpeed + *** --*** RoundConvert*(1+DoubleSpeed) *** --*** DoubleSpeed = 0, Roundconvert = 0 : 20 *** --*** DoubleSpeed = 1, Roundconvert = 0 : 22 *** --*** DoubleSpeed = 0, Roundconvert = 1 : 21 *** --*** DoubleSpeed = 1, Roundconvert = 1 : 24 *** --*** *** --*** Stratix III/IV *** --*** Latency = 19 + DoubleSpeed + *** --*** Roundconvert*(1+DoubleSpeed) *** --*** DoubleSpeed = 0, Roundconvert = 0 : 19 *** --*** DoubleSpeed = 1, Roundconvert = 0 : 20 *** --*** DoubleSpeed = 0, Roundconvert = 1 : 20 *** --*** DoubleSpeed = 1, Roundconvert = 1 : 22 *** --*** *** --*************************************************** ENTITY dp_inv IS GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); END dp_inv; ARCHITECTURE rtl OF dp_inv IS constant expwidth : positive := 11; constant manwidth : positive := 52; -- SII Latency = 19 + 2*speed -- SIII Latency = 18 + speed constant coredepth : positive := 19+2*doublespeed - device*(1+doublespeed); type expfftype IS ARRAY (coredepth-1 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal signinff : STD_LOGIC; signal manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal expoffset : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal invertnum : STD_LOGIC_VECTOR (54 DOWNTO 1); signal quotient : STD_LOGIC_VECTOR (55 DOWNTO 1); signal signff : STD_LOGIC_VECTOR (coredepth-1 DOWNTO 1); signal expff : expfftype; -- conditions signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zeromaninff : STD_LOGIC; signal zeroexpinff : STD_LOGIC; signal maxexpinff : STD_LOGIC; signal zeroinff : STD_LOGIC; signal infinityinff : STD_LOGIC; signal naninff : STD_LOGIC; signal dividebyzeroff, nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1); component dp_inv_core GENERIC ( doublespeed : integer := 0; -- 0/1 doubleaccuracy : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (54 DOWNTO 1); quotient : OUT STD_LOGIC_VECTOR (55 DOWNTO 1) ); end component; component dp_divnornd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1); mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; dividebyzeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component dp_divrnd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1); mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; dividebyzeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component dp_divrndpipe PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentdiv : IN STD_LOGIC_VECTOR (13 DOWNTO 1); mantissadiv : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; dividebyzeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; BEGIN gzva: FOR k IN 1 TO manwidth GENERATE zerovec(k) <= '0'; END GENERATE; gxa: FOR k IN 1 TO expwidth-1 GENERATE expoffset(k) <= '1'; END GENERATE; expoffset(expwidth+2 DOWNTO expwidth) <= "000"; pma: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO manwidth LOOP manff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP expinff(k) <= '0'; END LOOP; FOR k IN 1 TO coredepth-1 LOOP signff(k) <= '0'; END LOOP; FOR k IN 1 TO coredepth-1 LOOP FOR j IN 1 TO expwidth+2 LOOP expff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN signinff <= signin; manff <= mantissain; expinff <= exponentin; signff(1) <= signinff; FOR k IN 2 TO coredepth-1 LOOP signff(k) <= signff(k-1); END LOOP; expff(1)(expwidth+2 DOWNTO 1) <= expoffset - ("00" & expinff); expff(2)(expwidth+2 DOWNTO 1) <= expff(1)(expwidth+2 DOWNTO 1) + expoffset; FOR k IN 3 TO coredepth-2 LOOP expff(k)(expwidth+2 DOWNTO 1) <= expff(k-1)(expwidth+2 DOWNTO 1); END LOOP; -- quotient always <1, so decrement exponent expff(coredepth-1)(expwidth+2 DOWNTO 1) <= expff(coredepth-2)(expwidth+2 DOWNTO 1) - (zerovec(expwidth+1 DOWNTO 1) & '1'); END IF; END IF; END PROCESS; --******************** --*** CHECK INPUTS *** --******************** zeroman(1) <= manff(1); gca: FOR k IN 2 TO manwidth GENERATE zeroman(k) <= zeroman(k-1) OR manff(k); END GENERATE; zeroexp(1) <= expinff(1); gcb: FOR k IN 2 TO expwidth GENERATE zeroexp(k) <= zeroexp(k-1) OR expinff(k); END GENERATE; maxexp(1) <= expinff(1); gcc: FOR k IN 2 TO expwidth GENERATE maxexp(k) <= maxexp(k-1) AND expinff(k); END GENERATE; pcc: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN zeromaninff <= '0'; zeroexpinff <= '0'; maxexpinff <= '0'; zeroinff <= '0'; infinityinff <= '0'; naninff <= '0'; FOR k IN 1 TO coredepth-3 LOOP dividebyzeroff(k) <= '0'; nanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN zeromaninff <= zeroman(manwidth); zeroexpinff <= zeroexp(expwidth); maxexpinff <= maxexp(expwidth); -- zero when man = 0, exp = 0 -- infinity when man = 0, exp = max -- nan when man != 0, exp = max -- all ffs '1' when condition true zeroinff <= NOT(zeromaninff OR zeroexpinff); infinityinff <= NOT(zeromaninff) AND maxexpinff; naninff <= zeromaninff AND maxexpinff; -- nan output when nan input nanff(1) <= naninff; FOR k IN 2 TO coredepth-3 LOOP nanff(k) <= nanff(k-1); END LOOP; dividebyzeroff(1) <= zeroinff; FOR k IN 2 TO coredepth-3 LOOP dividebyzeroff(k) <= dividebyzeroff(k-1); END LOOP; END IF; END IF; END PROCESS; --******************* --*** DIVIDE CORE *** --******************* invertnum <= '1' & mantissain & '0'; invcore: dp_inv_core GENERIC MAP (doublespeed=>doublespeed,doubleaccuracy=>doubleaccuracy, device=>device,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>invertnum, quotient=>quotient); -- quotient always <1 --************************ --*** ROUND AND OUTPUT *** --************************ -- in depth coredepth+1 (core + normalff) gra: IF (roundconvert = 0) GENERATE norndout: dp_divnornd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signff(coredepth-1), exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1), mantissadiv=>quotient(53 DOWNTO 1), nanin=>nanff(coredepth-3), dividebyzeroin=>dividebyzeroff(coredepth-3), signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout, nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout); END GENERATE; grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE rndout: dp_divrnd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signff(coredepth-1), exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1), mantissadiv=>quotient(53 DOWNTO 1), nanin=>nanff(coredepth-3), dividebyzeroin=>dividebyzeroff(coredepth-3), signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout, nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout); END GENERATE; grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE rndoutpipe: dp_divrndpipe PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signff(coredepth-1), exponentdiv=>expff(coredepth-1)(expwidth+2 DOWNTO 1), mantissadiv=>quotient(53 DOWNTO 1), nanin=>nanff(coredepth-3), dividebyzeroin=>dividebyzeroff(coredepth-3), signout=>signout,exponentout=>exponentout,mantissaout=>mantissaout, nanout=>nanout,invalidout=>invalidout,dividebyzeroout=>dividebyzeroout); END GENERATE; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/dp_exprnd.vhd

10

6808

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPRND.VHD *** --*** *** --*** Function: DP Exponent Output Block - *** --*** Rounded *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_exprnd IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaexp : IN STD_LOGIC_VECTOR (53 DOWNTO 1); -- includes roundbit nanin : IN STD_LOGIC; rangeerror : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); END dp_exprnd; ARCHITECTURE rtl OF dp_exprnd IS constant expwidth : positive := 11; constant manwidth : positive := 52; type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1); signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal rangeerrorff : STD_LOGIC; signal overflownode, underflownode : STD_LOGIC; signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal manoverflowbitff : STD_LOGIC; signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1); signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal setmanzero, setmanmax : STD_LOGIC; signal setexpzero, setexpmax : STD_LOGIC; BEGIN gzv: FOR k IN 1 TO manwidth-1 GENERATE zerovec(k) <= '0'; END GENERATE; pra: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN nanff <= "00"; rangeerrorff <= '0'; overflowff <= "00"; underflowff <= "00"; manoverflowbitff <= '0'; FOR k IN 1 TO manwidth LOOP roundmantissaff(k) <= '0'; mantissaff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth+2 LOOP exponentoneff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF(enable = '1') THEN nanff(1) <= nanin; nanff(2) <= nanff(1); rangeerrorff <= rangeerror; overflowff(1) <= overflownode; overflowff(2) <= overflowff(1); underflowff(1) <= underflownode; underflowff(2) <= underflowff(1); manoverflowbitff <= manoverflow(manwidth+1); roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1)); -- nan takes precedence (set max) -- nan takes precedence (set max) FOR k IN 1 TO manwidth LOOP mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax; END LOOP; exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax; END LOOP; END IF; END IF; END PROCESS; exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) + (zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff); --********************************* --*** PREDICT MANTISSA OVERFLOW *** --********************************* manoverflow(1) <= mantissaexp(1); gmoa: FOR k IN 2 TO manwidth+1 GENERATE manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k); END GENERATE; --********************************** --*** CHECK GENERATED CONDITIONS *** --********************************** -- infinity if exponent == 255 infinitygen(1) <= exponentnode(1); gia: FOR k IN 2 TO expwidth GENERATE infinitygen(k) <= infinitygen(k-1) AND exponentnode(k); END GENERATE; infinitygen(expwidth+1) <= infinitygen(expwidth) OR (exponentnode(expwidth+1) AND NOT(exponentnode(expwidth+2))); -- '1' if infinity -- zero if exponent == 0 zerogen(1) <= exponentnode(1); gza: FOR k IN 2 TO expwidth GENERATE zerogen(k) <= zerogen(k-1) OR exponentnode(k); END GENERATE; zerogen(expwidth+1) <= zerogen(expwidth) AND NOT(exponentnode(expwidth+2)); -- '0' if zero -- trap any other overflow errors -- when sign = 0 and rangeerror = 1, overflow -- when sign = 1 and rangeerror = 1, underflow overflownode <= NOT(signin) AND rangeerror; underflownode <= signin AND rangeerror; -- set mantissa to 0 when infinity or zero condition setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff); -- setmantissa to "11..11" when nan setmanmax <= nanff(1); -- set exponent to 0 when zero condition setexpzero <= zerogen(expwidth+1); -- set exponent to "11..11" when nan, infinity, or divide by 0 setexpmax <= nanff(1) OR infinitygen(expwidth+1) OR rangeerrorff; --*************** --*** OUTPUTS *** --*************** signout <= '0'; mantissaout <= mantissaff; exponentout <= exponenttwoff; ----------------------------------------------- nanout <= nanff(2); overflowout <= overflowff(2); underflowout <= underflowff(2); END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/dp_fxsub.vhd

10

2876

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_FXSUB.VHD *** --*** *** --*** Function: Generic Fixed Point Subtractor *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_fxsub IS GENERIC ( width : positive := 64; pipes : positive := 1; synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END dp_fxsub; ARCHITECTURE rtl OF dp_fxsub IS component dp_subb IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component dp_subs IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gaa: IF (synthesize = 0) GENERATE addone: dp_subb GENERIC MAP (width=>width,pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,bb=>bb,borrowin=>borrowin, cc=>cc); END GENERATE; gab: IF (synthesize = 1) GENERATE addtwo: dp_subs GENERIC MAP (width=>width,pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,bb=>bb,borrowin=>borrowin, cc=>cc); END GENERATE; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_atanpi_s5.vhd

10

525003

----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_atanpi_s5 -- VHDL created on Tue Mar 12 11:23:23 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_atanpi_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_atanpi_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstBiasM2_uid6_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal ooPi_uid9_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstBias_uid22_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal piO2_uid46_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0); signal piO4_uid47_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal shiftBias_uid64_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal zS_uid67_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q : std_logic_vector (12 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a : std_logic_vector (23 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 : std_logic_vector (50 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr : UNSIGNED (50 downto 0); signal mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q : std_logic_vector (50 downto 0); signal fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (9 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (10 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector (23 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid165_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (47 downto 0); signal roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal signR_uid190_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (11 downto 0); signal leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (15 downto 0); signal rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (5 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid360_pT1_uid303_atanXOXPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_a : std_logic_vector (17 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (22 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 : std_logic_vector (40 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr : SIGNED (41 downto 0); signal prodXY_uid363_pT2_uid309_atanXOXPolyEval_q : std_logic_vector (40 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid366_pT1_uid348_invPolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_b : std_logic_vector (21 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_s1 : std_logic_vector (36 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_pr : SIGNED (37 downto 0); signal prodXY_uid369_pT2_uid354_invPolyEval_q : std_logic_vector (36 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid299_atanXOXTabGen_lutmem_ia : std_logic_vector (30 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_iq : std_logic_vector (30 downto 0); signal memoryC0_uid299_atanXOXTabGen_lutmem_q : std_logic_vector (30 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid300_atanXOXTabGen_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid300_atanXOXTabGen_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid301_atanXOXTabGen_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid301_atanXOXTabGen_lutmem_q : std_logic_vector (12 downto 0); signal memoryC0_uid344_invTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid344_invTabGen_lutmem_ia : std_logic_vector (28 downto 0); signal memoryC0_uid344_invTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid344_invTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid344_invTabGen_lutmem_iq : std_logic_vector (28 downto 0); signal memoryC0_uid344_invTabGen_lutmem_q : std_logic_vector (28 downto 0); signal memoryC1_uid345_invTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid345_invTabGen_lutmem_ia : std_logic_vector (19 downto 0); signal memoryC1_uid345_invTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid345_invTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid345_invTabGen_lutmem_iq : std_logic_vector (19 downto 0); signal memoryC1_uid345_invTabGen_lutmem_q : std_logic_vector (19 downto 0); signal memoryC2_uid346_invTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid346_invTabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid346_invTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid346_invTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid346_invTabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid346_invTabGen_lutmem_q : std_logic_vector (11 downto 0); signal reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q : std_logic_vector (11 downto 0); signal reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q : std_logic_vector (19 downto 0); signal reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q : std_logic_vector (21 downto 0); signal reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q : std_logic_vector (28 downto 0); signal reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (0 downto 0); signal reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (7 downto 0); signal reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (36 downto 0); signal reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (36 downto 0); signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q : std_logic_vector (20 downto 0); signal reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q : std_logic_vector (17 downto 0); signal reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q : std_logic_vector (22 downto 0); signal reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q : std_logic_vector (30 downto 0); signal reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (23 downto 0); signal reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (26 downto 0); signal reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (8 downto 0); signal reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (24 downto 0); signal reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (0 downto 0); signal reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (31 downto 0); signal reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q : std_logic_vector (32 downto 0); signal reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (22 downto 0); signal reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (22 downto 0); signal reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (22 downto 0); signal reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (22 downto 0); signal reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q : std_logic_vector (7 downto 0); signal reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q : std_logic_vector (7 downto 0); signal reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q : std_logic_vector (7 downto 0); signal reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q : std_logic_vector (7 downto 0); signal reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (7 downto 0); signal reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (22 downto 0); signal reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (23 downto 0); signal reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (23 downto 0); signal reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q : std_logic_vector (11 downto 0); signal reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q : std_logic_vector (2 downto 0); signal ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0); signal ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (23 downto 0); signal ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q : std_logic_vector (7 downto 0); signal ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (7 downto 0); signal ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (8 downto 0); signal ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (22 downto 0); signal ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q : std_logic_vector (7 downto 0); signal ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0); signal ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (1 downto 0); signal ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q : std_logic_vector (0 downto 0); signal ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (35 downto 0); signal ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (34 downto 0); signal ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (33 downto 0); signal ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (22 downto 0); signal ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (20 downto 0); signal ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q : std_logic_vector (18 downto 0); signal ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q : std_logic_vector (12 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic; signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic; signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true; signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic; signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (4 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic; signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq : std_logic; signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (22 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 : std_logic; signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q : std_logic_vector (22 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i : unsigned(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q : signal is true; signal ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q : std_logic_vector (7 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 : std_logic; signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q : signal is true; signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q : std_logic_vector(5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i : unsigned(5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq : std_logic; signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q : std_logic_vector (5 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q : std_logic_vector (6 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q : signal is true; signal ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q : signal is true; signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q : signal is true; signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q : signal is true; signal ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q : std_logic_vector (12 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q : signal is true; signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 : std_logic; signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa : std_logic_vector (5 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab : std_logic_vector (5 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q : signal is true; signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal shiftOut_uid91_atanX_uid8_fpArctanPiTest_c : std_logic_vector (0 downto 0); signal excSelBits_uid114_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a : std_logic_vector(33 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b : std_logic_vector(33 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o : std_logic_vector (33 downto 0); signal expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q : std_logic_vector (33 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o : std_logic_vector (32 downto 0); signal expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0); signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q : std_logic_vector (5 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal expX_uid15_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expX_uid15_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid16_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid16_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal singX_uid17_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal singX_uid17_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid36_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid36_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid36_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal inIsOne_uid45_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_cin : std_logic_vector (0 downto 0); signal path2_uid56_atanX_uid8_fpArctanPiTest_n : std_logic_vector (0 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal shiftValue_uid65_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a : std_logic_vector(10 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b : std_logic_vector(10 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o : std_logic_vector (10 downto 0); signal shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q : std_logic_vector (9 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_a : std_logic_vector(26 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_b : std_logic_vector(26 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_o : std_logic_vector (26 downto 0); signal path2Diff_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (26 downto 0); signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRCalc_uid113_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (35 downto 0); signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q : std_logic_vector(0 downto 0); signal fracOOPi_uid10_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracOOPi_uid10_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal normBit_uid80_atanX_uid8_fpArctanPiTest_in : std_logic_vector (49 downto 0); signal normBit_uid80_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in : std_logic_vector (48 downto 0); signal fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in : std_logic_vector (47 downto 0); signal fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in : std_logic_vector (40 downto 0); signal prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in : std_logic_vector (36 downto 0); signal prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b : std_logic_vector (22 downto 0); signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal R_uid221_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (14 downto 0); signal yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (14 downto 0); signal R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal constOut_uid54_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal constOut_uid54_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0); signal u_uid58_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal u_uid58_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(4 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(4 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a : std_logic_vector(5 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b : std_logic_vector(5 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b : std_logic_vector(0 downto 0); signal ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal R_uid120_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a : std_logic_vector(6 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b : std_logic_vector(6 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q : std_logic_vector(0 downto 0); signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal expRPath3_uid89_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal expRPath2_uid107_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (16 downto 0); signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (8 downto 0); signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in : std_logic_vector (8 downto 0); signal ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in : std_logic_vector (25 downto 0); signal normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (11 downto 0); signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (9 downto 0); signal udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0); signal LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (35 downto 0); signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0); signal LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0); signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (33 downto 0); signal LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (33 downto 0); signal fpOOPi_uid11_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (32 downto 0); signal X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (32 downto 0); signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0); signal X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (28 downto 0); signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (24 downto 0); signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (22 downto 0); signal lowRangeB_uid304_atanXOXPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid304_atanXOXPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid305_atanXOXPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid305_atanXOXPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid310_atanXOXPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid310_atanXOXPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid311_atanXOXPolyEval_in : std_logic_vector (23 downto 0); signal highBBits_uid311_atanXOXPolyEval_b : std_logic_vector (21 downto 0); signal lowRangeB_uid349_invPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid349_invPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid350_invPolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid350_invPolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid355_invPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid355_invPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid356_invPolyEval_in : std_logic_vector (22 downto 0); signal highBBits_uid356_invPolyEval_b : std_logic_vector (20 downto 0); signal y_uid73_atanX_uid8_fpArctanPiTest_in : std_logic_vector (35 downto 0); signal y_uid73_atanX_uid8_fpArctanPiTest_b : std_logic_vector (34 downto 0); signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal yT1_uid347_invPolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid347_invPolyEval_b : std_logic_vector (11 downto 0); signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expOutCst_uid112_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal expU_uid59_atanX_uid8_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expU_uid59_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal fracU_uid60_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracU_uid60_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expX_uid122_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal signX_uid124_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal exc_N_uid38_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid38_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid38_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0); signal fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b : std_logic_vector (3 downto 0); signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal expRPath2_uid103_atanX_uid8_fpArctanPiTest_q : std_logic_vector (7 downto 0); signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (30 downto 0); signal expY_uid123_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal signY_uid125_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q : std_logic_vector (36 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a : std_logic_vector(8 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b : std_logic_vector(8 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o : std_logic_vector (8 downto 0); signal expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q : std_logic_vector (8 downto 0); signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_a : std_logic_vector(21 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_b : std_logic_vector(21 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_o : std_logic_vector (21 downto 0); signal sumAHighB_uid306_atanXOXPolyEval_q : std_logic_vector (21 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_a : std_logic_vector(31 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_b : std_logic_vector(31 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_o : std_logic_vector (31 downto 0); signal sumAHighB_uid312_atanXOXPolyEval_q : std_logic_vector (31 downto 0); signal sumAHighB_uid351_invPolyEval_a : std_logic_vector(20 downto 0); signal sumAHighB_uid351_invPolyEval_b : std_logic_vector(20 downto 0); signal sumAHighB_uid351_invPolyEval_o : std_logic_vector (20 downto 0); signal sumAHighB_uid351_invPolyEval_q : std_logic_vector (20 downto 0); signal sumAHighB_uid357_invPolyEval_a : std_logic_vector(29 downto 0); signal sumAHighB_uid357_invPolyEval_b : std_logic_vector(29 downto 0); signal sumAHighB_uid357_invPolyEval_o : std_logic_vector (29 downto 0); signal sumAHighB_uid357_invPolyEval_q : std_logic_vector (29 downto 0); signal yAddr_uid75_atanX_uid8_fpArctanPiTest_in : std_logic_vector (34 downto 0); signal yAddr_uid75_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in : std_logic_vector (26 downto 0); signal yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b : std_logic_vector (17 downto 0); signal rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (7 downto 0); signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0); signal sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b : std_logic_vector (4 downto 0); signal expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q : std_logic_vector (31 downto 0); signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q : std_logic_vector (32 downto 0); signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal s1_uid304_uid307_atanXOXPolyEval_q : std_logic_vector (22 downto 0); signal s2_uid310_uid313_atanXOXPolyEval_q : std_logic_vector (33 downto 0); signal s1_uid349_uid352_invPolyEval_q : std_logic_vector (21 downto 0); signal s2_uid355_uid358_invPolyEval_q : std_logic_vector (31 downto 0); signal yT1_uid302_atanXOXPolyEval_in : std_logic_vector (17 downto 0); signal yT1_uid302_atanXOXPolyEval_b : std_logic_vector (12 downto 0); signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q : std_logic_vector (24 downto 0); signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (20 downto 0); signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (24 downto 0); signal RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (18 downto 0); signal signR_uid119_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal signR_uid119_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal signR_uid119_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : std_logic_vector (0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in : std_logic_vector (31 downto 0); signal fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b : std_logic_vector (26 downto 0); signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (28 downto 0); signal fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (23 downto 0); signal pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q : std_logic_vector (25 downto 0); signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in : std_logic_vector (22 downto 0); signal fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector (22 downto 0); signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b : std_logic_vector(0 downto 0); signal xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector(0 downto 0); signal excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q : std_logic_vector (2 downto 0); signal roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q : std_logic_vector (25 downto 0); begin --xIn(GPIN,3)@0 --cstAllZWF_uid19_atanX_uid8_fpArctanPiTest(CONSTANT,18) cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000000"; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable(LOGICAL,878) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a <= en; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q <= not ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_a; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,1008) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_a or ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,1004) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100001"; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,1005) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_mem_top_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q); ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_b else "0"; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,1006) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,1009) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,1010) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --fracX_uid16_atanX_uid8_fpArctanPiTest(BITSELECT,15)@0 fracX_uid16_atanX_uid8_fpArctanPiTest_in <= a(22 downto 0); fracX_uid16_atanX_uid8_fpArctanPiTest_b <= fracX_uid16_atanX_uid8_fpArctanPiTest_in(22 downto 0); --fracXIsZero_uid35_atanX_uid8_fpArctanPiTest(LOGICAL,34)@0 fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b; fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_b else "0"; --InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest(LOGICAL,36)@0 InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q; InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q <= not InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_a; --cstAllOWE_uid18_atanX_uid8_fpArctanPiTest(CONSTANT,17) cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q <= "11111111"; --expX_uid15_atanX_uid8_fpArctanPiTest(BITSELECT,14)@0 expX_uid15_atanX_uid8_fpArctanPiTest_in <= a(30 downto 0); expX_uid15_atanX_uid8_fpArctanPiTest_b <= expX_uid15_atanX_uid8_fpArctanPiTest_in(30 downto 23); --expXIsMax_uid33_atanX_uid8_fpArctanPiTest(LOGICAL,32)@0 expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b; expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsMax_uid33_atanX_uid8_fpArctanPiTest_a = expXIsMax_uid33_atanX_uid8_fpArctanPiTest_b else "0"; --exc_N_uid38_atanX_uid8_fpArctanPiTest(LOGICAL,37)@0 exc_N_uid38_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q; exc_N_uid38_atanX_uid8_fpArctanPiTest_b <= InvFracXIsZero_uid37_atanX_uid8_fpArctanPiTest_q; exc_N_uid38_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_a and exc_N_uid38_atanX_uid8_fpArctanPiTest_b; --InvExc_N_uid118_atanX_uid8_fpArctanPiTest(LOGICAL,117)@0 InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q; InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q <= not InvExc_N_uid118_atanX_uid8_fpArctanPiTest_a; --singX_uid17_atanX_uid8_fpArctanPiTest(BITSELECT,16)@0 singX_uid17_atanX_uid8_fpArctanPiTest_in <= a; singX_uid17_atanX_uid8_fpArctanPiTest_b <= singX_uid17_atanX_uid8_fpArctanPiTest_in(31 downto 31); --signR_uid119_atanX_uid8_fpArctanPiTest(LOGICAL,118)@0 signR_uid119_atanX_uid8_fpArctanPiTest_a <= singX_uid17_atanX_uid8_fpArctanPiTest_b; signR_uid119_atanX_uid8_fpArctanPiTest_b <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q; signR_uid119_atanX_uid8_fpArctanPiTest_q <= signR_uid119_atanX_uid8_fpArctanPiTest_a and signR_uid119_atanX_uid8_fpArctanPiTest_b; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,998) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid119_atanX_uid8_fpArctanPiTest_q, xout => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,1000) -- every=1, low=0, high=33, step=1, init=1 ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 32 THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 33; ELSE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6)); --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,1001) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,1002) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q) BEGIN CASE ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS WHEN "0" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; WHEN "1" => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,999) ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 34, width_b => 1, widthad_b => 6, numwords_b => 34, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,879) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_a or ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,875) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "0100000"; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,876) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_mem_top_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q); ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_b else "0"; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,877) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,880) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,881) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,869) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => singX_uid17_atanX_uid8_fpArctanPiTest_b, xout => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,871) -- every=1, low=0, high=32, step=1, init=1 ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,6); ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 31 THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 32; ELSE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,6)); --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,872) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,873) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q) BEGIN CASE ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS WHEN "0" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; WHEN "1" => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,870) ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0); --cstBias_uid22_atanX_uid8_fpArctanPiTest(CONSTANT,21) cstBias_uid22_atanX_uid8_fpArctanPiTest_q <= "01111111"; --piO2_uid46_atanX_uid8_fpArctanPiTest(CONSTANT,45) piO2_uid46_atanX_uid8_fpArctanPiTest_q <= "11001001000011111101101011"; --cstPiO2_uid48_atanX_uid8_fpArctanPiTest(BITSELECT,47)@35 cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in <= piO2_uid46_atanX_uid8_fpArctanPiTest_q(24 downto 0); cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b <= cstPiO2_uid48_atanX_uid8_fpArctanPiTest_in(24 downto 2); --fpPiO2C_uid49_atanX_uid8_fpArctanPiTest(BITJOIN,48)@35 fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBias_uid22_atanX_uid8_fpArctanPiTest_q & cstPiO2_uid48_atanX_uid8_fpArctanPiTest_b; --cstBiasM1_uid23_atanX_uid8_fpArctanPiTest(CONSTANT,22) cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q <= "01111110"; --piO4_uid47_atanX_uid8_fpArctanPiTest(CONSTANT,46) piO4_uid47_atanX_uid8_fpArctanPiTest_q <= "110010010000111111011011"; --cstPiO4_uid51_atanX_uid8_fpArctanPiTest(BITSELECT,50)@35 cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in <= piO4_uid47_atanX_uid8_fpArctanPiTest_q(22 downto 0); cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b <= cstPiO4_uid51_atanX_uid8_fpArctanPiTest_in(22 downto 0); --fpPiO4C_uid52_atanX_uid8_fpArctanPiTest(BITJOIN,51)@35 fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_mem_q & cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q & cstPiO4_uid51_atanX_uid8_fpArctanPiTest_b; --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,892) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_a or ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_b); --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,893) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,894) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_b; --exc_I_uid36_atanX_uid8_fpArctanPiTest(LOGICAL,35)@0 exc_I_uid36_atanX_uid8_fpArctanPiTest_a <= expXIsMax_uid33_atanX_uid8_fpArctanPiTest_q; exc_I_uid36_atanX_uid8_fpArctanPiTest_b <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q; exc_I_uid36_atanX_uid8_fpArctanPiTest_q <= exc_I_uid36_atanX_uid8_fpArctanPiTest_a and exc_I_uid36_atanX_uid8_fpArctanPiTest_b; --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,882) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_I_uid36_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,883) ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_inputreg_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq, address_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_aa, data_a => ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_ia ); ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset; ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(0 downto 0); --constOut_uid54_atanX_uid8_fpArctanPiTest(MUX,53)@35 constOut_uid54_atanX_uid8_fpArctanPiTest_s <= ld_exc_I_uid36_atanX_uid8_fpArctanPiTest_q_to_constOut_uid54_atanX_uid8_fpArctanPiTest_b_replace_mem_q; constOut_uid54_atanX_uid8_fpArctanPiTest: PROCESS (constOut_uid54_atanX_uid8_fpArctanPiTest_s, en, fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q, fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q) BEGIN CASE constOut_uid54_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO4C_uid52_atanX_uid8_fpArctanPiTest_q; WHEN "1" => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => constOut_uid54_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --expOutCst_uid112_atanX_uid8_fpArctanPiTest(BITSELECT,111)@35 expOutCst_uid112_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(30 downto 0); expOutCst_uid112_atanX_uid8_fpArctanPiTest_b <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_in(30 downto 23); --reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5(REG,428)@35 reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q <= expOutCst_uid112_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --cst01pWShift_uid69_atanX_uid8_fpArctanPiTest(CONSTANT,68) cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q <= "0000000000000"; --reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2(REG,389)@0 reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q <= signR_uid119_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c(DELAY,707)@1 ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 11 ) PORT MAP ( xin => reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor(LOGICAL,1022) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q <= not (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_a or ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_b); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top(CONSTANT,1018) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q <= "0111"; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp(LOGICAL,1019) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_mem_top_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q); ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_a = ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_b else "0"; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg(REG,1020) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena(REG,1023) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_nor_q = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd(LOGICAL,1024) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_sticky_ena_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b <= en; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_a and ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_b; --cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,230) cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111110"; --expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest(SUB,259)@0 expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2Bias_uid231_z_uid57_atanX_uid8_fpArctanPiTest_q); expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b); expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_b)); expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0); --expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,260)@0 expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompYIsOneExt_uid260_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0); expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0); --cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest(CONSTANT,229) cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11111101"; --expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest(SUB,256)@0 expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & cst2BiasM1_uid230_z_uid57_atanX_uid8_fpArctanPiTest_q); expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & expX_uid15_atanX_uid8_fpArctanPiTest_b); expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_b)); expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_o(8 downto 0); --expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,257)@0 expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in <= expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(7 downto 0); expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_in(7 downto 0); --GND(CONSTANT,0) GND_q <= "0"; --fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,249)@0 fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a <= fracX_uid16_atanX_uid8_fpArctanPiTest_b; fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0000000000000000000000" & GND_q); fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q <= "1" when fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_a = fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_b else "0"; --expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest(MUX,263)@0 expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s <= fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q; expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRComp_uid258_z_uid57_atanX_uid8_fpArctanPiTest_b; WHEN "1" => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCompYIsOne_uid261_z_uid57_atanX_uid8_fpArctanPiTest_b; WHEN OTHERS => expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --expXIsZero_uid31_atanX_uid8_fpArctanPiTest(LOGICAL,30)@0 expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b; expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsZero_uid31_atanX_uid8_fpArctanPiTest_a = expXIsZero_uid31_atanX_uid8_fpArctanPiTest_b else "0"; --udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,258)@0 udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in <= STD_LOGIC_VECTOR((9 downto 9 => expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q(8)) & expRCompExt_uid257_z_uid57_atanX_uid8_fpArctanPiTest_q); udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_in(9 downto 9); --InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,245)@0 InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q; InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_a; --InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,246)@0 InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a <= expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q; InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q <= not InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_a; --exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,247)@0 exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a <= InvExpXIsZero_uid247_z_uid57_atanX_uid8_fpArctanPiTest_q; exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b <= InvExc_I_uid246_z_uid57_atanX_uid8_fpArctanPiTest_q; exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c <= InvExc_N_uid118_atanX_uid8_fpArctanPiTest_q; exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_a and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_b and exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_c; --xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,264)@0 xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_R_uid248_z_uid57_atanX_uid8_fpArctanPiTest_q; xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b <= udf_uid259_z_uid57_atanX_uid8_fpArctanPiTest_b; xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_a and xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_b; --xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest(LOGICAL,265)@0 xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q; xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b <= xRegAndUdf_uid265_z_uid57_atanX_uid8_fpArctanPiTest_q; xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q <= xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_a or xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_b; --excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,266)@0 excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q <= exc_N_uid38_atanX_uid8_fpArctanPiTest_q & expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q & xIOrXRUdf_uid266_z_uid57_atanX_uid8_fpArctanPiTest_q; --reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0(REG,378)@0 reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest(LOOKUP,267)@1 outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_excSelBits_uid267_z_uid57_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest(MUX,269)@1 expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q; expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; WHEN "01" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid264_z_uid57_atanX_uid8_fpArctanPiTest_q; WHEN "10" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN "11" => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg(DELAY,1012) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt(COUNTER,1014) -- every=1, low=0, high=7, step=1, init=1 ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_i,3)); --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg(REG,1015) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux(MUX,1016) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s <= en; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q, ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q; WHEN "1" => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem(DUALMEM,1013) ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_inputreg_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdreg_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_rdmux_q; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 8, width_b => 8, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_ia ); ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q <= ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_iq(7 downto 0); --cstNaNWF_uid20_atanX_uid8_fpArctanPiTest(CONSTANT,19) cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q <= "00000000000000000000001"; --oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,248)@0 oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q <= VCC_q & fracX_uid16_atanX_uid8_fpArctanPiTest_b; --y_uid251_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,250)@0 y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in <= oFracX_uid249_uid249_z_uid57_atanX_uid8_fpArctanPiTest_q(22 downto 0); y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0); --yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,252)@0 yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in <= y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b; yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 15); --reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0(REG,379)@0 reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q <= yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid346_invTabGen_lutmem(DUALMEM,376)@1 memoryC2_uid346_invTabGen_lutmem_ia <= (others => '0'); memoryC2_uid346_invTabGen_lutmem_aa <= (others => '0'); memoryC2_uid346_invTabGen_lutmem_ab <= reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q; memoryC2_uid346_invTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC2_uid346_invTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid346_invTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid346_invTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid346_invTabGen_lutmem_iq, address_a => memoryC2_uid346_invTabGen_lutmem_aa, data_a => memoryC2_uid346_invTabGen_lutmem_ia ); memoryC2_uid346_invTabGen_lutmem_reset0 <= areset; memoryC2_uid346_invTabGen_lutmem_q <= memoryC2_uid346_invTabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1(REG,381)@3 reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q <= memoryC2_uid346_invTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,1011) ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a(DELAY,680)@0 ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_inputreg_q, xout => ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,253)@3 yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in <= ld_y_uid251_z_uid57_atanX_uid8_fpArctanPiTest_b_to_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_a_q(14 downto 0); yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_in(14 downto 0); --yT1_uid347_invPolyEval(BITSELECT,346)@3 yT1_uid347_invPolyEval_in <= yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b; yT1_uid347_invPolyEval_b <= yT1_uid347_invPolyEval_in(14 downto 3); --reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0(REG,380)@3 reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q <= yT1_uid347_invPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid366_pT1_uid348_invPolyEval(MULT,365)@4 prodXY_uid366_pT1_uid348_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid366_pT1_uid348_invPolyEval_a),13)) * SIGNED(prodXY_uid366_pT1_uid348_invPolyEval_b); prodXY_uid366_pT1_uid348_invPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid366_pT1_uid348_invPolyEval_a <= (others => '0'); prodXY_uid366_pT1_uid348_invPolyEval_b <= (others => '0'); prodXY_uid366_pT1_uid348_invPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid366_pT1_uid348_invPolyEval_a <= reg_yT1_uid347_invPolyEval_0_to_prodXY_uid366_pT1_uid348_invPolyEval_0_q; prodXY_uid366_pT1_uid348_invPolyEval_b <= reg_memoryC2_uid346_invTabGen_lutmem_0_to_prodXY_uid366_pT1_uid348_invPolyEval_1_q; prodXY_uid366_pT1_uid348_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid366_pT1_uid348_invPolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid366_pT1_uid348_invPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid366_pT1_uid348_invPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid366_pT1_uid348_invPolyEval_q <= prodXY_uid366_pT1_uid348_invPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid367_pT1_uid348_invPolyEval(BITSELECT,366)@7 prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in <= prodXY_uid366_pT1_uid348_invPolyEval_q; prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_in(23 downto 11); --highBBits_uid350_invPolyEval(BITSELECT,349)@7 highBBits_uid350_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b; highBBits_uid350_invPolyEval_b <= highBBits_uid350_invPolyEval_in(12 downto 1); --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a(DELAY,804)@1 ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid345_invTabGen_lutmem(DUALMEM,375)@4 memoryC1_uid345_invTabGen_lutmem_ia <= (others => '0'); memoryC1_uid345_invTabGen_lutmem_aa <= (others => '0'); memoryC1_uid345_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid345_invTabGen_lutmem_0_q_to_memoryC1_uid345_invTabGen_lutmem_a_q; memoryC1_uid345_invTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 20, widthad_a => 8, numwords_a => 256, width_b => 20, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC1_uid345_invTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid345_invTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid345_invTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid345_invTabGen_lutmem_iq, address_a => memoryC1_uid345_invTabGen_lutmem_aa, data_a => memoryC1_uid345_invTabGen_lutmem_ia ); memoryC1_uid345_invTabGen_lutmem_reset0 <= areset; memoryC1_uid345_invTabGen_lutmem_q <= memoryC1_uid345_invTabGen_lutmem_iq(19 downto 0); --reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0(REG,383)@6 reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= "00000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q <= memoryC1_uid345_invTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid351_invPolyEval(ADD,350)@7 sumAHighB_uid351_invPolyEval_a <= STD_LOGIC_VECTOR((20 downto 20 => reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q(19)) & reg_memoryC1_uid345_invTabGen_lutmem_0_to_sumAHighB_uid351_invPolyEval_0_q); sumAHighB_uid351_invPolyEval_b <= STD_LOGIC_VECTOR((20 downto 12 => highBBits_uid350_invPolyEval_b(11)) & highBBits_uid350_invPolyEval_b); sumAHighB_uid351_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid351_invPolyEval_a) + SIGNED(sumAHighB_uid351_invPolyEval_b)); sumAHighB_uid351_invPolyEval_q <= sumAHighB_uid351_invPolyEval_o(20 downto 0); --lowRangeB_uid349_invPolyEval(BITSELECT,348)@7 lowRangeB_uid349_invPolyEval_in <= prodXYTruncFR_uid367_pT1_uid348_invPolyEval_b(0 downto 0); lowRangeB_uid349_invPolyEval_b <= lowRangeB_uid349_invPolyEval_in(0 downto 0); --s1_uid349_uid352_invPolyEval(BITJOIN,351)@7 s1_uid349_uid352_invPolyEval_q <= sumAHighB_uid351_invPolyEval_q & lowRangeB_uid349_invPolyEval_b; --reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1(REG,385)@7 reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= "0000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q <= s1_uid349_uid352_invPolyEval_q; END IF; END IF; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor(LOGICAL,1059) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q <= not (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_a or ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_b); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg(REG,966) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena(REG,1060) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_nor_q = "1") THEN ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q; END IF; END IF; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd(LOGICAL,1061) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_sticky_ena_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b <= en; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_a and ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_b; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg(DELAY,1051) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b, xout => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt(COUNTER,962) -- every=1, low=0, high=1, step=1, init=1 ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_i,1)); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg(REG,963) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux(MUX,964) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s <= en; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux: PROCESS (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q) BEGIN CASE ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_s IS WHEN "0" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q; WHEN "1" => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdcnt_q; WHEN OTHERS => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem(DUALMEM,1052) ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_inputreg_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 1, numwords_a => 2, width_b => 15, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq, address_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_aa, data_a => ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_ia ); ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_reset0 <= areset; ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_iq(14 downto 0); --reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0(REG,384)@7 reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q <= ld_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_b_to_reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid369_pT2_uid354_invPolyEval(MULT,368)@8 prodXY_uid369_pT2_uid354_invPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid369_pT2_uid354_invPolyEval_a),16)) * SIGNED(prodXY_uid369_pT2_uid354_invPolyEval_b); prodXY_uid369_pT2_uid354_invPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid369_pT2_uid354_invPolyEval_a <= (others => '0'); prodXY_uid369_pT2_uid354_invPolyEval_b <= (others => '0'); prodXY_uid369_pT2_uid354_invPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid369_pT2_uid354_invPolyEval_a <= reg_yPPolyEval_uid254_z_uid57_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid369_pT2_uid354_invPolyEval_0_q; prodXY_uid369_pT2_uid354_invPolyEval_b <= reg_s1_uid349_uid352_invPolyEval_0_to_prodXY_uid369_pT2_uid354_invPolyEval_1_q; prodXY_uid369_pT2_uid354_invPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid369_pT2_uid354_invPolyEval_pr,37)); END IF; END IF; END PROCESS; prodXY_uid369_pT2_uid354_invPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid369_pT2_uid354_invPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid369_pT2_uid354_invPolyEval_q <= prodXY_uid369_pT2_uid354_invPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid370_pT2_uid354_invPolyEval(BITSELECT,369)@11 prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in <= prodXY_uid369_pT2_uid354_invPolyEval_q; prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_in(36 downto 14); --highBBits_uid356_invPolyEval(BITSELECT,355)@11 highBBits_uid356_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b; highBBits_uid356_invPolyEval_b <= highBBits_uid356_invPolyEval_in(22 downto 2); --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor(LOGICAL,1048) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_b); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top(CONSTANT,1031) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q <= "0100"; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp(LOGICAL,1032) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_mem_top_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q); ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_b else "0"; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg(REG,1033) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena(REG,1049) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_nor_q = "1") THEN ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd(LOGICAL,1050) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b <= en; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_b; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg(DELAY,1038) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid346_invTabGen_lutmem_0_q, xout => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt(COUNTER,1027) -- every=1, low=0, high=4, step=1, init=1 ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i = 3 THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i - 4; ELSE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_i,3)); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg(REG,1028) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux(MUX,1029) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s <= en; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem(DUALMEM,1039) ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_inputreg_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_ia ); ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_iq(7 downto 0); --memoryC0_uid344_invTabGen_lutmem(DUALMEM,374)@8 memoryC0_uid344_invTabGen_lutmem_ia <= (others => '0'); memoryC0_uid344_invTabGen_lutmem_aa <= (others => '0'); memoryC0_uid344_invTabGen_lutmem_ab <= ld_reg_yAddr_uid253_z_uid57_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid344_invTabGen_lutmem_0_q_to_memoryC0_uid344_invTabGen_lutmem_a_replace_mem_q; memoryC0_uid344_invTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 29, widthad_a => 8, numwords_a => 256, width_b => 29, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC0_uid344_invTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid344_invTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid344_invTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid344_invTabGen_lutmem_iq, address_a => memoryC0_uid344_invTabGen_lutmem_aa, data_a => memoryC0_uid344_invTabGen_lutmem_ia ); memoryC0_uid344_invTabGen_lutmem_reset0 <= areset; memoryC0_uid344_invTabGen_lutmem_q <= memoryC0_uid344_invTabGen_lutmem_iq(28 downto 0); --reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0(REG,387)@10 reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= "00000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q <= memoryC0_uid344_invTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid357_invPolyEval(ADD,356)@11 sumAHighB_uid357_invPolyEval_a <= STD_LOGIC_VECTOR((29 downto 29 => reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q(28)) & reg_memoryC0_uid344_invTabGen_lutmem_0_to_sumAHighB_uid357_invPolyEval_0_q); sumAHighB_uid357_invPolyEval_b <= STD_LOGIC_VECTOR((29 downto 21 => highBBits_uid356_invPolyEval_b(20)) & highBBits_uid356_invPolyEval_b); sumAHighB_uid357_invPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid357_invPolyEval_a) + SIGNED(sumAHighB_uid357_invPolyEval_b)); sumAHighB_uid357_invPolyEval_q <= sumAHighB_uid357_invPolyEval_o(29 downto 0); --lowRangeB_uid355_invPolyEval(BITSELECT,354)@11 lowRangeB_uid355_invPolyEval_in <= prodXYTruncFR_uid370_pT2_uid354_invPolyEval_b(1 downto 0); lowRangeB_uid355_invPolyEval_b <= lowRangeB_uid355_invPolyEval_in(1 downto 0); --s2_uid355_uid358_invPolyEval(BITJOIN,357)@11 s2_uid355_uid358_invPolyEval_q <= sumAHighB_uid357_invPolyEval_q & lowRangeB_uid355_invPolyEval_b; --fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,255)@11 fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in <= s2_uid355_uid358_invPolyEval_q(28 downto 0); fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_in(28 downto 5); --fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest(BITSELECT,261)@11 fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in <= fxpInverseRes_uid256_z_uid57_atanX_uid8_fpArctanPiTest_b(22 downto 0); fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_in(22 downto 0); --ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,688)@0 ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 11 ) PORT MAP ( xin => fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q, xout => ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest(MUX,262)@11 fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_fracXIsZero_uid250_z_uid57_atanX_uid8_fpArctanPiTest_q_to_fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_b_q; fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= fxpInverseResFrac_uid262_z_uid57_atanX_uid8_fpArctanPiTest_b; WHEN "1" => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1(REG,388)@1 reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q <= outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b(DELAY,701)@2 ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 10 ) PORT MAP ( xin => reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest(MUX,268)@12 fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s <= ld_reg_outMuxSelEnc_uid268_z_uid57_atanX_uid8_fpArctanPiTest_0_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_1_q_to_fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_b_q; fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q) BEGIN CASE fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "01" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid263_z_uid57_atanX_uid8_fpArctanPiTest_q; WHEN "10" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "11" => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid273_z_uid57_atanX_uid8_fpArctanPiTest(BITJOIN,272)@12 R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q <= ld_reg_signR_uid119_atanX_uid8_fpArctanPiTest_0_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_2_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_c_q & ld_expRPostExc_uid270_z_uid57_atanX_uid8_fpArctanPiTest_q_to_R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_b_replace_mem_q & fracRPostExc_uid269_z_uid57_atanX_uid8_fpArctanPiTest_q; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,905) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_a or ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top(CONSTANT,901) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q <= "01001"; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp(LOGICAL,902) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_mem_top_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b <= STD_LOGIC_VECTOR("0" & ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q); ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q <= "1" when ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_a = ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_b else "0"; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg(REG,903) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmp_q; END IF; END IF; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,906) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,907) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,895) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => a, xout => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt(COUNTER,897) -- every=1, low=0, high=9, step=1, init=1 ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i = 8 THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '1'; ELSE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq <= '0'; END IF; IF (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_eq = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i - 9; ELSE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_i,4)); --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg(REG,898) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux(MUX,899) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s <= en; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux: PROCESS (ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q) BEGIN CASE ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_s IS WHEN "0" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; WHEN "1" => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdcnt_q; WHEN OTHERS => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,896) ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 32, widthad_a => 4, numwords_a => 10, width_b => 32, widthad_b => 4, numwords_b => 10, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(31 downto 0); --path2_uid56_atanX_uid8_fpArctanPiTest(COMPARE,55)@0 path2_uid56_atanX_uid8_fpArctanPiTest_cin <= GND_q; path2_uid56_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & expX_uid15_atanX_uid8_fpArctanPiTest_b) & '0'; path2_uid56_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q) & path2_uid56_atanX_uid8_fpArctanPiTest_cin(0); path2_uid56_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2_uid56_atanX_uid8_fpArctanPiTest_b)); path2_uid56_atanX_uid8_fpArctanPiTest_n(0) <= not path2_uid56_atanX_uid8_fpArctanPiTest_o(10); --reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1(REG,390)@0 reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q <= path2_uid56_atanX_uid8_fpArctanPiTest_n; END IF; END IF; END PROCESS; --ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b(DELAY,466)@1 ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 11 ) PORT MAP ( xin => reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --u_uid58_atanX_uid8_fpArctanPiTest(MUX,57)@12 u_uid58_atanX_uid8_fpArctanPiTest_s <= ld_reg_path2_uid56_atanX_uid8_fpArctanPiTest_2_to_u_uid58_atanX_uid8_fpArctanPiTest_1_q_to_u_uid58_atanX_uid8_fpArctanPiTest_b_q; u_uid58_atanX_uid8_fpArctanPiTest: PROCESS (u_uid58_atanX_uid8_fpArctanPiTest_s, en, ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q, R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q) BEGIN CASE u_uid58_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => u_uid58_atanX_uid8_fpArctanPiTest_q <= ld_xIn_a_to_u_uid58_atanX_uid8_fpArctanPiTest_c_replace_mem_q; WHEN "1" => u_uid58_atanX_uid8_fpArctanPiTest_q <= R_uid273_z_uid57_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => u_uid58_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracU_uid60_atanX_uid8_fpArctanPiTest(BITSELECT,59)@12 fracU_uid60_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(22 downto 0); fracU_uid60_atanX_uid8_fpArctanPiTest_b <= fracU_uid60_atanX_uid8_fpArctanPiTest_in(22 downto 0); --ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a(DELAY,471)@12 ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracU_uid60_atanX_uid8_fpArctanPiTest_b, xout => ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest(BITJOIN,60)@13 oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracU_uid60_atanX_uid8_fpArctanPiTest_b_to_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_a_q; --oFracUExt_uid70_atanX_uid8_fpArctanPiTest(BITJOIN,69)@13 oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q <= cst01pWShift_uid69_atanX_uid8_fpArctanPiTest_q & oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q; --X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,282)@13 X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(24 downto 0); X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(24 downto 0); --leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,281) leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000000000000"; --leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,283)@13 leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X24dto0_uid283_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx3Pad12_uid282_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5(REG,399)@13 reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q <= leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,279)@13 X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(28 downto 0); X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(28 downto 0); --leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,280)@13 leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X28dto0_uid280_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; --reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4(REG,398)@13 reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q <= leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,276)@13 X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q(32 downto 0); X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(32 downto 0); --leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,275) leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "0000"; --leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,277)@13 leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= X32dto0_uid277_fxpU_uid72_atanX_uid8_fpArctanPiTest_b & leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3(REG,397)@13 reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q <= leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,396)@13 reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= oFracUExt_uid70_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --zS_uid67_atanX_uid8_fpArctanPiTest(CONSTANT,66) zS_uid67_atanX_uid8_fpArctanPiTest_q <= "000000000"; --shiftBias_uid64_atanX_uid8_fpArctanPiTest(CONSTANT,63) shiftBias_uid64_atanX_uid8_fpArctanPiTest_q <= "01110010"; --expU_uid59_atanX_uid8_fpArctanPiTest(BITSELECT,58)@12 expU_uid59_atanX_uid8_fpArctanPiTest_in <= u_uid58_atanX_uid8_fpArctanPiTest_q(30 downto 0); expU_uid59_atanX_uid8_fpArctanPiTest_b <= expU_uid59_atanX_uid8_fpArctanPiTest_in(30 downto 23); --reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1(REG,391)@12 reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q <= expU_uid59_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --shiftValue_uid65_atanX_uid8_fpArctanPiTest(SUB,64)@13 shiftValue_uid65_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q); shiftValue_uid65_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid64_atanX_uid8_fpArctanPiTest_q); shiftValue_uid65_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftValue_uid65_atanX_uid8_fpArctanPiTest_b)); shiftValue_uid65_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_o(8 downto 0); --ShiftValue8_uid66_atanX_uid8_fpArctanPiTest(BITSELECT,65)@13 ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q; ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_in(8 downto 8); --shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest(MUX,67)@13 shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s <= ShiftValue8_uid66_atanX_uid8_fpArctanPiTest_b; shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest: PROCESS (shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s, en, shiftValue_uid65_atanX_uid8_fpArctanPiTest_q, zS_uid67_atanX_uid8_fpArctanPiTest_q) BEGIN CASE shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= shiftValue_uid65_atanX_uid8_fpArctanPiTest_q; WHEN "1" => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= zS_uid67_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest(BITSELECT,70)@13 fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in <= shiftValuePostNeg_uid68_atanX_uid8_fpArctanPiTest_q(3 downto 0); fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_in(3 downto 0); --leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,284)@13 leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b; leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(3 downto 2); --reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,395)@13 reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,285)@14 leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel3Dto2_uid285_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q; leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q, reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q, reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q) BEGIN CASE leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_oFracUExt_uid70_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx1_uid278_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_3_q; WHEN "10" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx2_uid281_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_4_q; WHEN "11" => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0Idx3_uid284_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_5_q; WHEN OTHERS => leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,293)@14 LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(33 downto 0); LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(33 downto 0); --ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,725)@14 ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 34, depth => 1 ) PORT MAP ( xin => LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,292) leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "000"; --leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,294)@15 leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage033dto0_uid294_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx3Pad3_uid293_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,290)@14 LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(34 downto 0); LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(34 downto 0); --ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,723)@14 ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 35, depth => 1 ) PORT MAP ( xin => LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest(CONSTANT,289) leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= "00"; --leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,291)@15 leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage034dto0_uid291_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; --LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,287)@14 LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0); LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(35 downto 0); --ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b(DELAY,721)@14 ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 36, depth => 1 ) PORT MAP ( xin => LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITJOIN,288)@15 leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= ld_LeftShiftStage035dto0_uid288_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_q & GND_q; --reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2(REG,401)@14 reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q <= leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest(BITSELECT,295)@13 leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in <= fxpShifterBits_uid71_atanX_uid8_fpArctanPiTest_b(1 downto 0); leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b <= leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_in(1 downto 0); --ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a(DELAY,829)@13 ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1(REG,400)@14 reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_b_to_reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest(MUX,296)@15 leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s <= reg_leftShiftStageSel1Dto0_uid296_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_1_q; leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest: PROCESS (leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s, en, reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q, leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q, leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q) BEGIN CASE leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= reg_leftShiftStage0_uid286_fxpU_uid72_atanX_uid8_fpArctanPiTest_0_to_leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx1_uid289_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; WHEN "10" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2_uid292_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; WHEN "11" => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx3_uid295_fxpU_uid72_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid73_atanX_uid8_fpArctanPiTest(BITSELECT,72)@15 y_uid73_atanX_uid8_fpArctanPiTest_in <= leftShiftStage1_uid297_fxpU_uid72_atanX_uid8_fpArctanPiTest_q(35 downto 0); y_uid73_atanX_uid8_fpArctanPiTest_b <= y_uid73_atanX_uid8_fpArctanPiTest_in(35 downto 1); --yAddr_uid75_atanX_uid8_fpArctanPiTest(BITSELECT,74)@15 yAddr_uid75_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b; yAddr_uid75_atanX_uid8_fpArctanPiTest_b <= yAddr_uid75_atanX_uid8_fpArctanPiTest_in(34 downto 27); --reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0(REG,402)@15 reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q <= yAddr_uid75_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid301_atanXOXTabGen_lutmem(DUALMEM,373)@16 memoryC2_uid301_atanXOXTabGen_lutmem_ia <= (others => '0'); memoryC2_uid301_atanXOXTabGen_lutmem_aa <= (others => '0'); memoryC2_uid301_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC2_uid301_atanXOXTabGen_lutmem_0_q; memoryC2_uid301_atanXOXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 8, numwords_a => 256, width_b => 13, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC2_uid301_atanXOXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid301_atanXOXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid301_atanXOXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid301_atanXOXTabGen_lutmem_iq, address_a => memoryC2_uid301_atanXOXTabGen_lutmem_aa, data_a => memoryC2_uid301_atanXOXTabGen_lutmem_ia ); memoryC2_uid301_atanXOXTabGen_lutmem_reset0 <= areset; memoryC2_uid301_atanXOXTabGen_lutmem_q <= memoryC2_uid301_atanXOXTabGen_lutmem_iq(12 downto 0); --reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1(REG,404)@18 reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q <= memoryC2_uid301_atanXOXTabGen_lutmem_q; END IF; END IF; END PROCESS; --yPPolyEval_uid76_atanX_uid8_fpArctanPiTest(BITSELECT,75)@15 yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in <= y_uid73_atanX_uid8_fpArctanPiTest_b(26 downto 0); yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_in(26 downto 9); --yT1_uid302_atanXOXPolyEval(BITSELECT,301)@15 yT1_uid302_atanXOXPolyEval_in <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b; yT1_uid302_atanXOXPolyEval_b <= yT1_uid302_atanXOXPolyEval_in(17 downto 5); --ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg(DELAY,1062) ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 13, depth => 1 ) PORT MAP ( xin => yT1_uid302_atanXOXPolyEval_b, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a(DELAY,832)@15 ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a : dspba_delay GENERIC MAP ( width => 13, depth => 2 ) PORT MAP ( xin => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_inputreg_q, xout => ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0(REG,403)@18 reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q <= ld_yT1_uid302_atanXOXPolyEval_b_to_reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_a_q; END IF; END IF; END PROCESS; --prodXY_uid360_pT1_uid303_atanXOXPolyEval(MULT,359)@19 prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_a),14)) * SIGNED(prodXY_uid360_pT1_uid303_atanXOXPolyEval_b); prodXY_uid360_pT1_uid303_atanXOXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= (others => '0'); prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= (others => '0'); prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_a <= reg_yT1_uid302_atanXOXPolyEval_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_0_q; prodXY_uid360_pT1_uid303_atanXOXPolyEval_b <= reg_memoryC2_uid301_atanXOXTabGen_lutmem_0_to_prodXY_uid360_pT1_uid303_atanXOXPolyEval_1_q; prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid360_pT1_uid303_atanXOXPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid360_pT1_uid303_atanXOXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid360_pT1_uid303_atanXOXPolyEval_q <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval(BITSELECT,360)@22 prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in <= prodXY_uid360_pT1_uid303_atanXOXPolyEval_q; prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_in(25 downto 12); --highBBits_uid305_atanXOXPolyEval(BITSELECT,304)@22 highBBits_uid305_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b; highBBits_uid305_atanXOXPolyEval_b <= highBBits_uid305_atanXOXPolyEval_in(13 downto 1); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a(DELAY,834)@15 ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0(REG,405)@18 reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid300_atanXOXTabGen_lutmem(DUALMEM,372)@19 memoryC1_uid300_atanXOXTabGen_lutmem_ia <= (others => '0'); memoryC1_uid300_atanXOXTabGen_lutmem_aa <= (others => '0'); memoryC1_uid300_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC1_uid300_atanXOXTabGen_lutmem_0_q; memoryC1_uid300_atanXOXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC1_uid300_atanXOXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid300_atanXOXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid300_atanXOXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid300_atanXOXTabGen_lutmem_iq, address_a => memoryC1_uid300_atanXOXTabGen_lutmem_aa, data_a => memoryC1_uid300_atanXOXTabGen_lutmem_ia ); memoryC1_uid300_atanXOXTabGen_lutmem_reset0 <= areset; memoryC1_uid300_atanXOXTabGen_lutmem_q <= memoryC1_uid300_atanXOXTabGen_lutmem_iq(20 downto 0); --reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0(REG,406)@21 reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q <= memoryC1_uid300_atanXOXTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid306_atanXOXPolyEval(ADD,305)@22 sumAHighB_uid306_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q(20)) & reg_memoryC1_uid300_atanXOXTabGen_lutmem_0_to_sumAHighB_uid306_atanXOXPolyEval_0_q); sumAHighB_uid306_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid305_atanXOXPolyEval_b(12)) & highBBits_uid305_atanXOXPolyEval_b); sumAHighB_uid306_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid306_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid306_atanXOXPolyEval_b)); sumAHighB_uid306_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_o(21 downto 0); --lowRangeB_uid304_atanXOXPolyEval(BITSELECT,303)@22 lowRangeB_uid304_atanXOXPolyEval_in <= prodXYTruncFR_uid361_pT1_uid303_atanXOXPolyEval_b(0 downto 0); lowRangeB_uid304_atanXOXPolyEval_b <= lowRangeB_uid304_atanXOXPolyEval_in(0 downto 0); --s1_uid304_uid307_atanXOXPolyEval(BITJOIN,306)@22 s1_uid304_uid307_atanXOXPolyEval_q <= sumAHighB_uid306_atanXOXPolyEval_q & lowRangeB_uid304_atanXOXPolyEval_b; --reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1(REG,408)@22 reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q <= s1_uid304_uid307_atanXOXPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor(LOGICAL,1035) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_a or ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_b); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena(REG,1036) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_nor_q = "1") THEN ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd(LOGICAL,1037) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b <= en; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_b; --reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0(REG,407)@15 reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q <= yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg(DELAY,1025) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q, xout => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem(DUALMEM,1026) ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_inputreg_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 3, numwords_a => 5, width_b => 18, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq, address_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_aa, data_a => ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_ia ); ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_reset0 <= areset; ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_iq(17 downto 0); --prodXY_uid363_pT2_uid309_atanXOXPolyEval(MULT,362)@23 prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_a),19)) * SIGNED(prodXY_uid363_pT2_uid309_atanXOXPolyEval_b); prodXY_uid363_pT2_uid309_atanXOXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= (others => '0'); prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= (others => '0'); prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_a <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_mem_q; prodXY_uid363_pT2_uid309_atanXOXPolyEval_b <= reg_s1_uid304_uid307_atanXOXPolyEval_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_1_q; prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid363_pT2_uid309_atanXOXPolyEval_pr,41)); END IF; END IF; END PROCESS; prodXY_uid363_pT2_uid309_atanXOXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid363_pT2_uid309_atanXOXPolyEval_q <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval(BITSELECT,363)@26 prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in <= prodXY_uid363_pT2_uid309_atanXOXPolyEval_q; prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_in(40 downto 17); --highBBits_uid311_atanXOXPolyEval(BITSELECT,310)@26 highBBits_uid311_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b; highBBits_uid311_atanXOXPolyEval_b <= highBBits_uid311_atanXOXPolyEval_in(23 downto 2); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor(LOGICAL,1073) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q <= not (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_a or ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_b); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena(REG,1074) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_nor_q = "1") THEN ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd(LOGICAL,1075) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_sticky_ena_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b <= en; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_a and ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_b; --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg(DELAY,1063) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => yAddr_uid75_atanX_uid8_fpArctanPiTest_b, xout => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem(DUALMEM,1064) ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_inputreg_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdreg_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid76_atanX_uid8_fpArctanPiTest_0_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_0_q_to_prodXY_uid363_pT2_uid309_atanXOXPolyEval_a_replace_rdmux_q; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq, address_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_aa, data_a => ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_ia ); ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_reset0 <= areset; ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0(REG,409)@22 reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q <= ld_yAddr_uid75_atanX_uid8_fpArctanPiTest_b_to_reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid299_atanXOXTabGen_lutmem(DUALMEM,371)@23 memoryC0_uid299_atanXOXTabGen_lutmem_ia <= (others => '0'); memoryC0_uid299_atanXOXTabGen_lutmem_aa <= (others => '0'); memoryC0_uid299_atanXOXTabGen_lutmem_ab <= reg_yAddr_uid75_atanX_uid8_fpArctanPiTest_0_to_memoryC0_uid299_atanXOXTabGen_lutmem_0_q; memoryC0_uid299_atanXOXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 31, widthad_a => 8, numwords_a => 256, width_b => 31, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_atanpi_s5_memoryC0_uid299_atanXOXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid299_atanXOXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid299_atanXOXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid299_atanXOXTabGen_lutmem_iq, address_a => memoryC0_uid299_atanXOXTabGen_lutmem_aa, data_a => memoryC0_uid299_atanXOXTabGen_lutmem_ia ); memoryC0_uid299_atanXOXTabGen_lutmem_reset0 <= areset; memoryC0_uid299_atanXOXTabGen_lutmem_q <= memoryC0_uid299_atanXOXTabGen_lutmem_iq(30 downto 0); --reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0(REG,410)@25 reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= "0000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q <= memoryC0_uid299_atanXOXTabGen_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid312_atanXOXPolyEval(ADD,311)@26 sumAHighB_uid312_atanXOXPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q(30)) & reg_memoryC0_uid299_atanXOXTabGen_lutmem_0_to_sumAHighB_uid312_atanXOXPolyEval_0_q); sumAHighB_uid312_atanXOXPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid311_atanXOXPolyEval_b(21)) & highBBits_uid311_atanXOXPolyEval_b); sumAHighB_uid312_atanXOXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid312_atanXOXPolyEval_a) + SIGNED(sumAHighB_uid312_atanXOXPolyEval_b)); sumAHighB_uid312_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_o(31 downto 0); --lowRangeB_uid310_atanXOXPolyEval(BITSELECT,309)@26 lowRangeB_uid310_atanXOXPolyEval_in <= prodXYTruncFR_uid364_pT2_uid309_atanXOXPolyEval_b(1 downto 0); lowRangeB_uid310_atanXOXPolyEval_b <= lowRangeB_uid310_atanXOXPolyEval_in(1 downto 0); --s2_uid310_uid313_atanXOXPolyEval(BITJOIN,312)@26 s2_uid310_uid313_atanXOXPolyEval_q <= sumAHighB_uid312_atanXOXPolyEval_q & lowRangeB_uid310_atanXOXPolyEval_b; --fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest(BITSELECT,77)@26 fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in <= s2_uid310_uid313_atanXOXPolyEval_q(31 downto 0); fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_in(31 downto 5); --reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1(REG,412)@26 reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q <= fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,918) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,914) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01010"; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,915) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_mem_top_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q); ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_b else "0"; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,916) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,919) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,920) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0(REG,411)@13 reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q <= oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,908) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 24, depth => 1 ) PORT MAP ( xin => reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,910) -- every=1, low=0, high=10, step=1, init=1 ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 9 THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 10; ELSE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4)); --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,911) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,912) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q) BEGIN CASE ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS WHEN "0" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; WHEN "1" => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,909) ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 4, numwords_a => 11, width_b => 24, widthad_b => 4, numwords_b => 11, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(23 downto 0); --mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest(MULT,78)@27 mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr <= UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a) * UNSIGNED(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b); mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= (others => '0'); mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= (others => '0'); mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a <= ld_reg_oFracU_uid61_uid61_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_0_q_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_a_replace_mem_q; mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_b <= reg_fxpAtanXOXRes_uid78_atanX_uid8_fpArctanPiTest_0_to_mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_1_q; mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_pr); END IF; END IF; END PROCESS; mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_s1; END IF; END IF; END PROCESS; --normBit_uid80_atanX_uid8_fpArctanPiTest(BITSELECT,79)@30 normBit_uid80_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(49 downto 0); normBit_uid80_atanX_uid8_fpArctanPiTest_b <= normBit_uid80_atanX_uid8_fpArctanPiTest_in(49 downto 49); --InvNormBit_uid84_atanX_uid8_fpArctanPiTest(LOGICAL,83)@30 InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a <= normBit_uid80_atanX_uid8_fpArctanPiTest_b; InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q <= not InvNormBit_uid84_atanX_uid8_fpArctanPiTest_a; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,931) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,927) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "01111"; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,928) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_mem_top_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q); ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_b else "0"; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,929) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,932) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,933) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,921) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expU_uid59_atanX_uid8_fpArctanPiTest_b, xout => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,923) -- every=1, low=0, high=15, step=1, init=1 ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,4)); --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,924) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,925) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q) BEGIN CASE ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS WHEN "0" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; WHEN "1" => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,922) ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 16, width_b => 8, widthad_b => 4, numwords_b => 16, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(7 downto 0); --expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest(SUB,84)@30 expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & ld_expU_uid59_atanX_uid8_fpArctanPiTest_b_to_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a_replace_mem_q); expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000" & InvNormBit_uid84_atanX_uid8_fpArctanPiTest_q); expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_b)); expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_o(8 downto 0); --fracRPath3High_uid81_atanX_uid8_fpArctanPiTest(BITSELECT,80)@30 fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(48 downto 0); fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_in(48 downto 25); --fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest(BITSELECT,81)@30 fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in <= mulXAtanXOXRes_uid79_atanX_uid8_fpArctanPiTest_q(47 downto 0); fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_in(47 downto 24); --fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest(MUX,82)@30 fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s <= normBit_uid80_atanX_uid8_fpArctanPiTest_b; fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s, en, fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b, fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b) BEGIN CASE fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3Low_uid82_atanX_uid8_fpArctanPiTest_b; WHEN "1" => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= fracRPath3High_uid81_atanX_uid8_fpArctanPiTest_b; WHEN OTHERS => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest(BITJOIN,85)@30 expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q & fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q; --reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0(REG,420)@30 reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= "000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q <= expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest(ADD,86)@31 expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracPreRnd_uid86_atanX_uid8_fpArctanPiTest_0_to_expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_0_q); expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("000000000000000000000000000000000" & VCC_q); expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_b)); expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_o(33 downto 0); --expRPath3_uid89_atanX_uid8_fpArctanPiTest(BITSELECT,88)@31 expRPath3_uid89_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(31 downto 0); expRPath3_uid89_atanX_uid8_fpArctanPiTest_b <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_in(31 downto 24); --reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4(REG,427)@31 reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q <= expRPath3_uid89_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,971) ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e(DELAY,534)@32 ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_inputreg_q, xout => ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,337)@33 RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 1); --rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,339)@33 rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= GND_q & RightShiftStage124dto1_uid338_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,333) rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000"; --rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,322) rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "000000000000000000000000"; --X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,321)@32 X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 24); --rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,323)@32 rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3Pad24_uid323_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto24_uid322_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(CONSTANT,319) rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= "0000000000000000"; --X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,318)@32 X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 16); --rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,320)@32 rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2Pad16_uid320_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & X24dto16_uid319_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,315)@32 X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 8); --rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,317)@32 rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q & X24dto8_uid316_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; --ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a(DELAY,504)@30 ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 24, depth => 2 ) PORT MAP ( xin => fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q, xout => ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest(BITJOIN,93)@32 oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q <= VCC_q & ld_fracRPath3Pre_uid83_atanX_uid8_fpArctanPiTest_q_to_oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_a_q; --cstWFP2_uid25_atanX_uid8_fpArctanPiTest(CONSTANT,24) cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q <= "00011001"; --reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1(REG,413)@30 reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q <= expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest(SUB,89)@31 shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBias_uid22_atanX_uid8_fpArctanPiTest_q); shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR((10 downto 9 => reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q(8)) & reg_expRPath3Ext_uid85_atanX_uid8_fpArctanPiTest_0_to_shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_1_q); shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_a) - SIGNED(shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_b)); shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_o(9 downto 0); --shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest(BITSELECT,91)@31 shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in <= shiftValPath2PreSub_uid90_atanX_uid8_fpArctanPiTest_q(7 downto 0); shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_in(7 downto 0); --cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest(CONSTANT,23) cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q <= "01101000"; --shiftOut_uid91_atanX_uid8_fpArctanPiTest(COMPARE,90)@13 shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin <= GND_q; shiftOut_uid91_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & '0'; shiftOut_uid91_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & cstBiasMWF_uid24_atanX_uid8_fpArctanPiTest_q) & shiftOut_uid91_atanX_uid8_fpArctanPiTest_cin(0); shiftOut_uid91_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(shiftOut_uid91_atanX_uid8_fpArctanPiTest_b)); shiftOut_uid91_atanX_uid8_fpArctanPiTest_c(0) <= shiftOut_uid91_atanX_uid8_fpArctanPiTest_o(10); --ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b(DELAY,502)@13 ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 18 ) PORT MAP ( xin => shiftOut_uid91_atanX_uid8_fpArctanPiTest_c, xout => ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --sValPostSOut_uid93_atanX_uid8_fpArctanPiTest(MUX,92)@31 sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s <= ld_shiftOut_uid91_atanX_uid8_fpArctanPiTest_c_to_sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_b_q; sValPostSOut_uid93_atanX_uid8_fpArctanPiTest: PROCESS (sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s, en, shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b, cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q) BEGIN CASE sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= shiftValPath2PreSubR_uid92_atanX_uid8_fpArctanPiTest_b; WHEN "1" => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= cstWFP2_uid25_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest(BITSELECT,94)@31 sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in <= sValPostSOut_uid93_atanX_uid8_fpArctanPiTest_q(4 downto 0); sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,324)@31 rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b; rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(4 downto 3); --reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,414)@31 reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,325)@32 rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel4Dto3_uid325_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q; rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q) BEGIN CASE rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= oFracRPath2_uid94_uid94_atanX_uid8_fpArctanPiTest_q; WHEN "01" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx1_uid318_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "10" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx2_uid321_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "11" => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage0Idx3_uid324_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,332)@32 RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 6); --ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,762)@32 ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 19, depth => 1 ) PORT MAP ( xin => RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,334)@33 rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3Pad6_uid334_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto6_uid333_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q; --RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,329)@32 RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 4); --ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,760)@32 ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 21, depth => 1 ) PORT MAP ( xin => RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,331)@33 rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage0Idx1Pad4_uid276_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto4_uid330_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q; --RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,326)@32 RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(24 downto 2); --ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a(DELAY,758)@32 ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITJOIN,328)@33 rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= leftShiftStage1Idx2Pad2_uid290_fxpU_uid72_atanX_uid8_fpArctanPiTest_q & ld_RightShiftStage024dto2_uid327_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_a_q; --reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2(REG,416)@32 reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= "0000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q <= rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,335)@31 rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(2 downto 1); --ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a(DELAY,844)@31 ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b, xout => ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,415)@32 reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= ld_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_to_reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_a_q; END IF; END IF; END PROCESS; --rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,336)@33 rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= reg_rightShiftStageSel2Dto1_uid336_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q; rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q, rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q) BEGIN CASE rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= reg_rightShiftStage0_uid326_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx1_uid329_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "10" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx2_uid332_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "11" => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1Idx3_uid335_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(BITSELECT,340)@31 rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in <= sValPostSOutR_uid95_atanX_uid8_fpArctanPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1(REG,417)@31 reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q <= rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b(DELAY,772)@32 ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q, xout => ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest(MUX,341)@33 rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s <= ld_reg_rightShiftStageSel0Dto0_uid341_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_0_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_1_q_to_rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_b_q; rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest: PROCESS (rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s, en, rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q, rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q) BEGIN CASE rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage1_uid337_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN "1" => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2Idx1_uid340_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest(BITJOIN,96)@33 pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q <= rightShiftStage2_uid342_fxpOp2Path2_uid96_atanX_uid8_fpArctanPiTest_q & GND_q; --reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1(REG,418)@33 reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q <= pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --path2Diff_uid97_atanX_uid8_fpArctanPiTest(SUB,97)@34 path2Diff_uid97_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid46_atanX_uid8_fpArctanPiTest_q); path2Diff_uid97_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & reg_pad_fxpOp2Path2_uid96_uid97_atanX_uid8_fpArctanPiTest_0_to_path2Diff_uid97_atanX_uid8_fpArctanPiTest_1_q); path2Diff_uid97_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(path2Diff_uid97_atanX_uid8_fpArctanPiTest_b)); path2Diff_uid97_atanX_uid8_fpArctanPiTest_q <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_o(26 downto 0); --normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest(BITSELECT,98)@34 normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(25 downto 0); normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_in(25 downto 25); --expRPath2_uid103_atanX_uid8_fpArctanPiTest(MUX,102)@34 expRPath2_uid103_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b; expRPath2_uid103_atanX_uid8_fpArctanPiTest: PROCESS (expRPath2_uid103_atanX_uid8_fpArctanPiTest_s, en, cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q, cstBias_uid22_atanX_uid8_fpArctanPiTest_q) BEGIN CASE expRPath2_uid103_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBiasM1_uid23_atanX_uid8_fpArctanPiTest_q; WHEN "1" => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPath2_uid103_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest(BITSELECT,99)@34 path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(24 downto 0); path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_in(24 downto 1); --path2DiffLow_uid101_atanX_uid8_fpArctanPiTest(BITSELECT,100)@34 path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in <= path2Diff_uid97_atanX_uid8_fpArctanPiTest_q(23 downto 0); path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_in(23 downto 0); --fracRPath2_uid102_atanX_uid8_fpArctanPiTest(MUX,101)@34 fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s <= normBitPath2Diff_uid99_atanX_uid8_fpArctanPiTest_b; fracRPath2_uid102_atanX_uid8_fpArctanPiTest: PROCESS (fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s, en, path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b, path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b) BEGIN CASE fracRPath2_uid102_atanX_uid8_fpArctanPiTest_s IS WHEN "0" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffLow_uid101_atanX_uid8_fpArctanPiTest_b; WHEN "1" => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= path2DiffHigh_uid100_atanX_uid8_fpArctanPiTest_b; WHEN OTHERS => fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest(BITJOIN,103)@34 expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q <= expRPath2_uid103_atanX_uid8_fpArctanPiTest_q & fracRPath2_uid102_atanX_uid8_fpArctanPiTest_q; --reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0(REG,419)@34 reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q <= expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest(ADD,104)@35 expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid104_uid104_atanX_uid8_fpArctanPiTest_0_to_expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_0_q); expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q); expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_b)); expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_o(32 downto 0); --expRPath2_uid107_atanX_uid8_fpArctanPiTest(BITSELECT,106)@35 expRPath2_uid107_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(31 downto 0); expRPath2_uid107_atanX_uid8_fpArctanPiTest_b <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_in(31 downto 24); --reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3(REG,426)@35 reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q <= expRPath2_uid107_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor(LOGICAL,1086) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q <= not (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_a or ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_b); --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena(REG,1087) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_nor_q = "1") THEN ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd(LOGICAL,1088) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_sticky_ena_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b <= en; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_a and ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_b; --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg(DELAY,1076) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expX_uid15_atanX_uid8_fpArctanPiTest_b, xout => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem(DUALMEM,1077) ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_inputreg_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 6, numwords_a => 33, width_b => 8, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq, address_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_aa, data_a => ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_ia ); ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_reset0 <= areset; ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_iq(7 downto 0); --reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2(REG,425)@35 reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q <= ld_expX_uid15_atanX_uid8_fpArctanPiTest_b_to_reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_a_replace_mem_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,944) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_a or ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top(CONSTANT,940) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q <= "010010"; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp(LOGICAL,941) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_mem_top_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q); ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q <= "1" when ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_a = ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_b else "0"; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg(REG,942) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,945) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,946) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --expXIsBias_uid44_atanX_uid8_fpArctanPiTest(LOGICAL,43)@0 expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a <= expX_uid15_atanX_uid8_fpArctanPiTest_b; expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b <= cstBias_uid22_atanX_uid8_fpArctanPiTest_q; expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q <= "1" when expXIsBias_uid44_atanX_uid8_fpArctanPiTest_a = expXIsBias_uid44_atanX_uid8_fpArctanPiTest_b else "0"; --inIsOne_uid45_atanX_uid8_fpArctanPiTest(LOGICAL,44)@0 inIsOne_uid45_atanX_uid8_fpArctanPiTest_a <= fracXIsZero_uid35_atanX_uid8_fpArctanPiTest_q; inIsOne_uid45_atanX_uid8_fpArctanPiTest_b <= expXIsBias_uid44_atanX_uid8_fpArctanPiTest_q; inIsOne_uid45_atanX_uid8_fpArctanPiTest_q <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_a and inIsOne_uid45_atanX_uid8_fpArctanPiTest_b; --arctanIsConst_uid55_atanX_uid8_fpArctanPiTest(LOGICAL,54)@0 arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a <= exc_I_uid36_atanX_uid8_fpArctanPiTest_q; arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b <= inIsOne_uid45_atanX_uid8_fpArctanPiTest_q; arctanIsConst_uid55_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q <= arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_a or arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c(DELAY,522)@1 ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q, xout => ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --biasMwShift_uid62_atanX_uid8_fpArctanPiTest(CONSTANT,61) biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q <= "01110011"; --atanUIsU_uid63_atanX_uid8_fpArctanPiTest(COMPARE,62)@13 atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin <= GND_q; atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid62_atanX_uid8_fpArctanPiTest_q) & '0'; atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b <= STD_LOGIC_VECTOR("00" & reg_expU_uid59_atanX_uid8_fpArctanPiTest_0_to_atanUIsU_uid63_atanX_uid8_fpArctanPiTest_1_q) & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_cin(0); atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_a) - UNSIGNED(atanUIsU_uid63_atanX_uid8_fpArctanPiTest_b)); atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n(0) <= not atanUIsU_uid63_atanX_uid8_fpArctanPiTest_o(10); --ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a(DELAY,520)@0 ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => path2_uid56_atanX_uid8_fpArctanPiTest_n, xout => ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --pathSelBits_uid108_atanX_uid8_fpArctanPiTest(BITJOIN,107)@13 pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q <= ld_arctanIsConst_uid55_atanX_uid8_fpArctanPiTest_q_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_c_q & atanUIsU_uid63_atanX_uid8_fpArctanPiTest_n & ld_path2_uid56_atanX_uid8_fpArctanPiTest_n_to_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_a_q; --reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0(REG,392)@13 reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q <= pathSelBits_uid108_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,934) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q, xout => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt(COUNTER,936) -- every=1, low=0, high=18, step=1, init=1 ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i = 17 THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_eq = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i - 18; ELSE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_i,5)); --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg(REG,937) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux(MUX,938) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s <= en; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux: PROCESS (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q, ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q) BEGIN CASE ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_s IS WHEN "0" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; WHEN "1" => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,935) ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdreg_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_rdmux_q; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 5, numwords_a => 19, width_b => 3, widthad_b => 5, numwords_b => 19, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(2 downto 0); --fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest(LOOKUP,108)@35 fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (ld_reg_pathSelBits_uid108_atanX_uid8_fpArctanPiTest_0_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_0_q_to_fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_a_replace_mem_q) IS WHEN "000" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "10"; WHEN "001" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "010" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "00"; WHEN "011" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "100" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "101" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "110" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "111" => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN OTHERS => fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --expRCalc_uid113_atanX_uid8_fpArctanPiTest(MUX,112)@36 expRCalc_uid113_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q; expRCalc_uid113_atanX_uid8_fpArctanPiTest: PROCESS (expRCalc_uid113_atanX_uid8_fpArctanPiTest_s, en, reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q, reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q, ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q, reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q) BEGIN CASE expRCalc_uid113_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expX_uid15_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_2_q; WHEN "01" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expRPath2_uid107_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_3_q; WHEN "10" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= ld_reg_expRPath3_uid89_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_4_q_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_e_q; WHEN "11" => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= reg_expOutCst_uid112_atanX_uid8_fpArctanPiTest_0_to_expRCalc_uid113_atanX_uid8_fpArctanPiTest_5_q; WHEN OTHERS => expRCalc_uid113_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --cstAllZWE_uid21_atanX_uid8_fpArctanPiTest(CONSTANT,20) cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q <= "00000000"; --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,995) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_a or ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,996) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,997) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,985) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_N_uid38_atanX_uid8_fpArctanPiTest_q, xout => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,986) ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(0 downto 0); --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor(LOGICAL,982) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q <= not (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_a or ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_b); --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena(REG,983) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_nor_q = "1") THEN ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd(LOGICAL,984) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b <= en; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_a and ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_b; --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg(DELAY,972) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q, xout => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem(DUALMEM,973) ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_inputreg_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 6, numwords_a => 33, width_b => 1, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq, address_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_aa, data_a => ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_ia ); ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_reset0 <= areset; ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_iq(0 downto 0); --excSelBits_uid114_atanX_uid8_fpArctanPiTest(BITJOIN,113)@35 excSelBits_uid114_atanX_uid8_fpArctanPiTest_q <= ld_exc_N_uid38_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_atanX_uid8_fpArctanPiTest_q_to_excSelBits_uid114_atanX_uid8_fpArctanPiTest_a_replace_mem_q; --reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0(REG,377)@35 reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q <= excSelBits_uid114_atanX_uid8_fpArctanPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest(LOOKUP,114)@36 outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest: PROCESS (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_excSelBits_uid114_atanX_uid8_fpArctanPiTest_0_to_outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid117_atanX_uid8_fpArctanPiTest(MUX,116)@36 expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q; expRPostExc_uid117_atanX_uid8_fpArctanPiTest: PROCESS (expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, expRCalc_uid113_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) BEGIN CASE expRPostExc_uid117_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; WHEN "01" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= expRCalc_uid113_atanX_uid8_fpArctanPiTest_q; WHEN "10" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN "11" => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracOutCst_uid110_atanX_uid8_fpArctanPiTest(BITSELECT,109)@35 fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in <= constOut_uid54_atanX_uid8_fpArctanPiTest_q(22 downto 0); fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_in(22 downto 0); --reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5(REG,424)@35 reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q <= fracOutCst_uid110_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor(LOGICAL,968) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q <= not (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_a or ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_b); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena(REG,969) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_nor_q = "1") THEN ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd(LOGICAL,970) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_sticky_ena_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b <= en; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_a and ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_b; --fracRPath3_uid88_atanX_uid8_fpArctanPiTest(BITSELECT,87)@31 fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in <= expfracRPath3PostRnd_uid87_atanX_uid8_fpArctanPiTest_q(23 downto 0); fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_in(23 downto 1); --reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4(REG,423)@31 reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q <= fracRPath3_uid88_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg(DELAY,960) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q, xout => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem(DUALMEM,961) ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_inputreg_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdreg_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_rdmux_q; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 1, numwords_a => 2, width_b => 23, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0, clock1 => clk, address_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq, address_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_aa, data_a => ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_ia ); ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_reset0 <= areset; ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_iq(22 downto 0); --fracRPath2_uid106_atanX_uid8_fpArctanPiTest(BITSELECT,105)@35 fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in <= expFracRPath2PostRnd_uid105_atanX_uid8_fpArctanPiTest_q(23 downto 0); fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_in(23 downto 1); --reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3(REG,422)@35 reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q <= fracRPath2_uid106_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor(LOGICAL,957) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_notEnable_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q <= not (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_a or ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_b); --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena(REG,958) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_nor_q = "1") THEN ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd(LOGICAL,959) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_sticky_ena_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b <= en; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_a and ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_b; --reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2(REG,421)@0 reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q <= fracX_uid16_atanX_uid8_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg(DELAY,947) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q, xout => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem(DUALMEM,948) ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_inputreg_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdreg_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab <= ld_singX_uid17_atanX_uid8_fpArctanPiTest_b_to_fpPiO2C_uid49_atanX_uid8_fpArctanPiTest_c_replace_rdmux_q; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 6, numwords_a => 33, width_b => 23, widthad_b => 6, numwords_b => 33, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq, address_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_aa, data_a => ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_ia ); ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_reset0 <= areset; ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_iq(22 downto 0); --fracRCalc_uid111_atanX_uid8_fpArctanPiTest(MUX,110)@36 fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s <= fracOutMuxSelEnc_uid109_atanX_uid8_fpArctanPiTest_q; fracRCalc_uid111_atanX_uid8_fpArctanPiTest: PROCESS (fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s, en, ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q, reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q, ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q, reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q) BEGIN CASE fracRCalc_uid111_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracX_uid16_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_2_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_c_replace_mem_q; WHEN "01" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracRPath2_uid106_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_3_q; WHEN "10" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= ld_reg_fracRPath3_uid88_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_4_q_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_e_replace_mem_q; WHEN "11" => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= reg_fracOutCst_uid110_atanX_uid8_fpArctanPiTest_0_to_fracRCalc_uid111_atanX_uid8_fpArctanPiTest_5_q; WHEN OTHERS => fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPostExc_uid116_atanX_uid8_fpArctanPiTest(MUX,115)@36 fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s <= outMuxSelEnc_uid115_atanX_uid8_fpArctanPiTest_q; fracRPostExc_uid116_atanX_uid8_fpArctanPiTest: PROCESS (fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q) BEGIN CASE fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_s IS WHEN "00" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "01" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= fracRCalc_uid111_atanX_uid8_fpArctanPiTest_q; WHEN "10" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "11" => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid120_atanX_uid8_fpArctanPiTest(BITJOIN,119)@36 R_uid120_atanX_uid8_fpArctanPiTest_q <= ld_signR_uid119_atanX_uid8_fpArctanPiTest_q_to_R_uid120_atanX_uid8_fpArctanPiTest_c_replace_mem_q & expRPostExc_uid117_atanX_uid8_fpArctanPiTest_q & fracRPostExc_uid116_atanX_uid8_fpArctanPiTest_q; --fracX_uid126_rAtanPi_uid13_fpArctanPiTest(BITSELECT,125)@36 fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(22 downto 0); fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0); --reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1(REG,431)@36 reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q <= fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest(LOGICAL,137)@37 fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a <= reg_fracX_uid126_rAtanPi_uid13_fpArctanPiTest_0_to_fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_1_q; fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_b else "0"; --expX_uid122_rAtanPi_uid13_fpArctanPiTest(BITSELECT,121)@36 expX_uid122_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q(30 downto 0); expX_uid122_rAtanPi_uid13_fpArctanPiTest_b <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23); --reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1(REG,429)@36 reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q <= expX_uid122_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest(LOGICAL,135)@37 expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q; expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_b else "0"; --exc_I_uid139_rAtanPi_uid13_fpArctanPiTest(LOGICAL,138)@37 exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q; exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q; exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_b; --cstBiasM2_uid6_fpArctanPiTest(CONSTANT,5) cstBiasM2_uid6_fpArctanPiTest_q <= "01111101"; --ooPi_uid9_fpArctanPiTest(CONSTANT,8) ooPi_uid9_fpArctanPiTest_q <= "101000101111100110000011"; --fracOOPi_uid10_fpArctanPiTest(BITSELECT,9)@36 fracOOPi_uid10_fpArctanPiTest_in <= ooPi_uid9_fpArctanPiTest_q(22 downto 0); fracOOPi_uid10_fpArctanPiTest_b <= fracOOPi_uid10_fpArctanPiTest_in(22 downto 0); --fpOOPi_uid11_fpArctanPiTest(BITJOIN,10)@36 fpOOPi_uid11_fpArctanPiTest_q <= GND_q & cstBiasM2_uid6_fpArctanPiTest_q & fracOOPi_uid10_fpArctanPiTest_b; --expY_uid123_rAtanPi_uid13_fpArctanPiTest(BITSELECT,122)@36 expY_uid123_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(30 downto 0); expY_uid123_rAtanPi_uid13_fpArctanPiTest_b <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_in(30 downto 23); --expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest(LOGICAL,149)@36 expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b; expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_b else "0"; --ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a(DELAY,581)@36 ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest(LOGICAL,203)@37 excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_b; --fracY_uid128_rAtanPi_uid13_fpArctanPiTest(BITSELECT,127)@36 fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q(22 downto 0); fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_in(22 downto 0); --fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest(LOGICAL,153)@36 fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a <= fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b; fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q <= "1" when fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_a = fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_b else "0"; --ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b(DELAY,575)@36 ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest(LOGICAL,151)@36 expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a <= expY_uid123_rAtanPi_uid13_fpArctanPiTest_b; expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_a = expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_b else "0"; --ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a(DELAY,574)@36 ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --exc_I_uid155_rAtanPi_uid13_fpArctanPiTest(LOGICAL,154)@37 exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a_q; exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b <= ld_fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q_to_exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b_q; exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_a and exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_b; --expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest(LOGICAL,133)@37 expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a <= reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q; expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q <= "1" when expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_a = expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_b else "0"; --excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest(LOGICAL,204)@37 excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_b; --ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest(LOGICAL,205)@37 ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a <= excXZAndExcYI_uid205_rAtanPi_uid13_fpArctanPiTest_q; ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b <= excYZAndExcXI_uid204_rAtanPi_uid13_fpArctanPiTest_q; ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_a or ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_b; --InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest(LOGICAL,155)@36 InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid154_rAtanPi_uid13_fpArctanPiTest_q; InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_a; --exc_N_uid157_rAtanPi_uid13_fpArctanPiTest(LOGICAL,156)@36 exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid152_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid156_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_b; --ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a(DELAY,579)@36 ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest(LOGICAL,139)@37 InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a <= fracXIsZero_uid138_rAtanPi_uid13_fpArctanPiTest_q; InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q <= not InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_a; --exc_N_uid141_rAtanPi_uid13_fpArctanPiTest(LOGICAL,140)@37 exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a <= expXIsMax_uid136_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b <= InvFracXIsZero_uid140_rAtanPi_uid13_fpArctanPiTest_q; exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_a and exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_b; --excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest(LOGICAL,206)@37 excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q; excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q; excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c <= ZeroTimesInf_uid206_rAtanPi_uid13_fpArctanPiTest_q; excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_a or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_b or excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_c; --VCC(CONSTANT,1) VCC_q <= "1"; --InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest(LOGICAL,218)@37 InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a <= excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q; InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q <= not InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_a; END IF; END PROCESS; --signY_uid125_rAtanPi_uid13_fpArctanPiTest(BITSELECT,124)@36 signY_uid125_rAtanPi_uid13_fpArctanPiTest_in <= fpOOPi_uid11_fpArctanPiTest_q; signY_uid125_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31); --signX_uid124_rAtanPi_uid13_fpArctanPiTest(BITSELECT,123)@36 signX_uid124_rAtanPi_uid13_fpArctanPiTest_in <= R_uid120_atanX_uid8_fpArctanPiTest_q; signX_uid124_rAtanPi_uid13_fpArctanPiTest_b <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_in(31 downto 31); --signR_uid190_rAtanPi_uid13_fpArctanPiTest(LOGICAL,189)@36 signR_uid190_rAtanPi_uid13_fpArctanPiTest_a <= signX_uid124_rAtanPi_uid13_fpArctanPiTest_b; signR_uid190_rAtanPi_uid13_fpArctanPiTest_b <= signY_uid125_rAtanPi_uid13_fpArctanPiTest_b; signR_uid190_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN signR_uid190_rAtanPi_uid13_fpArctanPiTest_q <= signR_uid190_rAtanPi_uid13_fpArctanPiTest_a xor signR_uid190_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a(DELAY,666)@37 ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid190_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest(LOGICAL,219)@38 signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a <= ld_signR_uid190_rAtanPi_uid13_fpArctanPiTest_q_to_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a_q; signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b <= InvExcRNaN_uid219_rAtanPi_uid13_fpArctanPiTest_q; signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q <= signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_a and signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_b; --ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c(DELAY,670)@38 ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest(BITJOIN,128)@36 add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracY_uid128_rAtanPi_uid13_fpArctanPiTest_b; --reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1(REG,433)@36 reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q <= add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest(BITJOIN,126)@36 add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q <= VCC_q & fracX_uid126_rAtanPi_uid13_fpArctanPiTest_b; --reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0(REG,432)@36 reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q <= add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --prod_uid165_rAtanPi_uid13_fpArctanPiTest(MULT,164)@37 prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr <= UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_a) * UNSIGNED(prod_uid165_rAtanPi_uid13_fpArctanPiTest_b); prod_uid165_rAtanPi_uid13_fpArctanPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= (others => '0'); prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= (others => '0'); prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_a <= reg_add_one_fracX_uid126_uid127_uid127_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_0_q; prod_uid165_rAtanPi_uid13_fpArctanPiTest_b <= reg_add_one_fracY_uid128_uid129_uid129_rAtanPi_uid13_fpArctanPiTest_0_to_prod_uid165_rAtanPi_uid13_fpArctanPiTest_1_q; prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid165_rAtanPi_uid13_fpArctanPiTest_pr); END IF; END IF; END PROCESS; prod_uid165_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid165_rAtanPi_uid13_fpArctanPiTest_q <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest(BITSELECT,165)@40 normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q; normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_in(47 downto 47); --roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest(CONSTANT,179) roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q <= "010"; --fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest(BITSELECT,167)@40 fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(46 downto 0); fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_in(46 downto 23); --fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest(BITSELECT,168)@40 fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(45 downto 0); fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_in(45 downto 22); --fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest(MUX,169)@40 fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b; fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s, en, fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b, fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b) BEGIN CASE fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "0" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormLow_uid169_rAtanPi_uid13_fpArctanPiTest_b; WHEN "1" => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= fracRPostNormHigh_uid168_rAtanPi_uid13_fpArctanPiTest_b; WHEN OTHERS => fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest(BITSELECT,177)@40 FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in <= fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q(1 downto 0); FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_in(1 downto 0); --Prod22_uid172_rAtanPi_uid13_fpArctanPiTest(BITSELECT,171)@40 Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(22 downto 0); Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_in(22 downto 22); --extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest(MUX,172)@40 extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s <= normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b; extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest: PROCESS (extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s, en, GND_q, Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b) BEGIN CASE extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "0" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= Prod22_uid172_rAtanPi_uid13_fpArctanPiTest_b; WHEN OTHERS => extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest(BITSELECT,170)@40 stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in <= prod_uid165_rAtanPi_uid13_fpArctanPiTest_q(21 downto 0); stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b <= stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_in(21 downto 0); --stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest(BITJOIN,173)@40 stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q <= extraStickyBit_uid173_rAtanPi_uid13_fpArctanPiTest_q & stickyRange_uid171_rAtanPi_uid13_fpArctanPiTest_b; --stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest(LOGICAL,175)@40 stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a <= stickyExtendedRange_uid174_rAtanPi_uid13_fpArctanPiTest_q; stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q <= "1" when stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_a = stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_b else "0"; --sticky_uid177_rAtanPi_uid13_fpArctanPiTest(LOGICAL,176)@40 sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a <= stickyRangeComparator_uid176_rAtanPi_uid13_fpArctanPiTest_q; sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q <= not sticky_uid177_rAtanPi_uid13_fpArctanPiTest_a; --lrs_uid179_rAtanPi_uid13_fpArctanPiTest(BITJOIN,178)@40 lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q <= FracRPostNorm1dto0_uid178_rAtanPi_uid13_fpArctanPiTest_b & sticky_uid177_rAtanPi_uid13_fpArctanPiTest_q; --roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest(LOGICAL,180)@40 roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a <= lrs_uid179_rAtanPi_uid13_fpArctanPiTest_q; roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b <= roundBitDetectionConstant_uid180_rAtanPi_uid13_fpArctanPiTest_q; roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q <= "1" when roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_a = roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_b else "0"; --roundBit_uid182_rAtanPi_uid13_fpArctanPiTest(LOGICAL,181)@40 roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a <= roundBitDetectionPattern_uid181_rAtanPi_uid13_fpArctanPiTest_q; roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q <= not roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_a; --roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest(BITJOIN,184)@40 roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q <= GND_q & normalizeBit_uid166_rAtanPi_uid13_fpArctanPiTest_b & cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q & roundBit_uid182_rAtanPi_uid13_fpArctanPiTest_q; --reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1(REG,436)@40 reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q <= roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --biasInc_uid163_rAtanPi_uid13_fpArctanPiTest(CONSTANT,162) biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q <= "0001111111"; --ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b(DELAY,586)@36 ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expY_uid123_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expSum_uid162_rAtanPi_uid13_fpArctanPiTest(ADD,161)@37 expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid122_rAtanPi_uid13_fpArctanPiTest_0_to_expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_1_q); expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR("0" & ld_expY_uid123_rAtanPi_uid13_fpArctanPiTest_b_to_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b_q); expSum_uid162_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_a) + UNSIGNED(expSum_uid162_rAtanPi_uid13_fpArctanPiTest_b)); END IF; END IF; END PROCESS; expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q <= expSum_uid162_rAtanPi_uid13_fpArctanPiTest_o(8 downto 0); --ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a(DELAY,587)@38 ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest(SUB,163)@39 expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid162_rAtanPi_uid13_fpArctanPiTest_q_to_expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a_q); expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q(9)) & biasInc_uid163_rAtanPi_uid13_fpArctanPiTest_q); expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_o(10 downto 0); --expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest(BITJOIN,182)@40 expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q <= expSumMBias_uid164_rAtanPi_uid13_fpArctanPiTest_q & fracRPostNorm_uid170_rAtanPi_uid13_fpArctanPiTest_q; --reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0(REG,435)@40 reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q <= expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest(ADD,185)@41 expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q(34)) & reg_expFracPreRound_uid183_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_0_q); expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid185_rAtanPi_uid13_fpArctanPiTest_0_to_expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_1_q); expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_a) + SIGNED(expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_b)); expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_o(35 downto 0); --expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest(BITSELECT,187)@41 expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q; expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_in(35 downto 24); --expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest(BITSELECT,188)@41 expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b(7 downto 0); expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b <= expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_in(7 downto 0); --ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d(DELAY,664)@41 ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay GENERIC MAP ( width => 8, depth => 2 ) PORT MAP ( xin => expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c(DELAY,659)@37 ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1(REG,437)@41 reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q <= expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid193_rAtanPi_uid13_fpArctanPiTest(COMPARE,192)@42 expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q; expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & '0'; expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) & expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_cin(0); expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_b)); expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_o(14); --InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest(LOGICAL,157)@37 InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_N_uid157_rAtanPi_uid13_fpArctanPiTest_q_to_InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a_q; InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_a; --InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest(LOGICAL,158)@37 InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_a; --InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest(LOGICAL,159)@37 InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a; --exc_R_uid161_rAtanPi_uid13_fpArctanPiTest(LOGICAL,160)@37 exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid159_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid158_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_c; --ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b(DELAY,629)@37 ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest(LOGICAL,141)@37 InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a <= exc_N_uid141_rAtanPi_uid13_fpArctanPiTest_q; InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_a; --InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest(LOGICAL,142)@37 InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q <= not InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_a; --InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest(LOGICAL,143)@37 InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q <= not InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_a; --exc_R_uid145_rAtanPi_uid13_fpArctanPiTest(LOGICAL,144)@37 exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a <= InvExpXIsZero_uid144_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b <= InvExc_I_uid143_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c <= InvExc_N_uid142_rAtanPi_uid13_fpArctanPiTest_q; exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_a and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_b and exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_c; --ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a(DELAY,628)@37 ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest(LOGICAL,201)@42 ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q; ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q; ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c <= expOvf_uid193_rAtanPi_uid13_fpArctanPiTest_n; ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_a and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_b and ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_c; --excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest(LOGICAL,200)@37 excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q; excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q <= excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_a and excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_b; --ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c(DELAY,646)@37 ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest(LOGICAL,199)@37 excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q; excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q <= excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_a and excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b(DELAY,645)@37 ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest(LOGICAL,198)@37 excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a <= exc_I_uid139_rAtanPi_uid13_fpArctanPiTest_q; excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b <= exc_I_uid155_rAtanPi_uid13_fpArctanPiTest_q; excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q <= excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_a and excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a(DELAY,644)@37 ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid203_rAtanPi_uid13_fpArctanPiTest(LOGICAL,202)@42 excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXIAndExcYI_uid199_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXRAndExcYI_uid200_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYRAndExcXI_uid201_rAtanPi_uid13_fpArctanPiTest_q_to_excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d <= ExcROvfAndInReg_uid202_rAtanPi_uid13_fpArctanPiTest_q; excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q <= excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_a or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_b or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_c or excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_d; --expUdf_uid191_rAtanPi_uid13_fpArctanPiTest(COMPARE,190)@42 expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin <= GND_q; expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q(11)) & reg_expRPreExcExt_uid188_rAtanPi_uid13_fpArctanPiTest_0_to_expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_1_q) & expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_cin(0); expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_a) - SIGNED(expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_b)); expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n(0) <= not expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_o(14); --excZC3_uid197_rAtanPi_uid13_fpArctanPiTest(LOGICAL,196)@42 excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a <= ld_exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a_q; excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b <= ld_exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q_to_excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b_q; excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c <= expUdf_uid191_rAtanPi_uid13_fpArctanPiTest_n; excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_a and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_b and excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_c; --excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest(LOGICAL,195)@37 excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid145_rAtanPi_uid13_fpArctanPiTest_q; excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q <= excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_a and excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_b; --ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c(DELAY,633)@37 ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest(LOGICAL,194)@37 excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b <= exc_R_uid161_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b(DELAY,632)@37 ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest(LOGICAL,193)@37 excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a <= expXIsZero_uid134_rAtanPi_uid13_fpArctanPiTest_q; excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b <= ld_expXIsZero_uid150_rAtanPi_uid13_fpArctanPiTest_q_to_InvExpXIsZero_uid160_rAtanPi_uid13_fpArctanPiTest_a_q; excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q <= excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_a and excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_b; --ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a(DELAY,631)@37 ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q, xout => ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid198_rAtanPi_uid13_fpArctanPiTest(LOGICAL,197)@42 excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a <= ld_excXZAndExcYZ_uid194_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b <= ld_excXZAndExcYR_uid195_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c <= ld_excYZAndExcXR_uid196_rAtanPi_uid13_fpArctanPiTest_q_to_excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d <= excZC3_uid197_rAtanPi_uid13_fpArctanPiTest_q; excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q <= excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_a or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_b or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_c or excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_d; --concExc_uid208_rAtanPi_uid13_fpArctanPiTest(BITJOIN,207)@42 concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q <= ld_excRNaN_uid207_rAtanPi_uid13_fpArctanPiTest_q_to_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_c_q & excRInf_uid203_rAtanPi_uid13_fpArctanPiTest_q & excRZero_uid198_rAtanPi_uid13_fpArctanPiTest_q; --reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0(REG,439)@42 reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q <= concExc_uid208_rAtanPi_uid13_fpArctanPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid209_rAtanPi_uid13_fpArctanPiTest(LOOKUP,208)@43 excREnc_uid209_rAtanPi_uid13_fpArctanPiTest: PROCESS (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid208_rAtanPi_uid13_fpArctanPiTest_0_to_excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_0_q) IS WHEN "000" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "01"; WHEN "001" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "010" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "10"; WHEN "011" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "100" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "11"; WHEN "101" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "110" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN "111" => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= "00"; WHEN OTHERS => excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest(MUX,217)@43 expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q; expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest: PROCESS (expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q, ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q, cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q) BEGIN CASE expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "00" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWE_uid21_atanX_uid8_fpArctanPiTest_q; WHEN "01" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= ld_expRPreExc_uid189_rAtanPi_uid13_fpArctanPiTest_b_to_expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_d_q; WHEN "10" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN "11" => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= cstAllOWE_uid18_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest(BITSELECT,186)@41 fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in <= expFracRPostRounding_uid186_rAtanPi_uid13_fpArctanPiTest_q(23 downto 0); fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b <= fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_in(23 downto 1); --ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d(DELAY,662)@41 ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b, xout => ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest(MUX,212)@43 fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s <= excREnc_uid209_rAtanPi_uid13_fpArctanPiTest_q; fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest: PROCESS (fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s, en, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q, cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q, cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q) BEGIN CASE fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_s IS WHEN "00" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "01" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= ld_fracRPreExc_uid187_rAtanPi_uid13_fpArctanPiTest_b_to_fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_d_q; WHEN "10" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstAllZWF_uid19_atanX_uid8_fpArctanPiTest_q; WHEN "11" => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= cstNaNWF_uid20_atanX_uid8_fpArctanPiTest_q; WHEN OTHERS => fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid221_rAtanPi_uid13_fpArctanPiTest(BITJOIN,220)@43 R_uid221_rAtanPi_uid13_fpArctanPiTest_q <= ld_signRPostExc_uid220_rAtanPi_uid13_fpArctanPiTest_q_to_R_uid221_rAtanPi_uid13_fpArctanPiTest_c_q & expRPostExc_uid218_rAtanPi_uid13_fpArctanPiTest_q & fracRPostExc_uid213_rAtanPi_uid13_fpArctanPiTest_q; --xOut(GPOUT,4)@43 q <= R_uid221_rAtanPi_uid13_fpArctanPiTest_q; end normal;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/dp_explut10.vhd

10

174445

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUT10.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explut10 IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC ); END dp_explut10; ARCHITECTURE rtl OF dp_explut10 IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= '0'; WHEN "0000000001" => manhi <= conv_std_logic_vector(16392,24); manlo <= conv_std_logic_vector(699221,28); exponent <= '0'; WHEN "0000000010" => manhi <= conv_std_logic_vector(32800,24); manlo <= conv_std_logic_vector(5595137,28); exponent <= '0'; WHEN "0000000011" => manhi <= conv_std_logic_vector(49224,24); manlo <= conv_std_logic_vector(18888200,28); exponent <= '0'; WHEN "0000000100" => manhi <= conv_std_logic_vector(65664,24); manlo <= conv_std_logic_vector(44782967,28); exponent <= '0'; WHEN "0000000101" => manhi <= conv_std_logic_vector(82120,24); manlo <= conv_std_logic_vector(87488104,28); exponent <= '0'; WHEN "0000000110" => manhi <= conv_std_logic_vector(98592,24); manlo <= conv_std_logic_vector(151216387,28); exponent <= '0'; WHEN "0000000111" => manhi <= conv_std_logic_vector(115080,24); manlo <= conv_std_logic_vector(240184710,28); exponent <= '0'; WHEN "0000001000" => manhi <= conv_std_logic_vector(131585,24); manlo <= conv_std_logic_vector(90178630,28); exponent <= '0'; WHEN "0000001001" => manhi <= conv_std_logic_vector(148105,24); manlo <= conv_std_logic_vector(242294195,28); exponent <= '0'; WHEN "0000001010" => manhi <= conv_std_logic_vector(164642,24); manlo <= conv_std_logic_vector(163889760,28); exponent <= '0'; WHEN "0000001011" => manhi <= conv_std_logic_vector(181195,24); manlo <= conv_std_logic_vector(127634178,28); exponent <= '0'; WHEN "0000001100" => manhi <= conv_std_logic_vector(197764,24); manlo <= conv_std_logic_vector(137764983,28); exponent <= '0'; WHEN "0000001101" => manhi <= conv_std_logic_vector(214349,24); manlo <= conv_std_logic_vector(198523848,28); exponent <= '0'; WHEN "0000001110" => manhi <= conv_std_logic_vector(230951,24); manlo <= conv_std_logic_vector(45721136,28); exponent <= '0'; WHEN "0000001111" => manhi <= conv_std_logic_vector(247568,24); manlo <= conv_std_logic_vector(220477726,28); exponent <= '0'; WHEN "0000010000" => manhi <= conv_std_logic_vector(264202,24); manlo <= conv_std_logic_vector(190176825,28); exponent <= '0'; WHEN "0000010001" => manhi <= conv_std_logic_vector(280852,24); manlo <= conv_std_logic_vector(227512164,28); exponent <= '0'; WHEN "0000010010" => manhi <= conv_std_logic_vector(297519,24); manlo <= conv_std_logic_vector(68310723,28); exponent <= '0'; WHEN "0000010011" => manhi <= conv_std_logic_vector(314201,24); manlo <= conv_std_logic_vector(253710014,28); exponent <= '0'; WHEN "0000010100" => manhi <= conv_std_logic_vector(330900,24); manlo <= conv_std_logic_vector(251109895,28); exponent <= '0'; WHEN "0000010101" => manhi <= conv_std_logic_vector(347616,24); manlo <= conv_std_logic_vector(64785307,28); exponent <= '0'; WHEN "0000010110" => manhi <= conv_std_logic_vector(364347,24); manlo <= conv_std_logic_vector(235886282,28); exponent <= '0'; WHEN "0000010111" => manhi <= conv_std_logic_vector(381095,24); manlo <= conv_std_logic_vector(231825206,28); exponent <= '0'; WHEN "0000011000" => manhi <= conv_std_logic_vector(397860,24); manlo <= conv_std_logic_vector(56889565,28); exponent <= '0'; WHEN "0000011001" => manhi <= conv_std_logic_vector(414640,24); manlo <= conv_std_logic_vector(252241943,28); exponent <= '0'; WHEN "0000011010" => manhi <= conv_std_logic_vector(431438,24); manlo <= conv_std_logic_vector(16871840,28); exponent <= '0'; WHEN "0000011011" => manhi <= conv_std_logic_vector(448251,24); manlo <= conv_std_logic_vector(160385687,28); exponent <= '0'; WHEN "0000011100" => manhi <= conv_std_logic_vector(465081,24); manlo <= conv_std_logic_vector(150216837,28); exponent <= '0'; WHEN "0000011101" => manhi <= conv_std_logic_vector(481927,24); manlo <= conv_std_logic_vector(259109217,28); exponent <= '0'; WHEN "0000011110" => manhi <= conv_std_logic_vector(498790,24); manlo <= conv_std_logic_vector(222940052,28); exponent <= '0'; WHEN "0000011111" => manhi <= conv_std_logic_vector(515670,24); manlo <= conv_std_logic_vector(46026234,28); exponent <= '0'; WHEN "0000100000" => manhi <= conv_std_logic_vector(532566,24); manlo <= conv_std_logic_vector(1124333,28); exponent <= '0'; WHEN "0000100001" => manhi <= conv_std_logic_vector(549478,24); manlo <= conv_std_logic_vector(92559680,28); exponent <= '0'; WHEN "0000100010" => manhi <= conv_std_logic_vector(566407,24); manlo <= conv_std_logic_vector(56226380,28); exponent <= '0'; WHEN "0000100011" => manhi <= conv_std_logic_vector(583352,24); manlo <= conv_std_logic_vector(164893679,28); exponent <= '0'; WHEN "0000100100" => manhi <= conv_std_logic_vector(600314,24); manlo <= conv_std_logic_vector(154464145,28); exponent <= '0'; WHEN "0000100101" => manhi <= conv_std_logic_vector(617293,24); manlo <= conv_std_logic_vector(29280039,28); exponent <= '0'; WHEN "0000100110" => manhi <= conv_std_logic_vector(634288,24); manlo <= conv_std_logic_vector(62123323,28); exponent <= '0'; WHEN "0000100111" => manhi <= conv_std_logic_vector(651299,24); manlo <= conv_std_logic_vector(257344748,28); exponent <= '0'; WHEN "0000101000" => manhi <= conv_std_logic_vector(668328,24); manlo <= conv_std_logic_vector(82428406,28); exponent <= '0'; WHEN "0000101001" => manhi <= conv_std_logic_vector(685373,24); manlo <= conv_std_logic_vector(78604464,28); exponent <= '0'; WHEN "0000101010" => manhi <= conv_std_logic_vector(702434,24); manlo <= conv_std_logic_vector(250236442,28); exponent <= '0'; WHEN "0000101011" => manhi <= conv_std_logic_vector(719513,24); manlo <= conv_std_logic_vector(64821205,28); exponent <= '0'; WHEN "0000101100" => manhi <= conv_std_logic_vector(736608,24); manlo <= conv_std_logic_vector(63601714,28); exponent <= '0'; WHEN "0000101101" => manhi <= conv_std_logic_vector(753719,24); manlo <= conv_std_logic_vector(250954289,28); exponent <= '0'; WHEN "0000101110" => manhi <= conv_std_logic_vector(770848,24); manlo <= conv_std_logic_vector(94388611,28); exponent <= '0'; WHEN "0000101111" => manhi <= conv_std_logic_vector(787993,24); manlo <= conv_std_logic_vector(135160468,28); exponent <= '0'; WHEN "0000110000" => manhi <= conv_std_logic_vector(805155,24); manlo <= conv_std_logic_vector(109223564,28); exponent <= '0'; WHEN "0000110001" => manhi <= conv_std_logic_vector(822334,24); manlo <= conv_std_logic_vector(20971345,28); exponent <= '0'; WHEN "0000110010" => manhi <= conv_std_logic_vector(839529,24); manlo <= conv_std_logic_vector(143237009,28); exponent <= '0'; WHEN "0000110011" => manhi <= conv_std_logic_vector(856741,24); manlo <= conv_std_logic_vector(211987135,28); exponent <= '0'; WHEN "0000110100" => manhi <= conv_std_logic_vector(873970,24); manlo <= conv_std_logic_vector(231628063,28); exponent <= '0'; WHEN "0000110101" => manhi <= conv_std_logic_vector(891216,24); manlo <= conv_std_logic_vector(206570434,28); exponent <= '0'; WHEN "0000110110" => manhi <= conv_std_logic_vector(908479,24); manlo <= conv_std_logic_vector(141229202,28); exponent <= '0'; WHEN "0000110111" => manhi <= conv_std_logic_vector(925759,24); manlo <= conv_std_logic_vector(40023632,28); exponent <= '0'; WHEN "0000111000" => manhi <= conv_std_logic_vector(943055,24); manlo <= conv_std_logic_vector(175812765,28); exponent <= '0'; WHEN "0000111001" => manhi <= conv_std_logic_vector(960369,24); manlo <= conv_std_logic_vector(16153594,28); exponent <= '0'; WHEN "0000111010" => manhi <= conv_std_logic_vector(977699,24); manlo <= conv_std_logic_vector(102349263,28); exponent <= '0'; WHEN "0000111011" => manhi <= conv_std_logic_vector(995046,24); manlo <= conv_std_logic_vector(170400879,28); exponent <= '0'; WHEN "0000111100" => manhi <= conv_std_logic_vector(1012410,24); manlo <= conv_std_logic_vector(224749339,28); exponent <= '0'; WHEN "0000111101" => manhi <= conv_std_logic_vector(1029792,24); manlo <= conv_std_logic_vector(1404424,28); exponent <= '0'; WHEN "0000111110" => manhi <= conv_std_logic_vector(1047190,24); manlo <= conv_std_logic_vector(41686624,28); exponent <= '0'; WHEN "0000111111" => manhi <= conv_std_logic_vector(1064605,24); manlo <= conv_std_logic_vector(81614410,28); exponent <= '0'; WHEN "0001000000" => manhi <= conv_std_logic_vector(1082037,24); manlo <= conv_std_logic_vector(125646062,28); exponent <= '0'; WHEN "0001000001" => manhi <= conv_std_logic_vector(1099486,24); manlo <= conv_std_logic_vector(178244212,28); exponent <= '0'; WHEN "0001000010" => manhi <= conv_std_logic_vector(1116952,24); manlo <= conv_std_logic_vector(243875856,28); exponent <= '0'; WHEN "0001000011" => manhi <= conv_std_logic_vector(1134436,24); manlo <= conv_std_logic_vector(58576897,28); exponent <= '0'; WHEN "0001000100" => manhi <= conv_std_logic_vector(1151936,24); manlo <= conv_std_logic_vector(163693974,28); exponent <= '0'; WHEN "0001000101" => manhi <= conv_std_logic_vector(1169454,24); manlo <= conv_std_logic_vector(26836276,28); exponent <= '0'; WHEN "0001000110" => manhi <= conv_std_logic_vector(1186988,24); manlo <= conv_std_logic_vector(189359192,28); exponent <= '0'; WHEN "0001000111" => manhi <= conv_std_logic_vector(1204540,24); manlo <= conv_std_logic_vector(118880671,28); exponent <= '0'; WHEN "0001001000" => manhi <= conv_std_logic_vector(1222109,24); manlo <= conv_std_logic_vector(88329413,28); exponent <= '0'; WHEN "0001001001" => manhi <= conv_std_logic_vector(1239695,24); manlo <= conv_std_logic_vector(102203053,28); exponent <= '0'; WHEN "0001001010" => manhi <= conv_std_logic_vector(1257298,24); manlo <= conv_std_logic_vector(165003622,28); exponent <= '0'; WHEN "0001001011" => manhi <= conv_std_logic_vector(1274919,24); manlo <= conv_std_logic_vector(12802090,28); exponent <= '0'; WHEN "0001001100" => manhi <= conv_std_logic_vector(1292556,24); manlo <= conv_std_logic_vector(186980202,28); exponent <= '0'; WHEN "0001001101" => manhi <= conv_std_logic_vector(1310211,24); manlo <= conv_std_logic_vector(155182284,28); exponent <= '0'; WHEN "0001001110" => manhi <= conv_std_logic_vector(1327883,24); manlo <= conv_std_logic_vector(190363442,28); exponent <= '0'; WHEN "0001001111" => manhi <= conv_std_logic_vector(1345573,24); manlo <= conv_std_logic_vector(28612286,28); exponent <= '0'; WHEN "0001010000" => manhi <= conv_std_logic_vector(1363279,24); manlo <= conv_std_logic_vector(211328214,28); exponent <= '0'; WHEN "0001010001" => manhi <= conv_std_logic_vector(1381003,24); manlo <= conv_std_logic_vector(206173225,28); exponent <= '0'; WHEN "0001010010" => manhi <= conv_std_logic_vector(1398745,24); manlo <= conv_std_logic_vector(17684657,28); exponent <= '0'; WHEN "0001010011" => manhi <= conv_std_logic_vector(1416503,24); manlo <= conv_std_logic_vector(187275197,28); exponent <= '0'; WHEN "0001010100" => manhi <= conv_std_logic_vector(1434279,24); manlo <= conv_std_logic_vector(182620141,28); exponent <= '0'; WHEN "0001010101" => manhi <= conv_std_logic_vector(1452073,24); manlo <= conv_std_logic_vector(8270141,28); exponent <= '0'; WHEN "0001010110" => manhi <= conv_std_logic_vector(1469883,24); manlo <= conv_std_logic_vector(205651209,28); exponent <= '0'; WHEN "0001010111" => manhi <= conv_std_logic_vector(1487711,24); manlo <= conv_std_logic_vector(242451980,28); exponent <= '0'; WHEN "0001011000" => manhi <= conv_std_logic_vector(1505557,24); manlo <= conv_std_logic_vector(123236457,28); exponent <= '0'; WHEN "0001011001" => manhi <= conv_std_logic_vector(1523420,24); manlo <= conv_std_logic_vector(121008560,28); exponent <= '0'; WHEN "0001011010" => manhi <= conv_std_logic_vector(1541300,24); manlo <= conv_std_logic_vector(240341215,28); exponent <= '0'; WHEN "0001011011" => manhi <= conv_std_logic_vector(1559198,24); manlo <= conv_std_logic_vector(217376360,28); exponent <= '0'; WHEN "0001011100" => manhi <= conv_std_logic_vector(1577114,24); manlo <= conv_std_logic_vector(56695861,28); exponent <= '0'; WHEN "0001011101" => manhi <= conv_std_logic_vector(1595047,24); manlo <= conv_std_logic_vector(31321518,28); exponent <= '0'; WHEN "0001011110" => manhi <= conv_std_logic_vector(1612997,24); manlo <= conv_std_logic_vector(145844154,28); exponent <= '0'; WHEN "0001011111" => manhi <= conv_std_logic_vector(1630965,24); manlo <= conv_std_logic_vector(136423623,28); exponent <= '0'; WHEN "0001100000" => manhi <= conv_std_logic_vector(1648951,24); manlo <= conv_std_logic_vector(7659725,28); exponent <= '0'; WHEN "0001100001" => manhi <= conv_std_logic_vector(1666954,24); manlo <= conv_std_logic_vector(32592210,28); exponent <= '0'; WHEN "0001100010" => manhi <= conv_std_logic_vector(1684974,24); manlo <= conv_std_logic_vector(215829868,28); exponent <= '0'; WHEN "0001100011" => manhi <= conv_std_logic_vector(1703013,24); manlo <= conv_std_logic_vector(25115084,28); exponent <= '0'; WHEN "0001100100" => manhi <= conv_std_logic_vector(1721069,24); manlo <= conv_std_logic_vector(1936572,28); exponent <= '0'; WHEN "0001100101" => manhi <= conv_std_logic_vector(1739142,24); manlo <= conv_std_logic_vector(150916647,28); exponent <= '0'; WHEN "0001100110" => manhi <= conv_std_logic_vector(1757233,24); manlo <= conv_std_logic_vector(208246681,28); exponent <= '0'; WHEN "0001100111" => manhi <= conv_std_logic_vector(1775342,24); manlo <= conv_std_logic_vector(178558028,28); exponent <= '0'; WHEN "0001101000" => manhi <= conv_std_logic_vector(1793469,24); manlo <= conv_std_logic_vector(66486562,28); exponent <= '0'; WHEN "0001101001" => manhi <= conv_std_logic_vector(1811613,24); manlo <= conv_std_logic_vector(145108146,28); exponent <= '0'; WHEN "0001101010" => manhi <= conv_std_logic_vector(1829775,24); manlo <= conv_std_logic_vector(150632262,28); exponent <= '0'; WHEN "0001101011" => manhi <= conv_std_logic_vector(1847955,24); manlo <= conv_std_logic_vector(87708388,28); exponent <= '0'; WHEN "0001101100" => manhi <= conv_std_logic_vector(1866152,24); manlo <= conv_std_logic_vector(229426001,28); exponent <= '0'; WHEN "0001101101" => manhi <= conv_std_logic_vector(1884368,24); manlo <= conv_std_logic_vector(43572756,28); exponent <= '0'; WHEN "0001101110" => manhi <= conv_std_logic_vector(1902601,24); manlo <= conv_std_logic_vector(71682684,28); exponent <= '0'; WHEN "0001101111" => manhi <= conv_std_logic_vector(1920852,24); manlo <= conv_std_logic_vector(49988005,28); exponent <= '0'; WHEN "0001110000" => manhi <= conv_std_logic_vector(1939120,24); manlo <= conv_std_logic_vector(251596409,28); exponent <= '0'; WHEN "0001110001" => manhi <= conv_std_logic_vector(1957407,24); manlo <= conv_std_logic_vector(144313787,28); exponent <= '0'; WHEN "0001110010" => manhi <= conv_std_logic_vector(1975712,24); manlo <= conv_std_logic_vector(1256963,28); exponent <= '0'; WHEN "0001110011" => manhi <= conv_std_logic_vector(1994034,24); manlo <= conv_std_logic_vector(95547338,28); exponent <= '0'; WHEN "0001110100" => manhi <= conv_std_logic_vector(2012374,24); manlo <= conv_std_logic_vector(163439978,28); exponent <= '0'; WHEN "0001110101" => manhi <= conv_std_logic_vector(2030732,24); manlo <= conv_std_logic_vector(209629988,28); exponent <= '0'; WHEN "0001110110" => manhi <= conv_std_logic_vector(2049108,24); manlo <= conv_std_logic_vector(238817060,28); exponent <= '0'; WHEN "0001110111" => manhi <= conv_std_logic_vector(2067502,24); manlo <= conv_std_logic_vector(255705480,28); exponent <= '0'; WHEN "0001111000" => manhi <= conv_std_logic_vector(2085914,24); manlo <= conv_std_logic_vector(265004126,28); exponent <= '0'; WHEN "0001111001" => manhi <= conv_std_logic_vector(2104345,24); manlo <= conv_std_logic_vector(2991026,28); exponent <= '0'; WHEN "0001111010" => manhi <= conv_std_logic_vector(2122793,24); manlo <= conv_std_logic_vector(11255176,28); exponent <= '0'; WHEN "0001111011" => manhi <= conv_std_logic_vector(2141259,24); manlo <= conv_std_logic_vector(26083817,28); exponent <= '0'; WHEN "0001111100" => manhi <= conv_std_logic_vector(2159743,24); manlo <= conv_std_logic_vector(52204260,28); exponent <= '0'; WHEN "0001111101" => manhi <= conv_std_logic_vector(2178245,24); manlo <= conv_std_logic_vector(94348435,28); exponent <= '0'; WHEN "0001111110" => manhi <= conv_std_logic_vector(2196765,24); manlo <= conv_std_logic_vector(157252892,28); exponent <= '0'; WHEN "0001111111" => manhi <= conv_std_logic_vector(2215303,24); manlo <= conv_std_logic_vector(245658814,28); exponent <= '0'; WHEN "0010000000" => manhi <= conv_std_logic_vector(2233860,24); manlo <= conv_std_logic_vector(95876557,28); exponent <= '0'; WHEN "0010000001" => manhi <= conv_std_logic_vector(2252434,24); manlo <= conv_std_logic_vector(249527482,28); exponent <= '0'; WHEN "0010000010" => manhi <= conv_std_logic_vector(2271027,24); manlo <= conv_std_logic_vector(174495768,28); exponent <= '0'; WHEN "0010000011" => manhi <= conv_std_logic_vector(2289638,24); manlo <= conv_std_logic_vector(143976608,28); exponent <= '0'; WHEN "0010000100" => manhi <= conv_std_logic_vector(2308267,24); manlo <= conv_std_logic_vector(162734389,28); exponent <= '0'; WHEN "0010000101" => manhi <= conv_std_logic_vector(2326914,24); manlo <= conv_std_logic_vector(235538153,28); exponent <= '0'; WHEN "0010000110" => manhi <= conv_std_logic_vector(2345580,24); manlo <= conv_std_logic_vector(98726147,28); exponent <= '0'; WHEN "0010000111" => manhi <= conv_std_logic_vector(2364264,24); manlo <= conv_std_logic_vector(25512192,28); exponent <= '0'; WHEN "0010001000" => manhi <= conv_std_logic_vector(2382966,24); manlo <= conv_std_logic_vector(20679323,28); exponent <= '0'; WHEN "0010001001" => manhi <= conv_std_logic_vector(2401686,24); manlo <= conv_std_logic_vector(89015247,28); exponent <= '0'; WHEN "0010001010" => manhi <= conv_std_logic_vector(2420424,24); manlo <= conv_std_logic_vector(235312351,28); exponent <= '0'; WHEN "0010001011" => manhi <= conv_std_logic_vector(2439181,24); manlo <= conv_std_logic_vector(195932245,28); exponent <= '0'; WHEN "0010001100" => manhi <= conv_std_logic_vector(2457956,24); manlo <= conv_std_logic_vector(244112142,28); exponent <= '0'; WHEN "0010001101" => manhi <= conv_std_logic_vector(2476750,24); manlo <= conv_std_logic_vector(116223030,28); exponent <= '0'; WHEN "0010001110" => manhi <= conv_std_logic_vector(2495562,24); manlo <= conv_std_logic_vector(85511509,28); exponent <= '0'; WHEN "0010001111" => manhi <= conv_std_logic_vector(2514392,24); manlo <= conv_std_logic_vector(156793422,28); exponent <= '0'; WHEN "0010010000" => manhi <= conv_std_logic_vector(2533241,24); manlo <= conv_std_logic_vector(66453860,28); exponent <= '0'; WHEN "0010010001" => manhi <= conv_std_logic_vector(2552108,24); manlo <= conv_std_logic_vector(87753539,28); exponent <= '0'; WHEN "0010010010" => manhi <= conv_std_logic_vector(2570993,24); manlo <= conv_std_logic_vector(225522431,28); exponent <= '0'; WHEN "0010010011" => manhi <= conv_std_logic_vector(2589897,24); manlo <= conv_std_logic_vector(216159772,28); exponent <= '0'; WHEN "0010010100" => manhi <= conv_std_logic_vector(2608820,24); manlo <= conv_std_logic_vector(64504976,28); exponent <= '0'; WHEN "0010010101" => manhi <= conv_std_logic_vector(2627761,24); manlo <= conv_std_logic_vector(43837645,28); exponent <= '0'; WHEN "0010010110" => manhi <= conv_std_logic_vector(2646720,24); manlo <= conv_std_logic_vector(159006654,28); exponent <= '0'; WHEN "0010010111" => manhi <= conv_std_logic_vector(2665698,24); manlo <= conv_std_logic_vector(146430162,28); exponent <= '0'; WHEN "0010011000" => manhi <= conv_std_logic_vector(2684695,24); manlo <= conv_std_logic_vector(10966526,28); exponent <= '0'; WHEN "0010011001" => manhi <= conv_std_logic_vector(2703710,24); manlo <= conv_std_logic_vector(25914303,28); exponent <= '0'; WHEN "0010011010" => manhi <= conv_std_logic_vector(2722743,24); manlo <= conv_std_logic_vector(196141350,28); exponent <= '0'; WHEN "0010011011" => manhi <= conv_std_logic_vector(2741795,24); manlo <= conv_std_logic_vector(258084820,28); exponent <= '0'; WHEN "0010011100" => manhi <= conv_std_logic_vector(2760866,24); manlo <= conv_std_logic_vector(216622086,28); exponent <= '0'; WHEN "0010011101" => manhi <= conv_std_logic_vector(2779956,24); manlo <= conv_std_logic_vector(76635284,28); exponent <= '0'; WHEN "0010011110" => manhi <= conv_std_logic_vector(2799064,24); manlo <= conv_std_logic_vector(111446777,28); exponent <= '0'; WHEN "0010011111" => manhi <= conv_std_logic_vector(2818191,24); manlo <= conv_std_logic_vector(57512790,28); exponent <= '0'; WHEN "0010100000" => manhi <= conv_std_logic_vector(2837336,24); manlo <= conv_std_logic_vector(188165241,28); exponent <= '0'; WHEN "0010100001" => manhi <= conv_std_logic_vector(2856500,24); manlo <= conv_std_logic_vector(239869919,28); exponent <= '0'; WHEN "0010100010" => manhi <= conv_std_logic_vector(2875683,24); manlo <= conv_std_logic_vector(217532856,28); exponent <= '0'; WHEN "0010100011" => manhi <= conv_std_logic_vector(2894885,24); manlo <= conv_std_logic_vector(126064881,28); exponent <= '0'; WHEN "0010100100" => manhi <= conv_std_logic_vector(2914105,24); manlo <= conv_std_logic_vector(238817075,28); exponent <= '0'; WHEN "0010100101" => manhi <= conv_std_logic_vector(2933345,24); manlo <= conv_std_logic_vector(23838952,28); exponent <= '0'; WHEN "0010100110" => manhi <= conv_std_logic_vector(2952603,24); manlo <= conv_std_logic_vector(22926662,28); exponent <= '0'; WHEN "0010100111" => manhi <= conv_std_logic_vector(2971879,24); manlo <= conv_std_logic_vector(241010251,28); exponent <= '0'; WHEN "0010101000" => manhi <= conv_std_logic_vector(2991175,24); manlo <= conv_std_logic_vector(146153671,28); exponent <= '0'; WHEN "0010101001" => manhi <= conv_std_logic_vector(3010490,24); manlo <= conv_std_logic_vector(11732065,28); exponent <= '0'; WHEN "0010101010" => manhi <= conv_std_logic_vector(3029823,24); manlo <= conv_std_logic_vector(111125401,28); exponent <= '0'; WHEN "0010101011" => manhi <= conv_std_logic_vector(3049175,24); manlo <= conv_std_logic_vector(180847566,28); exponent <= '0'; WHEN "0010101100" => manhi <= conv_std_logic_vector(3068546,24); manlo <= conv_std_logic_vector(225852738,28); exponent <= '0'; WHEN "0010101101" => manhi <= conv_std_logic_vector(3087936,24); manlo <= conv_std_logic_vector(251099938,28); exponent <= '0'; WHEN "0010101110" => manhi <= conv_std_logic_vector(3107345,24); manlo <= conv_std_logic_vector(261553029,28); exponent <= '0'; WHEN "0010101111" => manhi <= conv_std_logic_vector(3126773,24); manlo <= conv_std_logic_vector(262180727,28); exponent <= '0'; WHEN "0010110000" => manhi <= conv_std_logic_vector(3146220,24); manlo <= conv_std_logic_vector(257956599,28); exponent <= '0'; WHEN "0010110001" => manhi <= conv_std_logic_vector(3165686,24); manlo <= conv_std_logic_vector(253859075,28); exponent <= '0'; WHEN "0010110010" => manhi <= conv_std_logic_vector(3185171,24); manlo <= conv_std_logic_vector(254871446,28); exponent <= '0'; WHEN "0010110011" => manhi <= conv_std_logic_vector(3204675,24); manlo <= conv_std_logic_vector(265981875,28); exponent <= '0'; WHEN "0010110100" => manhi <= conv_std_logic_vector(3224199,24); manlo <= conv_std_logic_vector(23747940,28); exponent <= '0'; WHEN "0010110101" => manhi <= conv_std_logic_vector(3243741,24); manlo <= conv_std_logic_vector(70038466,28); exponent <= '0'; WHEN "0010110110" => manhi <= conv_std_logic_vector(3263302,24); manlo <= conv_std_logic_vector(141420795,28); exponent <= '0'; WHEN "0010110111" => manhi <= conv_std_logic_vector(3282882,24); manlo <= conv_std_logic_vector(242902610,28); exponent <= '0'; WHEN "0010111000" => manhi <= conv_std_logic_vector(3302482,24); manlo <= conv_std_logic_vector(111061033,28); exponent <= '0'; WHEN "0010111001" => manhi <= conv_std_logic_vector(3322101,24); manlo <= conv_std_logic_vector(19348994,28); exponent <= '0'; WHEN "0010111010" => manhi <= conv_std_logic_vector(3341738,24); manlo <= conv_std_logic_vector(241224327,28); exponent <= '0'; WHEN "0010111011" => manhi <= conv_std_logic_vector(3361395,24); manlo <= conv_std_logic_vector(244843403,28); exponent <= '0'; WHEN "0010111100" => manhi <= conv_std_logic_vector(3381072,24); manlo <= conv_std_logic_vector(35238419,28); exponent <= '0'; WHEN "0010111101" => manhi <= conv_std_logic_vector(3400767,24); manlo <= conv_std_logic_vector(154317398,28); exponent <= '0'; WHEN "0010111110" => manhi <= conv_std_logic_vector(3420482,24); manlo <= conv_std_logic_vector(70251462,28); exponent <= '0'; WHEN "0010111111" => manhi <= conv_std_logic_vector(3440216,24); manlo <= conv_std_logic_vector(56523029,28); exponent <= '0'; WHEN "0011000000" => manhi <= conv_std_logic_vector(3459969,24); manlo <= conv_std_logic_vector(118183989,28); exponent <= '0'; WHEN "0011000001" => manhi <= conv_std_logic_vector(3479741,24); manlo <= conv_std_logic_vector(260291170,28); exponent <= '0'; WHEN "0011000010" => manhi <= conv_std_logic_vector(3499533,24); manlo <= conv_std_logic_vector(219470882,28); exponent <= '0'; WHEN "0011000011" => manhi <= conv_std_logic_vector(3519345,24); manlo <= conv_std_logic_vector(789841,28); exponent <= '0'; WHEN "0011000100" => manhi <= conv_std_logic_vector(3539175,24); manlo <= conv_std_logic_vector(146190621,28); exponent <= '0'; WHEN "0011000101" => manhi <= conv_std_logic_vector(3559025,24); manlo <= conv_std_logic_vector(123878930,28); exponent <= '0'; WHEN "0011000110" => manhi <= conv_std_logic_vector(3578894,24); manlo <= conv_std_logic_vector(207371803,28); exponent <= '0'; WHEN "0011000111" => manhi <= conv_std_logic_vector(3598783,24); manlo <= conv_std_logic_vector(133320328,28); exponent <= '0'; WHEN "0011001000" => manhi <= conv_std_logic_vector(3618691,24); manlo <= conv_std_logic_vector(175251474,28); exponent <= '0'; WHEN "0011001001" => manhi <= conv_std_logic_vector(3638619,24); manlo <= conv_std_logic_vector(69826275,28); exponent <= '0'; WHEN "0011001010" => manhi <= conv_std_logic_vector(3658566,24); manlo <= conv_std_logic_vector(90581653,28); exponent <= '0'; WHEN "0011001011" => manhi <= conv_std_logic_vector(3678532,24); manlo <= conv_std_logic_vector(242624062,28); exponent <= '0'; WHEN "0011001100" => manhi <= conv_std_logic_vector(3698518,24); manlo <= conv_std_logic_vector(262629486,28); exponent <= '0'; WHEN "0011001101" => manhi <= conv_std_logic_vector(3718524,24); manlo <= conv_std_logic_vector(155714362,28); exponent <= '0'; WHEN "0011001110" => manhi <= conv_std_logic_vector(3738549,24); manlo <= conv_std_logic_vector(195435578,28); exponent <= '0'; WHEN "0011001111" => manhi <= conv_std_logic_vector(3758594,24); manlo <= conv_std_logic_vector(118484119,28); exponent <= '0'; WHEN "0011010000" => manhi <= conv_std_logic_vector(3778658,24); manlo <= conv_std_logic_vector(198426886,28); exponent <= '0'; WHEN "0011010001" => manhi <= conv_std_logic_vector(3798742,24); manlo <= conv_std_logic_vector(171964885,28); exponent <= '0'; WHEN "0011010010" => manhi <= conv_std_logic_vector(3818846,24); manlo <= conv_std_logic_vector(44239595,28); exponent <= '0'; WHEN "0011010011" => manhi <= conv_std_logic_vector(3838969,24); manlo <= conv_std_logic_vector(88832973,28); exponent <= '0'; WHEN "0011010100" => manhi <= conv_std_logic_vector(3859112,24); manlo <= conv_std_logic_vector(42461096,28); exponent <= '0'; WHEN "0011010101" => manhi <= conv_std_logic_vector(3879274,24); manlo <= conv_std_logic_vector(178715983,28); exponent <= '0'; WHEN "0011010110" => manhi <= conv_std_logic_vector(3899456,24); manlo <= conv_std_logic_vector(234323781,28); exponent <= '0'; WHEN "0011010111" => manhi <= conv_std_logic_vector(3919658,24); manlo <= conv_std_logic_vector(214451135,28); exponent <= '0'; WHEN "0011011000" => manhi <= conv_std_logic_vector(3939880,24); manlo <= conv_std_logic_vector(124269738,28); exponent <= '0'; WHEN "0011011001" => manhi <= conv_std_logic_vector(3960121,24); manlo <= conv_std_logic_vector(237391794,28); exponent <= '0'; WHEN "0011011010" => manhi <= conv_std_logic_vector(3980383,24); manlo <= conv_std_logic_vector(22128194,28); exponent <= '0'; WHEN "0011011011" => manhi <= conv_std_logic_vector(4000664,24); manlo <= conv_std_logic_vector(20536717,28); exponent <= '0'; WHEN "0011011100" => manhi <= conv_std_logic_vector(4020964,24); manlo <= conv_std_logic_vector(237809299,28); exponent <= '0'; WHEN "0011011101" => manhi <= conv_std_logic_vector(4041285,24); manlo <= conv_std_logic_vector(142272034,28); exponent <= '0'; WHEN "0011011110" => manhi <= conv_std_logic_vector(4061626,24); manlo <= conv_std_logic_vector(7562465,28); exponent <= '0'; WHEN "0011011111" => manhi <= conv_std_logic_vector(4081986,24); manlo <= conv_std_logic_vector(107323215,28); exponent <= '0'; WHEN "0011100000" => manhi <= conv_std_logic_vector(4102366,24); manlo <= conv_std_logic_vector(178331084,28); exponent <= '0'; WHEN "0011100001" => manhi <= conv_std_logic_vector(4122766,24); manlo <= conv_std_logic_vector(225803419,28); exponent <= '0'; WHEN "0011100010" => manhi <= conv_std_logic_vector(4143186,24); manlo <= conv_std_logic_vector(254962667,28); exponent <= '0'; WHEN "0011100011" => manhi <= conv_std_logic_vector(4163627,24); manlo <= conv_std_logic_vector(2600920,28); exponent <= '0'; WHEN "0011100100" => manhi <= conv_std_logic_vector(4184087,24); manlo <= conv_std_logic_vector(10821746,28); exponent <= '0'; WHEN "0011100101" => manhi <= conv_std_logic_vector(4204567,24); manlo <= conv_std_logic_vector(16427456,28); exponent <= '0'; WHEN "0011100110" => manhi <= conv_std_logic_vector(4225067,24); manlo <= conv_std_logic_vector(24660936,28); exponent <= '0'; WHEN "0011100111" => manhi <= conv_std_logic_vector(4245587,24); manlo <= conv_std_logic_vector(40770196,28); exponent <= '0'; WHEN "0011101000" => manhi <= conv_std_logic_vector(4266127,24); manlo <= conv_std_logic_vector(70008370,28); exponent <= '0'; WHEN "0011101001" => manhi <= conv_std_logic_vector(4286687,24); manlo <= conv_std_logic_vector(117633727,28); exponent <= '0'; WHEN "0011101010" => manhi <= conv_std_logic_vector(4307267,24); manlo <= conv_std_logic_vector(188909673,28); exponent <= '0'; WHEN "0011101011" => manhi <= conv_std_logic_vector(4327868,24); manlo <= conv_std_logic_vector(20669300,28); exponent <= '0'; WHEN "0011101100" => manhi <= conv_std_logic_vector(4348488,24); manlo <= conv_std_logic_vector(155057216,28); exponent <= '0'; WHEN "0011101101" => manhi <= conv_std_logic_vector(4369129,24); manlo <= conv_std_logic_vector(60481357,28); exponent <= '0'; WHEN "0011101110" => manhi <= conv_std_logic_vector(4389790,24); manlo <= conv_std_logic_vector(10661187,28); exponent <= '0'; WHEN "0011101111" => manhi <= conv_std_logic_vector(4410471,24); manlo <= conv_std_logic_vector(10885873,28); exponent <= '0'; WHEN "0011110000" => manhi <= conv_std_logic_vector(4431172,24); manlo <= conv_std_logic_vector(66449753,28); exponent <= '0'; WHEN "0011110001" => manhi <= conv_std_logic_vector(4451893,24); manlo <= conv_std_logic_vector(182652336,28); exponent <= '0'; WHEN "0011110010" => manhi <= conv_std_logic_vector(4472635,24); manlo <= conv_std_logic_vector(96362852,28); exponent <= '0'; WHEN "0011110011" => manhi <= conv_std_logic_vector(4493397,24); manlo <= conv_std_logic_vector(81326629,28); exponent <= '0'; WHEN "0011110100" => manhi <= conv_std_logic_vector(4514179,24); manlo <= conv_std_logic_vector(142858724,28); exponent <= '0'; WHEN "0011110101" => manhi <= conv_std_logic_vector(4534982,24); manlo <= conv_std_logic_vector(17843933,28); exponent <= '0'; WHEN "0011110110" => manhi <= conv_std_logic_vector(4555804,24); manlo <= conv_std_logic_vector(248478616,28); exponent <= '0'; WHEN "0011110111" => manhi <= conv_std_logic_vector(4576648,24); manlo <= conv_std_logic_vector(34787059,28); exponent <= '0'; WHEN "0011111000" => manhi <= conv_std_logic_vector(4597511,24); manlo <= conv_std_logic_vector(187411489,28); exponent <= '0'; WHEN "0011111001" => manhi <= conv_std_logic_vector(4618395,24); manlo <= conv_std_logic_vector(174822068,28); exponent <= '0'; WHEN "0011111010" => manhi <= conv_std_logic_vector(4639300,24); manlo <= conv_std_logic_vector(2365090,28); exponent <= '0'; WHEN "0011111011" => manhi <= conv_std_logic_vector(4660224,24); manlo <= conv_std_logic_vector(212262982,28); exponent <= '0'; WHEN "0011111100" => manhi <= conv_std_logic_vector(4681170,24); manlo <= conv_std_logic_vector(4566120,28); exponent <= '0'; WHEN "0011111101" => manhi <= conv_std_logic_vector(4702135,24); manlo <= conv_std_logic_vector(189942850,28); exponent <= '0'; WHEN "0011111110" => manhi <= conv_std_logic_vector(4723121,24); manlo <= conv_std_logic_vector(236889480,28); exponent <= '0'; WHEN "0011111111" => manhi <= conv_std_logic_vector(4744128,24); manlo <= conv_std_logic_vector(150778468,28); exponent <= '0'; WHEN "0100000000" => manhi <= conv_std_logic_vector(4765155,24); manlo <= conv_std_logic_vector(205422982,28); exponent <= '0'; WHEN "0100000001" => manhi <= conv_std_logic_vector(4786203,24); manlo <= conv_std_logic_vector(137770531,28); exponent <= '0'; WHEN "0100000010" => manhi <= conv_std_logic_vector(4807271,24); manlo <= conv_std_logic_vector(221644793,28); exponent <= '0'; WHEN "0100000011" => manhi <= conv_std_logic_vector(4828360,24); manlo <= conv_std_logic_vector(194003802,28); exponent <= '0'; WHEN "0100000100" => manhi <= conv_std_logic_vector(4849470,24); manlo <= conv_std_logic_vector(60246316,28); exponent <= '0'; WHEN "0100000101" => manhi <= conv_std_logic_vector(4870600,24); manlo <= conv_std_logic_vector(94211823,28); exponent <= '0'; WHEN "0100000110" => manhi <= conv_std_logic_vector(4891751,24); manlo <= conv_std_logic_vector(32874180,28); exponent <= '0'; WHEN "0100000111" => manhi <= conv_std_logic_vector(4912922,24); manlo <= conv_std_logic_vector(150083442,28); exponent <= '0'; WHEN "0100001000" => manhi <= conv_std_logic_vector(4934114,24); manlo <= conv_std_logic_vector(182824039,28); exponent <= '0'; WHEN "0100001001" => manhi <= conv_std_logic_vector(4955327,24); manlo <= conv_std_logic_vector(136521157,28); exponent <= '0'; WHEN "0100001010" => manhi <= conv_std_logic_vector(4976561,24); manlo <= conv_std_logic_vector(16605280,28); exponent <= '0'; WHEN "0100001011" => manhi <= conv_std_logic_vector(4997815,24); manlo <= conv_std_logic_vector(96947652,28); exponent <= '0'; WHEN "0100001100" => manhi <= conv_std_logic_vector(5019090,24); manlo <= conv_std_logic_vector(114553920,28); exponent <= '0'; WHEN "0100001101" => manhi <= conv_std_logic_vector(5040386,24); manlo <= conv_std_logic_vector(74870501,28); exponent <= '0'; WHEN "0100001110" => manhi <= conv_std_logic_vector(5061702,24); manlo <= conv_std_logic_vector(251784590,28); exponent <= '0'; WHEN "0100001111" => manhi <= conv_std_logic_vector(5083040,24); manlo <= conv_std_logic_vector(113882338,28); exponent <= '0'; WHEN "0100010000" => manhi <= conv_std_logic_vector(5104398,24); manlo <= conv_std_logic_vector(203497056,28); exponent <= '0'; WHEN "0100010001" => manhi <= conv_std_logic_vector(5125777,24); manlo <= conv_std_logic_vector(257661021,28); exponent <= '0'; WHEN "0100010010" => manhi <= conv_std_logic_vector(5147178,24); manlo <= conv_std_logic_vector(13411854,28); exponent <= '0'; WHEN "0100010011" => manhi <= conv_std_logic_vector(5168599,24); manlo <= conv_std_logic_vector(13098889,28); exponent <= '0'; WHEN "0100010100" => manhi <= conv_std_logic_vector(5190040,24); manlo <= conv_std_logic_vector(262205904,28); exponent <= '0'; WHEN "0100010101" => manhi <= conv_std_logic_vector(5211503,24); manlo <= conv_std_logic_vector(229351119,28); exponent <= '0'; WHEN "0100010110" => manhi <= conv_std_logic_vector(5232987,24); manlo <= conv_std_logic_vector(188464488,28); exponent <= '0'; WHEN "0100010111" => manhi <= conv_std_logic_vector(5254492,24); manlo <= conv_std_logic_vector(145045878,28); exponent <= '0'; WHEN "0100011000" => manhi <= conv_std_logic_vector(5276018,24); manlo <= conv_std_logic_vector(104600525,28); exponent <= '0'; WHEN "0100011001" => manhi <= conv_std_logic_vector(5297565,24); manlo <= conv_std_logic_vector(72639049,28); exponent <= '0'; WHEN "0100011010" => manhi <= conv_std_logic_vector(5319133,24); manlo <= conv_std_logic_vector(54677451,28); exponent <= '0'; WHEN "0100011011" => manhi <= conv_std_logic_vector(5340722,24); manlo <= conv_std_logic_vector(56237123,28); exponent <= '0'; WHEN "0100011100" => manhi <= conv_std_logic_vector(5362332,24); manlo <= conv_std_logic_vector(82844851,28); exponent <= '0'; WHEN "0100011101" => manhi <= conv_std_logic_vector(5383963,24); manlo <= conv_std_logic_vector(140032820,28); exponent <= '0'; WHEN "0100011110" => manhi <= conv_std_logic_vector(5405615,24); manlo <= conv_std_logic_vector(233338622,28); exponent <= '0'; WHEN "0100011111" => manhi <= conv_std_logic_vector(5427289,24); manlo <= conv_std_logic_vector(99869801,28); exponent <= '0'; WHEN "0100100000" => manhi <= conv_std_logic_vector(5448984,24); manlo <= conv_std_logic_vector(13610232,28); exponent <= '0'; WHEN "0100100001" => manhi <= conv_std_logic_vector(5470699,24); manlo <= conv_std_logic_vector(248549207,28); exponent <= '0'; WHEN "0100100010" => manhi <= conv_std_logic_vector(5492437,24); manlo <= conv_std_logic_vector(4939624,28); exponent <= '0'; WHEN "0100100011" => manhi <= conv_std_logic_vector(5514195,24); manlo <= conv_std_logic_vector(93652547,28); exponent <= '0'; WHEN "0100100100" => manhi <= conv_std_logic_vector(5535974,24); manlo <= conv_std_logic_vector(251822653,28); exponent <= '0'; WHEN "0100100101" => manhi <= conv_std_logic_vector(5557775,24); manlo <= conv_std_logic_vector(216590061,28); exponent <= '0'; WHEN "0100100110" => manhi <= conv_std_logic_vector(5579597,24); manlo <= conv_std_logic_vector(261971250,28); exponent <= '0'; WHEN "0100100111" => manhi <= conv_std_logic_vector(5601441,24); manlo <= conv_std_logic_vector(125117240,28); exponent <= '0'; WHEN "0100101000" => manhi <= conv_std_logic_vector(5623306,24); manlo <= conv_std_logic_vector(80055420,28); exponent <= '0'; WHEN "0100101001" => manhi <= conv_std_logic_vector(5645192,24); manlo <= conv_std_logic_vector(132383188,28); exponent <= '0'; WHEN "0100101010" => manhi <= conv_std_logic_vector(5667100,24); manlo <= conv_std_logic_vector(19267955,28); exponent <= '0'; WHEN "0100101011" => manhi <= conv_std_logic_vector(5689029,24); manlo <= conv_std_logic_vector(14753516,28); exponent <= '0'; WHEN "0100101100" => manhi <= conv_std_logic_vector(5710979,24); manlo <= conv_std_logic_vector(124453694,28); exponent <= '0'; WHEN "0100101101" => manhi <= conv_std_logic_vector(5732951,24); manlo <= conv_std_logic_vector(85552334,28); exponent <= '0'; WHEN "0100101110" => manhi <= conv_std_logic_vector(5754944,24); manlo <= conv_std_logic_vector(172109691,28); exponent <= '0'; WHEN "0100101111" => manhi <= conv_std_logic_vector(5776959,24); manlo <= conv_std_logic_vector(121320598,28); exponent <= '0'; WHEN "0100110000" => manhi <= conv_std_logic_vector(5798995,24); manlo <= conv_std_logic_vector(207256304,28); exponent <= '0'; WHEN "0100110001" => manhi <= conv_std_logic_vector(5821053,24); manlo <= conv_std_logic_vector(167122651,28); exponent <= '0'; WHEN "0100110010" => manhi <= conv_std_logic_vector(5843133,24); manlo <= conv_std_logic_vector(6566449,28); exponent <= '0'; WHEN "0100110011" => manhi <= conv_std_logic_vector(5865233,24); manlo <= conv_std_logic_vector(268110937,28); exponent <= '0'; WHEN "0100110100" => manhi <= conv_std_logic_vector(5887356,24); manlo <= conv_std_logic_vector(152107598,28); exponent <= '0'; WHEN "0100110101" => manhi <= conv_std_logic_vector(5909500,24); manlo <= conv_std_logic_vector(201090721,28); exponent <= '0'; WHEN "0100110110" => manhi <= conv_std_logic_vector(5931666,24); manlo <= conv_std_logic_vector(152293761,28); exponent <= '0'; WHEN "0100110111" => manhi <= conv_std_logic_vector(5953854,24); manlo <= conv_std_logic_vector(11391168,28); exponent <= '0'; WHEN "0100111000" => manhi <= conv_std_logic_vector(5976063,24); manlo <= conv_std_logic_vector(52498394,28); exponent <= '0'; WHEN "0100111001" => manhi <= conv_std_logic_vector(5998294,24); manlo <= conv_std_logic_vector(12865523,28); exponent <= '0'; WHEN "0100111010" => manhi <= conv_std_logic_vector(6020546,24); manlo <= conv_std_logic_vector(166619112,28); exponent <= '0'; WHEN "0100111011" => manhi <= conv_std_logic_vector(6042820,24); manlo <= conv_std_logic_vector(251020365,28); exponent <= '0'; WHEN "0100111100" => manhi <= conv_std_logic_vector(6065117,24); manlo <= conv_std_logic_vector(3336048,28); exponent <= '0'; WHEN "0100111101" => manhi <= conv_std_logic_vector(6087434,24); manlo <= conv_std_logic_vector(234580328,28); exponent <= '0'; WHEN "0100111110" => manhi <= conv_std_logic_vector(6109774,24); manlo <= conv_std_logic_vector(145160209,28); exponent <= '0'; WHEN "0100111111" => manhi <= conv_std_logic_vector(6132136,24); manlo <= conv_std_logic_vector(9230102,28); exponent <= '0'; WHEN "0101000000" => manhi <= conv_std_logic_vector(6154519,24); manlo <= conv_std_logic_vector(100950005,28); exponent <= '0'; WHEN "0101000001" => manhi <= conv_std_logic_vector(6176924,24); manlo <= conv_std_logic_vector(157614600,28); exponent <= '0'; WHEN "0101000010" => manhi <= conv_std_logic_vector(6199351,24); manlo <= conv_std_logic_vector(184959620,28); exponent <= '0'; WHEN "0101000011" => manhi <= conv_std_logic_vector(6221800,24); manlo <= conv_std_logic_vector(188726403,28); exponent <= '0'; WHEN "0101000100" => manhi <= conv_std_logic_vector(6244271,24); manlo <= conv_std_logic_vector(174661898,28); exponent <= '0'; WHEN "0101000101" => manhi <= conv_std_logic_vector(6266764,24); manlo <= conv_std_logic_vector(148518669,28); exponent <= '0'; WHEN "0101000110" => manhi <= conv_std_logic_vector(6289279,24); manlo <= conv_std_logic_vector(116054898,28); exponent <= '0'; WHEN "0101000111" => manhi <= conv_std_logic_vector(6311816,24); manlo <= conv_std_logic_vector(83034395,28); exponent <= '0'; WHEN "0101001000" => manhi <= conv_std_logic_vector(6334375,24); manlo <= conv_std_logic_vector(55226600,28); exponent <= '0'; WHEN "0101001001" => manhi <= conv_std_logic_vector(6356956,24); manlo <= conv_std_logic_vector(38406593,28); exponent <= '0'; WHEN "0101001010" => manhi <= conv_std_logic_vector(6379559,24); manlo <= conv_std_logic_vector(38355093,28); exponent <= '0'; WHEN "0101001011" => manhi <= conv_std_logic_vector(6402184,24); manlo <= conv_std_logic_vector(60858469,28); exponent <= '0'; WHEN "0101001100" => manhi <= conv_std_logic_vector(6424831,24); manlo <= conv_std_logic_vector(111708742,28); exponent <= '0'; WHEN "0101001101" => manhi <= conv_std_logic_vector(6447500,24); manlo <= conv_std_logic_vector(196703594,28); exponent <= '0'; WHEN "0101001110" => manhi <= conv_std_logic_vector(6470192,24); manlo <= conv_std_logic_vector(53210914,28); exponent <= '0'; WHEN "0101001111" => manhi <= conv_std_logic_vector(6492905,24); manlo <= conv_std_logic_vector(223910630,28); exponent <= '0'; WHEN "0101010000" => manhi <= conv_std_logic_vector(6515641,24); manlo <= conv_std_logic_vector(177746520,28); exponent <= '0'; WHEN "0101010001" => manhi <= conv_std_logic_vector(6538399,24); manlo <= conv_std_logic_vector(188974414,28); exponent <= '0'; WHEN "0101010010" => manhi <= conv_std_logic_vector(6561179,24); manlo <= conv_std_logic_vector(263420371,28); exponent <= '0'; WHEN "0101010011" => manhi <= conv_std_logic_vector(6583982,24); manlo <= conv_std_logic_vector(138480686,28); exponent <= '0'; WHEN "0101010100" => manhi <= conv_std_logic_vector(6606807,24); manlo <= conv_std_logic_vector(88428264,28); exponent <= '0'; WHEN "0101010101" => manhi <= conv_std_logic_vector(6629654,24); manlo <= conv_std_logic_vector(119106258,28); exponent <= '0'; WHEN "0101010110" => manhi <= conv_std_logic_vector(6652523,24); manlo <= conv_std_logic_vector(236363530,28); exponent <= '0'; WHEN "0101010111" => manhi <= conv_std_logic_vector(6675415,24); manlo <= conv_std_logic_vector(177619200,28); exponent <= '0'; WHEN "0101011000" => manhi <= conv_std_logic_vector(6698329,24); manlo <= conv_std_logic_vector(217169020,28); exponent <= '0'; WHEN "0101011001" => manhi <= conv_std_logic_vector(6721266,24); manlo <= conv_std_logic_vector(92443558,28); exponent <= '0'; WHEN "0101011010" => manhi <= conv_std_logic_vector(6744225,24); manlo <= conv_std_logic_vector(77750021,28); exponent <= '0'; WHEN "0101011011" => manhi <= conv_std_logic_vector(6767206,24); manlo <= conv_std_logic_vector(178965902,28); exponent <= '0'; WHEN "0101011100" => manhi <= conv_std_logic_vector(6790210,24); manlo <= conv_std_logic_vector(133538975,28); exponent <= '0'; WHEN "0101011101" => manhi <= conv_std_logic_vector(6813236,24); manlo <= conv_std_logic_vector(215793680,28); exponent <= '0'; WHEN "0101011110" => manhi <= conv_std_logic_vector(6836285,24); manlo <= conv_std_logic_vector(163189294,28); exponent <= '0'; WHEN "0101011111" => manhi <= conv_std_logic_vector(6859356,24); manlo <= conv_std_logic_vector(250061769,28); exponent <= '0'; WHEN "0101100000" => manhi <= conv_std_logic_vector(6882450,24); manlo <= conv_std_logic_vector(213881907,28); exponent <= '0'; WHEN "0101100001" => manhi <= conv_std_logic_vector(6905567,24); manlo <= conv_std_logic_vector(60561738,28); exponent <= '0'; WHEN "0101100010" => manhi <= conv_std_logic_vector(6928706,24); manlo <= conv_std_logic_vector(64454525,28); exponent <= '0'; WHEN "0101100011" => manhi <= conv_std_logic_vector(6951867,24); manlo <= conv_std_logic_vector(231483856,28); exponent <= '0'; WHEN "0101100100" => manhi <= conv_std_logic_vector(6975052,24); manlo <= conv_std_logic_vector(30708194,28); exponent <= '0'; WHEN "0101100101" => manhi <= conv_std_logic_vector(6998259,24); manlo <= conv_std_logic_vector(4933620,28); exponent <= '0'; WHEN "0101100110" => manhi <= conv_std_logic_vector(7021488,24); manlo <= conv_std_logic_vector(160101103,28); exponent <= '0'; WHEN "0101100111" => manhi <= conv_std_logic_vector(7044740,24); manlo <= conv_std_logic_vector(233721959,28); exponent <= '0'; WHEN "0101101000" => manhi <= conv_std_logic_vector(7068015,24); manlo <= conv_std_logic_vector(231748770,28); exponent <= '0'; WHEN "0101101001" => manhi <= conv_std_logic_vector(7091313,24); manlo <= conv_std_logic_vector(160139936,28); exponent <= '0'; WHEN "0101101010" => manhi <= conv_std_logic_vector(7114634,24); manlo <= conv_std_logic_vector(24859676,28); exponent <= '0'; WHEN "0101101011" => manhi <= conv_std_logic_vector(7137977,24); manlo <= conv_std_logic_vector(100313494,28); exponent <= '0'; WHEN "0101101100" => manhi <= conv_std_logic_vector(7161343,24); manlo <= conv_std_logic_vector(124041814,28); exponent <= '0'; WHEN "0101101101" => manhi <= conv_std_logic_vector(7184732,24); manlo <= conv_std_logic_vector(102026355,28); exponent <= '0'; WHEN "0101101110" => manhi <= conv_std_logic_vector(7208144,24); manlo <= conv_std_logic_vector(40254681,28); exponent <= '0'; WHEN "0101101111" => manhi <= conv_std_logic_vector(7231578,24); manlo <= conv_std_logic_vector(213155662,28); exponent <= '0'; WHEN "0101110000" => manhi <= conv_std_logic_vector(7255036,24); manlo <= conv_std_logic_vector(89857654,28); exponent <= '0'; WHEN "0101110001" => manhi <= conv_std_logic_vector(7278516,24); manlo <= conv_std_logic_vector(213236700,28); exponent <= '0'; WHEN "0101110010" => manhi <= conv_std_logic_vector(7302020,24); manlo <= conv_std_logic_vector(52432888,28); exponent <= '0'; WHEN "0101110011" => manhi <= conv_std_logic_vector(7325546,24); manlo <= conv_std_logic_vector(150334000,28); exponent <= '0'; WHEN "0101110100" => manhi <= conv_std_logic_vector(7349095,24); manlo <= conv_std_logic_vector(244527329,28); exponent <= '0'; WHEN "0101110101" => manhi <= conv_std_logic_vector(7372668,24); manlo <= conv_std_logic_vector(72606054,28); exponent <= '0'; WHEN "0101110110" => manhi <= conv_std_logic_vector(7396263,24); manlo <= conv_std_logic_vector(177475612,28); exponent <= '0'; WHEN "0101110111" => manhi <= conv_std_logic_vector(7419882,24); manlo <= conv_std_logic_vector(28305511,28); exponent <= '0'; WHEN "0101111000" => manhi <= conv_std_logic_vector(7443523,24); manlo <= conv_std_logic_vector(168012985,28); exponent <= '0'; WHEN "0101111001" => manhi <= conv_std_logic_vector(7467188,24); manlo <= conv_std_logic_vector(65779352,28); exponent <= '0'; WHEN "0101111010" => manhi <= conv_std_logic_vector(7490875,24); manlo <= conv_std_logic_vector(264533668,28); exponent <= '0'; WHEN "0101111011" => manhi <= conv_std_logic_vector(7514586,24); manlo <= conv_std_logic_vector(233469080,28); exponent <= '0'; WHEN "0101111100" => manhi <= conv_std_logic_vector(7538320,24); manlo <= conv_std_logic_vector(247091035,28); exponent <= '0'; WHEN "0101111101" => manhi <= conv_std_logic_vector(7562078,24); manlo <= conv_std_logic_vector(43039991,28); exponent <= '0'; WHEN "0101111110" => manhi <= conv_std_logic_vector(7585858,24); manlo <= conv_std_logic_vector(164268716,28); exponent <= '0'; WHEN "0101111111" => manhi <= conv_std_logic_vector(7609662,24); manlo <= conv_std_logic_vector(79994093,28); exponent <= '0'; WHEN "0110000000" => manhi <= conv_std_logic_vector(7633489,24); manlo <= conv_std_logic_vector(64745322,28); exponent <= '0'; WHEN "0110000001" => manhi <= conv_std_logic_vector(7657339,24); manlo <= conv_std_logic_vector(124622102,28); exponent <= '0'; WHEN "0110000010" => manhi <= conv_std_logic_vector(7681212,24); manlo <= conv_std_logic_vector(265730090,28); exponent <= '0'; WHEN "0110000011" => manhi <= conv_std_logic_vector(7705109,24); manlo <= conv_std_logic_vector(225745453,28); exponent <= '0'; WHEN "0110000100" => manhi <= conv_std_logic_vector(7729030,24); manlo <= conv_std_logic_vector(10785785,28); exponent <= '0'; WHEN "0110000101" => manhi <= conv_std_logic_vector(7752973,24); manlo <= conv_std_logic_vector(163845570,28); exponent <= '0'; WHEN "0110000110" => manhi <= conv_std_logic_vector(7776940,24); manlo <= conv_std_logic_vector(154183450,28); exponent <= '0'; WHEN "0110000111" => manhi <= conv_std_logic_vector(7800930,24); manlo <= conv_std_logic_vector(256370426,28); exponent <= '0'; WHEN "0110001000" => manhi <= conv_std_logic_vector(7824944,24); manlo <= conv_std_logic_vector(208112577,28); exponent <= '0'; WHEN "0110001001" => manhi <= conv_std_logic_vector(7848982,24); manlo <= conv_std_logic_vector(15557444,28); exponent <= '0'; WHEN "0110001010" => manhi <= conv_std_logic_vector(7873042,24); manlo <= conv_std_logic_vector(221729482,28); exponent <= '0'; WHEN "0110001011" => manhi <= conv_std_logic_vector(7897127,24); manlo <= conv_std_logic_vector(27481881,28); exponent <= '0'; WHEN "0110001100" => manhi <= conv_std_logic_vector(7921234,24); manlo <= conv_std_logic_vector(244286584,28); exponent <= '0'; WHEN "0110001101" => manhi <= conv_std_logic_vector(7945366,24); manlo <= conv_std_logic_vector(73008824,28); exponent <= '0'; WHEN "0110001110" => manhi <= conv_std_logic_vector(7969521,24); manlo <= conv_std_logic_vector(56697140,28); exponent <= '0'; WHEN "0110001111" => manhi <= conv_std_logic_vector(7993699,24); manlo <= conv_std_logic_vector(201535196,28); exponent <= '0'; WHEN "0110010000" => manhi <= conv_std_logic_vector(8017901,24); manlo <= conv_std_logic_vector(245277246,28); exponent <= '0'; WHEN "0110010001" => manhi <= conv_std_logic_vector(8042127,24); manlo <= conv_std_logic_vector(194119042,28); exponent <= '0'; WHEN "0110010010" => manhi <= conv_std_logic_vector(8066377,24); manlo <= conv_std_logic_vector(54262392,28); exponent <= '0'; WHEN "0110010011" => manhi <= conv_std_logic_vector(8090650,24); manlo <= conv_std_logic_vector(100350618,28); exponent <= '0'; WHEN "0110010100" => manhi <= conv_std_logic_vector(8114947,24); manlo <= conv_std_logic_vector(70162199,28); exponent <= '0'; WHEN "0110010101" => manhi <= conv_std_logic_vector(8139267,24); manlo <= conv_std_logic_vector(238352593,28); exponent <= '0'; WHEN "0110010110" => manhi <= conv_std_logic_vector(8163612,24); manlo <= conv_std_logic_vector(74276969,28); exponent <= '0'; WHEN "0110010111" => manhi <= conv_std_logic_vector(8187980,24); manlo <= conv_std_logic_vector(121038404,28); exponent <= '0'; WHEN "0110011000" => manhi <= conv_std_logic_vector(8212372,24); manlo <= conv_std_logic_vector(116439694,28); exponent <= '0'; WHEN "0110011001" => manhi <= conv_std_logic_vector(8236788,24); manlo <= conv_std_logic_vector(66725186,28); exponent <= '0'; WHEN "0110011010" => manhi <= conv_std_logic_vector(8261227,24); manlo <= conv_std_logic_vector(246580788,28); exponent <= '0'; WHEN "0110011011" => manhi <= conv_std_logic_vector(8285691,24); manlo <= conv_std_logic_vector(125392143,28); exponent <= '0'; WHEN "0110011100" => manhi <= conv_std_logic_vector(8310178,24); manlo <= conv_std_logic_vector(246292830,28); exponent <= '0'; WHEN "0110011101" => manhi <= conv_std_logic_vector(8334690,24); manlo <= conv_std_logic_vector(78680728,28); exponent <= '0'; WHEN "0110011110" => manhi <= conv_std_logic_vector(8359225,24); manlo <= conv_std_logic_vector(165701659,28); exponent <= '0'; WHEN "0110011111" => manhi <= conv_std_logic_vector(8383784,24); manlo <= conv_std_logic_vector(245201212,28); exponent <= '0'; WHEN "0110100000" => manhi <= conv_std_logic_vector(8408368,24); manlo <= conv_std_logic_vector(55031110,28); exponent <= '0'; WHEN "0110100001" => manhi <= conv_std_logic_vector(8432975,24); manlo <= conv_std_logic_vector(138355589,28); exponent <= '0'; WHEN "0110100010" => manhi <= conv_std_logic_vector(8457606,24); manlo <= conv_std_logic_vector(233038665,28); exponent <= '0'; WHEN "0110100011" => manhi <= conv_std_logic_vector(8482262,24); manlo <= conv_std_logic_vector(76950508,28); exponent <= '0'; WHEN "0110100100" => manhi <= conv_std_logic_vector(8506941,24); manlo <= conv_std_logic_vector(213273820,28); exponent <= '0'; WHEN "0110100101" => manhi <= conv_std_logic_vector(8531645,24); manlo <= conv_std_logic_vector(111455640,28); exponent <= '0'; WHEN "0110100110" => manhi <= conv_std_logic_vector(8556373,24); manlo <= conv_std_logic_vector(46255554,28); exponent <= '0'; WHEN "0110100111" => manhi <= conv_std_logic_vector(8581125,24); manlo <= conv_std_logic_vector(24003868,28); exponent <= '0'; WHEN "0110101000" => manhi <= conv_std_logic_vector(8605901,24); manlo <= conv_std_logic_vector(51037072,28); exponent <= '0'; WHEN "0110101001" => manhi <= conv_std_logic_vector(8630701,24); manlo <= conv_std_logic_vector(133697849,28); exponent <= '0'; WHEN "0110101010" => manhi <= conv_std_logic_vector(8655526,24); manlo <= conv_std_logic_vector(9899623,28); exponent <= '0'; WHEN "0110101011" => manhi <= conv_std_logic_vector(8680374,24); manlo <= conv_std_logic_vector(222868388,28); exponent <= '0'; WHEN "0110101100" => manhi <= conv_std_logic_vector(8705247,24); manlo <= conv_std_logic_vector(242094523,28); exponent <= '0'; WHEN "0110101101" => manhi <= conv_std_logic_vector(8730145,24); manlo <= conv_std_logic_vector(73945536,28); exponent <= '0'; WHEN "0110101110" => manhi <= conv_std_logic_vector(8755066,24); manlo <= conv_std_logic_vector(261666066,28); exponent <= '0'; WHEN "0110101111" => manhi <= conv_std_logic_vector(8780013,24); manlo <= conv_std_logic_vector(6329700,28); exponent <= '0'; WHEN "0110110000" => manhi <= conv_std_logic_vector(8804983,24); manlo <= conv_std_logic_vector(119628997,28); exponent <= '0'; WHEN "0110110001" => manhi <= conv_std_logic_vector(8829978,24); manlo <= conv_std_logic_vector(71085473,28); exponent <= '0'; WHEN "0110110010" => manhi <= conv_std_logic_vector(8854997,24); manlo <= conv_std_logic_vector(135533257,28); exponent <= '0'; WHEN "0110110011" => manhi <= conv_std_logic_vector(8880041,24); manlo <= conv_std_logic_vector(50941820,28); exponent <= '0'; WHEN "0110110100" => manhi <= conv_std_logic_vector(8905109,24); manlo <= conv_std_logic_vector(92157802,28); exponent <= '0'; WHEN "0110110101" => manhi <= conv_std_logic_vector(8930201,24); manlo <= conv_std_logic_vector(265598650,28); exponent <= '0'; WHEN "0110110110" => manhi <= conv_std_logic_vector(8955319,24); manlo <= conv_std_logic_vector(40817170,28); exponent <= '0'; WHEN "0110110111" => manhi <= conv_std_logic_vector(8980460,24); manlo <= conv_std_logic_vector(229549724,28); exponent <= '0'; WHEN "0110111000" => manhi <= conv_std_logic_vector(9005627,24); manlo <= conv_std_logic_vector(32926222,28); exponent <= '0'; WHEN "0110111001" => manhi <= conv_std_logic_vector(9030817,24); manlo <= conv_std_logic_vector(262695596,28); exponent <= '0'; WHEN "0110111010" => manhi <= conv_std_logic_vector(9056033,24); manlo <= conv_std_logic_vector(120000337,28); exponent <= '0'; WHEN "0110111011" => manhi <= conv_std_logic_vector(9081273,24); manlo <= conv_std_logic_vector(148166518,28); exponent <= '0'; WHEN "0110111100" => manhi <= conv_std_logic_vector(9106538,24); manlo <= conv_std_logic_vector(85220151,28); exponent <= '0'; WHEN "0110111101" => manhi <= conv_std_logic_vector(9131827,24); manlo <= conv_std_logic_vector(206064472,28); exponent <= '0'; WHEN "0110111110" => manhi <= conv_std_logic_vector(9157141,24); manlo <= conv_std_logic_vector(248738124,28); exponent <= '0'; WHEN "0110111111" => manhi <= conv_std_logic_vector(9182480,24); manlo <= conv_std_logic_vector(219721533,28); exponent <= '0'; WHEN "0111000000" => manhi <= conv_std_logic_vector(9207844,24); manlo <= conv_std_logic_vector(125501456,28); exponent <= '0'; WHEN "0111000001" => manhi <= conv_std_logic_vector(9233232,24); manlo <= conv_std_logic_vector(241006443,28); exponent <= '0'; WHEN "0111000010" => manhi <= conv_std_logic_vector(9258646,24); manlo <= conv_std_logic_vector(35865021,28); exponent <= '0'; WHEN "0111000011" => manhi <= conv_std_logic_vector(9284084,24); manlo <= conv_std_logic_vector(53453891,28); exponent <= '0'; WHEN "0111000100" => manhi <= conv_std_logic_vector(9309547,24); manlo <= conv_std_logic_vector(31849742,28); exponent <= '0'; WHEN "0111000101" => manhi <= conv_std_logic_vector(9335034,24); manlo <= conv_std_logic_vector(246006538,28); exponent <= '0'; WHEN "0111000110" => manhi <= conv_std_logic_vector(9360547,24); manlo <= conv_std_logic_vector(165578245,28); exponent <= '0'; WHEN "0111000111" => manhi <= conv_std_logic_vector(9386085,24); manlo <= conv_std_logic_vector(65531569,28); exponent <= '0'; WHEN "0111001000" => manhi <= conv_std_logic_vector(9411647,24); manlo <= conv_std_logic_vector(220839600,28); exponent <= '0'; WHEN "0111001001" => manhi <= conv_std_logic_vector(9437235,24); manlo <= conv_std_logic_vector(101175446,28); exponent <= '0'; WHEN "0111001010" => manhi <= conv_std_logic_vector(9462847,24); manlo <= conv_std_logic_vector(249960434,28); exponent <= '0'; WHEN "0111001011" => manhi <= conv_std_logic_vector(9488485,24); manlo <= conv_std_logic_vector(136880466,28); exponent <= '0'; WHEN "0111001100" => manhi <= conv_std_logic_vector(9514148,24); manlo <= conv_std_logic_vector(36934219,28); exponent <= '0'; WHEN "0111001101" => manhi <= conv_std_logic_vector(9539835,24); manlo <= conv_std_logic_vector(225126782,28); exponent <= '0'; WHEN "0111001110" => manhi <= conv_std_logic_vector(9565548,24); manlo <= conv_std_logic_vector(171163295,28); exponent <= '0'; WHEN "0111001111" => manhi <= conv_std_logic_vector(9591286,24); manlo <= conv_std_logic_vector(150061692,28); exponent <= '0'; WHEN "0111010000" => manhi <= conv_std_logic_vector(9617049,24); manlo <= conv_std_logic_vector(168410880,28); exponent <= '0'; WHEN "0111010001" => manhi <= conv_std_logic_vector(9642837,24); manlo <= conv_std_logic_vector(232806206,28); exponent <= '0'; WHEN "0111010010" => manhi <= conv_std_logic_vector(9668651,24); manlo <= conv_std_logic_vector(81414002,28); exponent <= '0'; WHEN "0111010011" => manhi <= conv_std_logic_vector(9694489,24); manlo <= conv_std_logic_vector(257713424,28); exponent <= '0'; WHEN "0111010100" => manhi <= conv_std_logic_vector(9720353,24); manlo <= conv_std_logic_vector(231448253,28); exponent <= '0'; WHEN "0111010101" => manhi <= conv_std_logic_vector(9746243,24); manlo <= conv_std_logic_vector(9239650,28); exponent <= '0'; WHEN "0111010110" => manhi <= conv_std_logic_vector(9772157,24); manlo <= conv_std_logic_vector(134586155,28); exponent <= '0'; WHEN "0111010111" => manhi <= conv_std_logic_vector(9798097,24); manlo <= conv_std_logic_vector(77250961,28); exponent <= '0'; WHEN "0111011000" => manhi <= conv_std_logic_vector(9824062,24); manlo <= conv_std_logic_vector(112310110,28); exponent <= '0'; WHEN "0111011001" => manhi <= conv_std_logic_vector(9850052,24); manlo <= conv_std_logic_vector(246410674,28); exponent <= '0'; WHEN "0111011010" => manhi <= conv_std_logic_vector(9876068,24); manlo <= conv_std_logic_vector(217770768,28); exponent <= '0'; WHEN "0111011011" => manhi <= conv_std_logic_vector(9902110,24); manlo <= conv_std_logic_vector(33050459,28); exponent <= '0'; WHEN "0111011100" => manhi <= conv_std_logic_vector(9928176,24); manlo <= conv_std_logic_vector(235787236,28); exponent <= '0'; WHEN "0111011101" => manhi <= conv_std_logic_vector(9954269,24); manlo <= conv_std_logic_vector(27347822,28); exponent <= '0'; WHEN "0111011110" => manhi <= conv_std_logic_vector(9980386,24); manlo <= conv_std_logic_vector(219718194,28); exponent <= '0'; WHEN "0111011111" => manhi <= conv_std_logic_vector(10006530,24); manlo <= conv_std_logic_vector(14278120,28); exponent <= '0'; WHEN "0111100000" => manhi <= conv_std_logic_vector(10032698,24); manlo <= conv_std_logic_vector(223026636,28); exponent <= '0'; WHEN "0111100001" => manhi <= conv_std_logic_vector(10058893,24); manlo <= conv_std_logic_vector(47356582,28); exponent <= '0'; WHEN "0111100010" => manhi <= conv_std_logic_vector(10085113,24); manlo <= conv_std_logic_vector(30844624,28); exponent <= '0'; WHEN "0111100011" => manhi <= conv_std_logic_vector(10111358,24); manlo <= conv_std_logic_vector(180203065,28); exponent <= '0'; WHEN "0111100100" => manhi <= conv_std_logic_vector(10137629,24); manlo <= conv_std_logic_vector(233715314,28); exponent <= '0'; WHEN "0111100101" => manhi <= conv_std_logic_vector(10163926,24); manlo <= conv_std_logic_vector(198106796,28); exponent <= '0'; WHEN "0111100110" => manhi <= conv_std_logic_vector(10190249,24); manlo <= conv_std_logic_vector(80109512,28); exponent <= '0'; WHEN "0111100111" => manhi <= conv_std_logic_vector(10216597,24); manlo <= conv_std_logic_vector(154897493,28); exponent <= '0'; WHEN "0111101000" => manhi <= conv_std_logic_vector(10242971,24); manlo <= conv_std_logic_vector(160780443,28); exponent <= '0'; WHEN "0111101001" => manhi <= conv_std_logic_vector(10269371,24); manlo <= conv_std_logic_vector(104510112,28); exponent <= '0'; WHEN "0111101010" => manhi <= conv_std_logic_vector(10295796,24); manlo <= conv_std_logic_vector(261280303,28); exponent <= '0'; WHEN "0111101011" => manhi <= conv_std_logic_vector(10322248,24); manlo <= conv_std_logic_vector(100985054,28); exponent <= '0'; WHEN "0111101100" => manhi <= conv_std_logic_vector(10348725,24); manlo <= conv_std_logic_vector(167266836,28); exponent <= '0'; WHEN "0111101101" => manhi <= conv_std_logic_vector(10375228,24); manlo <= conv_std_logic_vector(198468370,28); exponent <= '0'; WHEN "0111101110" => manhi <= conv_std_logic_vector(10401757,24); manlo <= conv_std_logic_vector(201374454,28); exponent <= '0'; WHEN "0111101111" => manhi <= conv_std_logic_vector(10428312,24); manlo <= conv_std_logic_vector(182776514,28); exponent <= '0'; WHEN "0111110000" => manhi <= conv_std_logic_vector(10454893,24); manlo <= conv_std_logic_vector(149472614,28); exponent <= '0'; WHEN "0111110001" => manhi <= conv_std_logic_vector(10481500,24); manlo <= conv_std_logic_vector(108267459,28); exponent <= '0'; WHEN "0111110010" => manhi <= conv_std_logic_vector(10508133,24); manlo <= conv_std_logic_vector(65972402,28); exponent <= '0'; WHEN "0111110011" => manhi <= conv_std_logic_vector(10534792,24); manlo <= conv_std_logic_vector(29405451,28); exponent <= '0'; WHEN "0111110100" => manhi <= conv_std_logic_vector(10561477,24); manlo <= conv_std_logic_vector(5391275,28); exponent <= '0'; WHEN "0111110101" => manhi <= conv_std_logic_vector(10588188,24); manlo <= conv_std_logic_vector(761213,28); exponent <= '0'; WHEN "0111110110" => manhi <= conv_std_logic_vector(10614925,24); manlo <= conv_std_logic_vector(22353276,28); exponent <= '0'; WHEN "0111110111" => manhi <= conv_std_logic_vector(10641688,24); manlo <= conv_std_logic_vector(77012158,28); exponent <= '0'; WHEN "0111111000" => manhi <= conv_std_logic_vector(10668477,24); manlo <= conv_std_logic_vector(171589240,28); exponent <= '0'; WHEN "0111111001" => manhi <= conv_std_logic_vector(10695293,24); manlo <= conv_std_logic_vector(44507139,28); exponent <= '0'; WHEN "0111111010" => manhi <= conv_std_logic_vector(10722134,24); manlo <= conv_std_logic_vector(239501544,28); exponent <= '0'; WHEN "0111111011" => manhi <= conv_std_logic_vector(10749002,24); manlo <= conv_std_logic_vector(226573024,28); exponent <= '0'; WHEN "0111111100" => manhi <= conv_std_logic_vector(10775897,24); manlo <= conv_std_logic_vector(12599777,28); exponent <= '0'; WHEN "0111111101" => manhi <= conv_std_logic_vector(10802817,24); manlo <= conv_std_logic_vector(141337630,28); exponent <= '0'; WHEN "0111111110" => manhi <= conv_std_logic_vector(10829764,24); manlo <= conv_std_logic_vector(82807315,28); exponent <= '0'; WHEN "0111111111" => manhi <= conv_std_logic_vector(10856737,24); manlo <= conv_std_logic_vector(112342665,28); exponent <= '0'; WHEN "1000000000" => manhi <= conv_std_logic_vector(10883736,24); manlo <= conv_std_logic_vector(236848796,28); exponent <= '0'; WHEN "1000000001" => manhi <= conv_std_logic_vector(10910762,24); manlo <= conv_std_logic_vector(194802116,28); exponent <= '0'; WHEN "1000000010" => manhi <= conv_std_logic_vector(10937814,24); manlo <= conv_std_logic_vector(261556696,28); exponent <= '0'; WHEN "1000000011" => manhi <= conv_std_logic_vector(10964893,24); manlo <= conv_std_logic_vector(175602458,28); exponent <= '0'; WHEN "1000000100" => manhi <= conv_std_logic_vector(10991998,24); manlo <= conv_std_logic_vector(212307000,28); exponent <= '0'; WHEN "1000000101" => manhi <= conv_std_logic_vector(11019130,24); manlo <= conv_std_logic_vector(110173782,28); exponent <= '0'; WHEN "1000000110" => manhi <= conv_std_logic_vector(11046288,24); manlo <= conv_std_logic_vector(144583954,28); exponent <= '0'; WHEN "1000000111" => manhi <= conv_std_logic_vector(11073473,24); manlo <= conv_std_logic_vector(54054542,28); exponent <= '0'; WHEN "1000001000" => manhi <= conv_std_logic_vector(11100684,24); manlo <= conv_std_logic_vector(113980276,28); exponent <= '0'; WHEN "1000001001" => manhi <= conv_std_logic_vector(11127922,24); manlo <= conv_std_logic_vector(62891774,28); exponent <= '0'; WHEN "1000001010" => manhi <= conv_std_logic_vector(11155186,24); manlo <= conv_std_logic_vector(176197372,28); exponent <= '0'; WHEN "1000001011" => manhi <= conv_std_logic_vector(11182477,24); manlo <= conv_std_logic_vector(192441306,28); exponent <= '0'; WHEN "1000001100" => manhi <= conv_std_logic_vector(11209795,24); manlo <= conv_std_logic_vector(118610088,28); exponent <= '0'; WHEN "1000001101" => manhi <= conv_std_logic_vector(11237139,24); manlo <= conv_std_logic_vector(230132514,28); exponent <= '0'; WHEN "1000001110" => manhi <= conv_std_logic_vector(11264510,24); manlo <= conv_std_logic_vector(265573296,28); exponent <= '0'; WHEN "1000001111" => manhi <= conv_std_logic_vector(11291908,24); manlo <= conv_std_logic_vector(231939446,28); exponent <= '0'; WHEN "1000010000" => manhi <= conv_std_logic_vector(11319333,24); manlo <= conv_std_logic_vector(136244820,28); exponent <= '0'; WHEN "1000010001" => manhi <= conv_std_logic_vector(11346784,24); manlo <= conv_std_logic_vector(253945584,28); exponent <= '0'; WHEN "1000010010" => manhi <= conv_std_logic_vector(11374263,24); manlo <= conv_std_logic_vector(55198395,28); exponent <= '0'; WHEN "1000010011" => manhi <= conv_std_logic_vector(11401768,24); manlo <= conv_std_logic_vector(83908598,28); exponent <= '0'; WHEN "1000010100" => manhi <= conv_std_logic_vector(11429300,24); manlo <= conv_std_logic_vector(78682048,28); exponent <= '0'; WHEN "1000010101" => manhi <= conv_std_logic_vector(11456859,24); manlo <= conv_std_logic_vector(46566930,28); exponent <= '0'; WHEN "1000010110" => manhi <= conv_std_logic_vector(11484444,24); manlo <= conv_std_logic_vector(263053774,28); exponent <= '0'; WHEN "1000010111" => manhi <= conv_std_logic_vector(11512057,24); manlo <= conv_std_logic_vector(198333637,28); exponent <= '0'; WHEN "1000011000" => manhi <= conv_std_logic_vector(11539697,24); manlo <= conv_std_logic_vector(127910840,28); exponent <= '0'; WHEN "1000011001" => manhi <= conv_std_logic_vector(11567364,24); manlo <= conv_std_logic_vector(58861158,28); exponent <= '0'; WHEN "1000011010" => manhi <= conv_std_logic_vector(11595057,24); manlo <= conv_std_logic_vector(266702732,28); exponent <= '0'; WHEN "1000011011" => manhi <= conv_std_logic_vector(11622778,24); manlo <= conv_std_logic_vector(221654258,28); exponent <= '0'; WHEN "1000011100" => manhi <= conv_std_logic_vector(11650526,24); manlo <= conv_std_logic_vector(199247725,28); exponent <= '0'; WHEN "1000011101" => manhi <= conv_std_logic_vector(11678301,24); manlo <= conv_std_logic_vector(206586600,28); exponent <= '0'; WHEN "1000011110" => manhi <= conv_std_logic_vector(11706103,24); manlo <= conv_std_logic_vector(250781292,28); exponent <= '0'; WHEN "1000011111" => manhi <= conv_std_logic_vector(11733933,24); manlo <= conv_std_logic_vector(70513697,28); exponent <= '0'; WHEN "1000100000" => manhi <= conv_std_logic_vector(11761789,24); manlo <= conv_std_logic_vector(209779039,28); exponent <= '0'; WHEN "1000100001" => manhi <= conv_std_logic_vector(11789673,24); manlo <= conv_std_logic_vector(138837672,28); exponent <= '0'; WHEN "1000100010" => manhi <= conv_std_logic_vector(11817584,24); manlo <= conv_std_logic_vector(133263292,28); exponent <= '0'; WHEN "1000100011" => manhi <= conv_std_logic_vector(11845522,24); manlo <= conv_std_logic_vector(200201109,28); exponent <= '0'; WHEN "1000100100" => manhi <= conv_std_logic_vector(11873488,24); manlo <= conv_std_logic_vector(78367858,28); exponent <= '0'; WHEN "1000100101" => manhi <= conv_std_logic_vector(11901481,24); manlo <= conv_std_logic_vector(43358178,28); exponent <= '0'; WHEN "1000100110" => manhi <= conv_std_logic_vector(11929501,24); manlo <= conv_std_logic_vector(102338242,28); exponent <= '0'; WHEN "1000100111" => manhi <= conv_std_logic_vector(11957548,24); manlo <= conv_std_logic_vector(262481228,28); exponent <= '0'; WHEN "1000101000" => manhi <= conv_std_logic_vector(11985623,24); manlo <= conv_std_logic_vector(262531864,28); exponent <= '0'; WHEN "1000101001" => manhi <= conv_std_logic_vector(12013726,24); manlo <= conv_std_logic_vector(109677352,28); exponent <= '0'; WHEN "1000101010" => manhi <= conv_std_logic_vector(12041856,24); manlo <= conv_std_logic_vector(79547371,28); exponent <= '0'; WHEN "1000101011" => manhi <= conv_std_logic_vector(12070013,24); manlo <= conv_std_logic_vector(179343172,28); exponent <= '0'; WHEN "1000101100" => manhi <= conv_std_logic_vector(12098198,24); manlo <= conv_std_logic_vector(147837587,28); exponent <= '0'; WHEN "1000101101" => manhi <= conv_std_logic_vector(12126410,24); manlo <= conv_std_logic_vector(260681402,28); exponent <= '0'; WHEN "1000101110" => manhi <= conv_std_logic_vector(12154650,24); manlo <= conv_std_logic_vector(256661542,28); exponent <= '0'; WHEN "1000101111" => manhi <= conv_std_logic_vector(12182918,24); manlo <= conv_std_logic_vector(143007443,28); exponent <= '0'; WHEN "1000110000" => manhi <= conv_std_logic_vector(12211213,24); manlo <= conv_std_logic_vector(195391062,28); exponent <= '0'; WHEN "1000110001" => manhi <= conv_std_logic_vector(12239536,24); manlo <= conv_std_logic_vector(152620513,28); exponent <= '0'; WHEN "1000110010" => manhi <= conv_std_logic_vector(12267887,24); manlo <= conv_std_logic_vector(21946444,28); exponent <= '0'; WHEN "1000110011" => manhi <= conv_std_logic_vector(12296265,24); manlo <= conv_std_logic_vector(79062042,28); exponent <= '0'; WHEN "1000110100" => manhi <= conv_std_logic_vector(12324671,24); manlo <= conv_std_logic_vector(62796676,28); exponent <= '0'; WHEN "1000110101" => manhi <= conv_std_logic_vector(12353104,24); manlo <= conv_std_logic_vector(248857722,28); exponent <= '0'; WHEN "1000110110" => manhi <= conv_std_logic_vector(12381566,24); manlo <= conv_std_logic_vector(107653293,28); exponent <= '0'; WHEN "1000110111" => manhi <= conv_std_logic_vector(12410055,24); manlo <= conv_std_logic_vector(183340440,28); exponent <= '0'; WHEN "1000111000" => manhi <= conv_std_logic_vector(12438572,24); manlo <= conv_std_logic_vector(214776964,28); exponent <= '0'; WHEN "1000111001" => manhi <= conv_std_logic_vector(12467117,24); manlo <= conv_std_logic_vector(209263248,28); exponent <= '0'; WHEN "1000111010" => manhi <= conv_std_logic_vector(12495690,24); manlo <= conv_std_logic_vector(174106806,28); exponent <= '0'; WHEN "1000111011" => manhi <= conv_std_logic_vector(12524291,24); manlo <= conv_std_logic_vector(116622293,28); exponent <= '0'; WHEN "1000111100" => manhi <= conv_std_logic_vector(12552920,24); manlo <= conv_std_logic_vector(44131512,28); exponent <= '0'; WHEN "1000111101" => manhi <= conv_std_logic_vector(12581576,24); manlo <= conv_std_logic_vector(232398874,28); exponent <= '0'; WHEN "1000111110" => manhi <= conv_std_logic_vector(12610261,24); manlo <= conv_std_logic_vector(151889582,28); exponent <= '0'; WHEN "1000111111" => manhi <= conv_std_logic_vector(12638974,24); manlo <= conv_std_logic_vector(78382378,28); exponent <= '0'; WHEN "1001000000" => manhi <= conv_std_logic_vector(12667715,24); manlo <= conv_std_logic_vector(19227718,28); exponent <= '0'; WHEN "1001000001" => manhi <= conv_std_logic_vector(12696483,24); manlo <= conv_std_logic_vector(250218700,28); exponent <= '0'; WHEN "1001000010" => manhi <= conv_std_logic_vector(12725280,24); manlo <= conv_std_logic_vector(241849240,28); exponent <= '0'; WHEN "1001000011" => manhi <= conv_std_logic_vector(12754106,24); manlo <= conv_std_logic_vector(1491364,28); exponent <= '0'; WHEN "1001000100" => manhi <= conv_std_logic_vector(12782959,24); manlo <= conv_std_logic_vector(73395209,28); exponent <= '0'; WHEN "1001000101" => manhi <= conv_std_logic_vector(12811840,24); manlo <= conv_std_logic_vector(196511758,28); exponent <= '0'; WHEN "1001000110" => manhi <= conv_std_logic_vector(12840750,24); manlo <= conv_std_logic_vector(109799208,28); exponent <= '0'; WHEN "1001000111" => manhi <= conv_std_logic_vector(12869688,24); manlo <= conv_std_logic_vector(89093893,28); exponent <= '0'; WHEN "1001001000" => manhi <= conv_std_logic_vector(12898654,24); manlo <= conv_std_logic_vector(141803923,28); exponent <= '0'; WHEN "1001001001" => manhi <= conv_std_logic_vector(12927649,24); manlo <= conv_std_logic_vector(6909187,28); exponent <= '0'; WHEN "1001001010" => manhi <= conv_std_logic_vector(12956671,24); manlo <= conv_std_logic_vector(228703191,28); exponent <= '0'; WHEN "1001001011" => manhi <= conv_std_logic_vector(12985723,24); manlo <= conv_std_logic_vector(9309409,28); exponent <= '0'; WHEN "1001001100" => manhi <= conv_std_logic_vector(13014802,24); manlo <= conv_std_logic_vector(161471314,28); exponent <= '0'; WHEN "1001001101" => manhi <= conv_std_logic_vector(13043910,24); manlo <= conv_std_logic_vector(155762363,28); exponent <= '0'; WHEN "1001001110" => manhi <= conv_std_logic_vector(13073046,24); manlo <= conv_std_logic_vector(268069656,28); exponent <= '0'; WHEN "1001001111" => manhi <= conv_std_logic_vector(13102211,24); manlo <= conv_std_logic_vector(237416659,28); exponent <= '0'; WHEN "1001010000" => manhi <= conv_std_logic_vector(13131405,24); manlo <= conv_std_logic_vector(71269584,28); exponent <= '0'; WHEN "1001010001" => manhi <= conv_std_logic_vector(13160627,24); manlo <= conv_std_logic_vector(45537394,28); exponent <= '0'; WHEN "1001010010" => manhi <= conv_std_logic_vector(13189877,24); manlo <= conv_std_logic_vector(167700897,28); exponent <= '0'; WHEN "1001010011" => manhi <= conv_std_logic_vector(13219156,24); manlo <= conv_std_logic_vector(176812753,28); exponent <= '0'; WHEN "1001010100" => manhi <= conv_std_logic_vector(13248464,24); manlo <= conv_std_logic_vector(80368396,28); exponent <= '0'; WHEN "1001010101" => manhi <= conv_std_logic_vector(13277800,24); manlo <= conv_std_logic_vector(154306039,28); exponent <= '0'; WHEN "1001010110" => manhi <= conv_std_logic_vector(13307165,24); manlo <= conv_std_logic_vector(137700312,28); exponent <= '0'; WHEN "1001010111" => manhi <= conv_std_logic_vector(13336559,24); manlo <= conv_std_logic_vector(38068641,28); exponent <= '0'; WHEN "1001011000" => manhi <= conv_std_logic_vector(13365981,24); manlo <= conv_std_logic_vector(131371250,28); exponent <= '0'; WHEN "1001011001" => manhi <= conv_std_logic_vector(13395432,24); manlo <= conv_std_logic_vector(156704806,28); exponent <= '0'; WHEN "1001011010" => manhi <= conv_std_logic_vector(13424912,24); manlo <= conv_std_logic_vector(121608790,28); exponent <= '0'; WHEN "1001011011" => manhi <= conv_std_logic_vector(13454421,24); manlo <= conv_std_logic_vector(33630048,28); exponent <= '0'; WHEN "1001011100" => manhi <= conv_std_logic_vector(13483958,24); manlo <= conv_std_logic_vector(168758257,28); exponent <= '0'; WHEN "1001011101" => manhi <= conv_std_logic_vector(13513524,24); manlo <= conv_std_logic_vector(266119562,28); exponent <= '0'; WHEN "1001011110" => manhi <= conv_std_logic_vector(13543120,24); manlo <= conv_std_logic_vector(64847498,28); exponent <= '0'; WHEN "1001011111" => manhi <= conv_std_logic_vector(13572744,24); manlo <= conv_std_logic_vector(109389360,28); exponent <= '0'; WHEN "1001100000" => manhi <= conv_std_logic_vector(13602397,24); manlo <= conv_std_logic_vector(138893481,28); exponent <= '0'; WHEN "1001100001" => manhi <= conv_std_logic_vector(13632079,24); manlo <= conv_std_logic_vector(160951056,28); exponent <= '0'; WHEN "1001100010" => manhi <= conv_std_logic_vector(13661790,24); manlo <= conv_std_logic_vector(183160698,28); exponent <= '0'; WHEN "1001100011" => manhi <= conv_std_logic_vector(13691530,24); manlo <= conv_std_logic_vector(213128447,28); exponent <= '0'; WHEN "1001100100" => manhi <= conv_std_logic_vector(13721299,24); manlo <= conv_std_logic_vector(258467771,28); exponent <= '0'; WHEN "1001100101" => manhi <= conv_std_logic_vector(13751098,24); manlo <= conv_std_logic_vector(58364122,28); exponent <= '0'; WHEN "1001100110" => manhi <= conv_std_logic_vector(13780925,24); manlo <= conv_std_logic_vector(157316766,28); exponent <= '0'; WHEN "1001100111" => manhi <= conv_std_logic_vector(13810782,24); manlo <= conv_std_logic_vector(26090597,28); exponent <= '0'; WHEN "1001101000" => manhi <= conv_std_logic_vector(13840667,24); manlo <= conv_std_logic_vector(209199796,28); exponent <= '0'; WHEN "1001101001" => manhi <= conv_std_logic_vector(13870582,24); manlo <= conv_std_logic_vector(177424185,28); exponent <= '0'; WHEN "1001101010" => manhi <= conv_std_logic_vector(13900526,24); manlo <= conv_std_logic_vector(206857431,28); exponent <= '0'; WHEN "1001101011" => manhi <= conv_std_logic_vector(13930500,24); manlo <= conv_std_logic_vector(36729770,28); exponent <= '0'; WHEN "1001101100" => manhi <= conv_std_logic_vector(13960502,24); manlo <= conv_std_logic_vector(211585297,28); exponent <= '0'; WHEN "1001101101" => manhi <= conv_std_logic_vector(13990534,24); manlo <= conv_std_logic_vector(202233780,28); exponent <= '0'; WHEN "1001101110" => manhi <= conv_std_logic_vector(14020596,24); manlo <= conv_std_logic_vector(16363400,28); exponent <= '0'; WHEN "1001101111" => manhi <= conv_std_logic_vector(14050686,24); manlo <= conv_std_logic_vector(198540768,28); exponent <= '0'; WHEN "1001110000" => manhi <= conv_std_logic_vector(14080806,24); manlo <= conv_std_logic_vector(219598184,28); exponent <= '0'; WHEN "1001110001" => manhi <= conv_std_logic_vector(14110956,24); manlo <= conv_std_logic_vector(87246388,28); exponent <= '0'; WHEN "1001110010" => manhi <= conv_std_logic_vector(14141135,24); manlo <= conv_std_logic_vector(77639113,28); exponent <= '0'; WHEN "1001110011" => manhi <= conv_std_logic_vector(14171343,24); manlo <= conv_std_logic_vector(198502173,28); exponent <= '0'; WHEN "1001110100" => manhi <= conv_std_logic_vector(14201581,24); manlo <= conv_std_logic_vector(189133475,28); exponent <= '0'; WHEN "1001110101" => manhi <= conv_std_logic_vector(14231849,24); manlo <= conv_std_logic_vector(57273941,28); exponent <= '0'; WHEN "1001110110" => manhi <= conv_std_logic_vector(14262146,24); manlo <= conv_std_logic_vector(79107508,28); exponent <= '0'; WHEN "1001110111" => manhi <= conv_std_logic_vector(14292472,24); manlo <= conv_std_logic_vector(262390229,28); exponent <= '0'; WHEN "1001111000" => manhi <= conv_std_logic_vector(14322829,24); manlo <= conv_std_logic_vector(78014825,28); exponent <= '0'; WHEN "1001111001" => manhi <= conv_std_logic_vector(14353215,24); manlo <= conv_std_logic_vector(70623424,28); exponent <= '0'; WHEN "1001111010" => manhi <= conv_std_logic_vector(14383630,24); manlo <= conv_std_logic_vector(247994836,28); exponent <= '0'; WHEN "1001111011" => manhi <= conv_std_logic_vector(14414076,24); manlo <= conv_std_logic_vector(81044559,28); exponent <= '0'; WHEN "1001111100" => manhi <= conv_std_logic_vector(14444551,24); manlo <= conv_std_logic_vector(114437521,28); exponent <= '0'; WHEN "1001111101" => manhi <= conv_std_logic_vector(14475056,24); manlo <= conv_std_logic_vector(87539900,28); exponent <= '0'; WHEN "1001111110" => manhi <= conv_std_logic_vector(14505591,24); manlo <= conv_std_logic_vector(8160950,28); exponent <= '0'; WHEN "1001111111" => manhi <= conv_std_logic_vector(14536155,24); manlo <= conv_std_logic_vector(152553012,28); exponent <= '0'; WHEN "1010000000" => manhi <= conv_std_logic_vector(14566749,24); manlo <= conv_std_logic_vector(260105152,28); exponent <= '0'; WHEN "1010000001" => manhi <= conv_std_logic_vector(14597374,24); manlo <= conv_std_logic_vector(70214083,28); exponent <= '0'; WHEN "1010000010" => manhi <= conv_std_logic_vector(14628028,24); manlo <= conv_std_logic_vector(127590534,28); exponent <= '0'; WHEN "1010000011" => manhi <= conv_std_logic_vector(14658712,24); manlo <= conv_std_logic_vector(171646531,28); exponent <= '0'; WHEN "1010000100" => manhi <= conv_std_logic_vector(14689426,24); manlo <= conv_std_logic_vector(210237219,28); exponent <= '0'; WHEN "1010000101" => manhi <= conv_std_logic_vector(14720170,24); manlo <= conv_std_logic_vector(251225419,28); exponent <= '0'; WHEN "1010000110" => manhi <= conv_std_logic_vector(14750945,24); manlo <= conv_std_logic_vector(34046180,28); exponent <= '0'; WHEN "1010000111" => manhi <= conv_std_logic_vector(14781749,24); manlo <= conv_std_logic_vector(103448606,28); exponent <= '0'; WHEN "1010001000" => manhi <= conv_std_logic_vector(14812583,24); manlo <= conv_std_logic_vector(198883134,28); exponent <= '0'; WHEN "1010001001" => manhi <= conv_std_logic_vector(14843448,24); manlo <= conv_std_logic_vector(59807901,28); exponent <= '0'; WHEN "1010001010" => manhi <= conv_std_logic_vector(14874342,24); manlo <= conv_std_logic_vector(230995129,28); exponent <= '0'; WHEN "1010001011" => manhi <= conv_std_logic_vector(14905267,24); manlo <= conv_std_logic_vector(183482934,28); exponent <= '0'; WHEN "1010001100" => manhi <= conv_std_logic_vector(14936222,24); manlo <= conv_std_logic_vector(193623526,28); exponent <= '0'; WHEN "1010001101" => manhi <= conv_std_logic_vector(14967208,24); manlo <= conv_std_logic_vector(905939,28); exponent <= '0'; WHEN "1010001110" => manhi <= conv_std_logic_vector(14998223,24); manlo <= conv_std_logic_vector(150133320,28); exponent <= '0'; WHEN "1010001111" => manhi <= conv_std_logic_vector(15029269,24); manlo <= conv_std_logic_vector(112374738,28); exponent <= '0'; WHEN "1010010000" => manhi <= conv_std_logic_vector(15060345,24); manlo <= conv_std_logic_vector(164013390,28); exponent <= '0'; WHEN "1010010001" => manhi <= conv_std_logic_vector(15091452,24); manlo <= conv_std_logic_vector(44569327,28); exponent <= '0'; WHEN "1010010010" => manhi <= conv_std_logic_vector(15122589,24); manlo <= conv_std_logic_vector(30441282,28); exponent <= '0'; WHEN "1010010011" => manhi <= conv_std_logic_vector(15153756,24); manlo <= conv_std_logic_vector(129600316,28); exponent <= '0'; WHEN "1010010100" => manhi <= conv_std_logic_vector(15184954,24); manlo <= conv_std_logic_vector(81589818,28); exponent <= '0'; WHEN "1010010101" => manhi <= conv_std_logic_vector(15216182,24); manlo <= conv_std_logic_vector(162831889,28); exponent <= '0'; WHEN "1010010110" => manhi <= conv_std_logic_vector(15247441,24); manlo <= conv_std_logic_vector(112885518,28); exponent <= '0'; WHEN "1010010111" => manhi <= conv_std_logic_vector(15278730,24); manlo <= conv_std_logic_vector(208188418,28); exponent <= '0'; WHEN "1010011000" => manhi <= conv_std_logic_vector(15310050,24); manlo <= conv_std_logic_vector(188315209,28); exponent <= '0'; WHEN "1010011001" => manhi <= conv_std_logic_vector(15341401,24); manlo <= conv_std_logic_vector(61283792,28); exponent <= '0'; WHEN "1010011010" => manhi <= conv_std_logic_vector(15372782,24); manlo <= conv_std_logic_vector(103555359,28); exponent <= '0'; WHEN "1010011011" => manhi <= conv_std_logic_vector(15404194,24); manlo <= conv_std_logic_vector(54728032,28); exponent <= '0'; WHEN "1010011100" => manhi <= conv_std_logic_vector(15435636,24); manlo <= conv_std_logic_vector(191278690,28); exponent <= '0'; WHEN "1010011101" => manhi <= conv_std_logic_vector(15467109,24); manlo <= conv_std_logic_vector(252821163,28); exponent <= '0'; WHEN "1010011110" => manhi <= conv_std_logic_vector(15498613,24); manlo <= conv_std_logic_vector(247412597,28); exponent <= '0'; WHEN "1010011111" => manhi <= conv_std_logic_vector(15530148,24); manlo <= conv_std_logic_vector(183118012,28); exponent <= '0'; WHEN "1010100000" => manhi <= conv_std_logic_vector(15561714,24); manlo <= conv_std_logic_vector(68010306,28); exponent <= '0'; WHEN "1010100001" => manhi <= conv_std_logic_vector(15593310,24); manlo <= conv_std_logic_vector(178605723,28); exponent <= '0'; WHEN "1010100010" => manhi <= conv_std_logic_vector(15624937,24); manlo <= conv_std_logic_vector(254557489,28); exponent <= '0'; WHEN "1010100011" => manhi <= conv_std_logic_vector(15656596,24); manlo <= conv_std_logic_vector(35526733,28); exponent <= '0'; WHEN "1010100100" => manhi <= conv_std_logic_vector(15688285,24); manlo <= conv_std_logic_vector(66488863,28); exponent <= '0'; WHEN "1010100101" => manhi <= conv_std_logic_vector(15720005,24); manlo <= conv_std_logic_vector(87120837,28); exponent <= '0'; WHEN "1010100110" => manhi <= conv_std_logic_vector(15751756,24); manlo <= conv_std_logic_vector(105542995,28); exponent <= '0'; WHEN "1010100111" => manhi <= conv_std_logic_vector(15783538,24); manlo <= conv_std_logic_vector(129883612,28); exponent <= '0'; WHEN "1010101000" => manhi <= conv_std_logic_vector(15815351,24); manlo <= conv_std_logic_vector(168278902,28); exponent <= '0'; WHEN "1010101001" => manhi <= conv_std_logic_vector(15847195,24); manlo <= conv_std_logic_vector(228873033,28); exponent <= '0'; WHEN "1010101010" => manhi <= conv_std_logic_vector(15879071,24); manlo <= conv_std_logic_vector(51382669,28); exponent <= '0'; WHEN "1010101011" => manhi <= conv_std_logic_vector(15910977,24); manlo <= conv_std_logic_vector(180838811,28); exponent <= '0'; WHEN "1010101100" => manhi <= conv_std_logic_vector(15942915,24); manlo <= conv_std_logic_vector(88538606,28); exponent <= '0'; WHEN "1010101101" => manhi <= conv_std_logic_vector(15974884,24); manlo <= conv_std_logic_vector(51093552,28); exponent <= '0'; WHEN "1010101110" => manhi <= conv_std_logic_vector(16006884,24); manlo <= conv_std_logic_vector(76687676,28); exponent <= '0'; WHEN "1010101111" => manhi <= conv_std_logic_vector(16038915,24); manlo <= conv_std_logic_vector(173513005,28); exponent <= '0'; WHEN "1010110000" => manhi <= conv_std_logic_vector(16070978,24); manlo <= conv_std_logic_vector(81334110,28); exponent <= '0'; WHEN "1010110001" => manhi <= conv_std_logic_vector(16103072,24); manlo <= conv_std_logic_vector(76794490,28); exponent <= '0'; WHEN "1010110010" => manhi <= conv_std_logic_vector(16135197,24); manlo <= conv_std_logic_vector(168110204,28); exponent <= '0'; WHEN "1010110011" => manhi <= conv_std_logic_vector(16167354,24); manlo <= conv_std_logic_vector(95069884,28); exponent <= '0'; WHEN "1010110100" => manhi <= conv_std_logic_vector(16199542,24); manlo <= conv_std_logic_vector(134341108,28); exponent <= '0'; WHEN "1010110101" => manhi <= conv_std_logic_vector(16231762,24); manlo <= conv_std_logic_vector(25728588,28); exponent <= '0'; WHEN "1010110110" => manhi <= conv_std_logic_vector(16264013,24); manlo <= conv_std_logic_vector(45915996,28); exponent <= '0'; WHEN "1010110111" => manhi <= conv_std_logic_vector(16296295,24); manlo <= conv_std_logic_vector(203159607,28); exponent <= '0'; WHEN "1010111000" => manhi <= conv_std_logic_vector(16328609,24); manlo <= conv_std_logic_vector(237288310,28); exponent <= '0'; WHEN "1010111001" => manhi <= conv_std_logic_vector(16360955,24); manlo <= conv_std_logic_vector(156574520,28); exponent <= '0'; WHEN "1010111010" => manhi <= conv_std_logic_vector(16393332,24); manlo <= conv_std_logic_vector(237734194,28); exponent <= '0'; WHEN "1010111011" => manhi <= conv_std_logic_vector(16425741,24); manlo <= conv_std_logic_vector(220620465,28); exponent <= '0'; WHEN "1010111100" => manhi <= conv_std_logic_vector(16458182,24); manlo <= conv_std_logic_vector(113530022,28); exponent <= '0'; WHEN "1010111101" => manhi <= conv_std_logic_vector(16490654,24); manlo <= conv_std_logic_vector(193203116,28); exponent <= '0'; WHEN "1010111110" => manhi <= conv_std_logic_vector(16523158,24); manlo <= conv_std_logic_vector(199517199,28); exponent <= '0'; WHEN "1010111111" => manhi <= conv_std_logic_vector(16555694,24); manlo <= conv_std_logic_vector(140793302,28); exponent <= '0'; WHEN "1011000000" => manhi <= conv_std_logic_vector(16588262,24); manlo <= conv_std_logic_vector(25360585,28); exponent <= '0'; WHEN "1011000001" => manhi <= conv_std_logic_vector(16620861,24); manlo <= conv_std_logic_vector(129991803,28); exponent <= '0'; WHEN "1011000010" => manhi <= conv_std_logic_vector(16653492,24); manlo <= conv_std_logic_vector(194596944,28); exponent <= '0'; WHEN "1011000011" => manhi <= conv_std_logic_vector(16686155,24); manlo <= conv_std_logic_vector(227529607,28); exponent <= '0'; WHEN "1011000100" => manhi <= conv_std_logic_vector(16718850,24); manlo <= conv_std_logic_vector(237151552,28); exponent <= '0'; WHEN "1011000101" => manhi <= conv_std_logic_vector(16751577,24); manlo <= conv_std_logic_vector(231832709,28); exponent <= '0'; WHEN "1011000110" => manhi <= conv_std_logic_vector(3560,24); manlo <= conv_std_logic_vector(109975592,28); exponent <= '1'; WHEN "1011000111" => manhi <= conv_std_logic_vector(19955,24); manlo <= conv_std_logic_vector(239164365,28); exponent <= '1'; WHEN "1011001000" => manhi <= conv_std_logic_vector(36367,24); manlo <= conv_std_logic_vector(105026731,28); exponent <= '1'; WHEN "1011001001" => manhi <= conv_std_logic_vector(52794,24); manlo <= conv_std_logic_vector(248634947,28); exponent <= '1'; WHEN "1011001010" => manhi <= conv_std_logic_vector(69238,24); manlo <= conv_std_logic_vector(137323551,28); exponent <= '1'; WHEN "1011001011" => manhi <= conv_std_logic_vector(85698,24); manlo <= conv_std_logic_vector(43737556,28); exponent <= '1'; WHEN "1011001100" => manhi <= conv_std_logic_vector(102173,24); manlo <= conv_std_logic_vector(240526091,28); exponent <= '1'; WHEN "1011001101" => manhi <= conv_std_logic_vector(118665,24); manlo <= conv_std_logic_vector(195036030,28); exponent <= '1'; WHEN "1011001110" => manhi <= conv_std_logic_vector(135173,24); manlo <= conv_std_logic_vector(179924739,28); exponent <= '1'; WHEN "1011001111" => manhi <= conv_std_logic_vector(151697,24); manlo <= conv_std_logic_vector(199418251,28); exponent <= '1'; WHEN "1011010000" => manhi <= conv_std_logic_vector(168237,24); manlo <= conv_std_logic_vector(257746730,28); exponent <= '1'; WHEN "1011010001" => manhi <= conv_std_logic_vector(184794,24); manlo <= conv_std_logic_vector(90709016,28); exponent <= '1'; WHEN "1011010010" => manhi <= conv_std_logic_vector(201366,24); manlo <= conv_std_logic_vector(239414453,28); exponent <= '1'; WHEN "1011010011" => manhi <= conv_std_logic_vector(217955,24); manlo <= conv_std_logic_vector(171234704,28); exponent <= '1'; WHEN "1011010100" => manhi <= conv_std_logic_vector(234560,24); manlo <= conv_std_logic_vector(158851944,28); exponent <= '1'; WHEN "1011010101" => manhi <= conv_std_logic_vector(251181,24); manlo <= conv_std_logic_vector(206517042,28); exponent <= '1'; WHEN "1011010110" => manhi <= conv_std_logic_vector(267819,24); manlo <= conv_std_logic_vector(50049563,28); exponent <= '1'; WHEN "1011010111" => manhi <= conv_std_logic_vector(284472,24); manlo <= conv_std_logic_vector(230579599,28); exponent <= '1'; WHEN "1011011000" => manhi <= conv_std_logic_vector(301142,24); manlo <= conv_std_logic_vector(215499577,28); exponent <= '1'; WHEN "1011011001" => manhi <= conv_std_logic_vector(317829,24); manlo <= conv_std_logic_vector(9077005,28); exponent <= '1'; WHEN "1011011010" => manhi <= conv_std_logic_vector(334531,24); manlo <= conv_std_logic_vector(152454469,28); exponent <= '1'; WHEN "1011011011" => manhi <= conv_std_logic_vector(351250,24); manlo <= conv_std_logic_vector(113036907,28); exponent <= '1'; WHEN "1011011100" => manhi <= conv_std_logic_vector(367985,24); manlo <= conv_std_logic_vector(163539801,28); exponent <= '1'; WHEN "1011011101" => manhi <= conv_std_logic_vector(384737,24); manlo <= conv_std_logic_vector(39811903,28); exponent <= '1'; WHEN "1011011110" => manhi <= conv_std_logic_vector(401505,24); manlo <= conv_std_logic_vector(14577065,28); exponent <= '1'; WHEN "1011011111" => manhi <= conv_std_logic_vector(418289,24); manlo <= conv_std_logic_vector(92127870,28); exponent <= '1'; WHEN "1011100000" => manhi <= conv_std_logic_vector(435090,24); manlo <= conv_std_logic_vector(8325641,28); exponent <= '1'; WHEN "1011100001" => manhi <= conv_std_logic_vector(451907,24); manlo <= conv_std_logic_vector(35906810,28); exponent <= '1'; WHEN "1011100010" => manhi <= conv_std_logic_vector(468740,24); manlo <= conv_std_logic_vector(179176556,28); exponent <= '1'; WHEN "1011100011" => manhi <= conv_std_logic_vector(485590,24); manlo <= conv_std_logic_vector(174008808,28); exponent <= '1'; WHEN "1011100100" => manhi <= conv_std_logic_vector(502457,24); manlo <= conv_std_logic_vector(24717160,28); exponent <= '1'; WHEN "1011100101" => manhi <= conv_std_logic_vector(519340,24); manlo <= conv_std_logic_vector(4054880,28); exponent <= '1'; WHEN "1011100110" => manhi <= conv_std_logic_vector(536239,24); manlo <= conv_std_logic_vector(116343996,28); exponent <= '1'; WHEN "1011100111" => manhi <= conv_std_logic_vector(553155,24); manlo <= conv_std_logic_vector(97475302,28); exponent <= '1'; WHEN "1011101000" => manhi <= conv_std_logic_vector(570087,24); manlo <= conv_std_logic_vector(220214735,28); exponent <= '1'; WHEN "1011101001" => manhi <= conv_std_logic_vector(587036,24); manlo <= conv_std_logic_vector(220461546,28); exponent <= '1'; WHEN "1011101010" => manhi <= conv_std_logic_vector(604002,24); manlo <= conv_std_logic_vector(102554681,28); exponent <= '1'; WHEN "1011101011" => manhi <= conv_std_logic_vector(620984,24); manlo <= conv_std_logic_vector(139272779,28); exponent <= '1'; WHEN "1011101100" => manhi <= conv_std_logic_vector(637983,24); manlo <= conv_std_logic_vector(66527812,28); exponent <= '1'; WHEN "1011101101" => manhi <= conv_std_logic_vector(654998,24); manlo <= conv_std_logic_vector(157106911,28); exponent <= '1'; WHEN "1011101110" => manhi <= conv_std_logic_vector(672030,24); manlo <= conv_std_logic_vector(146930546,28); exponent <= '1'; WHEN "1011101111" => manhi <= conv_std_logic_vector(689079,24); manlo <= conv_std_logic_vector(40358901,28); exponent <= '1'; WHEN "1011110000" => manhi <= conv_std_logic_vector(706144,24); manlo <= conv_std_logic_vector(110191873,28); exponent <= '1'; WHEN "1011110001" => manhi <= conv_std_logic_vector(723226,24); manlo <= conv_std_logic_vector(92362714,28); exponent <= '1'; WHEN "1011110010" => manhi <= conv_std_logic_vector(740324,24); manlo <= conv_std_logic_vector(259679855,28); exponent <= '1'; WHEN "1011110011" => manhi <= conv_std_logic_vector(757440,24); manlo <= conv_std_logic_vector(79649632,28); exponent <= '1'; WHEN "1011110100" => manhi <= conv_std_logic_vector(774572,24); manlo <= conv_std_logic_vector(93524482,28); exponent <= '1'; WHEN "1011110101" => manhi <= conv_std_logic_vector(791721,24); manlo <= conv_std_logic_vector(37254754,28); exponent <= '1'; WHEN "1011110110" => manhi <= conv_std_logic_vector(808886,24); manlo <= conv_std_logic_vector(183665996,28); exponent <= '1'; WHEN "1011110111" => manhi <= conv_std_logic_vector(826069,24); manlo <= conv_std_logic_vector(281674,28); exponent <= '1'; WHEN "1011111000" => manhi <= conv_std_logic_vector(843268,24); manlo <= conv_std_logic_vector(28371374,28); exponent <= '1'; WHEN "1011111001" => manhi <= conv_std_logic_vector(860484,24); manlo <= conv_std_logic_vector(3902612,28); exponent <= '1'; WHEN "1011111010" => manhi <= conv_std_logic_vector(877716,24); manlo <= conv_std_logic_vector(199718117,28); exponent <= '1'; WHEN "1011111011" => manhi <= conv_std_logic_vector(894966,24); manlo <= conv_std_logic_vector(83358555,28); exponent <= '1'; WHEN "1011111100" => manhi <= conv_std_logic_vector(912232,24); manlo <= conv_std_logic_vector(196110728,28); exponent <= '1'; WHEN "1011111101" => manhi <= conv_std_logic_vector(929516,24); manlo <= conv_std_logic_vector(5523929,28); exponent <= '1'; WHEN "1011111110" => manhi <= conv_std_logic_vector(946816,24); manlo <= conv_std_logic_vector(52893590,28); exponent <= '1'; WHEN "1011111111" => manhi <= conv_std_logic_vector(964133,24); manlo <= conv_std_logic_vector(74213103,28); exponent <= '1'; WHEN "1100000000" => manhi <= conv_std_logic_vector(981467,24); manlo <= conv_std_logic_vector(73915640,28); exponent <= '1'; WHEN "1100000001" => manhi <= conv_std_logic_vector(998818,24); manlo <= conv_std_logic_vector(56438704,28); exponent <= '1'; WHEN "1100000010" => manhi <= conv_std_logic_vector(1016186,24); manlo <= conv_std_logic_vector(26224136,28); exponent <= '1'; WHEN "1100000011" => manhi <= conv_std_logic_vector(1033570,24); manlo <= conv_std_logic_vector(256153571,28); exponent <= '1'; WHEN "1100000100" => manhi <= conv_std_logic_vector(1050972,24); manlo <= conv_std_logic_vector(213806620,28); exponent <= '1'; WHEN "1100000101" => manhi <= conv_std_logic_vector(1068391,24); manlo <= conv_std_logic_vector(172073612,28); exponent <= '1'; WHEN "1100000110" => manhi <= conv_std_logic_vector(1085827,24); manlo <= conv_std_logic_vector(135413771,28); exponent <= '1'; WHEN "1100000111" => manhi <= conv_std_logic_vector(1103280,24); manlo <= conv_std_logic_vector(108290679,28); exponent <= '1'; WHEN "1100001000" => manhi <= conv_std_logic_vector(1120750,24); manlo <= conv_std_logic_vector(95172278,28); exponent <= '1'; WHEN "1100001001" => manhi <= conv_std_logic_vector(1138237,24); manlo <= conv_std_logic_vector(100530876,28); exponent <= '1'; WHEN "1100001010" => manhi <= conv_std_logic_vector(1155741,24); manlo <= conv_std_logic_vector(128843150,28); exponent <= '1'; WHEN "1100001011" => manhi <= conv_std_logic_vector(1173262,24); manlo <= conv_std_logic_vector(184590152,28); exponent <= '1'; WHEN "1100001100" => manhi <= conv_std_logic_vector(1190801,24); manlo <= conv_std_logic_vector(3821855,28); exponent <= '1'; WHEN "1100001101" => manhi <= conv_std_logic_vector(1208356,24); manlo <= conv_std_logic_vector(127898983,28); exponent <= '1'; WHEN "1100001110" => manhi <= conv_std_logic_vector(1225929,24); manlo <= conv_std_logic_vector(24444823,28); exponent <= '1'; WHEN "1100001111" => manhi <= conv_std_logic_vector(1243518,24); manlo <= conv_std_logic_vector(234828877,28); exponent <= '1'; WHEN "1100010000" => manhi <= conv_std_logic_vector(1261125,24); manlo <= conv_std_logic_vector(226683218,28); exponent <= '1'; WHEN "1100010001" => manhi <= conv_std_logic_vector(1278750,24); manlo <= conv_std_logic_vector(4515229,28); exponent <= '1'; WHEN "1100010010" => manhi <= conv_std_logic_vector(1296391,24); manlo <= conv_std_logic_vector(109707612,28); exponent <= '1'; WHEN "1100010011" => manhi <= conv_std_logic_vector(1314050,24); manlo <= conv_std_logic_vector(9905652,28); exponent <= '1'; WHEN "1100010100" => manhi <= conv_std_logic_vector(1331725,24); manlo <= conv_std_logic_vector(246500869,28); exponent <= '1'; WHEN "1100010101" => manhi <= conv_std_logic_vector(1349419,24); manlo <= conv_std_logic_vector(18711921,28); exponent <= '1'; WHEN "1100010110" => manhi <= conv_std_logic_vector(1367129,24); manlo <= conv_std_logic_vector(136374624,28); exponent <= '1'; WHEN "1100010111" => manhi <= conv_std_logic_vector(1384857,24); manlo <= conv_std_logic_vector(67151939,28); exponent <= '1'; WHEN "1100011000" => manhi <= conv_std_logic_vector(1402602,24); manlo <= conv_std_logic_vector(84017623,28); exponent <= '1'; WHEN "1100011001" => manhi <= conv_std_logic_vector(1420364,24); manlo <= conv_std_logic_vector(191514413,28); exponent <= '1'; WHEN "1100011010" => manhi <= conv_std_logic_vector(1438144,24); manlo <= conv_std_logic_vector(125754028,28); exponent <= '1'; WHEN "1100011011" => manhi <= conv_std_logic_vector(1455941,24); manlo <= conv_std_logic_vector(159723541,28); exponent <= '1'; WHEN "1100011100" => manhi <= conv_std_logic_vector(1473756,24); manlo <= conv_std_logic_vector(29543561,28); exponent <= '1'; WHEN "1100011101" => manhi <= conv_std_logic_vector(1491588,24); manlo <= conv_std_logic_vector(8210062,28); exponent <= '1'; WHEN "1100011110" => manhi <= conv_std_logic_vector(1509437,24); manlo <= conv_std_logic_vector(100288013,28); exponent <= '1'; WHEN "1100011111" => manhi <= conv_std_logic_vector(1527304,24); manlo <= conv_std_logic_vector(41911392,28); exponent <= '1'; WHEN "1100100000" => manhi <= conv_std_logic_vector(1545188,24); manlo <= conv_std_logic_vector(106089552,28); exponent <= '1'; WHEN "1100100001" => manhi <= conv_std_logic_vector(1563090,24); manlo <= conv_std_logic_vector(28965402,28); exponent <= '1'; WHEN "1100100010" => manhi <= conv_std_logic_vector(1581009,24); manlo <= conv_std_logic_vector(83557236,28); exponent <= '1'; WHEN "1100100011" => manhi <= conv_std_logic_vector(1598946,24); manlo <= conv_std_logic_vector(6016916,28); exponent <= '1'; WHEN "1100100100" => manhi <= conv_std_logic_vector(1616900,24); manlo <= conv_std_logic_vector(69371695,28); exponent <= '1'; WHEN "1100100101" => manhi <= conv_std_logic_vector(1634872,24); manlo <= conv_std_logic_vector(9782402,28); exponent <= '1'; WHEN "1100100110" => manhi <= conv_std_logic_vector(1652861,24); manlo <= conv_std_logic_vector(100285270,28); exponent <= '1'; WHEN "1100100111" => manhi <= conv_std_logic_vector(1670868,24); manlo <= conv_std_logic_vector(77050112,28); exponent <= '1'; WHEN "1100101000" => manhi <= conv_std_logic_vector(1688892,24); manlo <= conv_std_logic_vector(213122155,28); exponent <= '1'; WHEN "1100101001" => manhi <= conv_std_logic_vector(1706934,24); manlo <= conv_std_logic_vector(244680216,28); exponent <= '1'; WHEN "1100101010" => manhi <= conv_std_logic_vector(1724994,24); manlo <= conv_std_logic_vector(176343080,28); exponent <= '1'; WHEN "1100101011" => manhi <= conv_std_logic_vector(1743072,24); manlo <= conv_std_logic_vector(12734040,28); exponent <= '1'; WHEN "1100101100" => manhi <= conv_std_logic_vector(1761167,24); manlo <= conv_std_logic_vector(26916364,28); exponent <= '1'; WHEN "1100101101" => manhi <= conv_std_logic_vector(1779279,24); manlo <= conv_std_logic_vector(223522388,28); exponent <= '1'; WHEN "1100101110" => manhi <= conv_std_logic_vector(1797410,24); manlo <= conv_std_logic_vector(70318058,28); exponent <= '1'; WHEN "1100101111" => manhi <= conv_std_logic_vector(1815558,24); manlo <= conv_std_logic_vector(108815677,28); exponent <= '1'; WHEN "1100110000" => manhi <= conv_std_logic_vector(1833724,24); manlo <= conv_std_logic_vector(75225715,28); exponent <= '1'; WHEN "1100110001" => manhi <= conv_std_logic_vector(1851907,24); manlo <= conv_std_logic_vector(242634090,28); exponent <= '1'; WHEN "1100110010" => manhi <= conv_std_logic_vector(1870109,24); manlo <= conv_std_logic_vector(78824900,28); exponent <= '1'; WHEN "1100110011" => manhi <= conv_std_logic_vector(1888328,24); manlo <= conv_std_logic_vector(125328613,28); exponent <= '1'; WHEN "1100110100" => manhi <= conv_std_logic_vector(1906565,24); manlo <= conv_std_logic_vector(118373881,28); exponent <= '1'; WHEN "1100110101" => manhi <= conv_std_logic_vector(1924820,24); manlo <= conv_std_logic_vector(62629370,28); exponent <= '1'; WHEN "1100110110" => manhi <= conv_std_logic_vector(1943092,24); manlo <= conv_std_logic_vector(231203763,28); exponent <= '1'; WHEN "1100110111" => manhi <= conv_std_logic_vector(1961383,24); manlo <= conv_std_logic_vector(91903942,28); exponent <= '1'; WHEN "1100111000" => manhi <= conv_std_logic_vector(1979691,24); manlo <= conv_std_logic_vector(186283181,28); exponent <= '1'; WHEN "1100111001" => manhi <= conv_std_logic_vector(1998017,24); manlo <= conv_std_logic_vector(250592964,28); exponent <= '1'; WHEN "1100111010" => manhi <= conv_std_logic_vector(2016362,24); manlo <= conv_std_logic_vector(21089351,28); exponent <= '1'; WHEN "1100111011" => manhi <= conv_std_logic_vector(2034724,24); manlo <= conv_std_logic_vector(39339357,28); exponent <= '1'; WHEN "1100111100" => manhi <= conv_std_logic_vector(2053104,24); manlo <= conv_std_logic_vector(41608216,28); exponent <= '1'; WHEN "1100111101" => manhi <= conv_std_logic_vector(2071502,24); manlo <= conv_std_logic_vector(32601209,28); exponent <= '1'; WHEN "1100111110" => manhi <= conv_std_logic_vector(2089918,24); manlo <= conv_std_logic_vector(17028217,28); exponent <= '1'; WHEN "1100111111" => manhi <= conv_std_logic_vector(2108351,24); manlo <= conv_std_logic_vector(268039176,28); exponent <= '1'; WHEN "1101000000" => manhi <= conv_std_logic_vector(2126803,24); manlo <= conv_std_logic_vector(253482264,28); exponent <= '1'; WHEN "1101000001" => manhi <= conv_std_logic_vector(2145273,24); manlo <= conv_std_logic_vector(246516634,28); exponent <= '1'; WHEN "1101000010" => manhi <= conv_std_logic_vector(2163761,24); manlo <= conv_std_logic_vector(251870600,28); exponent <= '1'; WHEN "1101000011" => manhi <= conv_std_logic_vector(2182268,24); manlo <= conv_std_logic_vector(5841640,28); exponent <= '1'; WHEN "1101000100" => manhi <= conv_std_logic_vector(2200792,24); manlo <= conv_std_logic_vector(50038222,28); exponent <= '1'; WHEN "1101000101" => manhi <= conv_std_logic_vector(2219334,24); manlo <= conv_std_logic_vector(120767079,28); exponent <= '1'; WHEN "1101000110" => manhi <= conv_std_logic_vector(2237894,24); manlo <= conv_std_logic_vector(222775030,28); exponent <= '1'; WHEN "1101000111" => manhi <= conv_std_logic_vector(2256473,24); manlo <= conv_std_logic_vector(92378075,28); exponent <= '1'; WHEN "1101001000" => manhi <= conv_std_logic_vector(2275070,24); manlo <= conv_std_logic_vector(2767772,28); exponent <= '1'; WHEN "1101001001" => manhi <= conv_std_logic_vector(2293684,24); manlo <= conv_std_logic_vector(227140324,28); exponent <= '1'; WHEN "1101001010" => manhi <= conv_std_logic_vector(2312317,24); manlo <= conv_std_logic_vector(233390216,28); exponent <= '1'; WHEN "1101001011" => manhi <= conv_std_logic_vector(2330969,24); manlo <= conv_std_logic_vector(26287503,28); exponent <= '1'; WHEN "1101001100" => manhi <= conv_std_logic_vector(2349638,24); manlo <= conv_std_logic_vector(147477811,28); exponent <= '1'; WHEN "1101001101" => manhi <= conv_std_logic_vector(2368326,24); manlo <= conv_std_logic_vector(64869610,28); exponent <= '1'; WHEN "1101001110" => manhi <= conv_std_logic_vector(2387032,24); manlo <= conv_std_logic_vector(51682404,28); exponent <= '1'; WHEN "1101001111" => manhi <= conv_std_logic_vector(2405756,24); manlo <= conv_std_logic_vector(112704917,28); exponent <= '1'; WHEN "1101010000" => manhi <= conv_std_logic_vector(2424498,24); manlo <= conv_std_logic_vector(252730552,28); exponent <= '1'; WHEN "1101010001" => manhi <= conv_std_logic_vector(2443259,24); manlo <= conv_std_logic_vector(208121938,28); exponent <= '1'; WHEN "1101010010" => manhi <= conv_std_logic_vector(2462038,24); manlo <= conv_std_logic_vector(252117306,28); exponent <= '1'; WHEN "1101010011" => manhi <= conv_std_logic_vector(2480836,24); manlo <= conv_std_logic_vector(121088666,28); exponent <= '1'; WHEN "1101010100" => manhi <= conv_std_logic_vector(2499652,24); manlo <= conv_std_logic_vector(88283637,28); exponent <= '1'; WHEN "1101010101" => manhi <= conv_std_logic_vector(2518486,24); manlo <= conv_std_logic_vector(158519085,28); exponent <= '1'; WHEN "1101010110" => manhi <= conv_std_logic_vector(2537339,24); manlo <= conv_std_logic_vector(68181124,28); exponent <= '1'; WHEN "1101010111" => manhi <= conv_std_logic_vector(2556210,24); manlo <= conv_std_logic_vector(90531494,28); exponent <= '1'; WHEN "1101011000" => manhi <= conv_std_logic_vector(2575099,24); manlo <= conv_std_logic_vector(230401190,28); exponent <= '1'; WHEN "1101011001" => manhi <= conv_std_logic_vector(2594007,24); manlo <= conv_std_logic_vector(224190477,28); exponent <= '1'; WHEN "1101011010" => manhi <= conv_std_logic_vector(2612934,24); manlo <= conv_std_logic_vector(76739795,28); exponent <= '1'; WHEN "1101011011" => manhi <= conv_std_logic_vector(2631879,24); manlo <= conv_std_logic_vector(61329773,28); exponent <= '1'; WHEN "1101011100" => manhi <= conv_std_logic_vector(2650842,24); manlo <= conv_std_logic_vector(182810317,28); exponent <= '1'; WHEN "1101011101" => manhi <= conv_std_logic_vector(2669824,24); manlo <= conv_std_logic_vector(177600614,28); exponent <= '1'; WHEN "1101011110" => manhi <= conv_std_logic_vector(2688825,24); manlo <= conv_std_logic_vector(50560052,28); exponent <= '1'; WHEN "1101011111" => manhi <= conv_std_logic_vector(2707844,24); manlo <= conv_std_logic_vector(74988222,28); exponent <= '1'; WHEN "1101100000" => manhi <= conv_std_logic_vector(2726881,24); manlo <= conv_std_logic_vector(255754012,28); exponent <= '1'; WHEN "1101100001" => manhi <= conv_std_logic_vector(2745938,24); manlo <= conv_std_logic_vector(60860155,28); exponent <= '1'; WHEN "1101100010" => manhi <= conv_std_logic_vector(2765013,24); manlo <= conv_std_logic_vector(32055969,28); exponent <= '1'; WHEN "1101100011" => manhi <= conv_std_logic_vector(2784106,24); manlo <= conv_std_logic_vector(174224628,28); exponent <= '1'; WHEN "1101100100" => manhi <= conv_std_logic_vector(2803218,24); manlo <= conv_std_logic_vector(223818618,28); exponent <= '1'; WHEN "1101100101" => manhi <= conv_std_logic_vector(2822349,24); manlo <= conv_std_logic_vector(185730660,28); exponent <= '1'; WHEN "1101100110" => manhi <= conv_std_logic_vector(2841499,24); manlo <= conv_std_logic_vector(64858254,28); exponent <= '1'; WHEN "1101100111" => manhi <= conv_std_logic_vector(2860667,24); manlo <= conv_std_logic_vector(134539142,28); exponent <= '1'; WHEN "1101101000" => manhi <= conv_std_logic_vector(2879854,24); manlo <= conv_std_logic_vector(131244940,28); exponent <= '1'; WHEN "1101101001" => manhi <= conv_std_logic_vector(2899060,24); manlo <= conv_std_logic_vector(59887520,28); exponent <= '1'; WHEN "1101101010" => manhi <= conv_std_logic_vector(2918284,24); manlo <= conv_std_logic_vector(193819006,28); exponent <= '1'; WHEN "1101101011" => manhi <= conv_std_logic_vector(2937528,24); manlo <= conv_std_logic_vector(1089957,28); exponent <= '1'; WHEN "1101101100" => manhi <= conv_std_logic_vector(2956790,24); manlo <= conv_std_logic_vector(23497566,28); exponent <= '1'; WHEN "1101101101" => manhi <= conv_std_logic_vector(2976070,24); manlo <= conv_std_logic_vector(265972927,28); exponent <= '1'; WHEN "1101101110" => manhi <= conv_std_logic_vector(2995370,24); manlo <= conv_std_logic_vector(196581040,28); exponent <= '1'; WHEN "1101101111" => manhi <= conv_std_logic_vector(3014689,24); manlo <= conv_std_logic_vector(88698094,28); exponent <= '1'; WHEN "1101110000" => manhi <= conv_std_logic_vector(3034026,24); manlo <= conv_std_logic_vector(215705108,28); exponent <= '1'; WHEN "1101110001" => manhi <= conv_std_logic_vector(3053383,24); manlo <= conv_std_logic_vector(45681562,28); exponent <= '1'; WHEN "1101110010" => manhi <= conv_std_logic_vector(3072758,24); manlo <= conv_std_logic_vector(120453600,28); exponent <= '1'; WHEN "1101110011" => manhi <= conv_std_logic_vector(3092152,24); manlo <= conv_std_logic_vector(176545836,28); exponent <= '1'; WHEN "1101110100" => manhi <= conv_std_logic_vector(3111565,24); manlo <= conv_std_logic_vector(218923189,28); exponent <= '1'; WHEN "1101110101" => manhi <= conv_std_logic_vector(3130997,24); manlo <= conv_std_logic_vector(252555427,28); exponent <= '1'; WHEN "1101110110" => manhi <= conv_std_logic_vector(3150449,24); manlo <= conv_std_logic_vector(13981719,28); exponent <= '1'; WHEN "1101110111" => manhi <= conv_std_logic_vector(3169919,24); manlo <= conv_std_logic_vector(45052462,28); exponent <= '1'; WHEN "1101111000" => manhi <= conv_std_logic_vector(3189408,24); manlo <= conv_std_logic_vector(82316549,28); exponent <= '1'; WHEN "1101111001" => manhi <= conv_std_logic_vector(3208916,24); manlo <= conv_std_logic_vector(130763202,28); exponent <= '1'; WHEN "1101111010" => manhi <= conv_std_logic_vector(3228443,24); manlo <= conv_std_logic_vector(195386513,28); exponent <= '1'; WHEN "1101111011" => manhi <= conv_std_logic_vector(3247990,24); manlo <= conv_std_logic_vector(12750002,28); exponent <= '1'; WHEN "1101111100" => manhi <= conv_std_logic_vector(3267555,24); manlo <= conv_std_logic_vector(124728439,28); exponent <= '1'; WHEN "1101111101" => manhi <= conv_std_logic_vector(3287139,24); manlo <= conv_std_logic_vector(267895114,28); exponent <= '1'; WHEN "1101111110" => manhi <= conv_std_logic_vector(3306743,24); manlo <= conv_std_logic_vector(178828213,28); exponent <= '1'; WHEN "1101111111" => manhi <= conv_std_logic_vector(3326366,24); manlo <= conv_std_logic_vector(130981732,28); exponent <= '1'; WHEN "1110000000" => manhi <= conv_std_logic_vector(3346008,24); manlo <= conv_std_logic_vector(129379112,28); exponent <= '1'; WHEN "1110000001" => manhi <= conv_std_logic_vector(3365669,24); manlo <= conv_std_logic_vector(179048704,28); exponent <= '1'; WHEN "1110000010" => manhi <= conv_std_logic_vector(3385350,24); manlo <= conv_std_logic_vector(16588318,28); exponent <= '1'; WHEN "1110000011" => manhi <= conv_std_logic_vector(3405049,24); manlo <= conv_std_logic_vector(183907046,28); exponent <= '1'; WHEN "1110000100" => manhi <= conv_std_logic_vector(3424768,24); manlo <= conv_std_logic_vector(149177079,28); exponent <= '1'; WHEN "1110000101" => manhi <= conv_std_logic_vector(3444506,24); manlo <= conv_std_logic_vector(185881906,28); exponent <= '1'; WHEN "1110000110" => manhi <= conv_std_logic_vector(3464264,24); manlo <= conv_std_logic_vector(30639033,28); exponent <= '1'; WHEN "1110000111" => manhi <= conv_std_logic_vector(3484040,24); manlo <= conv_std_logic_vector(225377274,28); exponent <= '1'; WHEN "1110001000" => manhi <= conv_std_logic_vector(3503836,24); manlo <= conv_std_logic_vector(238288557,28); exponent <= '1'; WHEN "1110001001" => manhi <= conv_std_logic_vector(3523652,24); manlo <= conv_std_logic_vector(74440673,28); exponent <= '1'; WHEN "1110001010" => manhi <= conv_std_logic_vector(3543487,24); manlo <= conv_std_logic_vector(7341816,28); exponent <= '1'; WHEN "1110001011" => manhi <= conv_std_logic_vector(3563341,24); manlo <= conv_std_logic_vector(42069684,28); exponent <= '1'; WHEN "1110001100" => manhi <= conv_std_logic_vector(3583214,24); manlo <= conv_std_logic_vector(183706934,28); exponent <= '1'; WHEN "1110001101" => manhi <= conv_std_logic_vector(3603107,24); manlo <= conv_std_logic_vector(168905734,28); exponent <= '1'; WHEN "1110001110" => manhi <= conv_std_logic_vector(3623020,24); manlo <= conv_std_logic_vector(2758677,28); exponent <= '1'; WHEN "1110001111" => manhi <= conv_std_logic_vector(3642951,24); manlo <= conv_std_logic_vector(227234245,28); exponent <= '1'; WHEN "1110010000" => manhi <= conv_std_logic_vector(3662903,24); manlo <= conv_std_logic_vector(42128622,28); exponent <= '1'; WHEN "1110010001" => manhi <= conv_std_logic_vector(3682873,24); manlo <= conv_std_logic_vector(257855711,28); exponent <= '1'; WHEN "1110010010" => manhi <= conv_std_logic_vector(3702864,24); manlo <= conv_std_logic_vector(74221670,28); exponent <= '1'; WHEN "1110010011" => manhi <= conv_std_logic_vector(3722874,24); manlo <= conv_std_logic_vector(33214933,28); exponent <= '1'; WHEN "1110010100" => manhi <= conv_std_logic_vector(3742903,24); manlo <= conv_std_logic_vector(139958020,28); exponent <= '1'; WHEN "1110010101" => manhi <= conv_std_logic_vector(3762952,24); manlo <= conv_std_logic_vector(131143002,28); exponent <= '1'; WHEN "1110010110" => manhi <= conv_std_logic_vector(3783021,24); manlo <= conv_std_logic_vector(11902416,28); exponent <= '1'; WHEN "1110010111" => manhi <= conv_std_logic_vector(3803109,24); manlo <= conv_std_logic_vector(55809266,28); exponent <= '1'; WHEN "1110011000" => manhi <= conv_std_logic_vector(3823216,24); manlo <= conv_std_logic_vector(268006125,28); exponent <= '1'; WHEN "1110011001" => manhi <= conv_std_logic_vector(3843344,24); manlo <= conv_std_logic_vector(116769675,28); exponent <= '1'; WHEN "1110011010" => manhi <= conv_std_logic_vector(3863491,24); manlo <= conv_std_logic_vector(144123451,28); exponent <= '1'; WHEN "1110011011" => manhi <= conv_std_logic_vector(3883658,24); manlo <= conv_std_logic_vector(86789657,28); exponent <= '1'; WHEN "1110011100" => manhi <= conv_std_logic_vector(3903844,24); manlo <= conv_std_logic_vector(218366446,28); exponent <= '1'; WHEN "1110011101" => manhi <= conv_std_logic_vector(3924051,24); manlo <= conv_std_logic_vector(7150648,28); exponent <= '1'; WHEN "1110011110" => manhi <= conv_std_logic_vector(3944276,24); manlo <= conv_std_logic_vector(263621422,28); exponent <= '1'; WHEN "1110011111" => manhi <= conv_std_logic_vector(3964522,24); manlo <= conv_std_logic_vector(187650244,28); exponent <= '1'; WHEN "1110100000" => manhi <= conv_std_logic_vector(3984788,24); manlo <= conv_std_logic_vector(52855476,28); exponent <= '1'; WHEN "1110100001" => manhi <= conv_std_logic_vector(4005073,24); manlo <= conv_std_logic_vector(132860541,28); exponent <= '1'; WHEN "1110100010" => manhi <= conv_std_logic_vector(4025378,24); manlo <= conv_std_logic_vector(164423019,28); exponent <= '1'; WHEN "1110100011" => manhi <= conv_std_logic_vector(4045703,24); manlo <= conv_std_logic_vector(152741021,28); exponent <= '1'; WHEN "1110100100" => manhi <= conv_std_logic_vector(4066048,24); manlo <= conv_std_logic_vector(103017737,28); exponent <= '1'; WHEN "1110100101" => manhi <= conv_std_logic_vector(4086413,24); manlo <= conv_std_logic_vector(20461438,28); exponent <= '1'; WHEN "1110100110" => manhi <= conv_std_logic_vector(4106797,24); manlo <= conv_std_logic_vector(178720944,28); exponent <= '1'; WHEN "1110100111" => manhi <= conv_std_logic_vector(4127202,24); manlo <= conv_std_logic_vector(46143798,28); exponent <= '1'; WHEN "1110101000" => manhi <= conv_std_logic_vector(4147626,24); manlo <= conv_std_logic_vector(164824464,28); exponent <= '1'; WHEN "1110101001" => manhi <= conv_std_logic_vector(4168071,24); manlo <= conv_std_logic_vector(3120689,28); exponent <= '1'; WHEN "1110101010" => manhi <= conv_std_logic_vector(4188535,24); manlo <= conv_std_logic_vector(103137152,28); exponent <= '1'; WHEN "1110101011" => manhi <= conv_std_logic_vector(4209019,24); manlo <= conv_std_logic_vector(201677275,28); exponent <= '1'; WHEN "1110101100" => manhi <= conv_std_logic_vector(4229524,24); manlo <= conv_std_logic_vector(35549602,28); exponent <= '1'; WHEN "1110101101" => manhi <= conv_std_logic_vector(4250048,24); manlo <= conv_std_logic_vector(146874166,28); exponent <= '1'; WHEN "1110101110" => manhi <= conv_std_logic_vector(4270593,24); manlo <= conv_std_logic_vector(4034305,28); exponent <= '1'; WHEN "1110101111" => manhi <= conv_std_logic_vector(4291157,24); manlo <= conv_std_logic_vector(149160317,28); exponent <= '1'; WHEN "1110110000" => manhi <= conv_std_logic_vector(4311742,24); manlo <= conv_std_logic_vector(50645812,28); exponent <= '1'; WHEN "1110110001" => manhi <= conv_std_logic_vector(4332346,24); manlo <= conv_std_logic_vector(250631368,28); exponent <= '1'; WHEN "1110110010" => manhi <= conv_std_logic_vector(4352971,24); manlo <= conv_std_logic_vector(217520889,28); exponent <= '1'; WHEN "1110110011" => manhi <= conv_std_logic_vector(4373616,24); manlo <= conv_std_logic_vector(225029798,28); exponent <= '1'; WHEN "1110110100" => manhi <= conv_std_logic_vector(4394282,24); manlo <= conv_std_logic_vector(10007770,28); exponent <= '1'; WHEN "1110110101" => manhi <= conv_std_logic_vector(4414967,24); manlo <= conv_std_logic_vector(114616005,28); exponent <= '1'; WHEN "1110110110" => manhi <= conv_std_logic_vector(4435673,24); manlo <= conv_std_logic_vector(7279052,28); exponent <= '1'; WHEN "1110110111" => manhi <= conv_std_logic_vector(4456398,24); manlo <= conv_std_logic_vector(230168458,28); exponent <= '1'; WHEN "1110111000" => manhi <= conv_std_logic_vector(4477144,24); manlo <= conv_std_logic_vector(251719124,28); exponent <= '1'; WHEN "1110111001" => manhi <= conv_std_logic_vector(4497911,24); manlo <= conv_std_logic_vector(77242046,28); exponent <= '1'; WHEN "1110111010" => manhi <= conv_std_logic_vector(4518697,24); manlo <= conv_std_logic_vector(248924323,28); exponent <= '1'; WHEN "1110111011" => manhi <= conv_std_logic_vector(4539504,24); manlo <= conv_std_logic_vector(235216422,28); exponent <= '1'; WHEN "1110111100" => manhi <= conv_std_logic_vector(4560332,24); manlo <= conv_std_logic_vector(41444923,28); exponent <= '1'; WHEN "1110111101" => manhi <= conv_std_logic_vector(4581179,24); manlo <= conv_std_logic_vector(209812522,28); exponent <= '1'; WHEN "1110111110" => manhi <= conv_std_logic_vector(4602047,24); manlo <= conv_std_logic_vector(208785300,28); exponent <= '1'; WHEN "1110111111" => manhi <= conv_std_logic_vector(4622936,24); manlo <= conv_std_logic_vector(43705464,28); exponent <= '1'; WHEN "1111000000" => manhi <= conv_std_logic_vector(4643844,24); manlo <= conv_std_logic_vector(256791352,28); exponent <= '1'; WHEN "1111000001" => manhi <= conv_std_logic_vector(4664774,24); manlo <= conv_std_logic_vector(48089250,28); exponent <= '1'; WHEN "1111000010" => manhi <= conv_std_logic_vector(4685723,24); manlo <= conv_std_logic_vector(228263405,28); exponent <= '1'; WHEN "1111000011" => manhi <= conv_std_logic_vector(4706693,24); manlo <= conv_std_logic_vector(265806023,28); exponent <= '1'; WHEN "1111000100" => manhi <= conv_std_logic_vector(4727684,24); manlo <= conv_std_logic_vector(166085460,28); exponent <= '1'; WHEN "1111000101" => manhi <= conv_std_logic_vector(4748695,24); manlo <= conv_std_logic_vector(202910772,28); exponent <= '1'; WHEN "1111000110" => manhi <= conv_std_logic_vector(4769727,24); manlo <= conv_std_logic_vector(113225356,28); exponent <= '1'; WHEN "1111000111" => manhi <= conv_std_logic_vector(4790779,24); manlo <= conv_std_logic_vector(170848774,28); exponent <= '1'; WHEN "1111001000" => manhi <= conv_std_logic_vector(4811852,24); manlo <= conv_std_logic_vector(112734938,28); exponent <= '1'; WHEN "1111001001" => manhi <= conv_std_logic_vector(4832945,24); manlo <= conv_std_logic_vector(212713936,28); exponent <= '1'; WHEN "1111001010" => manhi <= conv_std_logic_vector(4854059,24); manlo <= conv_std_logic_vector(207750218,28); exponent <= '1'; WHEN "1111001011" => manhi <= conv_std_logic_vector(4875194,24); manlo <= conv_std_logic_vector(103248961,28); exponent <= '1'; WHEN "1111001100" => manhi <= conv_std_logic_vector(4896349,24); manlo <= conv_std_logic_vector(173056083,28); exponent <= '1'; WHEN "1111001101" => manhi <= conv_std_logic_vector(4917525,24); manlo <= conv_std_logic_vector(154151876,28); exponent <= '1'; WHEN "1111001110" => manhi <= conv_std_logic_vector(4938722,24); manlo <= conv_std_logic_vector(51957376,28); exponent <= '1'; WHEN "1111001111" => manhi <= conv_std_logic_vector(4959939,24); manlo <= conv_std_logic_vector(140334376,28); exponent <= '1'; WHEN "1111010000" => manhi <= conv_std_logic_vector(4981177,24); manlo <= conv_std_logic_vector(156279056,28); exponent <= '1'; WHEN "1111010001" => manhi <= conv_std_logic_vector(5002436,24); manlo <= conv_std_logic_vector(105228360,28); exponent <= '1'; WHEN "1111010010" => manhi <= conv_std_logic_vector(5023715,24); manlo <= conv_std_logic_vector(261060000,28); exponent <= '1'; WHEN "1111010011" => manhi <= conv_std_logic_vector(5045016,24); manlo <= conv_std_logic_vector(92350636,28); exponent <= '1'; WHEN "1111010100" => manhi <= conv_std_logic_vector(5066337,24); manlo <= conv_std_logic_vector(141424076,28); exponent <= '1'; WHEN "1111010101" => manhi <= conv_std_logic_vector(5087679,24); manlo <= conv_std_logic_vector(145303087,28); exponent <= '1'; WHEN "1111010110" => manhi <= conv_std_logic_vector(5109042,24); manlo <= conv_std_logic_vector(109451226,28); exponent <= '1'; WHEN "1111010111" => manhi <= conv_std_logic_vector(5130426,24); manlo <= conv_std_logic_vector(39337386,28); exponent <= '1'; WHEN "1111011000" => manhi <= conv_std_logic_vector(5151830,24); manlo <= conv_std_logic_vector(208871261,28); exponent <= '1'; WHEN "1111011001" => manhi <= conv_std_logic_vector(5173256,24); manlo <= conv_std_logic_vector(86661526,28); exponent <= '1'; WHEN "1111011010" => manhi <= conv_std_logic_vector(5194702,24); manlo <= conv_std_logic_vector(215064032,28); exponent <= '1'; WHEN "1111011011" => manhi <= conv_std_logic_vector(5216170,24); manlo <= conv_std_logic_vector(62698166,28); exponent <= '1'; WHEN "1111011100" => manhi <= conv_std_logic_vector(5237658,24); manlo <= conv_std_logic_vector(171930504,28); exponent <= '1'; WHEN "1111011101" => manhi <= conv_std_logic_vector(5259168,24); manlo <= conv_std_logic_vector(11391165,28); exponent <= '1'; WHEN "1111011110" => manhi <= conv_std_logic_vector(5280698,24); manlo <= conv_std_logic_vector(123457470,28); exponent <= '1'; WHEN "1111011111" => manhi <= conv_std_logic_vector(5302249,24); manlo <= conv_std_logic_vector(245205748,28); exponent <= '1'; WHEN "1111100000" => manhi <= conv_std_logic_vector(5323822,24); manlo <= conv_std_logic_vector(113717718,28); exponent <= '1'; WHEN "1111100001" => manhi <= conv_std_logic_vector(5345416,24); manlo <= conv_std_logic_vector(2951399,28); exponent <= '1'; WHEN "1111100010" => manhi <= conv_std_logic_vector(5367030,24); manlo <= conv_std_logic_vector(186870204,28); exponent <= '1'; WHEN "1111100011" => manhi <= conv_std_logic_vector(5388666,24); manlo <= conv_std_logic_vector(134136582,28); exponent <= '1'; WHEN "1111100100" => manhi <= conv_std_logic_vector(5410323,24); manlo <= conv_std_logic_vector(118724754,28); exponent <= '1'; WHEN "1111100101" => manhi <= conv_std_logic_vector(5432001,24); manlo <= conv_std_logic_vector(146178900,28); exponent <= '1'; WHEN "1111100110" => manhi <= conv_std_logic_vector(5453700,24); manlo <= conv_std_logic_vector(222048612,28); exponent <= '1'; WHEN "1111100111" => manhi <= conv_std_logic_vector(5475421,24); manlo <= conv_std_logic_vector(83453453,28); exponent <= '1'; WHEN "1111101000" => manhi <= conv_std_logic_vector(5497163,24); manlo <= conv_std_logic_vector(4389322,28); exponent <= '1'; WHEN "1111101001" => manhi <= conv_std_logic_vector(5518925,24); manlo <= conv_std_logic_vector(258857552,28); exponent <= '1'; WHEN "1111101010" => manhi <= conv_std_logic_vector(5540710,24); manlo <= conv_std_logic_vector(47123091,28); exponent <= '1'; WHEN "1111101011" => manhi <= conv_std_logic_vector(5562515,24); manlo <= conv_std_logic_vector(180069064,28); exponent <= '1'; WHEN "1111101100" => manhi <= conv_std_logic_vector(5584342,24); manlo <= conv_std_logic_vector(126406768,28); exponent <= '1'; WHEN "1111101101" => manhi <= conv_std_logic_vector(5606190,24); manlo <= conv_std_logic_vector(160159320,28); exponent <= '1'; WHEN "1111101110" => manhi <= conv_std_logic_vector(5628060,24); manlo <= conv_std_logic_vector(18484384,28); exponent <= '1'; WHEN "1111101111" => manhi <= conv_std_logic_vector(5649950,24); manlo <= conv_std_logic_vector(243851457,28); exponent <= '1'; WHEN "1111110000" => manhi <= conv_std_logic_vector(5671863,24); manlo <= conv_std_logic_vector(36558227,28); exponent <= '1'; WHEN "1111110001" => manhi <= conv_std_logic_vector(5693796,24); manlo <= conv_std_logic_vector(207520592,28); exponent <= '1'; WHEN "1111110010" => manhi <= conv_std_logic_vector(5715751,24); manlo <= conv_std_logic_vector(225482653,28); exponent <= '1'; WHEN "1111110011" => manhi <= conv_std_logic_vector(5737728,24); manlo <= conv_std_logic_vector(96064906,28); exponent <= '1'; WHEN "1111110100" => manhi <= conv_std_logic_vector(5759726,24); manlo <= conv_std_logic_vector(93328797,28); exponent <= '1'; WHEN "1111110101" => manhi <= conv_std_logic_vector(5781745,24); manlo <= conv_std_logic_vector(222905812,28); exponent <= '1'; WHEN "1111110110" => manhi <= conv_std_logic_vector(5803786,24); manlo <= conv_std_logic_vector(221997482,28); exponent <= '1'; WHEN "1111110111" => manhi <= conv_std_logic_vector(5825849,24); manlo <= conv_std_logic_vector(96246303,28); exponent <= '1'; WHEN "1111111000" => manhi <= conv_std_logic_vector(5847933,24); manlo <= conv_std_logic_vector(119735740,28); exponent <= '1'; WHEN "1111111001" => manhi <= conv_std_logic_vector(5870039,24); manlo <= conv_std_logic_vector(29683863,28); exponent <= '1'; WHEN "1111111010" => manhi <= conv_std_logic_vector(5892166,24); manlo <= conv_std_logic_vector(100185179,28); exponent <= '1'; WHEN "1111111011" => manhi <= conv_std_logic_vector(5914315,24); manlo <= conv_std_logic_vector(68468812,28); exponent <= '1'; WHEN "1111111100" => manhi <= conv_std_logic_vector(5936485,24); manlo <= conv_std_logic_vector(208640332,28); exponent <= '1'; WHEN "1111111101" => manhi <= conv_std_logic_vector(5958677,24); manlo <= conv_std_logic_vector(257939938,28); exponent <= '1'; WHEN "1111111110" => manhi <= conv_std_logic_vector(5980891,24); manlo <= conv_std_logic_vector(222048827,28); exponent <= '1'; WHEN "1111111111" => manhi <= conv_std_logic_vector(6003127,24); manlo <= conv_std_logic_vector(106653752,28); exponent <= '1'; WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= '0'; END CASE; END PROCESS; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_cos_s5.vhd

10

397588

----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_cos_s5 -- VHDL created on Tue Mar 12 15:57:58 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_cos_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_cos_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllOWE_uid6_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid7_fpCosPiTest_q : std_logic_vector (22 downto 0); signal cstBias_uid22_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMwShift_uid23_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstBiasMwShiftM2_uid24_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstZwShiftP1_uid25_fpCosPiTest_q : std_logic_vector (13 downto 0); signal cstAllZwE_uid28_fpCosPiTest_q : std_logic_vector (7 downto 0); signal cstNaNwF_uid30_fpCosPiTest_q : std_logic_vector (22 downto 0); signal cstZmwFRRPwSM1_uid46_fpCosPiTest_q : std_logic_vector (61 downto 0); signal biasM1_uid60_fpCosPiTest_q : std_logic_vector (7 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_a : std_logic_vector (25 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_b : std_logic_vector (25 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_s1 : std_logic_vector (51 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_pr : UNSIGNED (51 downto 0); signal mul2xSinRes_uid68_fpCosPiTest_q : std_logic_vector (51 downto 0); signal InvCosXIsOneXRR_uid79_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCosXIsOneXRR_uid79_fpCosPiTest_q : std_logic_vector(0 downto 0); signal expSelector_uid88_fpCosPiTest_q : std_logic_vector(1 downto 0); signal InvCosXOne_uid92_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCosXOne_uid92_fpCosPiTest_q : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_c : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_d : std_logic_vector(0 downto 0); signal signRCond2_uid95_fpCosPiTest_q : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_c : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_d : std_logic_vector(0 downto 0); signal signRCond1_uid100_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid102_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid102_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvExc_N_uid103_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid103_fpCosPiTest_q : std_logic_vector(0 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_a : std_logic_vector(10 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_b : std_logic_vector(10 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_o : std_logic_vector (10 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal xBranch_uid132_rrx_uid32_fpCosPiTest_n : std_logic_vector (0 downto 0); signal ZerosGB_uid147_rrx_uid32_fpCosPiTest_q : std_logic_vector (26 downto 0); signal leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q : std_logic_vector (11 downto 0); signal leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q : std_logic_vector (2 downto 0); signal zs_uid177_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0); signal vCount_uid179_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid179_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid179_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal mO_uid180_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0); signal zs_uid185_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0); signal vCount_uid199_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid199_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid199_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (47 downto 0); signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0); signal leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (5 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid328_pT1_uid256_sinPiZPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_a : std_logic_vector (17 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (22 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 : std_logic_vector (40 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr : SIGNED (41 downto 0); signal prodXY_uid331_pT2_uid262_sinPiZPolyEval_q : std_logic_vector (40 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic; signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (39 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (39 downto 0); signal rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (39 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 : std_logic; signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia : std_logic_vector (37 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa : std_logic_vector (7 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab : std_logic_vector (7 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq : std_logic_vector (37 downto 0); signal rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q : std_logic_vector (37 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr : UNSIGNED (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr : UNSIGNED (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr : UNSIGNED (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a : std_logic_vector(81 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b : std_logic_vector(81 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o : std_logic_vector (81 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q : std_logic_vector (81 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid249_sinPiZTableGenerator_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid251_sinPiZTableGenerator_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid253_sinPiZTableGenerator_lutmem_q : std_logic_vector (12 downto 0); signal reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q : std_logic_vector (39 downto 0); signal reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (37 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q : std_logic_vector (26 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q : std_logic_vector (26 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q : std_logic_vector (26 downto 0); signal reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q : std_logic_vector (26 downto 0); signal reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (15 downto 0); signal reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0); signal reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (1 downto 0); signal reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (1 downto 0); signal reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (0 downto 0); signal reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (75 downto 0); signal reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q : std_logic_vector (75 downto 0); signal reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q : std_logic_vector (75 downto 0); signal reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q : std_logic_vector (75 downto 0); signal reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (49 downto 0); signal reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q : std_logic_vector (7 downto 0); signal reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q : std_logic_vector (64 downto 0); signal reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q : std_logic_vector (62 downto 0); signal reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q : std_logic_vector (0 downto 0); signal reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q : std_logic_vector (63 downto 0); signal reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q : std_logic_vector (64 downto 0); signal reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q : std_logic_vector (0 downto 0); signal reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q : std_logic_vector (61 downto 0); signal reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q : std_logic_vector (61 downto 0); signal reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (7 downto 0); signal reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q : std_logic_vector (3 downto 0); signal reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q : std_logic_vector (3 downto 0); signal reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q : std_logic_vector (0 downto 0); signal reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0); signal reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q : std_logic_vector (61 downto 0); signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q : std_logic_vector (20 downto 0); signal reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q : std_logic_vector (17 downto 0); signal reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q : std_logic_vector (22 downto 0); signal reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q : std_logic_vector (29 downto 0); signal reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q : std_logic_vector (25 downto 0); signal reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q : std_logic_vector (25 downto 0); signal reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q : std_logic_vector (5 downto 0); signal reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q : std_logic_vector (7 downto 0); signal reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q : std_logic_vector (1 downto 0); signal reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q : std_logic_vector (22 downto 0); signal reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q : std_logic_vector (0 downto 0); signal reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q : std_logic_vector (3 downto 0); signal reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q : std_logic_vector (7 downto 0); signal ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q : std_logic_vector (49 downto 0); signal ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q : std_logic_vector (62 downto 0); signal ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q : std_logic_vector (61 downto 0); signal ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q : std_logic_vector (61 downto 0); signal ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q : std_logic_vector (0 downto 0); signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (7 downto 0); signal ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (63 downto 0); signal ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (62 downto 0); signal ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q : std_logic_vector (61 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q : std_logic_vector (29 downto 0); signal ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q : std_logic_vector (31 downto 0); signal ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q : std_logic_vector (0 downto 0); signal ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q : std_logic_vector (0 downto 0); signal ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (57 downto 0); signal ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (53 downto 0); signal ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (49 downto 0); signal ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (60 downto 0); signal ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (59 downto 0); signal ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q : std_logic_vector (58 downto 0); signal ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q : std_logic_vector (0 downto 0); signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (67 downto 0); signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (59 downto 0); signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (51 downto 0); signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q : std_logic_vector (75 downto 0); signal ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q : std_logic_vector (0 downto 0); signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q : std_logic_vector (12 downto 0); signal ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q : std_logic_vector (53 downto 0); signal ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q : std_logic_vector (0 downto 0); signal ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q : std_logic_vector (1 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q : std_logic_vector (5 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q : std_logic_vector (1 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q : std_logic_vector (4 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 : std_logic; signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q : std_logic_vector (31 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q : signal is true; signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q : std_logic_vector (22 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 : std_logic; signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq : std_logic; signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q : std_logic_vector (4 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q : signal is true; signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (45 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (29 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (29 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (29 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 : std_logic; signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q : std_logic_vector (13 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q : signal is true; signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 : std_logic; signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q : std_logic_vector (61 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q : signal is true; signal ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (67 downto 0); signal ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (59 downto 0); signal ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q : std_logic_vector (51 downto 0); signal ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q : std_logic_vector (75 downto 0); signal ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q : std_logic_vector (12 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q : signal is true; signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 : std_logic; signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q : std_logic_vector (25 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i : unsigned(1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq : std_logic; signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q : std_logic_vector (2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q : signal is true; signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 : std_logic; signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q : std_logic_vector (1 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q : signal is true; signal yIsZero_uid45_fpCosPiTest_a : std_logic_vector(62 downto 0); signal yIsZero_uid45_fpCosPiTest_b : std_logic_vector(62 downto 0); signal yIsZero_uid45_fpCosPiTest_q : std_logic_vector(0 downto 0); signal pad_one_uid49_fpCosPiTest_q : std_logic_vector (63 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_a : std_logic_vector(67 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_b : std_logic_vector(67 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_o : std_logic_vector (67 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal cmpYToOneMinusY_uid51_fpCosPiTest_c : std_logic_vector (0 downto 0); signal leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal InvCmpYToOneMinusY_uid52_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCmpYToOneMinusY_uid52_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvYIsZero_uid94_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvYIsZero_uid94_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvIntXParity_uid98_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvIntXParity_uid98_fpCosPiTest_q : std_logic_vector(0 downto 0); signal oFracXRR_uid38_uid38_fpCosPiTest_q : std_logic_vector (50 downto 0); signal half_uid47_fpCosPiTest_q : std_logic_vector (62 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q : std_logic_vector (1 downto 0); signal exp_uid11_fpCosPiTest_in : std_logic_vector (30 downto 0); signal exp_uid11_fpCosPiTest_b : std_logic_vector (7 downto 0); signal frac_uid13_fpCosPiTest_in : std_logic_vector (22 downto 0); signal frac_uid13_fpCosPiTest_b : std_logic_vector (22 downto 0); signal expFracX_uid107_px_uid31_fpCosPiTest_in : std_logic_vector (30 downto 0); signal expFracX_uid107_px_uid31_fpCosPiTest_b : std_logic_vector (30 downto 0); signal expXIsMax_uid12_fpCosPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid12_fpCosPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid12_fpCosPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid14_fpCosPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid14_fpCosPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid14_fpCosPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid15_fpCosPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid15_fpCosPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid15_fpCosPiTest_q : std_logic_vector(0 downto 0); signal cosXIsOne_uid36_fpCosPiTest_a : std_logic_vector(10 downto 0); signal cosXIsOne_uid36_fpCosPiTest_b : std_logic_vector(10 downto 0); signal cosXIsOne_uid36_fpCosPiTest_o : std_logic_vector (10 downto 0); signal cosXIsOne_uid36_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal cosXIsOne_uid36_fpCosPiTest_n : std_logic_vector (0 downto 0); signal yIsHalf_uid48_fpCosPiTest_a : std_logic_vector(62 downto 0); signal yIsHalf_uid48_fpCosPiTest_b : std_logic_vector(62 downto 0); signal yIsHalf_uid48_fpCosPiTest_q : std_logic_vector(0 downto 0); signal oneMinusY_uid49_fpCosPiTest_a : std_logic_vector(64 downto 0); signal oneMinusY_uid49_fpCosPiTest_b : std_logic_vector(64 downto 0); signal oneMinusY_uid49_fpCosPiTest_o : std_logic_vector (64 downto 0); signal oneMinusY_uid49_fpCosPiTest_q : std_logic_vector (64 downto 0); signal z_uid55_fpCosPiTest_s : std_logic_vector (0 downto 0); signal z_uid55_fpCosPiTest_q : std_logic_vector (61 downto 0); signal expHardCase_uid61_fpCosPiTest_a : std_logic_vector(8 downto 0); signal expHardCase_uid61_fpCosPiTest_b : std_logic_vector(8 downto 0); signal expHardCase_uid61_fpCosPiTest_o : std_logic_vector (8 downto 0); signal expHardCase_uid61_fpCosPiTest_q : std_logic_vector (8 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_a : std_logic_vector(0 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_b : std_logic_vector(0 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_c : std_logic_vector(0 downto 0); signal yHalfCosNotOne_uid81_fpCosPiTest_q : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_a : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_b : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_c : std_logic_vector(0 downto 0); signal excZOrCosOne_uid83_fpCosPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc_uid85_fpCosPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid85_fpCosPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid90_fpCosPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid90_fpCosPiTest_q : std_logic_vector (7 downto 0); signal signR_uid101_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signR_uid101_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signR_uid101_fpCosPiTest_q : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_a : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_b : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_c : std_logic_vector(0 downto 0); signal signRNotNaNOrInf_uid104_fpCosPiTest_q : std_logic_vector(0 downto 0); signal finalExp_uid150_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal finalExp_uid150_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0); signal vCount_uid193_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid193_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid193_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid196_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (7 downto 0); signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid202_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (3 downto 0); signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0); signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (7 downto 0); signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q : std_logic_vector(0 downto 0); signal extendedFracX_uid41_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal normBit_uid69_fpCosPiTest_in : std_logic_vector (51 downto 0); signal normBit_uid69_fpCosPiTest_b : std_logic_vector (0 downto 0); signal highRes_uid70_fpCosPiTest_in : std_logic_vector (50 downto 0); signal highRes_uid70_fpCosPiTest_b : std_logic_vector (23 downto 0); signal lowRes_uid71_fpCosPiTest_in : std_logic_vector (49 downto 0); signal lowRes_uid71_fpCosPiTest_b : std_logic_vector (23 downto 0); signal fracXRExt_uid148_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0); signal leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal cStage_uid182_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0); signal leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in : std_logic_vector (40 downto 0); signal prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b : std_logic_vector (23 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_0_q : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int : std_logic_vector (80 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_1_q : std_logic_vector (80 downto 0); signal os_uid137_rrx_uid32_fpCosPiTest_q : std_logic_vector (77 downto 0); signal finalFrac_uid149_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal finalFrac_uid149_rrx_uid32_fpCosPiTest_q : std_logic_vector (49 downto 0); signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal join_uid84_fpCosPiTest_q : std_logic_vector (1 downto 0); signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q : std_logic_vector (61 downto 0); signal join_uid86_fpCosPiTest_q : std_logic_vector (2 downto 0); signal expSelBits_uid87_fpCosPiTest_q : std_logic_vector (3 downto 0); signal cosXR_uid105_fpCosPiTest_q : std_logic_vector (31 downto 0); signal RRangeRed_uid151_rrx_uid32_fpCosPiTest_q : std_logic_vector (58 downto 0); signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid184_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (31 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int : std_logic_vector (107 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_align_2_q : std_logic_vector (107 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a : std_logic_vector(4 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b : std_logic_vector(4 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal fracX_uid128_rrx_uid32_fpCosPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid128_rrx_uid32_fpCosPiTest_b : std_logic_vector (22 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a : std_logic_vector(4 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b : std_logic_vector(4 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a : std_logic_vector(2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b : std_logic_vector(2 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b : std_logic_vector(0 downto 0); signal ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q : std_logic_vector(0 downto 0); signal R_uid108_px_uid31_fpCosPiTest_q : std_logic_vector (31 downto 0); signal InvFracXIsZero_uid16_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid16_fpCosPiTest_q : std_logic_vector(0 downto 0); signal InvCosXIsOne_uid80_fpCosPiTest_a : std_logic_vector(0 downto 0); signal InvCosXIsOne_uid80_fpCosPiTest_q : std_logic_vector(0 downto 0); signal oMyBottom_uid53_fpCosPiTest_in : std_logic_vector (61 downto 0); signal oMyBottom_uid53_fpCosPiTest_b : std_logic_vector (61 downto 0); signal zAddr_uid64_fpCosPiTest_in : std_logic_vector (61 downto 0); signal zAddr_uid64_fpCosPiTest_b : std_logic_vector (7 downto 0); signal zPPolyEval_uid65_fpCosPiTest_in : std_logic_vector (53 downto 0); signal zPPolyEval_uid65_fpCosPiTest_b : std_logic_vector (17 downto 0); signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (61 downto 0); signal rVStage_uid178_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid181_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (29 downto 0); signal vStage_uid181_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (29 downto 0); signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (45 downto 0); signal X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (45 downto 0); signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (13 downto 0); signal X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (13 downto 0); signal expP_uid62_fpCosPiTest_in : std_logic_vector (7 downto 0); signal expP_uid62_fpCosPiTest_b : std_logic_vector (7 downto 0); signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid198_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid200_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid200_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (3 downto 0); signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid204_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid206_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid206_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (1 downto 0); signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0); signal vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (3 downto 0); signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0); signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0); signal LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (74 downto 0); signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_in : std_logic_vector (60 downto 0); signal X60dto0_uid155_fxpX_uid42_fpCosPiTest_b : std_logic_vector (60 downto 0); signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_in : std_logic_vector (56 downto 0); signal X56dto0_uid158_fxpX_uid42_fpCosPiTest_b : std_logic_vector (56 downto 0); signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_in : std_logic_vector (52 downto 0); signal X52dto0_uid161_fxpX_uid42_fpCosPiTest_b : std_logic_vector (52 downto 0); signal fracRCompPreRnd_uid72_fpCosPiTest_s : std_logic_vector (0 downto 0); signal fracRCompPreRnd_uid72_fpCosPiTest_q : std_logic_vector (23 downto 0); signal rndOp_uid74_uid75_fpCosPiTest_q : std_logic_vector (24 downto 0); signal lowRangeB_uid257_sinPiZPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid257_sinPiZPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid258_sinPiZPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid258_sinPiZPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid263_sinPiZPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid263_sinPiZPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid264_sinPiZPolyEval_in : std_logic_vector (23 downto 0); signal highBBits_uid264_sinPiZPolyEval_b : std_logic_vector (21 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_in : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_0_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_in : std_logic_vector (53 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_1_b : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_in : std_logic_vector (80 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_a_2_b : std_logic_vector (26 downto 0); signal intXParity_uid43_fpCosPiTest_in : std_logic_vector (64 downto 0); signal intXParity_uid43_fpCosPiTest_b : std_logic_vector (0 downto 0); signal y_uid44_fpCosPiTest_in : std_logic_vector (63 downto 0); signal y_uid44_fpCosPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (57 downto 0); signal LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (57 downto 0); signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (53 downto 0); signal LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (53 downto 0); signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (49 downto 0); signal LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (49 downto 0); signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (60 downto 0); signal LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (60 downto 0); signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (59 downto 0); signal LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (59 downto 0); signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (58 downto 0); signal LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (58 downto 0); signal p_uid59_fpCosPiTest_in : std_logic_vector (61 downto 0); signal p_uid59_fpCosPiTest_b : std_logic_vector (25 downto 0); signal expXRR_uid34_fpCosPiTest_in : std_logic_vector (57 downto 0); signal expXRR_uid34_fpCosPiTest_b : std_logic_vector (7 downto 0); signal fracXRR_uid35_fpCosPiTest_in : std_logic_vector (49 downto 0); signal fracXRR_uid35_fpCosPiTest_b : std_logic_vector (49 downto 0); signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (31 downto 0); signal rVStage_uid186_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid188_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0); signal vStage_uid188_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (15 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a : std_logic_vector(108 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b : std_logic_vector(108 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o : std_logic_vector (108 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q : std_logic_vector (108 downto 0); signal oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q : std_logic_vector (23 downto 0); signal expX_uid127_rrx_uid32_fpCosPiTest_in : std_logic_vector (30 downto 0); signal expX_uid127_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal exc_N_uid17_fpCosPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid17_fpCosPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid17_fpCosPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid255_sinPiZPolyEval_in : std_logic_vector (17 downto 0); signal yT1_uid255_sinPiZPolyEval_b : std_logic_vector (12 downto 0); signal vCount_uid205_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid205_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid205_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid208_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (1 downto 0); signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (3 downto 0); signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q : std_logic_vector (31 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_a : std_logic_vector(32 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_b : std_logic_vector(32 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_o : std_logic_vector (32 downto 0); signal expRCompFracRComp_uid76_fpCosPiTest_q : std_logic_vector (32 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_a : std_logic_vector(21 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_b : std_logic_vector(21 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_o : std_logic_vector (21 downto 0); signal sumAHighB_uid259_sinPiZPolyEval_q : std_logic_vector (21 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid265_sinPiZPolyEval_q : std_logic_vector (30 downto 0); signal yBottom_uid54_fpCosPiTest_in : std_logic_vector (61 downto 0); signal yBottom_uid54_fpCosPiTest_b : std_logic_vector (61 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_a : std_logic_vector(11 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_b : std_logic_vector(11 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_o : std_logic_vector (11 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_cin : std_logic_vector (0 downto 0); signal cosXIsOneXRR_uid37_fpCosPiTest_n : std_logic_vector (0 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_a : std_logic_vector(10 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_b : std_logic_vector(10 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_o : std_logic_vector (10 downto 0); signal fxpXShiftValExt_uid39_fpCosPiTest_q : std_logic_vector (9 downto 0); signal vCount_uid187_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid187_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid187_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid190_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (15 downto 0); signal multFracBits_uid140_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0); signal multFracBits_uid140_rrx_uid32_fpCosPiTest_b : std_logic_vector (75 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_in : std_logic_vector (26 downto 0); signal prod_uid139_rrx_uid32_fpCosPiTest_b_0_b : std_logic_vector (26 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0); signal expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0); signal excRNaN_uid82_fpCosPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid82_fpCosPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid82_fpCosPiTest_q : std_logic_vector(0 downto 0); signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (1 downto 0); signal rVStage_uid210_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (0 downto 0); signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (3 downto 0); signal rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (1 downto 0); signal vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (4 downto 0); signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (0 downto 0); signal leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q : std_logic_vector (64 downto 0); signal fracRComp_uid77_fpCosPiTest_in : std_logic_vector (23 downto 0); signal fracRComp_uid77_fpCosPiTest_b : std_logic_vector (22 downto 0); signal expRComp_uid78_fpCosPiTest_in : std_logic_vector (31 downto 0); signal expRComp_uid78_fpCosPiTest_b : std_logic_vector (7 downto 0); signal s1_uid257_uid260_sinPiZPolyEval_q : std_logic_vector (22 downto 0); signal s2_uid263_uid266_sinPiZPolyEval_q : std_logic_vector (32 downto 0); signal cosXOne_uid91_fpCosPiTest_a : std_logic_vector(0 downto 0); signal cosXOne_uid91_fpCosPiTest_b : std_logic_vector(0 downto 0); signal cosXOne_uid91_fpCosPiTest_q : std_logic_vector(0 downto 0); signal fxpXShiftVal_uid40_fpCosPiTest_in : std_logic_vector (3 downto 0); signal fxpXShiftVal_uid40_fpCosPiTest_b : std_logic_vector (3 downto 0); signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (15 downto 0); signal rVStage_uid192_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid194_lzcZ_uid57_fpCosPiTest_in : std_logic_vector (7 downto 0); signal vStage_uid194_lzcZ_uid57_fpCosPiTest_b : std_logic_vector (7 downto 0); signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in : std_logic_vector (75 downto 0); signal multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b : std_logic_vector (29 downto 0); signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (67 downto 0); signal X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (67 downto 0); signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (59 downto 0); signal X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (59 downto 0); signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (51 downto 0); signal X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (51 downto 0); signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal vCount_uid211_lzcZ_uid57_fpCosPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid211_lzcZ_uid57_fpCosPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid211_lzcZ_uid57_fpCosPiTest_q : std_logic_vector(0 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a : std_logic_vector(8 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b : std_logic_vector(8 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o : std_logic_vector (8 downto 0); signal expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q : std_logic_vector (8 downto 0); signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (4 downto 0); signal leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (2 downto 0); signal leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (0 downto 0); signal leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (0 downto 0); signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_in : std_logic_vector (74 downto 0); signal fracCompOut_uid144_rrx_uid32_fpCosPiTest_b : std_logic_vector (49 downto 0); signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in : std_logic_vector (63 downto 0); signal LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b : std_logic_vector (63 downto 0); signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in : std_logic_vector (62 downto 0); signal LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b : std_logic_vector (62 downto 0); signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in : std_logic_vector (61 downto 0); signal LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b : std_logic_vector (61 downto 0); signal fxpSinRes_uid67_fpCosPiTest_in : std_logic_vector (30 downto 0); signal fxpSinRes_uid67_fpCosPiTest_b : std_logic_vector (25 downto 0); signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b : std_logic_vector (1 downto 0); signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (29 downto 0); signal rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in : std_logic_vector (13 downto 0); signal vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b : std_logic_vector (13 downto 0); signal r_uid212_lzcZ_uid57_fpCosPiTest_q : std_logic_vector (5 downto 0); signal expCompOut_uid146_rrx_uid32_fpCosPiTest_in : std_logic_vector (7 downto 0); signal expCompOut_uid146_rrx_uid32_fpCosPiTest_b : std_logic_vector (7 downto 0); signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q : std_logic_vector (15 downto 0); signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (5 downto 0); signal leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b : std_logic_vector (1 downto 0); signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (73 downto 0); signal LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (73 downto 0); signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (71 downto 0); signal LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (71 downto 0); signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in : std_logic_vector (69 downto 0); signal LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b : std_logic_vector (69 downto 0); signal leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); signal leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q : std_logic_vector (75 downto 0); begin --xIn(GPIN,3)@0 --GND(CONSTANT,0) GND_q <= "0"; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable(LOGICAL,823) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a <= en; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q <= not ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_a; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor(LOGICAL,874) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q <= not (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_a or ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_b); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top(CONSTANT,870) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q <= "01010"; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp(LOGICAL,871) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_mem_top_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q); ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q <= "1" when ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_a = ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_b else "0"; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg(REG,872) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmp_q; END IF; END IF; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena(REG,875) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_nor_q = "1") THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd(LOGICAL,876) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_sticky_ena_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b <= en; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_a and ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_b; --expFracX_uid107_px_uid31_fpCosPiTest(BITSELECT,106)@0 expFracX_uid107_px_uid31_fpCosPiTest_in <= a(30 downto 0); expFracX_uid107_px_uid31_fpCosPiTest_b <= expFracX_uid107_px_uid31_fpCosPiTest_in(30 downto 0); --R_uid108_px_uid31_fpCosPiTest(BITJOIN,107)@0 R_uid108_px_uid31_fpCosPiTest_q <= GND_q & expFracX_uid107_px_uid31_fpCosPiTest_b; --expX_uid127_rrx_uid32_fpCosPiTest(BITSELECT,126)@0 expX_uid127_rrx_uid32_fpCosPiTest_in <= R_uid108_px_uid31_fpCosPiTest_q(30 downto 0); expX_uid127_rrx_uid32_fpCosPiTest_b <= expX_uid127_rrx_uid32_fpCosPiTest_in(30 downto 23); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg(DELAY,864) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expX_uid127_rrx_uid32_fpCosPiTest_b, xout => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt(COUNTER,866) -- every=1, low=0, high=10, step=1, init=1 ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i = 9 THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_eq = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i - 10; ELSE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_i,4)); --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg(REG,867) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux(MUX,868) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s <= en; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux: PROCESS (ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q) BEGIN CASE ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_s IS WHEN "0" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q; WHEN "1" => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem(DUALMEM,865) ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_inputreg_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdreg_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_rdmux_q; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 11, width_b => 8, widthad_b => 4, numwords_b => 11, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq, address_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_aa, data_a => ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_ia ); ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_reset0 <= areset; ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_iq(7 downto 0); --zs_uid185_lzcZ_uid57_fpCosPiTest(CONSTANT,184) zs_uid185_lzcZ_uid57_fpCosPiTest_q <= "0000000000000000"; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor(LOGICAL,848) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q <= not (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_a or ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_b); --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg(REG,846) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena(REG,849) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_nor_q = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd(LOGICAL,850) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_sticky_ena_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b <= en; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_a and ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_b; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg(DELAY,840) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => R_uid108_px_uid31_fpCosPiTest_q, xout => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt(COUNTER,842) -- every=1, low=0, high=1, step=1, init=1 ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_i,1)); --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg(REG,843) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux(MUX,844) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s <= en; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux: PROCESS (ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q, ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q) BEGIN CASE ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_s IS WHEN "0" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; WHEN "1" => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem(DUALMEM,841) ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_inputreg_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 32, widthad_a => 1, numwords_a => 2, width_b => 32, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq, address_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_aa, data_a => ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_ia ); ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_reset0 <= areset; ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_iq(31 downto 0); --fracX_uid128_rrx_uid32_fpCosPiTest(BITSELECT,127)@4 fracX_uid128_rrx_uid32_fpCosPiTest_in <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_mem_q(22 downto 0); fracX_uid128_rrx_uid32_fpCosPiTest_b <= fracX_uid128_rrx_uid32_fpCosPiTest_in(22 downto 0); --oFracX_uid138_uid138_rrx_uid32_fpCosPiTest(BITJOIN,137)@4 oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q <= VCC_q & fracX_uid128_rrx_uid32_fpCosPiTest_b; --prod_uid139_rrx_uid32_fpCosPiTest_b_0(BITSELECT,338)@4 prod_uid139_rrx_uid32_fpCosPiTest_b_0_in <= STD_LOGIC_VECTOR("000" & oFracX_uid138_uid138_rrx_uid32_fpCosPiTest_q); prod_uid139_rrx_uid32_fpCosPiTest_b_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_in(26 downto 0); --reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1(REG,355)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_b_0_b; END IF; END IF; END PROCESS; --cstBiasMwShift_uid23_fpCosPiTest(CONSTANT,22) cstBiasMwShift_uid23_fpCosPiTest_q <= "01110011"; --expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest(SUB,132)@0 expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid127_rrx_uid32_fpCosPiTest_b); expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasMwShift_uid23_fpCosPiTest_q); expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_b)); expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_o(8 downto 0); --expXTableAddr_uid134_rrx_uid32_fpCosPiTest(BITSELECT,133)@0 expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in <= expXTableAddrExt_uid133_rrx_uid32_fpCosPiTest_q(7 downto 0); expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_in(7 downto 0); --reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0(REG,350)@0 reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q <= expXTableAddr_uid134_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,334)@1 rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0'); rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0'); rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q; rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 38, widthad_a => 8, numwords_a => 140, width_b => 38, widthad_b => 8, numwords_b => 140, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0, clock0 => clk, address_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ab, -- data_b => (others => '0'), q_b => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq, address_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_aa, data_a => rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_ia ); rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset; rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_iq(37 downto 0); --reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1(REG,353)@3 reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= "00000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q <= rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_q; END IF; END IF; END PROCESS; --rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem(DUALMEM,333)@1 rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia <= (others => '0'); rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa <= (others => '0'); rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab <= reg_expXTableAddr_uid134_rrx_uid32_fpCosPiTest_0_to_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_q; rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 40, widthad_a => 8, numwords_a => 140, width_b => 40, widthad_b => 8, numwords_b => 140, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0, clock0 => clk, address_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ab, -- data_b => (others => '0'), q_b => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq, address_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_aa, data_a => rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_ia ); rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_reset0 <= areset; rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_iq(39 downto 0); --reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0(REG,352)@3 reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q <= rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_q; END IF; END IF; END PROCESS; --os_uid137_rrx_uid32_fpCosPiTest(BITJOIN,136)@4 os_uid137_rrx_uid32_fpCosPiTest_q <= reg_rrTable_uid136_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_1_q & reg_rrTable_uid135_rrx_uid32_fpCosPiTest_lutmem_0_to_os_uid137_rrx_uid32_fpCosPiTest_0_q; --prod_uid139_rrx_uid32_fpCosPiTest_a_2(BITSELECT,337)@4 prod_uid139_rrx_uid32_fpCosPiTest_a_2_in <= STD_LOGIC_VECTOR("000" & os_uid137_rrx_uid32_fpCosPiTest_q); prod_uid139_rrx_uid32_fpCosPiTest_a_2_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_in(80 downto 54); --reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0(REG,358)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_2_b; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_a2_b0(MULT,341)@5 prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b); prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_2_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_0_q; prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q; prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_pr); END IF; END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_a2_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_s1; END IF; END IF; END PROCESS; --ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a(DELAY,736)@8 ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a : dspba_delay GENERIC MAP ( width => 54, depth => 1 ) PORT MAP ( xin => prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q, xout => ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q, ena => en(0), clk => clk, aclr => areset ); --prod_uid139_rrx_uid32_fpCosPiTest_align_2(BITSHIFT,344)@9 prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int <= ld_prod_uid139_rrx_uid32_fpCosPiTest_a2_b0_q_to_prod_uid139_rrx_uid32_fpCosPiTest_align_2_a_q & "000000000000000000000000000000000000000000000000000000"; prod_uid139_rrx_uid32_fpCosPiTest_align_2_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_2_q_int(107 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_a_1(BITSELECT,336)@4 prod_uid139_rrx_uid32_fpCosPiTest_a_1_in <= os_uid137_rrx_uid32_fpCosPiTest_q(53 downto 0); prod_uid139_rrx_uid32_fpCosPiTest_a_1_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_in(53 downto 27); --reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0(REG,356)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_1_b; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_a1_b0(MULT,340)@5 prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b); prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_1_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_0_q; prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q; prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_pr); END IF; END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_a1_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_s1; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_align_1(BITSHIFT,343)@8 prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a1_b0_q & "000000000000000000000000000"; prod_uid139_rrx_uid32_fpCosPiTest_align_1_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_1_q_int(80 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_a_0(BITSELECT,335)@4 prod_uid139_rrx_uid32_fpCosPiTest_a_0_in <= os_uid137_rrx_uid32_fpCosPiTest_q(26 downto 0); prod_uid139_rrx_uid32_fpCosPiTest_a_0_b <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_in(26 downto 0); --reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0(REG,354)@4 reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= "000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a_0_b; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_a0_b0(MULT,339)@5 prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr <= UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a) * UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b); prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= (others => '0'); prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_a <= reg_prod_uid139_rrx_uid32_fpCosPiTest_a_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_0_q; prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_b <= reg_prod_uid139_rrx_uid32_fpCosPiTest_b_0_0_to_prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_1_q; prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1 <= STD_LOGIC_VECTOR(prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_pr); END IF; END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_a0_b0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_s1; END IF; END IF; END PROCESS; --prod_uid139_rrx_uid32_fpCosPiTest_align_0(BITSHIFT,342)@8 prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int <= prod_uid139_rrx_uid32_fpCosPiTest_a0_b0_q; prod_uid139_rrx_uid32_fpCosPiTest_align_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_align_0_q_int(53 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0(ADD,345)@8 prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a <= STD_LOGIC_VECTOR("0000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_align_0_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_1_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_b)); END IF; END PROCESS; prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_o(81 downto 0); --prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0(ADD,346)@9 prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a <= STD_LOGIC_VECTOR("000000000000000000000000000" & prod_uid139_rrx_uid32_fpCosPiTest_result_add_0_0_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b <= STD_LOGIC_VECTOR("0" & prod_uid139_rrx_uid32_fpCosPiTest_align_2_q); prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o <= STD_LOGIC_VECTOR(UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_a) + UNSIGNED(prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_b)); prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_o(108 downto 0); --multFracBits_uid140_rrx_uid32_fpCosPiTest(BITSELECT,139)@9 multFracBits_uid140_rrx_uid32_fpCosPiTest_in <= prod_uid139_rrx_uid32_fpCosPiTest_result_add_1_0_q(75 downto 0); multFracBits_uid140_rrx_uid32_fpCosPiTest_b <= multFracBits_uid140_rrx_uid32_fpCosPiTest_in(75 downto 0); --multFracBitsTop_uid141_rrx_uid32_fpCosPiTest(BITSELECT,140)@9 multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b; multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_in(75 downto 46); --rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,268)@9 rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b; rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_in(29 downto 14); --reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1(REG,360)@9 reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q <= rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,269)@10 vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q; vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q; vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0"; --ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a(DELAY,762)@10 ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4(REG,368)@11 reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q <= ld_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_a_q; END IF; END IF; END PROCESS; --cstAllZwE_uid28_fpCosPiTest(CONSTANT,27) cstAllZwE_uid28_fpCosPiTest_q <= "00000000"; --vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,271)@9 vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in <= multFracBitsTop_uid141_rrx_uid32_fpCosPiTest_b(13 downto 0); vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_in(13 downto 0); --mO_uid180_lzcZ_uid57_fpCosPiTest(CONSTANT,179) mO_uid180_lzcZ_uid57_fpCosPiTest_q <= "11"; --cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,272)@9 cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid272_zCount_uid142_rrx_uid32_fpCosPiTest_b & mO_uid180_lzcZ_uid57_fpCosPiTest_q; --reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,362)@9 reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,274)@10 vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q, reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q) BEGIN CASE vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid269_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_1_q; WHEN "1" => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_cStage_uid273_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,276)@10 rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_in(15 downto 8); --vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,277)@10 vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q; vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1"; ELSE vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d(DELAY,684)@11 ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q, xout => ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest(CONSTANT,153) leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q <= "0000"; --vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,278)@10 vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid275_zCount_uid142_rrx_uid32_fpCosPiTest_q(7 downto 0); vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 0); --reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,364)@10 reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,363)@10 reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,280)@11 vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q) BEGIN CASE vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid277_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid279_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,282)@11 rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_in(7 downto 4); --vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,283)@11 vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0"; --reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,367)@11 reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest(CONSTANT,167) leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q <= "00"; --vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,284)@11 vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid281_zCount_uid142_rrx_uid32_fpCosPiTest_q(3 downto 0); vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 0); --vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,286)@11 vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b, vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b) BEGIN CASE vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= rVStage_uid283_zCount_uid142_rrx_uid32_fpCosPiTest_b; WHEN "1" => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= vStage_uid285_zCount_uid142_rrx_uid32_fpCosPiTest_b; WHEN OTHERS => vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,288)@11 rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_in(3 downto 2); --vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,289)@11 vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_b) THEN vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1"; ELSE vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,290)@11 vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid287_zCount_uid142_rrx_uid32_fpCosPiTest_q(1 downto 0); vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 0); --reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3(REG,366)@11 reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q <= vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2(REG,365)@11 reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q <= rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest(MUX,292)@12 vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s <= vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q; vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest: PROCESS (vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s, en, reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q, reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q) BEGIN CASE vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_s IS WHEN "0" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_rVStage_uid289_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vStage_uid291_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest(BITSELECT,294)@12 rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in <= vStagei_uid293_zCount_uid142_rrx_uid32_fpCosPiTest_q; rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_in(1 downto 1); --vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest(LOGICAL,295)@12 vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a <= rVStage_uid295_zCount_uid142_rrx_uid32_fpCosPiTest_b; vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b <= GND_q; vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q <= "1" when vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_a = vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_b else "0"; --r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest(BITJOIN,296)@12 r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q <= reg_vCount_uid270_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_4_q & ld_vCount_uid278_zCount_uid142_rrx_uid32_fpCosPiTest_q_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_d_q & reg_vCount_uid284_zCount_uid142_rrx_uid32_fpCosPiTest_0_to_r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_2_q & vCount_uid290_zCount_uid142_rrx_uid32_fpCosPiTest_q & vCount_uid296_zCount_uid142_rrx_uid32_fpCosPiTest_q; --biasM1_uid60_fpCosPiTest(CONSTANT,59) biasM1_uid60_fpCosPiTest_q <= "01111110"; --expCompOutExt_uid145_rrx_uid32_fpCosPiTest(SUB,144)@12 expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q); expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q); expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_a) - UNSIGNED(expCompOutExt_uid145_rrx_uid32_fpCosPiTest_b)); expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_o(8 downto 0); --expCompOut_uid146_rrx_uid32_fpCosPiTest(BITSELECT,145)@12 expCompOut_uid146_rrx_uid32_fpCosPiTest_in <= expCompOutExt_uid145_rrx_uid32_fpCosPiTest_q(7 downto 0); expCompOut_uid146_rrx_uid32_fpCosPiTest_b <= expCompOut_uid146_rrx_uid32_fpCosPiTest_in(7 downto 0); --reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2(REG,375)@12 reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q <= expCompOut_uid146_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --xBranch_uid132_rrx_uid32_fpCosPiTest(COMPARE,131)@0 xBranch_uid132_rrx_uid32_fpCosPiTest_cin <= GND_q; xBranch_uid132_rrx_uid32_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0'; xBranch_uid132_rrx_uid32_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid127_rrx_uid32_fpCosPiTest_b) & xBranch_uid132_rrx_uid32_fpCosPiTest_cin(0); xBranch_uid132_rrx_uid32_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN xBranch_uid132_rrx_uid32_fpCosPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN xBranch_uid132_rrx_uid32_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_a) - UNSIGNED(xBranch_uid132_rrx_uid32_fpCosPiTest_b)); END IF; END IF; END PROCESS; xBranch_uid132_rrx_uid32_fpCosPiTest_n(0) <= not xBranch_uid132_rrx_uid32_fpCosPiTest_o(10); --ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b(DELAY,538)@1 ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 12 ) PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --finalExp_uid150_rrx_uid32_fpCosPiTest(MUX,149)@13 finalExp_uid150_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalExp_uid150_rrx_uid32_fpCosPiTest_b_q; finalExp_uid150_rrx_uid32_fpCosPiTest: PROCESS (finalExp_uid150_rrx_uid32_fpCosPiTest_s, en, reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q, ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q) BEGIN CASE finalExp_uid150_rrx_uid32_fpCosPiTest_s IS WHEN "0" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= reg_expCompOut_uid146_rrx_uid32_fpCosPiTest_0_to_finalExp_uid150_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= ld_expX_uid127_rrx_uid32_fpCosPiTest_b_to_finalExp_uid150_rrx_uid32_fpCosPiTest_d_replace_mem_q; WHEN OTHERS => finalExp_uid150_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b(DELAY,542)@13 ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => finalExp_uid150_rrx_uid32_fpCosPiTest_q, xout => ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor(LOGICAL,861) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q <= not (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_a or ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_b); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top(CONSTANT,820) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q <= "0111"; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp(LOGICAL,821) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_mem_top_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q); ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q <= "1" when ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_a = ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_b else "0"; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg(REG,822) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena(REG,862) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_nor_q = "1") THEN ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd(LOGICAL,863) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_sticky_ena_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b <= en; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_a and ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_b; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,851) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracX_uid128_rrx_uid32_fpCosPiTest_b, xout => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt(COUNTER,816) -- every=1, low=0, high=7, step=1, init=1 ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_i,3)); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg(REG,817) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux(MUX,818) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s <= en; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux: PROCESS (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q, ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q; WHEN "1" => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem(DUALMEM,852) ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_inputreg_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 3, numwords_a => 8, width_b => 23, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq, address_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_aa, data_a => ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_ia ); ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_iq(22 downto 0); --ZerosGB_uid147_rrx_uid32_fpCosPiTest(CONSTANT,146) ZerosGB_uid147_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000000"; --fracXRExt_uid148_rrx_uid32_fpCosPiTest(BITJOIN,147)@14 fracXRExt_uid148_rrx_uid32_fpCosPiTest_q <= ld_fracX_uid128_rrx_uid32_fpCosPiTest_b_to_fracXRExt_uid148_rrx_uid32_fpCosPiTest_b_replace_mem_q & ZerosGB_uid147_rrx_uid32_fpCosPiTest_q; --LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,322)@13 LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0); LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_in(74 downto 0); --leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,323)@13 leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage174dto0_uid323_normMult_uid143_rrx_uid32_fpCosPiTest_b & GND_q; --X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,306)@9 X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(51 downto 0); X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_in(51 downto 0); --ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,923) ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 52, depth => 1 ) PORT MAP ( xin => X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,691)@9 ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 52, depth => 2 ) PORT MAP ( xin => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,305) leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000000000000000000000"; --leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,307)@12 leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X51dto0_uid307_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & leftShiftStage0Idx3Pad24_uid306_normMult_uid143_rrx_uid32_fpCosPiTest_q; --X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,303)@9 X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(59 downto 0); X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_in(59 downto 0); --ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,922) ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 60, depth => 1 ) PORT MAP ( xin => X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,689)@9 ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 60, depth => 2 ) PORT MAP ( xin => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,304)@12 leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X59dto0_uid304_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q; --X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,300)@9 X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in <= multFracBits_uid140_rrx_uid32_fpCosPiTest_b(67 downto 0); X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b <= X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_in(67 downto 0); --ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg(DELAY,921) ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 68, depth => 1 ) PORT MAP ( xin => X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,687)@9 ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 68, depth => 2 ) PORT MAP ( xin => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_inputreg_q, xout => ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,301)@12 leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_X67dto0_uid301_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q; --ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg(DELAY,924) ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 76, depth => 1 ) PORT MAP ( xin => multFracBits_uid140_rrx_uid32_fpCosPiTest_b, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c(DELAY,694)@9 ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 76, depth => 2 ) PORT MAP ( xin => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_inputreg_q, xout => ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,308)@12 leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q; leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_in(4 downto 3); --leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,309)@12 leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s <= leftShiftStageSel4Dto3_uid309_normMult_uid143_rrx_uid32_fpCosPiTest_b; leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q, leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q) BEGIN CASE leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_s IS WHEN "00" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= ld_multFracBits_uid140_rrx_uid32_fpCosPiTest_b_to_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_c_q; WHEN "01" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx1_uid302_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN "10" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx2_uid305_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN "11" => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage0Idx3_uid308_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN OTHERS => leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,317)@12 LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(69 downto 0); LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_in(69 downto 0); --leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest(CONSTANT,316) leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q <= "000000"; --leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,318)@12 leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage069dto0_uid318_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx3Pad6_uid317_normMult_uid143_rrx_uid32_fpCosPiTest_q; --reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5(REG,373)@12 reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q <= leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,314)@12 LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(71 downto 0); LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_in(71 downto 0); --leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,315)@12 leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage071dto0_uid315_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; --reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4(REG,372)@12 reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q <= leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,311)@12 LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q(73 downto 0); LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_in(73 downto 0); --leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest(BITJOIN,312)@12 leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q <= LeftShiftStage073dto0_uid312_normMult_uid143_rrx_uid32_fpCosPiTest_b & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; --reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3(REG,371)@12 reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q <= leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2(REG,370)@12 reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= "0000000000000000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q <= leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,319)@12 leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(2 downto 0); leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_in(2 downto 1); --reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1(REG,369)@12 reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q <= leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,320)@13 leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s <= reg_leftShiftStageSel2Dto1_uid320_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_1_q; leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q, reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q, reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q, reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q) BEGIN CASE leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_s IS WHEN "00" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage0_uid310_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_2_q; WHEN "01" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx1_uid313_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_3_q; WHEN "10" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx2_uid316_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_4_q; WHEN "11" => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= reg_leftShiftStage1Idx3_uid319_normMult_uid143_rrx_uid32_fpCosPiTest_0_to_leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_5_q; WHEN OTHERS => leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest(BITSELECT,324)@12 leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in <= r_uid297_zCount_uid142_rrx_uid32_fpCosPiTest_q(0 downto 0); leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b <= leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_in(0 downto 0); --ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b(DELAY,713)@12 ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b, xout => ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest(MUX,325)@13 leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s <= ld_leftShiftStageSel0Dto0_uid325_normMult_uid143_rrx_uid32_fpCosPiTest_b_to_leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_b_q; leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest: PROCESS (leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s, en, leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q, leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q) BEGIN CASE leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_s IS WHEN "0" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage1_uid321_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN "1" => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= leftShiftStage2Idx1_uid324_normMult_uid143_rrx_uid32_fpCosPiTest_q; WHEN OTHERS => leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracCompOut_uid144_rrx_uid32_fpCosPiTest(BITSELECT,143)@13 fracCompOut_uid144_rrx_uid32_fpCosPiTest_in <= leftShiftStage2_uid326_normMult_uid143_rrx_uid32_fpCosPiTest_q(74 downto 0); fracCompOut_uid144_rrx_uid32_fpCosPiTest_b <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_in(74 downto 25); --reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2(REG,374)@13 reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q <= fracCompOut_uid144_rrx_uid32_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b(DELAY,535)@1 ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 13 ) PORT MAP ( xin => xBranch_uid132_rrx_uid32_fpCosPiTest_n, xout => ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --finalFrac_uid149_rrx_uid32_fpCosPiTest(MUX,148)@14 finalFrac_uid149_rrx_uid32_fpCosPiTest_s <= ld_xBranch_uid132_rrx_uid32_fpCosPiTest_n_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_b_q; finalFrac_uid149_rrx_uid32_fpCosPiTest: PROCESS (finalFrac_uid149_rrx_uid32_fpCosPiTest_s, en, reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q, fracXRExt_uid148_rrx_uid32_fpCosPiTest_q) BEGIN CASE finalFrac_uid149_rrx_uid32_fpCosPiTest_s IS WHEN "0" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= reg_fracCompOut_uid144_rrx_uid32_fpCosPiTest_0_to_finalFrac_uid149_rrx_uid32_fpCosPiTest_2_q; WHEN "1" => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= fracXRExt_uid148_rrx_uid32_fpCosPiTest_q; WHEN OTHERS => finalFrac_uid149_rrx_uid32_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --RRangeRed_uid151_rrx_uid32_fpCosPiTest(BITJOIN,150)@14 RRangeRed_uid151_rrx_uid32_fpCosPiTest_q <= GND_q & ld_finalExp_uid150_rrx_uid32_fpCosPiTest_q_to_RRangeRed_uid151_rrx_uid32_fpCosPiTest_b_q & finalFrac_uid149_rrx_uid32_fpCosPiTest_q; --expXRR_uid34_fpCosPiTest(BITSELECT,33)@14 expXRR_uid34_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(57 downto 0); expXRR_uid34_fpCosPiTest_b <= expXRR_uid34_fpCosPiTest_in(57 downto 50); --cstBiasMwShiftM2_uid24_fpCosPiTest(CONSTANT,23) cstBiasMwShiftM2_uid24_fpCosPiTest_q <= "01110000"; --cosXIsOneXRR_uid37_fpCosPiTest(COMPARE,36)@14 cosXIsOneXRR_uid37_fpCosPiTest_cin <= GND_q; cosXIsOneXRR_uid37_fpCosPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q) & '0'; cosXIsOneXRR_uid37_fpCosPiTest_b <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b) & cosXIsOneXRR_uid37_fpCosPiTest_cin(0); cosXIsOneXRR_uid37_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_a) - SIGNED(cosXIsOneXRR_uid37_fpCosPiTest_b)); cosXIsOneXRR_uid37_fpCosPiTest_n(0) <= not cosXIsOneXRR_uid37_fpCosPiTest_o(11); --exp_uid11_fpCosPiTest(BITSELECT,10)@0 exp_uid11_fpCosPiTest_in <= a(30 downto 0); exp_uid11_fpCosPiTest_b <= exp_uid11_fpCosPiTest_in(30 downto 23); --cosXIsOne_uid36_fpCosPiTest(COMPARE,35)@0 cosXIsOne_uid36_fpCosPiTest_cin <= GND_q; cosXIsOne_uid36_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & cstBiasMwShift_uid23_fpCosPiTest_q) & '0'; cosXIsOne_uid36_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & exp_uid11_fpCosPiTest_b) & cosXIsOne_uid36_fpCosPiTest_cin(0); cosXIsOne_uid36_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cosXIsOne_uid36_fpCosPiTest_a) - UNSIGNED(cosXIsOne_uid36_fpCosPiTest_b)); cosXIsOne_uid36_fpCosPiTest_n(0) <= not cosXIsOne_uid36_fpCosPiTest_o(10); --ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a(DELAY,496)@0 ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 14 ) PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --cosXOne_uid91_fpCosPiTest(LOGICAL,90)@14 cosXOne_uid91_fpCosPiTest_a <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_cosXOne_uid91_fpCosPiTest_a_q; cosXOne_uid91_fpCosPiTest_b <= cosXIsOneXRR_uid37_fpCosPiTest_n; cosXOne_uid91_fpCosPiTest_q <= cosXOne_uid91_fpCosPiTest_a or cosXOne_uid91_fpCosPiTest_b; --ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a(DELAY,498)@14 ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => cosXOne_uid91_fpCosPiTest_q, xout => ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --VCC(CONSTANT,1) VCC_q <= "1"; --InvCosXOne_uid92_fpCosPiTest(LOGICAL,91)@17 InvCosXOne_uid92_fpCosPiTest_a <= ld_cosXOne_uid91_fpCosPiTest_q_to_InvCosXOne_uid92_fpCosPiTest_a_q; InvCosXOne_uid92_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvCosXOne_uid92_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvCosXOne_uid92_fpCosPiTest_q <= not InvCosXOne_uid92_fpCosPiTest_a; END IF; END PROCESS; --X52dto0_uid161_fxpX_uid42_fpCosPiTest(BITSELECT,160)@15 X52dto0_uid161_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(52 downto 0); X52dto0_uid161_fxpX_uid42_fpCosPiTest_b <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_in(52 downto 0); --leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest(CONSTANT,159) leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q <= "000000000000"; --leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest(BITJOIN,161)@15 leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q <= X52dto0_uid161_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q; --X56dto0_uid158_fxpX_uid42_fpCosPiTest(BITSELECT,157)@15 X56dto0_uid158_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(56 downto 0); X56dto0_uid158_fxpX_uid42_fpCosPiTest_b <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_in(56 downto 0); --leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest(BITJOIN,158)@15 leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q <= X56dto0_uid158_fxpX_uid42_fpCosPiTest_b & cstAllZwE_uid28_fpCosPiTest_q; --X60dto0_uid155_fxpX_uid42_fpCosPiTest(BITSELECT,154)@15 X60dto0_uid155_fxpX_uid42_fpCosPiTest_in <= extendedFracX_uid41_fpCosPiTest_q(60 downto 0); X60dto0_uid155_fxpX_uid42_fpCosPiTest_b <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_in(60 downto 0); --leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest(BITJOIN,155)@15 leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q <= X60dto0_uid155_fxpX_uid42_fpCosPiTest_b & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; --cstZwShiftP1_uid25_fpCosPiTest(CONSTANT,24) cstZwShiftP1_uid25_fpCosPiTest_q <= "00000000000000"; --fracXRR_uid35_fpCosPiTest(BITSELECT,34)@14 fracXRR_uid35_fpCosPiTest_in <= RRangeRed_uid151_rrx_uid32_fpCosPiTest_q(49 downto 0); fracXRR_uid35_fpCosPiTest_b <= fracXRR_uid35_fpCosPiTest_in(49 downto 0); --ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a(DELAY,434)@14 ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 50, depth => 1 ) PORT MAP ( xin => fracXRR_uid35_fpCosPiTest_b, xout => ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oFracXRR_uid38_uid38_fpCosPiTest(BITJOIN,37)@15 oFracXRR_uid38_uid38_fpCosPiTest_q <= VCC_q & ld_fracXRR_uid35_fpCosPiTest_b_to_oFracXRR_uid38_uid38_fpCosPiTest_a_q; --extendedFracX_uid41_fpCosPiTest(BITJOIN,40)@15 extendedFracX_uid41_fpCosPiTest_q <= cstZwShiftP1_uid25_fpCosPiTest_q & oFracXRR_uid38_uid38_fpCosPiTest_q; --fxpXShiftValExt_uid39_fpCosPiTest(SUB,38)@14 fxpXShiftValExt_uid39_fpCosPiTest_a <= STD_LOGIC_VECTOR((10 downto 8 => expXRR_uid34_fpCosPiTest_b(7)) & expXRR_uid34_fpCosPiTest_b); fxpXShiftValExt_uid39_fpCosPiTest_b <= STD_LOGIC_VECTOR('0' & "00" & cstBiasMwShiftM2_uid24_fpCosPiTest_q); fxpXShiftValExt_uid39_fpCosPiTest_o <= STD_LOGIC_VECTOR(SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_a) - SIGNED(fxpXShiftValExt_uid39_fpCosPiTest_b)); fxpXShiftValExt_uid39_fpCosPiTest_q <= fxpXShiftValExt_uid39_fpCosPiTest_o(9 downto 0); --fxpXShiftVal_uid40_fpCosPiTest(BITSELECT,39)@14 fxpXShiftVal_uid40_fpCosPiTest_in <= fxpXShiftValExt_uid39_fpCosPiTest_q(3 downto 0); fxpXShiftVal_uid40_fpCosPiTest_b <= fxpXShiftVal_uid40_fpCosPiTest_in(3 downto 0); --leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest(BITSELECT,162)@14 leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b; leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_in(3 downto 2); --reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1(REG,376)@14 reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q <= leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest(MUX,163)@15 leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid163_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_1_q; leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s, en, extendedFracX_uid41_fpCosPiTest_q, leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q, leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q) BEGIN CASE leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_s IS WHEN "00" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= extendedFracX_uid41_fpCosPiTest_q; WHEN "01" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx1_uid156_fxpX_uid42_fpCosPiTest_q; WHEN "10" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx2_uid159_fxpX_uid42_fpCosPiTest_q; WHEN "11" => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= leftShiftStage0Idx3_uid162_fxpX_uid42_fpCosPiTest_q; WHEN OTHERS => leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest(BITSELECT,171)@15 LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(61 downto 0); LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_in(61 downto 0); --ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b(DELAY,560)@15 ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 62, depth => 1 ) PORT MAP ( xin => LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest(CONSTANT,170) leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q <= "000"; --leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest(BITJOIN,172)@16 leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage061dto0_uid172_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest(BITSELECT,168)@15 LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(62 downto 0); LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_in(62 downto 0); --ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b(DELAY,558)@15 ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 63, depth => 1 ) PORT MAP ( xin => LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest(BITJOIN,169)@16 leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage062dto0_uid169_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest(BITSELECT,165)@15 LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q(63 downto 0); LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b <= LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_in(63 downto 0); --ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b(DELAY,556)@15 ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 64, depth => 1 ) PORT MAP ( xin => LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b, xout => ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest(BITJOIN,166)@16 leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q <= ld_LeftShiftStage063dto0_uid166_fxpX_uid42_fpCosPiTest_b_to_leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_b_q & GND_q; --reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2(REG,378)@15 reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q <= leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest(BITSELECT,173)@14 leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in <= fxpXShiftVal_uid40_fpCosPiTest_b(1 downto 0); leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_in(1 downto 0); --ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a(DELAY,771)@14 ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1(REG,377)@15 reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest(MUX,174)@16 leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid174_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_1_q; leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest: PROCESS (leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s, en, reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q, leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q, leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q) BEGIN CASE leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_s IS WHEN "00" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= reg_leftShiftStage0_uid164_fxpX_uid42_fpCosPiTest_0_to_leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_2_q; WHEN "01" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx1_uid167_fxpX_uid42_fpCosPiTest_q; WHEN "10" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx2_uid170_fxpX_uid42_fpCosPiTest_q; WHEN "11" => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= leftShiftStage1Idx3_uid173_fxpX_uid42_fpCosPiTest_q; WHEN OTHERS => leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid44_fpCosPiTest(BITSELECT,43)@16 y_uid44_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q(63 downto 0); y_uid44_fpCosPiTest_b <= y_uid44_fpCosPiTest_in(63 downto 1); --ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b(DELAY,446)@16 ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 63, depth => 2 ) PORT MAP ( xin => y_uid44_fpCosPiTest_b, xout => ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1(REG,379)@16 reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= "000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q <= y_uid44_fpCosPiTest_b; END IF; END IF; END PROCESS; --pad_one_uid49_fpCosPiTest(BITJOIN,48)@16 pad_one_uid49_fpCosPiTest_q <= VCC_q & STD_LOGIC_VECTOR((62 downto 1 => GND_q(0)) & GND_q); --reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0(REG,384)@16 reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= "0000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q <= pad_one_uid49_fpCosPiTest_q; END IF; END IF; END PROCESS; --oneMinusY_uid49_fpCosPiTest(SUB,49)@17 oneMinusY_uid49_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & reg_pad_one_uid49_fpCosPiTest_0_to_oneMinusY_uid49_fpCosPiTest_0_q); oneMinusY_uid49_fpCosPiTest_b <= STD_LOGIC_VECTOR("00" & reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q); oneMinusY_uid49_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oneMinusY_uid49_fpCosPiTest_a) - UNSIGNED(oneMinusY_uid49_fpCosPiTest_b)); oneMinusY_uid49_fpCosPiTest_q <= oneMinusY_uid49_fpCosPiTest_o(64 downto 0); --reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0(REG,386)@17 reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= "00000000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q <= oneMinusY_uid49_fpCosPiTest_q; END IF; END IF; END PROCESS; --cmpYToOneMinusY_uid51_fpCosPiTest(COMPARE,50)@18 cmpYToOneMinusY_uid51_fpCosPiTest_cin <= GND_q; cmpYToOneMinusY_uid51_fpCosPiTest_a <= STD_LOGIC_VECTOR("00" & reg_oneMinusY_uid49_fpCosPiTest_0_to_cmpYToOneMinusY_uid51_fpCosPiTest_0_q) & '0'; cmpYToOneMinusY_uid51_fpCosPiTest_b <= STD_LOGIC_VECTOR("0000" & ld_y_uid44_fpCosPiTest_b_to_cmpYToOneMinusY_uid51_fpCosPiTest_b_q) & cmpYToOneMinusY_uid51_fpCosPiTest_cin(0); cmpYToOneMinusY_uid51_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_a) - UNSIGNED(cmpYToOneMinusY_uid51_fpCosPiTest_b)); cmpYToOneMinusY_uid51_fpCosPiTest_c(0) <= cmpYToOneMinusY_uid51_fpCosPiTest_o(67); --InvCmpYToOneMinusY_uid52_fpCosPiTest(LOGICAL,51)@18 InvCmpYToOneMinusY_uid52_fpCosPiTest_a <= cmpYToOneMinusY_uid51_fpCosPiTest_c; InvCmpYToOneMinusY_uid52_fpCosPiTest_q <= not InvCmpYToOneMinusY_uid52_fpCosPiTest_a; --intXParity_uid43_fpCosPiTest(BITSELECT,42)@16 intXParity_uid43_fpCosPiTest_in <= leftShiftStage1_uid175_fxpX_uid42_fpCosPiTest_q; intXParity_uid43_fpCosPiTest_b <= intXParity_uid43_fpCosPiTest_in(64 downto 64); --ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b(DELAY,501)@16 ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => intXParity_uid43_fpCosPiTest_b, xout => ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --yIsZero_uid45_fpCosPiTest(LOGICAL,44)@17 yIsZero_uid45_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q; yIsZero_uid45_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000000000000000000000000000000000" & GND_q); yIsZero_uid45_fpCosPiTest_q <= "1" when yIsZero_uid45_fpCosPiTest_a = yIsZero_uid45_fpCosPiTest_b else "0"; --ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a(DELAY,499)@17 ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => yIsZero_uid45_fpCosPiTest_q, xout => ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvYIsZero_uid94_fpCosPiTest(LOGICAL,93)@18 InvYIsZero_uid94_fpCosPiTest_a <= ld_yIsZero_uid45_fpCosPiTest_q_to_InvYIsZero_uid94_fpCosPiTest_a_q; InvYIsZero_uid94_fpCosPiTest_q <= not InvYIsZero_uid94_fpCosPiTest_a; --signRCond2_uid95_fpCosPiTest(LOGICAL,94)@18 signRCond2_uid95_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q; signRCond2_uid95_fpCosPiTest_b <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q; signRCond2_uid95_fpCosPiTest_c <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q; signRCond2_uid95_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q; signRCond2_uid95_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRCond2_uid95_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN signRCond2_uid95_fpCosPiTest_q <= signRCond2_uid95_fpCosPiTest_a and signRCond2_uid95_fpCosPiTest_b and signRCond2_uid95_fpCosPiTest_c and signRCond2_uid95_fpCosPiTest_d; END IF; END IF; END PROCESS; --InvIntXParity_uid98_fpCosPiTest(LOGICAL,97)@18 InvIntXParity_uid98_fpCosPiTest_a <= ld_intXParity_uid43_fpCosPiTest_b_to_signRCond2_uid95_fpCosPiTest_b_q; InvIntXParity_uid98_fpCosPiTest_q <= not InvIntXParity_uid98_fpCosPiTest_a; --signRCond1_uid100_fpCosPiTest(LOGICAL,99)@18 signRCond1_uid100_fpCosPiTest_a <= InvYIsZero_uid94_fpCosPiTest_q; signRCond1_uid100_fpCosPiTest_b <= InvIntXParity_uid98_fpCosPiTest_q; signRCond1_uid100_fpCosPiTest_c <= cmpYToOneMinusY_uid51_fpCosPiTest_c; signRCond1_uid100_fpCosPiTest_d <= InvCosXOne_uid92_fpCosPiTest_q; signRCond1_uid100_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRCond1_uid100_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN signRCond1_uid100_fpCosPiTest_q <= signRCond1_uid100_fpCosPiTest_a and signRCond1_uid100_fpCosPiTest_b and signRCond1_uid100_fpCosPiTest_c and signRCond1_uid100_fpCosPiTest_d; END IF; END IF; END PROCESS; --signR_uid101_fpCosPiTest(LOGICAL,100)@19 signR_uid101_fpCosPiTest_a <= signRCond1_uid100_fpCosPiTest_q; signR_uid101_fpCosPiTest_b <= signRCond2_uid95_fpCosPiTest_q; signR_uid101_fpCosPiTest_q <= signR_uid101_fpCosPiTest_a or signR_uid101_fpCosPiTest_b; --cstAllZWF_uid7_fpCosPiTest(CONSTANT,6) cstAllZWF_uid7_fpCosPiTest_q <= "00000000000000000000000"; --frac_uid13_fpCosPiTest(BITSELECT,12)@0 frac_uid13_fpCosPiTest_in <= a(22 downto 0); frac_uid13_fpCosPiTest_b <= frac_uid13_fpCosPiTest_in(22 downto 0); --fracXIsZero_uid14_fpCosPiTest(LOGICAL,13)@0 fracXIsZero_uid14_fpCosPiTest_a <= frac_uid13_fpCosPiTest_b; fracXIsZero_uid14_fpCosPiTest_b <= cstAllZWF_uid7_fpCosPiTest_q; fracXIsZero_uid14_fpCosPiTest_q <= "1" when fracXIsZero_uid14_fpCosPiTest_a = fracXIsZero_uid14_fpCosPiTest_b else "0"; --cstAllOWE_uid6_fpCosPiTest(CONSTANT,5) cstAllOWE_uid6_fpCosPiTest_q <= "11111111"; --expXIsMax_uid12_fpCosPiTest(LOGICAL,11)@0 expXIsMax_uid12_fpCosPiTest_a <= exp_uid11_fpCosPiTest_b; expXIsMax_uid12_fpCosPiTest_b <= cstAllOWE_uid6_fpCosPiTest_q; expXIsMax_uid12_fpCosPiTest_q <= "1" when expXIsMax_uid12_fpCosPiTest_a = expXIsMax_uid12_fpCosPiTest_b else "0"; --exc_I_uid15_fpCosPiTest(LOGICAL,14)@0 exc_I_uid15_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q; exc_I_uid15_fpCosPiTest_b <= fracXIsZero_uid14_fpCosPiTest_q; exc_I_uid15_fpCosPiTest_q <= exc_I_uid15_fpCosPiTest_a and exc_I_uid15_fpCosPiTest_b; --ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a(DELAY,511)@0 ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 18 ) PORT MAP ( xin => exc_I_uid15_fpCosPiTest_q, xout => ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_I_uid102_fpCosPiTest(LOGICAL,101)@18 InvExc_I_uid102_fpCosPiTest_a <= ld_exc_I_uid15_fpCosPiTest_q_to_InvExc_I_uid102_fpCosPiTest_a_q; InvExc_I_uid102_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_I_uid102_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvExc_I_uid102_fpCosPiTest_q <= not InvExc_I_uid102_fpCosPiTest_a; END IF; END PROCESS; --InvFracXIsZero_uid16_fpCosPiTest(LOGICAL,15)@0 InvFracXIsZero_uid16_fpCosPiTest_a <= fracXIsZero_uid14_fpCosPiTest_q; InvFracXIsZero_uid16_fpCosPiTest_q <= not InvFracXIsZero_uid16_fpCosPiTest_a; --exc_N_uid17_fpCosPiTest(LOGICAL,16)@0 exc_N_uid17_fpCosPiTest_a <= expXIsMax_uid12_fpCosPiTest_q; exc_N_uid17_fpCosPiTest_b <= InvFracXIsZero_uid16_fpCosPiTest_q; exc_N_uid17_fpCosPiTest_q <= exc_N_uid17_fpCosPiTest_a and exc_N_uid17_fpCosPiTest_b; --InvExc_N_uid103_fpCosPiTest(LOGICAL,102)@0 InvExc_N_uid103_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q; InvExc_N_uid103_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExc_N_uid103_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvExc_N_uid103_fpCosPiTest_q <= not InvExc_N_uid103_fpCosPiTest_a; END IF; END PROCESS; --ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a(DELAY,513)@1 ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 18 ) PORT MAP ( xin => InvExc_N_uid103_fpCosPiTest_q, xout => ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRNotNaNOrInf_uid104_fpCosPiTest(LOGICAL,103)@19 signRNotNaNOrInf_uid104_fpCosPiTest_a <= ld_InvExc_N_uid103_fpCosPiTest_q_to_signRNotNaNOrInf_uid104_fpCosPiTest_a_q; signRNotNaNOrInf_uid104_fpCosPiTest_b <= InvExc_I_uid102_fpCosPiTest_q; signRNotNaNOrInf_uid104_fpCosPiTest_c <= signR_uid101_fpCosPiTest_q; signRNotNaNOrInf_uid104_fpCosPiTest_q <= signRNotNaNOrInf_uid104_fpCosPiTest_a and signRNotNaNOrInf_uid104_fpCosPiTest_b and signRNotNaNOrInf_uid104_fpCosPiTest_c; --ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c(DELAY,518)@19 ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 16 ) PORT MAP ( xin => signRNotNaNOrInf_uid104_fpCosPiTest_q, xout => ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --cstBias_uid22_fpCosPiTest(CONSTANT,21) cstBias_uid22_fpCosPiTest_q <= "01111111"; --oMyBottom_uid53_fpCosPiTest(BITSELECT,52)@17 oMyBottom_uid53_fpCosPiTest_in <= oneMinusY_uid49_fpCosPiTest_q(61 downto 0); oMyBottom_uid53_fpCosPiTest_b <= oMyBottom_uid53_fpCosPiTest_in(61 downto 0); --reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3(REG,389)@17 reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q <= oMyBottom_uid53_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d(DELAY,452)@18 ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d : dspba_delay GENERIC MAP ( width => 62, depth => 1 ) PORT MAP ( xin => reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q, xout => ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --yBottom_uid54_fpCosPiTest(BITSELECT,53)@16 yBottom_uid54_fpCosPiTest_in <= y_uid44_fpCosPiTest_b(61 downto 0); yBottom_uid54_fpCosPiTest_b <= yBottom_uid54_fpCosPiTest_in(61 downto 0); --reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2(REG,388)@16 reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q <= yBottom_uid54_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c(DELAY,451)@17 ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 62, depth => 2 ) PORT MAP ( xin => reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q, xout => ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1(REG,387)@18 reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q <= InvCmpYToOneMinusY_uid52_fpCosPiTest_q; END IF; END IF; END PROCESS; --z_uid55_fpCosPiTest(MUX,54)@19 z_uid55_fpCosPiTest_s <= reg_InvCmpYToOneMinusY_uid52_fpCosPiTest_0_to_z_uid55_fpCosPiTest_1_q; z_uid55_fpCosPiTest: PROCESS (z_uid55_fpCosPiTest_s, en, ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q, ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q) BEGIN CASE z_uid55_fpCosPiTest_s IS WHEN "0" => z_uid55_fpCosPiTest_q <= ld_reg_yBottom_uid54_fpCosPiTest_0_to_z_uid55_fpCosPiTest_2_q_to_z_uid55_fpCosPiTest_c_q; WHEN "1" => z_uid55_fpCosPiTest_q <= ld_reg_oMyBottom_uid53_fpCosPiTest_0_to_z_uid55_fpCosPiTest_3_q_to_z_uid55_fpCosPiTest_d_q; WHEN OTHERS => z_uid55_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --zAddr_uid64_fpCosPiTest(BITSELECT,63)@19 zAddr_uid64_fpCosPiTest_in <= z_uid55_fpCosPiTest_q; zAddr_uid64_fpCosPiTest_b <= zAddr_uid64_fpCosPiTest_in(61 downto 54); --reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0(REG,401)@19 reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q <= zAddr_uid64_fpCosPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid253_sinPiZTableGenerator_lutmem(DUALMEM,349)@20 memoryC2_uid253_sinPiZTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid253_sinPiZTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid253_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q; memoryC2_uid253_sinPiZTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 8, numwords_a => 256, width_b => 13, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_memoryC2_uid253_sinPiZTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid253_sinPiZTableGenerator_lutmem_iq, address_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_aa, data_a => memoryC2_uid253_sinPiZTableGenerator_lutmem_ia ); memoryC2_uid253_sinPiZTableGenerator_lutmem_reset0 <= areset; memoryC2_uid253_sinPiZTableGenerator_lutmem_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_iq(12 downto 0); --reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1(REG,403)@22 reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q <= memoryC2_uid253_sinPiZTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --zPPolyEval_uid65_fpCosPiTest(BITSELECT,64)@19 zPPolyEval_uid65_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(53 downto 0); zPPolyEval_uid65_fpCosPiTest_b <= zPPolyEval_uid65_fpCosPiTest_in(53 downto 36); --yT1_uid255_sinPiZPolyEval(BITSELECT,254)@19 yT1_uid255_sinPiZPolyEval_in <= zPPolyEval_uid65_fpCosPiTest_b; yT1_uid255_sinPiZPolyEval_b <= yT1_uid255_sinPiZPolyEval_in(17 downto 5); --reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0(REG,402)@19 reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q <= yT1_uid255_sinPiZPolyEval_b; END IF; END IF; END PROCESS; --ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg(DELAY,925) ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg : dspba_delay GENERIC MAP ( width => 13, depth => 1 ) PORT MAP ( xin => reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a(DELAY,716)@20 ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a : dspba_delay GENERIC MAP ( width => 13, depth => 2 ) PORT MAP ( xin => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_inputreg_q, xout => ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q, ena => en(0), clk => clk, aclr => areset ); --prodXY_uid328_pT1_uid256_sinPiZPolyEval(MULT,327)@23 prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_a),14)) * SIGNED(prodXY_uid328_pT1_uid256_sinPiZPolyEval_b); prodXY_uid328_pT1_uid256_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= (others => '0'); prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= (others => '0'); prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_a <= ld_reg_yT1_uid255_sinPiZPolyEval_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_0_q_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_a_q; prodXY_uid328_pT1_uid256_sinPiZPolyEval_b <= reg_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_to_prodXY_uid328_pT1_uid256_sinPiZPolyEval_1_q; prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid328_pT1_uid256_sinPiZPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid328_pT1_uid256_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid328_pT1_uid256_sinPiZPolyEval_q <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval(BITSELECT,328)@26 prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in <= prodXY_uid328_pT1_uid256_sinPiZPolyEval_q; prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_in(25 downto 12); --highBBits_uid258_sinPiZPolyEval(BITSELECT,257)@26 highBBits_uid258_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b; highBBits_uid258_sinPiZPolyEval_b <= highBBits_uid258_sinPiZPolyEval_in(13 downto 1); --ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a(DELAY,742)@20 ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_zAddr_uid64_fpCosPiTest_0_to_memoryC2_uid253_sinPiZTableGenerator_lutmem_0_q, xout => ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid251_sinPiZTableGenerator_lutmem(DUALMEM,348)@23 memoryC1_uid251_sinPiZTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid251_sinPiZTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid251_sinPiZTableGenerator_lutmem_ab <= ld_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_q_to_memoryC1_uid251_sinPiZTableGenerator_lutmem_a_q; memoryC1_uid251_sinPiZTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_memoryC1_uid251_sinPiZTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid251_sinPiZTableGenerator_lutmem_iq, address_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_aa, data_a => memoryC1_uid251_sinPiZTableGenerator_lutmem_ia ); memoryC1_uid251_sinPiZTableGenerator_lutmem_reset0 <= areset; memoryC1_uid251_sinPiZTableGenerator_lutmem_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_iq(20 downto 0); --reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0(REG,405)@25 reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q <= memoryC1_uid251_sinPiZTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid259_sinPiZPolyEval(ADD,258)@26 sumAHighB_uid259_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q(20)) & reg_memoryC1_uid251_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid259_sinPiZPolyEval_0_q); sumAHighB_uid259_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid258_sinPiZPolyEval_b(12)) & highBBits_uid258_sinPiZPolyEval_b); sumAHighB_uid259_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid259_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid259_sinPiZPolyEval_b)); sumAHighB_uid259_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_o(21 downto 0); --lowRangeB_uid257_sinPiZPolyEval(BITSELECT,256)@26 lowRangeB_uid257_sinPiZPolyEval_in <= prodXYTruncFR_uid329_pT1_uid256_sinPiZPolyEval_b(0 downto 0); lowRangeB_uid257_sinPiZPolyEval_b <= lowRangeB_uid257_sinPiZPolyEval_in(0 downto 0); --s1_uid257_uid260_sinPiZPolyEval(BITJOIN,259)@26 s1_uid257_uid260_sinPiZPolyEval_q <= sumAHighB_uid259_sinPiZPolyEval_q & lowRangeB_uid257_sinPiZPolyEval_b; --reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1(REG,407)@26 reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q <= s1_uid257_uid260_sinPiZPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor(LOGICAL,936) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q <= not (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_a or ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_b); --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top(CONSTANT,932) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q <= "0100"; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp(LOGICAL,933) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_mem_top_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q); ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q <= "1" when ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_a = ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_b else "0"; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg(REG,934) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena(REG,937) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_nor_q = "1") THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd(LOGICAL,938) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_sticky_ena_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b <= en; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_a and ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_b; --reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0(REG,406)@19 reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q <= zPPolyEval_uid65_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg(DELAY,926) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg : dspba_delay GENERIC MAP ( width => 18, depth => 1 ) PORT MAP ( xin => reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q, xout => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt(COUNTER,928) -- every=1, low=0, high=4, step=1, init=1 ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i = 3 THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i - 4; ELSE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_i,3)); --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg(REG,929) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux(MUX,930) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s <= en; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux: PROCESS (ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q, ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem(DUALMEM,927) ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_inputreg_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 3, numwords_a => 5, width_b => 18, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq, address_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_aa, data_a => ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_ia ); ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_reset0 <= areset; ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_iq(17 downto 0); --prodXY_uid331_pT2_uid262_sinPiZPolyEval(MULT,330)@27 prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_a),19)) * SIGNED(prodXY_uid331_pT2_uid262_sinPiZPolyEval_b); prodXY_uid331_pT2_uid262_sinPiZPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= (others => '0'); prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= (others => '0'); prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_a <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_mem_q; prodXY_uid331_pT2_uid262_sinPiZPolyEval_b <= reg_s1_uid257_uid260_sinPiZPolyEval_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_1_q; prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid331_pT2_uid262_sinPiZPolyEval_pr,41)); END IF; END IF; END PROCESS; prodXY_uid331_pT2_uid262_sinPiZPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid331_pT2_uid262_sinPiZPolyEval_q <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval(BITSELECT,331)@30 prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in <= prodXY_uid331_pT2_uid262_sinPiZPolyEval_q; prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_in(40 downto 17); --highBBits_uid264_sinPiZPolyEval(BITSELECT,263)@30 highBBits_uid264_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b; highBBits_uid264_sinPiZPolyEval_b <= highBBits_uid264_sinPiZPolyEval_in(23 downto 2); --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor(LOGICAL,949) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q <= not (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_a or ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_b); --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena(REG,950) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd(LOGICAL,951) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_sticky_ena_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_a and ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_b; --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg(DELAY,939) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => zAddr_uid64_fpCosPiTest_b, xout => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem(DUALMEM,940) ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_inputreg_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdreg_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_zPPolyEval_uid65_fpCosPiTest_0_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_0_q_to_prodXY_uid331_pT2_uid262_sinPiZPolyEval_a_replace_rdmux_q; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 5, width_b => 8, widthad_b => 3, numwords_b => 5, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_ia ); ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0(REG,408)@26 reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q <= ld_zAddr_uid64_fpCosPiTest_b_to_reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid249_sinPiZTableGenerator_lutmem(DUALMEM,347)@27 memoryC0_uid249_sinPiZTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid249_sinPiZTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid249_sinPiZTableGenerator_lutmem_ab <= reg_zAddr_uid64_fpCosPiTest_0_to_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_q; memoryC0_uid249_sinPiZTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_cos_s5_memoryC0_uid249_sinPiZTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid249_sinPiZTableGenerator_lutmem_iq, address_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_aa, data_a => memoryC0_uid249_sinPiZTableGenerator_lutmem_ia ); memoryC0_uid249_sinPiZTableGenerator_lutmem_reset0 <= areset; memoryC0_uid249_sinPiZTableGenerator_lutmem_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_iq(29 downto 0); --reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0(REG,409)@29 reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= "000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q <= memoryC0_uid249_sinPiZTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --sumAHighB_uid265_sinPiZPolyEval(ADD,264)@30 sumAHighB_uid265_sinPiZPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q(29)) & reg_memoryC0_uid249_sinPiZTableGenerator_lutmem_0_to_sumAHighB_uid265_sinPiZPolyEval_0_q); sumAHighB_uid265_sinPiZPolyEval_b <= STD_LOGIC_VECTOR((30 downto 22 => highBBits_uid264_sinPiZPolyEval_b(21)) & highBBits_uid264_sinPiZPolyEval_b); sumAHighB_uid265_sinPiZPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid265_sinPiZPolyEval_a) + SIGNED(sumAHighB_uid265_sinPiZPolyEval_b)); sumAHighB_uid265_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_o(30 downto 0); --lowRangeB_uid263_sinPiZPolyEval(BITSELECT,262)@30 lowRangeB_uid263_sinPiZPolyEval_in <= prodXYTruncFR_uid332_pT2_uid262_sinPiZPolyEval_b(1 downto 0); lowRangeB_uid263_sinPiZPolyEval_b <= lowRangeB_uid263_sinPiZPolyEval_in(1 downto 0); --s2_uid263_uid266_sinPiZPolyEval(BITJOIN,265)@30 s2_uid263_uid266_sinPiZPolyEval_q <= sumAHighB_uid265_sinPiZPolyEval_q & lowRangeB_uid263_sinPiZPolyEval_b; --fxpSinRes_uid67_fpCosPiTest(BITSELECT,66)@30 fxpSinRes_uid67_fpCosPiTest_in <= s2_uid263_uid266_sinPiZPolyEval_q(30 downto 0); fxpSinRes_uid67_fpCosPiTest_b <= fxpSinRes_uid67_fpCosPiTest_in(30 downto 5); --reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1(REG,411)@30 reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q <= fxpSinRes_uid67_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor(LOGICAL,962) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q <= not (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_a or ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_b); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top(CONSTANT,958) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q <= "010"; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp(LOGICAL,959) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_mem_top_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q); ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q <= "1" when ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_a = ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_b else "0"; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg(REG,960) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena(REG,963) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_nor_q = "1") THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd(LOGICAL,964) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_sticky_ena_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b <= en; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_a and ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_b; --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,907) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_b); --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,908) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,909) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_b; --X13dto0_uid222_alignedZ_uid58_fpCosPiTest(BITSELECT,221)@19 X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(13 downto 0); X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b <= X13dto0_uid222_alignedZ_uid58_fpCosPiTest_in(13 downto 0); --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,899) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 14, depth => 1 ) PORT MAP ( xin => X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b, xout => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,900) ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_inputreg_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 14, widthad_a => 1, numwords_a => 2, width_b => 14, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq, address_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa, data_a => ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia ); ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(13 downto 0); --leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest(CONSTANT,220) leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q <= "000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest(BITJOIN,222)@23 leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q <= ld_X13dto0_uid222_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & leftShiftStage0Idx3Pad48_uid221_alignedZ_uid58_fpCosPiTest_q; --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,896) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_b); --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,897) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,898) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_b; --vStage_uid181_lzcZ_uid57_fpCosPiTest(BITSELECT,180)@19 vStage_uid181_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(29 downto 0); vStage_uid181_lzcZ_uid57_fpCosPiTest_b <= vStage_uid181_lzcZ_uid57_fpCosPiTest_in(29 downto 0); --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b(DELAY,570)@19 ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 30, depth => 1 ) PORT MAP ( xin => vStage_uid181_lzcZ_uid57_fpCosPiTest_b, xout => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,889) ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 1, numwords_a => 2, width_b => 30, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq, address_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa, data_a => ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia ); ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(29 downto 0); --zs_uid177_lzcZ_uid57_fpCosPiTest(CONSTANT,176) zs_uid177_lzcZ_uid57_fpCosPiTest_q <= "00000000000000000000000000000000"; --leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest(BITJOIN,219)@23 leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid177_lzcZ_uid57_fpCosPiTest_q; --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor(LOGICAL,885) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q <= not (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_a or ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_b); --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena(REG,886) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_nor_q = "1") THEN ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd(LOGICAL,887) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_sticky_ena_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b <= en; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_a and ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_b; --X45dto0_uid216_alignedZ_uid58_fpCosPiTest(BITSELECT,215)@19 X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in <= z_uid55_fpCosPiTest_q(45 downto 0); X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b <= X45dto0_uid216_alignedZ_uid58_fpCosPiTest_in(45 downto 0); --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg(DELAY,877) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 46, depth => 1 ) PORT MAP ( xin => X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b, xout => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem(DUALMEM,878) ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_inputreg_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 46, widthad_a => 1, numwords_a => 2, width_b => 46, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq, address_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_aa, data_a => ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_ia ); ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_iq(45 downto 0); --leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest(BITJOIN,216)@23 leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q <= ld_X45dto0_uid216_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_b_replace_mem_q & zs_uid185_lzcZ_uid57_fpCosPiTest_q; --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor(LOGICAL,918) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q <= not (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_a or ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_b); --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena(REG,919) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_nor_q = "1") THEN ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd(LOGICAL,920) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_sticky_ena_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b <= en; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_a and ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_b; --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg(DELAY,910) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 62, depth => 1 ) PORT MAP ( xin => z_uid55_fpCosPiTest_q, xout => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem(DUALMEM,911) ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_inputreg_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdreg_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab <= ld_R_uid108_px_uid31_fpCosPiTest_q_to_fracX_uid128_rrx_uid32_fpCosPiTest_a_replace_rdmux_q; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 62, widthad_a => 1, numwords_a => 2, width_b => 62, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq, address_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_aa, data_a => ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_ia ); ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_reset0 <= areset; ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_iq(61 downto 0); --rVStage_uid178_lzcZ_uid57_fpCosPiTest(BITSELECT,177)@19 rVStage_uid178_lzcZ_uid57_fpCosPiTest_in <= z_uid55_fpCosPiTest_q; rVStage_uid178_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_in(61 downto 30); --vCount_uid179_lzcZ_uid57_fpCosPiTest(LOGICAL,178)@19 vCount_uid179_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid178_lzcZ_uid57_fpCosPiTest_b; vCount_uid179_lzcZ_uid57_fpCosPiTest_b <= zs_uid177_lzcZ_uid57_fpCosPiTest_q; vCount_uid179_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid179_lzcZ_uid57_fpCosPiTest_a = vCount_uid179_lzcZ_uid57_fpCosPiTest_b) THEN vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "1"; ELSE vCount_uid179_lzcZ_uid57_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f(DELAY,605)@20 ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid179_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q, ena => en(0), clk => clk, aclr => areset ); --cStage_uid182_lzcZ_uid57_fpCosPiTest(BITJOIN,181)@20 cStage_uid182_lzcZ_uid57_fpCosPiTest_q <= ld_vStage_uid181_lzcZ_uid57_fpCosPiTest_b_to_cStage_uid182_lzcZ_uid57_fpCosPiTest_b_q & mO_uid180_lzcZ_uid57_fpCosPiTest_q; --ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c(DELAY,572)@19 ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 32, depth => 1 ) PORT MAP ( xin => rVStage_uid178_lzcZ_uid57_fpCosPiTest_b, xout => ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --vStagei_uid184_lzcZ_uid57_fpCosPiTest(MUX,183)@20 vStagei_uid184_lzcZ_uid57_fpCosPiTest_s <= vCount_uid179_lzcZ_uid57_fpCosPiTest_q; vStagei_uid184_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid184_lzcZ_uid57_fpCosPiTest_s, en, ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q, cStage_uid182_lzcZ_uid57_fpCosPiTest_q) BEGIN CASE vStagei_uid184_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= ld_rVStage_uid178_lzcZ_uid57_fpCosPiTest_b_to_vStagei_uid184_lzcZ_uid57_fpCosPiTest_c_q; WHEN "1" => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= cStage_uid182_lzcZ_uid57_fpCosPiTest_q; WHEN OTHERS => vStagei_uid184_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid186_lzcZ_uid57_fpCosPiTest(BITSELECT,185)@20 rVStage_uid186_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q; rVStage_uid186_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_in(31 downto 16); --vCount_uid187_lzcZ_uid57_fpCosPiTest(LOGICAL,186)@20 vCount_uid187_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b; vCount_uid187_lzcZ_uid57_fpCosPiTest_b <= zs_uid185_lzcZ_uid57_fpCosPiTest_q; vCount_uid187_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid187_lzcZ_uid57_fpCosPiTest_a = vCount_uid187_lzcZ_uid57_fpCosPiTest_b else "0"; --reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4(REG,395)@20 reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e(DELAY,604)@21 ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q, xout => ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid188_lzcZ_uid57_fpCosPiTest(BITSELECT,187)@20 vStage_uid188_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid184_lzcZ_uid57_fpCosPiTest_q(15 downto 0); vStage_uid188_lzcZ_uid57_fpCosPiTest_b <= vStage_uid188_lzcZ_uid57_fpCosPiTest_in(15 downto 0); --vStagei_uid190_lzcZ_uid57_fpCosPiTest(MUX,189)@20 vStagei_uid190_lzcZ_uid57_fpCosPiTest_s <= vCount_uid187_lzcZ_uid57_fpCosPiTest_q; vStagei_uid190_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid190_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid186_lzcZ_uid57_fpCosPiTest_b, vStage_uid188_lzcZ_uid57_fpCosPiTest_b) BEGIN CASE vStagei_uid190_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid186_lzcZ_uid57_fpCosPiTest_b; WHEN "1" => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= vStage_uid188_lzcZ_uid57_fpCosPiTest_b; WHEN OTHERS => vStagei_uid190_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid192_lzcZ_uid57_fpCosPiTest(BITSELECT,191)@20 rVStage_uid192_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q; rVStage_uid192_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_in(15 downto 8); --reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1(REG,390)@20 reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q <= rVStage_uid192_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --vCount_uid193_lzcZ_uid57_fpCosPiTest(LOGICAL,192)@21 vCount_uid193_lzcZ_uid57_fpCosPiTest_a <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q; vCount_uid193_lzcZ_uid57_fpCosPiTest_b <= cstAllZwE_uid28_fpCosPiTest_q; vCount_uid193_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid193_lzcZ_uid57_fpCosPiTest_a = vCount_uid193_lzcZ_uid57_fpCosPiTest_b else "0"; --ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d(DELAY,603)@21 ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid193_lzcZ_uid57_fpCosPiTest_q, xout => ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid194_lzcZ_uid57_fpCosPiTest(BITSELECT,193)@20 vStage_uid194_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid190_lzcZ_uid57_fpCosPiTest_q(7 downto 0); vStage_uid194_lzcZ_uid57_fpCosPiTest_b <= vStage_uid194_lzcZ_uid57_fpCosPiTest_in(7 downto 0); --reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3(REG,392)@20 reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid194_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid196_lzcZ_uid57_fpCosPiTest(MUX,195)@21 vStagei_uid196_lzcZ_uid57_fpCosPiTest_s <= vCount_uid193_lzcZ_uid57_fpCosPiTest_q; vStagei_uid196_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid196_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q, reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q) BEGIN CASE vStagei_uid196_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid192_lzcZ_uid57_fpCosPiTest_0_to_vCount_uid193_lzcZ_uid57_fpCosPiTest_1_q; WHEN "1" => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid194_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid196_lzcZ_uid57_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid196_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid198_lzcZ_uid57_fpCosPiTest(BITSELECT,197)@21 rVStage_uid198_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q; rVStage_uid198_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_in(7 downto 4); --vCount_uid199_lzcZ_uid57_fpCosPiTest(LOGICAL,198)@21 vCount_uid199_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b; vCount_uid199_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; vCount_uid199_lzcZ_uid57_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN IF (en = "1") THEN IF (vCount_uid199_lzcZ_uid57_fpCosPiTest_a = vCount_uid199_lzcZ_uid57_fpCosPiTest_b) THEN vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "1"; ELSE vCount_uid199_lzcZ_uid57_fpCosPiTest_q <= "0"; END IF; END IF; END IF; END PROCESS; --vStage_uid200_lzcZ_uid57_fpCosPiTest(BITSELECT,199)@21 vStage_uid200_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid196_lzcZ_uid57_fpCosPiTest_q(3 downto 0); vStage_uid200_lzcZ_uid57_fpCosPiTest_b <= vStage_uid200_lzcZ_uid57_fpCosPiTest_in(3 downto 0); --reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3(REG,394)@21 reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q <= vStage_uid200_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2(REG,393)@21 reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q <= rVStage_uid198_lzcZ_uid57_fpCosPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid202_lzcZ_uid57_fpCosPiTest(MUX,201)@22 vStagei_uid202_lzcZ_uid57_fpCosPiTest_s <= vCount_uid199_lzcZ_uid57_fpCosPiTest_q; vStagei_uid202_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid202_lzcZ_uid57_fpCosPiTest_s, en, reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q, reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q) BEGIN CASE vStagei_uid202_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_rVStage_uid198_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_2_q; WHEN "1" => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= reg_vStage_uid200_lzcZ_uid57_fpCosPiTest_0_to_vStagei_uid202_lzcZ_uid57_fpCosPiTest_3_q; WHEN OTHERS => vStagei_uid202_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid204_lzcZ_uid57_fpCosPiTest(BITSELECT,203)@22 rVStage_uid204_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q; rVStage_uid204_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_in(3 downto 2); --vCount_uid205_lzcZ_uid57_fpCosPiTest(LOGICAL,204)@22 vCount_uid205_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b; vCount_uid205_lzcZ_uid57_fpCosPiTest_b <= leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; vCount_uid205_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid205_lzcZ_uid57_fpCosPiTest_a = vCount_uid205_lzcZ_uid57_fpCosPiTest_b else "0"; --vStage_uid206_lzcZ_uid57_fpCosPiTest(BITSELECT,205)@22 vStage_uid206_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid202_lzcZ_uid57_fpCosPiTest_q(1 downto 0); vStage_uid206_lzcZ_uid57_fpCosPiTest_b <= vStage_uid206_lzcZ_uid57_fpCosPiTest_in(1 downto 0); --vStagei_uid208_lzcZ_uid57_fpCosPiTest(MUX,207)@22 vStagei_uid208_lzcZ_uid57_fpCosPiTest_s <= vCount_uid205_lzcZ_uid57_fpCosPiTest_q; vStagei_uid208_lzcZ_uid57_fpCosPiTest: PROCESS (vStagei_uid208_lzcZ_uid57_fpCosPiTest_s, en, rVStage_uid204_lzcZ_uid57_fpCosPiTest_b, vStage_uid206_lzcZ_uid57_fpCosPiTest_b) BEGIN CASE vStagei_uid208_lzcZ_uid57_fpCosPiTest_s IS WHEN "0" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= rVStage_uid204_lzcZ_uid57_fpCosPiTest_b; WHEN "1" => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= vStage_uid206_lzcZ_uid57_fpCosPiTest_b; WHEN OTHERS => vStagei_uid208_lzcZ_uid57_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid210_lzcZ_uid57_fpCosPiTest(BITSELECT,209)@22 rVStage_uid210_lzcZ_uid57_fpCosPiTest_in <= vStagei_uid208_lzcZ_uid57_fpCosPiTest_q; rVStage_uid210_lzcZ_uid57_fpCosPiTest_b <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_in(1 downto 1); --vCount_uid211_lzcZ_uid57_fpCosPiTest(LOGICAL,210)@22 vCount_uid211_lzcZ_uid57_fpCosPiTest_a <= rVStage_uid210_lzcZ_uid57_fpCosPiTest_b; vCount_uid211_lzcZ_uid57_fpCosPiTest_b <= GND_q; vCount_uid211_lzcZ_uid57_fpCosPiTest_q <= "1" when vCount_uid211_lzcZ_uid57_fpCosPiTest_a = vCount_uid211_lzcZ_uid57_fpCosPiTest_b else "0"; --r_uid212_lzcZ_uid57_fpCosPiTest(BITJOIN,211)@22 r_uid212_lzcZ_uid57_fpCosPiTest_q <= ld_vCount_uid179_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_f_q & ld_reg_vCount_uid187_lzcZ_uid57_fpCosPiTest_0_to_r_uid212_lzcZ_uid57_fpCosPiTest_4_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_e_q & ld_vCount_uid193_lzcZ_uid57_fpCosPiTest_q_to_r_uid212_lzcZ_uid57_fpCosPiTest_d_q & vCount_uid199_lzcZ_uid57_fpCosPiTest_q & vCount_uid205_lzcZ_uid57_fpCosPiTest_q & vCount_uid211_lzcZ_uid57_fpCosPiTest_q; --leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest(BITSELECT,223)@22 leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q; leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_in(5 downto 4); --reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1(REG,396)@22 reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q <= leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest(MUX,224)@23 leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel5Dto4_uid224_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_1_q; leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s, en, ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q, leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q, leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q) BEGIN CASE leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_s IS WHEN "00" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= ld_z_uid55_fpCosPiTest_q_to_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_c_replace_mem_q; WHEN "01" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx1_uid217_alignedZ_uid58_fpCosPiTest_q; WHEN "10" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx2_uid220_alignedZ_uid58_fpCosPiTest_q; WHEN "11" => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage0Idx3_uid223_alignedZ_uid58_fpCosPiTest_q; WHEN OTHERS => leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest(BITSELECT,232)@23 LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(49 downto 0); LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_in(49 downto 0); --ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b(DELAY,622)@23 ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 50, depth => 1 ) PORT MAP ( xin => LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest(BITJOIN,233)@24 leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage049dto0_uid233_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx3Pad12_uid160_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest(BITSELECT,229)@23 LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(53 downto 0); LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_in(53 downto 0); --ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b(DELAY,620)@23 ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 54, depth => 1 ) PORT MAP ( xin => LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest(BITJOIN,230)@24 leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage053dto0_uid230_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_b_q & cstAllZwE_uid28_fpCosPiTest_q; --LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest(BITSELECT,226)@23 LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q(57 downto 0); LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_in(57 downto 0); --ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b(DELAY,618)@23 ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 58, depth => 1 ) PORT MAP ( xin => LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest(BITJOIN,227)@24 leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage057dto0_uid227_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage0Idx1Pad4_uid154_fxpX_uid42_fpCosPiTest_q; --reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2(REG,398)@23 reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest(BITSELECT,234)@22 leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(3 downto 0); leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_in(3 downto 2); --ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a(DELAY,791)@22 ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1(REG,397)@23 reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest(MUX,235)@24 leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel3Dto2_uid235_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_1_q; leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q, leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q) BEGIN CASE leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_s IS WHEN "00" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage0_uid225_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_2_q; WHEN "01" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx1_uid228_alignedZ_uid58_fpCosPiTest_q; WHEN "10" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx2_uid231_alignedZ_uid58_fpCosPiTest_q; WHEN "11" => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage1Idx3_uid234_alignedZ_uid58_fpCosPiTest_q; WHEN OTHERS => leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest(BITSELECT,243)@24 LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(58 downto 0); LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_in(58 downto 0); --ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b(DELAY,634)@24 ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 59, depth => 1 ) PORT MAP ( xin => LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest(BITJOIN,244)@25 leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage158dto0_uid244_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx3Pad3_uid171_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest(BITSELECT,240)@24 LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(59 downto 0); LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_in(59 downto 0); --ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b(DELAY,632)@24 ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 60, depth => 1 ) PORT MAP ( xin => LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest(BITJOIN,241)@25 leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage159dto0_uid241_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_b_q & leftShiftStage1Idx2Pad2_uid168_fxpX_uid42_fpCosPiTest_q; --LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest(BITSELECT,237)@24 LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q(60 downto 0); LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b <= LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_in(60 downto 0); --ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b(DELAY,630)@24 ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 61, depth => 1 ) PORT MAP ( xin => LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b, xout => ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest(BITJOIN,238)@25 leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q <= ld_LeftShiftStage160dto0_uid238_alignedZ_uid58_fpCosPiTest_b_to_leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_b_q & GND_q; --reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2(REG,400)@24 reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= "00000000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q <= leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest(BITSELECT,245)@22 leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in <= r_uid212_lzcZ_uid57_fpCosPiTest_q(1 downto 0); leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b <= leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_in(1 downto 0); --ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a(DELAY,793)@22 ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a : dspba_delay GENERIC MAP ( width => 2, depth => 2 ) PORT MAP ( xin => leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b, xout => ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1(REG,399)@24 reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q <= ld_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_b_to_reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_a_q; END IF; END IF; END PROCESS; --leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest(MUX,246)@25 leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s <= reg_leftShiftStageSel1Dto0_uid246_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_1_q; leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest: PROCESS (leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s, en, reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q, leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q, leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q) BEGIN CASE leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_s IS WHEN "00" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= reg_leftShiftStage1_uid236_alignedZ_uid58_fpCosPiTest_0_to_leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_2_q; WHEN "01" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx1_uid239_alignedZ_uid58_fpCosPiTest_q; WHEN "10" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx2_uid242_alignedZ_uid58_fpCosPiTest_q; WHEN "11" => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= leftShiftStage2Idx3_uid245_alignedZ_uid58_fpCosPiTest_q; WHEN OTHERS => leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --p_uid59_fpCosPiTest(BITSELECT,58)@25 p_uid59_fpCosPiTest_in <= leftShiftStage2_uid247_alignedZ_uid58_fpCosPiTest_q; p_uid59_fpCosPiTest_b <= p_uid59_fpCosPiTest_in(61 downto 36); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg(DELAY,952) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => p_uid59_fpCosPiTest_b, xout => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt(COUNTER,954) -- every=1, low=0, high=2, step=1, init=1 ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i = 1 THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '1'; ELSE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_eq = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i - 2; ELSE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_i,2)); --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg(REG,955) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux(MUX,956) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s <= en; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux: PROCESS (ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q, ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q) BEGIN CASE ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_s IS WHEN "0" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q; WHEN "1" => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdcnt_q; WHEN OTHERS => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem(DUALMEM,953) ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_inputreg_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdreg_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_rdmux_q; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 26, widthad_a => 2, numwords_a => 3, width_b => 26, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq, address_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_aa, data_a => ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_ia ); ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_reset0 <= areset; ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_iq(25 downto 0); --reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0(REG,410)@30 reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q <= ld_p_uid59_fpCosPiTest_b_to_reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_a_replace_mem_q; END IF; END IF; END PROCESS; --mul2xSinRes_uid68_fpCosPiTest(MULT,67)@31 mul2xSinRes_uid68_fpCosPiTest_pr <= UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_a) * UNSIGNED(mul2xSinRes_uid68_fpCosPiTest_b); mul2xSinRes_uid68_fpCosPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid68_fpCosPiTest_a <= (others => '0'); mul2xSinRes_uid68_fpCosPiTest_b <= (others => '0'); mul2xSinRes_uid68_fpCosPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2xSinRes_uid68_fpCosPiTest_a <= reg_p_uid59_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_0_q; mul2xSinRes_uid68_fpCosPiTest_b <= reg_fxpSinRes_uid67_fpCosPiTest_0_to_mul2xSinRes_uid68_fpCosPiTest_1_q; mul2xSinRes_uid68_fpCosPiTest_s1 <= STD_LOGIC_VECTOR(mul2xSinRes_uid68_fpCosPiTest_pr); END IF; END IF; END PROCESS; mul2xSinRes_uid68_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2xSinRes_uid68_fpCosPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2xSinRes_uid68_fpCosPiTest_q <= mul2xSinRes_uid68_fpCosPiTest_s1; END IF; END IF; END PROCESS; --normBit_uid69_fpCosPiTest(BITSELECT,68)@34 normBit_uid69_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q; normBit_uid69_fpCosPiTest_b <= normBit_uid69_fpCosPiTest_in(51 downto 51); --rndOp_uid74_uid75_fpCosPiTest(BITJOIN,74)@34 rndOp_uid74_uid75_fpCosPiTest_q <= normBit_uid69_fpCosPiTest_b & cstAllZWF_uid7_fpCosPiTest_q & VCC_q; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor(LOGICAL,824) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q <= not (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_a or ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_b); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena(REG,825) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_nor_q = "1") THEN ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd(LOGICAL,826) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_sticky_ena_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b <= en; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_a and ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_b; --reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1(REG,412)@22 reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q <= r_uid212_lzcZ_uid57_fpCosPiTest_q; END IF; END IF; END PROCESS; --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg(DELAY,814) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 6, depth => 1 ) PORT MAP ( xin => reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q, xout => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem(DUALMEM,815) ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_inputreg_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdreg_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_rdmux_q; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 6, widthad_a => 3, numwords_a => 8, width_b => 6, widthad_b => 3, numwords_b => 8, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq, address_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_aa, data_a => ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_ia ); ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_iq(5 downto 0); --expHardCase_uid61_fpCosPiTest(SUB,60)@33 expHardCase_uid61_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & biasM1_uid60_fpCosPiTest_q); expHardCase_uid61_fpCosPiTest_b <= STD_LOGIC_VECTOR("000" & ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_replace_mem_q); expHardCase_uid61_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expHardCase_uid61_fpCosPiTest_a) - UNSIGNED(expHardCase_uid61_fpCosPiTest_b)); expHardCase_uid61_fpCosPiTest_q <= expHardCase_uid61_fpCosPiTest_o(8 downto 0); --expP_uid62_fpCosPiTest(BITSELECT,61)@33 expP_uid62_fpCosPiTest_in <= expHardCase_uid61_fpCosPiTest_q(7 downto 0); expP_uid62_fpCosPiTest_b <= expP_uid62_fpCosPiTest_in(7 downto 0); --reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1(REG,413)@33 reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q <= expP_uid62_fpCosPiTest_b; END IF; END IF; END PROCESS; --highRes_uid70_fpCosPiTest(BITSELECT,69)@34 highRes_uid70_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(50 downto 0); highRes_uid70_fpCosPiTest_b <= highRes_uid70_fpCosPiTest_in(50 downto 27); --lowRes_uid71_fpCosPiTest(BITSELECT,70)@34 lowRes_uid71_fpCosPiTest_in <= mul2xSinRes_uid68_fpCosPiTest_q(49 downto 0); lowRes_uid71_fpCosPiTest_b <= lowRes_uid71_fpCosPiTest_in(49 downto 26); --fracRCompPreRnd_uid72_fpCosPiTest(MUX,71)@34 fracRCompPreRnd_uid72_fpCosPiTest_s <= normBit_uid69_fpCosPiTest_b; fracRCompPreRnd_uid72_fpCosPiTest: PROCESS (fracRCompPreRnd_uid72_fpCosPiTest_s, en, lowRes_uid71_fpCosPiTest_b, highRes_uid70_fpCosPiTest_b) BEGIN CASE fracRCompPreRnd_uid72_fpCosPiTest_s IS WHEN "0" => fracRCompPreRnd_uid72_fpCosPiTest_q <= lowRes_uid71_fpCosPiTest_b; WHEN "1" => fracRCompPreRnd_uid72_fpCosPiTest_q <= highRes_uid70_fpCosPiTest_b; WHEN OTHERS => fracRCompPreRnd_uid72_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest(BITJOIN,72)@34 expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q <= reg_expP_uid62_fpCosPiTest_0_to_expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_1_q & fracRCompPreRnd_uid72_fpCosPiTest_q; --expRCompFracRComp_uid76_fpCosPiTest(ADD,75)@34 expRCompFracRComp_uid76_fpCosPiTest_a <= STD_LOGIC_VECTOR("0" & expRCompFracRCompPreRnd_uid73_uid73_fpCosPiTest_q); expRCompFracRComp_uid76_fpCosPiTest_b <= STD_LOGIC_VECTOR("00000000" & rndOp_uid74_uid75_fpCosPiTest_q); expRCompFracRComp_uid76_fpCosPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_a) + UNSIGNED(expRCompFracRComp_uid76_fpCosPiTest_b)); expRCompFracRComp_uid76_fpCosPiTest_q <= expRCompFracRComp_uid76_fpCosPiTest_o(32 downto 0); --expRComp_uid78_fpCosPiTest(BITSELECT,77)@34 expRComp_uid78_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(31 downto 0); expRComp_uid78_fpCosPiTest_b <= expRComp_uid78_fpCosPiTest_in(31 downto 24); --reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2(REG,418)@34 reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q <= expRComp_uid78_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor(LOGICAL,837) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q <= not (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_a or ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_b); --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top(CONSTANT,833) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q <= "01101"; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp(LOGICAL,834) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_mem_top_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q); ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q <= "1" when ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_a = ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_b else "0"; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg(REG,835) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena(REG,838) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_nor_q = "1") THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd(LOGICAL,839) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_sticky_ena_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b <= en; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_a and ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_b; --ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b(DELAY,492)@0 ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 17 ) PORT MAP ( xin => cosXIsOne_uid36_fpCosPiTest_n, xout => ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a(DELAY,474)@14 ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => cosXIsOneXRR_uid37_fpCosPiTest_n, xout => ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2(REG,416)@16 reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q; END IF; END IF; END PROCESS; --InvCosXIsOneXRR_uid79_fpCosPiTest(LOGICAL,78)@16 InvCosXIsOneXRR_uid79_fpCosPiTest_a <= ld_cosXIsOneXRR_uid37_fpCosPiTest_n_to_InvCosXIsOneXRR_uid79_fpCosPiTest_a_q; InvCosXIsOneXRR_uid79_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvCosXIsOneXRR_uid79_fpCosPiTest_q <= (others => '0'); ELSIF rising_edge(clk) THEN InvCosXIsOneXRR_uid79_fpCosPiTest_q <= not InvCosXIsOneXRR_uid79_fpCosPiTest_a; END IF; END PROCESS; --InvCosXIsOne_uid80_fpCosPiTest(LOGICAL,79)@0 InvCosXIsOne_uid80_fpCosPiTest_a <= cosXIsOne_uid36_fpCosPiTest_n; InvCosXIsOne_uid80_fpCosPiTest_q <= not InvCosXIsOne_uid80_fpCosPiTest_a; --ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b(DELAY,477)@0 ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 17 ) PORT MAP ( xin => InvCosXIsOne_uid80_fpCosPiTest_q, xout => ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --cstZmwFRRPwSM1_uid46_fpCosPiTest(CONSTANT,45) cstZmwFRRPwSM1_uid46_fpCosPiTest_q <= "00000000000000000000000000000000000000000000000000000000000000"; --half_uid47_fpCosPiTest(BITJOIN,46)@17 half_uid47_fpCosPiTest_q <= VCC_q & cstZmwFRRPwSM1_uid46_fpCosPiTest_q; --yIsHalf_uid48_fpCosPiTest(LOGICAL,47)@17 yIsHalf_uid48_fpCosPiTest_a <= reg_y_uid44_fpCosPiTest_0_to_yIsHalf_uid48_fpCosPiTest_1_q; yIsHalf_uid48_fpCosPiTest_b <= half_uid47_fpCosPiTest_q; yIsHalf_uid48_fpCosPiTest_q <= "1" when yIsHalf_uid48_fpCosPiTest_a = yIsHalf_uid48_fpCosPiTest_b else "0"; --yHalfCosNotOne_uid81_fpCosPiTest(LOGICAL,80)@17 yHalfCosNotOne_uid81_fpCosPiTest_a <= yIsHalf_uid48_fpCosPiTest_q; yHalfCosNotOne_uid81_fpCosPiTest_b <= ld_InvCosXIsOne_uid80_fpCosPiTest_q_to_yHalfCosNotOne_uid81_fpCosPiTest_b_q; yHalfCosNotOne_uid81_fpCosPiTest_c <= InvCosXIsOneXRR_uid79_fpCosPiTest_q; yHalfCosNotOne_uid81_fpCosPiTest_q <= yHalfCosNotOne_uid81_fpCosPiTest_a and yHalfCosNotOne_uid81_fpCosPiTest_b and yHalfCosNotOne_uid81_fpCosPiTest_c; --excRNaN_uid82_fpCosPiTest(LOGICAL,81)@0 excRNaN_uid82_fpCosPiTest_a <= exc_N_uid17_fpCosPiTest_q; excRNaN_uid82_fpCosPiTest_b <= exc_I_uid15_fpCosPiTest_q; excRNaN_uid82_fpCosPiTest_q <= excRNaN_uid82_fpCosPiTest_a or excRNaN_uid82_fpCosPiTest_b; --ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a(DELAY,488)@0 ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 17 ) PORT MAP ( xin => excRNaN_uid82_fpCosPiTest_q, xout => ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --join_uid86_fpCosPiTest(BITJOIN,85)@17 join_uid86_fpCosPiTest_q <= reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_join_uid86_fpCosPiTest_2_q & yHalfCosNotOne_uid81_fpCosPiTest_q & ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q; --expSelBits_uid87_fpCosPiTest(BITJOIN,86)@17 expSelBits_uid87_fpCosPiTest_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q & join_uid86_fpCosPiTest_q; --reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0(REG,417)@17 reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q <= expSelBits_uid87_fpCosPiTest_q; END IF; END IF; END PROCESS; --expSelector_uid88_fpCosPiTest(LOOKUP,87)@18 expSelector_uid88_fpCosPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSelector_uid88_fpCosPiTest_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN CASE (reg_expSelBits_uid87_fpCosPiTest_0_to_expSelector_uid88_fpCosPiTest_0_q) IS WHEN "0000" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "0001" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "0010" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "0011" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "0100" => expSelector_uid88_fpCosPiTest_q <= "01"; WHEN "0101" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "0110" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "0111" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "1000" => expSelector_uid88_fpCosPiTest_q <= "01"; WHEN "1001" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "1010" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "1011" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN "1100" => expSelector_uid88_fpCosPiTest_q <= "01"; WHEN "1101" => expSelector_uid88_fpCosPiTest_q <= "11"; WHEN "1110" => expSelector_uid88_fpCosPiTest_q <= "10"; WHEN "1111" => expSelector_uid88_fpCosPiTest_q <= "00"; WHEN OTHERS => expSelector_uid88_fpCosPiTest_q <= (others => '-'); END CASE; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg(DELAY,827) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => expSelector_uid88_fpCosPiTest_q, xout => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt(COUNTER,829) -- every=1, low=0, high=13, step=1, init=1 ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i = 12 THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_eq = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i - 13; ELSE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_i,4)); --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg(REG,830) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux(MUX,831) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s <= en; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux: PROCESS (ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q, ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q; WHEN "1" => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem(DUALMEM,828) ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_inputreg_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 4, numwords_a => 14, width_b => 2, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq, address_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_aa, data_a => ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_ia ); ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_reset0 <= areset; ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_iq(1 downto 0); --expRPostExc_uid90_fpCosPiTest(MUX,89)@35 expRPostExc_uid90_fpCosPiTest_s <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_mem_q; expRPostExc_uid90_fpCosPiTest: PROCESS (expRPostExc_uid90_fpCosPiTest_s, en, reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q, cstBias_uid22_fpCosPiTest_q, cstAllZwE_uid28_fpCosPiTest_q, cstAllOWE_uid6_fpCosPiTest_q) BEGIN CASE expRPostExc_uid90_fpCosPiTest_s IS WHEN "00" => expRPostExc_uid90_fpCosPiTest_q <= reg_expRComp_uid78_fpCosPiTest_0_to_expRPostExc_uid90_fpCosPiTest_2_q; WHEN "01" => expRPostExc_uid90_fpCosPiTest_q <= cstBias_uid22_fpCosPiTest_q; WHEN "10" => expRPostExc_uid90_fpCosPiTest_q <= cstAllZwE_uid28_fpCosPiTest_q; WHEN "11" => expRPostExc_uid90_fpCosPiTest_q <= cstAllOWE_uid6_fpCosPiTest_q; WHEN OTHERS => expRPostExc_uid90_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --cstNaNwF_uid30_fpCosPiTest(CONSTANT,29) cstNaNwF_uid30_fpCosPiTest_q <= "00000000000000000000001"; --fracRComp_uid77_fpCosPiTest(BITSELECT,76)@34 fracRComp_uid77_fpCosPiTest_in <= expRCompFracRComp_uid76_fpCosPiTest_q(23 downto 0); fracRComp_uid77_fpCosPiTest_b <= fracRComp_uid77_fpCosPiTest_in(23 downto 1); --reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2(REG,415)@34 reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q <= fracRComp_uid77_fpCosPiTest_b; END IF; END IF; END PROCESS; --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor(LOGICAL,975) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a <= ld_reg_r_uid212_lzcZ_uid57_fpCosPiTest_0_to_expHardCase_uid61_fpCosPiTest_1_q_to_expHardCase_uid61_fpCosPiTest_b_notEnable_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q <= not (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_a or ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_b); --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena(REG,976) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_nor_q = "1") THEN ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd(LOGICAL,977) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_sticky_ena_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b <= en; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_a and ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_b; --reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1(REG,383)@17 reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q <= ld_excRNaN_uid82_fpCosPiTest_q_to_join_uid86_fpCosPiTest_a_q; END IF; END IF; END PROCESS; --reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3(REG,382)@14 reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q <= cosXIsOneXRR_uid37_fpCosPiTest_n; END IF; END IF; END PROCESS; --ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c(DELAY,483)@15 ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 3 ) PORT MAP ( xin => reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q, xout => ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2(REG,381)@17 reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q <= ld_cosXIsOne_uid36_fpCosPiTest_n_to_expSelBits_uid87_fpCosPiTest_b_q; END IF; END IF; END PROCESS; --reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1(REG,380)@17 reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q <= yHalfCosNotOne_uid81_fpCosPiTest_q; END IF; END IF; END PROCESS; --excZOrCosOne_uid83_fpCosPiTest(LOGICAL,82)@18 excZOrCosOne_uid83_fpCosPiTest_a <= reg_yHalfCosNotOne_uid81_fpCosPiTest_0_to_excZOrCosOne_uid83_fpCosPiTest_1_q; excZOrCosOne_uid83_fpCosPiTest_b <= reg_cosXIsOne_uid36_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_2_q; excZOrCosOne_uid83_fpCosPiTest_c <= ld_reg_cosXIsOneXRR_uid37_fpCosPiTest_2_to_excZOrCosOne_uid83_fpCosPiTest_3_q_to_excZOrCosOne_uid83_fpCosPiTest_c_q; excZOrCosOne_uid83_fpCosPiTest_q <= excZOrCosOne_uid83_fpCosPiTest_a or excZOrCosOne_uid83_fpCosPiTest_b or excZOrCosOne_uid83_fpCosPiTest_c; --join_uid84_fpCosPiTest(BITJOIN,83)@18 join_uid84_fpCosPiTest_q <= reg_excRNaN_uid82_fpCosPiTest_0_to_join_uid84_fpCosPiTest_1_q & excZOrCosOne_uid83_fpCosPiTest_q; --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg(DELAY,965) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg : dspba_delay GENERIC MAP ( width => 2, depth => 1 ) PORT MAP ( xin => join_uid84_fpCosPiTest_q, xout => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem(DUALMEM,966) ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_inputreg_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdreg_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab <= ld_expSelector_uid88_fpCosPiTest_q_to_expRPostExc_uid90_fpCosPiTest_b_replace_rdmux_q; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 2, widthad_a => 4, numwords_a => 14, width_b => 2, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0, clock1 => clk, address_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq, address_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_aa, data_a => ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_ia ); ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_reset0 <= areset; ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_iq(1 downto 0); --reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1(REG,414)@34 reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q <= ld_join_uid84_fpCosPiTest_q_to_reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_a_replace_mem_q; END IF; END IF; END PROCESS; --fracRPostExc_uid85_fpCosPiTest(MUX,84)@35 fracRPostExc_uid85_fpCosPiTest_s <= reg_join_uid84_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_1_q; fracRPostExc_uid85_fpCosPiTest: PROCESS (fracRPostExc_uid85_fpCosPiTest_s, en, reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q, cstAllZWF_uid7_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q, cstNaNwF_uid30_fpCosPiTest_q) BEGIN CASE fracRPostExc_uid85_fpCosPiTest_s IS WHEN "00" => fracRPostExc_uid85_fpCosPiTest_q <= reg_fracRComp_uid77_fpCosPiTest_0_to_fracRPostExc_uid85_fpCosPiTest_2_q; WHEN "01" => fracRPostExc_uid85_fpCosPiTest_q <= cstAllZWF_uid7_fpCosPiTest_q; WHEN "10" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q; WHEN "11" => fracRPostExc_uid85_fpCosPiTest_q <= cstNaNwF_uid30_fpCosPiTest_q; WHEN OTHERS => fracRPostExc_uid85_fpCosPiTest_q <= (others => '0'); END CASE; END PROCESS; --cosXR_uid105_fpCosPiTest(BITJOIN,104)@35 cosXR_uid105_fpCosPiTest_q <= ld_signRNotNaNOrInf_uid104_fpCosPiTest_q_to_cosXR_uid105_fpCosPiTest_c_q & expRPostExc_uid90_fpCosPiTest_q & fracRPostExc_uid85_fpCosPiTest_q; --xOut(GPOUT,4)@35 q <= cosXR_uid105_fpCosPiTest_q; end normal;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/dp_floatfix.vhd

10

12529

LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CONVERSION - TOP LEVEL *** --*** *** --*** DP_FLOATFIX.VHD *** --*** *** --*** Function: Convert Floating Point to Fixed *** --*** Point Number *** --*** *** --*** 07/12/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** LATENCY : *** --*** speed = 0 : 3 *** --*** speed = 1 : 5 *** --*************************************************** --*************************************************** --*** OUTPUT FORMAT - UNSIGNED *** --*** maximum number is (2^decimal)-1, else *** --*** saturate. if input negative, zero output *** --*** OUTPUT FORMAT - SIGNED *** --*** maximum number is (2^decimal-1)-1, else *** --*** saturate *** --*************************************************** ENTITY dp_floatfix IS GENERIC ( unsigned : integer := 1; -- unsigned = 0, signed = 1 decimal : integer := 14; fractional : integer := 6; precision : integer := 0; -- single = 0, double = 1 speed : integer := 0 -- low speed = 0, high speed = 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; sign : IN STD_LOGIC; exponent : IN STD_LOGIC_VECTOR (8+3*precision DOWNTO 1); mantissa : IN STD_LOGIC_VECTOR (23+29*precision DOWNTO 1); fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1) ); END dp_floatfix; ARCHITECTURE rtl of dp_floatfix IS constant fixed_width : positive := decimal + fractional; constant mantissa_width : positive := 23 + 29*precision; constant exponent_width : positive := 8 + 3*precision; constant exponent_base_number : positive := 127+896*precision; -- input stage signal zerovec : STD_LOGIC_VECTOR (116 DOWNTO 1); signal exponent_base_node : STD_LOGIC_VECTOR (exponent_width+1 DOWNTO 1); signal saturate_check : STD_LOGIC_VECTOR (exponent_width+1 DOWNTO 1); signal saturate_output, zero_output : STD_LOGIC; signal saturate_apply, zero_apply : STD_LOGIC; signal sign_apply : STD_LOGIC; signal signed_mantissa_node : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1); signal signed_mantissa_comp : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1); signal signed_mantissa : STD_LOGIC_VECTOR (mantissa_width+2 DOWNTO 1); signal input_vector : STD_LOGIC_VECTOR (116 DOWNTO 1); signal negexponent : STD_LOGIC_VECTOR (exponent_width DOWNTO 1); signal expbase, negexpbase : STD_LOGIC_VECTOR (exponent_width DOWNTO 1); signal leftshift, rightshift : STD_LOGIC_VECTOR (exponent_width DOWNTO 1); -- shift stage signal leftbus, rightbus : STD_LOGIC_VECTOR (116 DOWNTO 1); signal shiftbus, shiftbusff : STD_LOGIC_VECTOR (fixed_width DOWNTO 1); signal select_bit : STD_LOGIC; -- output stage signal fixed_numberff : STD_LOGIC_VECTOR (fixed_width DOWNTO 1); component dp_addpipe IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component dp_lsft64x64 IS PORT ( inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component dp_lsftpipe64x64 IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component dp_rsft64x64 IS PORT ( inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component dp_rsftpipe64x64 IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (116 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (116 DOWNTO 1) ); end component; component fp_delbit IS GENERIC ( pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; BEGIN gera : IF NOT((unsigned = 0) OR (unsigned = 1)) GENERATE assert false report "unsigned must be 0 or 1" severity error; END GENERATE; gerb : IF NOT((precision = 0) OR (precision = 1)) GENERATE assert false report "precision must be 0 (single precision) or 1 (double precision)" severity error; END GENERATE; gerc : IF NOT((speed = 0) OR (speed = 1)) GENERATE assert false report "speed must be 0 or 1" severity error; END GENERATE; gerd : IF (decimal < 2) GENERATE assert false report "decimal must be greater than 2" severity error; END GENERATE; gere : IF (fixed_width > 64) GENERATE assert false report "maximum fixed point precision must be 64 or less" severity error; END GENERATE; gza: FOR k IN 1 TO 116 GENERATE zerovec(k) <= '0'; END GENERATE; --*** LEVEL 1-2 *** -- level 1 if speed = 0 -- level 2 if speed = 1 -- check for zero and saturate conditions exponent_base_node <= conv_std_logic_vector(exponent_base_number,exponent_width+1); gzsa: IF (unsigned = 0) GENERATE saturate_check <= exponent - exponent_base_node - decimal; -- '1' when condition true saturate_output <= NOT(saturate_check(exponent_width+1)); zero_output <= sign; END GENERATE; gzsb: IF (unsigned = 1) GENERATE saturate_check <= exponent - exponent_base_node - decimal + 1; -- '1' when condition true saturate_output <= NOT(saturate_check(exponent_width+1)); zero_output <= '0'; dss: fp_delbit GENERIC MAP (pipes=>2+2*speed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>sign, cc=>sign_apply); END GENERATE; ds: fp_delbit GENERIC MAP (pipes=>2+2*speed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>saturate_output, cc=>saturate_apply); dz: fp_delbit GENERIC MAP (pipes=>2+2*speed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>zero_output, cc=>zero_apply); signed_mantissa_node <= "01" & mantissa; gsma: FOR k IN 1 TO mantissa_width+2 GENERATE signed_mantissa_comp(k) <= signed_mantissa_node(k) XOR sign; END GENERATE; addtop: dp_addpipe GENERIC MAP (width=>mantissa_width+2,pipes=>speed+1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>signed_mantissa_comp,bb=>zerovec(mantissa_width+2 DOWNTO 1), carryin=>sign, cc=>signed_mantissa); giva: FOR k IN 116-decimal+3 TO 116 GENERATE input_vector(k) <= signed_mantissa(mantissa_width+2); END GENERATE; input_vector(116-decimal+2 DOWNTO 116-decimal-mantissa_width+1) <= signed_mantissa; givb: IF (116-decimal-mantissa_width+1 > 1) GENERATE input_vector(116-decimal-mantissa_width DOWNTO 1) <= zerovec(116-decimal-mantissa_width DOWNTO 1); END GENERATE; gcxa: FOR k IN 1 TO exponent_width GENERATE negexponent(k) <= NOT(exponent(k)); END GENERATE; gcxb: FOR k IN 1 TO exponent_width-1 GENERATE expbase(k) <= '1'; negexpbase(k) <= '0'; END GENERATE; expbase(exponent_width) <= '0'; negexpbase(exponent_width) <= '1'; sublx: dp_addpipe GENERIC MAP (width=>exponent_width,pipes=>speed+1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>exponent,bb=>negexpbase, carryin=>'1', cc=>leftshift); subrx: dp_addpipe GENERIC MAP (width=>exponent_width,pipes=>speed+1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>negexponent,bb=>expbase, carryin=>'1', cc=>rightshift); --*** LEVEL 2-4 (shiftbusff) *** -- level 2 if speed = 0 -- level 4 if speed = 1 gsfa: IF (speed = 0) GENERATE clsc: dp_lsft64x64 PORT MAP (inbus=>input_vector,shift=>leftshift(6 DOWNTO 1), outbus=>leftbus); crsc: dp_rsft64x64 PORT MAP (inbus=>input_vector,shift=>rightshift(6 DOWNTO 1), outbus=>rightbus); select_bit <= leftshift(exponent_width); END GENERATE; gsfb: IF (speed = 1) GENERATE clsp: dp_lsftpipe64x64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>input_vector,shift=>leftshift(6 DOWNTO 1), outbus=>leftbus); crsp: dp_rsftpipe64x64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>input_vector,shift=>rightshift(6 DOWNTO 1), outbus=>rightbus); db: fp_delbit GENERIC MAP (pipes=>1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>leftshift(exponent_width), cc=>select_bit); END GENERATE; gsba: FOR k IN 1 TO fixed_width GENERATE shiftbus(k) <= (leftbus(116-fixed_width+k) AND NOT(select_bit)) OR (rightbus(116-fixed_width+k) AND select_bit); END GENERATE; psa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO fixed_width LOOP shiftbusff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN shiftbusff <= shiftbus; END IF; END IF; END PROCESS; --*** LEVEL 3-5 *** -- level 3 if speed = 0 -- level 5 if speed = 1 gou: IF (unsigned = 0) GENERATE poa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO fixed_width LOOP fixed_numberff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO fixed_width LOOP fixed_numberff(k) <= (shiftbusff(k) AND NOT(zero_apply)) OR saturate_apply; END LOOP; END IF; END IF; END PROCESS; END GENERATE; gos: IF (unsigned = 1) GENERATE pos: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO fixed_width LOOP fixed_numberff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO fixed_width-1 LOOP fixed_numberff(k) <= (shiftbusff(k) AND NOT(zero_apply) AND NOT(saturate_apply AND sign_apply)) OR (saturate_apply AND NOT(sign_apply)); END LOOP; fixed_numberff(fixed_width) <= (shiftbusff(fixed_width) AND NOT(zero_apply) AND NOT(saturate_apply AND NOT(sign_apply))) OR (saturate_apply AND sign_apply); END IF; END IF; END PROCESS; END GENERATE; fixed_number <= fixed_numberff; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/dp_explutneg.vhd

10

140760

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_EXPLUTNEG.VHD *** --*** *** --*** Function: Look Up Table - EXP() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_explutneg IS PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); manhi : OUT STD_LOGIC_VECTOR (24 DOWNTO 1); manlo : OUT STD_LOGIC_VECTOR (28 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_explutneg; ARCHITECTURE rtl OF dp_explutneg IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000000" => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(1023,11); WHEN "0000000001" => manhi <= conv_std_logic_vector(7910755,24); manlo <= conv_std_logic_vector(103608120,28); exponent <= conv_std_logic_vector(1021,11); WHEN "0000000010" => manhi <= conv_std_logic_vector(1387178,24); manlo <= conv_std_logic_vector(62882252,28); exponent <= conv_std_logic_vector(1020,11); WHEN "0000000011" => manhi <= conv_std_logic_vector(9952012,24); manlo <= conv_std_logic_vector(214872239,28); exponent <= conv_std_logic_vector(1018,11); WHEN "0000000100" => manhi <= conv_std_logic_vector(2889051,24); manlo <= conv_std_logic_vector(136396020,28); exponent <= conv_std_logic_vector(1017,11); WHEN "0000000101" => manhi <= conv_std_logic_vector(12162046,24); manlo <= conv_std_logic_vector(873334,28); exponent <= conv_std_logic_vector(1015,11); WHEN "0000000110" => manhi <= conv_std_logic_vector(4515103,24); manlo <= conv_std_logic_vector(18076886,28); exponent <= conv_std_logic_vector(1014,11); WHEN "0000000111" => manhi <= conv_std_logic_vector(14554809,24); manlo <= conv_std_logic_vector(203729295,28); exponent <= conv_std_logic_vector(1012,11); WHEN "0000001000" => manhi <= conv_std_logic_vector(6275600,24); manlo <= conv_std_logic_vector(68167597,28); exponent <= conv_std_logic_vector(1011,11); WHEN "0000001001" => manhi <= conv_std_logic_vector(184098,24); manlo <= conv_std_logic_vector(86398042,28); exponent <= conv_std_logic_vector(1010,11); WHEN "0000001010" => manhi <= conv_std_logic_vector(8181659,24); manlo <= conv_std_logic_vector(90471578,28); exponent <= conv_std_logic_vector(1008,11); WHEN "0000001011" => manhi <= conv_std_logic_vector(1586498,24); manlo <= conv_std_logic_vector(59729764,28); exponent <= conv_std_logic_vector(1007,11); WHEN "0000001100" => manhi <= conv_std_logic_vector(10245315,24); manlo <= conv_std_logic_vector(188988555,28); exponent <= conv_std_logic_vector(1005,11); WHEN "0000001101" => manhi <= conv_std_logic_vector(3104851,24); manlo <= conv_std_logic_vector(194518424,28); exponent <= conv_std_logic_vector(1004,11); WHEN "0000001110" => manhi <= conv_std_logic_vector(12479599,24); manlo <= conv_std_logic_vector(229643794,28); exponent <= conv_std_logic_vector(1002,11); WHEN "0000001111" => manhi <= conv_std_logic_vector(4748746,24); manlo <= conv_std_logic_vector(36170808,28); exponent <= conv_std_logic_vector(1001,11); WHEN "0000010000" => manhi <= conv_std_logic_vector(14898619,24); manlo <= conv_std_logic_vector(183403979,28); exponent <= conv_std_logic_vector(999,11); WHEN "0000010001" => manhi <= conv_std_logic_vector(6528561,24); manlo <= conv_std_logic_vector(123365533,28); exponent <= conv_std_logic_vector(998,11); WHEN "0000010010" => manhi <= conv_std_logic_vector(370216,24); manlo <= conv_std_logic_vector(208248737,28); exponent <= conv_std_logic_vector(997,11); WHEN "0000010011" => manhi <= conv_std_logic_vector(8455535,24); manlo <= conv_std_logic_vector(254564210,28); exponent <= conv_std_logic_vector(995,11); WHEN "0000010100" => manhi <= conv_std_logic_vector(1788005,24); manlo <= conv_std_logic_vector(99840615,28); exponent <= conv_std_logic_vector(994,11); WHEN "0000010101" => manhi <= conv_std_logic_vector(10541837,24); manlo <= conv_std_logic_vector(14529516,28); exponent <= conv_std_logic_vector(992,11); WHEN "0000010110" => manhi <= conv_std_logic_vector(3323019,24); manlo <= conv_std_logic_vector(252804514,28); exponent <= conv_std_logic_vector(991,11); WHEN "0000010111" => manhi <= conv_std_logic_vector(12800638,24); manlo <= conv_std_logic_vector(70515377,28); exponent <= conv_std_logic_vector(989,11); WHEN "0000011000" => manhi <= conv_std_logic_vector(4984952,24); manlo <= conv_std_logic_vector(266936970,28); exponent <= conv_std_logic_vector(988,11); WHEN "0000011001" => manhi <= conv_std_logic_vector(15246202,24); manlo <= conv_std_logic_vector(73384750,28); exponent <= conv_std_logic_vector(986,11); WHEN "0000011010" => manhi <= conv_std_logic_vector(6784298,24); manlo <= conv_std_logic_vector(117472834,28); exponent <= conv_std_logic_vector(985,11); WHEN "0000011011" => manhi <= conv_std_logic_vector(558377,24); manlo <= conv_std_logic_vector(141983386,28); exponent <= conv_std_logic_vector(984,11); WHEN "0000011100" => manhi <= conv_std_logic_vector(8732417,24); manlo <= conv_std_logic_vector(225268666,28); exponent <= conv_std_logic_vector(982,11); WHEN "0000011101" => manhi <= conv_std_logic_vector(1991723,24); manlo <= conv_std_logic_vector(183207072,28); exponent <= conv_std_logic_vector(981,11); WHEN "0000011110" => manhi <= conv_std_logic_vector(10841612,24); manlo <= conv_std_logic_vector(44859253,28); exponent <= conv_std_logic_vector(979,11); WHEN "0000011111" => manhi <= conv_std_logic_vector(3543582,24); manlo <= conv_std_logic_vector(38615994,28); exponent <= conv_std_logic_vector(978,11); WHEN "0000100000" => manhi <= conv_std_logic_vector(13125199,24); manlo <= conv_std_logic_vector(123823208,28); exponent <= conv_std_logic_vector(976,11); WHEN "0000100001" => manhi <= conv_std_logic_vector(5223751,24); manlo <= conv_std_logic_vector(209149352,28); exponent <= conv_std_logic_vector(975,11); WHEN "0000100010" => manhi <= conv_std_logic_vector(15597598,24); manlo <= conv_std_logic_vector(248916640,28); exponent <= conv_std_logic_vector(973,11); WHEN "0000100011" => manhi <= conv_std_logic_vector(7042841,24); manlo <= conv_std_logic_vector(173666528,28); exponent <= conv_std_logic_vector(972,11); WHEN "0000100100" => manhi <= conv_std_logic_vector(748602,24); manlo <= conv_std_logic_vector(266199140,28); exponent <= conv_std_logic_vector(971,11); WHEN "0000100101" => manhi <= conv_std_logic_vector(9012337,24); manlo <= conv_std_logic_vector(264921173,28); exponent <= conv_std_logic_vector(969,11); WHEN "0000100110" => manhi <= conv_std_logic_vector(2197677,24); manlo <= conv_std_logic_vector(112079619,28); exponent <= conv_std_logic_vector(968,11); WHEN "0000100111" => manhi <= conv_std_logic_vector(11144676,24); manlo <= conv_std_logic_vector(200497976,28); exponent <= conv_std_logic_vector(966,11); WHEN "0000101000" => manhi <= conv_std_logic_vector(3766564,24); manlo <= conv_std_logic_vector(161159716,28); exponent <= conv_std_logic_vector(965,11); WHEN "0000101001" => manhi <= conv_std_logic_vector(13453322,24); manlo <= conv_std_logic_vector(28788768,28); exponent <= conv_std_logic_vector(963,11); WHEN "0000101010" => manhi <= conv_std_logic_vector(5465170,24); manlo <= conv_std_logic_vector(249755484,28); exponent <= conv_std_logic_vector(962,11); WHEN "0000101011" => manhi <= conv_std_logic_vector(15952851,24); manlo <= conv_std_logic_vector(133443390,28); exponent <= conv_std_logic_vector(960,11); WHEN "0000101100" => manhi <= conv_std_logic_vector(7304221,24); manlo <= conv_std_logic_vector(236407020,28); exponent <= conv_std_logic_vector(959,11); WHEN "0000101101" => manhi <= conv_std_logic_vector(940915,24); manlo <= conv_std_logic_vector(220198205,28); exponent <= conv_std_logic_vector(958,11); WHEN "0000101110" => manhi <= conv_std_logic_vector(9295329,24); manlo <= conv_std_logic_vector(196124030,28); exponent <= conv_std_logic_vector(956,11); WHEN "0000101111" => manhi <= conv_std_logic_vector(2405891,24); manlo <= conv_std_logic_vector(28613594,28); exponent <= conv_std_logic_vector(955,11); WHEN "0000110000" => manhi <= conv_std_logic_vector(11451066,24); manlo <= conv_std_logic_vector(238698933,28); exponent <= conv_std_logic_vector(953,11); WHEN "0000110001" => manhi <= conv_std_logic_vector(3991993,24); manlo <= conv_std_logic_vector(233279365,28); exponent <= conv_std_logic_vector(952,11); WHEN "0000110010" => manhi <= conv_std_logic_vector(13785045,24); manlo <= conv_std_logic_vector(75368511,28); exponent <= conv_std_logic_vector(950,11); WHEN "0000110011" => manhi <= conv_std_logic_vector(5709239,24); manlo <= conv_std_logic_vector(54173026,28); exponent <= conv_std_logic_vector(949,11); WHEN "0000110100" => manhi <= conv_std_logic_vector(16312002,24); manlo <= conv_std_logic_vector(78993710,28); exponent <= conv_std_logic_vector(947,11); WHEN "0000110101" => manhi <= conv_std_logic_vector(7568470,24); manlo <= conv_std_logic_vector(72422582,28); exponent <= conv_std_logic_vector(946,11); WHEN "0000110110" => manhi <= conv_std_logic_vector(1135338,24); manlo <= conv_std_logic_vector(246889480,28); exponent <= conv_std_logic_vector(945,11); WHEN "0000110111" => manhi <= conv_std_logic_vector(9581426,24); manlo <= conv_std_logic_vector(208117876,28); exponent <= conv_std_logic_vector(943,11); WHEN "0000111000" => manhi <= conv_std_logic_vector(2616389,24); manlo <= conv_std_logic_vector(147217980,28); exponent <= conv_std_logic_vector(942,11); WHEN "0000111001" => manhi <= conv_std_logic_vector(11760819,24); manlo <= conv_std_logic_vector(23037889,28); exponent <= conv_std_logic_vector(940,11); WHEN "0000111010" => manhi <= conv_std_logic_vector(4219896,24); manlo <= conv_std_logic_vector(214481816,28); exponent <= conv_std_logic_vector(939,11); WHEN "0000111011" => manhi <= conv_std_logic_vector(14120408,24); manlo <= conv_std_logic_vector(131761485,28); exponent <= conv_std_logic_vector(937,11); WHEN "0000111100" => manhi <= conv_std_logic_vector(5955985,24); manlo <= conv_std_logic_vector(177821786,28); exponent <= conv_std_logic_vector(936,11); WHEN "0000111101" => manhi <= conv_std_logic_vector(16675094,24); manlo <= conv_std_logic_vector(25356748,28); exponent <= conv_std_logic_vector(934,11); WHEN "0000111110" => manhi <= conv_std_logic_vector(7835618,24); manlo <= conv_std_logic_vector(77011020,28); exponent <= conv_std_logic_vector(933,11); WHEN "0000111111" => manhi <= conv_std_logic_vector(1331895,24); manlo <= conv_std_logic_vector(119779026,28); exponent <= conv_std_logic_vector(932,11); WHEN "0001000000" => manhi <= conv_std_logic_vector(9870663,24); manlo <= conv_std_logic_vector(52552908,28); exponent <= conv_std_logic_vector(930,11); WHEN "0001000001" => manhi <= conv_std_logic_vector(2829197,24); manlo <= conv_std_logic_vector(218477336,28); exponent <= conv_std_logic_vector(929,11); WHEN "0001000010" => manhi <= conv_std_logic_vector(12073970,24); manlo <= conv_std_logic_vector(61450731,28); exponent <= conv_std_logic_vector(927,11); WHEN "0001000011" => manhi <= conv_std_logic_vector(4450300,24); manlo <= conv_std_logic_vector(143360086,28); exponent <= conv_std_logic_vector(926,11); WHEN "0001000100" => manhi <= conv_std_logic_vector(14459451,24); manlo <= conv_std_logic_vector(182543396,28); exponent <= conv_std_logic_vector(924,11); WHEN "0001000101" => manhi <= conv_std_logic_vector(6205439,24); manlo <= conv_std_logic_vector(188004913,28); exponent <= conv_std_logic_vector(923,11); WHEN "0001000110" => manhi <= conv_std_logic_vector(132477,24); manlo <= conv_std_logic_vector(19160299,28); exponent <= conv_std_logic_vector(922,11); WHEN "0001000111" => manhi <= conv_std_logic_vector(8105697,24); manlo <= conv_std_logic_vector(201304075,28); exponent <= conv_std_logic_vector(920,11); WHEN "0001001000" => manhi <= conv_std_logic_vector(1530608,24); manlo <= conv_std_logic_vector(217452229,28); exponent <= conv_std_logic_vector(919,11); WHEN "0001001001" => manhi <= conv_std_logic_vector(10163073,24); manlo <= conv_std_logic_vector(118320126,28); exponent <= conv_std_logic_vector(917,11); WHEN "0001001010" => manhi <= conv_std_logic_vector(3044341,24); manlo <= conv_std_logic_vector(66824260,28); exponent <= conv_std_logic_vector(916,11); WHEN "0001001011" => manhi <= conv_std_logic_vector(12390557,24); manlo <= conv_std_logic_vector(165235674,28); exponent <= conv_std_logic_vector(914,11); WHEN "0001001100" => manhi <= conv_std_logic_vector(4683232,24); manlo <= conv_std_logic_vector(138461149,28); exponent <= conv_std_logic_vector(913,11); WHEN "0001001101" => manhi <= conv_std_logic_vector(14802215,24); manlo <= conv_std_logic_vector(61508170,28); exponent <= conv_std_logic_vector(911,11); WHEN "0001001110" => manhi <= conv_std_logic_vector(6457631,24); manlo <= conv_std_logic_vector(7025744,28); exponent <= conv_std_logic_vector(910,11); WHEN "0001001111" => manhi <= conv_std_logic_vector(318029,24); manlo <= conv_std_logic_vector(21309721,28); exponent <= conv_std_logic_vector(909,11); WHEN "0001010000" => manhi <= conv_std_logic_vector(8378740,24); manlo <= conv_std_logic_vector(221720132,28); exponent <= conv_std_logic_vector(907,11); WHEN "0001010001" => manhi <= conv_std_logic_vector(1731502,24); manlo <= conv_std_logic_vector(182144977,28); exponent <= conv_std_logic_vector(906,11); WHEN "0001010010" => manhi <= conv_std_logic_vector(10458692,24); manlo <= conv_std_logic_vector(90475423,28); exponent <= conv_std_logic_vector(904,11); WHEN "0001010011" => manhi <= conv_std_logic_vector(3261845,24); manlo <= conv_std_logic_vector(128220642,28); exponent <= conv_std_logic_vector(903,11); WHEN "0001010100" => manhi <= conv_std_logic_vector(12710618,24); manlo <= conv_std_logic_vector(255552070,28); exponent <= conv_std_logic_vector(901,11); WHEN "0001010101" => manhi <= conv_std_logic_vector(4918720,24); manlo <= conv_std_logic_vector(130727832,28); exponent <= conv_std_logic_vector(900,11); WHEN "0001010110" => manhi <= conv_std_logic_vector(15148739,24); manlo <= conv_std_logic_vector(258265342,28); exponent <= conv_std_logic_vector(898,11); WHEN "0001010111" => manhi <= conv_std_logic_vector(6712589,24); manlo <= conv_std_logic_vector(181573149,28); exponent <= conv_std_logic_vector(897,11); WHEN "0001011000" => manhi <= conv_std_logic_vector(505617,24); manlo <= conv_std_logic_vector(45883390,28); exponent <= conv_std_logic_vector(896,11); WHEN "0001011001" => manhi <= conv_std_logic_vector(8654780,24); manlo <= conv_std_logic_vector(9428106,28); exponent <= conv_std_logic_vector(894,11); WHEN "0001011010" => manhi <= conv_std_logic_vector(1934600,24); manlo <= conv_std_logic_vector(262677610,28); exponent <= conv_std_logic_vector(893,11); WHEN "0001011011" => manhi <= conv_std_logic_vector(10757555,24); manlo <= conv_std_logic_vector(25094861,28); exponent <= conv_std_logic_vector(891,11); WHEN "0001011100" => manhi <= conv_std_logic_vector(3481736,24); manlo <= conv_std_logic_vector(108799619,28); exponent <= conv_std_logic_vector(890,11); WHEN "0001011101" => manhi <= conv_std_logic_vector(13034192,24); manlo <= conv_std_logic_vector(96190464,28); exponent <= conv_std_logic_vector(888,11); WHEN "0001011110" => manhi <= conv_std_logic_vector(5156792,24); manlo <= conv_std_logic_vector(132821234,28); exponent <= conv_std_logic_vector(887,11); WHEN "0001011111" => manhi <= conv_std_logic_vector(15499067,24); manlo <= conv_std_logic_vector(40497064,28); exponent <= conv_std_logic_vector(885,11); WHEN "0001100000" => manhi <= conv_std_logic_vector(6970346,24); manlo <= conv_std_logic_vector(4633646,28); exponent <= conv_std_logic_vector(884,11); WHEN "0001100001" => manhi <= conv_std_logic_vector(695263,24); manlo <= conv_std_logic_vector(184734272,28); exponent <= conv_std_logic_vector(883,11); WHEN "0001100010" => manhi <= conv_std_logic_vector(8933848,24); manlo <= conv_std_logic_vector(68258056,28); exponent <= conv_std_logic_vector(881,11); WHEN "0001100011" => manhi <= conv_std_logic_vector(2139927,24); manlo <= conv_std_logic_vector(241478077,28); exponent <= conv_std_logic_vector(880,11); WHEN "0001100100" => manhi <= conv_std_logic_vector(11059697,24); manlo <= conv_std_logic_vector(81964893,28); exponent <= conv_std_logic_vector(878,11); WHEN "0001100101" => manhi <= conv_std_logic_vector(3704040,24); manlo <= conv_std_logic_vector(59435624,28); exponent <= conv_std_logic_vector(877,11); WHEN "0001100110" => manhi <= conv_std_logic_vector(13361316,24); manlo <= conv_std_logic_vector(100097713,28); exponent <= conv_std_logic_vector(875,11); WHEN "0001100111" => manhi <= conv_std_logic_vector(5397476,24); manlo <= conv_std_logic_vector(240017437,28); exponent <= conv_std_logic_vector(874,11); WHEN "0001101000" => manhi <= conv_std_logic_vector(15853238,24); manlo <= conv_std_logic_vector(139632179,28); exponent <= conv_std_logic_vector(872,11); WHEN "0001101001" => manhi <= conv_std_logic_vector(7230930,24); manlo <= conv_std_logic_vector(200816807,28); exponent <= conv_std_logic_vector(871,11); WHEN "0001101010" => manhi <= conv_std_logic_vector(886991,24); manlo <= conv_std_logic_vector(58654941,28); exponent <= conv_std_logic_vector(870,11); WHEN "0001101011" => manhi <= conv_std_logic_vector(9215978,24); manlo <= conv_std_logic_vector(193575030,28); exponent <= conv_std_logic_vector(868,11); WHEN "0001101100" => manhi <= conv_std_logic_vector(2347507,24); manlo <= conv_std_logic_vector(240661664,28); exponent <= conv_std_logic_vector(867,11); WHEN "0001101101" => manhi <= conv_std_logic_vector(11365154,24); manlo <= conv_std_logic_vector(257284930,28); exponent <= conv_std_logic_vector(865,11); WHEN "0001101110" => manhi <= conv_std_logic_vector(3928783,24); manlo <= conv_std_logic_vector(108146246,28); exponent <= conv_std_logic_vector(864,11); WHEN "0001101111" => manhi <= conv_std_logic_vector(13692029,24); manlo <= conv_std_logic_vector(256867284,28); exponent <= conv_std_logic_vector(862,11); WHEN "0001110000" => manhi <= conv_std_logic_vector(5640802,24); manlo <= conv_std_logic_vector(94243132,28); exponent <= conv_std_logic_vector(861,11); WHEN "0001110001" => manhi <= conv_std_logic_vector(16211296,24); manlo <= conv_std_logic_vector(67825654,28); exponent <= conv_std_logic_vector(859,11); WHEN "0001110010" => manhi <= conv_std_logic_vector(7494374,24); manlo <= conv_std_logic_vector(242982196,28); exponent <= conv_std_logic_vector(858,11); WHEN "0001110011" => manhi <= conv_std_logic_vector(1080822,24); manlo <= conv_std_logic_vector(160277009,28); exponent <= conv_std_logic_vector(857,11); WHEN "0001110100" => manhi <= conv_std_logic_vector(9501205,24); manlo <= conv_std_logic_vector(10212621,28); exponent <= conv_std_logic_vector(855,11); WHEN "0001110101" => manhi <= conv_std_logic_vector(2557365,24); manlo <= conv_std_logic_vector(185941944,28); exponent <= conv_std_logic_vector(854,11); WHEN "0001110110" => manhi <= conv_std_logic_vector(11673964,24); manlo <= conv_std_logic_vector(116382402,28); exponent <= conv_std_logic_vector(852,11); WHEN "0001110111" => manhi <= conv_std_logic_vector(4155992,24); manlo <= conv_std_logic_vector(192503267,28); exponent <= conv_std_logic_vector(851,11); WHEN "0001111000" => manhi <= conv_std_logic_vector(14026372,24); manlo <= conv_std_logic_vector(133984890,28); exponent <= conv_std_logic_vector(849,11); WHEN "0001111001" => manhi <= conv_std_logic_vector(5886797,24); manlo <= conv_std_logic_vector(227169396,28); exponent <= conv_std_logic_vector(848,11); WHEN "0001111010" => manhi <= conv_std_logic_vector(16573282,24); manlo <= conv_std_logic_vector(266790864,28); exponent <= conv_std_logic_vector(846,11); WHEN "0001111011" => manhi <= conv_std_logic_vector(7760709,24); manlo <= conv_std_logic_vector(232279832,28); exponent <= conv_std_logic_vector(845,11); WHEN "0001111100" => manhi <= conv_std_logic_vector(1276780,24); manlo <= conv_std_logic_vector(244188460,28); exponent <= conv_std_logic_vector(844,11); WHEN "0001111101" => manhi <= conv_std_logic_vector(9789561,24); manlo <= conv_std_logic_vector(47289108,28); exponent <= conv_std_logic_vector(842,11); WHEN "0001111110" => manhi <= conv_std_logic_vector(2769526,24); manlo <= conv_std_logic_vector(75856665,28); exponent <= conv_std_logic_vector(841,11); WHEN "0001111111" => manhi <= conv_std_logic_vector(11986162,24); manlo <= conv_std_logic_vector(137053172,28); exponent <= conv_std_logic_vector(839,11); WHEN "0010000000" => manhi <= conv_std_logic_vector(4385695,24); manlo <= conv_std_logic_vector(60488459,28); exponent <= conv_std_logic_vector(838,11); WHEN "0010000001" => manhi <= conv_std_logic_vector(14364383,24); manlo <= conv_std_logic_vector(220265084,28); exponent <= conv_std_logic_vector(836,11); WHEN "0010000010" => manhi <= conv_std_logic_vector(6135492,24); manlo <= conv_std_logic_vector(182090040,28); exponent <= conv_std_logic_vector(835,11); WHEN "0010000011" => manhi <= conv_std_logic_vector(81012,24); manlo <= conv_std_logic_vector(249275143,28); exponent <= conv_std_logic_vector(834,11); WHEN "0010000100" => manhi <= conv_std_logic_vector(8029967,24); manlo <= conv_std_logic_vector(93846972,28); exponent <= conv_std_logic_vector(832,11); WHEN "0010000101" => manhi <= conv_std_logic_vector(1474889,24); manlo <= conv_std_logic_vector(132978099,28); exponent <= conv_std_logic_vector(831,11); WHEN "0010000110" => manhi <= conv_std_logic_vector(10081081,24); manlo <= conv_std_logic_vector(128680817,28); exponent <= conv_std_logic_vector(829,11); WHEN "0010000111" => manhi <= conv_std_logic_vector(2984014,24); manlo <= conv_std_logic_vector(251002315,28); exponent <= conv_std_logic_vector(828,11); WHEN "0010001000" => manhi <= conv_std_logic_vector(12301786,24); manlo <= conv_std_logic_vector(100124707,28); exponent <= conv_std_logic_vector(826,11); WHEN "0010001001" => manhi <= conv_std_logic_vector(4617918,24); manlo <= conv_std_logic_vector(76665129,28); exponent <= conv_std_logic_vector(825,11); WHEN "0010001010" => manhi <= conv_std_logic_vector(14706104,24); manlo <= conv_std_logic_vector(48076192,28); exponent <= conv_std_logic_vector(823,11); WHEN "0010001011" => manhi <= conv_std_logic_vector(6386916,24); manlo <= conv_std_logic_vector(125471070,28); exponent <= conv_std_logic_vector(822,11); WHEN "0010001100" => manhi <= conv_std_logic_vector(266000,24); manlo <= conv_std_logic_vector(57624675,28); exponent <= conv_std_logic_vector(821,11); WHEN "0010001101" => manhi <= conv_std_logic_vector(8302179,24); manlo <= conv_std_logic_vector(114693198,28); exponent <= conv_std_logic_vector(819,11); WHEN "0010001110" => manhi <= conv_std_logic_vector(1675171,24); manlo <= conv_std_logic_vector(254852645,28); exponent <= conv_std_logic_vector(818,11); WHEN "0010001111" => manhi <= conv_std_logic_vector(10375800,24); manlo <= conv_std_logic_vector(179426511,28); exponent <= conv_std_logic_vector(816,11); WHEN "0010010000" => manhi <= conv_std_logic_vector(3200857,24); manlo <= conv_std_logic_vector(52664716,28); exponent <= conv_std_logic_vector(815,11); WHEN "0010010001" => manhi <= conv_std_logic_vector(12620873,24); manlo <= conv_std_logic_vector(164386702,28); exponent <= conv_std_logic_vector(813,11); WHEN "0010010010" => manhi <= conv_std_logic_vector(4852689,24); manlo <= conv_std_logic_vector(149310968,28); exponent <= conv_std_logic_vector(812,11); WHEN "0010010011" => manhi <= conv_std_logic_vector(15051574,24); manlo <= conv_std_logic_vector(73675604,28); exponent <= conv_std_logic_vector(810,11); WHEN "0010010100" => manhi <= conv_std_logic_vector(6641099,24); manlo <= conv_std_logic_vector(42591307,28); exponent <= conv_std_logic_vector(809,11); WHEN "0010010101" => manhi <= conv_std_logic_vector(453017,24); manlo <= conv_std_logic_vector(104016801,28); exponent <= conv_std_logic_vector(808,11); WHEN "0010010110" => manhi <= conv_std_logic_vector(8577378,24); manlo <= conv_std_logic_vector(139419332,28); exponent <= conv_std_logic_vector(806,11); WHEN "0010010111" => manhi <= conv_std_logic_vector(1877652,24); manlo <= conv_std_logic_vector(33778363,28); exponent <= conv_std_logic_vector(805,11); WHEN "0010011000" => manhi <= conv_std_logic_vector(10673753,24); manlo <= conv_std_logic_vector(226837452,28); exponent <= conv_std_logic_vector(803,11); WHEN "0010011001" => manhi <= conv_std_logic_vector(3420078,24); manlo <= conv_std_logic_vector(239554874,28); exponent <= conv_std_logic_vector(802,11); WHEN "0010011010" => manhi <= conv_std_logic_vector(12943462,24); manlo <= conv_std_logic_vector(62486566,28); exponent <= conv_std_logic_vector(800,11); WHEN "0010011011" => manhi <= conv_std_logic_vector(5090036,24); manlo <= conv_std_logic_vector(268173235,28); exponent <= conv_std_logic_vector(799,11); WHEN "0010011100" => manhi <= conv_std_logic_vector(15400835,24); manlo <= conv_std_logic_vector(67898261,28); exponent <= conv_std_logic_vector(797,11); WHEN "0010011101" => manhi <= conv_std_logic_vector(6898071,24); manlo <= conv_std_logic_vector(6935226,28); exponent <= conv_std_logic_vector(796,11); WHEN "0010011110" => manhi <= conv_std_logic_vector(642086,24); manlo <= conv_std_logic_vector(193616024,28); exponent <= conv_std_logic_vector(795,11); WHEN "0010011111" => manhi <= conv_std_logic_vector(8855597,24); manlo <= conv_std_logic_vector(108124901,28); exponent <= conv_std_logic_vector(793,11); WHEN "0010100000" => manhi <= conv_std_logic_vector(2082354,24); manlo <= conv_std_logic_vector(37727361,28); exponent <= conv_std_logic_vector(792,11); WHEN "0010100001" => manhi <= conv_std_logic_vector(10974976,24); manlo <= conv_std_logic_vector(133184200,28); exponent <= conv_std_logic_vector(790,11); WHEN "0010100010" => manhi <= conv_std_logic_vector(3641706,24); manlo <= conv_std_logic_vector(35844662,28); exponent <= conv_std_logic_vector(789,11); WHEN "0010100011" => manhi <= conv_std_logic_vector(13269590,24); manlo <= conv_std_logic_vector(175886280,28); exponent <= conv_std_logic_vector(787,11); WHEN "0010100100" => manhi <= conv_std_logic_vector(5329988,24); manlo <= conv_std_logic_vector(236927280,28); exponent <= conv_std_logic_vector(786,11); WHEN "0010100101" => manhi <= conv_std_logic_vector(15753928,24); manlo <= conv_std_logic_vector(191213976,28); exponent <= conv_std_logic_vector(784,11); WHEN "0010100110" => manhi <= conv_std_logic_vector(7157862,24); manlo <= conv_std_logic_vector(181160855,28); exponent <= conv_std_logic_vector(783,11); WHEN "0010100111" => manhi <= conv_std_logic_vector(833230,24); manlo <= conv_std_logic_vector(197197075,28); exponent <= conv_std_logic_vector(782,11); WHEN "0010101000" => manhi <= conv_std_logic_vector(9136869,24); manlo <= conv_std_logic_vector(57456047,28); exponent <= conv_std_logic_vector(780,11); WHEN "0010101001" => manhi <= conv_std_logic_vector(2289302,24); manlo <= conv_std_logic_vector(100400411,28); exponent <= conv_std_logic_vector(779,11); WHEN "0010101010" => manhi <= conv_std_logic_vector(11279504,24); manlo <= conv_std_logic_vector(133702078,28); exponent <= conv_std_logic_vector(777,11); WHEN "0010101011" => manhi <= conv_std_logic_vector(3865765,24); manlo <= conv_std_logic_vector(84791606,28); exponent <= conv_std_logic_vector(776,11); WHEN "0010101100" => manhi <= conv_std_logic_vector(13599297,24); manlo <= conv_std_logic_vector(193913492,28); exponent <= conv_std_logic_vector(774,11); WHEN "0010101101" => manhi <= conv_std_logic_vector(5572573,24); manlo <= conv_std_logic_vector(210951234,28); exponent <= conv_std_logic_vector(773,11); WHEN "0010101110" => manhi <= conv_std_logic_vector(16110896,24); manlo <= conv_std_logic_vector(189751005,28); exponent <= conv_std_logic_vector(771,11); WHEN "0010101111" => manhi <= conv_std_logic_vector(7420505,24); manlo <= conv_std_logic_vector(12771910,28); exponent <= conv_std_logic_vector(770,11); WHEN "0010110000" => manhi <= conv_std_logic_vector(1026472,24); manlo <= conv_std_logic_vector(51864863,28); exponent <= conv_std_logic_vector(769,11); WHEN "0010110001" => manhi <= conv_std_logic_vector(9421227,24); manlo <= conv_std_logic_vector(121664951,28); exponent <= conv_std_logic_vector(767,11); WHEN "0010110010" => manhi <= conv_std_logic_vector(2498521,24); manlo <= conv_std_logic_vector(127312793,28); exponent <= conv_std_logic_vector(766,11); WHEN "0010110011" => manhi <= conv_std_logic_vector(11587374,24); manlo <= conv_std_logic_vector(32431827,28); exponent <= conv_std_logic_vector(764,11); WHEN "0010110100" => manhi <= conv_std_logic_vector(4092283,24); manlo <= conv_std_logic_vector(33663701,28); exponent <= conv_std_logic_vector(763,11); WHEN "0010110101" => manhi <= conv_std_logic_vector(13932622,24); manlo <= conv_std_logic_vector(188745186,28); exponent <= conv_std_logic_vector(761,11); WHEN "0010110110" => manhi <= conv_std_logic_vector(5817820,24); manlo <= conv_std_logic_vector(161368804,28); exponent <= conv_std_logic_vector(760,11); WHEN "0010110111" => manhi <= conv_std_logic_vector(16471781,24); manlo <= conv_std_logic_vector(201946939,28); exponent <= conv_std_logic_vector(758,11); WHEN "0010111000" => manhi <= conv_std_logic_vector(7686029,24); manlo <= conv_std_logic_vector(114155240,28); exponent <= conv_std_logic_vector(757,11); WHEN "0010111001" => manhi <= conv_std_logic_vector(1221834,24); manlo <= conv_std_logic_vector(30217784,28); exponent <= conv_std_logic_vector(756,11); WHEN "0010111010" => manhi <= conv_std_logic_vector(9708705,24); manlo <= conv_std_logic_vector(265245416,28); exponent <= conv_std_logic_vector(754,11); WHEN "0010111011" => manhi <= conv_std_logic_vector(2710036,24); manlo <= conv_std_logic_vector(96582323,28); exponent <= conv_std_logic_vector(753,11); WHEN "0010111100" => manhi <= conv_std_logic_vector(11898622,24); manlo <= conv_std_logic_vector(8685564,28); exponent <= conv_std_logic_vector(751,11); WHEN "0010111101" => manhi <= conv_std_logic_vector(4321286,24); manlo <= conv_std_logic_vector(145205332,28); exponent <= conv_std_logic_vector(750,11); WHEN "0010111110" => manhi <= conv_std_logic_vector(14269605,24); manlo <= conv_std_logic_vector(79792252,28); exponent <= conv_std_logic_vector(748,11); WHEN "0010111111" => manhi <= conv_std_logic_vector(6065758,24); manlo <= conv_std_logic_vector(144408455,28); exponent <= conv_std_logic_vector(747,11); WHEN "0011000000" => manhi <= conv_std_logic_vector(29705,24); manlo <= conv_std_logic_vector(111518540,28); exponent <= conv_std_logic_vector(746,11); WHEN "0011000001" => manhi <= conv_std_logic_vector(7954467,24); manlo <= conv_std_logic_vector(116097284,28); exponent <= conv_std_logic_vector(744,11); WHEN "0011000010" => manhi <= conv_std_logic_vector(1419339,24); manlo <= conv_std_logic_vector(204212637,28); exponent <= conv_std_logic_vector(743,11); WHEN "0011000011" => manhi <= conv_std_logic_vector(9999339,24); manlo <= conv_std_logic_vector(15580207,28); exponent <= conv_std_logic_vector(741,11); WHEN "0011000100" => manhi <= conv_std_logic_vector(2923872,24); manlo <= conv_std_logic_vector(59726033,28); exponent <= conv_std_logic_vector(740,11); WHEN "0011000101" => manhi <= conv_std_logic_vector(12213285,24); manlo <= conv_std_logic_vector(81348195,28); exponent <= conv_std_logic_vector(738,11); WHEN "0011000110" => manhi <= conv_std_logic_vector(4552802,24); manlo <= conv_std_logic_vector(224758002,28); exponent <= conv_std_logic_vector(737,11); WHEN "0011000111" => manhi <= conv_std_logic_vector(14610285,24); manlo <= conv_std_logic_vector(171839647,28); exponent <= conv_std_logic_vector(735,11); WHEN "0011001000" => manhi <= conv_std_logic_vector(6316417,24); manlo <= conv_std_logic_vector(33901818,28); exponent <= conv_std_logic_vector(734,11); WHEN "0011001001" => manhi <= conv_std_logic_vector(214129,24); manlo <= conv_std_logic_vector(187432044,28); exponent <= conv_std_logic_vector(733,11); WHEN "0011001010" => manhi <= conv_std_logic_vector(8225851,24); manlo <= conv_std_logic_vector(10972428,28); exponent <= conv_std_logic_vector(731,11); WHEN "0011001011" => manhi <= conv_std_logic_vector(1619012,24); manlo <= conv_std_logic_vector(177473085,28); exponent <= conv_std_logic_vector(730,11); WHEN "0011001100" => manhi <= conv_std_logic_vector(10293161,24); manlo <= conv_std_logic_vector(74648462,28); exponent <= conv_std_logic_vector(728,11); WHEN "0011001101" => manhi <= conv_std_logic_vector(3140054,24); manlo <= conv_std_logic_vector(142465582,28); exponent <= conv_std_logic_vector(727,11); WHEN "0011001110" => manhi <= conv_std_logic_vector(12531401,24); manlo <= conv_std_logic_vector(110062606,28); exponent <= conv_std_logic_vector(725,11); WHEN "0011001111" => manhi <= conv_std_logic_vector(4786859,24); manlo <= conv_std_logic_vector(158003247,28); exponent <= conv_std_logic_vector(724,11); WHEN "0011010000" => manhi <= conv_std_logic_vector(14954704,24); manlo <= conv_std_logic_vector(82587752,28); exponent <= conv_std_logic_vector(722,11); WHEN "0011010001" => manhi <= conv_std_logic_vector(6569826,24); manlo <= conv_std_logic_vector(59098716,28); exponent <= conv_std_logic_vector(721,11); WHEN "0011010010" => manhi <= conv_std_logic_vector(400577,24); manlo <= conv_std_logic_vector(185198176,28); exponent <= conv_std_logic_vector(720,11); WHEN "0011010011" => manhi <= conv_std_logic_vector(8500212,24); manlo <= conv_std_logic_vector(153765179,28); exponent <= conv_std_logic_vector(718,11); WHEN "0011010100" => manhi <= conv_std_logic_vector(1820876,24); manlo <= conv_std_logic_vector(159783545,28); exponent <= conv_std_logic_vector(717,11); WHEN "0011010101" => manhi <= conv_std_logic_vector(10590207,24); manlo <= conv_std_logic_vector(172648734,28); exponent <= conv_std_logic_vector(715,11); WHEN "0011010110" => manhi <= conv_std_logic_vector(3358609,24); manlo <= conv_std_logic_vector(8670608,28); exponent <= conv_std_logic_vector(714,11); WHEN "0011010111" => manhi <= conv_std_logic_vector(12853008,24); manlo <= conv_std_logic_vector(64863304,28); exponent <= conv_std_logic_vector(712,11); WHEN "0011011000" => manhi <= conv_std_logic_vector(5023484,24); manlo <= conv_std_logic_vector(180279682,28); exponent <= conv_std_logic_vector(711,11); WHEN "0011011001" => manhi <= conv_std_logic_vector(15302902,24); manlo <= conv_std_logic_vector(86126918,28); exponent <= conv_std_logic_vector(709,11); WHEN "0011011010" => manhi <= conv_std_logic_vector(6826016,24); manlo <= conv_std_logic_vector(315265,28); exponent <= conv_std_logic_vector(708,11); WHEN "0011011011" => manhi <= conv_std_logic_vector(589071,24); manlo <= conv_std_logic_vector(160219440,28); exponent <= conv_std_logic_vector(707,11); WHEN "0011011100" => manhi <= conv_std_logic_vector(8777584,24); manlo <= conv_std_logic_vector(189361726,28); exponent <= conv_std_logic_vector(705,11); WHEN "0011011101" => manhi <= conv_std_logic_vector(2024955,24); manlo <= conv_std_logic_vector(162543151,28); exponent <= conv_std_logic_vector(704,11); WHEN "0011011110" => manhi <= conv_std_logic_vector(10890513,24); manlo <= conv_std_logic_vector(142859647,28); exponent <= conv_std_logic_vector(702,11); WHEN "0011011111" => manhi <= conv_std_logic_vector(3579561,24); manlo <= conv_std_logic_vector(203359193,28); exponent <= conv_std_logic_vector(701,11); WHEN "0011100000" => manhi <= conv_std_logic_vector(13178144,24); manlo <= conv_std_logic_vector(27387766,28); exponent <= conv_std_logic_vector(699,11); WHEN "0011100001" => manhi <= conv_std_logic_vector(5262706,24); manlo <= conv_std_logic_vector(72167880,28); exponent <= conv_std_logic_vector(698,11); WHEN "0011100010" => manhi <= conv_std_logic_vector(15654921,24); manlo <= conv_std_logic_vector(40507130,28); exponent <= conv_std_logic_vector(696,11); WHEN "0011100011" => manhi <= conv_std_logic_vector(7085016,24); manlo <= conv_std_logic_vector(263640644,28); exponent <= conv_std_logic_vector(695,11); WHEN "0011100100" => manhi <= conv_std_logic_vector(779633,24); manlo <= conv_std_logic_vector(233308885,28); exponent <= conv_std_logic_vector(694,11); WHEN "0011100101" => manhi <= conv_std_logic_vector(9058000,24); manlo <= conv_std_logic_vector(127336500,28); exponent <= conv_std_logic_vector(692,11); WHEN "0011100110" => manhi <= conv_std_logic_vector(2231273,24); manlo <= conv_std_logic_vector(267969878,28); exponent <= conv_std_logic_vector(691,11); WHEN "0011100111" => manhi <= conv_std_logic_vector(11194114,24); manlo <= conv_std_logic_vector(191206462,28); exponent <= conv_std_logic_vector(689,11); WHEN "0011101000" => manhi <= conv_std_logic_vector(3802939,24); manlo <= conv_std_logic_vector(6046440,28); exponent <= conv_std_logic_vector(688,11); WHEN "0011101001" => manhi <= conv_std_logic_vector(13506847,24); manlo <= conv_std_logic_vector(192101060,28); exponent <= conv_std_logic_vector(686,11); WHEN "0011101010" => manhi <= conv_std_logic_vector(5504552,24); manlo <= conv_std_logic_vector(234133234,28); exponent <= conv_std_logic_vector(685,11); WHEN "0011101011" => manhi <= conv_std_logic_vector(16010802,24); manlo <= conv_std_logic_vector(194370273,28); exponent <= conv_std_logic_vector(683,11); WHEN "0011101100" => manhi <= conv_std_logic_vector(7346860,24); manlo <= conv_std_logic_vector(2864438,28); exponent <= conv_std_logic_vector(682,11); WHEN "0011101101" => manhi <= conv_std_logic_vector(972287,24); manlo <= conv_std_logic_vector(54536955,28); exponent <= conv_std_logic_vector(681,11); WHEN "0011101110" => manhi <= conv_std_logic_vector(9341493,24); manlo <= conv_std_logic_vector(74572905,28); exponent <= conv_std_logic_vector(679,11); WHEN "0011101111" => manhi <= conv_std_logic_vector(2439856,24); manlo <= conv_std_logic_vector(93006730,28); exponent <= conv_std_logic_vector(678,11); WHEN "0011110000" => manhi <= conv_std_logic_vector(11501047,24); manlo <= conv_std_logic_vector(92098230,28); exponent <= conv_std_logic_vector(676,11); WHEN "0011110001" => manhi <= conv_std_logic_vector(4028767,24); manlo <= conv_std_logic_vector(115940390,28); exponent <= conv_std_logic_vector(675,11); WHEN "0011110010" => manhi <= conv_std_logic_vector(13839158,24); manlo <= conv_std_logic_vector(62227559,28); exponent <= conv_std_logic_vector(673,11); WHEN "0011110011" => manhi <= conv_std_logic_vector(5749053,24); manlo <= conv_std_logic_vector(76824142,28); exponent <= conv_std_logic_vector(672,11); WHEN "0011110100" => manhi <= conv_std_logic_vector(16370589,24); manlo <= conv_std_logic_vector(114548734,28); exponent <= conv_std_logic_vector(670,11); WHEN "0011110101" => manhi <= conv_std_logic_vector(7611576,24); manlo <= conv_std_logic_vector(73252889,28); exponent <= conv_std_logic_vector(669,11); WHEN "0011110110" => manhi <= conv_std_logic_vector(1167054,24); manlo <= conv_std_logic_vector(146134399,28); exponent <= conv_std_logic_vector(668,11); WHEN "0011110111" => manhi <= conv_std_logic_vector(9628096,24); manlo <= conv_std_logic_vector(236331104,28); exponent <= conv_std_logic_vector(666,11); WHEN "0011111000" => manhi <= conv_std_logic_vector(2650727,24); manlo <= conv_std_logic_vector(132284651,28); exponent <= conv_std_logic_vector(665,11); WHEN "0011111001" => manhi <= conv_std_logic_vector(11811347,24); manlo <= conv_std_logic_vector(263325685,28); exponent <= conv_std_logic_vector(663,11); WHEN "0011111010" => manhi <= conv_std_logic_vector(4257073,24); manlo <= conv_std_logic_vector(236873507,28); exponent <= conv_std_logic_vector(662,11); WHEN "0011111011" => manhi <= conv_std_logic_vector(14175115,24); manlo <= conv_std_logic_vector(61615323,28); exponent <= conv_std_logic_vector(660,11); WHEN "0011111100" => manhi <= conv_std_logic_vector(5996236,24); manlo <= conv_std_logic_vector(169476567,28); exponent <= conv_std_logic_vector(659,11); WHEN "0011111101" => manhi <= conv_std_logic_vector(16734324,24); manlo <= conv_std_logic_vector(29597837,28); exponent <= conv_std_logic_vector(657,11); WHEN "0011111110" => manhi <= conv_std_logic_vector(7879197,24); manlo <= conv_std_logic_vector(79755942,28); exponent <= conv_std_logic_vector(656,11); WHEN "0011111111" => manhi <= conv_std_logic_vector(1363959,24); manlo <= conv_std_logic_vector(24177677,28); exponent <= conv_std_logic_vector(655,11); WHEN "0100000000" => manhi <= conv_std_logic_vector(9917845,24); manlo <= conv_std_logic_vector(112021148,28); exponent <= conv_std_logic_vector(653,11); WHEN "0100000001" => manhi <= conv_std_logic_vector(2863912,24); manlo <= conv_std_logic_vector(148304045,28); exponent <= conv_std_logic_vector(652,11); WHEN "0100000010" => manhi <= conv_std_logic_vector(12125053,24); manlo <= conv_std_logic_vector(156617262,28); exponent <= conv_std_logic_vector(650,11); WHEN "0100000011" => manhi <= conv_std_logic_vector(4487885,24); manlo <= conv_std_logic_vector(151904422,28); exponent <= conv_std_logic_vector(649,11); WHEN "0100000100" => manhi <= conv_std_logic_vector(14514758,24); manlo <= conv_std_logic_vector(193824214,28); exponent <= conv_std_logic_vector(647,11); WHEN "0100000101" => manhi <= conv_std_logic_vector(6246132,24); manlo <= conv_std_logic_vector(93361418,28); exponent <= conv_std_logic_vector(646,11); WHEN "0100000110" => manhi <= conv_std_logic_vector(162417,24); manlo <= conv_std_logic_vector(12929741,28); exponent <= conv_std_logic_vector(645,11); WHEN "0100000111" => manhi <= conv_std_logic_vector(8149754,24); manlo <= conv_std_logic_vector(257063442,28); exponent <= conv_std_logic_vector(643,11); WHEN "0100001000" => manhi <= conv_std_logic_vector(1563024,24); manlo <= conv_std_logic_vector(78378796,28); exponent <= conv_std_logic_vector(642,11); WHEN "0100001001" => manhi <= conv_std_logic_vector(10210773,24); manlo <= conv_std_logic_vector(106907060,28); exponent <= conv_std_logic_vector(640,11); WHEN "0100001010" => manhi <= conv_std_logic_vector(3079436,24); manlo <= conv_std_logic_vector(245979562,28); exponent <= conv_std_logic_vector(639,11); WHEN "0100001011" => manhi <= conv_std_logic_vector(12442201,24); manlo <= conv_std_logic_vector(137868870,28); exponent <= conv_std_logic_vector(637,11); WHEN "0100001100" => manhi <= conv_std_logic_vector(4721229,24); manlo <= conv_std_logic_vector(261058204,28); exponent <= conv_std_logic_vector(636,11); WHEN "0100001101" => manhi <= conv_std_logic_vector(14858129,24); manlo <= conv_std_logic_vector(43405174,28); exponent <= conv_std_logic_vector(634,11); WHEN "0100001110" => manhi <= conv_std_logic_vector(6498770,24); manlo <= conv_std_logic_vector(53338521,28); exponent <= conv_std_logic_vector(633,11); WHEN "0100001111" => manhi <= conv_std_logic_vector(348297,24); manlo <= conv_std_logic_vector(158641329,28); exponent <= conv_std_logic_vector(632,11); WHEN "0100010000" => manhi <= conv_std_logic_vector(8423281,24); manlo <= conv_std_logic_vector(128446906,28); exponent <= conv_std_logic_vector(630,11); WHEN "0100010001" => manhi <= conv_std_logic_vector(1764273,24); manlo <= conv_std_logic_vector(230657816,28); exponent <= conv_std_logic_vector(629,11); WHEN "0100010010" => manhi <= conv_std_logic_vector(10506915,24); manlo <= conv_std_logic_vector(191032874,28); exponent <= conv_std_logic_vector(627,11); WHEN "0100010011" => manhi <= conv_std_logic_vector(3297326,24); manlo <= conv_std_logic_vector(68145509,28); exponent <= conv_std_logic_vector(626,11); WHEN "0100010100" => manhi <= conv_std_logic_vector(12762829,24); manlo <= conv_std_logic_vector(146161159,28); exponent <= conv_std_logic_vector(624,11); WHEN "0100010101" => manhi <= conv_std_logic_vector(4957134,24); manlo <= conv_std_logic_vector(240027976,28); exponent <= conv_std_logic_vector(623,11); WHEN "0100010110" => manhi <= conv_std_logic_vector(15205267,24); manlo <= conv_std_logic_vector(119370809,28); exponent <= conv_std_logic_vector(621,11); WHEN "0100010111" => manhi <= conv_std_logic_vector(6754180,24); manlo <= conv_std_logic_vector(73501816,28); exponent <= conv_std_logic_vector(620,11); WHEN "0100011000" => manhi <= conv_std_logic_vector(536217,24); manlo <= conv_std_logic_vector(220758658,28); exponent <= conv_std_logic_vector(619,11); WHEN "0100011001" => manhi <= conv_std_logic_vector(8699809,24); manlo <= conv_std_logic_vector(117402516,28); exponent <= conv_std_logic_vector(617,11); WHEN "0100011010" => manhi <= conv_std_logic_vector(1967731,24); manlo <= conv_std_logic_vector(204336317,28); exponent <= conv_std_logic_vector(616,11); WHEN "0100011011" => manhi <= conv_std_logic_vector(10806307,24); manlo <= conv_std_logic_vector(168773516,28); exponent <= conv_std_logic_vector(614,11); WHEN "0100011100" => manhi <= conv_std_logic_vector(3517606,24); manlo <= conv_std_logic_vector(138553816,28); exponent <= conv_std_logic_vector(613,11); WHEN "0100011101" => manhi <= conv_std_logic_vector(13086975,24); manlo <= conv_std_logic_vector(231838082,28); exponent <= conv_std_logic_vector(611,11); WHEN "0100011110" => manhi <= conv_std_logic_vector(5195628,24); manlo <= conv_std_logic_vector(114805284,28); exponent <= conv_std_logic_vector(610,11); WHEN "0100011111" => manhi <= conv_std_logic_vector(15556214,24); manlo <= conv_std_logic_vector(245890169,28); exponent <= conv_std_logic_vector(608,11); WHEN "0100100000" => manhi <= conv_std_logic_vector(7012392,24); manlo <= conv_std_logic_vector(266576824,28); exponent <= conv_std_logic_vector(607,11); WHEN "0100100001" => manhi <= conv_std_logic_vector(726200,24); manlo <= conv_std_logic_vector(33318175,28); exponent <= conv_std_logic_vector(606,11); WHEN "0100100010" => manhi <= conv_std_logic_vector(8979371,24); manlo <= conv_std_logic_vector(206515377,28); exponent <= conv_std_logic_vector(604,11); WHEN "0100100011" => manhi <= conv_std_logic_vector(2173422,24); manlo <= conv_std_logic_vector(61774637,28); exponent <= conv_std_logic_vector(603,11); WHEN "0100100100" => manhi <= conv_std_logic_vector(11108984,24); manlo <= conv_std_logic_vector(216833386,28); exponent <= conv_std_logic_vector(601,11); WHEN "0100100101" => manhi <= conv_std_logic_vector(3740303,24); manlo <= conv_std_logic_vector(252090990,28); exponent <= conv_std_logic_vector(600,11); WHEN "0100100110" => manhi <= conv_std_logic_vector(13414679,24); manlo <= conv_std_logic_vector(20856890,28); exponent <= conv_std_logic_vector(598,11); WHEN "0100100111" => manhi <= conv_std_logic_vector(5436738,24); manlo <= conv_std_logic_vector(262578382,28); exponent <= conv_std_logic_vector(597,11); WHEN "0100101000" => manhi <= conv_std_logic_vector(15911013,24); manlo <= conv_std_logic_vector(100481506,28); exponent <= conv_std_logic_vector(595,11); WHEN "0100101001" => manhi <= conv_std_logic_vector(7273439,24); manlo <= conv_std_logic_vector(29586843,28); exponent <= conv_std_logic_vector(594,11); WHEN "0100101010" => manhi <= conv_std_logic_vector(918267,24); manlo <= conv_std_logic_vector(33154287,28); exponent <= conv_std_logic_vector(593,11); WHEN "0100101011" => manhi <= conv_std_logic_vector(9262001,24); manlo <= conv_std_logic_vector(206947959,28); exponent <= conv_std_logic_vector(591,11); WHEN "0100101100" => manhi <= conv_std_logic_vector(2381369,24); manlo <= conv_std_logic_vector(205146615,28); exponent <= conv_std_logic_vector(590,11); WHEN "0100101101" => manhi <= conv_std_logic_vector(11414983,24); manlo <= conv_std_logic_vector(80080029,28); exponent <= conv_std_logic_vector(588,11); WHEN "0100101110" => manhi <= conv_std_logic_vector(3965445,24); manlo <= conv_std_logic_vector(12487826,28); exponent <= conv_std_logic_vector(587,11); WHEN "0100101111" => manhi <= conv_std_logic_vector(13745978,24); manlo <= conv_std_logic_vector(58199715,28); exponent <= conv_std_logic_vector(585,11); WHEN "0100110000" => manhi <= conv_std_logic_vector(5680495,24); manlo <= conv_std_logic_vector(70463110,28); exponent <= conv_std_logic_vector(584,11); WHEN "0100110001" => manhi <= conv_std_logic_vector(16269705,24); manlo <= conv_std_logic_vector(20654997,28); exponent <= conv_std_logic_vector(582,11); WHEN "0100110010" => manhi <= conv_std_logic_vector(7537349,24); manlo <= conv_std_logic_vector(192319832,28); exponent <= conv_std_logic_vector(581,11); WHEN "0100110011" => manhi <= conv_std_logic_vector(1112441,24); manlo <= conv_std_logic_vector(186880957,28); exponent <= conv_std_logic_vector(580,11); WHEN "0100110100" => manhi <= conv_std_logic_vector(9547733,24); manlo <= conv_std_logic_vector(27940083,28); exponent <= conv_std_logic_vector(578,11); WHEN "0100110101" => manhi <= conv_std_logic_vector(2591599,24); manlo <= conv_std_logic_vector(35045549,28); exponent <= conv_std_logic_vector(577,11); WHEN "0100110110" => manhi <= conv_std_logic_vector(11724339,24); manlo <= conv_std_logic_vector(146438512,28); exponent <= conv_std_logic_vector(575,11); WHEN "0100110111" => manhi <= conv_std_logic_vector(4193056,24); manlo <= conv_std_logic_vector(175344679,28); exponent <= conv_std_logic_vector(574,11); WHEN "0100111000" => manhi <= conv_std_logic_vector(14080912,24); manlo <= conv_std_logic_vector(198508677,28); exponent <= conv_std_logic_vector(572,11); WHEN "0100111001" => manhi <= conv_std_logic_vector(5926926,24); manlo <= conv_std_logic_vector(83904648,28); exponent <= conv_std_logic_vector(571,11); WHEN "0100111010" => manhi <= conv_std_logic_vector(16632332,24); manlo <= conv_std_logic_vector(199957404,28); exponent <= conv_std_logic_vector(569,11); WHEN "0100111011" => manhi <= conv_std_logic_vector(7804156,24); manlo <= conv_std_logic_vector(65532420,28); exponent <= conv_std_logic_vector(568,11); WHEN "0100111100" => manhi <= conv_std_logic_vector(1308746,24); manlo <= conv_std_logic_vector(260058525,28); exponent <= conv_std_logic_vector(567,11); WHEN "0100111101" => manhi <= conv_std_logic_vector(9836599,24); manlo <= conv_std_logic_vector(214756046,28); exponent <= conv_std_logic_vector(565,11); WHEN "0100111110" => manhi <= conv_std_logic_vector(2804135,24); manlo <= conv_std_logic_vector(98759674,28); exponent <= conv_std_logic_vector(564,11); WHEN "0100111111" => manhi <= conv_std_logic_vector(12037090,24); manlo <= conv_std_logic_vector(105879341,28); exponent <= conv_std_logic_vector(562,11); WHEN "0101000000" => manhi <= conv_std_logic_vector(4423165,24); manlo <= conv_std_logic_vector(233069674,28); exponent <= conv_std_logic_vector(561,11); WHEN "0101000001" => manhi <= conv_std_logic_vector(14419522,24); manlo <= conv_std_logic_vector(144218340,28); exponent <= conv_std_logic_vector(559,11); WHEN "0101000010" => manhi <= conv_std_logic_vector(6176061,24); manlo <= conv_std_logic_vector(128557517,28); exponent <= conv_std_logic_vector(558,11); WHEN "0101000011" => manhi <= conv_std_logic_vector(110861,24); manlo <= conv_std_logic_vector(210451229,28); exponent <= conv_std_logic_vector(557,11); WHEN "0101000100" => manhi <= conv_std_logic_vector(8073890,24); manlo <= conv_std_logic_vector(126309403,28); exponent <= conv_std_logic_vector(555,11); WHEN "0101000101" => manhi <= conv_std_logic_vector(1507206,24); manlo <= conv_std_logic_vector(86368556,28); exponent <= conv_std_logic_vector(554,11); WHEN "0101000110" => manhi <= conv_std_logic_vector(10128636,24); manlo <= conv_std_logic_vector(70724454,28); exponent <= conv_std_logic_vector(552,11); WHEN "0101000111" => manhi <= conv_std_logic_vector(3019003,24); manlo <= conv_std_logic_vector(212024500,28); exponent <= conv_std_logic_vector(551,11); WHEN "0101001000" => manhi <= conv_std_logic_vector(12353273,24); manlo <= conv_std_logic_vector(25338267,28); exponent <= conv_std_logic_vector(549,11); WHEN "0101001001" => manhi <= conv_std_logic_vector(4655800,24); manlo <= conv_std_logic_vector(26358145,28); exponent <= conv_std_logic_vector(548,11); WHEN "0101001010" => manhi <= conv_std_logic_vector(14761847,24); manlo <= conv_std_logic_vector(252137457,28); exponent <= conv_std_logic_vector(546,11); WHEN "0101001011" => manhi <= conv_std_logic_vector(6427930,24); manlo <= conv_std_logic_vector(116530320,28); exponent <= conv_std_logic_vector(545,11); WHEN "0101001100" => manhi <= conv_std_logic_vector(296176,24); manlo <= conv_std_logic_vector(162393576,28); exponent <= conv_std_logic_vector(544,11); WHEN "0101001101" => manhi <= conv_std_logic_vector(8346584,24); manlo <= conv_std_logic_vector(140031506,28); exponent <= conv_std_logic_vector(542,11); WHEN "0101001110" => manhi <= conv_std_logic_vector(1707843,24); manlo <= conv_std_logic_vector(105232250,28); exponent <= conv_std_logic_vector(541,11); WHEN "0101001111" => manhi <= conv_std_logic_vector(10423877,24); manlo <= conv_std_logic_vector(74257288,28); exponent <= conv_std_logic_vector(539,11); WHEN "0101010000" => manhi <= conv_std_logic_vector(3236229,24); manlo <= conv_std_logic_vector(265138481,28); exponent <= conv_std_logic_vector(538,11); WHEN "0101010001" => manhi <= conv_std_logic_vector(12672925,24); manlo <= conv_std_logic_vector(81471742,28); exponent <= conv_std_logic_vector(536,11); WHEN "0101010010" => manhi <= conv_std_logic_vector(4890987,24); manlo <= conv_std_logic_vector(13504322,28); exponent <= conv_std_logic_vector(535,11); WHEN "0101010011" => manhi <= conv_std_logic_vector(15107929,24); manlo <= conv_std_logic_vector(192561070,28); exponent <= conv_std_logic_vector(533,11); WHEN "0101010100" => manhi <= conv_std_logic_vector(6682563,24); manlo <= conv_std_logic_vector(47334412,28); exponent <= conv_std_logic_vector(532,11); WHEN "0101010101" => manhi <= conv_std_logic_vector(483524,24); manlo <= conv_std_logic_vector(243414774,28); exponent <= conv_std_logic_vector(531,11); WHEN "0101010110" => manhi <= conv_std_logic_vector(8622270,24); manlo <= conv_std_logic_vector(235144322,28); exponent <= conv_std_logic_vector(529,11); WHEN "0101010111" => manhi <= conv_std_logic_vector(1910682,24); manlo <= conv_std_logic_vector(20388866,28); exponent <= conv_std_logic_vector(528,11); WHEN "0101011000" => manhi <= conv_std_logic_vector(10722358,24); manlo <= conv_std_logic_vector(913747,28); exponent <= conv_std_logic_vector(526,11); WHEN "0101011001" => manhi <= conv_std_logic_vector(3455839,24); manlo <= conv_std_logic_vector(223781205,28); exponent <= conv_std_logic_vector(525,11); WHEN "0101011010" => manhi <= conv_std_logic_vector(12996085,24); manlo <= conv_std_logic_vector(24989984,28); exponent <= conv_std_logic_vector(523,11); WHEN "0101011011" => manhi <= conv_std_logic_vector(5128754,24); manlo <= conv_std_logic_vector(197545335,28); exponent <= conv_std_logic_vector(522,11); WHEN "0101011100" => manhi <= conv_std_logic_vector(15457809,24); manlo <= conv_std_logic_vector(24315860,28); exponent <= conv_std_logic_vector(520,11); WHEN "0101011101" => manhi <= conv_std_logic_vector(6939990,24); manlo <= conv_std_logic_vector(8842978,28); exponent <= conv_std_logic_vector(519,11); WHEN "0101011110" => manhi <= conv_std_logic_vector(672929,24); manlo <= conv_std_logic_vector(830489,28); exponent <= conv_std_logic_vector(518,11); WHEN "0101011111" => manhi <= conv_std_logic_vector(8900982,24); manlo <= conv_std_logic_vector(98890321,28); exponent <= conv_std_logic_vector(516,11); WHEN "0101100000" => manhi <= conv_std_logic_vector(2115746,24); manlo <= conv_std_logic_vector(142837003,28); exponent <= conv_std_logic_vector(515,11); WHEN "0101100001" => manhi <= conv_std_logic_vector(11024113,24); manlo <= conv_std_logic_vector(266701758,28); exponent <= conv_std_logic_vector(513,11); WHEN "0101100010" => manhi <= conv_std_logic_vector(3677859,24); manlo <= conv_std_logic_vector(129840563,28); exponent <= conv_std_logic_vector(512,11); WHEN "0101100011" => manhi <= conv_std_logic_vector(13322790,24); manlo <= conv_std_logic_vector(255615990,28); exponent <= conv_std_logic_vector(510,11); WHEN "0101100100" => manhi <= conv_std_logic_vector(5369131,24); manlo <= conv_std_logic_vector(127156783,28); exponent <= conv_std_logic_vector(509,11); WHEN "0101100101" => manhi <= conv_std_logic_vector(15811527,24); manlo <= conv_std_logic_vector(196077973,28); exponent <= conv_std_logic_vector(507,11); WHEN "0101100110" => manhi <= conv_std_logic_vector(7200241,24); manlo <= conv_std_logic_vector(178260644,28); exponent <= conv_std_logic_vector(506,11); WHEN "0101100111" => manhi <= conv_std_logic_vector(864411,24); manlo <= conv_std_logic_vector(121424610,28); exponent <= conv_std_logic_vector(505,11); WHEN "0101101000" => manhi <= conv_std_logic_vector(9182752,24); manlo <= conv_std_logic_vector(52100447,28); exponent <= conv_std_logic_vector(503,11); WHEN "0101101001" => manhi <= conv_std_logic_vector(2323061,24); manlo <= conv_std_logic_vector(49429697,28); exponent <= conv_std_logic_vector(502,11); WHEN "0101101010" => manhi <= conv_std_logic_vector(11329181,24); manlo <= conv_std_logic_vector(50166358,28); exponent <= conv_std_logic_vector(500,11); WHEN "0101101011" => manhi <= conv_std_logic_vector(3902315,24); manlo <= conv_std_logic_vector(102248985,28); exponent <= conv_std_logic_vector(499,11); WHEN "0101101100" => manhi <= conv_std_logic_vector(13653081,24); manlo <= conv_std_logic_vector(212703346,28); exponent <= conv_std_logic_vector(497,11); WHEN "0101101101" => manhi <= conv_std_logic_vector(5612145,24); manlo <= conv_std_logic_vector(239735388,28); exponent <= conv_std_logic_vector(496,11); WHEN "0101101110" => manhi <= conv_std_logic_vector(16169127,24); manlo <= conv_std_logic_vector(205528034,28); exponent <= conv_std_logic_vector(494,11); WHEN "0101101111" => manhi <= conv_std_logic_vector(7463349,24); manlo <= conv_std_logic_vector(17797346,28); exponent <= conv_std_logic_vector(493,11); WHEN "0101110000" => manhi <= conv_std_logic_vector(1057995,24); manlo <= conv_std_logic_vector(16251369,28); exponent <= conv_std_logic_vector(492,11); WHEN "0101110001" => manhi <= conv_std_logic_vector(9467613,24); manlo <= conv_std_logic_vector(244949044,28); exponent <= conv_std_logic_vector(490,11); WHEN "0101110010" => manhi <= conv_std_logic_vector(2532650,24); manlo <= conv_std_logic_vector(194268012,28); exponent <= conv_std_logic_vector(489,11); WHEN "0101110011" => manhi <= conv_std_logic_vector(11637595,24); manlo <= conv_std_logic_vector(246328755,28); exponent <= conv_std_logic_vector(487,11); WHEN "0101110100" => manhi <= conv_std_logic_vector(4129234,24); manlo <= conv_std_logic_vector(69393408,28); exponent <= conv_std_logic_vector(486,11); WHEN "0101110101" => manhi <= conv_std_logic_vector(13986996,24); manlo <= conv_std_logic_vector(255528468,28); exponent <= conv_std_logic_vector(484,11); WHEN "0101110110" => manhi <= conv_std_logic_vector(5857826,24); manlo <= conv_std_logic_vector(251701587,28); exponent <= conv_std_logic_vector(483,11); WHEN "0101110111" => manhi <= conv_std_logic_vector(16530651,24); manlo <= conv_std_logic_vector(211310789,28); exponent <= conv_std_logic_vector(481,11); WHEN "0101111000" => manhi <= conv_std_logic_vector(7729343,24); manlo <= conv_std_logic_vector(154707528,28); exponent <= conv_std_logic_vector(480,11); WHEN "0101111001" => manhi <= conv_std_logic_vector(1253702,24); manlo <= conv_std_logic_vector(237283577,28); exponent <= conv_std_logic_vector(479,11); WHEN "0101111010" => manhi <= conv_std_logic_vector(9755601,24); manlo <= conv_std_logic_vector(121155884,28); exponent <= conv_std_logic_vector(477,11); WHEN "0101111011" => manhi <= conv_std_logic_vector(2744540,24); manlo <= conv_std_logic_vector(30442277,28); exponent <= conv_std_logic_vector(476,11); WHEN "0101111100" => manhi <= conv_std_logic_vector(11949394,24); manlo <= conv_std_logic_vector(246622503,28); exponent <= conv_std_logic_vector(474,11); WHEN "0101111101" => manhi <= conv_std_logic_vector(4358643,24); manlo <= conv_std_logic_vector(38405425,28); exponent <= conv_std_logic_vector(473,11); WHEN "0101111110" => manhi <= conv_std_logic_vector(14324576,24); manlo <= conv_std_logic_vector(53935566,28); exponent <= conv_std_logic_vector(471,11); WHEN "0101111111" => manhi <= conv_std_logic_vector(6106203,24); manlo <= conv_std_logic_vector(233166714,28); exponent <= conv_std_logic_vector(470,11); WHEN "0110000000" => manhi <= conv_std_logic_vector(59463,24); manlo <= conv_std_logic_vector(114545214,28); exponent <= conv_std_logic_vector(469,11); WHEN "0110000001" => manhi <= conv_std_logic_vector(7998256,24); manlo <= conv_std_logic_vector(234808364,28); exponent <= conv_std_logic_vector(467,11); WHEN "0110000010" => manhi <= conv_std_logic_vector(1451558,24); manlo <= conv_std_logic_vector(62230667,28); exponent <= conv_std_logic_vector(466,11); WHEN "0110000011" => manhi <= conv_std_logic_vector(10046749,24); manlo <= conv_std_logic_vector(29683609,28); exponent <= conv_std_logic_vector(464,11); WHEN "0110000100" => manhi <= conv_std_logic_vector(2958754,24); manlo <= conv_std_logic_vector(158313814,28); exponent <= conv_std_logic_vector(463,11); WHEN "0110000101" => manhi <= conv_std_logic_vector(12264615,24); manlo <= conv_std_logic_vector(87551554,28); exponent <= conv_std_logic_vector(461,11); WHEN "0110000110" => manhi <= conv_std_logic_vector(4590569,24); manlo <= conv_std_logic_vector(96025360,28); exponent <= conv_std_logic_vector(460,11); WHEN "0110000111" => manhi <= conv_std_logic_vector(14665859,24); manlo <= conv_std_logic_vector(200220878,28); exponent <= conv_std_logic_vector(458,11); WHEN "0110001000" => manhi <= conv_std_logic_vector(6357306,24); manlo <= conv_std_logic_vector(71997608,28); exponent <= conv_std_logic_vector(457,11); WHEN "0110001001" => manhi <= conv_std_logic_vector(244214,24); manlo <= conv_std_logic_vector(66463607,28); exponent <= conv_std_logic_vector(456,11); WHEN "0110001010" => manhi <= conv_std_logic_vector(8270120,24); manlo <= conv_std_logic_vector(265669912,28); exponent <= conv_std_logic_vector(454,11); WHEN "0110001011" => manhi <= conv_std_logic_vector(1651584,24); manlo <= conv_std_logic_vector(179638473,28); exponent <= conv_std_logic_vector(453,11); WHEN "0110001100" => manhi <= conv_std_logic_vector(10341091,24); manlo <= conv_std_logic_vector(152092530,28); exponent <= conv_std_logic_vector(451,11); WHEN "0110001101" => manhi <= conv_std_logic_vector(3175319,24); manlo <= conv_std_logic_vector(178838140,28); exponent <= conv_std_logic_vector(450,11); WHEN "0110001110" => manhi <= conv_std_logic_vector(12583294,24); manlo <= conv_std_logic_vector(183442082,28); exponent <= conv_std_logic_vector(448,11); WHEN "0110001111" => manhi <= conv_std_logic_vector(4825040,24); manlo <= conv_std_logic_vector(141040370,28); exponent <= conv_std_logic_vector(447,11); WHEN "0110010000" => manhi <= conv_std_logic_vector(15010888,24); manlo <= conv_std_logic_vector(62934477,28); exponent <= conv_std_logic_vector(445,11); WHEN "0110010001" => manhi <= conv_std_logic_vector(6611164,24); manlo <= conv_std_logic_vector(11633311,28); exponent <= conv_std_logic_vector(444,11); WHEN "0110010010" => manhi <= conv_std_logic_vector(430992,24); manlo <= conv_std_logic_vector(96770068,28); exponent <= conv_std_logic_vector(443,11); WHEN "0110010011" => manhi <= conv_std_logic_vector(8544968,24); manlo <= conv_std_logic_vector(80768180,28); exponent <= conv_std_logic_vector(441,11); WHEN "0110010100" => manhi <= conv_std_logic_vector(1853806,24); manlo <= conv_std_logic_vector(5288079,28); exponent <= conv_std_logic_vector(440,11); WHEN "0110010101" => manhi <= conv_std_logic_vector(10638663,24); manlo <= conv_std_logic_vector(235213815,28); exponent <= conv_std_logic_vector(438,11); WHEN "0110010110" => manhi <= conv_std_logic_vector(3394261,24); manlo <= conv_std_logic_vector(36557939,28); exponent <= conv_std_logic_vector(437,11); WHEN "0110010111" => manhi <= conv_std_logic_vector(12905470,24); manlo <= conv_std_logic_vector(253900977,28); exponent <= conv_std_logic_vector(435,11); WHEN "0110011000" => manhi <= conv_std_logic_vector(5062084,24); manlo <= conv_std_logic_vector(153603034,28); exponent <= conv_std_logic_vector(434,11); WHEN "0110011001" => manhi <= conv_std_logic_vector(15359702,24); manlo <= conv_std_logic_vector(204098933,28); exponent <= conv_std_logic_vector(432,11); WHEN "0110011010" => manhi <= conv_std_logic_vector(6867807,24); manlo <= conv_std_logic_vector(115170312,28); exponent <= conv_std_logic_vector(431,11); WHEN "0110011011" => manhi <= conv_std_logic_vector(619820,24); manlo <= conv_std_logic_vector(2986045,28); exponent <= conv_std_logic_vector(430,11); WHEN "0110011100" => manhi <= conv_std_logic_vector(8822831,24); manlo <= conv_std_logic_vector(145826716,28); exponent <= conv_std_logic_vector(428,11); WHEN "0110011101" => manhi <= conv_std_logic_vector(2058246,24); manlo <= conv_std_logic_vector(98876593,28); exponent <= conv_std_logic_vector(427,11); WHEN "0110011110" => manhi <= conv_std_logic_vector(10939501,24); manlo <= conv_std_logic_vector(129141213,28); exponent <= conv_std_logic_vector(425,11); WHEN "0110011111" => manhi <= conv_std_logic_vector(3615605,24); manlo <= conv_std_logic_vector(20427716,28); exponent <= conv_std_logic_vector(424,11); WHEN "0110100000" => manhi <= conv_std_logic_vector(13231182,24); manlo <= conv_std_logic_vector(130335695,28); exponent <= conv_std_logic_vector(422,11); WHEN "0110100001" => manhi <= conv_std_logic_vector(5301729,24); manlo <= conv_std_logic_vector(196124198,28); exponent <= conv_std_logic_vector(421,11); WHEN "0110100010" => manhi <= conv_std_logic_vector(15712344,24); manlo <= conv_std_logic_vector(233039482,28); exponent <= conv_std_logic_vector(419,11); WHEN "0110100011" => manhi <= conv_std_logic_vector(7127266,24); manlo <= conv_std_logic_vector(266329205,28); exponent <= conv_std_logic_vector(418,11); WHEN "0110100100" => manhi <= conv_std_logic_vector(810719,24); manlo <= conv_std_logic_vector(185030259,28); exponent <= conv_std_logic_vector(417,11); WHEN "0110100101" => manhi <= conv_std_logic_vector(9103743,24); manlo <= conv_std_logic_vector(217685905,28); exponent <= conv_std_logic_vector(415,11); WHEN "0110100110" => manhi <= conv_std_logic_vector(2264930,24); manlo <= conv_std_logic_vector(17303531,28); exponent <= conv_std_logic_vector(414,11); WHEN "0110100111" => manhi <= conv_std_logic_vector(11243640,24); manlo <= conv_std_logic_vector(56799625,28); exponent <= conv_std_logic_vector(412,11); WHEN "0110101000" => manhi <= conv_std_logic_vector(3839377,24); manlo <= conv_std_logic_vector(227776580,28); exponent <= conv_std_logic_vector(411,11); WHEN "0110101001" => manhi <= conv_std_logic_vector(13560468,24); manlo <= conv_std_logic_vector(25616516,28); exponent <= conv_std_logic_vector(409,11); WHEN "0110101010" => manhi <= conv_std_logic_vector(5544004,24); manlo <= conv_std_logic_vector(145740137,28); exponent <= conv_std_logic_vector(408,11); WHEN "0110101011" => manhi <= conv_std_logic_vector(16068856,24); manlo <= conv_std_logic_vector(149889545,28); exponent <= conv_std_logic_vector(406,11); WHEN "0110101100" => manhi <= conv_std_logic_vector(7389573,24); manlo <= conv_std_logic_vector(170431948,28); exponent <= conv_std_logic_vector(405,11); WHEN "0110101101" => manhi <= conv_std_logic_vector(1003714,24); manlo <= conv_std_logic_vector(35324999,28); exponent <= conv_std_logic_vector(404,11); WHEN "0110101110" => manhi <= conv_std_logic_vector(9387738,24); manlo <= conv_std_logic_vector(150667400,28); exponent <= conv_std_logic_vector(402,11); WHEN "0110101111" => manhi <= conv_std_logic_vector(2473881,24); manlo <= conv_std_logic_vector(194497484,28); exponent <= conv_std_logic_vector(401,11); WHEN "0110110000" => manhi <= conv_std_logic_vector(11551116,24); manlo <= conv_std_logic_vector(78219737,28); exponent <= conv_std_logic_vector(399,11); WHEN "0110110001" => manhi <= conv_std_logic_vector(4065606,24); manlo <= conv_std_logic_vector(28280174,28); exponent <= conv_std_logic_vector(398,11); WHEN "0110110010" => manhi <= conv_std_logic_vector(13893366,24); manlo <= conv_std_logic_vector(266881350,28); exponent <= conv_std_logic_vector(396,11); WHEN "0110110011" => manhi <= conv_std_logic_vector(5788937,24); manlo <= conv_std_logic_vector(232096008,28); exponent <= conv_std_logic_vector(395,11); WHEN "0110110100" => manhi <= conv_std_logic_vector(16429280,24); manlo <= conv_std_logic_vector(78498076,28); exponent <= conv_std_logic_vector(393,11); WHEN "0110110101" => manhi <= conv_std_logic_vector(7654758,24); manlo <= conv_std_logic_vector(160696217,28); exponent <= conv_std_logic_vector(392,11); WHEN "0110110110" => manhi <= conv_std_logic_vector(1198826,24); manlo <= conv_std_logic_vector(87006684,28); exponent <= conv_std_logic_vector(391,11); WHEN "0110110111" => manhi <= conv_std_logic_vector(9674849,24); manlo <= conv_std_logic_vector(166079254,28); exponent <= conv_std_logic_vector(389,11); WHEN "0110111000" => manhi <= conv_std_logic_vector(2685126,24); manlo <= conv_std_logic_vector(63154951,28); exponent <= conv_std_logic_vector(388,11); WHEN "0110111001" => manhi <= conv_std_logic_vector(11861966,24); manlo <= conv_std_logic_vector(91696135,28); exponent <= conv_std_logic_vector(386,11); WHEN "0110111010" => manhi <= conv_std_logic_vector(4294316,24); manlo <= conv_std_logic_vector(212296424,28); exponent <= conv_std_logic_vector(385,11); WHEN "0110111011" => manhi <= conv_std_logic_vector(14229918,24); manlo <= conv_std_logic_vector(223047784,28); exponent <= conv_std_logic_vector(383,11); WHEN "0110111100" => manhi <= conv_std_logic_vector(6036558,24); manlo <= conv_std_logic_vector(232962025,28); exponent <= conv_std_logic_vector(382,11); WHEN "0110111101" => manhi <= conv_std_logic_vector(8221,24); manlo <= conv_std_logic_vector(133893557,28); exponent <= conv_std_logic_vector(381,11); WHEN "0110111110" => manhi <= conv_std_logic_vector(7922853,24); manlo <= conv_std_logic_vector(125492404,28); exponent <= conv_std_logic_vector(379,11); WHEN "0110111111" => manhi <= conv_std_logic_vector(1396079,24); manlo <= conv_std_logic_vector(135612572,28); exponent <= conv_std_logic_vector(378,11); WHEN "0111000000" => manhi <= conv_std_logic_vector(9965111,24); manlo <= conv_std_logic_vector(47990958,28); exponent <= conv_std_logic_vector(376,11); WHEN "0111000001" => manhi <= conv_std_logic_vector(2898688,24); manlo <= conv_std_logic_vector(203019642,28); exponent <= conv_std_logic_vector(375,11); WHEN "0111000010" => manhi <= conv_std_logic_vector(12176227,24); manlo <= conv_std_logic_vector(103393586,28); exponent <= conv_std_logic_vector(373,11); WHEN "0111000011" => manhi <= conv_std_logic_vector(4525537,24); manlo <= conv_std_logic_vector(38936964,28); exponent <= conv_std_logic_vector(372,11); WHEN "0111000100" => manhi <= conv_std_logic_vector(14570163,24); manlo <= conv_std_logic_vector(185128905,28); exponent <= conv_std_logic_vector(370,11); WHEN "0111000101" => manhi <= conv_std_logic_vector(6286897,24); manlo <= conv_std_logic_vector(12037044,28); exponent <= conv_std_logic_vector(369,11); WHEN "0111000110" => manhi <= conv_std_logic_vector(192410,24); manlo <= conv_std_logic_vector(9691196,28); exponent <= conv_std_logic_vector(368,11); WHEN "0111000111" => manhi <= conv_std_logic_vector(8193890,24); manlo <= conv_std_logic_vector(46224319,28); exponent <= conv_std_logic_vector(366,11); WHEN "0111001000" => manhi <= conv_std_logic_vector(1595497,24); manlo <= conv_std_logic_vector(45130080,28); exponent <= conv_std_logic_vector(365,11); WHEN "0111001001" => manhi <= conv_std_logic_vector(10258557,24); manlo <= conv_std_logic_vector(218068546,28); exponent <= conv_std_logic_vector(363,11); WHEN "0111001010" => manhi <= conv_std_logic_vector(3114594,24); manlo <= conv_std_logic_vector(194203222,28); exponent <= conv_std_logic_vector(362,11); WHEN "0111001011" => manhi <= conv_std_logic_vector(12493936,24); manlo <= conv_std_logic_vector(228530713,28); exponent <= conv_std_logic_vector(360,11); WHEN "0111001100" => manhi <= conv_std_logic_vector(4759294,24); manlo <= conv_std_logic_vector(189728046,28); exponent <= conv_std_logic_vector(359,11); WHEN "0111001101" => manhi <= conv_std_logic_vector(14914142,24); manlo <= conv_std_logic_vector(25337562,28); exponent <= conv_std_logic_vector(357,11); WHEN "0111001110" => manhi <= conv_std_logic_vector(6539982,24); manlo <= conv_std_logic_vector(56762382,28); exponent <= conv_std_logic_vector(356,11); WHEN "0111001111" => manhi <= conv_std_logic_vector(378619,24); manlo <= conv_std_logic_vector(186677702,28); exponent <= conv_std_logic_vector(355,11); WHEN "0111010000" => manhi <= conv_std_logic_vector(8467900,24); manlo <= conv_std_logic_vector(266785510,28); exponent <= conv_std_logic_vector(353,11); WHEN "0111010001" => manhi <= conv_std_logic_vector(1797103,24); manlo <= conv_std_logic_vector(17183357,28); exponent <= conv_std_logic_vector(352,11); WHEN "0111010010" => manhi <= conv_std_logic_vector(10555224,24); manlo <= conv_std_logic_vector(126067134,28); exponent <= conv_std_logic_vector(350,11); WHEN "0111010011" => manhi <= conv_std_logic_vector(3332869,24); manlo <= conv_std_logic_vector(228611260,28); exponent <= conv_std_logic_vector(349,11); WHEN "0111010100" => manhi <= conv_std_logic_vector(12815132,24); manlo <= conv_std_logic_vector(155705738,28); exponent <= conv_std_logic_vector(347,11); WHEN "0111010101" => manhi <= conv_std_logic_vector(4995617,24); manlo <= conv_std_logic_vector(85136440,28); exponent <= conv_std_logic_vector(346,11); WHEN "0111010110" => manhi <= conv_std_logic_vector(15261895,24); manlo <= conv_std_logic_vector(3688335,28); exponent <= conv_std_logic_vector(344,11); WHEN "0111010111" => manhi <= conv_std_logic_vector(6795844,24); manlo <= conv_std_logic_vector(137097782,28); exponent <= conv_std_logic_vector(343,11); WHEN "0111011000" => manhi <= conv_std_logic_vector(566872,24); manlo <= conv_std_logic_vector(175764875,28); exponent <= conv_std_logic_vector(342,11); WHEN "0111011001" => manhi <= conv_std_logic_vector(8744918,24); manlo <= conv_std_logic_vector(152414052,28); exponent <= conv_std_logic_vector(340,11); WHEN "0111011010" => manhi <= conv_std_logic_vector(2000921,24); manlo <= conv_std_logic_vector(54921723,28); exponent <= conv_std_logic_vector(339,11); WHEN "0111011011" => manhi <= conv_std_logic_vector(10855146,24); manlo <= conv_std_logic_vector(129996510,28); exponent <= conv_std_logic_vector(337,11); WHEN "0111011100" => manhi <= conv_std_logic_vector(3553540,24); manlo <= conv_std_logic_vector(37023540,28); exponent <= conv_std_logic_vector(336,11); WHEN "0111011101" => manhi <= conv_std_logic_vector(13139852,24); manlo <= conv_std_logic_vector(221848100,28); exponent <= conv_std_logic_vector(334,11); WHEN "0111011110" => manhi <= conv_std_logic_vector(5234533,24); manlo <= conv_std_logic_vector(32943194,28); exponent <= conv_std_logic_vector(333,11); WHEN "0111011111" => manhi <= conv_std_logic_vector(15613463,24); manlo <= conv_std_logic_vector(232436445,28); exponent <= conv_std_logic_vector(331,11); WHEN "0111100000" => manhi <= conv_std_logic_vector(7054514,24); manlo <= conv_std_logic_vector(111791498,28); exponent <= conv_std_logic_vector(330,11); WHEN "0111100001" => manhi <= conv_std_logic_vector(757191,24); manlo <= conv_std_logic_vector(90062360,28); exponent <= conv_std_logic_vector(329,11); WHEN "0111100010" => manhi <= conv_std_logic_vector(9024975,24); manlo <= conv_std_logic_vector(238219590,28); exponent <= conv_std_logic_vector(327,11); WHEN "0111100011" => manhi <= conv_std_logic_vector(2206975,24); manlo <= conv_std_logic_vector(232222812,28); exponent <= conv_std_logic_vector(326,11); WHEN "0111100100" => manhi <= conv_std_logic_vector(11158359,24); manlo <= conv_std_logic_vector(155073518,28); exponent <= conv_std_logic_vector(324,11); WHEN "0111100101" => manhi <= conv_std_logic_vector(3776631,24); manlo <= conv_std_logic_vector(232102510,28); exponent <= conv_std_logic_vector(323,11); WHEN "0111100110" => manhi <= conv_std_logic_vector(13468136,24); manlo <= conv_std_logic_vector(71264246,28); exponent <= conv_std_logic_vector(321,11); WHEN "0111100111" => manhi <= conv_std_logic_vector(5476070,24); manlo <= conv_std_logic_vector(155401688,28); exponent <= conv_std_logic_vector(320,11); WHEN "0111101000" => manhi <= conv_std_logic_vector(15968890,24); manlo <= conv_std_logic_vector(140531032,28); exponent <= conv_std_logic_vector(318,11); WHEN "0111101001" => manhi <= conv_std_logic_vector(7316022,24); manlo <= conv_std_logic_vector(197790036,28); exponent <= conv_std_logic_vector(317,11); WHEN "0111101010" => manhi <= conv_std_logic_vector(949598,24); manlo <= conv_std_logic_vector(108723575,28); exponent <= conv_std_logic_vector(316,11); WHEN "0111101011" => manhi <= conv_std_logic_vector(9308106,24); manlo <= conv_std_logic_vector(82754530,28); exponent <= conv_std_logic_vector(314,11); WHEN "0111101100" => manhi <= conv_std_logic_vector(2415291,24); manlo <= conv_std_logic_vector(157597766,28); exponent <= conv_std_logic_vector(313,11); WHEN "0111101101" => manhi <= conv_std_logic_vector(11464899,24); manlo <= conv_std_logic_vector(231735034,28); exponent <= conv_std_logic_vector(311,11); WHEN "0111101110" => manhi <= conv_std_logic_vector(4002171,24); manlo <= conv_std_logic_vector(161749904,28); exponent <= conv_std_logic_vector(310,11); WHEN "0111101111" => manhi <= conv_std_logic_vector(13800021,24); manlo <= conv_std_logic_vector(267486845,28); exponent <= conv_std_logic_vector(308,11); WHEN "0111110000" => manhi <= conv_std_logic_vector(5720258,24); manlo <= conv_std_logic_vector(121711942,28); exponent <= conv_std_logic_vector(307,11); WHEN "0111110001" => manhi <= conv_std_logic_vector(16328217,24); manlo <= conv_std_logic_vector(85566619,28); exponent <= conv_std_logic_vector(305,11); WHEN "0111110010" => manhi <= conv_std_logic_vector(7580400,24); manlo <= conv_std_logic_vector(165916765,28); exponent <= conv_std_logic_vector(304,11); WHEN "0111110011" => manhi <= conv_std_logic_vector(1144116,24); manlo <= conv_std_logic_vector(209234965,28); exponent <= conv_std_logic_vector(303,11); WHEN "0111110100" => manhi <= conv_std_logic_vector(9594343,24); manlo <= conv_std_logic_vector(148128653,28); exponent <= conv_std_logic_vector(301,11); WHEN "0111110101" => manhi <= conv_std_logic_vector(2625893,24); manlo <= conv_std_logic_vector(48717694,28); exponent <= conv_std_logic_vector(300,11); WHEN "0111110110" => manhi <= conv_std_logic_vector(11774803,24); manlo <= conv_std_logic_vector(228357100,28); exponent <= conv_std_logic_vector(298,11); WHEN "0111110111" => manhi <= conv_std_logic_vector(4230186,24); manlo <= conv_std_logic_vector(57439900,28); exponent <= conv_std_logic_vector(297,11); WHEN "0111111000" => manhi <= conv_std_logic_vector(14135549,24); manlo <= conv_std_logic_vector(147041206,28); exponent <= conv_std_logic_vector(295,11); WHEN "0111111001" => manhi <= conv_std_logic_vector(5967125,24); manlo <= conv_std_logic_vector(222682176,28); exponent <= conv_std_logic_vector(294,11); WHEN "0111111010" => manhi <= conv_std_logic_vector(16691487,24); manlo <= conv_std_logic_vector(12959237,28); exponent <= conv_std_logic_vector(292,11); WHEN "0111111011" => manhi <= conv_std_logic_vector(7847679,24); manlo <= conv_std_logic_vector(147174066,28); exponent <= conv_std_logic_vector(291,11); WHEN "0111111100" => manhi <= conv_std_logic_vector(1340769,24); manlo <= conv_std_logic_vector(168148656,28); exponent <= conv_std_logic_vector(290,11); WHEN "0111111101" => manhi <= conv_std_logic_vector(9883721,24); manlo <= conv_std_logic_vector(190474495,28); exponent <= conv_std_logic_vector(288,11); WHEN "0111111110" => manhi <= conv_std_logic_vector(2838805,24); manlo <= conv_std_logic_vector(196335986,28); exponent <= conv_std_logic_vector(287,11); WHEN "0111111111" => manhi <= conv_std_logic_vector(12088108,24); manlo <= conv_std_logic_vector(120857634,28); exponent <= conv_std_logic_vector(285,11); WHEN "1000000000" => manhi <= conv_std_logic_vector(4460702,24); manlo <= conv_std_logic_vector(229771569,28); exponent <= conv_std_logic_vector(284,11); WHEN "1000000001" => manhi <= conv_std_logic_vector(14474758,24); manlo <= conv_std_logic_vector(236628147,28); exponent <= conv_std_logic_vector(282,11); WHEN "1000000010" => manhi <= conv_std_logic_vector(6216702,24); manlo <= conv_std_logic_vector(29481361,28); exponent <= conv_std_logic_vector(281,11); WHEN "1000000011" => manhi <= conv_std_logic_vector(140763,24); manlo <= conv_std_logic_vector(131310533,28); exponent <= conv_std_logic_vector(280,11); WHEN "1000000100" => manhi <= conv_std_logic_vector(8117891,24); manlo <= conv_std_logic_vector(96879140,28); exponent <= conv_std_logic_vector(278,11); WHEN "1000000101" => manhi <= conv_std_logic_vector(1539580,24); manlo <= conv_std_logic_vector(98694067,28); exponent <= conv_std_logic_vector(277,11); WHEN "1000000110" => manhi <= conv_std_logic_vector(10176275,24); manlo <= conv_std_logic_vector(66343668,28); exponent <= conv_std_logic_vector(275,11); WHEN "1000000111" => manhi <= conv_std_logic_vector(3054054,24); manlo <= conv_std_logic_vector(159783892,28); exponent <= conv_std_logic_vector(274,11); WHEN "1000001000" => manhi <= conv_std_logic_vector(12404850,24); manlo <= conv_std_logic_vector(262311967,28); exponent <= conv_std_logic_vector(272,11); WHEN "1000001001" => manhi <= conv_std_logic_vector(4693748,24); manlo <= conv_std_logic_vector(264030756,28); exponent <= conv_std_logic_vector(271,11); WHEN "1000001010" => manhi <= conv_std_logic_vector(14817690,24); manlo <= conv_std_logic_vector(106917994,28); exponent <= conv_std_logic_vector(269,11); WHEN "1000001011" => manhi <= conv_std_logic_vector(6469017,24); manlo <= conv_std_logic_vector(5191992,28); exponent <= conv_std_logic_vector(268,11); WHEN "1000001100" => manhi <= conv_std_logic_vector(326406,24); manlo <= conv_std_logic_vector(114083215,28); exponent <= conv_std_logic_vector(267,11); WHEN "1000001101" => manhi <= conv_std_logic_vector(8391068,24); manlo <= conv_std_logic_vector(64117214,28); exponent <= conv_std_logic_vector(265,11); WHEN "1000001110" => manhi <= conv_std_logic_vector(1740572,24); manlo <= conv_std_logic_vector(183091279,28); exponent <= conv_std_logic_vector(264,11); WHEN "1000001111" => manhi <= conv_std_logic_vector(10472039,24); manlo <= conv_std_logic_vector(2244224,28); exponent <= conv_std_logic_vector(262,11); WHEN "1000010000" => manhi <= conv_std_logic_vector(3271665,24); manlo <= conv_std_logic_vector(109958542,28); exponent <= conv_std_logic_vector(261,11); WHEN "1000010001" => manhi <= conv_std_logic_vector(12725069,24); manlo <= conv_std_logic_vector(41968573,28); exponent <= conv_std_logic_vector(259,11); WHEN "1000010010" => manhi <= conv_std_logic_vector(4929352,24); manlo <= conv_std_logic_vector(94809674,28); exponent <= conv_std_logic_vector(258,11); WHEN "1000010011" => manhi <= conv_std_logic_vector(15164384,24); manlo <= conv_std_logic_vector(252890425,28); exponent <= conv_std_logic_vector(256,11); WHEN "1000010100" => manhi <= conv_std_logic_vector(6724100,24); manlo <= conv_std_logic_vector(163583158,28); exponent <= conv_std_logic_vector(255,11); WHEN "1000010101" => manhi <= conv_std_logic_vector(514086,24); manlo <= conv_std_logic_vector(118679222,28); exponent <= conv_std_logic_vector(254,11); WHEN "1000010110" => manhi <= conv_std_logic_vector(8667242,24); manlo <= conv_std_logic_vector(192770478,28); exponent <= conv_std_logic_vector(252,11); WHEN "1000010111" => manhi <= conv_std_logic_vector(1943770,24); manlo <= conv_std_logic_vector(136437165,28); exponent <= conv_std_logic_vector(251,11); WHEN "1000011000" => manhi <= conv_std_logic_vector(10771048,24); manlo <= conv_std_logic_vector(58883744,28); exponent <= conv_std_logic_vector(249,11); WHEN "1000011001" => manhi <= conv_std_logic_vector(3491664,24); manlo <= conv_std_logic_vector(24836209,28); exponent <= conv_std_logic_vector(248,11); WHEN "1000011010" => manhi <= conv_std_logic_vector(13048801,24); manlo <= conv_std_logic_vector(33938829,28); exponent <= conv_std_logic_vector(246,11); WHEN "1000011011" => manhi <= conv_std_logic_vector(5167541,24); manlo <= conv_std_logic_vector(6894318,28); exponent <= conv_std_logic_vector(245,11); WHEN "1000011100" => manhi <= conv_std_logic_vector(15514883,24); manlo <= conv_std_logic_vector(216092120,28); exponent <= conv_std_logic_vector(243,11); WHEN "1000011101" => manhi <= conv_std_logic_vector(6981983,24); manlo <= conv_std_logic_vector(70071320,28); exponent <= conv_std_logic_vector(242,11); WHEN "1000011110" => manhi <= conv_std_logic_vector(703825,24); manlo <= conv_std_logic_vector(239890498,28); exponent <= conv_std_logic_vector(241,11); WHEN "1000011111" => manhi <= conv_std_logic_vector(8946447,24); manlo <= conv_std_logic_vector(185687386,28); exponent <= conv_std_logic_vector(239,11); WHEN "1000100000" => manhi <= conv_std_logic_vector(2149198,24); manlo <= conv_std_logic_vector(12777107,28); exponent <= conv_std_logic_vector(238,11); WHEN "1000100001" => manhi <= conv_std_logic_vector(11073338,24); manlo <= conv_std_logic_vector(132295567,28); exponent <= conv_std_logic_vector(236,11); WHEN "1000100010" => manhi <= conv_std_logic_vector(3714076,24); manlo <= conv_std_logic_vector(227171857,28); exponent <= conv_std_logic_vector(235,11); WHEN "1000100011" => manhi <= conv_std_logic_vector(13376085,24); manlo <= conv_std_logic_vector(119368169,28); exponent <= conv_std_logic_vector(233,11); WHEN "1000100100" => manhi <= conv_std_logic_vector(5408343,24); manlo <= conv_std_logic_vector(99290689,28); exponent <= conv_std_logic_vector(232,11); WHEN "1000100101" => manhi <= conv_std_logic_vector(15869228,24); manlo <= conv_std_logic_vector(196569651,28); exponent <= conv_std_logic_vector(230,11); WHEN "1000100110" => manhi <= conv_std_logic_vector(7242695,24); manlo <= conv_std_logic_vector(184868911,28); exponent <= conv_std_logic_vector(229,11); WHEN "1000100111" => manhi <= conv_std_logic_vector(895647,24); manlo <= conv_std_logic_vector(101480846,28); exponent <= conv_std_logic_vector(228,11); WHEN "1000101000" => manhi <= conv_std_logic_vector(9228716,24); manlo <= conv_std_logic_vector(111040654,28); exponent <= conv_std_logic_vector(226,11); WHEN "1000101001" => manhi <= conv_std_logic_vector(2356879,24); manlo <= conv_std_logic_vector(205878747,28); exponent <= conv_std_logic_vector(225,11); WHEN "1000101010" => manhi <= conv_std_logic_vector(11378945,24); manlo <= conv_std_logic_vector(223412824,28); exponent <= conv_std_logic_vector(223,11); WHEN "1000101011" => manhi <= conv_std_logic_vector(3938930,24); manlo <= conv_std_logic_vector(43159582,28); exponent <= conv_std_logic_vector(222,11); WHEN "1000101100" => manhi <= conv_std_logic_vector(13706961,24); manlo <= conv_std_logic_vector(24539717,28); exponent <= conv_std_logic_vector(220,11); WHEN "1000101101" => manhi <= conv_std_logic_vector(5651788,24); manlo <= conv_std_logic_vector(17696328,28); exponent <= conv_std_logic_vector(219,11); WHEN "1000101110" => manhi <= conv_std_logic_vector(16227461,24); manlo <= conv_std_logic_vector(248897772,28); exponent <= conv_std_logic_vector(217,11); WHEN "1000101111" => manhi <= conv_std_logic_vector(7506268,24); manlo <= conv_std_logic_vector(253353585,28); exponent <= conv_std_logic_vector(216,11); WHEN "1000110000" => manhi <= conv_std_logic_vector(1089573,24); manlo <= conv_std_logic_vector(199085712,28); exponent <= conv_std_logic_vector(215,11); WHEN "1000110001" => manhi <= conv_std_logic_vector(9514082,24); manlo <= conv_std_logic_vector(134954983,28); exponent <= conv_std_logic_vector(213,11); WHEN "1000110010" => manhi <= conv_std_logic_vector(2566840,24); manlo <= conv_std_logic_vector(107836942,28); exponent <= conv_std_logic_vector(212,11); WHEN "1000110011" => manhi <= conv_std_logic_vector(11687906,24); manlo <= conv_std_logic_vector(170784064,28); exponent <= conv_std_logic_vector(210,11); WHEN "1000110100" => manhi <= conv_std_logic_vector(4166250,24); manlo <= conv_std_logic_vector(219198631,28); exponent <= conv_std_logic_vector(209,11); WHEN "1000110101" => manhi <= conv_std_logic_vector(14041467,24); manlo <= conv_std_logic_vector(127426909,28); exponent <= conv_std_logic_vector(207,11); WHEN "1000110110" => manhi <= conv_std_logic_vector(5897904,24); manlo <= conv_std_logic_vector(29159081,28); exponent <= conv_std_logic_vector(206,11); WHEN "1000110111" => manhi <= conv_std_logic_vector(16589626,24); manlo <= conv_std_logic_vector(15093248,28); exponent <= conv_std_logic_vector(204,11); WHEN "1000111000" => manhi <= conv_std_logic_vector(7772734,24); manlo <= conv_std_logic_vector(112367334,28); exponent <= conv_std_logic_vector(203,11); WHEN "1000111001" => manhi <= conv_std_logic_vector(1285628,24); manlo <= conv_std_logic_vector(21894417,28); exponent <= conv_std_logic_vector(202,11); WHEN "1000111010" => manhi <= conv_std_logic_vector(9802579,24); manlo <= conv_std_logic_vector(254146435,28); exponent <= conv_std_logic_vector(200,11); WHEN "1000111011" => manhi <= conv_std_logic_vector(2779104,24); manlo <= conv_std_logic_vector(257348234,28); exponent <= conv_std_logic_vector(199,11); WHEN "1000111100" => manhi <= conv_std_logic_vector(12000257,24); manlo <= conv_std_logic_vector(188607876,28); exponent <= conv_std_logic_vector(197,11); WHEN "1000111101" => manhi <= conv_std_logic_vector(4396065,24); manlo <= conv_std_logic_vector(238395052,28); exponent <= conv_std_logic_vector(196,11); WHEN "1000111110" => manhi <= conv_std_logic_vector(14379644,24); manlo <= conv_std_logic_vector(116776141,28); exponent <= conv_std_logic_vector(194,11); WHEN "1000111111" => manhi <= conv_std_logic_vector(6146720,24); manlo <= conv_std_logic_vector(217697734,28); exponent <= conv_std_logic_vector(193,11); WHEN "1001000000" => manhi <= conv_std_logic_vector(89274,24); manlo <= conv_std_logic_vector(34078121,28); exponent <= conv_std_logic_vector(192,11); WHEN "1001000001" => manhi <= conv_std_logic_vector(8042123,24); manlo <= conv_std_logic_vector(228091050,28); exponent <= conv_std_logic_vector(190,11); WHEN "1001000010" => manhi <= conv_std_logic_vector(1483833,24); manlo <= conv_std_logic_vector(200872250,28); exponent <= conv_std_logic_vector(189,11); WHEN "1001000011" => manhi <= conv_std_logic_vector(10094243,24); manlo <= conv_std_logic_vector(28573613,28); exponent <= conv_std_logic_vector(187,11); WHEN "1001000100" => manhi <= conv_std_logic_vector(2993698,24); manlo <= conv_std_logic_vector(193026703,28); exponent <= conv_std_logic_vector(186,11); WHEN "1001000101" => manhi <= conv_std_logic_vector(12316036,24); manlo <= conv_std_logic_vector(62602992,28); exponent <= conv_std_logic_vector(184,11); WHEN "1001000110" => manhi <= conv_std_logic_vector(4628402,24); manlo <= conv_std_logic_vector(200475490,28); exponent <= conv_std_logic_vector(183,11); WHEN "1001000111" => manhi <= conv_std_logic_vector(14721532,24); manlo <= conv_std_logic_vector(67122338,28); exponent <= conv_std_logic_vector(181,11); WHEN "1001001000" => manhi <= conv_std_logic_vector(6398267,24); manlo <= conv_std_logic_vector(216803728,28); exponent <= conv_std_logic_vector(180,11); WHEN "1001001001" => manhi <= conv_std_logic_vector(274352,24); manlo <= conv_std_logic_vector(17200594,28); exponent <= conv_std_logic_vector(179,11); WHEN "1001001010" => manhi <= conv_std_logic_vector(8314469,24); manlo <= conv_std_logic_vector(86446456,28); exponent <= conv_std_logic_vector(177,11); WHEN "1001001011" => manhi <= conv_std_logic_vector(1684214,24); manlo <= conv_std_logic_vector(93587914,28); exponent <= conv_std_logic_vector(176,11); WHEN "1001001100" => manhi <= conv_std_logic_vector(10389106,24); manlo <= conv_std_logic_vector(193148951,28); exponent <= conv_std_logic_vector(174,11); WHEN "1001001101" => manhi <= conv_std_logic_vector(3210647,24); manlo <= conv_std_logic_vector(64824977,28); exponent <= conv_std_logic_vector(173,11); WHEN "1001001110" => manhi <= conv_std_logic_vector(12635279,24); manlo <= conv_std_logic_vector(224939505,28); exponent <= conv_std_logic_vector(171,11); WHEN "1001001111" => manhi <= conv_std_logic_vector(4863289,24); manlo <= conv_std_logic_vector(17355920,28); exponent <= conv_std_logic_vector(170,11); WHEN "1001010000" => manhi <= conv_std_logic_vector(15067171,24); manlo <= conv_std_logic_vector(171641236,28); exponent <= conv_std_logic_vector(168,11); WHEN "1001010001" => manhi <= conv_std_logic_vector(6652575,24); manlo <= conv_std_logic_vector(15694991,28); exponent <= conv_std_logic_vector(167,11); WHEN "1001010010" => manhi <= conv_std_logic_vector(461460,24); manlo <= conv_std_logic_vector(236949593,28); exponent <= conv_std_logic_vector(166,11); WHEN "1001010011" => manhi <= conv_std_logic_vector(8589803,24); manlo <= conv_std_logic_vector(73170085,28); exponent <= conv_std_logic_vector(164,11); WHEN "1001010100" => manhi <= conv_std_logic_vector(1886793,24); manlo <= conv_std_logic_vector(200887360,28); exponent <= conv_std_logic_vector(163,11); WHEN "1001010101" => manhi <= conv_std_logic_vector(10687205,24); manlo <= conv_std_logic_vector(242930225,28); exponent <= conv_std_logic_vector(161,11); WHEN "1001010110" => manhi <= conv_std_logic_vector(3429976,24); manlo <= conv_std_logic_vector(97980458,28); exponent <= conv_std_logic_vector(160,11); WHEN "1001010111" => manhi <= conv_std_logic_vector(12958026,24); manlo <= conv_std_logic_vector(144828568,28); exponent <= conv_std_logic_vector(158,11); WHEN "1001011000" => manhi <= conv_std_logic_vector(5100752,24); manlo <= conv_std_logic_vector(219332721,28); exponent <= conv_std_logic_vector(157,11); WHEN "1001011001" => manhi <= conv_std_logic_vector(15416603,24); manlo <= conv_std_logic_vector(206580322,28); exponent <= conv_std_logic_vector(155,11); WHEN "1001011010" => manhi <= conv_std_logic_vector(6909672,24); manlo <= conv_std_logic_vector(228709240,28); exponent <= conv_std_logic_vector(154,11); WHEN "1001011011" => manhi <= conv_std_logic_vector(650622,24); manlo <= conv_std_logic_vector(232984198,28); exponent <= conv_std_logic_vector(153,11); WHEN "1001011100" => manhi <= conv_std_logic_vector(8868158,24); manlo <= conv_std_logic_vector(132673062,28); exponent <= conv_std_logic_vector(151,11); WHEN "1001011101" => manhi <= conv_std_logic_vector(2091596,24); manlo <= conv_std_logic_vector(20173170,28); exponent <= conv_std_logic_vector(150,11); WHEN "1001011110" => manhi <= conv_std_logic_vector(10988576,24); manlo <= conv_std_logic_vector(44856082,28); exponent <= conv_std_logic_vector(148,11); WHEN "1001011111" => manhi <= conv_std_logic_vector(3651712,24); manlo <= conv_std_logic_vector(56970522,28); exponent <= conv_std_logic_vector(147,11); WHEN "1001100000" => manhi <= conv_std_logic_vector(13284314,24); manlo <= conv_std_logic_vector(208786223,28); exponent <= conv_std_logic_vector(145,11); WHEN "1001100001" => manhi <= conv_std_logic_vector(5340822,24); manlo <= conv_std_logic_vector(76928898,28); exponent <= conv_std_logic_vector(144,11); WHEN "1001100010" => manhi <= conv_std_logic_vector(15769870,24); manlo <= conv_std_logic_vector(69445892,28); exponent <= conv_std_logic_vector(142,11); WHEN "1001100011" => manhi <= conv_std_logic_vector(7169591,24); manlo <= conv_std_logic_vector(217224162,28); exponent <= conv_std_logic_vector(141,11); WHEN "1001100100" => manhi <= conv_std_logic_vector(841860,24); manlo <= conv_std_logic_vector(147476782,28); exponent <= conv_std_logic_vector(140,11); WHEN "1001100101" => manhi <= conv_std_logic_vector(9149568,24); manlo <= conv_std_logic_vector(37524984,28); exponent <= conv_std_logic_vector(138,11); WHEN "1001100110" => manhi <= conv_std_logic_vector(2298645,24); manlo <= conv_std_logic_vector(193659590,28); exponent <= conv_std_logic_vector(137,11); WHEN "1001100111" => manhi <= conv_std_logic_vector(11293253,24); manlo <= conv_std_logic_vector(107316618,28); exponent <= conv_std_logic_vector(135,11); WHEN "1001101000" => manhi <= conv_std_logic_vector(3875881,24); manlo <= conv_std_logic_vector(51654059,28); exponent <= conv_std_logic_vector(134,11); WHEN "1001101001" => manhi <= conv_std_logic_vector(13614183,24); manlo <= conv_std_logic_vector(111249634,28); exponent <= conv_std_logic_vector(132,11); WHEN "1001101010" => manhi <= conv_std_logic_vector(5583526,24); manlo <= conv_std_logic_vector(17717412,28); exponent <= conv_std_logic_vector(131,11); WHEN "1001101011" => manhi <= conv_std_logic_vector(16127013,24); manlo <= conv_std_logic_vector(48769099,28); exponent <= conv_std_logic_vector(129,11); WHEN "1001101100" => manhi <= conv_std_logic_vector(7432362,24); manlo <= conv_std_logic_vector(238120049,28); exponent <= conv_std_logic_vector(128,11); WHEN "1001101101" => manhi <= conv_std_logic_vector(1035196,24); manlo <= conv_std_logic_vector(188962402,28); exponent <= conv_std_logic_vector(127,11); WHEN "1001101110" => manhi <= conv_std_logic_vector(9434065,24); manlo <= conv_std_logic_vector(194820226,28); exponent <= conv_std_logic_vector(125,11); WHEN "1001101111" => manhi <= conv_std_logic_vector(2507967,24); manlo <= conv_std_logic_vector(93233285,28); exponent <= conv_std_logic_vector(124,11); WHEN "1001110000" => manhi <= conv_std_logic_vector(11601273,24); manlo <= conv_std_logic_vector(239123672,28); exponent <= conv_std_logic_vector(122,11); WHEN "1001110001" => manhi <= conv_std_logic_vector(4102510,24); manlo <= conv_std_logic_vector(1244898,28); exponent <= conv_std_logic_vector(121,11); WHEN "1001110010" => manhi <= conv_std_logic_vector(13947671,24); manlo <= conv_std_logic_vector(197996828,28); exponent <= conv_std_logic_vector(119,11); WHEN "1001110011" => manhi <= conv_std_logic_vector(5828893,24); manlo <= conv_std_logic_vector(16622593,28); exponent <= conv_std_logic_vector(118,11); WHEN "1001110100" => manhi <= conv_std_logic_vector(16488075,24); manlo <= conv_std_logic_vector(20144764,28); exponent <= conv_std_logic_vector(116,11); WHEN "1001110101" => manhi <= conv_std_logic_vector(7698017,24); manlo <= conv_std_logic_vector(102592250,28); exponent <= conv_std_logic_vector(115,11); WHEN "1001110110" => manhi <= conv_std_logic_vector(1230654,24); manlo <= conv_std_logic_vector(96196092,28); exponent <= conv_std_logic_vector(114,11); WHEN "1001110111" => manhi <= conv_std_logic_vector(9721685,24); manlo <= conv_std_logic_vector(36636777,28); exponent <= conv_std_logic_vector(112,11); WHEN "1001111000" => manhi <= conv_std_logic_vector(2719585,24); manlo <= conv_std_logic_vector(237160861,28); exponent <= conv_std_logic_vector(111,11); WHEN "1001111001" => manhi <= conv_std_logic_vector(11912674,24); manlo <= conv_std_logic_vector(87541902,28); exponent <= conv_std_logic_vector(109,11); WHEN "1001111010" => manhi <= conv_std_logic_vector(4331625,24); manlo <= conv_std_logic_vector(172036325,28); exponent <= conv_std_logic_vector(108,11); WHEN "1001111011" => manhi <= conv_std_logic_vector(14284819,24); manlo <= conv_std_logic_vector(125225503,28); exponent <= conv_std_logic_vector(106,11); WHEN "1001111100" => manhi <= conv_std_logic_vector(6076952,24); manlo <= conv_std_logic_vector(133715238,28); exponent <= conv_std_logic_vector(105,11); WHEN "1001111101" => manhi <= conv_std_logic_vector(37941,24); manlo <= conv_std_logic_vector(126448851,28); exponent <= conv_std_logic_vector(104,11); WHEN "1001111110" => manhi <= conv_std_logic_vector(7966586,24); manlo <= conv_std_logic_vector(250893596,28); exponent <= conv_std_logic_vector(102,11); WHEN "1001111111" => manhi <= conv_std_logic_vector(1428256,24); manlo <= conv_std_logic_vector(212630882,28); exponent <= conv_std_logic_vector(101,11); WHEN "1010000000" => manhi <= conv_std_logic_vector(10012460,24); manlo <= conv_std_logic_vector(168603206,28); exponent <= conv_std_logic_vector(99,11); WHEN "1010000001" => manhi <= conv_std_logic_vector(2933526,24); manlo <= conv_std_logic_vector(143402282,28); exponent <= conv_std_logic_vector(98,11); WHEN "1010000010" => manhi <= conv_std_logic_vector(12227491,24); manlo <= conv_std_logic_vector(213203509,28); exponent <= conv_std_logic_vector(96,11); WHEN "1010000011" => manhi <= conv_std_logic_vector(4563255,24); manlo <= conv_std_logic_vector(104522224,28); exponent <= conv_std_logic_vector(95,11); WHEN "1010000100" => manhi <= conv_std_logic_vector(14625666,24); manlo <= conv_std_logic_vector(203000190,28); exponent <= conv_std_logic_vector(93,11); WHEN "1010000101" => manhi <= conv_std_logic_vector(6327733,24); manlo <= conv_std_logic_vector(246711469,28); exponent <= conv_std_logic_vector(92,11); WHEN "1010000110" => manhi <= conv_std_logic_vector(222456,24); manlo <= conv_std_logic_vector(34640152,28); exponent <= conv_std_logic_vector(91,11); WHEN "1010000111" => manhi <= conv_std_logic_vector(8238103,24); manlo <= conv_std_logic_vector(142733230,28); exponent <= conv_std_logic_vector(89,11); WHEN "1010001000" => manhi <= conv_std_logic_vector(1628027,24); manlo <= conv_std_logic_vector(144984792,28); exponent <= conv_std_logic_vector(88,11); WHEN "1010001001" => manhi <= conv_std_logic_vector(10306426,24); manlo <= conv_std_logic_vector(223510234,28); exponent <= conv_std_logic_vector(86,11); WHEN "1010001010" => manhi <= conv_std_logic_vector(3149814,24); manlo <= conv_std_logic_vector(209464872,28); exponent <= conv_std_logic_vector(85,11); WHEN "1010001011" => manhi <= conv_std_logic_vector(12545763,24); manlo <= conv_std_logic_vector(212245812,28); exponent <= conv_std_logic_vector(83,11); WHEN "1010001100" => manhi <= conv_std_logic_vector(4797426,24); manlo <= conv_std_logic_vector(224882259,28); exponent <= conv_std_logic_vector(82,11); WHEN "1010001101" => manhi <= conv_std_logic_vector(14970254,24); manlo <= conv_std_logic_vector(54358776,28); exponent <= conv_std_logic_vector(80,11); WHEN "1010001110" => manhi <= conv_std_logic_vector(6581267,24); manlo <= conv_std_logic_vector(51917314,28); exponent <= conv_std_logic_vector(79,11); WHEN "1010001111" => manhi <= conv_std_logic_vector(408995,24); manlo <= conv_std_logic_vector(130890803,28); exponent <= conv_std_logic_vector(78,11); WHEN "1010010000" => manhi <= conv_std_logic_vector(8512599,24); manlo <= conv_std_logic_vector(137347476,28); exponent <= conv_std_logic_vector(76,11); WHEN "1010010001" => manhi <= conv_std_logic_vector(1829990,24); manlo <= conv_std_logic_vector(106170554,28); exponent <= conv_std_logic_vector(75,11); WHEN "1010010010" => manhi <= conv_std_logic_vector(10603618,24); manlo <= conv_std_logic_vector(204595238,28); exponent <= conv_std_logic_vector(73,11); WHEN "1010010011" => manhi <= conv_std_logic_vector(3368476,24); manlo <= conv_std_logic_vector(102605239,28); exponent <= conv_std_logic_vector(72,11); WHEN "1010010100" => manhi <= conv_std_logic_vector(12867528,24); manlo <= conv_std_logic_vector(59687307,28); exponent <= conv_std_logic_vector(70,11); WHEN "1010010101" => manhi <= conv_std_logic_vector(5034167,24); manlo <= conv_std_logic_vector(235251142,28); exponent <= conv_std_logic_vector(69,11); WHEN "1010010110" => manhi <= conv_std_logic_vector(15318622,24); manlo <= conv_std_logic_vector(227223140,28); exponent <= conv_std_logic_vector(67,11); WHEN "1010010111" => manhi <= conv_std_logic_vector(6837582,24); manlo <= conv_std_logic_vector(138925467,28); exponent <= conv_std_logic_vector(66,11); WHEN "1010011000" => manhi <= conv_std_logic_vector(597581,24); manlo <= conv_std_logic_vector(205088968,28); exponent <= conv_std_logic_vector(65,11); WHEN "1010011001" => manhi <= conv_std_logic_vector(8790107,24); manlo <= conv_std_logic_vector(152356460,28); exponent <= conv_std_logic_vector(63,11); WHEN "1010011010" => manhi <= conv_std_logic_vector(2034169,24); manlo <= conv_std_logic_vector(110749946,28); exponent <= conv_std_logic_vector(62,11); WHEN "1010011011" => manhi <= conv_std_logic_vector(10904071,24); manlo <= conv_std_logic_vector(218226183,28); exponent <= conv_std_logic_vector(60,11); WHEN "1010011100" => manhi <= conv_std_logic_vector(3589537,24); manlo <= conv_std_logic_vector(102830143,28); exponent <= conv_std_logic_vector(59,11); WHEN "1010011101" => manhi <= conv_std_logic_vector(13192823,24); manlo <= conv_std_logic_vector(110639602,28); exponent <= conv_std_logic_vector(57,11); WHEN "1010011110" => manhi <= conv_std_logic_vector(5273506,24); manlo <= conv_std_logic_vector(188352155,28); exponent <= conv_std_logic_vector(56,11); WHEN "1010011111" => manhi <= conv_std_logic_vector(15670814,24); manlo <= conv_std_logic_vector(48227643,28); exponent <= conv_std_logic_vector(54,11); WHEN "1010100000" => manhi <= conv_std_logic_vector(7096710,24); manlo <= conv_std_logic_vector(112532514,28); exponent <= conv_std_logic_vector(53,11); WHEN "1010100001" => manhi <= conv_std_logic_vector(788237,24); manlo <= conv_std_logic_vector(112565412,28); exponent <= conv_std_logic_vector(52,11); WHEN "1010100010" => manhi <= conv_std_logic_vector(9070660,24); manlo <= conv_std_logic_vector(201680253,28); exponent <= conv_std_logic_vector(50,11); WHEN "1010100011" => manhi <= conv_std_logic_vector(2240588,24); manlo <= conv_std_logic_vector(244138286,28); exponent <= conv_std_logic_vector(49,11); WHEN "1010100100" => manhi <= conv_std_logic_vector(11207821,24); manlo <= conv_std_logic_vector(206597824,28); exponent <= conv_std_logic_vector(47,11); WHEN "1010100101" => manhi <= conv_std_logic_vector(3813024,24); manlo <= conv_std_logic_vector(29987310,28); exponent <= conv_std_logic_vector(46,11); WHEN "1010100110" => manhi <= conv_std_logic_vector(13521688,24); manlo <= conv_std_logic_vector(27790821,28); exponent <= conv_std_logic_vector(44,11); WHEN "1010100111" => manhi <= conv_std_logic_vector(5515471,24); manlo <= conv_std_logic_vector(219963166,28); exponent <= conv_std_logic_vector(43,11); WHEN "1010101000" => manhi <= conv_std_logic_vector(16026870,24); manlo <= conv_std_logic_vector(39964772,28); exponent <= conv_std_logic_vector(41,11); WHEN "1010101001" => manhi <= conv_std_logic_vector(7358681,24); manlo <= conv_std_logic_vector(204327682,28); exponent <= conv_std_logic_vector(40,11); WHEN "1010101010" => manhi <= conv_std_logic_vector(980985,24); manlo <= conv_std_logic_vector(43247066,28); exponent <= conv_std_logic_vector(39,11); WHEN "1010101011" => manhi <= conv_std_logic_vector(9354292,24); manlo <= conv_std_logic_vector(128160132,28); exponent <= conv_std_logic_vector(37,11); WHEN "1010101100" => manhi <= conv_std_logic_vector(2449273,24); manlo <= conv_std_logic_vector(126511008,28); exponent <= conv_std_logic_vector(36,11); WHEN "1010101101" => manhi <= conv_std_logic_vector(11514904,24); manlo <= conv_std_logic_vector(217311246,28); exponent <= conv_std_logic_vector(34,11); WHEN "1010101110" => manhi <= conv_std_logic_vector(4038963,24); manlo <= conv_std_logic_vector(49913566,28); exponent <= conv_std_logic_vector(33,11); WHEN "1010101111" => manhi <= conv_std_logic_vector(13854161,24); manlo <= conv_std_logic_vector(124821568,28); exponent <= conv_std_logic_vector(31,11); WHEN "1010110000" => manhi <= conv_std_logic_vector(5760092,24); manlo <= conv_std_logic_vector(12957085,28); exponent <= conv_std_logic_vector(30,11); WHEN "1010110001" => manhi <= conv_std_logic_vector(16386833,24); manlo <= conv_std_logic_vector(43278038,28); exponent <= conv_std_logic_vector(28,11); WHEN "1010110010" => manhi <= conv_std_logic_vector(7623527,24); manlo <= conv_std_logic_vector(199937734,28); exponent <= conv_std_logic_vector(27,11); WHEN "1010110011" => manhi <= conv_std_logic_vector(1175847,24); manlo <= conv_std_logic_vector(253947561,28); exponent <= conv_std_logic_vector(26,11); WHEN "1010110100" => manhi <= conv_std_logic_vector(9641036,24); manlo <= conv_std_logic_vector(141497796,28); exponent <= conv_std_logic_vector(24,11); WHEN "1010110101" => manhi <= conv_std_logic_vector(2660247,24); manlo <= conv_std_logic_vector(255766959,28); exponent <= conv_std_logic_vector(23,11); WHEN "1010110110" => manhi <= conv_std_logic_vector(11825357,24); manlo <= conv_std_logic_vector(136095046,28); exponent <= conv_std_logic_vector(21,11); WHEN "1010110111" => manhi <= conv_std_logic_vector(4267381,24); manlo <= conv_std_logic_vector(138414926,28); exponent <= conv_std_logic_vector(20,11); WHEN "1010111000" => manhi <= conv_std_logic_vector(14190283,24); manlo <= conv_std_logic_vector(25479908,28); exponent <= conv_std_logic_vector(18,11); WHEN "1010111001" => manhi <= conv_std_logic_vector(6007396,24); manlo <= conv_std_logic_vector(140400514,28); exponent <= conv_std_logic_vector(17,11); WHEN "1010111010" => manhi <= conv_std_logic_vector(16750746,24); manlo <= conv_std_logic_vector(23924155,28); exponent <= conv_std_logic_vector(15,11); WHEN "1010111011" => manhi <= conv_std_logic_vector(7891279,24); manlo <= conv_std_logic_vector(245330892,28); exponent <= conv_std_logic_vector(14,11); WHEN "1010111100" => manhi <= conv_std_logic_vector(1372848,24); manlo <= conv_std_logic_vector(263794815,28); exponent <= conv_std_logic_vector(13,11); WHEN "1010111101" => manhi <= conv_std_logic_vector(9930927,24); manlo <= conv_std_logic_vector(14029030,28); exponent <= conv_std_logic_vector(11,11); WHEN "1010111110" => manhi <= conv_std_logic_vector(2873537,24); manlo <= conv_std_logic_vector(129274844,28); exponent <= conv_std_logic_vector(10,11); WHEN "1010111111" => manhi <= conv_std_logic_vector(12139216,24); manlo <= conv_std_logic_vector(224845565,28); exponent <= conv_std_logic_vector(8,11); WHEN "1011000000" => manhi <= conv_std_logic_vector(4498306,24); manlo <= conv_std_logic_vector(82126943,28); exponent <= conv_std_logic_vector(7,11); WHEN "1011000001" => manhi <= conv_std_logic_vector(14530093,24); manlo <= conv_std_logic_vector(7024665,28); exponent <= conv_std_logic_vector(5,11); WHEN "1011000010" => manhi <= conv_std_logic_vector(6257414,24); manlo <= conv_std_logic_vector(187437029,28); exponent <= conv_std_logic_vector(4,11); WHEN "1011000011" => manhi <= conv_std_logic_vector(170718,24); manlo <= conv_std_logic_vector(36971864,28); exponent <= conv_std_logic_vector(3,11); WHEN "1011000100" => manhi <= conv_std_logic_vector(8161970,24); manlo <= conv_std_logic_vector(42518955,28); exponent <= conv_std_logic_vector(1,11); WHEN "1011000101" => manhi <= conv_std_logic_vector(1572011,24); manlo <= conv_std_logic_vector(197150320,28); exponent <= conv_std_logic_vector(0,11); WHEN others => manhi <= conv_std_logic_vector(0,24); manlo <= conv_std_logic_vector(0,28); exponent <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/dp_log.vhd

10

10521

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** DOUBLE PRECISION LOG(LN) - TOP LEVEL *** --*** *** --*** DP_LOG.VHD *** --*** *** --*** Function: IEEE754 DP LN() *** --*** *** --*** 11/08/09 ML *** --*** *** --*** (c) 2009 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** Notes: *** --*** Latency = 27 + 7*DoubleSpeed + *** --*** RoundConvert*(1+DoubleSpeed) *** --*** DoubleSpeed = 0, RoundConvert = 0 : 27 *** --*** DoubleSpeed = 1, RoundConvert = 0 : 34 *** --*** DoubleSpeed = 0, RoundConvert = 1 : 28 *** --*** DoubleSpeed = 1, RoundConvert = 1 : 36 *** --*** *** --*************************************************** ENTITY dp_log IS GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); END dp_log; ARCHITECTURE rtl OF dp_log IS constant expwidth : positive := 11; constant manwidth : positive := 52; constant coredepth : positive := 26 + 7*doublespeed; signal signinff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal signnode : STD_LOGIC; signal mantissanode : STD_LOGIC_VECTOR (53 DOWNTO 1); signal exponentnode : STD_LOGIC_VECTOR (11 DOWNTO 1); signal zeronode : STD_LOGIC; -- conditions signal zeroman : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal zeroexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal maxexp : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zeromaninff : STD_LOGIC; signal zeroexpinff : STD_LOGIC; signal maxexpinff : STD_LOGIC; signal naninff : STD_LOGIC; signal nanff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1); signal infinityinff : STD_LOGIC; signal infinityff : STD_LOGIC_VECTOR (coredepth-3 DOWNTO 1); component dp_ln_core GENERIC ( doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aaman : IN STD_LOGIC_VECTOR (52 DOWNTO 1); aaexp : IN STD_LOGIC_VECTOR (11 DOWNTO 1); ccman : OUT STD_LOGIC_VECTOR (53 DOWNTO 1); ccexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); ccsgn : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_lnnornd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signln : IN STD_LOGIC; exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; infinityin : IN STD_LOGIC; zeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_lnrnd PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signln : IN STD_LOGIC; exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; infinityin : IN STD_LOGIC; zeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_lnrndpipe PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signln : IN STD_LOGIC; exponentln : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaln : IN STD_LOGIC_VECTOR (53 DOWNTO 1); nanin : IN STD_LOGIC; infinityin : IN STD_LOGIC; zeroin : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; BEGIN pma: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO manwidth LOOP maninff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP expinff(k) <= '0'; END LOOP; signinff <= "00"; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN maninff <= mantissain; expinff <= exponentin; signinff(1) <= signin; signinff(2) <= signinff(1); END IF; END IF; END PROCESS; --******************** --*** CHECK INPUTS *** --******************** zeroman(1) <= maninff(1); gca: FOR k IN 2 TO manwidth GENERATE zeroman(k) <= zeroman(k-1) OR maninff(k); END GENERATE; zeroexp(1) <= expinff(1); gcb: FOR k IN 2 TO expwidth GENERATE zeroexp(k) <= zeroexp(k-1) OR expinff(k); END GENERATE; maxexp(1) <= expinff(1); gcc: FOR k IN 2 TO expwidth GENERATE maxexp(k) <= maxexp(k-1) AND expinff(k); END GENERATE; pcc: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN zeromaninff <= '0'; zeroexpinff <= '0'; maxexpinff <= '0'; naninff <= '0'; FOR k IN 1 TO coredepth-3 LOOP nanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN zeromaninff <= NOT(zeroman(manwidth)); zeroexpinff <= NOT(zeroexp(expwidth)); maxexpinff <= maxexp(expwidth); -- infinity when exp = zero -- nan when man != 0, exp = max -- all ffs '1' when condition true naninff <= (zeromaninff AND maxexpinff) OR signinff(2); infinityinff <= zeroexpinff OR maxexpinff; -- nan output when nan input nanff(1) <= naninff; FOR k IN 2 TO coredepth-3 LOOP nanff(k) <= nanff(k-1); END LOOP; infinityff(1) <= infinityinff; FOR k IN 2 TO coredepth-3 LOOP infinityff(k) <= infinityff(k-1); END LOOP; END IF; END IF; END PROCESS; --*************** --*** LN CORE *** --*************** lncore: dp_ln_core GENERIC MAP (doublespeed=>doublespeed,device=>device,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aaman=>mantissain,aaexp=>exponentin, ccman=>mantissanode,ccexp=>exponentnode,ccsgn=>signnode, zeroout=>zeronode); --************************ --*** ROUND AND OUTPUT *** --************************ gra: IF (roundconvert = 0) GENERATE norndout: dp_lnnornd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signln=>signnode, exponentln=>exponentnode, mantissaln=>mantissanode, nanin=>nanff(coredepth-3), infinityin=>infinityff(coredepth-3), zeroin=>zeronode, signout=>signout, exponentout=>exponentout, mantissaout=>mantissaout, nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout); END GENERATE; grb: IF (roundconvert = 1 AND doublespeed = 0) GENERATE rndout: dp_lnrnd PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signln=>signnode, exponentln=>exponentnode, mantissaln=>mantissanode, nanin=>nanff(coredepth-3), infinityin=>infinityff(coredepth-3), zeroin=>zeronode, signout=>signout, exponentout=>exponentout, mantissaout=>mantissaout, nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout); END GENERATE; grc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE rndoutpipe: dp_lnrndpipe PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signln=>signnode, exponentln=>exponentnode, mantissaln=>mantissanode, nanin=>nanff(coredepth-3), infinityin=>infinityff(coredepth-3), zeroin=>zeronode, signout=>signout, exponentout=>exponentout, mantissaout=>mantissaout, nanout=>nanout,overflowout=>overflowout,zeroout=>zeroout); END GENERATE; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_scmul3236.vhd

10

4216

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_SCMUL3236.VHD *** --*** *** --*** Function: Scale (normalized for overflow *** --*** only) a 32 or 36 bit mantissa *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_scmul3236 IS GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); END hcc_scmul3236; ARCHITECTURE rtl OF hcc_scmul3236 IS signal scale : STD_LOGIC_VECTOR (5 DOWNTO 1); BEGIN -- for single 32 bit mantissa input -- [S ][O....O][1 ][M...M][RGS] -- [32][31..28][27][26..4][321] - NB underflow can run into RGS -- '1' may end up in overflow, i.e. [S1M..] or [SS1M..] or [SSS1M..]..... -- output -- [S ][1 ][M...M] -- [32][31][30..1], count is shift -- for single 36 bit mantissa -- [S ][O....O][1 ][M...M][O..O][RGS] -- [36][35..32][31][30..8][7..4][321] -- shift 0 if "01XX" or "10XX" scale(5) <= (NOT(frac(mantissa)) AND frac(mantissa-1)) OR (frac(mantissa) AND NOT(frac(mantissa-1))); -- shift 1 if "001XX" or "110XX" scale(4) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND frac(mantissa-2)) OR (frac(mantissa) AND frac(mantissa-1) AND NOT(frac(mantissa-2))); -- shift 2 if "0001XX" or "1110XX" scale(3) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND frac(mantissa-3)) OR (frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND NOT(frac(mantissa-3))); -- shift 3 if "00001XX" or "11110XX" scale(2) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND NOT(frac(mantissa-3)) AND frac(mantissa-4)) OR (frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND frac(mantissa-3) AND NOT(frac(mantissa-4))); -- shift 4 if "00000XX" or "11111XX" scale(1) <= (NOT(frac(mantissa)) AND NOT(frac(mantissa-1)) AND NOT(frac(mantissa-2)) AND NOT(frac(mantissa-3)) AND NOT(frac(mantissa-4))) OR (frac(mantissa) AND frac(mantissa-1) AND frac(mantissa-2) AND frac(mantissa-3) AND frac(mantissa-4)); scaled(mantissa) <= frac(mantissa); gsa: FOR k IN 1 TO mantissa-5 GENERATE scaled(mantissa-k) <= (frac(mantissa-k-4) AND scale(1)) OR (frac(mantissa-k-3) AND scale(2)) OR (frac(mantissa-k-2) AND scale(3)) OR (frac(mantissa-k-1) AND scale(4)) OR (frac(mantissa-k) AND scale(5)); END GENERATE; scaled(4) <= (frac(1) AND scale(2)) OR (frac(2) AND scale(3)) OR (frac(3) AND scale(4)) OR (frac(4) AND scale(5)); scaled(3) <= (frac(1) AND scale(3)) OR (frac(2) AND scale(4)) OR (frac(3) AND scale(5)); scaled(2) <= (frac(1) AND scale(4)) OR (frac(2) AND scale(5)); scaled(1) <= (frac(1) AND scale(5)); -- shifts everything to SSSSS1XXXXX -- if '1' is in a position greater than 27,add to exponent count(3) <= scale(5); count(2) <= scale(4) OR scale(3); count(1) <= scale(4) OR scale(2); END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_sqr.vhd

10

9456

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** SINGLE PRECISION SQUARE ROOT - TOP LEVEL *** --*** *** --*** FP_SQR.VHD *** --*** *** --*** Function: IEEE754 FP Square Root *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** Notes: *** --*** Latency = 28 *** --*** Based on FPROOT1.VHD (12/06) *** --*************************************************** ENTITY fp_sqr IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); END fp_sqr; ARCHITECTURE rtl OF fp_sqr IS constant manwidth : positive := 23; constant expwidth : positive := 8; type expfftype IS ARRAY (manwidth+4 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal signinff : STD_LOGIC; signal maninff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expinff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal signff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1); signal expnode, expdiv : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal expff : expfftype; signal radicand : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1); signal squareroot : STD_LOGIC_VECTOR (manwidth+2 DOWNTO 1); signal roundff, manff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal roundbit : STD_LOGIC; signal preadjust : STD_LOGIC; signal zerovec : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal offset : STD_LOGIC_VECTOR (expwidth DOWNTO 1); -- conditions signal nanmanff, nanexpff : STD_LOGIC_VECTOR (manwidth+4 DOWNTO 1); signal zeroexpff, zeromanff : STD_LOGIC_VECTOR (manwidth+3 DOWNTO 1); signal expinzero, expinmax : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal maninzero : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal expzero, expmax, manzero : STD_LOGIC; signal infinitycondition, nancondition : STD_LOGIC; component fp_sqrroot IS GENERIC (width : positive := 52); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; rad : IN STD_LOGIC_VECTOR (width+1 DOWNTO 1); root : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gzva: FOR k IN 1 TO manwidth GENERATE zerovec(k) <= '0'; END GENERATE; gxoa: FOR k IN 1 TO expwidth-1 GENERATE offset(k) <= '1'; END GENERATE; offset(expwidth) <= '0'; pma: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN signinff <= '0'; FOR k IN 1 TO manwidth LOOP maninff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP expinff(k) <= '0'; END LOOP; FOR k IN 1 TO manwidth+4 LOOP signff(k) <= '0'; END LOOP; FOR k IN 1 TO manwidth+4 LOOP FOR j IN 1 TO expwidth LOOP expff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO manwidth LOOP roundff(k) <= '0'; manff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN signinff <= signin; maninff <= mantissain; expinff <= exponentin; signff(1) <= signinff; FOR k IN 2 TO manwidth+4 LOOP signff(k) <= signff(k-1); END LOOP; expff(1)(expwidth DOWNTO 1) <= expdiv; expff(2)(expwidth DOWNTO 1) <= expff(1)(expwidth DOWNTO 1) + offset; FOR k IN 3 TO manwidth+3 LOOP expff(k)(expwidth DOWNTO 1) <= expff(k-1)(expwidth DOWNTO 1); END LOOP; FOR k IN 1 TO expwidth LOOP expff(manwidth+4)(k) <= (expff(manwidth+3)(k) AND zeroexpff(manwidth+3)) OR nanexpff(manwidth+3); END LOOP; roundff <= squareroot(manwidth+1 DOWNTO 2) + (zerovec(manwidth-1 DOWNTO 1) & roundbit); FOR k IN 1 TO manwidth LOOP manff(k) <= (roundff(k) AND zeromanff(manwidth+3)) OR nanmanff(manwidth+3); END LOOP; END IF; END PROCESS; --******************* --*** CONDITIONS *** --******************* pcc: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO manwidth+4 LOOP nanmanff(k) <= '0'; nanexpff(k) <= '0'; END LOOP; FOR k IN 1 TO manwidth+3 LOOP zeroexpff(k) <= '0'; zeromanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN nanmanff(1) <= nancondition; -- level 1 nanexpff(1) <= nancondition OR infinitycondition; -- also max exp when infinity FOR k IN 2 TO manwidth+4 LOOP nanmanff(k) <= nanmanff(k-1); nanexpff(k) <= nanexpff(k-1); END LOOP; zeromanff(1) <= expzero AND NOT(infinitycondition); -- level 1 zeroexpff(1) <= expzero; -- level 1 FOR k IN 2 TO manwidth+3 LOOP zeromanff(k) <= zeromanff(k-1); zeroexpff(k) <= zeroexpff(k-1); END LOOP; END IF; END PROCESS; --******************* --*** SQUARE ROOT *** --******************* -- if exponent is odd, double mantissa and adjust exponent -- core latency manwidth+2 = 25 -- top latency = core + 1 (input) + 2 (output) = 28 sqr: fp_sqrroot GENERIC MAP (width=>manwidth+2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, rad=>radicand, root=>squareroot); radicand(1) <= '0'; radicand(2) <= maninff(1) AND NOT(preadjust); gra: FOR k IN 3 TO manwidth+1 GENERATE radicand(k) <= (maninff(k-1) AND NOT(preadjust)) OR (maninff(k-2) AND preadjust); END GENERATE; radicand(manwidth+2) <= NOT(preadjust) OR (maninff(manwidth) AND preadjust); radicand(manwidth+3) <= preadjust; --**************** --*** EXPONENT *** --**************** -- subtract 1023, divide result/2, if odd - preadjust -- if zero input, zero exponent and mantissa expnode <= expinff - offset; preadjust <= expnode(1); expdiv <= expnode(expwidth) & expnode(expwidth DOWNTO 2); --************* --*** ROUND *** --************* -- only need to round up, round to nearest not possible out of root roundbit <= squareroot(1); --********************* --*** SPECIAL CASES *** --********************* -- 1. if negative input, invalid operation, NAN (unless -0) -- 2. -0 in -0 out -- 3. infinity in, invalid operation, infinity out -- 4. NAN in, invalid operation, NAN -- '0' if 0 expinzero(1) <= expinff(1); gxza: FOR k IN 2 TO expwidth GENERATE expinzero(k) <= expinzero(k-1) OR expinff(k); END GENERATE; expzero <= expinzero(expwidth); -- '0' when zero -- '1' if nan or infinity expinmax(1) <= expinff(1); gxia: FOR k IN 2 TO expwidth GENERATE expinmax(k) <= expinmax(k-1) AND expinff(k); END GENERATE; expmax <= expinmax(expwidth); -- '1' when true -- '1' if not zero or infinity maninzero(1) <= maninff(1); gmza: FOR k IN 2 TO manwidth GENERATE maninzero(k) <= maninzero(k-1) OR maninff(k); END GENERATE; manzero <= maninzero(manwidth); infinitycondition <= NOT(manzero) AND expmax; nancondition <= (signinff AND expzero) OR (expmax AND manzero); --*************** --*** OUTPUTS *** --*************** signout <= signff(manwidth+4); exponentout <= expff(manwidth+4)(expwidth DOWNTO 1); mantissaout <= manff; ----------------------------------------------- nanout <= nanmanff(manwidth+4); invalidout <= nanmanff(manwidth+4); END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_arcsinpi_s5.vhd

10

575341

----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_arcsinpi_s5 -- VHDL created on Thu Feb 28 17:21:04 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; entity fp_arcsinpi_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_arcsinpi_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstBiasM2_uid6_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal ooPi_uid9_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cstBias_uid22_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(10 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(10 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (10 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n : std_logic_vector (0 downto 0); signal shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (12 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a : std_logic_vector (23 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (25 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 : std_logic_vector (49 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr : UNSIGNED (49 downto 0); signal mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (49 downto 0); signal z2_uid93_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (1 downto 0); signal piO2_uid101_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (27 downto 0); signal fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (9 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(11 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(11 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (11 downto 0); signal expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (10 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector (23 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 : std_logic_vector (47 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr : UNSIGNED (47 downto 0); signal prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (47 downto 0); signal roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (11 downto 0); signal leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (15 downto 0); signal maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a : std_logic_vector (11 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 : std_logic_vector (23 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr : SIGNED (24 downto 0); signal prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q : std_logic_vector (23 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a : std_logic_vector (17 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b : std_logic_vector (20 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 : std_logic_vector (38 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr : SIGNED (39 downto 0); signal prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q : std_logic_vector (38 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid438_pT1_uid404_arcsinXPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_a : std_logic_vector (16 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_b : std_logic_vector (24 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 : std_logic_vector (41 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr : SIGNED (42 downto 0); signal prodXY_uid441_pT2_uid410_arcsinXPolyEval_q : std_logic_vector (41 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a : std_logic_vector (11 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 : std_logic_vector (23 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr : SIGNED (24 downto 0); signal prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q : std_logic_vector (23 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a : std_logic_vector (15 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b : std_logic_vector (22 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 : std_logic_vector (38 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr : SIGNED (39 downto 0); signal prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q : std_logic_vector (38 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid253_arcsinXO2XTabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (18 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (18 downto 0); signal memoryC1_uid254_arcsinXO2XTabGen_lutmem_q : std_logic_vector (18 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid255_arcsinXO2XTabGen_lutmem_q : std_logic_vector (11 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid400_arcsinXTabGen_lutmem_ia : std_logic_vector (29 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_iq : std_logic_vector (29 downto 0); signal memoryC0_uid400_arcsinXTabGen_lutmem_q : std_logic_vector (29 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid401_arcsinXTabGen_lutmem_ia : std_logic_vector (22 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_iq : std_logic_vector (22 downto 0); signal memoryC1_uid401_arcsinXTabGen_lutmem_q : std_logic_vector (22 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid402_arcsinXTabGen_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid402_arcsinXTabGen_lutmem_q : std_logic_vector (12 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC0_uid422_sqrtTableGenerator_lutmem_ia : std_logic_vector (28 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_iq : std_logic_vector (28 downto 0); signal memoryC0_uid422_sqrtTableGenerator_lutmem_q : std_logic_vector (28 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC1_uid423_sqrtTableGenerator_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid423_sqrtTableGenerator_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_reset0 : std_logic; signal memoryC2_uid424_sqrtTableGenerator_lutmem_ia : std_logic_vector (11 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_aa : std_logic_vector (7 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_ab : std_logic_vector (7 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_iq : std_logic_vector (11 downto 0); signal memoryC2_uid424_sqrtTableGenerator_lutmem_q : std_logic_vector (11 downto 0); signal reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (2 downto 0); signal reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q : std_logic_vector (36 downto 0); signal reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q : std_logic_vector (36 downto 0); signal reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q : std_logic_vector (11 downto 0); signal reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q : std_logic_vector (17 downto 0); signal reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q : std_logic_vector (20 downto 0); signal reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (23 downto 0); signal reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (25 downto 0); signal reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (31 downto 0); signal reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (15 downto 0); signal reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0); signal reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (3 downto 0); signal reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (34 downto 0); signal reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (34 downto 0); signal reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (0 downto 0); signal reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (5 downto 0); signal reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (22 downto 0); signal reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (22 downto 0); signal reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (3 downto 0); signal reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q : std_logic_vector (11 downto 0); signal reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q : std_logic_vector (11 downto 0); signal reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q : std_logic_vector (15 downto 0); signal reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q : std_logic_vector (22 downto 0); signal reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (7 downto 0); signal reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (7 downto 0); signal reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (1 downto 0); signal reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q : std_logic_vector (25 downto 0); signal reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q : std_logic_vector (25 downto 0); signal reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q : std_logic_vector (25 downto 0); signal reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q : std_logic_vector (25 downto 0); signal reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q : std_logic_vector (16 downto 0); signal reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q : std_logic_vector (24 downto 0); signal reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q : std_logic_vector (7 downto 0); signal reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (27 downto 0); signal reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q : std_logic_vector (31 downto 0); signal reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q : std_logic_vector (34 downto 0); signal reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (25 downto 0); signal reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (11 downto 0); signal reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q : std_logic_vector (0 downto 0); signal reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q : std_logic_vector (2 downto 0); signal reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q : std_logic_vector (22 downto 0); signal reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q : std_logic_vector (7 downto 0); signal ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0); signal ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0); signal ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (25 downto 0); signal ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (8 downto 0); signal ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q : std_logic_vector (0 downto 0); signal ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q : std_logic_vector (5 downto 0); signal ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q : std_logic_vector (0 downto 0); signal ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (22 downto 0); signal ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q : std_logic_vector (0 downto 0); signal ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q : std_logic_vector (1 downto 0); signal ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q : std_logic_vector (0 downto 0); signal ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q : std_logic_vector (7 downto 0); signal ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q : std_logic_vector (11 downto 0); signal ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q : std_logic_vector (7 downto 0); signal ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q : std_logic_vector (0 downto 0); signal ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q : std_logic_vector (22 downto 0); signal ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q : std_logic_vector (4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : signal is true; signal ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (25 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 : std_logic; signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq : std_logic; signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : signal is true; signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 : std_logic; signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q : std_logic_vector (22 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i : unsigned(4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq : std_logic; signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q : std_logic_vector (5 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q : std_logic_vector (0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : signal is true; signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 : std_logic; signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q : std_logic_vector (22 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : signal is true; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 : std_logic; signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q : signal is true; signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 : std_logic; signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q : signal is true; signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 : std_logic; signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q : std_logic_vector (0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q : signal is true; signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 : std_logic; signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : signal is true; signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 : std_logic; signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia : std_logic_vector (0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq : std_logic_vector (0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q : std_logic_vector (0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q : signal is true; signal ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q : std_logic_vector (22 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 : std_logic; signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i : unsigned(2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq : std_logic; signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q : std_logic_vector (3 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q : signal is true; signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q : std_logic_vector (17 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q : signal is true; signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0 : std_logic; signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia : std_logic_vector (16 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa : std_logic_vector (1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab : std_logic_vector (1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq : std_logic_vector (16 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q : std_logic_vector (16 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q : std_logic_vector(1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i : unsigned(1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq : std_logic; signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q : std_logic_vector (1 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q : signal is true; signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q : std_logic_vector (7 downto 0); signal ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q : std_logic_vector (11 downto 0); signal ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0 : std_logic; signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia : std_logic_vector (23 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq : std_logic_vector (23 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q : std_logic_vector (23 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq : std_logic; signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q : signal is true; signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 : std_logic; signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q : std_logic_vector (15 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q : signal is true; signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q : signal is true; signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0 : std_logic; signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q : signal is true; signal pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (35 downto 0); signal excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(14 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(14 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (14 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n : std_logic_vector (0 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(14 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(14 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (14 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n : std_logic_vector (0 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c : std_logic_vector (0 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (32 downto 0); signal expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (32 downto 0); signal InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q : std_logic_vector (1 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal expX_uid15_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expX_uid15_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid16_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid16_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal singX_uid17_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal singX_uid17_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid36_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(10 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(10 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (10 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin : std_logic_vector (0 downto 0); signal expGT0_uid44_asinX_uid8_fpArcsinPiTest_c : std_logic_vector (0 downto 0); signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expL_uid82_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal srVal_uid89_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(28 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(28 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (28 downto 0); signal path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (28 downto 0); signal fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal signR_uid125_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid125_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid125_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(36 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o : std_logic_vector (36 downto 0); signal expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (35 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d : std_logic_vector(0 downto 0); signal excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d : std_logic_vector(0 downto 0); signal excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(31 downto 0); signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(31 downto 0); signal vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(15 downto 0); signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(15 downto 0); signal vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(3 downto 0); signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(3 downto 0); signal vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (8 downto 0); signal expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (8 downto 0); signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(1 downto 0); signal expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal fracOOPi_uid10_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracOOPi_uid10_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (49 downto 0); signal normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (48 downto 0); signal fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (47 downto 0); signal fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (47 downto 0); signal normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (46 downto 0); signal fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (45 downto 0); signal fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (21 downto 0); signal stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (21 downto 0); signal Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a : std_logic_vector(2 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b : std_logic_vector(2 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b : std_logic_vector (21 downto 0); signal prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in : std_logic_vector (41 downto 0); signal prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b : std_logic_vector (12 downto 0); signal prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in : std_logic_vector (38 downto 0); signal prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b : std_logic_vector (23 downto 0); signal mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (17 downto 0); signal mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (16 downto 0); signal concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal R_uid227_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (15 downto 0); signal FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (15 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a : std_logic_vector(4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b : std_logic_vector(4 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a : std_logic_vector(5 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b : std_logic_vector(5 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a : std_logic_vector(5 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b : std_logic_vector(5 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b : std_logic_vector(0 downto 0); signal ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b : std_logic_vector(0 downto 0); signal ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal R_uid126_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b : std_logic_vector(0 downto 0); signal ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b : std_logic_vector(3 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b : std_logic_vector(0 downto 0); signal ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a : std_logic_vector(4 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b : std_logic_vector(4 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q : std_logic_vector(0 downto 0); signal fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (23 downto 0); signal fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (3 downto 0); signal fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (3 downto 0); signal expLRange_uid84_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (7 downto 0); signal expLRange_uid84_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal srValRange_uid92_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (4 downto 0); signal srValRange_uid92_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (4 downto 0); signal normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (27 downto 0); signal normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (23 downto 0); signal fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (35 downto 0); signal expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (11 downto 0); signal InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (36 downto 0); signal arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal y_uid59_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (35 downto 0); signal y_uid59_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0); signal rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (15 downto 0); signal vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (18 downto 0); signal vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (18 downto 0); signal rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (26 downto 0); signal rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (32 downto 0); signal vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (32 downto 0); signal InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (8 downto 0); signal expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (8 downto 0); signal expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (24 downto 0); signal fpOOPi_uid11_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (24 downto 0); signal X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (17 downto 0); signal X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (9 downto 0); signal X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (0 downto 0); signal stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal lowRangeB_uid258_arcsinXO2XPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid258_arcsinXO2XPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid259_arcsinXO2XPolyEval_in : std_logic_vector (12 downto 0); signal highBBits_uid259_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal lowRangeB_uid264_arcsinXO2XPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid264_arcsinXO2XPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid265_arcsinXO2XPolyEval_in : std_logic_vector (21 downto 0); signal highBBits_uid265_arcsinXO2XPolyEval_b : std_logic_vector (19 downto 0); signal lowRangeB_uid405_arcsinXPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid405_arcsinXPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid406_arcsinXPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid406_arcsinXPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid411_arcsinXPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid411_arcsinXPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid412_arcsinXPolyEval_in : std_logic_vector (25 downto 0); signal highBBits_uid412_arcsinXPolyEval_b : std_logic_vector (23 downto 0); signal lowRangeB_uid427_sqrtPolynomialEvaluator_in : std_logic_vector (0 downto 0); signal lowRangeB_uid427_sqrtPolynomialEvaluator_b : std_logic_vector (0 downto 0); signal highBBits_uid428_sqrtPolynomialEvaluator_in : std_logic_vector (12 downto 0); signal highBBits_uid428_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal lowRangeB_uid433_sqrtPolynomialEvaluator_in : std_logic_vector (1 downto 0); signal lowRangeB_uid433_sqrtPolynomialEvaluator_b : std_logic_vector (1 downto 0); signal highBBits_uid434_sqrtPolynomialEvaluator_in : std_logic_vector (23 downto 0); signal highBBits_uid434_sqrtPolynomialEvaluator_b : std_logic_vector (21 downto 0); signal yT1_uid403_arcsinXPolyEval_in : std_logic_vector (16 downto 0); signal yT1_uid403_arcsinXPolyEval_b : std_logic_vector (12 downto 0); signal yT1_uid425_sqrtPolynomialEvaluator_in : std_logic_vector (15 downto 0); signal yT1_uid425_sqrtPolynomialEvaluator_b : std_logic_vector (11 downto 0); signal expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid38_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal fpL_uid85_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (4 downto 0); signal rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (2 downto 0); signal rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (0 downto 0); signal rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (7 downto 0); signal expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal Y34_uid60_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal Y34_uid60_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal yAddr_uid63_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal yAddr_uid63_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (26 downto 0); signal yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (17 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(36 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(36 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (36 downto 0); signal oMy_uid78_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(1 downto 0); signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(1 downto 0); signal vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(32 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o : std_logic_vector (32 downto 0); signal expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (32 downto 0); signal rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in : std_logic_vector (1 downto 0); signal FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector (1 downto 0); signal expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_a : std_logic_vector(19 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_b : std_logic_vector(19 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_o : std_logic_vector (19 downto 0); signal sumAHighB_uid260_arcsinXO2XPolyEval_q : std_logic_vector (19 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid266_arcsinXO2XPolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_a : std_logic_vector(23 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_b : std_logic_vector(23 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_o : std_logic_vector (23 downto 0); signal sumAHighB_uid407_arcsinXPolyEval_q : std_logic_vector (23 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_a : std_logic_vector(30 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_b : std_logic_vector(30 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_o : std_logic_vector (30 downto 0); signal sumAHighB_uid413_arcsinXPolyEval_q : std_logic_vector (30 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_a : std_logic_vector(21 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_b : std_logic_vector(21 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_o : std_logic_vector (21 downto 0); signal sumAHighB_uid429_sqrtPolynomialEvaluator_q : std_logic_vector (21 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_a : std_logic_vector(29 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_b : std_logic_vector(29 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_o : std_logic_vector (29 downto 0); signal sumAHighB_uid435_sqrtPolynomialEvaluator_q : std_logic_vector (29 downto 0); signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (32 downto 0); signal X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (32 downto 0); signal X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (28 downto 0); signal X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (28 downto 0); signal X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (24 downto 0); signal X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (24 downto 0); signal InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal path2_uid61_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal path2_uid61_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal yT1_uid256_arcsinXO2XPolyEval_in : std_logic_vector (17 downto 0); signal yT1_uid256_arcsinXO2XPolyEval_b : std_logic_vector (11 downto 0); signal l_uid80_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal l_uid80_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0); signal vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (23 downto 0); signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (23 downto 0); signal fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (31 downto 0); signal expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal s1_uid258_uid261_arcsinXO2XPolyEval_q : std_logic_vector (20 downto 0); signal s2_uid264_uid267_arcsinXO2XPolyEval_q : std_logic_vector (32 downto 0); signal s1_uid405_uid408_arcsinXPolyEval_q : std_logic_vector (24 downto 0); signal s2_uid411_uid414_arcsinXPolyEval_q : std_logic_vector (32 downto 0); signal s1_uid427_uid430_sqrtPolynomialEvaluator_q : std_logic_vector (22 downto 0); signal s2_uid433_uid436_sqrtPolynomialEvaluator_q : std_logic_vector (31 downto 0); signal InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid42_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (0 downto 0); signal expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (6 downto 0); signal RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (23 downto 0); signal RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (21 downto 0); signal RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (19 downto 0); signal pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (31 downto 0); signal vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (2 downto 0); signal vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (2 downto 0); signal rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (3 downto 0); signal vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (30 downto 0); signal rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (0 downto 0); signal vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0); signal vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (33 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal mAddr_uid97_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (25 downto 0); signal mAddr_uid97_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (25 downto 0); signal fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (27 downto 0); signal fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (28 downto 0); signal fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (7 downto 0); signal rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(2 downto 0); signal roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (22 downto 0); signal InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (35 downto 0); signal LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (35 downto 0); signal LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (34 downto 0); signal LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (34 downto 0); signal LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0); signal LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (33 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s : std_logic_vector (0 downto 0); signal vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (34 downto 0); signal vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (5 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (31 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (36 downto 0); signal fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (33 downto 0); signal fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (2 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c : std_logic_vector(0 downto 0); signal exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector (25 downto 0); signal SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (30 downto 0); signal SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (7 downto 0); signal SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in : std_logic_vector (22 downto 0); signal SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b : std_logic_vector (22 downto 0); signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q : std_logic_vector (3 downto 0); signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b : std_logic_vector(0 downto 0); signal excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q : std_logic_vector(0 downto 0); begin --xIn(GPIN,3)@0 --cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest(CONSTANT,18) cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000000"; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable(LOGICAL,1059) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q <= not ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_a; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor(LOGICAL,1162) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q <= not (ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_a or ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_b); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top(CONSTANT,1082) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q <= "011110"; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp(LOGICAL,1083) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_mem_top_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b <= STD_LOGIC_VECTOR("0" & ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q); ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q <= "1" when ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_a = ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_b else "0"; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg(REG,1084) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmp_q; END IF; END IF; END PROCESS; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena(REG,1163) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_nor_q = "1") THEN ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd(LOGICAL,1164) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b <= en; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_a and ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_b; --fracX_uid16_asinX_uid8_fpArcsinPiTest(BITSELECT,15)@0 fracX_uid16_asinX_uid8_fpArcsinPiTest_in <= a(22 downto 0); fracX_uid16_asinX_uid8_fpArcsinPiTest_b <= fracX_uid16_asinX_uid8_fpArcsinPiTest_in(22 downto 0); --fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest(LOGICAL,34)@0 fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a <= fracX_uid16_asinX_uid8_fpArcsinPiTest_b; fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q <= "1" when fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_a = fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_b else "0"; --InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest(LOGICAL,36)@0 InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a <= fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q; InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q <= not InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_a; --cstBias_uid22_asinX_uid8_fpArcsinPiTest(CONSTANT,21) cstBias_uid22_asinX_uid8_fpArcsinPiTest_q <= "01111111"; --expX_uid15_asinX_uid8_fpArcsinPiTest(BITSELECT,14)@0 expX_uid15_asinX_uid8_fpArcsinPiTest_in <= a(30 downto 0); expX_uid15_asinX_uid8_fpArcsinPiTest_b <= expX_uid15_asinX_uid8_fpArcsinPiTest_in(30 downto 23); --expEQ0_uid45_asinX_uid8_fpArcsinPiTest(LOGICAL,44)@0 expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q; expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q <= "1" when expEQ0_uid45_asinX_uid8_fpArcsinPiTest_a = expEQ0_uid45_asinX_uid8_fpArcsinPiTest_b else "0"; --exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest(LOGICAL,46)@0 exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a <= expEQ0_uid45_asinX_uid8_fpArcsinPiTest_q; exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q; exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q <= exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_a and exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_b; --GND(CONSTANT,0) GND_q <= "0"; --expGT0_uid44_asinX_uid8_fpArcsinPiTest(COMPARE,43)@0 expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin <= GND_q; expGT0_uid44_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & cstBias_uid22_asinX_uid8_fpArcsinPiTest_q) & '0'; expGT0_uid44_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_asinX_uid8_fpArcsinPiTest_b) & expGT0_uid44_asinX_uid8_fpArcsinPiTest_cin(0); expGT0_uid44_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expGT0_uid44_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(expGT0_uid44_asinX_uid8_fpArcsinPiTest_b)); expGT0_uid44_asinX_uid8_fpArcsinPiTest_c(0) <= expGT0_uid44_asinX_uid8_fpArcsinPiTest_o(10); --inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest(LOGICAL,47)@0 inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a <= expGT0_uid44_asinX_uid8_fpArcsinPiTest_c; inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b <= exp0FracNotZero_uid47_asinX_uid8_fpArcsinPiTest_q; inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q <= inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_a or inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_b; --InvExc_N_uid39_asinX_uid8_fpArcsinPiTest(LOGICAL,38)@0 InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_q; InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q <= not InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_a; --InvExc_I_uid40_asinX_uid8_fpArcsinPiTest(LOGICAL,39)@0 InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_q; InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q <= not InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_a; --cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest(CONSTANT,20) cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q <= "00000000"; --expXIsZero_uid31_asinX_uid8_fpArcsinPiTest(LOGICAL,30)@0 expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_a = expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_b else "0"; --InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest(LOGICAL,40)@0 InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q; InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q <= not InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_a; --exc_R_uid42_asinX_uid8_fpArcsinPiTest(LOGICAL,41)@0 exc_R_uid42_asinX_uid8_fpArcsinPiTest_a <= InvExpXIsZero_uid41_asinX_uid8_fpArcsinPiTest_q; exc_R_uid42_asinX_uid8_fpArcsinPiTest_b <= InvExc_I_uid40_asinX_uid8_fpArcsinPiTest_q; exc_R_uid42_asinX_uid8_fpArcsinPiTest_c <= InvExc_N_uid39_asinX_uid8_fpArcsinPiTest_q; exc_R_uid42_asinX_uid8_fpArcsinPiTest_q <= exc_R_uid42_asinX_uid8_fpArcsinPiTest_a and exc_R_uid42_asinX_uid8_fpArcsinPiTest_b and exc_R_uid42_asinX_uid8_fpArcsinPiTest_c; --xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest(LOGICAL,117)@0 xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a <= exc_R_uid42_asinX_uid8_fpArcsinPiTest_q; xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b <= inputOutOfRange_uid48_asinX_uid8_fpArcsinPiTest_q; xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q <= xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_a and xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_b; --cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest(CONSTANT,17) cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q <= "11111111"; --expXIsMax_uid33_asinX_uid8_fpArcsinPiTest(LOGICAL,32)@0 expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_a = expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_b else "0"; --exc_I_uid36_asinX_uid8_fpArcsinPiTest(LOGICAL,35)@0 exc_I_uid36_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q; exc_I_uid36_asinX_uid8_fpArcsinPiTest_b <= fracXIsZero_uid35_asinX_uid8_fpArcsinPiTest_q; exc_I_uid36_asinX_uid8_fpArcsinPiTest_q <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_a and exc_I_uid36_asinX_uid8_fpArcsinPiTest_b; --exc_N_uid38_asinX_uid8_fpArcsinPiTest(LOGICAL,37)@0 exc_N_uid38_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid33_asinX_uid8_fpArcsinPiTest_q; exc_N_uid38_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid37_asinX_uid8_fpArcsinPiTest_q; exc_N_uid38_asinX_uid8_fpArcsinPiTest_q <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_a and exc_N_uid38_asinX_uid8_fpArcsinPiTest_b; --excRNaN_uid119_asinX_uid8_fpArcsinPiTest(LOGICAL,118)@0 excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid38_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b <= exc_I_uid36_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c <= xRegInOutOfRange_uid118_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid119_asinX_uid8_fpArcsinPiTest_a or excRNaN_uid119_asinX_uid8_fpArcsinPiTest_b or excRNaN_uid119_asinX_uid8_fpArcsinPiTest_c; --InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest(LOGICAL,123)@0 InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a <= excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q; InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q <= not InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_a; END IF; END PROCESS; --singX_uid17_asinX_uid8_fpArcsinPiTest(BITSELECT,16)@0 singX_uid17_asinX_uid8_fpArcsinPiTest_in <= a; singX_uid17_asinX_uid8_fpArcsinPiTest_b <= singX_uid17_asinX_uid8_fpArcsinPiTest_in(31 downto 31); --reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1(REG,512)@0 reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q <= singX_uid17_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --signR_uid125_asinX_uid8_fpArcsinPiTest(LOGICAL,124)@1 signR_uid125_asinX_uid8_fpArcsinPiTest_a <= reg_singX_uid17_asinX_uid8_fpArcsinPiTest_0_to_signR_uid125_asinX_uid8_fpArcsinPiTest_1_q; signR_uid125_asinX_uid8_fpArcsinPiTest_b <= InvExcRNaN_uid124_asinX_uid8_fpArcsinPiTest_q; signR_uid125_asinX_uid8_fpArcsinPiTest_q <= signR_uid125_asinX_uid8_fpArcsinPiTest_a and signR_uid125_asinX_uid8_fpArcsinPiTest_b; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt(COUNTER,1078) -- every=1, low=0, high=30, step=1, init=1 ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i = 29 THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '1'; ELSE ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq <= '0'; END IF; IF (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_eq = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i - 30; ELSE ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_i,5)); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg(REG,1079) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux(MUX,1080) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s <= en; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux: PROCESS (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s, ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q, ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q) BEGIN CASE ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_s IS WHEN "0" => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; WHEN "1" => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdcnt_q; WHEN OTHERS => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem(DUALMEM,1153) ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 <= areset; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia <= signR_uid125_asinX_uid8_fpArcsinPiTest_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q; ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 31, width_b => 1, widthad_b => 5, numwords_b => 31, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq, address_a => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa, data_a => ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia ); ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq(0 downto 0); --cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest(CONSTANT,22) cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q <= "01111110"; --RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,393)@19 RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 1); --rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,395)@19 rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= GND_q & RightShiftStage125dto1_uid394_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(CONSTANT,389) rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= "000000"; --rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(CONSTANT,378) rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= "000000000000000000000000"; --X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,377)@18 X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 24); --rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,379)@18 rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx3Pad24_uid379_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q & X25dto24_uid378_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,275) zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "0000000000000000"; --X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,374)@18 X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 16); --rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,376)@18 rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & X25dto16_uid375_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,371)@18 X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 8); --rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,373)@18 rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q & X25dto8_uid372_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,311) maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "100011"; --zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(CONSTANT,268) zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000000000000000"; --X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,236)@0 X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(24 downto 0); X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(24 downto 0); --leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,235) leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "000000000000"; --leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,237)@0 leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X24dto0_uid237_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx3Pad12_uid236_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,233)@0 X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(28 downto 0); X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(28 downto 0); --leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,234)@0 leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X28dto0_uid234_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; --X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,230)@0 X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q(32 downto 0); X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(32 downto 0); --leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,229) leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "0000"; --leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,231)@0 leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= X32dto0_uid231_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest(CONSTANT,53) cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q <= "0000000000000"; --oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest(BITJOIN,48)@0 oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q <= VCC_q & fracX_uid16_asinX_uid8_fpArcsinPiTest_b; --oFracXExt_uid55_asinX_uid8_fpArcsinPiTest(BITJOIN,54)@0 oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q <= cst01pWShift_uid54_asinX_uid8_fpArcsinPiTest_q & oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q; --shiftBias_uid52_asinX_uid8_fpArcsinPiTest(CONSTANT,51) shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q <= "01110010"; --shiftValue_uid53_asinX_uid8_fpArcsinPiTest(SUB,52)@0 shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid15_asinX_uid8_fpArcsinPiTest_b); shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & shiftBias_uid52_asinX_uid8_fpArcsinPiTest_q); shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(shiftValue_uid53_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(shiftValue_uid53_asinX_uid8_fpArcsinPiTest_b)); shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q <= shiftValue_uid53_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest(BITSELECT,55)@0 fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in <= shiftValue_uid53_asinX_uid8_fpArcsinPiTest_q(3 downto 0); fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_in(3 downto 0); --leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,238)@0 leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b; leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(3 downto 2); --leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest(MUX,239)@0 leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s <= leftShiftStageSel3Dto2_uid239_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b; leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest: PROCESS (leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s, en, oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q, leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= oFracXExt_uid55_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx1_uid232_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx2_uid235_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx3_uid238_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,247)@0 LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(33 downto 0); LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(33 downto 0); --leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest(CONSTANT,246) leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= "000"; --leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,248)@0 leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage033dto0_uid248_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & leftShiftStage1Idx3Pad3_uid247_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5(REG,463)@0 reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q <= leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,244)@0 LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(34 downto 0); LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(34 downto 0); --leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,245)@0 leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage034dto0_uid245_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & z2_uid93_asinX_uid8_fpArcsinPiTest_q; --reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4(REG,462)@0 reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q <= leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,241)@0 LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(35 downto 0); LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(35 downto 0); --leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITJOIN,242)@0 leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= LeftShiftStage035dto0_uid242_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b & GND_q; --reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3(REG,461)@0 reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q <= leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2(REG,460)@0 reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q <= "0000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q <= leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest(BITSELECT,249)@0 leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in <= fxpShifterBits_uid56_asinX_uid8_fpArcsinPiTest_b(1 downto 0); leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b <= leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_in(1 downto 0); --reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1(REG,459)@0 reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q <= leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest(MUX,250)@1 leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s <= reg_leftShiftStageSel1Dto0_uid250_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_1_q; leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest: PROCESS (leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s, en, reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q, reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q, reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q, reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q) BEGIN CASE leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage0_uid240_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_2_q; WHEN "01" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx1_uid243_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_3_q; WHEN "10" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx2_uid246_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_4_q; WHEN "11" => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= reg_leftShiftStage1Idx3_uid249_fxpX_uid57_asinX_uid8_fpArcsinPiTest_0_to_leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_5_q; WHEN OTHERS => leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --y_uid59_asinX_uid8_fpArcsinPiTest(BITSELECT,58)@1 y_uid59_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q(35 downto 0); y_uid59_asinX_uid8_fpArcsinPiTest_b <= y_uid59_asinX_uid8_fpArcsinPiTest_in(35 downto 1); --pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest(BITJOIN,77)@1 pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q <= VCC_q & STD_LOGIC_VECTOR((34 downto 1 => GND_q(0)) & GND_q); --oMy_uid78_asinX_uid8_fpArcsinPiTest(SUB,78)@1 oMy_uid78_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid25_uid78_asinX_uid8_fpArcsinPiTest_q); oMy_uid78_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & y_uid59_asinX_uid8_fpArcsinPiTest_b); oMy_uid78_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMy_uid78_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(oMy_uid78_asinX_uid8_fpArcsinPiTest_b)); oMy_uid78_asinX_uid8_fpArcsinPiTest_q <= oMy_uid78_asinX_uid8_fpArcsinPiTest_o(36 downto 0); --l_uid80_asinX_uid8_fpArcsinPiTest(BITSELECT,79)@1 l_uid80_asinX_uid8_fpArcsinPiTest_in <= oMy_uid78_asinX_uid8_fpArcsinPiTest_q(34 downto 0); l_uid80_asinX_uid8_fpArcsinPiTest_b <= l_uid80_asinX_uid8_fpArcsinPiTest_in(34 downto 0); --rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,269)@1 rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= l_uid80_asinX_uid8_fpArcsinPiTest_b; rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 3); --reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,473)@1 reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,270)@2 vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid270_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q; vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f(DELAY,842)@2 ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,272)@1 vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= l_uid80_asinX_uid8_fpArcsinPiTest_b(2 downto 0); vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(2 downto 0); --cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,273)@1 cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid273_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & zs_uid269_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; --reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,475)@1 reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,474)@1 reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= l_uid80_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,274)@2 vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q) BEGIN CASE vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_l_uid80_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q; WHEN "1" => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid274_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q; WHEN OTHERS => vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,276)@2 rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 19); --reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,476)@2 reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,277)@3 vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid277_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q; vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e(DELAY,841)@3 ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,279)@2 vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(18 downto 0); vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(18 downto 0); --cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,280)@2 cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid280_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & zs_uid276_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; --reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,478)@2 reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,477)@2 reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,281)@3 vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q) BEGIN CASE vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_vStagei_uid275_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q; WHEN "1" => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid281_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q; WHEN OTHERS => vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,283)@3 rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 27); --vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,284)@3 vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid284_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,482)@3 reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,286)@3 vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(26 downto 0); vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(26 downto 0); --cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,287)@3 cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid287_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; --vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,288)@3 vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid282_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid288_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,290)@3 rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 31); --reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,479)@3 reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,291)@4 vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= reg_rVStage_uid291_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q; vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,293)@3 vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(30 downto 0); vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(30 downto 0); --cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,294)@3 cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid294_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; --reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3(REG,481)@3 reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q <= cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2(REG,480)@3 reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q <= vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,295)@4 vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q, reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q) BEGIN CASE vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_vStagei_uid289_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_2_q; WHEN "1" => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= reg_cStage_uid295_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q; WHEN OTHERS => vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,297)@4 rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 33); --vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,298)@4 vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid298_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= z2_uid93_asinX_uid8_fpArcsinPiTest_q; vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,300)@4 vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(32 downto 0); vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(32 downto 0); --cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,301)@4 cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid301_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & z2_uid93_asinX_uid8_fpArcsinPiTest_q; --vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,302)@4 vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid296_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid302_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,304)@4 rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(34 downto 34); --vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(LOGICAL,305)@4 vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= rVStage_uid305_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b; vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= GND_q; vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= "1" when vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a = vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b else "0"; --vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,310)@4 vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= ld_vCount_uid271_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_f_q & ld_vCount_uid278_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_e_q & reg_vCount_uid285_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_3_q & vCount_uid292_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & vCount_uid299_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q & vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; --ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c(DELAY,845)@4 ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 6, depth => 1 ) PORT MAP ( xin => vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, xout => ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1(REG,483)@4 reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q <= vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(COMPARE,312)@5 vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin <= GND_q; vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) & '0'; vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & reg_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_0_to_vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_1_q) & vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_cin(0); vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b)); vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c(0) <= vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_o(8); --vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,314)@5 vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCountBig_uid313_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c; vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= ld_vCount_uid311_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q_to_vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_c_q; WHEN "1" => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= maxCountVal_uid312_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --cstBiasM2_uid6_fpArcsinPiTest(CONSTANT,5) cstBiasM2_uid6_fpArcsinPiTest_q <= "01111101"; --expL_uid82_asinX_uid8_fpArcsinPiTest(SUB,81)@6 expL_uid82_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM2_uid6_fpArcsinPiTest_q); expL_uid82_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("000" & vCountFinal_uid315_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q); expL_uid82_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expL_uid82_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(expL_uid82_asinX_uid8_fpArcsinPiTest_b)); expL_uid82_asinX_uid8_fpArcsinPiTest_q <= expL_uid82_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --expLRange_uid84_asinX_uid8_fpArcsinPiTest(BITSELECT,83)@6 expLRange_uid84_asinX_uid8_fpArcsinPiTest_in <= expL_uid82_asinX_uid8_fpArcsinPiTest_q(7 downto 0); expLRange_uid84_asinX_uid8_fpArcsinPiTest_b <= expLRange_uid84_asinX_uid8_fpArcsinPiTest_in(7 downto 0); --vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITSELECT,307)@4 vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(33 downto 0); vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b <= vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_in(33 downto 0); --cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(BITJOIN,308)@4 cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStage_uid308_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_b & GND_q; --vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest(MUX,309)@4 vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s <= vCount_uid306_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest: PROCESS (vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s, en, vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q, cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= vStagei_uid303_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= cStage_uid309_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest(BITSELECT,82)@4 fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in <= vStagei_uid310_fpLOut1_uid81_asinX_uid8_fpArcsinPiTest_q(33 downto 0); fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b <= fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_in(33 downto 11); --reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0(REG,484)@4 reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q <= fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a(DELAY,581)@5 ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q, xout => ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --fpL_uid85_asinX_uid8_fpArcsinPiTest(BITJOIN,84)@6 fpL_uid85_asinX_uid8_fpArcsinPiTest_q <= GND_q & expLRange_uid84_asinX_uid8_fpArcsinPiTest_b & ld_reg_fpLOutFrac_uid83_asinX_uid8_fpArcsinPiTest_0_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_0_q_to_fpL_uid85_asinX_uid8_fpArcsinPiTest_a_q; --signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,319)@6 signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q; signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(31 downto 31); --expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,317)@6 expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q(30 downto 0); expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(30 downto 23); --expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,324)@6 expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1" when expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b else "0"; --negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,367)@6 negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; END IF; END PROCESS; --ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c(DELAY,901)@7 ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 10 ) PORT MAP ( xin => negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor(LOGICAL,1176) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q <= not (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_a or ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_b); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top(CONSTANT,1172) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q <= "0110"; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp(LOGICAL,1173) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_mem_top_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q); ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q <= "1" when ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_a = ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_b else "0"; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg(REG,1174) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena(REG,1177) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_nor_q = "1") THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd(LOGICAL,1178) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b <= en; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_a and ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_b; --reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0(REG,494)@6 reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(ADD,340)@7 expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q); expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q); expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b)); expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,341)@7 expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expOddSig_uid341_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(8 downto 1); --expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(ADD,337)@7 expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q); expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid22_asinX_uid8_fpArcsinPiTest_q); expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b)); expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,338)@7 expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expEvenSig_uid338_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(8 downto 1); --expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,342)@6 expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(0 downto 0); expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(0 downto 0); --expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,343)@6 expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX0_uid343_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(DELAY,869)@6 ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,344)@7 expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= ld_expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q; expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expREven_uid339_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; WHEN "1" => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expROdd_uid342_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,877)@6 ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,332)@7 InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,318)@6 fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fpL_uid85_asinX_uid8_fpArcsinPiTest_q(22 downto 0); fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(22 downto 0); --reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1(REG,485)@6 reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,328)@7 fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= reg_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_1_q; fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1" when fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b else "0"; --expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,326)@6 expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expX_uid318_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN IF (expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a = expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b) THEN expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "1"; ELSE expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "0"; END IF; END IF; END PROCESS; --exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,329)@7 exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,333)@7 InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,334)@6 InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; END IF; END PROCESS; --exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,335)@7 exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= InvExpXIsZero_uid335_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvExc_I_uid334_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c <= InvExc_N_uid333_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b and exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c; --minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,353)@7 minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_R_uid336_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,354)@7 minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,330)@7 InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= fracXIsZero_uid329_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,331)@7 exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= expXIsMax_uid327_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvFracXIsZero_uid331_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,355)@7 excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_N_uid332_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= minInf_uid355_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c <= minReg_uid354_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a or excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b or excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c; --InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,351)@7 InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= not InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a; --inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOGICAL,352)@7 inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a <= exc_I_uid330_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a and inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,887)@6 ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,356)@7 join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= excRNaN_uid356_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & inInfAndNotNeg_uid353_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & ld_expXIsZero_uid325_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q; --fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,357)@7 fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= ld_signX_uid320_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_InvSignX_uid352_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q & join_uid357_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; --reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0(REG,486)@7 reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q <= fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(LOOKUP,358)@8 fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_fracSelIn_uid358_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_q) IS WHEN "0000" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "0001" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "0010" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "0011" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "0100" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "0101" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "0110" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "0111" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "1000" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1001" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "1010" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1011" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1100" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1101" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1110" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "1111" => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN OTHERS => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,362)@8 expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expRMux_uid345_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg(DELAY,1166) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt(COUNTER,1168) -- every=1, low=0, high=6, step=1, init=1 ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i = 5 THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i - 6; ELSE ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i,3)); --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg(REG,1169) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux(MUX,1170) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s <= en; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux: PROCESS (ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s, ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q, ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem(DUALMEM,1167) ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 <= areset; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_inputreg_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 7, width_b => 8, widthad_b => 3, numwords_b => 7, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq, address_a => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa, data_a => ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia ); ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q <= ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq(7 downto 0); --cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest(CONSTANT,19) cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q <= "00000000000000000000001"; --fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,346)@6 fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(22 downto 16); --addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,347)@6 addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= expOddSelect_uid344_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q & fracXAddr_uid347_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; --reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0(REG,487)@6 reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q <= addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --memoryC2_uid424_sqrtTableGenerator_lutmem(DUALMEM,457)@7 memoryC2_uid424_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC2_uid424_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC2_uid424_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC2_uid424_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q; memoryC2_uid424_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC2_uid424_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid424_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid424_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid424_sqrtTableGenerator_lutmem_iq, address_a => memoryC2_uid424_sqrtTableGenerator_lutmem_aa, data_a => memoryC2_uid424_sqrtTableGenerator_lutmem_ia ); memoryC2_uid424_sqrtTableGenerator_lutmem_q <= memoryC2_uid424_sqrtTableGenerator_lutmem_iq(11 downto 0); --reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1(REG,489)@9 reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q <= memoryC2_uid424_sqrtTableGenerator_lutmem_q; END IF; END IF; END PROCESS; --ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1165) ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a(DELAY,875)@6 ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_inputreg_q, xout => ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,348)@9 FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= ld_fracX_uid319_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_a_q(15 downto 0); FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(15 downto 0); --yT1_uid425_sqrtPolynomialEvaluator(BITSELECT,424)@9 yT1_uid425_sqrtPolynomialEvaluator_in <= FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; yT1_uid425_sqrtPolynomialEvaluator_b <= yT1_uid425_sqrtPolynomialEvaluator_in(15 downto 4); --reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0(REG,488)@9 reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q <= yT1_uid425_sqrtPolynomialEvaluator_b; END IF; END IF; END PROCESS; --prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator(MULT,443)@10 prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a),13)) * SIGNED(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b); prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_a <= reg_yT1_uid425_sqrtPolynomialEvaluator_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_0_q; prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_b <= reg_memoryC2_uid424_sqrtTableGenerator_lutmem_0_to_prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_1_q; prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_pr,24)); END IF; END IF; END PROCESS; prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q <= prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator(BITSELECT,444)@13 prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in <= prodXY_uid444_pT1_uid426_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_in(23 downto 11); --highBBits_uid428_sqrtPolynomialEvaluator(BITSELECT,427)@13 highBBits_uid428_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b; highBBits_uid428_sqrtPolynomialEvaluator_b <= highBBits_uid428_sqrtPolynomialEvaluator_in(12 downto 1); --ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a(DELAY,983)@7 ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid424_sqrtTableGenerator_lutmem_0_q, xout => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg(DELAY,1217) ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_q, xout => ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid423_sqrtTableGenerator_lutmem(DUALMEM,456)@11 memoryC1_uid423_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC1_uid423_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC1_uid423_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC1_uid423_sqrtTableGenerator_lutmem_ab <= ld_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid423_sqrtTableGenerator_lutmem_0_q_to_memoryC1_uid423_sqrtTableGenerator_lutmem_a_outputreg_q; memoryC1_uid423_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 8, numwords_a => 256, width_b => 21, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC1_uid423_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid423_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid423_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid423_sqrtTableGenerator_lutmem_iq, address_a => memoryC1_uid423_sqrtTableGenerator_lutmem_aa, data_a => memoryC1_uid423_sqrtTableGenerator_lutmem_ia ); memoryC1_uid423_sqrtTableGenerator_lutmem_q <= memoryC1_uid423_sqrtTableGenerator_lutmem_iq(20 downto 0); --sumAHighB_uid429_sqrtPolynomialEvaluator(ADD,428)@13 sumAHighB_uid429_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid423_sqrtTableGenerator_lutmem_q(20)) & memoryC1_uid423_sqrtTableGenerator_lutmem_q); sumAHighB_uid429_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((21 downto 12 => highBBits_uid428_sqrtPolynomialEvaluator_b(11)) & highBBits_uid428_sqrtPolynomialEvaluator_b); sumAHighB_uid429_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid429_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid429_sqrtPolynomialEvaluator_b)); sumAHighB_uid429_sqrtPolynomialEvaluator_q <= sumAHighB_uid429_sqrtPolynomialEvaluator_o(21 downto 0); --lowRangeB_uid427_sqrtPolynomialEvaluator(BITSELECT,426)@13 lowRangeB_uid427_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid445_pT1_uid426_sqrtPolynomialEvaluator_b(0 downto 0); lowRangeB_uid427_sqrtPolynomialEvaluator_b <= lowRangeB_uid427_sqrtPolynomialEvaluator_in(0 downto 0); --s1_uid427_uid430_sqrtPolynomialEvaluator(BITJOIN,429)@13 s1_uid427_uid430_sqrtPolynomialEvaluator_q <= sumAHighB_uid429_sqrtPolynomialEvaluator_q & lowRangeB_uid427_sqrtPolynomialEvaluator_b; --reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1(REG,492)@13 reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q <= s1_uid427_uid430_sqrtPolynomialEvaluator_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor(LOGICAL,1240) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q <= not (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_a or ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_b); --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg(REG,1238) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena(REG,1241) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_nor_q = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd(LOGICAL,1242) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_sticky_ena_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b <= en; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_a and ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_b; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg(DELAY,1232) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg : dspba_delay GENERIC MAP ( width => 16, depth => 1 ) PORT MAP ( xin => FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, xout => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt(COUNTER,1234) -- every=1, low=0, high=1, step=1, init=1 ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_i,1)); --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg(REG,1235) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux(MUX,1236) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s <= en; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux: PROCESS (ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s, ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q, ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q) BEGIN CASE ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_s IS WHEN "0" => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; WHEN "1" => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdcnt_q; WHEN OTHERS => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem(DUALMEM,1233) ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0 <= areset; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_inputreg_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdreg_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_rdmux_q; ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 16, widthad_a => 1, numwords_a => 2, width_b => 16, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq, address_a => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_aa, data_a => ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_ia ); ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_iq(15 downto 0); --reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0(REG,491)@13 reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q <= ld_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_to_reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator(MULT,446)@14 prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr <= signed(resize(UNSIGNED(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a),17)) * SIGNED(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b); prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a <= (others => '0'); prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b <= (others => '0'); prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_a <= reg_FracX15dto0_uid349_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_0_q; prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_b <= reg_s1_uid427_uid430_sqrtPolynomialEvaluator_0_to_prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_1_q; prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_pr,39)); END IF; END IF; END PROCESS; prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q <= prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator(BITSELECT,447)@17 prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in <= prodXY_uid447_pT2_uid432_sqrtPolynomialEvaluator_q; prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_in(38 downto 15); --highBBits_uid434_sqrtPolynomialEvaluator(BITSELECT,433)@17 highBBits_uid434_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b; highBBits_uid434_sqrtPolynomialEvaluator_b <= highBBits_uid434_sqrtPolynomialEvaluator_in(23 downto 2); --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor(LOGICAL,1253) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q <= not (ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_a or ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_b); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top(CONSTANT,1184) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q <= "0101"; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp(LOGICAL,1185) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_mem_top_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q); ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q <= "1" when ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_a = ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_b else "0"; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg(REG,1186) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena(REG,1254) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_nor_q = "1") THEN ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd(LOGICAL,1255) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_sticky_ena_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b <= en; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_a and ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_b; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg(DELAY,1243) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt(COUNTER,1180) -- every=1, low=0, high=5, step=1, init=1 ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i = 4 THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i - 5; ELSE ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_i,3)); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg(REG,1181) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux(MUX,1182) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s <= en; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux: PROCESS (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s, ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q, ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem(DUALMEM,1244) ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0 <= areset; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_inputreg_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq, address_a => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_aa, data_a => ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_ia ); ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0(REG,493)@14 reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q <= ld_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid422_sqrtTableGenerator_lutmem(DUALMEM,455)@15 memoryC0_uid422_sqrtTableGenerator_lutmem_reset0 <= areset; memoryC0_uid422_sqrtTableGenerator_lutmem_ia <= (others => '0'); memoryC0_uid422_sqrtTableGenerator_lutmem_aa <= (others => '0'); memoryC0_uid422_sqrtTableGenerator_lutmem_ab <= reg_addrTable_uid348_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid422_sqrtTableGenerator_lutmem_0_q; memoryC0_uid422_sqrtTableGenerator_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 29, widthad_a => 8, numwords_a => 256, width_b => 29, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC0_uid422_sqrtTableGenerator_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid422_sqrtTableGenerator_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid422_sqrtTableGenerator_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid422_sqrtTableGenerator_lutmem_iq, address_a => memoryC0_uid422_sqrtTableGenerator_lutmem_aa, data_a => memoryC0_uid422_sqrtTableGenerator_lutmem_ia ); memoryC0_uid422_sqrtTableGenerator_lutmem_q <= memoryC0_uid422_sqrtTableGenerator_lutmem_iq(28 downto 0); --sumAHighB_uid435_sqrtPolynomialEvaluator(ADD,434)@17 sumAHighB_uid435_sqrtPolynomialEvaluator_a <= STD_LOGIC_VECTOR((29 downto 29 => memoryC0_uid422_sqrtTableGenerator_lutmem_q(28)) & memoryC0_uid422_sqrtTableGenerator_lutmem_q); sumAHighB_uid435_sqrtPolynomialEvaluator_b <= STD_LOGIC_VECTOR((29 downto 22 => highBBits_uid434_sqrtPolynomialEvaluator_b(21)) & highBBits_uid434_sqrtPolynomialEvaluator_b); sumAHighB_uid435_sqrtPolynomialEvaluator_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid435_sqrtPolynomialEvaluator_a) + SIGNED(sumAHighB_uid435_sqrtPolynomialEvaluator_b)); sumAHighB_uid435_sqrtPolynomialEvaluator_q <= sumAHighB_uid435_sqrtPolynomialEvaluator_o(29 downto 0); --lowRangeB_uid433_sqrtPolynomialEvaluator(BITSELECT,432)@17 lowRangeB_uid433_sqrtPolynomialEvaluator_in <= prodXYTruncFR_uid448_pT2_uid432_sqrtPolynomialEvaluator_b(1 downto 0); lowRangeB_uid433_sqrtPolynomialEvaluator_b <= lowRangeB_uid433_sqrtPolynomialEvaluator_in(1 downto 0); --s2_uid433_uid436_sqrtPolynomialEvaluator(BITJOIN,435)@17 s2_uid433_uid436_sqrtPolynomialEvaluator_q <= sumAHighB_uid435_sqrtPolynomialEvaluator_q & lowRangeB_uid433_sqrtPolynomialEvaluator_b; --fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITSELECT,350)@17 fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in <= s2_uid433_uid436_sqrtPolynomialEvaluator_q(28 downto 0); fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b <= fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_in(28 downto 6); --ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b(DELAY,895)@8 ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 2, depth => 9 ) PORT MAP ( xin => fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q, xout => ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(MUX,366)@17 fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s <= ld_fracSel_uid359_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_q; fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= fracR_uid351_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b; WHEN "10" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest(BITJOIN,368)@17 RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q <= ld_negZero_uid368_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_c_q & ld_expRPostExc_uid363_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q_to_RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_b_replace_mem_q & fracRPostExc_uid367_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q; --SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest(BITSELECT,89)@17 SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in <= RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q(22 downto 0); SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b <= SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_in(22 downto 0); --ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a(DELAY,586)@17 ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b, xout => ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest(BITJOIN,90)@18 oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q <= VCC_q & ld_SqrtFPL22dto0_uid90_asinX_uid8_fpArcsinPiTest_b_to_oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_a_q; --z2_uid93_asinX_uid8_fpArcsinPiTest(CONSTANT,92) z2_uid93_asinX_uid8_fpArcsinPiTest_q <= "00"; --oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest(BITJOIN,93)@18 oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q <= oSqrtFPLFrac_uid91_asinX_uid8_fpArcsinPiTest_q & z2_uid93_asinX_uid8_fpArcsinPiTest_q; --SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest(BITSELECT,87)@17 SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in <= RSqrt_uid369_sqrtFPL_uid87_asinX_uid8_fpArcsinPiTest_q(30 downto 0); SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b <= SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_in(30 downto 23); --reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1(REG,496)@17 reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q <= SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --srVal_uid89_asinX_uid8_fpArcsinPiTest(SUB,88)@18 srVal_uid89_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q); srVal_uid89_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & reg_SqrtFPL30dto23_uid88_asinX_uid8_fpArcsinPiTest_0_to_srVal_uid89_asinX_uid8_fpArcsinPiTest_1_q); srVal_uid89_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(srVal_uid89_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(srVal_uid89_asinX_uid8_fpArcsinPiTest_b)); srVal_uid89_asinX_uid8_fpArcsinPiTest_q <= srVal_uid89_asinX_uid8_fpArcsinPiTest_o(8 downto 0); --srValRange_uid92_asinX_uid8_fpArcsinPiTest(BITSELECT,91)@18 srValRange_uid92_asinX_uid8_fpArcsinPiTest_in <= srVal_uid89_asinX_uid8_fpArcsinPiTest_q(4 downto 0); srValRange_uid92_asinX_uid8_fpArcsinPiTest_b <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_in(4 downto 0); --rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,380)@18 rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b; rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(4 downto 3); --rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,381)@18 rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= rightShiftStageSel4Dto3_uid381_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= oSqrtFPLFracZ2_uid94_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx1_uid374_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx2_uid377_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage0Idx3_uid380_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,388)@18 RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 6); --rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,390)@18 rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage1Idx3Pad6_uid390_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto6_uid389_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5(REG,501)@18 reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q <= rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,385)@18 RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 4); --rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,387)@18 rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= leftShiftStage0Idx1Pad4_uid230_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto4_uid386_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4(REG,500)@18 reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q <= rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,382)@18 RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(25 downto 2); --rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITJOIN,384)@18 rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= z2_uid93_asinX_uid8_fpArcsinPiTest_q & RightShiftStage025dto2_uid383_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; --reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3(REG,499)@18 reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q <= rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2(REG,498)@18 reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q <= rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,391)@18 rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b(2 downto 0); rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(2 downto 1); --reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1(REG,497)@18 reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,392)@19 rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= reg_rightShiftStageSel2Dto1_uid392_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q; rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q, reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q, reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q, reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q) BEGIN CASE rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage0_uid382_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_2_q; WHEN "01" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx1_uid385_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_3_q; WHEN "10" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx2_uid388_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_4_q; WHEN "11" => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= reg_rightShiftStage1Idx3_uid391_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_5_q; WHEN OTHERS => rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(BITSELECT,396)@18 rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in <= srValRange_uid92_asinX_uid8_fpArcsinPiTest_b(0 downto 0); rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b <= rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_in(0 downto 0); --reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1(REG,502)@18 reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q <= rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest(MUX,397)@19 rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s <= reg_rightShiftStageSel0Dto0_uid397_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_0_to_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_1_q; rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest: PROCESS (rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s, en, rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage1_uid393_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= rightShiftStage2Idx1_uid396_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --mAddr_uid97_asinX_uid8_fpArcsinPiTest(BITSELECT,96)@19 mAddr_uid97_asinX_uid8_fpArcsinPiTest_in <= rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q; mAddr_uid97_asinX_uid8_fpArcsinPiTest_b <= mAddr_uid97_asinX_uid8_fpArcsinPiTest_in(25 downto 18); --reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0(REG,503)@19 reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q <= mAddr_uid97_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid402_arcsinXTabGen_lutmem(DUALMEM,454)@20 memoryC2_uid402_arcsinXTabGen_lutmem_reset0 <= areset; memoryC2_uid402_arcsinXTabGen_lutmem_ia <= (others => '0'); memoryC2_uid402_arcsinXTabGen_lutmem_aa <= (others => '0'); memoryC2_uid402_arcsinXTabGen_lutmem_ab <= reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q; memoryC2_uid402_arcsinXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 8, numwords_a => 256, width_b => 13, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC2_uid402_arcsinXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid402_arcsinXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid402_arcsinXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid402_arcsinXTabGen_lutmem_iq, address_a => memoryC2_uid402_arcsinXTabGen_lutmem_aa, data_a => memoryC2_uid402_arcsinXTabGen_lutmem_ia ); memoryC2_uid402_arcsinXTabGen_lutmem_q <= memoryC2_uid402_arcsinXTabGen_lutmem_iq(12 downto 0); --reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1(REG,505)@22 reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q <= memoryC2_uid402_arcsinXTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1063) ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q, xout => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a(DELAY,590)@19 ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 26, depth => 2 ) PORT MAP ( xin => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_inputreg_q, xout => ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest(BITSELECT,97)@22 mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in <= ld_rightShiftStage2_uid398_alignSqrt_uid95_asinX_uid8_fpArcsinPiTest_q_to_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_a_q(17 downto 0); mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_in(17 downto 1); --yT1_uid403_arcsinXPolyEval(BITSELECT,402)@22 yT1_uid403_arcsinXPolyEval_in <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b; yT1_uid403_arcsinXPolyEval_b <= yT1_uid403_arcsinXPolyEval_in(16 downto 4); --reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0(REG,504)@22 reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q <= yT1_uid403_arcsinXPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid438_pT1_uid404_arcsinXPolyEval(MULT,437)@23 prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid438_pT1_uid404_arcsinXPolyEval_a),14)) * SIGNED(prodXY_uid438_pT1_uid404_arcsinXPolyEval_b); prodXY_uid438_pT1_uid404_arcsinXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_a <= (others => '0'); prodXY_uid438_pT1_uid404_arcsinXPolyEval_b <= (others => '0'); prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_a <= reg_yT1_uid403_arcsinXPolyEval_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_0_q; prodXY_uid438_pT1_uid404_arcsinXPolyEval_b <= reg_memoryC2_uid402_arcsinXTabGen_lutmem_0_to_prodXY_uid438_pT1_uid404_arcsinXPolyEval_1_q; prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid438_pT1_uid404_arcsinXPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid438_pT1_uid404_arcsinXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid438_pT1_uid404_arcsinXPolyEval_q <= prodXY_uid438_pT1_uid404_arcsinXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval(BITSELECT,438)@26 prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in <= prodXY_uid438_pT1_uid404_arcsinXPolyEval_q; prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_in(25 downto 12); --highBBits_uid406_arcsinXPolyEval(BITSELECT,405)@26 highBBits_uid406_arcsinXPolyEval_in <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b; highBBits_uid406_arcsinXPolyEval_b <= highBBits_uid406_arcsinXPolyEval_in(13 downto 1); --ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a(DELAY,980)@20 ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid402_arcsinXTabGen_lutmem_0_q, xout => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg(DELAY,1216) ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_q, xout => ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid401_arcsinXTabGen_lutmem(DUALMEM,453)@24 memoryC1_uid401_arcsinXTabGen_lutmem_reset0 <= areset; memoryC1_uid401_arcsinXTabGen_lutmem_ia <= (others => '0'); memoryC1_uid401_arcsinXTabGen_lutmem_aa <= (others => '0'); memoryC1_uid401_arcsinXTabGen_lutmem_ab <= ld_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid401_arcsinXTabGen_lutmem_0_q_to_memoryC1_uid401_arcsinXTabGen_lutmem_a_outputreg_q; memoryC1_uid401_arcsinXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 8, numwords_a => 256, width_b => 23, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC1_uid401_arcsinXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid401_arcsinXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid401_arcsinXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid401_arcsinXTabGen_lutmem_iq, address_a => memoryC1_uid401_arcsinXTabGen_lutmem_aa, data_a => memoryC1_uid401_arcsinXTabGen_lutmem_ia ); memoryC1_uid401_arcsinXTabGen_lutmem_q <= memoryC1_uid401_arcsinXTabGen_lutmem_iq(22 downto 0); --sumAHighB_uid407_arcsinXPolyEval(ADD,406)@26 sumAHighB_uid407_arcsinXPolyEval_a <= STD_LOGIC_VECTOR((23 downto 23 => memoryC1_uid401_arcsinXTabGen_lutmem_q(22)) & memoryC1_uid401_arcsinXTabGen_lutmem_q); sumAHighB_uid407_arcsinXPolyEval_b <= STD_LOGIC_VECTOR((23 downto 13 => highBBits_uid406_arcsinXPolyEval_b(12)) & highBBits_uid406_arcsinXPolyEval_b); sumAHighB_uid407_arcsinXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid407_arcsinXPolyEval_a) + SIGNED(sumAHighB_uid407_arcsinXPolyEval_b)); sumAHighB_uid407_arcsinXPolyEval_q <= sumAHighB_uid407_arcsinXPolyEval_o(23 downto 0); --lowRangeB_uid405_arcsinXPolyEval(BITSELECT,404)@26 lowRangeB_uid405_arcsinXPolyEval_in <= prodXYTruncFR_uid439_pT1_uid404_arcsinXPolyEval_b(0 downto 0); lowRangeB_uid405_arcsinXPolyEval_b <= lowRangeB_uid405_arcsinXPolyEval_in(0 downto 0); --s1_uid405_uid408_arcsinXPolyEval(BITJOIN,407)@26 s1_uid405_uid408_arcsinXPolyEval_q <= sumAHighB_uid407_arcsinXPolyEval_q & lowRangeB_uid405_arcsinXPolyEval_b; --reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1(REG,508)@26 reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q <= "0000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q <= s1_uid405_uid408_arcsinXPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor(LOGICAL,1200) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q <= not (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_a or ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_b); --roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest(CONSTANT,185) roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q <= "010"; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp(LOGICAL,1197) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a <= roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q); ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q <= "1" when ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_a = ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_b else "0"; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg(REG,1198) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena(REG,1201) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_nor_q = "1") THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd(LOGICAL,1202) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_sticky_ena_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b <= en; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_a and ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_b; --reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0(REG,507)@22 reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q <= "00000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q <= mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt(COUNTER,1192) -- every=1, low=0, high=2, step=1, init=1 ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= TO_UNSIGNED(1,2); ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i = 1 THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_eq = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i - 2; ELSE ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_i,2)); --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg(REG,1193) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux(MUX,1194) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s <= en; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux: PROCESS (ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s, ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q, ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q) BEGIN CASE ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_s IS WHEN "0" => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q; WHEN "1" => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem(DUALMEM,1191) ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0 <= areset; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia <= reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdreg_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_rdmux_q; ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 17, widthad_a => 2, numwords_a => 3, width_b => 17, widthad_b => 2, numwords_b => 3, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq, address_a => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_aa, data_a => ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_ia ); ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_iq(16 downto 0); --prodXY_uid441_pT2_uid410_arcsinXPolyEval(MULT,440)@27 prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid441_pT2_uid410_arcsinXPolyEval_a),18)) * SIGNED(prodXY_uid441_pT2_uid410_arcsinXPolyEval_b); prodXY_uid441_pT2_uid410_arcsinXPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_a <= (others => '0'); prodXY_uid441_pT2_uid410_arcsinXPolyEval_b <= (others => '0'); prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_a <= ld_reg_mPPolyEval_uid98_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_0_q_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_a_replace_mem_q; prodXY_uid441_pT2_uid410_arcsinXPolyEval_b <= reg_s1_uid405_uid408_arcsinXPolyEval_0_to_prodXY_uid441_pT2_uid410_arcsinXPolyEval_1_q; prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid441_pT2_uid410_arcsinXPolyEval_pr,42)); END IF; END IF; END PROCESS; prodXY_uid441_pT2_uid410_arcsinXPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid441_pT2_uid410_arcsinXPolyEval_q <= prodXY_uid441_pT2_uid410_arcsinXPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval(BITSELECT,441)@30 prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in <= prodXY_uid441_pT2_uid410_arcsinXPolyEval_q; prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_in(41 downto 16); --highBBits_uid412_arcsinXPolyEval(BITSELECT,411)@30 highBBits_uid412_arcsinXPolyEval_in <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b; highBBits_uid412_arcsinXPolyEval_b <= highBBits_uid412_arcsinXPolyEval_in(25 downto 2); --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor(LOGICAL,1266) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q <= not (ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_a or ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_b); --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena(REG,1267) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_nor_q = "1") THEN ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd(LOGICAL,1268) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_sticky_ena_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b <= en; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_a and ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_b; --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg(DELAY,1256) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => mAddr_uid97_asinX_uid8_fpArcsinPiTest_b, xout => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem(DUALMEM,1257) ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0 <= areset; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_inputreg_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq, address_a => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_aa, data_a => ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_ia ); ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_iq(7 downto 0); --reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0(REG,509)@27 reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q <= ld_mAddr_uid97_asinX_uid8_fpArcsinPiTest_b_to_reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_a_replace_mem_q; END IF; END IF; END PROCESS; --memoryC0_uid400_arcsinXTabGen_lutmem(DUALMEM,452)@28 memoryC0_uid400_arcsinXTabGen_lutmem_reset0 <= areset; memoryC0_uid400_arcsinXTabGen_lutmem_ia <= (others => '0'); memoryC0_uid400_arcsinXTabGen_lutmem_aa <= (others => '0'); memoryC0_uid400_arcsinXTabGen_lutmem_ab <= reg_mAddr_uid97_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid400_arcsinXTabGen_lutmem_0_q; memoryC0_uid400_arcsinXTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC0_uid400_arcsinXTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid400_arcsinXTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid400_arcsinXTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid400_arcsinXTabGen_lutmem_iq, address_a => memoryC0_uid400_arcsinXTabGen_lutmem_aa, data_a => memoryC0_uid400_arcsinXTabGen_lutmem_ia ); memoryC0_uid400_arcsinXTabGen_lutmem_q <= memoryC0_uid400_arcsinXTabGen_lutmem_iq(29 downto 0); --sumAHighB_uid413_arcsinXPolyEval(ADD,412)@30 sumAHighB_uid413_arcsinXPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid400_arcsinXTabGen_lutmem_q(29)) & memoryC0_uid400_arcsinXTabGen_lutmem_q); sumAHighB_uid413_arcsinXPolyEval_b <= STD_LOGIC_VECTOR((30 downto 24 => highBBits_uid412_arcsinXPolyEval_b(23)) & highBBits_uid412_arcsinXPolyEval_b); sumAHighB_uid413_arcsinXPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid413_arcsinXPolyEval_a) + SIGNED(sumAHighB_uid413_arcsinXPolyEval_b)); sumAHighB_uid413_arcsinXPolyEval_q <= sumAHighB_uid413_arcsinXPolyEval_o(30 downto 0); --lowRangeB_uid411_arcsinXPolyEval(BITSELECT,410)@30 lowRangeB_uid411_arcsinXPolyEval_in <= prodXYTruncFR_uid442_pT2_uid410_arcsinXPolyEval_b(1 downto 0); lowRangeB_uid411_arcsinXPolyEval_b <= lowRangeB_uid411_arcsinXPolyEval_in(1 downto 0); --s2_uid411_uid414_arcsinXPolyEval(BITJOIN,413)@30 s2_uid411_uid414_arcsinXPolyEval_q <= sumAHighB_uid413_arcsinXPolyEval_q & lowRangeB_uid411_arcsinXPolyEval_b; --fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest(BITSELECT,99)@30 fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in <= s2_uid411_uid414_arcsinXPolyEval_q(30 downto 0); fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b <= fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_in(30 downto 3); --reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1(REG,510)@30 reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q <= "0000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q <= fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --piO2_uid101_asinX_uid8_fpArcsinPiTest(CONSTANT,100) piO2_uid101_asinX_uid8_fpArcsinPiTest_q <= "1100100100001111110110101010"; --path3Diff_uid102_asinX_uid8_fpArcsinPiTest(SUB,101)@31 path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & piO2_uid101_asinX_uid8_fpArcsinPiTest_q); path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & reg_fxpArcsinX_uid100_asinX_uid8_fpArcsinPiTest_0_to_path3Diff_uid102_asinX_uid8_fpArcsinPiTest_1_q); path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(path3Diff_uid102_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(path3Diff_uid102_asinX_uid8_fpArcsinPiTest_b)); path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_o(28 downto 0); --normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest(BITSELECT,102)@31 normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(27 downto 0); normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_in(27 downto 27); --expRPath3_uid107_asinX_uid8_fpArcsinPiTest(MUX,106)@31 expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b; expRPath3_uid107_asinX_uid8_fpArcsinPiTest: PROCESS (expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s, en, cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q, cstBias_uid22_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPath3_uid107_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= cstBiasM1_uid23_asinX_uid8_fpArcsinPiTest_q; WHEN "1" => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest(BITSELECT,103)@31 path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(26 downto 0); path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b <= path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_in(26 downto 3); --path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest(BITSELECT,104)@31 path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in <= path3Diff_uid102_asinX_uid8_fpArcsinPiTest_q(25 downto 0); path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b <= path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_in(25 downto 2); --fracRPath3_uid106_asinX_uid8_fpArcsinPiTest(MUX,105)@31 fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s <= normBitPath3Diff_uid103_asinX_uid8_fpArcsinPiTest_b; fracRPath3_uid106_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s, en, path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b, path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b) BEGIN CASE fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= path3DiffLow_uid105_asinX_uid8_fpArcsinPiTest_b; WHEN "1" => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= path3DiffHigh_uid104_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest(BITJOIN,107)@31 expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q <= expRPath3_uid107_asinX_uid8_fpArcsinPiTest_q & fracRPath3_uid106_asinX_uid8_fpArcsinPiTest_q; --reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0(REG,511)@31 reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q <= expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest(ADD,108)@32 expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid108_uid108_asinX_uid8_fpArcsinPiTest_0_to_expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_0_q); expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00000000000000000000000000000000" & VCC_q); expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_b)); expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_o(32 downto 0); --expRPath3_uid111_asinX_uid8_fpArcsinPiTest(BITSELECT,110)@32 expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q(31 downto 0); expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b <= expRPath3_uid111_asinX_uid8_fpArcsinPiTest_in(31 downto 24); --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor(LOGICAL,1124) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q <= not (ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_a or ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_b); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top(CONSTANT,1056) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q <= "01101"; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp(LOGICAL,1057) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_mem_top_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q <= "1" when ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_a = ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_b else "0"; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg(REG,1058) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmp_q; END IF; END IF; END PROCESS; --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena(REG,1125) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_nor_q = "1") THEN ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd(LOGICAL,1126) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b <= en; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_a and ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_b; --yAddr_uid63_asinX_uid8_fpArcsinPiTest(BITSELECT,62)@1 yAddr_uid63_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b; yAddr_uid63_asinX_uid8_fpArcsinPiTest_b <= yAddr_uid63_asinX_uid8_fpArcsinPiTest_in(34 downto 27); --reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0(REG,464)@1 reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q <= yAddr_uid63_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --memoryC2_uid255_arcsinXO2XTabGen_lutmem(DUALMEM,451)@2 memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q; memoryC2_uid255_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 12, widthad_a => 8, numwords_a => 256, width_b => 12, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC2_uid255_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid255_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid255_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC2_uid255_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC2_uid255_arcsinXO2XTabGen_lutmem_ia ); memoryC2_uid255_arcsinXO2XTabGen_lutmem_q <= memoryC2_uid255_arcsinXO2XTabGen_lutmem_iq(11 downto 0); --reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1(REG,466)@4 reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q <= memoryC2_uid255_arcsinXO2XTabGen_lutmem_q; END IF; END IF; END PROCESS; --yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest(BITSELECT,63)@1 yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b(26 downto 0); yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_in(26 downto 9); --yT1_uid256_arcsinXO2XPolyEval(BITSELECT,255)@1 yT1_uid256_arcsinXO2XPolyEval_in <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b; yT1_uid256_arcsinXO2XPolyEval_b <= yT1_uid256_arcsinXO2XPolyEval_in(17 downto 6); --ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg(DELAY,1218) ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 12, depth => 1 ) PORT MAP ( xin => yT1_uid256_arcsinXO2XPolyEval_b, xout => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a(DELAY,992)@1 ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a : dspba_delay GENERIC MAP ( width => 12, depth => 2 ) PORT MAP ( xin => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_inputreg_q, xout => ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0(REG,465)@4 reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q <= ld_yT1_uid256_arcsinXO2XPolyEval_b_to_reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_a_q; END IF; END IF; END PROCESS; --prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval(MULT,415)@5 prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a),13)) * SIGNED(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b); prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_a <= reg_yT1_uid256_arcsinXO2XPolyEval_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_0_q; prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_b <= reg_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_to_prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_1_q; prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_pr,24)); END IF; END IF; END PROCESS; prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q <= prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval(BITSELECT,416)@8 prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in <= prodXY_uid416_pT1_uid257_arcsinXO2XPolyEval_q; prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_in(23 downto 11); --highBBits_uid259_arcsinXO2XPolyEval(BITSELECT,258)@8 highBBits_uid259_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b; highBBits_uid259_arcsinXO2XPolyEval_b <= highBBits_uid259_arcsinXO2XPolyEval_in(12 downto 1); --ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg(DELAY,1219) ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => yAddr_uid63_asinX_uid8_fpArcsinPiTest_b, xout => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a(DELAY,994)@1 ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a : dspba_delay GENERIC MAP ( width => 8, depth => 3 ) PORT MAP ( xin => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_inputreg_q, xout => ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0(REG,467)@5 reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q <= ld_yAddr_uid63_asinX_uid8_fpArcsinPiTest_b_to_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_a_q; END IF; END IF; END PROCESS; --memoryC1_uid254_arcsinXO2XTabGen_lutmem(DUALMEM,450)@6 memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC1_uid254_arcsinXO2XTabGen_lutmem_0_q; memoryC1_uid254_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 19, widthad_a => 8, numwords_a => 256, width_b => 19, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC1_uid254_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid254_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid254_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC1_uid254_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC1_uid254_arcsinXO2XTabGen_lutmem_ia ); memoryC1_uid254_arcsinXO2XTabGen_lutmem_q <= memoryC1_uid254_arcsinXO2XTabGen_lutmem_iq(18 downto 0); --sumAHighB_uid260_arcsinXO2XPolyEval(ADD,259)@8 sumAHighB_uid260_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((19 downto 19 => memoryC1_uid254_arcsinXO2XTabGen_lutmem_q(18)) & memoryC1_uid254_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid260_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((19 downto 12 => highBBits_uid259_arcsinXO2XPolyEval_b(11)) & highBBits_uid259_arcsinXO2XPolyEval_b); sumAHighB_uid260_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid260_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid260_arcsinXO2XPolyEval_b)); sumAHighB_uid260_arcsinXO2XPolyEval_q <= sumAHighB_uid260_arcsinXO2XPolyEval_o(19 downto 0); --lowRangeB_uid258_arcsinXO2XPolyEval(BITSELECT,257)@8 lowRangeB_uid258_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid417_pT1_uid257_arcsinXO2XPolyEval_b(0 downto 0); lowRangeB_uid258_arcsinXO2XPolyEval_b <= lowRangeB_uid258_arcsinXO2XPolyEval_in(0 downto 0); --s1_uid258_uid261_arcsinXO2XPolyEval(BITJOIN,260)@8 s1_uid258_uid261_arcsinXO2XPolyEval_q <= sumAHighB_uid260_arcsinXO2XPolyEval_q & lowRangeB_uid258_arcsinXO2XPolyEval_b; --reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1(REG,469)@8 reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q <= "000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q <= s1_uid258_uid261_arcsinXO2XPolyEval_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor(LOGICAL,1188) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q <= not (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_a or ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_b); --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena(REG,1189) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_nor_q = "1") THEN ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd(LOGICAL,1190) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_sticky_ena_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b <= en; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_a and ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_b; --reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0(REG,468)@1 reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q <= "000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q <= yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem(DUALMEM,1179) ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0 <= areset; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia <= reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 18, widthad_a => 3, numwords_a => 6, width_b => 18, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq, address_a => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_aa, data_a => ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_ia ); ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_iq(17 downto 0); --prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval(MULT,418)@9 prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a),19)) * SIGNED(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b); prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a <= (others => '0'); prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b <= (others => '0'); prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_mem_q; prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_b <= reg_s1_uid258_uid261_arcsinXO2XPolyEval_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_1_q; prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_pr,39)); END IF; END IF; END PROCESS; prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q <= prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval(BITSELECT,419)@12 prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in <= prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_q; prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_in(38 downto 17); --highBBits_uid265_arcsinXO2XPolyEval(BITSELECT,264)@12 highBBits_uid265_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b; highBBits_uid265_arcsinXO2XPolyEval_b <= highBBits_uid265_arcsinXO2XPolyEval_in(21 downto 2); --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor(LOGICAL,1213) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q <= not (ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_a or ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_b); --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena(REG,1214) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_nor_q = "1") THEN ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd(LOGICAL,1215) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_sticky_ena_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b <= en; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_a and ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_b; --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem(DUALMEM,1204) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia <= reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC2_uid255_arcsinXO2XTabGen_lutmem_0_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdreg_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab <= ld_reg_yPPolyEval_uid64_asinX_uid8_fpArcsinPiTest_0_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_0_q_to_prodXY_uid419_pT2_uid263_arcsinXO2XPolyEval_a_replace_rdmux_q; ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 3, numwords_a => 6, width_b => 8, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_ia ); ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_iq(7 downto 0); --ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg(DELAY,1203) ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_replace_mem_q, xout => ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC0_uid253_arcsinXO2XTabGen_lutmem(DUALMEM,449)@10 memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0 <= areset; memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia <= (others => '0'); memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa <= (others => '0'); memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab <= ld_reg_yAddr_uid63_asinX_uid8_fpArcsinPiTest_0_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_0_q_to_memoryC0_uid253_arcsinXO2XTabGen_lutmem_a_outputreg_q; memoryC0_uid253_arcsinXO2XTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 30, widthad_a => 8, numwords_a => 256, width_b => 30, widthad_b => 8, numwords_b => 256, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_arcsinpi_s5_memoryC0_uid253_arcsinXO2XTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid253_arcsinXO2XTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid253_arcsinXO2XTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq, address_a => memoryC0_uid253_arcsinXO2XTabGen_lutmem_aa, data_a => memoryC0_uid253_arcsinXO2XTabGen_lutmem_ia ); memoryC0_uid253_arcsinXO2XTabGen_lutmem_q <= memoryC0_uid253_arcsinXO2XTabGen_lutmem_iq(29 downto 0); --sumAHighB_uid266_arcsinXO2XPolyEval(ADD,265)@12 sumAHighB_uid266_arcsinXO2XPolyEval_a <= STD_LOGIC_VECTOR((30 downto 30 => memoryC0_uid253_arcsinXO2XTabGen_lutmem_q(29)) & memoryC0_uid253_arcsinXO2XTabGen_lutmem_q); sumAHighB_uid266_arcsinXO2XPolyEval_b <= STD_LOGIC_VECTOR((30 downto 20 => highBBits_uid265_arcsinXO2XPolyEval_b(19)) & highBBits_uid265_arcsinXO2XPolyEval_b); sumAHighB_uid266_arcsinXO2XPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid266_arcsinXO2XPolyEval_a) + SIGNED(sumAHighB_uid266_arcsinXO2XPolyEval_b)); sumAHighB_uid266_arcsinXO2XPolyEval_q <= sumAHighB_uid266_arcsinXO2XPolyEval_o(30 downto 0); --lowRangeB_uid264_arcsinXO2XPolyEval(BITSELECT,263)@12 lowRangeB_uid264_arcsinXO2XPolyEval_in <= prodXYTruncFR_uid420_pT2_uid263_arcsinXO2XPolyEval_b(1 downto 0); lowRangeB_uid264_arcsinXO2XPolyEval_b <= lowRangeB_uid264_arcsinXO2XPolyEval_in(1 downto 0); --s2_uid264_uid267_arcsinXO2XPolyEval(BITJOIN,266)@12 s2_uid264_uid267_arcsinXO2XPolyEval_q <= sumAHighB_uid266_arcsinXO2XPolyEval_q & lowRangeB_uid264_arcsinXO2XPolyEval_b; --fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest(BITSELECT,65)@12 fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in <= s2_uid264_uid267_arcsinXO2XPolyEval_q(30 downto 0); fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b <= fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_in(30 downto 5); --reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1(REG,472)@12 reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q <= fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor(LOGICAL,1229) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q <= not (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_a or ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_b); --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top(CONSTANT,1225) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q <= "01010"; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp(LOGICAL,1226) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_mem_top_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q); ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q <= "1" when ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_a = ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_b else "0"; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg(REG,1227) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena(REG,1230) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_nor_q = "1") THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd(LOGICAL,1231) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_sticky_ena_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b <= en; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_a and ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_b; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt(COUNTER,1221) -- every=1, low=0, high=10, step=1, init=1 ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i = 9 THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '1'; ELSE ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_eq = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i - 10; ELSE ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_i,4)); --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg(REG,1222) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux(MUX,1223) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s <= en; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux: PROCESS (ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s, ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q, ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q) BEGIN CASE ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_s IS WHEN "0" => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q; WHEN "1" => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdcnt_q; WHEN OTHERS => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem(DUALMEM,1220) ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0 <= areset; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia <= oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdreg_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_rdmux_q; ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 24, widthad_a => 4, numwords_a => 11, width_b => 24, widthad_b => 4, numwords_b => 11, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq, address_a => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_aa, data_a => ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_ia ); ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_iq(23 downto 0); --reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0(REG,471)@12 reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q <= "000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q <= ld_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_q_to_reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_a_replace_mem_q; END IF; END IF; END PROCESS; --mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest(MULT,66)@13 mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr <= UNSIGNED(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a) * UNSIGNED(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b); mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a <= (others => '0'); mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b <= (others => '0'); mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_a <= reg_oFracX_uid49_uid49_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_0_q; mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_b <= reg_fxpArcSinXO2XRes_uid66_asinX_uid8_fpArcsinPiTest_0_to_mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_1_q; mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1 <= STD_LOGIC_VECTOR(mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_pr); END IF; END IF; END PROCESS; mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_s1; END IF; END IF; END PROCESS; --normBitPath2_uid68_asinX_uid8_fpArcsinPiTest(BITSELECT,67)@16 normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q; normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_in(49 downto 49); --add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest(BITJOIN,72)@16 add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b & cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q & VCC_q; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor(LOGICAL,1060) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q <= not (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_a or ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_b); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena(REG,1061) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_nor_q = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd(LOGICAL,1062) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_a and ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_b; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem(DUALMEM,1051) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0 <= areset; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 14, width_b => 8, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq, address_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_aa, data_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_ia ); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_iq(7 downto 0); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg(DELAY,1050) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_mem_q, xout => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest(BITSELECT,68)@16 fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q(48 downto 0); fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b <= fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_in(48 downto 25); --fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest(BITSELECT,69)@16 fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in <= mul2XArcsinXO2XRes_uid67_asinX_uid8_fpArcsinPiTest_q(47 downto 0); fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b <= fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_in(47 downto 24); --fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest(MUX,70)@16 fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s <= normBitPath2_uid68_asinX_uid8_fpArcsinPiTest_b; fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s, en, fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b, fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b) BEGIN CASE fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_s IS WHEN "0" => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= fracRPath2Low_uid70_asinX_uid8_fpArcsinPiTest_b; WHEN "1" => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= fracRPath2High_uid69_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest(BITJOIN,73)@16 expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_outputreg_q & fracRPath2Pre_uid71_asinX_uid8_fpArcsinPiTest_q; --expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest(ADD,74)@16 expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_q); expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00000000" & add_normUpdate_uid72_fracRPath2PreUlp_uid72_uid72_uid73_asinX_uid8_fpArcsinPiTest_q); expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_a) + UNSIGNED(expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_b)); expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_o(32 downto 0); --expRPath2_uid77_asinX_uid8_fpArcsinPiTest(BITSELECT,76)@16 expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q(31 downto 0); expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b <= expRPath2_uid77_asinX_uid8_fpArcsinPiTest_in(31 downto 24); --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg(DELAY,1114) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b, xout => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt(COUNTER,1052) -- every=1, low=0, high=13, step=1, init=1 ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i = 12 THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_eq = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i - 13; ELSE ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_i,4)); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg(REG,1053) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux(MUX,1054) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux: PROCESS (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s, ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q, ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q) BEGIN CASE ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_s IS WHEN "0" => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; WHEN "1" => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem(DUALMEM,1115) ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 <= areset; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_inputreg_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 14, width_b => 8, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0, clock1 => clk, address_b => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq, address_a => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa, data_a => ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia ); ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq(7 downto 0); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor(LOGICAL,1111) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q <= not (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_a or ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_b); --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena(REG,1112) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_nor_q = "1") THEN ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd(LOGICAL,1113) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b <= en; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_a and ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_b; --ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem(DUALMEM,1102) ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 <= areset; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia <= expX_uid15_asinX_uid8_fpArcsinPiTest_b; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q; ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 5, numwords_a => 31, width_b => 8, widthad_b => 5, numwords_b => 31, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq, address_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa, data_a => ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia ); ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq(7 downto 0); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor(LOGICAL,1074) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q <= not (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_a or ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_b); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top(CONSTANT,1070) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q <= "011100"; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp(LOGICAL,1071) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_mem_top_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q); ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q <= "1" when ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_a = ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_b else "0"; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg(REG,1072) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmp_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena(REG,1075) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_nor_q = "1") THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd(LOGICAL,1076) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b <= en; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_a and ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_b; --arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest(BITSELECT,57)@1 arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in <= leftShiftStage1_uid251_fxpX_uid57_asinX_uid8_fpArcsinPiTest_q; arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b <= arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_in(36 downto 36); --biasMwShift_uid50_asinX_uid8_fpArcsinPiTest(CONSTANT,49) biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q <= "01110011"; --arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest(COMPARE,50)@0 arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin <= GND_q; arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("00" & biasMwShift_uid50_asinX_uid8_fpArcsinPiTest_q) & '0'; arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("00" & expX_uid15_asinX_uid8_fpArcsinPiTest_b) & arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_cin(0); arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_a) - UNSIGNED(arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_b)); END IF; END IF; END PROCESS; arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n(0) <= not arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_o(10); --Y34_uid60_asinX_uid8_fpArcsinPiTest(BITSELECT,59)@1 Y34_uid60_asinX_uid8_fpArcsinPiTest_in <= y_uid59_asinX_uid8_fpArcsinPiTest_b; Y34_uid60_asinX_uid8_fpArcsinPiTest_b <= Y34_uid60_asinX_uid8_fpArcsinPiTest_in(34 downto 34); --path2_uid61_asinX_uid8_fpArcsinPiTest(LOGICAL,60)@1 path2_uid61_asinX_uid8_fpArcsinPiTest_a <= Y34_uid60_asinX_uid8_fpArcsinPiTest_b; path2_uid61_asinX_uid8_fpArcsinPiTest_q <= not path2_uid61_asinX_uid8_fpArcsinPiTest_a; --pathSelBits_uid112_asinX_uid8_fpArcsinPiTest(BITJOIN,111)@1 pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q <= arcsinIsMax_uid58_asinX_uid8_fpArcsinPiTest_b & arcsinXIsX_uid51_asinX_uid8_fpArcsinPiTest_n & path2_uid61_asinX_uid8_fpArcsinPiTest_q; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1064) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q, xout => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt(COUNTER,1066) -- every=1, low=0, high=28, step=1, init=1 ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i = 27 THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '1'; ELSE ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_eq = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i - 28; ELSE ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_i,5)); --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg(REG,1067) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux(MUX,1068) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s <= en; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux: PROCESS (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s, ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q, ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q) BEGIN CASE ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_s IS WHEN "0" => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; WHEN "1" => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdcnt_q; WHEN OTHERS => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem(DUALMEM,1065) ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 <= areset; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_inputreg_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q; ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 5, numwords_a => 29, width_b => 3, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq, address_a => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa, data_a => ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia ); ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq(2 downto 0); --fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest(LOOKUP,112)@32 fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest: PROCESS (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q) BEGIN -- Begin reserved scope level CASE (ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_mem_q) IS WHEN "000" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "001" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "010" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "011" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "100" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "101" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "110" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "111" => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN OTHERS => fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRCalc_uid117_asinX_uid8_fpArcsinPiTest(MUX,116)@32 expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s <= fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q; expRCalc_uid117_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE expRCalc_uid117_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= cstBias_uid22_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_d_replace_mem_q; WHEN "10" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= ld_expRPath2_uid77_asinX_uid8_fpArcsinPiTest_b_to_expRCalc_uid117_asinX_uid8_fpArcsinPiTest_e_replace_mem_q; WHEN "11" => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= expRPath3_uid111_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor(LOGICAL,1150) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q <= not (ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_a or ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_b); --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena(REG,1151) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_nor_q = "1") THEN ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd(LOGICAL,1152) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_sticky_ena_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b <= en; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_a and ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_b; --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg(DELAY,1140) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q, xout => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem(DUALMEM,1141) ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0 <= areset; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_inputreg_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q; ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 29, width_b => 1, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_reset0, clock1 => clk, address_b => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq, address_a => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_aa, data_a => ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_ia ); ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_iq(0 downto 0); --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor(LOGICAL,1137) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q <= not (ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_a or ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_b); --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena(REG,1138) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_nor_q = "1") THEN ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd(LOGICAL,1139) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_sticky_ena_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b <= en; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_a and ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_b; --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg(DELAY,1127) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q, xout => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem(DUALMEM,1128) ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0 <= areset; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_inputreg_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdreg_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab <= ld_pathSelBits_uid112_asinX_uid8_fpArcsinPiTest_q_to_fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_a_replace_rdmux_q; ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 1, widthad_a => 5, numwords_a => 29, width_b => 1, widthad_b => 5, numwords_b => 29, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq, address_a => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_aa, data_a => ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_ia ); ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q <= ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_iq(0 downto 0); --excSelBits_uid120_asinX_uid8_fpArcsinPiTest(BITJOIN,119)@31 excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q <= ld_excRNaN_uid119_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_c_replace_mem_q & GND_q & ld_expXIsZero_uid31_asinX_uid8_fpArcsinPiTest_q_to_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_a_replace_mem_q; --reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0(REG,458)@31 reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q <= excSelBits_uid120_asinX_uid8_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest(LOOKUP,120)@32 outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (reg_excSelBits_uid120_asinX_uid8_fpArcsinPiTest_0_to_outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_0_q) IS WHEN "000" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "001" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "00"; WHEN "010" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "10"; WHEN "011" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "100" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "11"; WHEN "101" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "110" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN "111" => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= "01"; WHEN OTHERS => outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q <= (others => '-'); END CASE; END IF; END PROCESS; --expRPostExc_uid123_asinX_uid8_fpArcsinPiTest(MUX,122)@33 expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s <= outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q; expRPostExc_uid123_asinX_uid8_fpArcsinPiTest: PROCESS (expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= expRCalc_uid117_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPath3_uid110_asinX_uid8_fpArcsinPiTest(BITSELECT,109)@32 fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid109_asinX_uid8_fpArcsinPiTest_q(23 downto 0); fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b <= fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_in(23 downto 1); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor(LOGICAL,1099) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q <= not (ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_a or ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_b); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena(REG,1100) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_nor_q = "1") THEN ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd(LOGICAL,1101) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_sticky_ena_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b <= en; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_a and ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_b; --fracRPath2_uid76_asinX_uid8_fpArcsinPiTest(BITSELECT,75)@16 fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in <= expFracRPath2PostRnd_uid75_asinX_uid8_fpArcsinPiTest_q(23 downto 0); fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b <= fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_in(23 downto 1); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg(DELAY,1089) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b, xout => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem(DUALMEM,1090) ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0 <= areset; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_inputreg_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdreg_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_replace_rdmux_q; ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 4, numwords_a => 14, width_b => 23, widthad_b => 4, numwords_b => 14, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_reset0, clock1 => clk, address_b => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq, address_a => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_aa, data_a => ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_ia ); ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_iq(22 downto 0); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor(LOGICAL,1086) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a <= ld_expX_uid15_asinX_uid8_fpArcsinPiTest_b_to_expFracConc_uid74_uid74_asinX_uid8_fpArcsinPiTest_b_notEnable_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q <= not (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_a or ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_b); --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena(REG,1087) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_nor_q = "1") THEN ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_cmpReg_q; END IF; END IF; END PROCESS; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd(LOGICAL,1088) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_sticky_ena_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b <= en; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_a and ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_b; --ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem(DUALMEM,1077) ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0 <= areset; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia <= fracX_uid16_asinX_uid8_fpArcsinPiTest_b; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdreg_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_rdmux_q; ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 23, widthad_a => 5, numwords_a => 31, width_b => 23, widthad_b => 5, numwords_b => 31, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_reset0, clock1 => clk, address_b => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq, address_a => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_aa, data_a => ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_ia ); ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_iq(22 downto 0); --piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest(BITSELECT,113)@32 piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in <= piO2_uid101_asinX_uid8_fpArcsinPiTest_q(26 downto 0); piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b <= piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_in(26 downto 4); --fracRCalc_uid115_asinX_uid8_fpArcsinPiTest(MUX,114)@32 fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s <= fracOutMuxSelEnc_uid113_asinX_uid8_fpArcsinPiTest_q; fracRCalc_uid115_asinX_uid8_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= piO2OutRange_uid114_asinX_uid8_fpArcsinPiTest_b; WHEN "01" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= ld_fracX_uid16_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_d_replace_mem_q; WHEN "10" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= ld_fracRPath2_uid76_asinX_uid8_fpArcsinPiTest_b_to_fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_e_replace_mem_q; WHEN "11" => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= fracRPath3_uid110_asinX_uid8_fpArcsinPiTest_b; WHEN OTHERS => fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest(MUX,121)@33 fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s <= outMuxSelEnc_uid121_asinX_uid8_fpArcsinPiTest_q; fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest: PROCESS (fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_s IS WHEN "00" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= fracRCalc_uid115_asinX_uid8_fpArcsinPiTest_q; WHEN "10" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid126_asinX_uid8_fpArcsinPiTest(BITJOIN,125)@33 R_uid126_asinX_uid8_fpArcsinPiTest_q <= ld_signR_uid125_asinX_uid8_fpArcsinPiTest_q_to_R_uid126_asinX_uid8_fpArcsinPiTest_c_replace_mem_q & expRPostExc_uid123_asinX_uid8_fpArcsinPiTest_q & fracRPostExc_uid122_asinX_uid8_fpArcsinPiTest_q; --fracX_uid132_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,131)@33 fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q(22 downto 0); fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b <= fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 0); --fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,143)@33 fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a <= fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b; fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_a = fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --expX_uid128_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,127)@33 expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q(30 downto 0); expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_in(30 downto 23); --expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,141)@33 expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b; expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_a = expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,144)@33 exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b <= fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_a and exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_b; --ooPi_uid9_fpArcsinPiTest(CONSTANT,8) ooPi_uid9_fpArcsinPiTest_q <= "101000101111100110000011"; --fracOOPi_uid10_fpArcsinPiTest(BITSELECT,9)@33 fracOOPi_uid10_fpArcsinPiTest_in <= ooPi_uid9_fpArcsinPiTest_q(22 downto 0); fracOOPi_uid10_fpArcsinPiTest_b <= fracOOPi_uid10_fpArcsinPiTest_in(22 downto 0); --fpOOPi_uid11_fpArcsinPiTest(BITJOIN,10)@33 fpOOPi_uid11_fpArcsinPiTest_q <= GND_q & cstBiasM2_uid6_fpArcsinPiTest_q & fracOOPi_uid10_fpArcsinPiTest_b; --expY_uid129_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,128)@33 expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q(30 downto 0); expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_in(30 downto 23); --expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,155)@33 expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b; expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_a = expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,209)@33 excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q <= excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_a and excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_b; --fracY_uid134_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,133)@33 fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q(22 downto 0); fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b <= fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 0); --fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,159)@33 fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a <= fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b; fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_a = fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,157)@33 expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a <= expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b; expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_a = expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,160)@33 exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b <= fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q; exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_a and exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_b; --expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,139)@33 expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a <= expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b; expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_a = expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,210)@33 excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_b; --ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,211)@33 ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a <= excXZAndExcYI_uid211_rAsinPi_uid13_fpArcsinPiTest_q; ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b <= excYZAndExcXI_uid210_rAsinPi_uid13_fpArcsinPiTest_q; ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q <= ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_a or ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_b; END IF; END PROCESS; --InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,161)@33 InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a <= fracXIsZero_uid160_rAsinPi_uid13_fpArcsinPiTest_q; InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q <= not InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_a; --exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,162)@33 exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid158_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b <= InvFracXIsZero_uid162_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q <= exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_a and exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_b; --ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,742)@33 ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,145)@33 InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a <= fracXIsZero_uid144_rAsinPi_uid13_fpArcsinPiTest_q; InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q <= not InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_a; --exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,146)@33 exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsMax_uid142_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b <= InvFracXIsZero_uid146_rAsinPi_uid13_fpArcsinPiTest_q; exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_a and exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_b; --reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1(REG,519)@33 reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,212)@34 excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a <= reg_exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_0_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_1_q; excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q_to_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b_q; excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c <= ZeroTimesInf_uid212_rAsinPi_uid13_fpArcsinPiTest_q; excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q <= excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_a or excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_b or excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_c; --VCC(CONSTANT,1) VCC_q <= "1"; --InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,224)@34 InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a <= excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q; InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_a; --signY_uid131_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,130)@33 signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in <= fpOOPi_uid11_fpArcsinPiTest_q; signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b <= signY_uid131_rAsinPi_uid13_fpArcsinPiTest_in(31 downto 31); --signX_uid130_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,129)@33 signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in <= R_uid126_asinX_uid8_fpArcsinPiTest_q; signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b <= signX_uid130_rAsinPi_uid13_fpArcsinPiTest_in(31 downto 31); --signR_uid196_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,195)@33 signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a <= signX_uid130_rAsinPi_uid13_fpArcsinPiTest_b; signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b <= signY_uid131_rAsinPi_uid13_fpArcsinPiTest_b; signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q <= signR_uid196_rAsinPi_uid13_fpArcsinPiTest_a xor signR_uid196_rAsinPi_uid13_fpArcsinPiTest_b; --ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,753)@33 ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,225)@34 signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a <= ld_signR_uid196_rAsinPi_uid13_fpArcsinPiTest_q_to_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a_q; signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b <= InvExcRNaN_uid225_rAsinPi_uid13_fpArcsinPiTest_q; signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q <= signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_a and signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_b; --ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,757)@34 ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,134)@33 add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q <= VCC_q & fracY_uid134_rAsinPi_uid13_fpArcsinPiTest_b; --add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,132)@33 add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q <= VCC_q & fracX_uid132_rAsinPi_uid13_fpArcsinPiTest_b; --prod_uid171_rAsinPi_uid13_fpArcsinPiTest(MULT,170)@33 prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr <= UNSIGNED(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a) * UNSIGNED(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b); prod_uid171_rAsinPi_uid13_fpArcsinPiTest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a <= (others => '0'); prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b <= (others => '0'); prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_a <= add_one_fracX_uid132_uid133_uid133_rAsinPi_uid13_fpArcsinPiTest_q; prod_uid171_rAsinPi_uid13_fpArcsinPiTest_b <= add_one_fracY_uid134_uid135_uid135_rAsinPi_uid13_fpArcsinPiTest_q; prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1 <= STD_LOGIC_VECTOR(prod_uid171_rAsinPi_uid13_fpArcsinPiTest_pr); END IF; END IF; END PROCESS; prod_uid171_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_s1; END IF; END IF; END PROCESS; --normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,171)@36 normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q; normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_in(47 downto 47); --fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,173)@36 fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(46 downto 0); fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_in(46 downto 23); --fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,174)@36 fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(45 downto 0); fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_in(45 downto 22); --fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest(MUX,175)@36 fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b; fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest: PROCESS (fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s, en, fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b, fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b) BEGIN CASE fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "0" => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= fracRPostNormLow_uid175_rAsinPi_uid13_fpArcsinPiTest_b; WHEN "1" => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= fracRPostNormHigh_uid174_rAsinPi_uid13_fpArcsinPiTest_b; WHEN OTHERS => fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,183)@36 FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in <= fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q(1 downto 0); FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b <= FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_in(1 downto 0); --Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,177)@36 Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(22 downto 0); Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b <= Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_in(22 downto 22); --extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest(MUX,178)@36 extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s <= normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b; extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest: PROCESS (extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s, en, GND_q, Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b) BEGIN CASE extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "0" => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= GND_q; WHEN "1" => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= Prod22_uid178_rAsinPi_uid13_fpArcsinPiTest_b; WHEN OTHERS => extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,176)@36 stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in <= prod_uid171_rAsinPi_uid13_fpArcsinPiTest_q(21 downto 0); stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b <= stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_in(21 downto 0); --stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,179)@36 stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q <= extraStickyBit_uid179_rAsinPi_uid13_fpArcsinPiTest_q & stickyRange_uid177_rAsinPi_uid13_fpArcsinPiTest_b; --stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,181)@36 stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a <= stickyExtendedRange_uid180_rAsinPi_uid13_fpArcsinPiTest_q; stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_a = stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --sticky_uid183_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,182)@36 sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a <= stickyRangeComparator_uid182_rAsinPi_uid13_fpArcsinPiTest_q; sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q <= not sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_a; --lrs_uid185_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,184)@36 lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q <= FracRPostNorm1dto0_uid184_rAsinPi_uid13_fpArcsinPiTest_b & sticky_uid183_rAsinPi_uid13_fpArcsinPiTest_q; --roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,186)@36 roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a <= lrs_uid185_rAsinPi_uid13_fpArcsinPiTest_q; roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b <= roundBitDetectionConstant_uid186_rAsinPi_uid13_fpArcsinPiTest_q; roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q <= "1" when roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_a = roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_b else "0"; --roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,187)@36 roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a <= roundBitDetectionPattern_uid187_rAsinPi_uid13_fpArcsinPiTest_q; roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q <= not roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_a; --roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,190)@36 roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q <= GND_q & normalizeBit_uid172_rAsinPi_uid13_fpArcsinPiTest_b & cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q & roundBit_uid188_rAsinPi_uid13_fpArcsinPiTest_q; --reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1(REG,514)@36 reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q <= roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest(CONSTANT,168) biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q <= "0001111111"; --expSum_uid168_rAsinPi_uid13_fpArcsinPiTest(ADD,167)@33 expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR("0" & expX_uid128_rAsinPi_uid13_fpArcsinPiTest_b); expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR("0" & expY_uid129_rAsinPi_uid13_fpArcsinPiTest_b); expSum_uid168_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(UNSIGNED(expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_a) + UNSIGNED(expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_b)); END IF; END IF; END PROCESS; expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q <= expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_o(8 downto 0); --ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,674)@34 ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest(SUB,169)@35 expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR('0' & "00" & ld_expSum_uid168_rAsinPi_uid13_fpArcsinPiTest_q_to_expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a_q); expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR((11 downto 10 => biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q(9)) & biasInc_uid169_rAsinPi_uid13_fpArcsinPiTest_q); expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_b)); END IF; END IF; END PROCESS; expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q <= expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_o(10 downto 0); --expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,188)@36 expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q <= expSumMBias_uid170_rAsinPi_uid13_fpArcsinPiTest_q & fracRPostNorm_uid176_rAsinPi_uid13_fpArcsinPiTest_q; --reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0(REG,513)@36 reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q <= "00000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q <= expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest(ADD,191)@37 expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR((36 downto 35 => reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q(34)) & reg_expFracPreRound_uid189_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_0_q); expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR('0' & "0000000000" & reg_roundBitAndNormalizationOp_uid191_rAsinPi_uid13_fpArcsinPiTest_0_to_expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_1_q); expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_a) + SIGNED(expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_b)); expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_o(35 downto 0); --expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,193)@37 expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q; expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_in(35 downto 24); --expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,194)@37 expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b(7 downto 0); expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b <= expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_in(7 downto 0); --ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a(DELAY,1049)@37 ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a : dspba_delay GENERIC MAP ( width => 8, depth => 1 ) PORT MAP ( xin => expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b, xout => ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3(REG,522)@38 reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q <= "00000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q <= ld_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_a_q; END IF; END IF; END PROCESS; --ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,746)@34 ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1(REG,515)@37 reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q <= "000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q <= expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_b; END IF; END IF; END PROCESS; --expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest(COMPARE,198)@38 expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin <= GND_q; expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q(11)) & reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q) & '0'; expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR('0' & "00000" & cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) & expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_cin(0); expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_b)); expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n(0) <= not expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_o(14); --InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,163)@33 InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a <= exc_N_uid163_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_a; --InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,164)@33 InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_a; --InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,165)@33 InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_a; --exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,166)@33 exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a <= InvExpXIsZero_uid166_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b <= InvExc_I_uid165_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c <= InvExc_N_uid164_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_a and exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_b and exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_c; --ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,716)@33 ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,147)@33 InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a <= exc_N_uid147_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_a; --InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,148)@33 InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_a; --InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,149)@33 InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q <= not InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_a; --exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,150)@33 exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a <= InvExpXIsZero_uid150_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b <= InvExc_I_uid149_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c <= InvExc_N_uid148_rAsinPi_uid13_fpArcsinPiTest_q; exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_a and exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_b and exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_c; --ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a(DELAY,1045)@33 ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1(REG,518)@37 reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q <= ld_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q_to_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_a_q; END IF; END IF; END PROCESS; --ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,207)@38 ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a <= reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_1_q; ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q; ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c <= expOvf_uid199_rAsinPi_uid13_fpArcsinPiTest_n; ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q <= ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_a and ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_b and ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_c; --excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,206)@33 excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q; excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q <= excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_a and excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,733)@33 ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,205)@33 excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q; excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q <= excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_a and excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,732)@33 ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,204)@33 excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a <= exc_I_uid145_rAsinPi_uid13_fpArcsinPiTest_q; excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b <= exc_I_uid161_rAsinPi_uid13_fpArcsinPiTest_q; excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q <= excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_a and excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,731)@33 ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,208)@38 excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a <= ld_excXIAndExcYI_uid205_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b <= ld_excXRAndExcYI_uid206_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c <= ld_excYRAndExcXI_uid207_rAsinPi_uid13_fpArcsinPiTest_q_to_excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d <= ExcROvfAndInReg_uid208_rAsinPi_uid13_fpArcsinPiTest_q; excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q <= excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_a or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_b or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_c or excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_d; --expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest(COMPARE,196)@38 expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin <= GND_q; expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a <= STD_LOGIC_VECTOR('0' & "000000000000" & GND_q) & '0'; expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b <= STD_LOGIC_VECTOR((13 downto 12 => reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q(11)) & reg_expRPreExcExt_uid194_rAsinPi_uid13_fpArcsinPiTest_0_to_expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_1_q) & expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_cin(0); expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o <= STD_LOGIC_VECTOR(SIGNED(expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_a) - SIGNED(expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_b)); expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n(0) <= not expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_o(14); --reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1(REG,516)@33 reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,715)@34 ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 4 ) PORT MAP ( xin => reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q, xout => ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,202)@38 excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a <= ld_reg_exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_0_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_1_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a_q; excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b <= ld_exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q_to_excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b_q; excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c <= expUdf_uid197_rAsinPi_uid13_fpArcsinPiTest_n; excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q <= excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_a and excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_b and excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_c; --excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,201)@33 excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b <= exc_R_uid151_rAsinPi_uid13_fpArcsinPiTest_q; excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q <= excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_a and excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c(DELAY,720)@33 ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,200)@33 excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b <= exc_R_uid167_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b(DELAY,719)@33 ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q, ena => en(0), clk => clk, aclr => areset ); --excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,199)@33 excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a <= expXIsZero_uid140_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b <= expXIsZero_uid156_rAsinPi_uid13_fpArcsinPiTest_q; excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q <= excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_a and excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_b; --ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a(DELAY,718)@33 ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q, xout => ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q, ena => en(0), clk => clk, aclr => areset ); --excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest(LOGICAL,203)@38 excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a <= ld_excXZAndExcYZ_uid200_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b <= ld_excXZAndExcYR_uid201_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c <= ld_excYZAndExcXR_uid202_rAsinPi_uid13_fpArcsinPiTest_q_to_excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d <= excZC3_uid203_rAsinPi_uid13_fpArcsinPiTest_q; excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q <= excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_a or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_b or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_c or excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_d; --concExc_uid214_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,213)@38 concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q <= ld_excRNaN_uid213_rAsinPi_uid13_fpArcsinPiTest_q_to_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_c_q & excRInf_uid209_rAsinPi_uid13_fpArcsinPiTest_q & excRZero_uid204_rAsinPi_uid13_fpArcsinPiTest_q; --reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0(REG,520)@38 reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q <= concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_q; END IF; END IF; END PROCESS; --excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest(LOOKUP,214)@39 excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest: PROCESS (reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid214_rAsinPi_uid13_fpArcsinPiTest_0_to_excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_0_q) IS WHEN "000" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "01"; WHEN "001" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "010" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "10"; WHEN "011" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "100" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "11"; WHEN "101" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "110" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN "111" => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= "00"; WHEN OTHERS => excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest(MUX,223)@39 expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s <= excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q; expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest: PROCESS (expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s, en, cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q, reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q, cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "00" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWE_uid21_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= reg_expRPreExc_uid195_rAsinPi_uid13_fpArcsinPiTest_0_to_expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_3_q; WHEN "10" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllOWE_uid18_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest(BITSELECT,192)@37 fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in <= expFracRPostRounding_uid192_rAsinPi_uid13_fpArcsinPiTest_q(23 downto 0); fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b <= fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_in(23 downto 1); --ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a(DELAY,1048)@37 ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b, xout => ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q, ena => en(0), clk => clk, aclr => areset ); --reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3(REG,521)@38 reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q <= ld_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_b_to_reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_a_q; END IF; END IF; END PROCESS; --fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest(MUX,218)@39 fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s <= excREnc_uid215_rAsinPi_uid13_fpArcsinPiTest_q; fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest: PROCESS (fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s, en, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q, cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q, cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q) BEGIN CASE fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_s IS WHEN "00" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "01" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= reg_fracRPreExc_uid193_rAsinPi_uid13_fpArcsinPiTest_0_to_fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_3_q; WHEN "10" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstAllZWF_uid19_asinX_uid8_fpArcsinPiTest_q; WHEN "11" => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= cstNaNWF_uid20_asinX_uid8_fpArcsinPiTest_q; WHEN OTHERS => fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q <= (others => '0'); END CASE; END PROCESS; --R_uid227_rAsinPi_uid13_fpArcsinPiTest(BITJOIN,226)@39 R_uid227_rAsinPi_uid13_fpArcsinPiTest_q <= ld_signRPostExc_uid226_rAsinPi_uid13_fpArcsinPiTest_q_to_R_uid227_rAsinPi_uid13_fpArcsinPiTest_c_q & expRPostExc_uid224_rAsinPi_uid13_fpArcsinPiTest_q & fracRPostExc_uid219_rAsinPi_uid13_fpArcsinPiTest_q; --xOut(GPOUT,4)@39 q <= R_uid227_rAsinPi_uid13_fpArcsinPiTest_q; end normal;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_castytol.vhd

10

6849

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_CASTYTOL.VHD *** --*** *** --*** Function: Cast Internal Double Format to *** --*** Long *** --*** *** --*** 13/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_castytol IS GENERIC (normspeed : positive := 2); -- 1,2 pipes for conversion PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aazip, aasat : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); END hcc_castytol; ARCHITECTURE rtl OF hcc_castytol IS signal leftshiftnum, rightshiftnum : STD_LOGIC_VECTOR (13 DOWNTO 1); signal midpoint, maxpoint, minpoint : STD_LOGIC_VECTOR (13 DOWNTO 1); signal leftshiftmax, rightshiftmin : STD_LOGIC_VECTOR (13 DOWNTO 1); signal leftshiftbus, rightshiftbus : STD_LOGIC_VECTOR (64 DOWNTO 1); signal selectleftbit, selectleftbitdel : STD_LOGIC; signal satshiftbit, satshiftout : STD_LOGIC; signal zipshiftbit, zipshiftout : STD_LOGIC; signal satout, zipout : STD_LOGIC; signal leftshiftbusff, rightshiftbusff : STD_LOGIC_VECTOR (32 DOWNTO 1); signal shiftmuxff : STD_LOGIC_VECTOR (32 DOWNTO 1); component hcc_delaybit IS GENERIC (delay : positive := 32); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC; cc : OUT STD_LOGIC ); end component; component hcc_lsftcomb64 PORT ( inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; component hcc_lsftpipe64 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; component hcc_rsftpipe64 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; component hcc_rsftcomb64 PORT ( inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; BEGIN midpoint <= conv_std_logic_vector (1054,13); maxpoint <= conv_std_logic_vector (1118,13); minpoint <= conv_std_logic_vector (1022,13); leftshiftnum <= aa(13 DOWNTO 1) - midpoint; -- 1054 is 1.0 point rightshiftnum <= midpoint - aa(13 DOWNTO 1); -- because of 64 bit Y mantissa > 32 bit long, left shift range > right shift rangre leftshiftmax <= aa(13 DOWNTO 1) - maxpoint; -- 1118 is the max - if +ve, saturate rightshiftmin <= aa(13 DOWNTO 1) - minpoint; -- 1022 is the min - if -ve, zero selectleftbit <= rightshiftnum(13); satshiftbit <= selectleftbit AND NOT(leftshiftmax(13)); zipshiftbit <= NOT(selectleftbit) AND rightshiftmin(13); gsa: IF (normspeed = 1) GENERATE sftlc: hcc_lsftcomb64 PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1), outbus=>leftshiftbus); sftrc: hcc_rsftcomb64 PORT MAP (inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1), outbus=>rightshiftbus); END GENERATE; gsb: IF (normspeed > 1) GENERATE sftlp: hcc_lsftpipe64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>aa(77 DOWNTO 14),shift=>leftshiftnum(6 DOWNTO 1), outbus=>leftshiftbus); sftrp: hcc_rsftpipe64 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>aa(77 DOWNTO 14),shift=>rightshiftnum(6 DOWNTO 1), outbus=>rightshiftbus); END GENERATE; --*** DELAY CONTROL AND CONDITION SIGNALS *** dbmux: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>selectleftbit,cc=>selectleftbitdel); dbsat: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aasat,cc=>satout); dbzip: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aazip,cc=>zipout); dbsftsat: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>satshiftbit,cc=>satshiftout); dbsftzip: hcc_delaybit GENERIC MAP (delay=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>zipshiftbit,cc=>zipshiftout); --*** OUTPUT MUX *** pao: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP leftshiftbusff(k) <= '0'; rightshiftbusff(k) <= '0'; shiftmuxff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN leftshiftbusff <= leftshiftbus(64 DOWNTO 33); rightshiftbusff <= rightshiftbus(64 DOWNTO 33); FOR k IN 1 TO 32 LOOP shiftmuxff(k) <= (((leftshiftbusff(k) AND selectleftbitdel) OR (rightshiftbusff(k) AND NOT(selectleftbitdel))) OR (satout OR satshiftout)) AND NOT(zipout OR zipshiftout); END LOOP; END IF; END IF; END PROCESS; --************** --*** OUTPUT *** --************** cc <= shiftmuxff; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/dp_subs.vhd

10

2556

LIBRARY ieee; LIBRARY work; LIBRARY lpm; USE lpm.all; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** DOUBLE PRECISION CORE LIBRARY *** --*** *** --*** DP_ADDS.VHD *** --*** *** --*** Function: Synthesizable Fixed Point *** --*** Subtractor *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_subs IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); borrowin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END dp_subs; ARCHITECTURE syn of dp_subs IS component lpm_add_sub GENERIC ( lpm_direction : STRING; lpm_hint : STRING; lpm_pipeline : NATURAL; lpm_type : STRING; lpm_width : NATURAL ); PORT ( dataa : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0); cin : IN STD_LOGIC ; clken : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (lpm_width-1 DOWNTO 0) ); end component; BEGIN addtwo: lpm_add_sub GENERIC MAP ( lpm_direction => "SUB", lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", lpm_pipeline => pipes, lpm_type => "LPM_ADD_SUB", lpm_width => width ) PORT MAP ( dataa => aa, datab => bb, cin => borrowin, clken => enable, aclr => reset, clock => sysclk, result => cc ); END syn;

mit

ou-cse-378/vhdl-tetris

pc.vhd

1

1080

-- ================================================================================= -- // Name: Bryan Mason, James Batcheler, & Brad McMahon -- // File: PC.vhd -- // Date: 12/9/2004 -- // Description: Program Counter -- // Class: CSE 378 -- ================================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity PC is port ( d : in STD_LOGIC_VECTOR (15 downto 0); clr : in STD_LOGIC; clk : in STD_LOGIC; inc : in STD_LOGIC; pload : in STD_LOGIC; q : out STD_LOGIC_VECTOR (15 downto 0) ); end PC; architecture PC_arch of PC is signal COUNT: STD_LOGIC_VECTOR (15 downto 0); begin process (clk, clr) begin if clr = '1' then COUNT <= "0000000000000000"; elsif clk'event and clk='1' then if pload = '0' then if inc = '1' then COUNT <= COUNT + 1; end if; else COUNT <= d; end if; end if; q <= COUNT; end process; end PC_arch;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_ln_s5.vhd

10

195654

----------------------------------------------------------------------------- -- Altera DSP Builder Advanced Flow Tools Release Version 13.1 -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: Copyright 2013 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing device programming or simulation files), and -- any associated documentation or information are expressly subject to the -- terms and conditions of the Altera Program License Subscription Agreement, -- Altera MegaCore Function License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for the sole -- purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. ----------------------------------------------------------------------------- -- VHDL created from fp_ln_s5 -- VHDL created on Wed Feb 27 15:13:10 2013 library IEEE; use IEEE.std_logic_1164.all; use IEEE.NUMERIC_STD.all; use IEEE.MATH_REAL.all; use std.TextIO.all; use work.dspba_library_package.all; LIBRARY altera_mf; USE altera_mf.altera_mf_components.all; LIBRARY lpm; USE lpm.lpm_components.all; -- Text written from /data/tczajkow/polyeval/p4/ip/aion/src/mip_common/hw_model.cpp:1248 entity fp_ln_s5 is port ( a : in std_logic_vector(31 downto 0); en : in std_logic_vector(0 downto 0); q : out std_logic_vector(31 downto 0); clk : in std_logic; areset : in std_logic ); end; architecture normal of fp_ln_s5 is attribute altera_attribute : string; attribute altera_attribute of normal : architecture is "-name NOT_GATE_PUSH_BACK OFF; -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON; -name AUTO_SHIFT_REGISTER_RECOGNITION OFF; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 10037; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 10036; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410"; signal GND_q : std_logic_vector (0 downto 0); signal VCC_q : std_logic_vector (0 downto 0); signal cstAllZWF_uid8_fpLogETest_q : std_logic_vector (22 downto 0); signal cstBias_uid9_fpLogETest_q : std_logic_vector (7 downto 0); signal cstBiasMO_uid10_fpLogETest_q : std_logic_vector (7 downto 0); signal cstAllOWE_uid12_fpLogETest_q : std_logic_vector (7 downto 0); signal cstAllZWE_uid14_fpLogETest_q : std_logic_vector (7 downto 0); signal exc_R_uid27_fpLogETest_a : std_logic_vector(0 downto 0); signal exc_R_uid27_fpLogETest_b : std_logic_vector(0 downto 0); signal exc_R_uid27_fpLogETest_c : std_logic_vector(0 downto 0); signal exc_R_uid27_fpLogETest_q : std_logic_vector(0 downto 0); signal z2_uid40_fpLogETest_q : std_logic_vector (1 downto 0); signal multTermOne_uid42_fpLogETest_s : std_logic_vector (0 downto 0); signal multTermOne_uid42_fpLogETest_q : std_logic_vector (24 downto 0); signal postPEMul_uid43_fpLogETest_a : std_logic_vector (24 downto 0); signal postPEMul_uid43_fpLogETest_b : std_logic_vector (25 downto 0); signal postPEMul_uid43_fpLogETest_s1 : std_logic_vector (50 downto 0); signal postPEMul_uid43_fpLogETest_pr : SIGNED (50 downto 0); signal postPEMul_uid43_fpLogETest_q : std_logic_vector (50 downto 0); signal wideZero_uid44_fpLogETest_q : std_logic_vector (34 downto 0); signal addTermOne_uid45_fpLogETest_s : std_logic_vector (0 downto 0); signal addTermOne_uid45_fpLogETest_q : std_logic_vector (34 downto 0); signal finalSumOneComp_uid52_fpLogETest_a : std_logic_vector(56 downto 0); signal finalSumOneComp_uid52_fpLogETest_b : std_logic_vector(56 downto 0); signal finalSumOneComp_uid52_fpLogETest_q : std_logic_vector(56 downto 0); signal cstMSBFinalSumPBias_uid56_fpLogETest_q : std_logic_vector (8 downto 0); signal signRC1_uid73_fpLogETest_a : std_logic_vector(0 downto 0); signal signRC1_uid73_fpLogETest_b : std_logic_vector(0 downto 0); signal signRC1_uid73_fpLogETest_q : std_logic_vector(0 downto 0); signal InvExcRNaN_uid76_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExcRNaN_uid76_fpLogETest_q : std_logic_vector(0 downto 0); signal oneFracRPostExc2_uid80_fpLogETest_q : std_logic_vector (22 downto 0); signal p1_uid92_constMult_q : std_logic_vector(36 downto 0); signal p0_uid93_constMult_q : std_logic_vector(33 downto 0); signal zs_uid113_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0); signal mO_uid116_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0); signal zs_uid121_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0); signal zs_uid133_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0); signal leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q : std_logic_vector (47 downto 0); signal leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q : std_logic_vector (11 downto 0); signal leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q : std_logic_vector (2 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_a : std_logic_vector (12 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_b : std_logic_vector (12 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_s1 : std_logic_vector (25 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_pr : SIGNED (26 downto 0); signal prodXY_uid185_pT1_uid101_natLogPolyEval_q : std_logic_vector (25 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_a : std_logic_vector (14 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_b : std_logic_vector (22 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_s1 : std_logic_vector (37 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_pr : SIGNED (38 downto 0); signal prodXY_uid188_pT2_uid107_natLogPolyEval_q : std_logic_vector (37 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_reset0 : std_logic; signal memoryC0_uid97_natLogTabGen_lutmem_ia : std_logic_vector (30 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_iq : std_logic_vector (30 downto 0); signal memoryC0_uid97_natLogTabGen_lutmem_q : std_logic_vector (30 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_reset0 : std_logic; signal memoryC1_uid98_natLogTabGen_lutmem_ia : std_logic_vector (20 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_iq : std_logic_vector (20 downto 0); signal memoryC1_uid98_natLogTabGen_lutmem_q : std_logic_vector (20 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_reset0 : std_logic; signal memoryC2_uid99_natLogTabGen_lutmem_ia : std_logic_vector (12 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_aa : std_logic_vector (8 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_ab : std_logic_vector (8 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_iq : std_logic_vector (12 downto 0); signal memoryC2_uid99_natLogTabGen_lutmem_q : std_logic_vector (12 downto 0); signal reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q : std_logic_vector (2 downto 0); signal reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q : std_logic_vector (8 downto 0); signal reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q : std_logic_vector (12 downto 0); signal reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q : std_logic_vector (12 downto 0); signal reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q : std_logic_vector (14 downto 0); signal reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q : std_logic_vector (22 downto 0); signal reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q : std_logic_vector (25 downto 0); signal reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q : std_logic_vector (31 downto 0); signal reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q : std_logic_vector (31 downto 0); signal reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q : std_logic_vector (15 downto 0); signal reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q : std_logic_vector (15 downto 0); signal reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q : std_logic_vector (3 downto 0); signal reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q : std_logic_vector (3 downto 0); signal reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q : std_logic_vector (0 downto 0); signal reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0); signal reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q : std_logic_vector (57 downto 0); signal reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q : std_logic_vector (57 downto 0); signal reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q : std_logic_vector (57 downto 0); signal reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q : std_logic_vector (57 downto 0); signal reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q : std_logic_vector (1 downto 0); signal reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q : std_logic_vector (5 downto 0); signal reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q : std_logic_vector (33 downto 0); signal reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q : std_logic_vector (0 downto 0); signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q : std_logic_vector (22 downto 0); signal ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q : std_logic_vector (0 downto 0); signal ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q : std_logic_vector (0 downto 0); signal ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q : std_logic_vector (0 downto 0); signal ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q : std_logic_vector (0 downto 0); signal ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q : std_logic_vector (0 downto 0); signal ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q : std_logic_vector (0 downto 0); signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q : std_logic_vector (41 downto 0); signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q : std_logic_vector (25 downto 0); signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q : std_logic_vector (9 downto 0); signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q : std_logic_vector (57 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q : std_logic_vector (8 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 : std_logic; signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia : std_logic_vector (7 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq : std_logic_vector (7 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q : std_logic_vector (7 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq : std_logic; signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve : boolean; attribute preserve of ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q : signal is true; signal ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q : std_logic_vector (22 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 : std_logic; signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa : std_logic_vector (3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab : std_logic_vector (3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q : std_logic_vector (24 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q : std_logic_vector(3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i : unsigned(3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq : std_logic; signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q : std_logic_vector (3 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q : std_logic_vector (4 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q : signal is true; signal ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (41 downto 0); signal ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (25 downto 0); signal ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q : std_logic_vector (9 downto 0); signal ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q : std_logic_vector (57 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 : std_logic; signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa : std_logic_vector (2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab : std_logic_vector (2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q : std_logic_vector (8 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q : std_logic_vector(2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i : unsigned(2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq : std_logic; signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q : std_logic_vector (2 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q : std_logic_vector (3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q : signal is true; signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q : std_logic_vector (8 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 : std_logic; signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa : std_logic_vector (4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab : std_logic_vector (4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q : std_logic_vector(4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i : unsigned(4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq : std_logic; signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q : std_logic_vector (4 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q : std_logic_vector (5 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q : signal is true; signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 : std_logic; signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q : std_logic_vector (14 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i : unsigned(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : std_logic_vector (0 downto 0); attribute preserve of ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q : signal is true; signal pad_o_uid11_uid38_fpLogETest_q : std_logic_vector (23 downto 0); signal FPOne_uid63_fpLogETest_q : std_logic_vector (31 downto 0); signal expFracPostRnd_uid60_fpLogETest_a : std_logic_vector(34 downto 0); signal expFracPostRnd_uid60_fpLogETest_b : std_logic_vector(34 downto 0); signal expFracPostRnd_uid60_fpLogETest_o : std_logic_vector (34 downto 0); signal expFracPostRnd_uid60_fpLogETest_q : std_logic_vector (34 downto 0); signal notC_uid71_fpLogETest_a : std_logic_vector(0 downto 0); signal notC_uid71_fpLogETest_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q : std_logic_vector (3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q : std_logic_vector (2 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q : std_logic_vector (4 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s : std_logic_vector (0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q : std_logic_vector (0 downto 0); signal expX_uid6_fpLogETest_in : std_logic_vector (30 downto 0); signal expX_uid6_fpLogETest_b : std_logic_vector (7 downto 0); signal signX_uid7_fpLogETest_in : std_logic_vector (31 downto 0); signal signX_uid7_fpLogETest_b : std_logic_vector (0 downto 0); signal frac_uid19_fpLogETest_in : std_logic_vector (22 downto 0); signal frac_uid19_fpLogETest_b : std_logic_vector (22 downto 0); signal excRZero_uid64_fpLogETest_a : std_logic_vector(31 downto 0); signal excRZero_uid64_fpLogETest_b : std_logic_vector(31 downto 0); signal excRZero_uid64_fpLogETest_q : std_logic_vector(0 downto 0); signal expXIsZero_uid16_fpLogETest_a : std_logic_vector(7 downto 0); signal expXIsZero_uid16_fpLogETest_b : std_logic_vector(7 downto 0); signal expXIsZero_uid16_fpLogETest_q : std_logic_vector(0 downto 0); signal expXIsMax_uid18_fpLogETest_a : std_logic_vector(7 downto 0); signal expXIsMax_uid18_fpLogETest_b : std_logic_vector(7 downto 0); signal expXIsMax_uid18_fpLogETest_q : std_logic_vector(0 downto 0); signal fracXIsZero_uid20_fpLogETest_a : std_logic_vector(22 downto 0); signal fracXIsZero_uid20_fpLogETest_b : std_logic_vector(22 downto 0); signal fracXIsZero_uid20_fpLogETest_q : std_logic_vector(0 downto 0); signal exc_I_uid21_fpLogETest_a : std_logic_vector(0 downto 0); signal exc_I_uid21_fpLogETest_b : std_logic_vector(0 downto 0); signal exc_I_uid21_fpLogETest_q : std_logic_vector(0 downto 0); signal e_uid29_fpLogETest_a : std_logic_vector(8 downto 0); signal e_uid29_fpLogETest_b : std_logic_vector(8 downto 0); signal e_uid29_fpLogETest_o : std_logic_vector (8 downto 0); signal e_uid29_fpLogETest_q : std_logic_vector (8 downto 0); signal c_uid31_fpLogETest_a : std_logic_vector(7 downto 0); signal c_uid31_fpLogETest_b : std_logic_vector(7 downto 0); signal c_uid31_fpLogETest_q : std_logic_vector(0 downto 0); signal oMz_uid38_fpLogETest_a : std_logic_vector(24 downto 0); signal oMz_uid38_fpLogETest_b : std_logic_vector(24 downto 0); signal oMz_uid38_fpLogETest_o : std_logic_vector (24 downto 0); signal oMz_uid38_fpLogETest_q : std_logic_vector (24 downto 0); signal finalSumAbs_uid53_fpLogETest_a : std_logic_vector(57 downto 0); signal finalSumAbs_uid53_fpLogETest_b : std_logic_vector(57 downto 0); signal finalSumAbs_uid53_fpLogETest_o : std_logic_vector (57 downto 0); signal finalSumAbs_uid53_fpLogETest_q : std_logic_vector (57 downto 0); signal expRExt_uid57_fpLogETest_a : std_logic_vector(9 downto 0); signal expRExt_uid57_fpLogETest_b : std_logic_vector(9 downto 0); signal expRExt_uid57_fpLogETest_o : std_logic_vector (9 downto 0); signal expRExt_uid57_fpLogETest_q : std_logic_vector (9 downto 0); signal signRC11_uid74_fpLogETest_a : std_logic_vector(0 downto 0); signal signRC11_uid74_fpLogETest_b : std_logic_vector(0 downto 0); signal signRC11_uid74_fpLogETest_q : std_logic_vector(0 downto 0); signal signR_uid75_fpLogETest_a : std_logic_vector(0 downto 0); signal signR_uid75_fpLogETest_b : std_logic_vector(0 downto 0); signal signR_uid75_fpLogETest_q : std_logic_vector(0 downto 0); signal signRFull_uid77_fpLogETest_a : std_logic_vector(0 downto 0); signal signRFull_uid77_fpLogETest_b : std_logic_vector(0 downto 0); signal signRFull_uid77_fpLogETest_q : std_logic_vector(0 downto 0); signal excREnc_uid79_fpLogETest_q : std_logic_vector(1 downto 0); signal lev1_a0_uid94_constMult_a : std_logic_vector(38 downto 0); signal lev1_a0_uid94_constMult_b : std_logic_vector(38 downto 0); signal lev1_a0_uid94_constMult_o : std_logic_vector (38 downto 0); signal lev1_a0_uid94_constMult_q : std_logic_vector (37 downto 0); signal vCount_uid115_countZ_uid54_fpLogETest_a : std_logic_vector(31 downto 0); signal vCount_uid115_countZ_uid54_fpLogETest_b : std_logic_vector(31 downto 0); signal vCount_uid115_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid120_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid120_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0); signal vCount_uid123_countZ_uid54_fpLogETest_a : std_logic_vector(15 downto 0); signal vCount_uid123_countZ_uid54_fpLogETest_b : std_logic_vector(15 downto 0); signal vCount_uid123_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid126_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid126_countZ_uid54_fpLogETest_q : std_logic_vector (15 downto 0); signal vCount_uid135_countZ_uid54_fpLogETest_a : std_logic_vector(3 downto 0); signal vCount_uid135_countZ_uid54_fpLogETest_b : std_logic_vector(3 downto 0); signal vCount_uid135_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid138_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid138_countZ_uid54_fpLogETest_q : std_logic_vector (3 downto 0); signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0); signal leftShiftStage1_uid172_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q : std_logic_vector(0 downto 0); signal sEz_uid41_fpLogETest_q : std_logic_vector (24 downto 0); signal lowRangeB_uid46_fpLogETest_in : std_logic_vector (20 downto 0); signal lowRangeB_uid46_fpLogETest_b : std_logic_vector (20 downto 0); signal highBBits_uid47_fpLogETest_in : std_logic_vector (50 downto 0); signal highBBits_uid47_fpLogETest_b : std_logic_vector (29 downto 0); signal sumAHighB_uid48_fpLogETest_a : std_logic_vector(35 downto 0); signal sumAHighB_uid48_fpLogETest_b : std_logic_vector(35 downto 0); signal sumAHighB_uid48_fpLogETest_o : std_logic_vector (35 downto 0); signal sumAHighB_uid48_fpLogETest_q : std_logic_vector (35 downto 0); signal leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in : std_logic_vector (25 downto 0); signal prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b : std_logic_vector (13 downto 0); signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in : std_logic_vector (37 downto 0); signal prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b : std_logic_vector (23 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b : std_logic_vector(0 downto 0); signal ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q : std_logic_vector(0 downto 0); signal zPPolyEval_uid35_fpLogETest_in : std_logic_vector (14 downto 0); signal zPPolyEval_uid35_fpLogETest_b : std_logic_vector (14 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a : std_logic_vector(4 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b : std_logic_vector(4 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b : std_logic_vector(0 downto 0); signal ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a : std_logic_vector(3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b : std_logic_vector(3 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b : std_logic_vector(0 downto 0); signal ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a : std_logic_vector(5 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b : std_logic_vector(5 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b : std_logic_vector(0 downto 0); signal ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q : std_logic_vector(0 downto 0); signal fracR_uid61_fpLogETest_in : std_logic_vector (23 downto 0); signal fracR_uid61_fpLogETest_b : std_logic_vector (22 downto 0); signal expR_uid62_fpLogETest_in : std_logic_vector (31 downto 0); signal expR_uid62_fpLogETest_b : std_logic_vector (7 downto 0); signal InvSignX_uid65_fpLogETest_a : std_logic_vector(0 downto 0); signal InvSignX_uid65_fpLogETest_q : std_logic_vector(0 downto 0); signal zAddrLow_uid33_fpLogETest_in : std_logic_vector (22 downto 0); signal zAddrLow_uid33_fpLogETest_b : std_logic_vector (7 downto 0); signal InvExpXIsZero_uid26_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExpXIsZero_uid26_fpLogETest_q : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid22_fpLogETest_a : std_logic_vector(0 downto 0); signal InvFracXIsZero_uid22_fpLogETest_q : std_logic_vector(0 downto 0); signal InvExc_I_uid25_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExc_I_uid25_fpLogETest_q : std_logic_vector(0 downto 0); signal excRInfC1_uid66_fpLogETest_a : std_logic_vector(0 downto 0); signal excRInfC1_uid66_fpLogETest_b : std_logic_vector(0 downto 0); signal excRInfC1_uid66_fpLogETest_q : std_logic_vector(0 downto 0); signal xv0_uid90_constMult_in : std_logic_vector (5 downto 0); signal xv0_uid90_constMult_b : std_logic_vector (5 downto 0); signal xv1_uid91_constMult_in : std_logic_vector (8 downto 0); signal xv1_uid91_constMult_b : std_logic_vector (2 downto 0); signal addr_uid34_fpLogETest_q : std_logic_vector (8 downto 0); signal rVStage_uid114_countZ_uid54_fpLogETest_in : std_logic_vector (57 downto 0); signal rVStage_uid114_countZ_uid54_fpLogETest_b : std_logic_vector (31 downto 0); signal vStage_uid117_countZ_uid54_fpLogETest_in : std_logic_vector (25 downto 0); signal vStage_uid117_countZ_uid54_fpLogETest_b : std_logic_vector (25 downto 0); signal X41dto0_uid152_normVal_uid55_fpLogETest_in : std_logic_vector (41 downto 0); signal X41dto0_uid152_normVal_uid55_fpLogETest_b : std_logic_vector (41 downto 0); signal X9dto0_uid158_normVal_uid55_fpLogETest_in : std_logic_vector (9 downto 0); signal X9dto0_uid158_normVal_uid55_fpLogETest_b : std_logic_vector (9 downto 0); signal fracRPostExc_uid83_fpLogETest_s : std_logic_vector (1 downto 0); signal fracRPostExc_uid83_fpLogETest_q : std_logic_vector (22 downto 0); signal expRPostExc_uid87_fpLogETest_s : std_logic_vector (1 downto 0); signal expRPostExc_uid87_fpLogETest_q : std_logic_vector (7 downto 0); signal sR_uid95_constMult_in : std_logic_vector (36 downto 0); signal sR_uid95_constMult_b : std_logic_vector (34 downto 0); signal rVStage_uid122_countZ_uid54_fpLogETest_in : std_logic_vector (31 downto 0); signal rVStage_uid122_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0); signal vStage_uid124_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0); signal vStage_uid124_countZ_uid54_fpLogETest_b : std_logic_vector (15 downto 0); signal rVStage_uid128_countZ_uid54_fpLogETest_in : std_logic_vector (15 downto 0); signal rVStage_uid128_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0); signal vStage_uid130_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0); signal vStage_uid130_countZ_uid54_fpLogETest_b : std_logic_vector (7 downto 0); signal rVStage_uid140_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0); signal rVStage_uid140_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0); signal vStage_uid142_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0); signal vStage_uid142_countZ_uid54_fpLogETest_b : std_logic_vector (1 downto 0); signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in : std_logic_vector (56 downto 0); signal LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b : std_logic_vector (56 downto 0); signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in : std_logic_vector (55 downto 0); signal LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b : std_logic_vector (55 downto 0); signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in : std_logic_vector (54 downto 0); signal LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b : std_logic_vector (54 downto 0); signal finalSum_uid46_uid49_fpLogETest_q : std_logic_vector (56 downto 0); signal lowRangeB_uid102_natLogPolyEval_in : std_logic_vector (0 downto 0); signal lowRangeB_uid102_natLogPolyEval_b : std_logic_vector (0 downto 0); signal highBBits_uid103_natLogPolyEval_in : std_logic_vector (13 downto 0); signal highBBits_uid103_natLogPolyEval_b : std_logic_vector (12 downto 0); signal lowRangeB_uid108_natLogPolyEval_in : std_logic_vector (1 downto 0); signal lowRangeB_uid108_natLogPolyEval_b : std_logic_vector (1 downto 0); signal highBBits_uid109_natLogPolyEval_in : std_logic_vector (23 downto 0); signal highBBits_uid109_natLogPolyEval_b : std_logic_vector (21 downto 0); signal yT1_uid100_natLogPolyEval_in : std_logic_vector (14 downto 0); signal yT1_uid100_natLogPolyEval_b : std_logic_vector (12 downto 0); signal negNonZero_uid69_fpLogETest_a : std_logic_vector(0 downto 0); signal negNonZero_uid69_fpLogETest_b : std_logic_vector(0 downto 0); signal negNonZero_uid69_fpLogETest_q : std_logic_vector(0 downto 0); signal exc_N_uid23_fpLogETest_a : std_logic_vector(0 downto 0); signal exc_N_uid23_fpLogETest_b : std_logic_vector(0 downto 0); signal exc_N_uid23_fpLogETest_q : std_logic_vector(0 downto 0); signal excRInf_uid67_fpLogETest_a : std_logic_vector(0 downto 0); signal excRInf_uid67_fpLogETest_b : std_logic_vector(0 downto 0); signal excRInf_uid67_fpLogETest_q : std_logic_vector(0 downto 0); signal cStage_uid118_countZ_uid54_fpLogETest_q : std_logic_vector (31 downto 0); signal RLn_uid88_fpLogETest_q : std_logic_vector (31 downto 0); signal vCount_uid129_countZ_uid54_fpLogETest_a : std_logic_vector(7 downto 0); signal vCount_uid129_countZ_uid54_fpLogETest_b : std_logic_vector(7 downto 0); signal vCount_uid129_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid132_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid132_countZ_uid54_fpLogETest_q : std_logic_vector (7 downto 0); signal vCount_uid141_countZ_uid54_fpLogETest_a : std_logic_vector(1 downto 0); signal vCount_uid141_countZ_uid54_fpLogETest_b : std_logic_vector(1 downto 0); signal vCount_uid141_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal vStagei_uid144_countZ_uid54_fpLogETest_s : std_logic_vector (0 downto 0); signal vStagei_uid144_countZ_uid54_fpLogETest_q : std_logic_vector (1 downto 0); signal leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal FullSumAB56_uid50_fpLogETest_in : std_logic_vector (56 downto 0); signal FullSumAB56_uid50_fpLogETest_b : std_logic_vector (0 downto 0); signal sumAHighB_uid104_natLogPolyEval_a : std_logic_vector(21 downto 0); signal sumAHighB_uid104_natLogPolyEval_b : std_logic_vector(21 downto 0); signal sumAHighB_uid104_natLogPolyEval_o : std_logic_vector (21 downto 0); signal sumAHighB_uid104_natLogPolyEval_q : std_logic_vector (21 downto 0); signal sumAHighB_uid110_natLogPolyEval_a : std_logic_vector(31 downto 0); signal sumAHighB_uid110_natLogPolyEval_b : std_logic_vector(31 downto 0); signal sumAHighB_uid110_natLogPolyEval_o : std_logic_vector (31 downto 0); signal sumAHighB_uid110_natLogPolyEval_q : std_logic_vector (31 downto 0); signal excRNaN_uid70_fpLogETest_a : std_logic_vector(0 downto 0); signal excRNaN_uid70_fpLogETest_b : std_logic_vector(0 downto 0); signal excRNaN_uid70_fpLogETest_q : std_logic_vector(0 downto 0); signal InvExc_N_uid24_fpLogETest_a : std_logic_vector(0 downto 0); signal InvExc_N_uid24_fpLogETest_q : std_logic_vector(0 downto 0); signal concExc_uid78_fpLogETest_q : std_logic_vector (2 downto 0); signal rVStage_uid134_countZ_uid54_fpLogETest_in : std_logic_vector (7 downto 0); signal rVStage_uid134_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0); signal vStage_uid136_countZ_uid54_fpLogETest_in : std_logic_vector (3 downto 0); signal vStage_uid136_countZ_uid54_fpLogETest_b : std_logic_vector (3 downto 0); signal rVStage_uid146_countZ_uid54_fpLogETest_in : std_logic_vector (1 downto 0); signal rVStage_uid146_countZ_uid54_fpLogETest_b : std_logic_vector (0 downto 0); signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0); signal leftShiftStage2_uid183_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal signTerm2_uid72_fpLogETest_a : std_logic_vector(0 downto 0); signal signTerm2_uid72_fpLogETest_b : std_logic_vector(0 downto 0); signal signTerm2_uid72_fpLogETest_q : std_logic_vector(0 downto 0); signal s1_uid102_uid105_natLogPolyEval_q : std_logic_vector (22 downto 0); signal s2_uid108_uid111_natLogPolyEval_q : std_logic_vector (33 downto 0); signal vCount_uid147_countZ_uid54_fpLogETest_a : std_logic_vector(0 downto 0); signal vCount_uid147_countZ_uid54_fpLogETest_b : std_logic_vector(0 downto 0); signal vCount_uid147_countZ_uid54_fpLogETest_q : std_logic_vector(0 downto 0); signal fracR_uid58_fpLogETest_in : std_logic_vector (56 downto 0); signal fracR_uid58_fpLogETest_b : std_logic_vector (23 downto 0); signal peOR_uid37_fpLogETest_in : std_logic_vector (32 downto 0); signal peOR_uid37_fpLogETest_b : std_logic_vector (25 downto 0); signal r_uid148_countZ_uid54_fpLogETest_q : std_logic_vector (5 downto 0); signal expFracConc_uid59_fpLogETest_q : std_logic_vector (33 downto 0); signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in : std_logic_vector (5 downto 0); signal leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in : std_logic_vector (3 downto 0); signal leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in : std_logic_vector (1 downto 0); signal leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b : std_logic_vector (1 downto 0); signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_s : std_logic_vector (1 downto 0); signal leftShiftStage0_uid161_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in : std_logic_vector (53 downto 0); signal LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b : std_logic_vector (53 downto 0); signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in : std_logic_vector (49 downto 0); signal LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b : std_logic_vector (49 downto 0); signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in : std_logic_vector (45 downto 0); signal LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b : std_logic_vector (45 downto 0); signal leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); signal leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q : std_logic_vector (57 downto 0); begin --xIn(GPIN,3)@0 --cstBiasMO_uid10_fpLogETest(CONSTANT,9) cstBiasMO_uid10_fpLogETest_q <= "01111110"; --expX_uid6_fpLogETest(BITSELECT,5)@0 expX_uid6_fpLogETest_in <= a(30 downto 0); expX_uid6_fpLogETest_b <= expX_uid6_fpLogETest_in(30 downto 23); --c_uid31_fpLogETest(LOGICAL,30)@0 c_uid31_fpLogETest_a <= expX_uid6_fpLogETest_b; c_uid31_fpLogETest_b <= cstBiasMO_uid10_fpLogETest_q; c_uid31_fpLogETest_q <= "1" when c_uid31_fpLogETest_a = c_uid31_fpLogETest_b else "0"; --frac_uid19_fpLogETest(BITSELECT,18)@0 frac_uid19_fpLogETest_in <= a(22 downto 0); frac_uid19_fpLogETest_b <= frac_uid19_fpLogETest_in(22 downto 0); --zAddrLow_uid33_fpLogETest(BITSELECT,32)@0 zAddrLow_uid33_fpLogETest_in <= frac_uid19_fpLogETest_b; zAddrLow_uid33_fpLogETest_b <= zAddrLow_uid33_fpLogETest_in(22 downto 15); --addr_uid34_fpLogETest(BITJOIN,33)@0 addr_uid34_fpLogETest_q <= c_uid31_fpLogETest_q & zAddrLow_uid33_fpLogETest_b; --reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0(REG,194)@0 reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= "000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q <= addr_uid34_fpLogETest_q; END IF; END IF; END PROCESS; --memoryC2_uid99_natLogTabGen_lutmem(DUALMEM,192)@1 memoryC2_uid99_natLogTabGen_lutmem_reset0 <= areset; memoryC2_uid99_natLogTabGen_lutmem_ia <= (others => '0'); memoryC2_uid99_natLogTabGen_lutmem_aa <= (others => '0'); memoryC2_uid99_natLogTabGen_lutmem_ab <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q; memoryC2_uid99_natLogTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 13, widthad_a => 9, numwords_a => 512, width_b => 13, widthad_b => 9, numwords_b => 512, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_ln_s5_memoryC2_uid99_natLogTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC2_uid99_natLogTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC2_uid99_natLogTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC2_uid99_natLogTabGen_lutmem_iq, address_a => memoryC2_uid99_natLogTabGen_lutmem_aa, data_a => memoryC2_uid99_natLogTabGen_lutmem_ia ); memoryC2_uid99_natLogTabGen_lutmem_q <= memoryC2_uid99_natLogTabGen_lutmem_iq(12 downto 0); --reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1(REG,196)@3 reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q <= memoryC2_uid99_natLogTabGen_lutmem_q; END IF; END IF; END PROCESS; --ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a(DELAY,244)@0 ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a : dspba_delay GENERIC MAP ( width => 23, depth => 2 ) PORT MAP ( xin => frac_uid19_fpLogETest_b, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg(DELAY,451) ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg : dspba_delay GENERIC MAP ( width => 23, depth => 1 ) PORT MAP ( xin => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_q, xout => ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --zPPolyEval_uid35_fpLogETest(BITSELECT,34)@3 zPPolyEval_uid35_fpLogETest_in <= ld_frac_uid19_fpLogETest_b_to_zPPolyEval_uid35_fpLogETest_a_outputreg_q(14 downto 0); zPPolyEval_uid35_fpLogETest_b <= zPPolyEval_uid35_fpLogETest_in(14 downto 0); --yT1_uid100_natLogPolyEval(BITSELECT,99)@3 yT1_uid100_natLogPolyEval_in <= zPPolyEval_uid35_fpLogETest_b; yT1_uid100_natLogPolyEval_b <= yT1_uid100_natLogPolyEval_in(14 downto 2); --reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0(REG,195)@3 reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= "0000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q <= yT1_uid100_natLogPolyEval_b; END IF; END IF; END PROCESS; --prodXY_uid185_pT1_uid101_natLogPolyEval(MULT,184)@4 prodXY_uid185_pT1_uid101_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_a),14)) * SIGNED(prodXY_uid185_pT1_uid101_natLogPolyEval_b); prodXY_uid185_pT1_uid101_natLogPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid185_pT1_uid101_natLogPolyEval_a <= (others => '0'); prodXY_uid185_pT1_uid101_natLogPolyEval_b <= (others => '0'); prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid185_pT1_uid101_natLogPolyEval_a <= reg_yT1_uid100_natLogPolyEval_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_0_q; prodXY_uid185_pT1_uid101_natLogPolyEval_b <= reg_memoryC2_uid99_natLogTabGen_lutmem_0_to_prodXY_uid185_pT1_uid101_natLogPolyEval_1_q; prodXY_uid185_pT1_uid101_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid185_pT1_uid101_natLogPolyEval_pr,26)); END IF; END IF; END PROCESS; prodXY_uid185_pT1_uid101_natLogPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid185_pT1_uid101_natLogPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid185_pT1_uid101_natLogPolyEval_q <= prodXY_uid185_pT1_uid101_natLogPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval(BITSELECT,185)@7 prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in <= prodXY_uid185_pT1_uid101_natLogPolyEval_q; prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_in(25 downto 12); --highBBits_uid103_natLogPolyEval(BITSELECT,102)@7 highBBits_uid103_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b; highBBits_uid103_natLogPolyEval_b <= highBBits_uid103_natLogPolyEval_in(13 downto 1); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a(DELAY,409)@1 ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a : dspba_delay GENERIC MAP ( width => 9, depth => 3 ) PORT MAP ( xin => reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, ena => en(0), clk => clk, aclr => areset ); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg(DELAY,482) ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC1_uid98_natLogTabGen_lutmem(DUALMEM,191)@5 memoryC1_uid98_natLogTabGen_lutmem_reset0 <= areset; memoryC1_uid98_natLogTabGen_lutmem_ia <= (others => '0'); memoryC1_uid98_natLogTabGen_lutmem_aa <= (others => '0'); memoryC1_uid98_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC1_uid98_natLogTabGen_lutmem_0_q_to_memoryC1_uid98_natLogTabGen_lutmem_a_outputreg_q; memoryC1_uid98_natLogTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 21, widthad_a => 9, numwords_a => 512, width_b => 21, widthad_b => 9, numwords_b => 512, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_ln_s5_memoryC1_uid98_natLogTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC1_uid98_natLogTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC1_uid98_natLogTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC1_uid98_natLogTabGen_lutmem_iq, address_a => memoryC1_uid98_natLogTabGen_lutmem_aa, data_a => memoryC1_uid98_natLogTabGen_lutmem_ia ); memoryC1_uid98_natLogTabGen_lutmem_q <= memoryC1_uid98_natLogTabGen_lutmem_iq(20 downto 0); --sumAHighB_uid104_natLogPolyEval(ADD,103)@7 sumAHighB_uid104_natLogPolyEval_a <= STD_LOGIC_VECTOR((21 downto 21 => memoryC1_uid98_natLogTabGen_lutmem_q(20)) & memoryC1_uid98_natLogTabGen_lutmem_q); sumAHighB_uid104_natLogPolyEval_b <= STD_LOGIC_VECTOR((21 downto 13 => highBBits_uid103_natLogPolyEval_b(12)) & highBBits_uid103_natLogPolyEval_b); sumAHighB_uid104_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid104_natLogPolyEval_a) + SIGNED(sumAHighB_uid104_natLogPolyEval_b)); sumAHighB_uid104_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_o(21 downto 0); --lowRangeB_uid102_natLogPolyEval(BITSELECT,101)@7 lowRangeB_uid102_natLogPolyEval_in <= prodXYTruncFR_uid186_pT1_uid101_natLogPolyEval_b(0 downto 0); lowRangeB_uid102_natLogPolyEval_b <= lowRangeB_uid102_natLogPolyEval_in(0 downto 0); --s1_uid102_uid105_natLogPolyEval(BITJOIN,104)@7 s1_uid102_uid105_natLogPolyEval_q <= sumAHighB_uid104_natLogPolyEval_q & lowRangeB_uid102_natLogPolyEval_b; --reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1(REG,199)@7 reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= "00000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q <= s1_uid102_uid105_natLogPolyEval_q; END IF; END IF; END PROCESS; --VCC(CONSTANT,1) VCC_q <= "1"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable(LOGICAL,447) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a <= en; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q <= not ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_a; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor(LOGICAL,504) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q <= not (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_a or ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_b); --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg(REG,502) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q <= VCC_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena(REG,505) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_nor_q = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd(LOGICAL,506) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_sticky_ena_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b <= en; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_a and ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_b; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg(DELAY,496) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg : dspba_delay GENERIC MAP ( width => 15, depth => 1 ) PORT MAP ( xin => zPPolyEval_uid35_fpLogETest_b, xout => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt(COUNTER,498) -- every=1, low=0, high=1, step=1, init=1 ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,1); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i + 1; END IF; END IF; END PROCESS; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_i,1)); --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg(REG,499) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux(MUX,500) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s <= en; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux: PROCESS (ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q, ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q) BEGIN CASE ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_s IS WHEN "0" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q; WHEN "1" => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdcnt_q; WHEN OTHERS => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem(DUALMEM,497) ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0 <= areset; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_inputreg_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdreg_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_rdmux_q; ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 15, widthad_a => 1, numwords_a => 2, width_b => 15, widthad_b => 1, numwords_b => 2, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq, address_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_aa, data_a => ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_ia ); ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_iq(14 downto 0); --reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0(REG,198)@7 reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= "000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q <= ld_zPPolyEval_uid35_fpLogETest_b_to_reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_a_replace_mem_q; END IF; END IF; END PROCESS; --prodXY_uid188_pT2_uid107_natLogPolyEval(MULT,187)@8 prodXY_uid188_pT2_uid107_natLogPolyEval_pr <= signed(resize(UNSIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_a),16)) * SIGNED(prodXY_uid188_pT2_uid107_natLogPolyEval_b); prodXY_uid188_pT2_uid107_natLogPolyEval_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid188_pT2_uid107_natLogPolyEval_a <= (others => '0'); prodXY_uid188_pT2_uid107_natLogPolyEval_b <= (others => '0'); prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid188_pT2_uid107_natLogPolyEval_a <= reg_zPPolyEval_uid35_fpLogETest_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_0_q; prodXY_uid188_pT2_uid107_natLogPolyEval_b <= reg_s1_uid102_uid105_natLogPolyEval_0_to_prodXY_uid188_pT2_uid107_natLogPolyEval_1_q; prodXY_uid188_pT2_uid107_natLogPolyEval_s1 <= STD_LOGIC_VECTOR(resize(prodXY_uid188_pT2_uid107_natLogPolyEval_pr,38)); END IF; END IF; END PROCESS; prodXY_uid188_pT2_uid107_natLogPolyEval: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN prodXY_uid188_pT2_uid107_natLogPolyEval_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN prodXY_uid188_pT2_uid107_natLogPolyEval_q <= prodXY_uid188_pT2_uid107_natLogPolyEval_s1; END IF; END IF; END PROCESS; --prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval(BITSELECT,188)@11 prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in <= prodXY_uid188_pT2_uid107_natLogPolyEval_q; prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_in(37 downto 14); --highBBits_uid109_natLogPolyEval(BITSELECT,108)@11 highBBits_uid109_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b; highBBits_uid109_natLogPolyEval_b <= highBBits_uid109_natLogPolyEval_in(23 downto 2); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor(LOGICAL,479) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q <= not (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_a or ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_b); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top(CONSTANT,475) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q <= "0101"; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp(LOGICAL,476) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_mem_top_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q); ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q <= "1" when ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_a = ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_b else "0"; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg(REG,477) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmp_q; END IF; END IF; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena(REG,480) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_nor_q = "1") THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd(LOGICAL,481) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_sticky_ena_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b <= en; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_a and ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_b; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt(COUNTER,471) -- every=1, low=0, high=5, step=1, init=1 ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= TO_UNSIGNED(1,3); ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i = 4 THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '1'; ELSE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_eq = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i - 5; ELSE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_i,3)); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg(REG,472) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux(MUX,473) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s <= en; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux: PROCESS (ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q, ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q) BEGIN CASE ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_s IS WHEN "0" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q; WHEN "1" => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdcnt_q; WHEN OTHERS => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem(DUALMEM,470) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0 <= areset; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia <= reg_addr_uid34_fpLogETest_0_to_memoryC2_uid99_natLogTabGen_lutmem_0_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdreg_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_rdmux_q; ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 9, widthad_a => 3, numwords_a => 6, width_b => 9, widthad_b => 3, numwords_b => 6, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_reset0, clock1 => clk, address_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq, address_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_aa, data_a => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_ia ); ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_iq(8 downto 0); --ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg(DELAY,469) ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg : dspba_delay GENERIC MAP ( width => 9, depth => 1 ) PORT MAP ( xin => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_replace_mem_q, xout => ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --memoryC0_uid97_natLogTabGen_lutmem(DUALMEM,190)@9 memoryC0_uid97_natLogTabGen_lutmem_reset0 <= areset; memoryC0_uid97_natLogTabGen_lutmem_ia <= (others => '0'); memoryC0_uid97_natLogTabGen_lutmem_aa <= (others => '0'); memoryC0_uid97_natLogTabGen_lutmem_ab <= ld_reg_addr_uid34_fpLogETest_0_to_memoryC0_uid97_natLogTabGen_lutmem_0_q_to_memoryC0_uid97_natLogTabGen_lutmem_a_outputreg_q; memoryC0_uid97_natLogTabGen_lutmem_dmem : altsyncram GENERIC MAP ( ram_block_type => "M20K", operation_mode => "DUAL_PORT", width_a => 31, widthad_a => 9, numwords_a => 512, width_b => 31, widthad_b => 9, numwords_b => 512, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK0", outdata_aclr_b => "CLEAR0", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "fp_ln_s5_memoryC0_uid97_natLogTabGen_lutmem.hex", init_file_layout => "PORT_B", intended_device_family => "Stratix V" ) PORT MAP ( clocken0 => en(0), wren_a => '0', aclr0 => memoryC0_uid97_natLogTabGen_lutmem_reset0, clock0 => clk, address_b => memoryC0_uid97_natLogTabGen_lutmem_ab, -- data_b => (others => '0'), q_b => memoryC0_uid97_natLogTabGen_lutmem_iq, address_a => memoryC0_uid97_natLogTabGen_lutmem_aa, data_a => memoryC0_uid97_natLogTabGen_lutmem_ia ); memoryC0_uid97_natLogTabGen_lutmem_q <= memoryC0_uid97_natLogTabGen_lutmem_iq(30 downto 0); --sumAHighB_uid110_natLogPolyEval(ADD,109)@11 sumAHighB_uid110_natLogPolyEval_a <= STD_LOGIC_VECTOR((31 downto 31 => memoryC0_uid97_natLogTabGen_lutmem_q(30)) & memoryC0_uid97_natLogTabGen_lutmem_q); sumAHighB_uid110_natLogPolyEval_b <= STD_LOGIC_VECTOR((31 downto 22 => highBBits_uid109_natLogPolyEval_b(21)) & highBBits_uid109_natLogPolyEval_b); sumAHighB_uid110_natLogPolyEval_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid110_natLogPolyEval_a) + SIGNED(sumAHighB_uid110_natLogPolyEval_b)); sumAHighB_uid110_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_o(31 downto 0); --lowRangeB_uid108_natLogPolyEval(BITSELECT,107)@11 lowRangeB_uid108_natLogPolyEval_in <= prodXYTruncFR_uid189_pT2_uid107_natLogPolyEval_b(1 downto 0); lowRangeB_uid108_natLogPolyEval_b <= lowRangeB_uid108_natLogPolyEval_in(1 downto 0); --s2_uid108_uid111_natLogPolyEval(BITJOIN,110)@11 s2_uid108_uid111_natLogPolyEval_q <= sumAHighB_uid110_natLogPolyEval_q & lowRangeB_uid108_natLogPolyEval_b; --peOR_uid37_fpLogETest(BITSELECT,36)@11 peOR_uid37_fpLogETest_in <= s2_uid108_uid111_natLogPolyEval_q(32 downto 0); peOR_uid37_fpLogETest_b <= peOR_uid37_fpLogETest_in(32 downto 7); --reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1(REG,201)@11 reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= "00000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q <= peOR_uid37_fpLogETest_b; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor(LOGICAL,462) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q <= not (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_a or ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_b); --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top(CONSTANT,458) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q <= "01000"; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp(LOGICAL,459) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_mem_top_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q); ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q <= "1" when ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_a = ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_b else "0"; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg(REG,460) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmp_q; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena(REG,463) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_nor_q = "1") THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd(LOGICAL,464) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_sticky_ena_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b <= en; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_a and ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_b; --GND(CONSTANT,0) GND_q <= "0"; --pad_o_uid11_uid38_fpLogETest(BITJOIN,37)@0 pad_o_uid11_uid38_fpLogETest_q <= VCC_q & STD_LOGIC_VECTOR((22 downto 1 => GND_q(0)) & GND_q); --oMz_uid38_fpLogETest(SUB,38)@0 oMz_uid38_fpLogETest_a <= STD_LOGIC_VECTOR("0" & pad_o_uid11_uid38_fpLogETest_q); oMz_uid38_fpLogETest_b <= STD_LOGIC_VECTOR("00" & frac_uid19_fpLogETest_b); oMz_uid38_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(oMz_uid38_fpLogETest_a) - UNSIGNED(oMz_uid38_fpLogETest_b)); oMz_uid38_fpLogETest_q <= oMz_uid38_fpLogETest_o(24 downto 0); --z2_uid40_fpLogETest(CONSTANT,39) z2_uid40_fpLogETest_q <= "00"; --sEz_uid41_fpLogETest(BITJOIN,40)@0 sEz_uid41_fpLogETest_q <= z2_uid40_fpLogETest_q & frac_uid19_fpLogETest_b; --multTermOne_uid42_fpLogETest(MUX,41)@0 multTermOne_uid42_fpLogETest_s <= c_uid31_fpLogETest_q; multTermOne_uid42_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN multTermOne_uid42_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE multTermOne_uid42_fpLogETest_s IS WHEN "0" => multTermOne_uid42_fpLogETest_q <= sEz_uid41_fpLogETest_q; WHEN "1" => multTermOne_uid42_fpLogETest_q <= oMz_uid38_fpLogETest_q; WHEN OTHERS => multTermOne_uid42_fpLogETest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt(COUNTER,454) -- every=1, low=0, high=8, step=1, init=1 ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i = 7 THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '1'; ELSE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_eq = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i - 8; ELSE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_i,4)); --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg(REG,455) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux(MUX,456) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s <= en; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux: PROCESS (ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q, ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q) BEGIN CASE ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_s IS WHEN "0" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q; WHEN "1" => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdcnt_q; WHEN OTHERS => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem(DUALMEM,453) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0 <= areset; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia <= multTermOne_uid42_fpLogETest_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdreg_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_rdmux_q; ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 25, widthad_a => 4, numwords_a => 9, width_b => 25, widthad_b => 4, numwords_b => 9, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_reset0, clock1 => clk, address_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq, address_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_aa, data_a => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_ia ); ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_iq(24 downto 0); --ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg(DELAY,452) ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg : dspba_delay GENERIC MAP ( width => 25, depth => 1 ) PORT MAP ( xin => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_replace_mem_q, xout => ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q, ena => en(0), clk => clk, aclr => areset ); --postPEMul_uid43_fpLogETest(MULT,42)@12 postPEMul_uid43_fpLogETest_pr <= SIGNED(postPEMul_uid43_fpLogETest_a) * SIGNED(postPEMul_uid43_fpLogETest_b); postPEMul_uid43_fpLogETest_component: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN postPEMul_uid43_fpLogETest_a <= (others => '0'); postPEMul_uid43_fpLogETest_b <= (others => '0'); postPEMul_uid43_fpLogETest_s1 <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN postPEMul_uid43_fpLogETest_a <= ld_multTermOne_uid42_fpLogETest_q_to_postPEMul_uid43_fpLogETest_a_outputreg_q; postPEMul_uid43_fpLogETest_b <= reg_peOR_uid37_fpLogETest_0_to_postPEMul_uid43_fpLogETest_1_q; postPEMul_uid43_fpLogETest_s1 <= STD_LOGIC_VECTOR(postPEMul_uid43_fpLogETest_pr); END IF; END IF; END PROCESS; postPEMul_uid43_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN postPEMul_uid43_fpLogETest_q <= (others => '0'); ELSIF(clk'EVENT AND clk = '1') THEN IF (en = "1") THEN postPEMul_uid43_fpLogETest_q <= postPEMul_uid43_fpLogETest_s1; END IF; END IF; END PROCESS; --highBBits_uid47_fpLogETest(BITSELECT,46)@15 highBBits_uid47_fpLogETest_in <= postPEMul_uid43_fpLogETest_q; highBBits_uid47_fpLogETest_b <= highBBits_uid47_fpLogETest_in(50 downto 21); --wideZero_uid44_fpLogETest(CONSTANT,43) wideZero_uid44_fpLogETest_q <= "00000000000000000000000000000000000"; --cstBias_uid9_fpLogETest(CONSTANT,8) cstBias_uid9_fpLogETest_q <= "01111111"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor(LOGICAL,448) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q <= not (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_a or ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_b); --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top(CONSTANT,444) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q <= "01011"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp(LOGICAL,445) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_mem_top_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q); ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q <= "1" when ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_a = ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_b else "0"; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg(REG,446) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmp_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena(REG,449) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_nor_q = "1") THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd(LOGICAL,450) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_sticky_ena_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b <= en; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_a and ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_b; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt(COUNTER,440) -- every=1, low=0, high=11, step=1, init=1 ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= TO_UNSIGNED(1,4); ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i = 10 THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '1'; ELSE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_eq = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i - 11; ELSE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_i,4)); --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg(REG,441) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux(MUX,442) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s <= en; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux: PROCESS (ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q, ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q) BEGIN CASE ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_s IS WHEN "0" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q; WHEN "1" => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdcnt_q; WHEN OTHERS => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem(DUALMEM,439) ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0 <= areset; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia <= expX_uid6_fpLogETest_b; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdreg_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_rdmux_q; ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 8, widthad_a => 4, numwords_a => 12, width_b => 8, widthad_b => 4, numwords_b => 12, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_reset0, clock1 => clk, address_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq, address_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_aa, data_a => ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_ia ); ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_iq(7 downto 0); --e_uid29_fpLogETest(SUB,28)@13 e_uid29_fpLogETest_a <= STD_LOGIC_VECTOR("0" & ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_replace_mem_q); e_uid29_fpLogETest_b <= STD_LOGIC_VECTOR("0" & cstBias_uid9_fpLogETest_q); e_uid29_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(e_uid29_fpLogETest_a) - UNSIGNED(e_uid29_fpLogETest_b)); e_uid29_fpLogETest_q <= e_uid29_fpLogETest_o(8 downto 0); --xv0_uid90_constMult(BITSELECT,89)@13 xv0_uid90_constMult_in <= e_uid29_fpLogETest_q(5 downto 0); xv0_uid90_constMult_b <= xv0_uid90_constMult_in(5 downto 0); --p0_uid93_constMult(LOOKUP,92)@13 p0_uid93_constMult: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN p0_uid93_constMult_q <= "0000000000000000000000000000000000"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (xv0_uid90_constMult_b) IS WHEN "000000" => p0_uid93_constMult_q <= "0000000000000000000000000000000000"; WHEN "000001" => p0_uid93_constMult_q <= "0000001011000101110010000110000000"; WHEN "000010" => p0_uid93_constMult_q <= "0000010110001011100100001100000000"; WHEN "000011" => p0_uid93_constMult_q <= "0000100001010001010110010010000000"; WHEN "000100" => p0_uid93_constMult_q <= "0000101100010111001000011000000000"; WHEN "000101" => p0_uid93_constMult_q <= "0000110111011100111010011110000000"; WHEN "000110" => p0_uid93_constMult_q <= "0001000010100010101100100100000000"; WHEN "000111" => p0_uid93_constMult_q <= "0001001101101000011110101010000000"; WHEN "001000" => p0_uid93_constMult_q <= "0001011000101110010000110000000000"; WHEN "001001" => p0_uid93_constMult_q <= "0001100011110100000010110110000000"; WHEN "001010" => p0_uid93_constMult_q <= "0001101110111001110100111100000000"; WHEN "001011" => p0_uid93_constMult_q <= "0001111001111111100111000010000000"; WHEN "001100" => p0_uid93_constMult_q <= "0010000101000101011001001000000000"; WHEN "001101" => p0_uid93_constMult_q <= "0010010000001011001011001110000000"; WHEN "001110" => p0_uid93_constMult_q <= "0010011011010000111101010100000000"; WHEN "001111" => p0_uid93_constMult_q <= "0010100110010110101111011010000000"; WHEN "010000" => p0_uid93_constMult_q <= "0010110001011100100001100000000000"; WHEN "010001" => p0_uid93_constMult_q <= "0010111100100010010011100110000000"; WHEN "010010" => p0_uid93_constMult_q <= "0011000111101000000101101100000000"; WHEN "010011" => p0_uid93_constMult_q <= "0011010010101101110111110010000000"; WHEN "010100" => p0_uid93_constMult_q <= "0011011101110011101001111000000000"; WHEN "010101" => p0_uid93_constMult_q <= "0011101000111001011011111110000000"; WHEN "010110" => p0_uid93_constMult_q <= "0011110011111111001110000100000000"; WHEN "010111" => p0_uid93_constMult_q <= "0011111111000101000000001010000000"; WHEN "011000" => p0_uid93_constMult_q <= "0100001010001010110010010000000000"; WHEN "011001" => p0_uid93_constMult_q <= "0100010101010000100100010110000000"; WHEN "011010" => p0_uid93_constMult_q <= "0100100000010110010110011100000000"; WHEN "011011" => p0_uid93_constMult_q <= "0100101011011100001000100010000000"; WHEN "011100" => p0_uid93_constMult_q <= "0100110110100001111010101000000000"; WHEN "011101" => p0_uid93_constMult_q <= "0101000001100111101100101110000000"; WHEN "011110" => p0_uid93_constMult_q <= "0101001100101101011110110100000000"; WHEN "011111" => p0_uid93_constMult_q <= "0101010111110011010000111010000000"; WHEN "100000" => p0_uid93_constMult_q <= "0101100010111001000011000000000000"; WHEN "100001" => p0_uid93_constMult_q <= "0101101101111110110101000110000000"; WHEN "100010" => p0_uid93_constMult_q <= "0101111001000100100111001100000000"; WHEN "100011" => p0_uid93_constMult_q <= "0110000100001010011001010010000000"; WHEN "100100" => p0_uid93_constMult_q <= "0110001111010000001011011000000000"; WHEN "100101" => p0_uid93_constMult_q <= "0110011010010101111101011110000000"; WHEN "100110" => p0_uid93_constMult_q <= "0110100101011011101111100100000000"; WHEN "100111" => p0_uid93_constMult_q <= "0110110000100001100001101010000000"; WHEN "101000" => p0_uid93_constMult_q <= "0110111011100111010011110000000000"; WHEN "101001" => p0_uid93_constMult_q <= "0111000110101101000101110110000000"; WHEN "101010" => p0_uid93_constMult_q <= "0111010001110010110111111100000000"; WHEN "101011" => p0_uid93_constMult_q <= "0111011100111000101010000010000000"; WHEN "101100" => p0_uid93_constMult_q <= "0111100111111110011100001000000000"; WHEN "101101" => p0_uid93_constMult_q <= "0111110011000100001110001110000000"; WHEN "101110" => p0_uid93_constMult_q <= "0111111110001010000000010100000000"; WHEN "101111" => p0_uid93_constMult_q <= "1000001001001111110010011010000000"; WHEN "110000" => p0_uid93_constMult_q <= "1000010100010101100100100000000000"; WHEN "110001" => p0_uid93_constMult_q <= "1000011111011011010110100110000000"; WHEN "110010" => p0_uid93_constMult_q <= "1000101010100001001000101100000000"; WHEN "110011" => p0_uid93_constMult_q <= "1000110101100110111010110010000000"; WHEN "110100" => p0_uid93_constMult_q <= "1001000000101100101100111000000000"; WHEN "110101" => p0_uid93_constMult_q <= "1001001011110010011110111110000000"; WHEN "110110" => p0_uid93_constMult_q <= "1001010110111000010001000100000000"; WHEN "110111" => p0_uid93_constMult_q <= "1001100001111110000011001010000000"; WHEN "111000" => p0_uid93_constMult_q <= "1001101101000011110101010000000000"; WHEN "111001" => p0_uid93_constMult_q <= "1001111000001001100111010110000000"; WHEN "111010" => p0_uid93_constMult_q <= "1010000011001111011001011100000000"; WHEN "111011" => p0_uid93_constMult_q <= "1010001110010101001011100010000000"; WHEN "111100" => p0_uid93_constMult_q <= "1010011001011010111101101000000000"; WHEN "111101" => p0_uid93_constMult_q <= "1010100100100000101111101110000000"; WHEN "111110" => p0_uid93_constMult_q <= "1010101111100110100001110100000000"; WHEN "111111" => p0_uid93_constMult_q <= "1010111010101100010011111010000000"; WHEN OTHERS => p0_uid93_constMult_q <= "0000000000000000000000000000000000"; END CASE; END IF; END PROCESS; --xv1_uid91_constMult(BITSELECT,90)@13 xv1_uid91_constMult_in <= e_uid29_fpLogETest_q; xv1_uid91_constMult_b <= xv1_uid91_constMult_in(8 downto 6); --p1_uid92_constMult(LOOKUP,91)@13 p1_uid92_constMult: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN p1_uid92_constMult_q <= "0000000000000000000000000000000000000"; ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN CASE (xv1_uid91_constMult_b) IS WHEN "000" => p1_uid92_constMult_q <= "0000000000000000000000000000000000000"; WHEN "001" => p1_uid92_constMult_q <= "0001011000101110010000110000000000000"; WHEN "010" => p1_uid92_constMult_q <= "0010110001011100100001100000000000000"; WHEN "011" => p1_uid92_constMult_q <= "0100001010001010110010010000000000000"; WHEN "100" => p1_uid92_constMult_q <= "1010011101000110111101000000000000000"; WHEN "101" => p1_uid92_constMult_q <= "1011110101110101001101110000000000000"; WHEN "110" => p1_uid92_constMult_q <= "1101001110100011011110100000000000000"; WHEN "111" => p1_uid92_constMult_q <= "1110100111010001101111010000000000000"; WHEN OTHERS => p1_uid92_constMult_q <= "0000000000000000000000000000000000000"; END CASE; END IF; END PROCESS; --lev1_a0_uid94_constMult(ADD,93)@14 lev1_a0_uid94_constMult_a <= STD_LOGIC_VECTOR((38 downto 37 => p1_uid92_constMult_q(36)) & p1_uid92_constMult_q); lev1_a0_uid94_constMult_b <= STD_LOGIC_VECTOR('0' & "0000" & p0_uid93_constMult_q); lev1_a0_uid94_constMult_o <= STD_LOGIC_VECTOR(SIGNED(lev1_a0_uid94_constMult_a) + SIGNED(lev1_a0_uid94_constMult_b)); lev1_a0_uid94_constMult_q <= lev1_a0_uid94_constMult_o(37 downto 0); --sR_uid95_constMult(BITSELECT,94)@14 sR_uid95_constMult_in <= lev1_a0_uid94_constMult_q(36 downto 0); sR_uid95_constMult_b <= sR_uid95_constMult_in(36 downto 2); --ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b(DELAY,254)@0 ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b : dspba_delay GENERIC MAP ( width => 1, depth => 14 ) PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --addTermOne_uid45_fpLogETest(MUX,44)@14 addTermOne_uid45_fpLogETest_s <= ld_c_uid31_fpLogETest_q_to_addTermOne_uid45_fpLogETest_b_q; addTermOne_uid45_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN addTermOne_uid45_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN CASE addTermOne_uid45_fpLogETest_s IS WHEN "0" => addTermOne_uid45_fpLogETest_q <= sR_uid95_constMult_b; WHEN "1" => addTermOne_uid45_fpLogETest_q <= wideZero_uid44_fpLogETest_q; WHEN OTHERS => addTermOne_uid45_fpLogETest_q <= (others => '0'); END CASE; END IF; END IF; END PROCESS; --sumAHighB_uid48_fpLogETest(ADD,47)@15 sumAHighB_uid48_fpLogETest_a <= STD_LOGIC_VECTOR((35 downto 35 => addTermOne_uid45_fpLogETest_q(34)) & addTermOne_uid45_fpLogETest_q); sumAHighB_uid48_fpLogETest_b <= STD_LOGIC_VECTOR((35 downto 30 => highBBits_uid47_fpLogETest_b(29)) & highBBits_uid47_fpLogETest_b); sumAHighB_uid48_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(sumAHighB_uid48_fpLogETest_a) + SIGNED(sumAHighB_uid48_fpLogETest_b)); sumAHighB_uid48_fpLogETest_q <= sumAHighB_uid48_fpLogETest_o(35 downto 0); --lowRangeB_uid46_fpLogETest(BITSELECT,45)@15 lowRangeB_uid46_fpLogETest_in <= postPEMul_uid43_fpLogETest_q(20 downto 0); lowRangeB_uid46_fpLogETest_b <= lowRangeB_uid46_fpLogETest_in(20 downto 0); --finalSum_uid46_uid49_fpLogETest(BITJOIN,48)@15 finalSum_uid46_uid49_fpLogETest_q <= sumAHighB_uid48_fpLogETest_q & lowRangeB_uid46_fpLogETest_b; --FullSumAB56_uid50_fpLogETest(BITSELECT,49)@15 FullSumAB56_uid50_fpLogETest_in <= finalSum_uid46_uid49_fpLogETest_q; FullSumAB56_uid50_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_in(56 downto 56); --notC_uid71_fpLogETest(LOGICAL,70)@15 notC_uid71_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q; notC_uid71_fpLogETest_q <= not notC_uid71_fpLogETest_a; --signTerm2_uid72_fpLogETest(LOGICAL,71)@15 signTerm2_uid72_fpLogETest_a <= notC_uid71_fpLogETest_q; signTerm2_uid72_fpLogETest_b <= FullSumAB56_uid50_fpLogETest_b; signTerm2_uid72_fpLogETest_q <= signTerm2_uid72_fpLogETest_a and signTerm2_uid72_fpLogETest_b; --ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a(DELAY,285)@0 ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => c_uid31_fpLogETest_q, xout => ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRC1_uid73_fpLogETest(LOGICAL,72)@15 signRC1_uid73_fpLogETest_a <= ld_c_uid31_fpLogETest_q_to_notC_uid71_fpLogETest_a_q; signRC1_uid73_fpLogETest_b <= signTerm2_uid72_fpLogETest_q; signRC1_uid73_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN signRC1_uid73_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN signRC1_uid73_fpLogETest_q <= signRC1_uid73_fpLogETest_a or signRC1_uid73_fpLogETest_b; END IF; END PROCESS; --cstAllZWF_uid8_fpLogETest(CONSTANT,7) cstAllZWF_uid8_fpLogETest_q <= "00000000000000000000000"; --fracXIsZero_uid20_fpLogETest(LOGICAL,19)@0 fracXIsZero_uid20_fpLogETest_a <= frac_uid19_fpLogETest_b; fracXIsZero_uid20_fpLogETest_b <= cstAllZWF_uid8_fpLogETest_q; fracXIsZero_uid20_fpLogETest_q <= "1" when fracXIsZero_uid20_fpLogETest_a = fracXIsZero_uid20_fpLogETest_b else "0"; --InvFracXIsZero_uid22_fpLogETest(LOGICAL,21)@0 InvFracXIsZero_uid22_fpLogETest_a <= fracXIsZero_uid20_fpLogETest_q; InvFracXIsZero_uid22_fpLogETest_q <= not InvFracXIsZero_uid22_fpLogETest_a; --cstAllOWE_uid12_fpLogETest(CONSTANT,11) cstAllOWE_uid12_fpLogETest_q <= "11111111"; --expXIsMax_uid18_fpLogETest(LOGICAL,17)@0 expXIsMax_uid18_fpLogETest_a <= expX_uid6_fpLogETest_b; expXIsMax_uid18_fpLogETest_b <= cstAllOWE_uid12_fpLogETest_q; expXIsMax_uid18_fpLogETest_q <= "1" when expXIsMax_uid18_fpLogETest_a = expXIsMax_uid18_fpLogETest_b else "0"; --exc_N_uid23_fpLogETest(LOGICAL,22)@0 exc_N_uid23_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q; exc_N_uid23_fpLogETest_b <= InvFracXIsZero_uid22_fpLogETest_q; exc_N_uid23_fpLogETest_q <= exc_N_uid23_fpLogETest_a and exc_N_uid23_fpLogETest_b; --InvExc_N_uid24_fpLogETest(LOGICAL,23)@0 InvExc_N_uid24_fpLogETest_a <= exc_N_uid23_fpLogETest_q; InvExc_N_uid24_fpLogETest_q <= not InvExc_N_uid24_fpLogETest_a; --exc_I_uid21_fpLogETest(LOGICAL,20)@0 exc_I_uid21_fpLogETest_a <= expXIsMax_uid18_fpLogETest_q; exc_I_uid21_fpLogETest_b <= fracXIsZero_uid20_fpLogETest_q; exc_I_uid21_fpLogETest_q <= exc_I_uid21_fpLogETest_a and exc_I_uid21_fpLogETest_b; --InvExc_I_uid25_fpLogETest(LOGICAL,24)@0 InvExc_I_uid25_fpLogETest_a <= exc_I_uid21_fpLogETest_q; InvExc_I_uid25_fpLogETest_q <= not InvExc_I_uid25_fpLogETest_a; --cstAllZWE_uid14_fpLogETest(CONSTANT,13) cstAllZWE_uid14_fpLogETest_q <= "00000000"; --expXIsZero_uid16_fpLogETest(LOGICAL,15)@0 expXIsZero_uid16_fpLogETest_a <= expX_uid6_fpLogETest_b; expXIsZero_uid16_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q; expXIsZero_uid16_fpLogETest_q <= "1" when expXIsZero_uid16_fpLogETest_a = expXIsZero_uid16_fpLogETest_b else "0"; --InvExpXIsZero_uid26_fpLogETest(LOGICAL,25)@0 InvExpXIsZero_uid26_fpLogETest_a <= expXIsZero_uid16_fpLogETest_q; InvExpXIsZero_uid26_fpLogETest_q <= not InvExpXIsZero_uid26_fpLogETest_a; --exc_R_uid27_fpLogETest(LOGICAL,26)@0 exc_R_uid27_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q; exc_R_uid27_fpLogETest_b <= InvExc_I_uid25_fpLogETest_q; exc_R_uid27_fpLogETest_c <= InvExc_N_uid24_fpLogETest_q; exc_R_uid27_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN exc_R_uid27_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN exc_R_uid27_fpLogETest_q <= exc_R_uid27_fpLogETest_a and exc_R_uid27_fpLogETest_b and exc_R_uid27_fpLogETest_c; END IF; END PROCESS; --ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a(DELAY,290)@1 ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => exc_R_uid27_fpLogETest_q, xout => ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --signRC11_uid74_fpLogETest(LOGICAL,73)@16 signRC11_uid74_fpLogETest_a <= ld_exc_R_uid27_fpLogETest_q_to_signRC11_uid74_fpLogETest_a_q; signRC11_uid74_fpLogETest_b <= signRC1_uid73_fpLogETest_q; signRC11_uid74_fpLogETest_q <= signRC11_uid74_fpLogETest_a and signRC11_uid74_fpLogETest_b; --reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1(REG,220)@0 reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q <= expXIsZero_uid16_fpLogETest_q; END IF; END IF; END PROCESS; --ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a(DELAY,292)@1 ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q, xout => ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --signR_uid75_fpLogETest(LOGICAL,74)@16 signR_uid75_fpLogETest_a <= ld_reg_expXIsZero_uid16_fpLogETest_0_to_signR_uid75_fpLogETest_1_q_to_signR_uid75_fpLogETest_a_q; signR_uid75_fpLogETest_b <= signRC11_uid74_fpLogETest_q; signR_uid75_fpLogETest_q <= signR_uid75_fpLogETest_a or signR_uid75_fpLogETest_b; --signX_uid7_fpLogETest(BITSELECT,6)@0 signX_uid7_fpLogETest_in <= a; signX_uid7_fpLogETest_b <= signX_uid7_fpLogETest_in(31 downto 31); --negNonZero_uid69_fpLogETest(LOGICAL,68)@0 negNonZero_uid69_fpLogETest_a <= InvExpXIsZero_uid26_fpLogETest_q; negNonZero_uid69_fpLogETest_b <= signX_uid7_fpLogETest_b; negNonZero_uid69_fpLogETest_q <= negNonZero_uid69_fpLogETest_a and negNonZero_uid69_fpLogETest_b; --excRNaN_uid70_fpLogETest(LOGICAL,69)@0 excRNaN_uid70_fpLogETest_a <= negNonZero_uid69_fpLogETest_q; excRNaN_uid70_fpLogETest_b <= exc_N_uid23_fpLogETest_q; excRNaN_uid70_fpLogETest_q <= excRNaN_uid70_fpLogETest_a or excRNaN_uid70_fpLogETest_b; --ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a(DELAY,294)@0 ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a : dspba_delay GENERIC MAP ( width => 1, depth => 15 ) PORT MAP ( xin => excRNaN_uid70_fpLogETest_q, xout => ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q, ena => en(0), clk => clk, aclr => areset ); --InvExcRNaN_uid76_fpLogETest(LOGICAL,75)@15 InvExcRNaN_uid76_fpLogETest_a <= ld_excRNaN_uid70_fpLogETest_q_to_InvExcRNaN_uid76_fpLogETest_a_q; InvExcRNaN_uid76_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN InvExcRNaN_uid76_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND VCC_q = "1") THEN InvExcRNaN_uid76_fpLogETest_q <= not InvExcRNaN_uid76_fpLogETest_a; END IF; END PROCESS; --signRFull_uid77_fpLogETest(LOGICAL,76)@16 signRFull_uid77_fpLogETest_a <= InvExcRNaN_uid76_fpLogETest_q; signRFull_uid77_fpLogETest_b <= signR_uid75_fpLogETest_q; signRFull_uid77_fpLogETest_q <= signRFull_uid77_fpLogETest_a and signRFull_uid77_fpLogETest_b; --ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c(DELAY,307)@16 ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c : dspba_delay GENERIC MAP ( width => 1, depth => 5 ) PORT MAP ( xin => signRFull_uid77_fpLogETest_q, xout => ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset ); --zs_uid113_countZ_uid54_fpLogETest(CONSTANT,112) zs_uid113_countZ_uid54_fpLogETest_q <= "00000000000000000000000000000000"; --ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b(DELAY,266)@15 ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => FullSumAB56_uid50_fpLogETest_b, xout => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --finalSumOneComp_uid52_fpLogETest(LOGICAL,51)@15 finalSumOneComp_uid52_fpLogETest_a <= finalSum_uid46_uid49_fpLogETest_q; finalSumOneComp_uid52_fpLogETest_b <= STD_LOGIC_VECTOR((56 downto 1 => FullSumAB56_uid50_fpLogETest_b(0)) & FullSumAB56_uid50_fpLogETest_b); finalSumOneComp_uid52_fpLogETest: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN finalSumOneComp_uid52_fpLogETest_q <= (others => '0'); ELSIF (clk'EVENT AND clk = '1' AND en = "1") THEN finalSumOneComp_uid52_fpLogETest_q <= finalSumOneComp_uid52_fpLogETest_a xor finalSumOneComp_uid52_fpLogETest_b; END IF; END PROCESS; --finalSumAbs_uid53_fpLogETest(ADD,52)@16 finalSumAbs_uid53_fpLogETest_a <= STD_LOGIC_VECTOR((57 downto 57 => finalSumOneComp_uid52_fpLogETest_q(56)) & finalSumOneComp_uid52_fpLogETest_q); finalSumAbs_uid53_fpLogETest_b <= STD_LOGIC_VECTOR((57 downto 1 => ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q(0)) & ld_FullSumAB56_uid50_fpLogETest_b_to_finalSumAbs_uid53_fpLogETest_b_q); finalSumAbs_uid53_fpLogETest_o <= STD_LOGIC_VECTOR(SIGNED(finalSumAbs_uid53_fpLogETest_a) + SIGNED(finalSumAbs_uid53_fpLogETest_b)); finalSumAbs_uid53_fpLogETest_q <= finalSumAbs_uid53_fpLogETest_o(57 downto 0); --rVStage_uid114_countZ_uid54_fpLogETest(BITSELECT,113)@16 rVStage_uid114_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q; rVStage_uid114_countZ_uid54_fpLogETest_b <= rVStage_uid114_countZ_uid54_fpLogETest_in(57 downto 26); --reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1(REG,202)@16 reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q <= rVStage_uid114_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vCount_uid115_countZ_uid54_fpLogETest(LOGICAL,114)@17 vCount_uid115_countZ_uid54_fpLogETest_a <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q; vCount_uid115_countZ_uid54_fpLogETest_b <= zs_uid113_countZ_uid54_fpLogETest_q; vCount_uid115_countZ_uid54_fpLogETest_q <= "1" when vCount_uid115_countZ_uid54_fpLogETest_a = vCount_uid115_countZ_uid54_fpLogETest_b else "0"; --ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f(DELAY,366)@17 ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f : dspba_delay GENERIC MAP ( width => 1, depth => 2 ) PORT MAP ( xin => vCount_uid115_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q, ena => en(0), clk => clk, aclr => areset ); --zs_uid121_countZ_uid54_fpLogETest(CONSTANT,120) zs_uid121_countZ_uid54_fpLogETest_q <= "0000000000000000"; --vStage_uid117_countZ_uid54_fpLogETest(BITSELECT,116)@16 vStage_uid117_countZ_uid54_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(25 downto 0); vStage_uid117_countZ_uid54_fpLogETest_b <= vStage_uid117_countZ_uid54_fpLogETest_in(25 downto 0); --mO_uid116_countZ_uid54_fpLogETest(CONSTANT,115) mO_uid116_countZ_uid54_fpLogETest_q <= "111111"; --cStage_uid118_countZ_uid54_fpLogETest(BITJOIN,117)@16 cStage_uid118_countZ_uid54_fpLogETest_q <= vStage_uid117_countZ_uid54_fpLogETest_b & mO_uid116_countZ_uid54_fpLogETest_q; --reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3(REG,204)@16 reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= "00000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q <= cStage_uid118_countZ_uid54_fpLogETest_q; END IF; END IF; END PROCESS; --vStagei_uid120_countZ_uid54_fpLogETest(MUX,119)@17 vStagei_uid120_countZ_uid54_fpLogETest_s <= vCount_uid115_countZ_uid54_fpLogETest_q; vStagei_uid120_countZ_uid54_fpLogETest: PROCESS (vStagei_uid120_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q, reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q) BEGIN CASE vStagei_uid120_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_rVStage_uid114_countZ_uid54_fpLogETest_0_to_vCount_uid115_countZ_uid54_fpLogETest_1_q; WHEN "1" => vStagei_uid120_countZ_uid54_fpLogETest_q <= reg_cStage_uid118_countZ_uid54_fpLogETest_0_to_vStagei_uid120_countZ_uid54_fpLogETest_3_q; WHEN OTHERS => vStagei_uid120_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid122_countZ_uid54_fpLogETest(BITSELECT,121)@17 rVStage_uid122_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q; rVStage_uid122_countZ_uid54_fpLogETest_b <= rVStage_uid122_countZ_uid54_fpLogETest_in(31 downto 16); --reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1(REG,205)@17 reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q <= rVStage_uid122_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vCount_uid123_countZ_uid54_fpLogETest(LOGICAL,122)@18 vCount_uid123_countZ_uid54_fpLogETest_a <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q; vCount_uid123_countZ_uid54_fpLogETest_b <= zs_uid121_countZ_uid54_fpLogETest_q; vCount_uid123_countZ_uid54_fpLogETest_q <= "1" when vCount_uid123_countZ_uid54_fpLogETest_a = vCount_uid123_countZ_uid54_fpLogETest_b else "0"; --ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e(DELAY,365)@18 ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e : dspba_delay GENERIC MAP ( width => 1, depth => 1 ) PORT MAP ( xin => vCount_uid123_countZ_uid54_fpLogETest_q, xout => ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q, ena => en(0), clk => clk, aclr => areset ); --vStage_uid124_countZ_uid54_fpLogETest(BITSELECT,123)@17 vStage_uid124_countZ_uid54_fpLogETest_in <= vStagei_uid120_countZ_uid54_fpLogETest_q(15 downto 0); vStage_uid124_countZ_uid54_fpLogETest_b <= vStage_uid124_countZ_uid54_fpLogETest_in(15 downto 0); --reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3(REG,207)@17 reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= "0000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q <= vStage_uid124_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vStagei_uid126_countZ_uid54_fpLogETest(MUX,125)@18 vStagei_uid126_countZ_uid54_fpLogETest_s <= vCount_uid123_countZ_uid54_fpLogETest_q; vStagei_uid126_countZ_uid54_fpLogETest: PROCESS (vStagei_uid126_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q, reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q) BEGIN CASE vStagei_uid126_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_rVStage_uid122_countZ_uid54_fpLogETest_0_to_vCount_uid123_countZ_uid54_fpLogETest_1_q; WHEN "1" => vStagei_uid126_countZ_uid54_fpLogETest_q <= reg_vStage_uid124_countZ_uid54_fpLogETest_0_to_vStagei_uid126_countZ_uid54_fpLogETest_3_q; WHEN OTHERS => vStagei_uid126_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid128_countZ_uid54_fpLogETest(BITSELECT,127)@18 rVStage_uid128_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q; rVStage_uid128_countZ_uid54_fpLogETest_b <= rVStage_uid128_countZ_uid54_fpLogETest_in(15 downto 8); --vCount_uid129_countZ_uid54_fpLogETest(LOGICAL,128)@18 vCount_uid129_countZ_uid54_fpLogETest_a <= rVStage_uid128_countZ_uid54_fpLogETest_b; vCount_uid129_countZ_uid54_fpLogETest_b <= cstAllZWE_uid14_fpLogETest_q; vCount_uid129_countZ_uid54_fpLogETest_q <= "1" when vCount_uid129_countZ_uid54_fpLogETest_a = vCount_uid129_countZ_uid54_fpLogETest_b else "0"; --reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3(REG,211)@18 reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q <= vCount_uid129_countZ_uid54_fpLogETest_q; END IF; END IF; END PROCESS; --zs_uid133_countZ_uid54_fpLogETest(CONSTANT,132) zs_uid133_countZ_uid54_fpLogETest_q <= "0000"; --vStage_uid130_countZ_uid54_fpLogETest(BITSELECT,129)@18 vStage_uid130_countZ_uid54_fpLogETest_in <= vStagei_uid126_countZ_uid54_fpLogETest_q(7 downto 0); vStage_uid130_countZ_uid54_fpLogETest_b <= vStage_uid130_countZ_uid54_fpLogETest_in(7 downto 0); --vStagei_uid132_countZ_uid54_fpLogETest(MUX,131)@18 vStagei_uid132_countZ_uid54_fpLogETest_s <= vCount_uid129_countZ_uid54_fpLogETest_q; vStagei_uid132_countZ_uid54_fpLogETest: PROCESS (vStagei_uid132_countZ_uid54_fpLogETest_s, en, rVStage_uid128_countZ_uid54_fpLogETest_b, vStage_uid130_countZ_uid54_fpLogETest_b) BEGIN CASE vStagei_uid132_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid132_countZ_uid54_fpLogETest_q <= rVStage_uid128_countZ_uid54_fpLogETest_b; WHEN "1" => vStagei_uid132_countZ_uid54_fpLogETest_q <= vStage_uid130_countZ_uid54_fpLogETest_b; WHEN OTHERS => vStagei_uid132_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid134_countZ_uid54_fpLogETest(BITSELECT,133)@18 rVStage_uid134_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q; rVStage_uid134_countZ_uid54_fpLogETest_b <= rVStage_uid134_countZ_uid54_fpLogETest_in(7 downto 4); --reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1(REG,208)@18 reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q <= rVStage_uid134_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vCount_uid135_countZ_uid54_fpLogETest(LOGICAL,134)@19 vCount_uid135_countZ_uid54_fpLogETest_a <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q; vCount_uid135_countZ_uid54_fpLogETest_b <= zs_uid133_countZ_uid54_fpLogETest_q; vCount_uid135_countZ_uid54_fpLogETest_q <= "1" when vCount_uid135_countZ_uid54_fpLogETest_a = vCount_uid135_countZ_uid54_fpLogETest_b else "0"; --vStage_uid136_countZ_uid54_fpLogETest(BITSELECT,135)@18 vStage_uid136_countZ_uid54_fpLogETest_in <= vStagei_uid132_countZ_uid54_fpLogETest_q(3 downto 0); vStage_uid136_countZ_uid54_fpLogETest_b <= vStage_uid136_countZ_uid54_fpLogETest_in(3 downto 0); --reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3(REG,210)@18 reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= "0000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q <= vStage_uid136_countZ_uid54_fpLogETest_b; END IF; END IF; END PROCESS; --vStagei_uid138_countZ_uid54_fpLogETest(MUX,137)@19 vStagei_uid138_countZ_uid54_fpLogETest_s <= vCount_uid135_countZ_uid54_fpLogETest_q; vStagei_uid138_countZ_uid54_fpLogETest: PROCESS (vStagei_uid138_countZ_uid54_fpLogETest_s, en, reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q, reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q) BEGIN CASE vStagei_uid138_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_rVStage_uid134_countZ_uid54_fpLogETest_0_to_vCount_uid135_countZ_uid54_fpLogETest_1_q; WHEN "1" => vStagei_uid138_countZ_uid54_fpLogETest_q <= reg_vStage_uid136_countZ_uid54_fpLogETest_0_to_vStagei_uid138_countZ_uid54_fpLogETest_3_q; WHEN OTHERS => vStagei_uid138_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid140_countZ_uid54_fpLogETest(BITSELECT,139)@19 rVStage_uid140_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q; rVStage_uid140_countZ_uid54_fpLogETest_b <= rVStage_uid140_countZ_uid54_fpLogETest_in(3 downto 2); --vCount_uid141_countZ_uid54_fpLogETest(LOGICAL,140)@19 vCount_uid141_countZ_uid54_fpLogETest_a <= rVStage_uid140_countZ_uid54_fpLogETest_b; vCount_uid141_countZ_uid54_fpLogETest_b <= z2_uid40_fpLogETest_q; vCount_uid141_countZ_uid54_fpLogETest_q <= "1" when vCount_uid141_countZ_uid54_fpLogETest_a = vCount_uid141_countZ_uid54_fpLogETest_b else "0"; --vStage_uid142_countZ_uid54_fpLogETest(BITSELECT,141)@19 vStage_uid142_countZ_uid54_fpLogETest_in <= vStagei_uid138_countZ_uid54_fpLogETest_q(1 downto 0); vStage_uid142_countZ_uid54_fpLogETest_b <= vStage_uid142_countZ_uid54_fpLogETest_in(1 downto 0); --vStagei_uid144_countZ_uid54_fpLogETest(MUX,143)@19 vStagei_uid144_countZ_uid54_fpLogETest_s <= vCount_uid141_countZ_uid54_fpLogETest_q; vStagei_uid144_countZ_uid54_fpLogETest: PROCESS (vStagei_uid144_countZ_uid54_fpLogETest_s, en, rVStage_uid140_countZ_uid54_fpLogETest_b, vStage_uid142_countZ_uid54_fpLogETest_b) BEGIN CASE vStagei_uid144_countZ_uid54_fpLogETest_s IS WHEN "0" => vStagei_uid144_countZ_uid54_fpLogETest_q <= rVStage_uid140_countZ_uid54_fpLogETest_b; WHEN "1" => vStagei_uid144_countZ_uid54_fpLogETest_q <= vStage_uid142_countZ_uid54_fpLogETest_b; WHEN OTHERS => vStagei_uid144_countZ_uid54_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --rVStage_uid146_countZ_uid54_fpLogETest(BITSELECT,145)@19 rVStage_uid146_countZ_uid54_fpLogETest_in <= vStagei_uid144_countZ_uid54_fpLogETest_q; rVStage_uid146_countZ_uid54_fpLogETest_b <= rVStage_uid146_countZ_uid54_fpLogETest_in(1 downto 1); --vCount_uid147_countZ_uid54_fpLogETest(LOGICAL,146)@19 vCount_uid147_countZ_uid54_fpLogETest_a <= rVStage_uid146_countZ_uid54_fpLogETest_b; vCount_uid147_countZ_uid54_fpLogETest_b <= GND_q; vCount_uid147_countZ_uid54_fpLogETest_q <= "1" when vCount_uid147_countZ_uid54_fpLogETest_a = vCount_uid147_countZ_uid54_fpLogETest_b else "0"; --r_uid148_countZ_uid54_fpLogETest(BITJOIN,147)@19 r_uid148_countZ_uid54_fpLogETest_q <= ld_vCount_uid115_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_f_q & ld_vCount_uid123_countZ_uid54_fpLogETest_q_to_r_uid148_countZ_uid54_fpLogETest_e_q & reg_vCount_uid129_countZ_uid54_fpLogETest_0_to_r_uid148_countZ_uid54_fpLogETest_3_q & vCount_uid135_countZ_uid54_fpLogETest_q & vCount_uid141_countZ_uid54_fpLogETest_q & vCount_uid147_countZ_uid54_fpLogETest_q; --reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1(REG,218)@19 reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= "000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q <= r_uid148_countZ_uid54_fpLogETest_q; END IF; END IF; END PROCESS; --cstMSBFinalSumPBias_uid56_fpLogETest(CONSTANT,55) cstMSBFinalSumPBias_uid56_fpLogETest_q <= "010001001"; --expRExt_uid57_fpLogETest(SUB,56)@20 expRExt_uid57_fpLogETest_a <= STD_LOGIC_VECTOR("0" & cstMSBFinalSumPBias_uid56_fpLogETest_q); expRExt_uid57_fpLogETest_b <= STD_LOGIC_VECTOR("0000" & reg_r_uid148_countZ_uid54_fpLogETest_0_to_expRExt_uid57_fpLogETest_1_q); expRExt_uid57_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expRExt_uid57_fpLogETest_a) - UNSIGNED(expRExt_uid57_fpLogETest_b)); expRExt_uid57_fpLogETest_q <= expRExt_uid57_fpLogETest_o(9 downto 0); --LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest(BITSELECT,179)@20 LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(54 downto 0); LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_in(54 downto 0); --leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest(CONSTANT,178) leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q <= "000"; --leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest(BITJOIN,180)@20 leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q <= LeftShiftStage154dto0_uid180_normVal_uid55_fpLogETest_b & leftShiftStage2Idx3Pad3_uid179_normVal_uid55_fpLogETest_q; --LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest(BITSELECT,176)@20 LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(55 downto 0); LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_in(55 downto 0); --leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest(BITJOIN,177)@20 leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q <= LeftShiftStage155dto0_uid177_normVal_uid55_fpLogETest_b & z2_uid40_fpLogETest_q; --LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest(BITSELECT,173)@20 LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q(56 downto 0); LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_in(56 downto 0); --leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest(BITJOIN,174)@20 leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q <= LeftShiftStage156dto0_uid174_normVal_uid55_fpLogETest_b & GND_q; --X9dto0_uid158_normVal_uid55_fpLogETest(BITSELECT,157)@16 X9dto0_uid158_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(9 downto 0); X9dto0_uid158_normVal_uid55_fpLogETest_b <= X9dto0_uid158_normVal_uid55_fpLogETest_in(9 downto 0); --ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg(DELAY,467) ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg : dspba_delay GENERIC MAP ( width => 10, depth => 1 ) PORT MAP ( xin => X9dto0_uid158_normVal_uid55_fpLogETest_b, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b(DELAY,371)@16 ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b : dspba_delay GENERIC MAP ( width => 10, depth => 2 ) PORT MAP ( xin => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest(CONSTANT,156) leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q <= "000000000000000000000000000000000000000000000000"; --leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest(BITJOIN,158)@19 leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q <= ld_X9dto0_uid158_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_b_q & leftShiftStage0Idx3Pad48_uid157_normVal_uid55_fpLogETest_q; --ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg(DELAY,466) ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg : dspba_delay GENERIC MAP ( width => 26, depth => 1 ) PORT MAP ( xin => vStage_uid117_countZ_uid54_fpLogETest_b, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b(DELAY,369)@16 ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b : dspba_delay GENERIC MAP ( width => 26, depth => 2 ) PORT MAP ( xin => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest(BITJOIN,155)@19 leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q <= ld_vStage_uid117_countZ_uid54_fpLogETest_b_to_leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_b_q & zs_uid113_countZ_uid54_fpLogETest_q; --X41dto0_uid152_normVal_uid55_fpLogETest(BITSELECT,151)@16 X41dto0_uid152_normVal_uid55_fpLogETest_in <= finalSumAbs_uid53_fpLogETest_q(41 downto 0); X41dto0_uid152_normVal_uid55_fpLogETest_b <= X41dto0_uid152_normVal_uid55_fpLogETest_in(41 downto 0); --ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg(DELAY,465) ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg : dspba_delay GENERIC MAP ( width => 42, depth => 1 ) PORT MAP ( xin => X41dto0_uid152_normVal_uid55_fpLogETest_b, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b(DELAY,368)@16 ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b : dspba_delay GENERIC MAP ( width => 42, depth => 2 ) PORT MAP ( xin => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_inputreg_q, xout => ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest(BITJOIN,152)@19 leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q <= ld_X41dto0_uid152_normVal_uid55_fpLogETest_b_to_leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_b_q & zs_uid121_countZ_uid54_fpLogETest_q; --ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg(DELAY,468) ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg : dspba_delay GENERIC MAP ( width => 58, depth => 1 ) PORT MAP ( xin => finalSumAbs_uid53_fpLogETest_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c(DELAY,374)@16 ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c : dspba_delay GENERIC MAP ( width => 58, depth => 2 ) PORT MAP ( xin => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_inputreg_q, xout => ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, ena => en(0), clk => clk, aclr => areset ); --leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest(BITSELECT,159)@19 leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q; leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_in(5 downto 4); --leftShiftStage0_uid161_normVal_uid55_fpLogETest(MUX,160)@19 leftShiftStage0_uid161_normVal_uid55_fpLogETest_s <= leftShiftStageSel5Dto4_uid160_normVal_uid55_fpLogETest_b; leftShiftStage0_uid161_normVal_uid55_fpLogETest: PROCESS (leftShiftStage0_uid161_normVal_uid55_fpLogETest_s, en, ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q, leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q, leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q, leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q) BEGIN CASE leftShiftStage0_uid161_normVal_uid55_fpLogETest_s IS WHEN "00" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= ld_finalSumAbs_uid53_fpLogETest_q_to_leftShiftStage0_uid161_normVal_uid55_fpLogETest_c_q; WHEN "01" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx1_uid153_normVal_uid55_fpLogETest_q; WHEN "10" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx2_uid156_normVal_uid55_fpLogETest_q; WHEN "11" => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= leftShiftStage0Idx3_uid159_normVal_uid55_fpLogETest_q; WHEN OTHERS => leftShiftStage0_uid161_normVal_uid55_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest(BITSELECT,168)@19 LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(45 downto 0); LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_in(45 downto 0); --leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest(CONSTANT,167) leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q <= "000000000000"; --leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest(BITJOIN,169)@19 leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q <= LeftShiftStage045dto0_uid169_normVal_uid55_fpLogETest_b & leftShiftStage1Idx3Pad12_uid168_normVal_uid55_fpLogETest_q; --reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5(REG,216)@19 reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q <= leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest(BITSELECT,165)@19 LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(49 downto 0); LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_in(49 downto 0); --leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest(BITJOIN,166)@19 leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q <= LeftShiftStage049dto0_uid166_normVal_uid55_fpLogETest_b & cstAllZWE_uid14_fpLogETest_q; --reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4(REG,215)@19 reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q <= leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest(BITSELECT,162)@19 LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q(53 downto 0); LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_in(53 downto 0); --leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest(BITJOIN,163)@19 leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q <= LeftShiftStage053dto0_uid163_normVal_uid55_fpLogETest_b & zs_uid133_countZ_uid54_fpLogETest_q; --reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3(REG,214)@19 reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q <= leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2(REG,213)@19 reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= "0000000000000000000000000000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q <= leftShiftStage0_uid161_normVal_uid55_fpLogETest_q; END IF; END IF; END PROCESS; --leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest(BITSELECT,170)@19 leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(3 downto 0); leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_in(3 downto 2); --reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1(REG,212)@19 reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_b; END IF; END IF; END PROCESS; --leftShiftStage1_uid172_normVal_uid55_fpLogETest(MUX,171)@20 leftShiftStage1_uid172_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel3Dto2_uid171_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_1_q; leftShiftStage1_uid172_normVal_uid55_fpLogETest: PROCESS (leftShiftStage1_uid172_normVal_uid55_fpLogETest_s, en, reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q, reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q, reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q, reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q) BEGIN CASE leftShiftStage1_uid172_normVal_uid55_fpLogETest_s IS WHEN "00" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage0_uid161_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_2_q; WHEN "01" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx1_uid164_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_3_q; WHEN "10" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx2_uid167_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_4_q; WHEN "11" => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= reg_leftShiftStage1Idx3_uid170_normVal_uid55_fpLogETest_0_to_leftShiftStage1_uid172_normVal_uid55_fpLogETest_5_q; WHEN OTHERS => leftShiftStage1_uid172_normVal_uid55_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest(BITSELECT,181)@19 leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in <= r_uid148_countZ_uid54_fpLogETest_q(1 downto 0); leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_in(1 downto 0); --reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1(REG,217)@19 reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= "00"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q <= leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_b; END IF; END IF; END PROCESS; --leftShiftStage2_uid183_normVal_uid55_fpLogETest(MUX,182)@20 leftShiftStage2_uid183_normVal_uid55_fpLogETest_s <= reg_leftShiftStageSel1Dto0_uid182_normVal_uid55_fpLogETest_0_to_leftShiftStage2_uid183_normVal_uid55_fpLogETest_1_q; leftShiftStage2_uid183_normVal_uid55_fpLogETest: PROCESS (leftShiftStage2_uid183_normVal_uid55_fpLogETest_s, en, leftShiftStage1_uid172_normVal_uid55_fpLogETest_q, leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q, leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q, leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q) BEGIN CASE leftShiftStage2_uid183_normVal_uid55_fpLogETest_s IS WHEN "00" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage1_uid172_normVal_uid55_fpLogETest_q; WHEN "01" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx1_uid175_normVal_uid55_fpLogETest_q; WHEN "10" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx2_uid178_normVal_uid55_fpLogETest_q; WHEN "11" => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= leftShiftStage2Idx3_uid181_normVal_uid55_fpLogETest_q; WHEN OTHERS => leftShiftStage2_uid183_normVal_uid55_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --fracR_uid58_fpLogETest(BITSELECT,57)@20 fracR_uid58_fpLogETest_in <= leftShiftStage2_uid183_normVal_uid55_fpLogETest_q(56 downto 0); fracR_uid58_fpLogETest_b <= fracR_uid58_fpLogETest_in(56 downto 33); --expFracConc_uid59_fpLogETest(BITJOIN,58)@20 expFracConc_uid59_fpLogETest_q <= expRExt_uid57_fpLogETest_q & fracR_uid58_fpLogETest_b; --reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0(REG,219)@20 reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= "0000000000000000000000000000000000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q <= expFracConc_uid59_fpLogETest_q; END IF; END IF; END PROCESS; --expFracPostRnd_uid60_fpLogETest(ADD,59)@21 expFracPostRnd_uid60_fpLogETest_a <= STD_LOGIC_VECTOR("0" & reg_expFracConc_uid59_fpLogETest_0_to_expFracPostRnd_uid60_fpLogETest_0_q); expFracPostRnd_uid60_fpLogETest_b <= STD_LOGIC_VECTOR("0000000000000000000000000000000000" & VCC_q); expFracPostRnd_uid60_fpLogETest_o <= STD_LOGIC_VECTOR(UNSIGNED(expFracPostRnd_uid60_fpLogETest_a) + UNSIGNED(expFracPostRnd_uid60_fpLogETest_b)); expFracPostRnd_uid60_fpLogETest_q <= expFracPostRnd_uid60_fpLogETest_o(34 downto 0); --expR_uid62_fpLogETest(BITSELECT,61)@21 expR_uid62_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(31 downto 0); expR_uid62_fpLogETest_b <= expR_uid62_fpLogETest_in(31 downto 24); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor(LOGICAL,493) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a <= ld_expX_uid6_fpLogETest_b_to_e_uid29_fpLogETest_a_notEnable_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q <= not (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_a or ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_b); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top(CONSTANT,489) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q <= "010001"; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp(LOGICAL,490) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_mem_top_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b <= STD_LOGIC_VECTOR("0" & ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q); ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q <= "1" when ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_a = ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_b else "0"; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg(REG,491) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= "0"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmp_q; END IF; END IF; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena(REG,494) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= "0"; ELSIF rising_edge(clk) THEN IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_nor_q = "1") THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_cmpReg_q; END IF; END IF; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd(LOGICAL,495) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_sticky_ena_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b <= en; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_a and ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_b; --InvSignX_uid65_fpLogETest(LOGICAL,64)@0 InvSignX_uid65_fpLogETest_a <= signX_uid7_fpLogETest_b; InvSignX_uid65_fpLogETest_q <= not InvSignX_uid65_fpLogETest_a; --excRInfC1_uid66_fpLogETest(LOGICAL,65)@0 excRInfC1_uid66_fpLogETest_a <= exc_I_uid21_fpLogETest_q; excRInfC1_uid66_fpLogETest_b <= InvSignX_uid65_fpLogETest_q; excRInfC1_uid66_fpLogETest_q <= excRInfC1_uid66_fpLogETest_a and excRInfC1_uid66_fpLogETest_b; --excRInf_uid67_fpLogETest(LOGICAL,66)@0 excRInf_uid67_fpLogETest_a <= excRInfC1_uid66_fpLogETest_q; excRInf_uid67_fpLogETest_b <= expXIsZero_uid16_fpLogETest_q; excRInf_uid67_fpLogETest_q <= excRInf_uid67_fpLogETest_a or excRInf_uid67_fpLogETest_b; --FPOne_uid63_fpLogETest(BITJOIN,62)@0 FPOne_uid63_fpLogETest_q <= GND_q & cstBias_uid9_fpLogETest_q & cstAllZWF_uid8_fpLogETest_q; --excRZero_uid64_fpLogETest(LOGICAL,63)@0 excRZero_uid64_fpLogETest_a <= a; excRZero_uid64_fpLogETest_b <= FPOne_uid63_fpLogETest_q; excRZero_uid64_fpLogETest_q <= "1" when excRZero_uid64_fpLogETest_a = excRZero_uid64_fpLogETest_b else "0"; --concExc_uid78_fpLogETest(BITJOIN,77)@0 concExc_uid78_fpLogETest_q <= excRNaN_uid70_fpLogETest_q & excRInf_uid67_fpLogETest_q & excRZero_uid64_fpLogETest_q; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg(DELAY,483) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg : dspba_delay GENERIC MAP ( width => 3, depth => 1 ) PORT MAP ( xin => concExc_uid78_fpLogETest_q, xout => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q, ena => en(0), clk => clk, aclr => areset ); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt(COUNTER,485) -- every=1, low=0, high=17, step=1, init=1 ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= TO_UNSIGNED(1,5); ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0'; ELSIF (clk'EVENT AND clk = '1') THEN IF (en = "1") THEN IF ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i = 16 THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '1'; ELSE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq <= '0'; END IF; IF (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_eq = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i - 17; ELSE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i + 1; END IF; END IF; END IF; END PROCESS; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q <= STD_LOGIC_VECTOR(RESIZE(ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_i,5)); --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg(REG,486) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= "00000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q; END IF; END IF; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux(MUX,487) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s <= en; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux: PROCESS (ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q, ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q) BEGIN CASE ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_s IS WHEN "0" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q; WHEN "1" => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdcnt_q; WHEN OTHERS => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q <= (others => '0'); END CASE; END PROCESS; --ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem(DUALMEM,484) ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0 <= areset; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_inputreg_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdreg_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_rdmux_q; ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_dmem : altsyncram GENERIC MAP ( ram_block_type => "MLAB", operation_mode => "DUAL_PORT", width_a => 3, widthad_a => 5, numwords_a => 18, width_b => 3, widthad_b => 5, numwords_b => 18, lpm_type => "altsyncram", width_byteena_a => 1, indata_reg_b => "CLOCK0", wrcontrol_wraddress_reg_b => "CLOCK0", rdcontrol_reg_b => "CLOCK0", byteena_reg_b => "CLOCK0", outdata_reg_b => "CLOCK1", outdata_aclr_b => "CLEAR1", address_reg_b => "CLOCK0", clock_enable_input_a => "NORMAL", clock_enable_input_b => "NORMAL", clock_enable_output_b => "NORMAL", read_during_write_mode_mixed_ports => "DONT_CARE", power_up_uninitialized => "FALSE", init_file => "UNUSED", intended_device_family => "Stratix V" ) PORT MAP ( clocken1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_enaAnd_q(0), clocken0 => '1', wren_a => en(0), clock0 => clk, aclr1 => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_reset0, clock1 => clk, address_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ab, -- data_b => (others => '0'), q_b => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq, address_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_aa, data_a => ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_ia ); ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_iq(2 downto 0); --reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0(REG,193)@20 reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0: PROCESS (clk, areset) BEGIN IF (areset = '1') THEN reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= "000"; ELSIF rising_edge(clk) THEN IF (en = "1") THEN reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q <= ld_concExc_uid78_fpLogETest_q_to_reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_a_replace_mem_q; END IF; END IF; END PROCESS; --excREnc_uid79_fpLogETest(LOOKUP,78)@21 excREnc_uid79_fpLogETest: PROCESS (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q) BEGIN -- Begin reserved scope level CASE (reg_concExc_uid78_fpLogETest_0_to_excREnc_uid79_fpLogETest_0_q) IS WHEN "000" => excREnc_uid79_fpLogETest_q <= "01"; WHEN "001" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "010" => excREnc_uid79_fpLogETest_q <= "10"; WHEN "011" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "100" => excREnc_uid79_fpLogETest_q <= "11"; WHEN "101" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "110" => excREnc_uid79_fpLogETest_q <= "00"; WHEN "111" => excREnc_uid79_fpLogETest_q <= "00"; WHEN OTHERS => excREnc_uid79_fpLogETest_q <= (others => '-'); END CASE; -- End reserved scope level END PROCESS; --expRPostExc_uid87_fpLogETest(MUX,86)@21 expRPostExc_uid87_fpLogETest_s <= excREnc_uid79_fpLogETest_q; expRPostExc_uid87_fpLogETest: PROCESS (expRPostExc_uid87_fpLogETest_s, en, cstAllZWE_uid14_fpLogETest_q, expR_uid62_fpLogETest_b, cstAllOWE_uid12_fpLogETest_q, cstAllOWE_uid12_fpLogETest_q) BEGIN CASE expRPostExc_uid87_fpLogETest_s IS WHEN "00" => expRPostExc_uid87_fpLogETest_q <= cstAllZWE_uid14_fpLogETest_q; WHEN "01" => expRPostExc_uid87_fpLogETest_q <= expR_uid62_fpLogETest_b; WHEN "10" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q; WHEN "11" => expRPostExc_uid87_fpLogETest_q <= cstAllOWE_uid12_fpLogETest_q; WHEN OTHERS => expRPostExc_uid87_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --oneFracRPostExc2_uid80_fpLogETest(CONSTANT,79) oneFracRPostExc2_uid80_fpLogETest_q <= "00000000000000000000001"; --fracR_uid61_fpLogETest(BITSELECT,60)@21 fracR_uid61_fpLogETest_in <= expFracPostRnd_uid60_fpLogETest_q(23 downto 0); fracR_uid61_fpLogETest_b <= fracR_uid61_fpLogETest_in(23 downto 1); --fracRPostExc_uid83_fpLogETest(MUX,82)@21 fracRPostExc_uid83_fpLogETest_s <= excREnc_uid79_fpLogETest_q; fracRPostExc_uid83_fpLogETest: PROCESS (fracRPostExc_uid83_fpLogETest_s, en, cstAllZWF_uid8_fpLogETest_q, fracR_uid61_fpLogETest_b, cstAllZWF_uid8_fpLogETest_q, oneFracRPostExc2_uid80_fpLogETest_q) BEGIN CASE fracRPostExc_uid83_fpLogETest_s IS WHEN "00" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q; WHEN "01" => fracRPostExc_uid83_fpLogETest_q <= fracR_uid61_fpLogETest_b; WHEN "10" => fracRPostExc_uid83_fpLogETest_q <= cstAllZWF_uid8_fpLogETest_q; WHEN "11" => fracRPostExc_uid83_fpLogETest_q <= oneFracRPostExc2_uid80_fpLogETest_q; WHEN OTHERS => fracRPostExc_uid83_fpLogETest_q <= (others => '0'); END CASE; END PROCESS; --RLn_uid88_fpLogETest(BITJOIN,87)@21 RLn_uid88_fpLogETest_q <= ld_signRFull_uid77_fpLogETest_q_to_RLn_uid88_fpLogETest_c_q & expRPostExc_uid87_fpLogETest_q & fracRPostExc_uid83_fpLogETest_q; --xOut(GPOUT,4)@21 q <= RLn_uid88_fpLogETest_q; end normal;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/dp_lnlut18.vhd

10

143091

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** DP_LNLUT18.VHD *** --*** *** --*** Function: Look Up Table - LN() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_lnlut18 IS PORT ( add : IN STD_LOGIC_VECTOR (9 DOWNTO 1); inv : OUT STD_LOGIC_VECTOR (18 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (11 DOWNTO 1) ); END dp_lnlut18; ARCHITECTURE rtl OF dp_lnlut18 IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "000000000" => inv <= conv_std_logic_vector(131072,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); WHEN "000000001" => inv <= conv_std_logic_vector(262143,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(31,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(268391765,28); logexp <= conv_std_logic_vector(1005,11); WHEN "000000010" => inv <= conv_std_logic_vector(262141,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8388752,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(327672,28); logexp <= conv_std_logic_vector(1006,11); WHEN "000000011" => inv <= conv_std_logic_vector(262139,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4194504,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(666254,28); logexp <= conv_std_logic_vector(1007,11); WHEN "000000100" => inv <= conv_std_logic_vector(262137,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12583304,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1889508,28); logexp <= conv_std_logic_vector(1007,11); WHEN "000000101" => inv <= conv_std_logic_vector(262135,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2097476,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1982311,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000000110" => inv <= conv_std_logic_vector(262133,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6291940,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3642366,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000000111" => inv <= conv_std_logic_vector(262131,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10486436,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5990414,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000001000" => inv <= conv_std_logic_vector(262129,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14680964,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9223005,28); logexp <= conv_std_logic_vector(1008,11); WHEN "000001001" => inv <= conv_std_logic_vector(262127,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1049154,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6702808,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001010" => inv <= conv_std_logic_vector(262125,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3146450,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9367390,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001011" => inv <= conv_std_logic_vector(262123,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5243762,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12637977,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001100" => inv <= conv_std_logic_vector(262121,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7341090,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(16612827,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001101" => inv <= conv_std_logic_vector(262119,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9438434,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21341043,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001110" => inv <= conv_std_logic_vector(262117,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11535794,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26871724,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000001111" => inv <= conv_std_logic_vector(262115,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13633170,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33303113,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000010000" => inv <= conv_std_logic_vector(262113,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15730562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40684301,28); logexp <= conv_std_logic_vector(1009,11); WHEN "000010001" => inv <= conv_std_logic_vector(262111,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(525377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24532187,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010010" => inv <= conv_std_logic_vector(262109,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1574089,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29270780,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010011" => inv <= conv_std_logic_vector(262107,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2622809,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34582468,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010100" => inv <= conv_std_logic_vector(262105,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3671537,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40499978,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010101" => inv <= conv_std_logic_vector(262103,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4720273,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47056037,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010110" => inv <= conv_std_logic_vector(262101,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5769017,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54283367,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000010111" => inv <= conv_std_logic_vector(262099,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6817769,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(62214689,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011000" => inv <= conv_std_logic_vector(262097,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7866529,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70882721,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011001" => inv <= conv_std_logic_vector(262095,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8915297,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80328369,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011010" => inv <= conv_std_logic_vector(262093,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9964073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90567968,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011011" => inv <= conv_std_logic_vector(262091,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11012857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101650610,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011100" => inv <= conv_std_logic_vector(262089,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12061649,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113592623,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011101" => inv <= conv_std_logic_vector(262087,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13110449,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126443095,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011110" => inv <= conv_std_logic_vector(262085,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14159257,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140226541,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000011111" => inv <= conv_std_logic_vector(262083,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15208073,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(154975663,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000100000" => inv <= conv_std_logic_vector(262081,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16256897,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170731353,28); logexp <= conv_std_logic_vector(1010,11); WHEN "000100001" => inv <= conv_std_logic_vector(262079,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(264256,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227972692,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100010" => inv <= conv_std_logic_vector(262077,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(788676,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236897961,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100011" => inv <= conv_std_logic_vector(262075,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1313100,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(246371462,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100100" => inv <= conv_std_logic_vector(262073,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1837528,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256409541,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100101" => inv <= conv_std_logic_vector(262071,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2361960,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(267028543,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100110" => inv <= conv_std_logic_vector(262069,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2886397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9813450,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000100111" => inv <= conv_std_logic_vector(262067,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3410837,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21647423,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101000" => inv <= conv_std_logic_vector(262065,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3935281,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34111345,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101001" => inv <= conv_std_logic_vector(262063,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4459729,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47221557,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101010" => inv <= conv_std_logic_vector(262061,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4984181,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60998494,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101011" => inv <= conv_std_logic_vector(262059,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5508637,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75454397,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101100" => inv <= conv_std_logic_vector(262057,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6033097,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90605604,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101101" => inv <= conv_std_logic_vector(262055,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6557561,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106472545,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101110" => inv <= conv_std_logic_vector(262053,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7082029,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123067460,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000101111" => inv <= conv_std_logic_vector(262051,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7606501,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140410777,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110000" => inv <= conv_std_logic_vector(262049,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8130977,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(158510638,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110001" => inv <= conv_std_logic_vector(262047,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8655457,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177395659,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110010" => inv <= conv_std_logic_vector(262045,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9179941,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197069887,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110011" => inv <= conv_std_logic_vector(262043,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9704429,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217561932,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110100" => inv <= conv_std_logic_vector(262041,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10228921,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238875840,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110101" => inv <= conv_std_logic_vector(262039,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10753417,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261036127,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110110" => inv <= conv_std_logic_vector(262037,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11277918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15623661,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000110111" => inv <= conv_std_logic_vector(262035,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11802422,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39521584,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111000" => inv <= conv_std_logic_vector(262033,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12326930,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64314859,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111001" => inv <= conv_std_logic_vector(262031,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12851442,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90015713,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111010" => inv <= conv_std_logic_vector(262029,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13375958,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(116644561,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111011" => inv <= conv_std_logic_vector(262027,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13900478,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144213628,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111100" => inv <= conv_std_logic_vector(262025,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14425002,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(172743328,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111101" => inv <= conv_std_logic_vector(262023,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14949530,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(202249979,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111110" => inv <= conv_std_logic_vector(262021,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15474062,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232745802,28); logexp <= conv_std_logic_vector(1011,11); WHEN "000111111" => inv <= conv_std_logic_vector(262019,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15998598,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264251207,28); logexp <= conv_std_logic_vector(1011,11); WHEN "001000000" => inv <= conv_std_logic_vector(262017,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16523139,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28347053,28); logexp <= conv_std_logic_vector(1011,11); WHEN "001000001" => inv <= conv_std_logic_vector(262015,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(135233,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165175963,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000010" => inv <= conv_std_logic_vector(262013,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(397507,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182491979,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000011" => inv <= conv_std_logic_vector(262011,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(659783,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(200343364,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000100" => inv <= conv_std_logic_vector(262009,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(922061,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(218740319,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000101" => inv <= conv_std_logic_vector(262007,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1184341,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237688954,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000110" => inv <= conv_std_logic_vector(262005,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1446623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257201513,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001000111" => inv <= conv_std_logic_vector(262003,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1708908,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(8846602,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001000" => inv <= conv_std_logic_vector(262001,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1971194,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29507379,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001001" => inv <= conv_std_logic_vector(261999,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2233482,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50752445,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001010" => inv <= conv_std_logic_vector(261997,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2495772,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72592000,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001011" => inv <= conv_std_logic_vector(261995,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2758064,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(95036240,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001100" => inv <= conv_std_logic_vector(261993,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3020358,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118089223,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001101" => inv <= conv_std_logic_vector(261991,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3282654,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141761145,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001110" => inv <= conv_std_logic_vector(261989,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3544952,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166062202,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001001111" => inv <= conv_std_logic_vector(261987,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3807252,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190996450,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010000" => inv <= conv_std_logic_vector(261985,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4069554,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216576129,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010001" => inv <= conv_std_logic_vector(261983,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4331858,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242805295,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010010" => inv <= conv_std_logic_vector(261981,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4594165,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1260730,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010011" => inv <= conv_std_logic_vector(261979,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4856473,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28821495,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010100" => inv <= conv_std_logic_vector(261977,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5118783,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57056185,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010101" => inv <= conv_std_logic_vector(261975,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5381095,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85977038,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010110" => inv <= conv_std_logic_vector(261973,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5643409,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115590153,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001010111" => inv <= conv_std_logic_vector(261971,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5905725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145903675,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011000" => inv <= conv_std_logic_vector(261969,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6168043,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(176927792,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011001" => inv <= conv_std_logic_vector(261967,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6430363,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208668602,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011010" => inv <= conv_std_logic_vector(261965,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6692685,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241134248,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011011" => inv <= conv_std_logic_vector(261963,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6955010,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5901507,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011100" => inv <= conv_std_logic_vector(261961,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7217336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39843294,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011101" => inv <= conv_std_logic_vector(261959,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7479664,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(74536387,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011110" => inv <= conv_std_logic_vector(261957,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7741994,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109988926,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001011111" => inv <= conv_std_logic_vector(261955,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8004326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146207004,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100000" => inv <= conv_std_logic_vector(261953,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8266660,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183200806,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100001" => inv <= conv_std_logic_vector(261951,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8528996,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(220976425,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100010" => inv <= conv_std_logic_vector(261949,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8791334,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259546091,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100011" => inv <= conv_std_logic_vector(261947,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9053675,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30478393,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100100" => inv <= conv_std_logic_vector(261945,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9316017,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70652380,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100101" => inv <= conv_std_logic_vector(261943,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9578361,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111644825,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100110" => inv <= conv_std_logic_vector(261941,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9840707,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153461817,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001100111" => inv <= conv_std_logic_vector(261939,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10103055,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196109445,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101000" => inv <= conv_std_logic_vector(261937,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10365405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239597890,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101001" => inv <= conv_std_logic_vector(261935,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10627758,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(15499830,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101010" => inv <= conv_std_logic_vector(261933,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10890112,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60696356,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101011" => inv <= conv_std_logic_vector(261931,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11152468,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106756053,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101100" => inv <= conv_std_logic_vector(261929,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11414826,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153689099,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101101" => inv <= conv_std_logic_vector(261927,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11677186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(201505673,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101110" => inv <= conv_std_logic_vector(261925,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11939548,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250209813,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001101111" => inv <= conv_std_logic_vector(261923,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12201913,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31378287,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110000" => inv <= conv_std_logic_vector(261921,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12464279,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81888089,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110001" => inv <= conv_std_logic_vector(261919,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12726647,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133313941,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110010" => inv <= conv_std_logic_vector(261917,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12989017,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185659877,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110011" => inv <= conv_std_logic_vector(261915,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13251389,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238938120,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110100" => inv <= conv_std_logic_vector(261913,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13513764,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(24721341,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110101" => inv <= conv_std_logic_vector(261911,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13776140,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79886532,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110110" => inv <= conv_std_logic_vector(261909,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14038518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136006365,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001110111" => inv <= conv_std_logic_vector(261907,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14300898,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193091012,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111000" => inv <= conv_std_logic_vector(261905,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14563280,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251146552,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111001" => inv <= conv_std_logic_vector(261903,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14825665,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41747701,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111010" => inv <= conv_std_logic_vector(261901,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15088051,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(101773495,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111011" => inv <= conv_std_logic_vector(261899,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15350439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162796601,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111100" => inv <= conv_std_logic_vector(261897,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15612829,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224823097,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111101" => inv <= conv_std_logic_vector(261895,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15875222,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19427696,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111110" => inv <= conv_std_logic_vector(261893,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16137616,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83489431,28); logexp <= conv_std_logic_vector(1012,11); WHEN "001111111" => inv <= conv_std_logic_vector(261891,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16400012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148578923,28); logexp <= conv_std_logic_vector(1012,11); WHEN "010000000" => inv <= conv_std_logic_vector(261889,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16662410,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(214708384,28); logexp <= conv_std_logic_vector(1012,11); WHEN "010000001" => inv <= conv_std_logic_vector(261887,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(73797,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140941945,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000010" => inv <= conv_std_logic_vector(261885,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(204998,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(175055756,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000011" => inv <= conv_std_logic_vector(261883,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(336200,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209701733,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000100" => inv <= conv_std_logic_vector(261881,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(467403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244882910,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000101" => inv <= conv_std_logic_vector(261879,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(598608,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12167891,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000110" => inv <= conv_std_logic_vector(261877,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(729813,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48431647,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010000111" => inv <= conv_std_logic_vector(261875,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(861019,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85243804,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001000" => inv <= conv_std_logic_vector(261873,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(992226,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122607396,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001001" => inv <= conv_std_logic_vector(261871,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1123434,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160526482,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001010" => inv <= conv_std_logic_vector(261869,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1254643,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199006142,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001011" => inv <= conv_std_logic_vector(261867,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1385853,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(238049411,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001100" => inv <= conv_std_logic_vector(261865,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1517065,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(9224891,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001101" => inv <= conv_std_logic_vector(261863,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1648277,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49409594,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001110" => inv <= conv_std_logic_vector(261861,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1779490,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(90169054,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010001111" => inv <= conv_std_logic_vector(261859,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1910704,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131510396,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010000" => inv <= conv_std_logic_vector(261857,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2041919,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173435630,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010001" => inv <= conv_std_logic_vector(261855,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2173135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215949833,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010010" => inv <= conv_std_logic_vector(261853,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2304352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259057063,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010011" => inv <= conv_std_logic_vector(261851,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2435571,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34325917,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010100" => inv <= conv_std_logic_vector(261849,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2566790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78630340,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010101" => inv <= conv_std_logic_vector(261847,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2698010,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(123540976,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010110" => inv <= conv_std_logic_vector(261845,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2829231,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169060858,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010010111" => inv <= conv_std_logic_vector(261843,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2960453,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(215194037,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011000" => inv <= conv_std_logic_vector(261841,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3091676,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(261943547,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011001" => inv <= conv_std_logic_vector(261839,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3222901,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(40881052,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011010" => inv <= conv_std_logic_vector(261837,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3354126,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88878449,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011011" => inv <= conv_std_logic_vector(261835,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3485352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137506381,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011100" => inv <= conv_std_logic_vector(261833,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3616579,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186767878,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011101" => inv <= conv_std_logic_vector(261831,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3747807,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236666992,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011110" => inv <= conv_std_logic_vector(261829,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3879037,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(18774364,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010011111" => inv <= conv_std_logic_vector(261827,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4010267,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69961890,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100000" => inv <= conv_std_logic_vector(261825,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4141498,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121800212,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100001" => inv <= conv_std_logic_vector(261823,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4272730,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174293379,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100010" => inv <= conv_std_logic_vector(261821,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4403963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227445444,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100011" => inv <= conv_std_logic_vector(261819,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4535198,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12823978,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100100" => inv <= conv_std_logic_vector(261817,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4666433,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(67305989,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100101" => inv <= conv_std_logic_vector(261815,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4797669,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(122458025,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100110" => inv <= conv_std_logic_vector(261813,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4928906,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178285160,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010100111" => inv <= conv_std_logic_vector(261811,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5060144,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234791442,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101000" => inv <= conv_std_logic_vector(261809,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5191384,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(23545465,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101001" => inv <= conv_std_logic_vector(261807,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5322624,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(81422190,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101010" => inv <= conv_std_logic_vector(261805,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5453865,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(139991231,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101011" => inv <= conv_std_logic_vector(261803,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5585107,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199255616,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101100" => inv <= conv_std_logic_vector(261801,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5716350,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(259219392,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101101" => inv <= conv_std_logic_vector(261799,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5847595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51452173,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101110" => inv <= conv_std_logic_vector(261797,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5978840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(112827896,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010101111" => inv <= conv_std_logic_vector(261795,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6110086,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174915153,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110000" => inv <= conv_std_logic_vector(261793,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6241333,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237719013,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110001" => inv <= conv_std_logic_vector(261791,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6372582,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(32808067,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110010" => inv <= conv_std_logic_vector(261789,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6503831,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97057274,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110011" => inv <= conv_std_logic_vector(261787,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6635081,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162034200,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110100" => inv <= conv_std_logic_vector(261785,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6766332,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227743914,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110101" => inv <= conv_std_logic_vector(261783,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6897585,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25755007,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110110" => inv <= conv_std_logic_vector(261781,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7028838,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(92942434,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010110111" => inv <= conv_std_logic_vector(261779,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7160092,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160875808,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111000" => inv <= conv_std_logic_vector(261777,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7291347,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(229557128,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111001" => inv <= conv_std_logic_vector(261775,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7422604,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(30556006,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111010" => inv <= conv_std_logic_vector(261773,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7553861,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100748419,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111011" => inv <= conv_std_logic_vector(261771,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7685119,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171701934,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111100" => inv <= conv_std_logic_vector(261769,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7816378,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243420594,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111101" => inv <= conv_std_logic_vector(261767,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7947639,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47474008,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111110" => inv <= conv_std_logic_vector(261765,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8078900,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120736110,28); logexp <= conv_std_logic_vector(1013,11); WHEN "010111111" => inv <= conv_std_logic_vector(261763,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8210162,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194776508,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000000" => inv <= conv_std_logic_vector(261761,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8341426,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(1163789,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000001" => inv <= conv_std_logic_vector(261759,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8472690,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(76771885,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000010" => inv <= conv_std_logic_vector(261757,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8603955,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153170403,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000011" => inv <= conv_std_logic_vector(261755,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8735221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(230363387,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000100" => inv <= conv_std_logic_vector(261753,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8866489,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39919420,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000101" => inv <= conv_std_logic_vector(261751,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8997757,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118713456,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000110" => inv <= conv_std_logic_vector(261749,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9129026,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(198314080,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011000111" => inv <= conv_std_logic_vector(261747,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9260297,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10289876,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001000" => inv <= conv_std_logic_vector(261745,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9391568,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91515797,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001001" => inv <= conv_std_logic_vector(261743,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9522840,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173561448,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001010" => inv <= conv_std_logic_vector(261741,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9654113,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256429848,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001011" => inv <= conv_std_logic_vector(261739,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9785388,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71690601,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001100" => inv <= conv_std_logic_vector(261737,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9916663,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156217637,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001101" => inv <= conv_std_logic_vector(261735,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10047939,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(241580560,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001110" => inv <= conv_std_logic_vector(261733,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10179217,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(59346931,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011001111" => inv <= conv_std_logic_vector(261731,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10310495,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146392723,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010000" => inv <= conv_std_logic_vector(261729,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10441774,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234286516,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010001" => inv <= conv_std_logic_vector(261727,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10573055,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54596894,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010010" => inv <= conv_std_logic_vector(261725,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10704336,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144198805,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010011" => inv <= conv_std_logic_vector(261723,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10835618,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234660830,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010100" => inv <= conv_std_logic_vector(261721,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10966902,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57551551,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010101" => inv <= conv_std_logic_vector(261719,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11098186,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149745915,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010110" => inv <= conv_std_logic_vector(261717,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11229471,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242812504,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011010111" => inv <= conv_std_logic_vector(261715,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11360758,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68320919,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011000" => inv <= conv_std_logic_vector(261713,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11492045,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163146107,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011001" => inv <= conv_std_logic_vector(261711,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11623333,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258854605,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011010" => inv <= conv_std_logic_vector(261709,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11754623,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87018057,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011011" => inv <= conv_std_logic_vector(261707,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11885913,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184509366,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011100" => inv <= conv_std_logic_vector(261705,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12017205,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(14462677,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011101" => inv <= conv_std_logic_vector(261703,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12148497,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113752937,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011110" => inv <= conv_std_logic_vector(261701,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12279790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213947700,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011011111" => inv <= conv_std_logic_vector(261699,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12411085,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46617589,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100000" => inv <= conv_std_logic_vector(261697,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12542380,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(148636528,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100001" => inv <= conv_std_logic_vector(261695,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12673676,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251573093,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100010" => inv <= conv_std_logic_vector(261693,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12804974,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86995861,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100011" => inv <= conv_std_logic_vector(261691,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12936272,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191780799,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100100" => inv <= conv_std_logic_vector(261689,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13067572,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29060005,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100101" => inv <= conv_std_logic_vector(261687,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13198872,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135708424,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100110" => inv <= conv_std_logic_vector(261685,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13330173,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243295652,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011100111" => inv <= conv_std_logic_vector(261683,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13461476,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83390266,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101000" => inv <= conv_std_logic_vector(261681,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13592779,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(192867209,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101001" => inv <= conv_std_logic_vector(261679,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13724084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34858577,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101010" => inv <= conv_std_logic_vector(261677,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13855389,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(146240336,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101011" => inv <= conv_std_logic_vector(261675,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13986695,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258581058,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101100" => inv <= conv_std_logic_vector(261673,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14118003,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103450342,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101101" => inv <= conv_std_logic_vector(261671,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14249311,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(217721083,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101110" => inv <= conv_std_logic_vector(261669,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14380621,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(64528444,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011101111" => inv <= conv_std_logic_vector(261667,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14511931,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(180746345,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110000" => inv <= conv_std_logic_vector(261665,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14643243,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29508923,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110001" => inv <= conv_std_logic_vector(261663,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14774555,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(147690097,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110010" => inv <= conv_std_logic_vector(261661,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14905868,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266859463,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110011" => inv <= conv_std_logic_vector(261659,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15037183,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118585591,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110100" => inv <= conv_std_logic_vector(261657,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15168498,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239742400,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110101" => inv <= conv_std_logic_vector(261655,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15299815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93464027,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110110" => inv <= conv_std_logic_vector(261653,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15431132,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216625411,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011110111" => inv <= conv_std_logic_vector(261651,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15562451,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72360690,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111000" => inv <= conv_std_logic_vector(261649,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15693770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197542758,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111001" => inv <= conv_std_logic_vector(261647,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15825091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(55306773,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111010" => inv <= conv_std_logic_vector(261645,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15956412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(182526652,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111011" => inv <= conv_std_logic_vector(261643,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16087735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42335507,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111100" => inv <= conv_std_logic_vector(261641,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16219058,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(171609300,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111101" => inv <= conv_std_logic_vector(261639,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16350383,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33481142,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111110" => inv <= conv_std_logic_vector(261637,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16481708,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164824949,28); logexp <= conv_std_logic_vector(1013,11); WHEN "011111111" => inv <= conv_std_logic_vector(261635,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16613035,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28774856,28); logexp <= conv_std_logic_vector(1013,11); WHEN "100000000" => inv <= conv_std_logic_vector(261633,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16744362,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(162205798,28); logexp <= conv_std_logic_vector(1013,11); WHEN "100000001" => inv <= conv_std_logic_vector(261632,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97880094,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000010" => inv <= conv_std_logic_vector(261630,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(82069,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232492642,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000011" => inv <= conv_std_logic_vector(261628,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(147734,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233414771,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000100" => inv <= conv_std_logic_vector(261626,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(213400,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100649515,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000101" => inv <= conv_std_logic_vector(261624,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(279066,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102634341,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000110" => inv <= conv_std_logic_vector(261622,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(344732,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(239370238,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100000111" => inv <= conv_std_logic_vector(261620,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(410399,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(242424784,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001000" => inv <= conv_std_logic_vector(261618,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(476067,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111799989,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001001" => inv <= conv_std_logic_vector(261616,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(541735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(115933322,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001010" => inv <= conv_std_logic_vector(261614,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(607403,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254826281,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001011" => inv <= conv_std_logic_vector(261612,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(673072,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(260045933,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001100" => inv <= conv_std_logic_vector(261610,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(738742,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(131594288,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001101" => inv <= conv_std_logic_vector(261608,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(804412,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137909323,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001110" => inv <= conv_std_logic_vector(261606,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(870083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(10556570,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100001111" => inv <= conv_std_logic_vector(261604,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(935754,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17974519,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010000" => inv <= conv_std_logic_vector(261602,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1001425,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(160164667,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010001" => inv <= conv_std_logic_vector(261600,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1067097,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168694080,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010010" => inv <= conv_std_logic_vector(261598,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1132770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(43564256,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010011" => inv <= conv_std_logic_vector(261596,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1198443,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53213172,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010100" => inv <= conv_std_logic_vector(261594,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1264116,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(197642837,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010101" => inv <= conv_std_logic_vector(261592,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1329790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208419294,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010110" => inv <= conv_std_logic_vector(261590,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1395465,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85545574,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100010111" => inv <= conv_std_logic_vector(261588,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1461140,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97458630,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011000" => inv <= conv_std_logic_vector(261586,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1526815,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(244160472,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011001" => inv <= conv_std_logic_vector(261584,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1592491,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257217653,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011010" => inv <= conv_std_logic_vector(261582,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1658168,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(136632180,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011011" => inv <= conv_std_logic_vector(261580,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1723845,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(150842541,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011100" => inv <= conv_std_logic_vector(261578,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1789523,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31413754,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011101" => inv <= conv_std_logic_vector(261576,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1855201,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46784817,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011110" => inv <= conv_std_logic_vector(261574,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1920879,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(196956715,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100011111" => inv <= conv_std_logic_vector(261572,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(1986558,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213496513,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100000" => inv <= conv_std_logic_vector(261570,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2052238,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(96406727,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100001" => inv <= conv_std_logic_vector(261568,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2117918,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(114123801,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100010" => inv <= conv_std_logic_vector(261566,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2183598,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(266650763,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100011" => inv <= conv_std_logic_vector(261564,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2249280,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17118198,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100100" => inv <= conv_std_logic_vector(261562,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2314961,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(170834480,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100101" => inv <= conv_std_logic_vector(261560,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2380643,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(190931217,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100110" => inv <= conv_std_logic_vector(261558,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2446326,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(77410414,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100100111" => inv <= conv_std_logic_vector(261556,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2512009,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(98709023,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101000" => inv <= conv_std_logic_vector(261554,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2577692,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254830073,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101001" => inv <= conv_std_logic_vector(261552,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2643377,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(8903637,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101010" => inv <= conv_std_logic_vector(261550,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2709061,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166239111,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101011" => inv <= conv_std_logic_vector(261548,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2774746,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(189966567,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101100" => inv <= conv_std_logic_vector(261546,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2840432,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80089032,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101101" => inv <= conv_std_logic_vector(261544,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2906118,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(105043970,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101110" => inv <= conv_std_logic_vector(261542,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(2971804,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(264832874,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100101111" => inv <= conv_std_logic_vector(261540,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3037492,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22586838,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110000" => inv <= conv_std_logic_vector(261538,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3103179,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(183615258,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110001" => inv <= conv_std_logic_vector(261536,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3168867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211048205,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110010" => inv <= conv_std_logic_vector(261534,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3234556,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(104888194,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110011" => inv <= conv_std_logic_vector(261532,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3300245,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(133573199,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110100" => inv <= conv_std_logic_vector(261530,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3365935,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(28668746,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110101" => inv <= conv_std_logic_vector(261528,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3431625,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(58613318,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110110" => inv <= conv_std_logic_vector(261526,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3497315,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(223408408,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100110111" => inv <= conv_std_logic_vector(261524,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3563006,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(254621075,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111000" => inv <= conv_std_logic_vector(261522,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3628698,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152253325,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111001" => inv <= conv_std_logic_vector(261520,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3694390,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(184742106,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111010" => inv <= conv_std_logic_vector(261518,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3760083,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83654478,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111011" => inv <= conv_std_logic_vector(261516,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3825776,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(117428410,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111100" => inv <= conv_std_logic_vector(261514,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3891470,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(17629430,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111101" => inv <= conv_std_logic_vector(261512,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(3957164,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52695507,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111110" => inv <= conv_std_logic_vector(261510,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4022858,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(222629156,28); logexp <= conv_std_logic_vector(1014,11); WHEN "100111111" => inv <= conv_std_logic_vector(261508,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4088553,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258996925,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000000" => inv <= conv_std_logic_vector(261506,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4154249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161800305,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000001" => inv <= conv_std_logic_vector(261504,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4219945,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(199477266,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000010" => inv <= conv_std_logic_vector(261502,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4285642,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(103593845,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000011" => inv <= conv_std_logic_vector(261500,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4351339,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142588522,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000100" => inv <= conv_std_logic_vector(261498,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4417037,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(48026823,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000101" => inv <= conv_std_logic_vector(261496,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4482735,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(88347226,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000110" => inv <= conv_std_logic_vector(261494,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4548433,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(263551224,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101000111" => inv <= conv_std_logic_vector(261492,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4614133,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(36769906,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001000" => inv <= conv_std_logic_vector(261490,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4679832,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213312155,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001001" => inv <= conv_std_logic_vector(261488,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4745532,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(256309059,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001010" => inv <= conv_std_logic_vector(261486,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4811233,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(165762621,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001011" => inv <= conv_std_logic_vector(261484,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4876934,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210109787,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001100" => inv <= conv_std_logic_vector(261482,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(4942636,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120917613,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001101" => inv <= conv_std_logic_vector(261480,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5008338,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(166624068,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001110" => inv <= conv_std_logic_vector(261478,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5074041,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78795186,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101001111" => inv <= conv_std_logic_vector(261476,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5139744,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(125868425,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010000" => inv <= conv_std_logic_vector(261474,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5205448,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39410329,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010001" => inv <= conv_std_logic_vector(261472,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5271152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87859376,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010010" => inv <= conv_std_logic_vector(261470,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5336857,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(2781090,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010011" => inv <= conv_std_logic_vector(261468,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5402562,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52613438,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010100" => inv <= conv_std_logic_vector(261466,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5468267,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237358419,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010101" => inv <= conv_std_logic_vector(261464,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5533974,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(20147124,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010110" => inv <= conv_std_logic_vector(261462,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5599680,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206287919,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101010111" => inv <= conv_std_logic_vector(261460,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5665387,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(258912403,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011000" => inv <= conv_std_logic_vector(261458,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5731095,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(178022066,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011001" => inv <= conv_std_logic_vector(261456,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5796803,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232054873,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011010" => inv <= conv_std_logic_vector(261454,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5862512,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152577368,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011011" => inv <= conv_std_logic_vector(261452,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5928221,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(208027007,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011100" => inv <= conv_std_logic_vector(261450,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(5993931,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129969822,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011101" => inv <= conv_std_logic_vector(261448,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6059641,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186844290,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011110" => inv <= conv_std_logic_vector(261446,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6125352,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(110216442,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101011111" => inv <= conv_std_logic_vector(261444,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6191063,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168523735,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100000" => inv <= conv_std_logic_vector(261442,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6256775,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(93333220,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100001" => inv <= conv_std_logic_vector(261440,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6322487,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153082353,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100010" => inv <= conv_std_logic_vector(261438,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6388200,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(79337165,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100011" => inv <= conv_std_logic_vector(261436,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6453913,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140535621,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100100" => inv <= conv_std_logic_vector(261434,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6519627,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68244774,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100101" => inv <= conv_std_logic_vector(261432,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6585341,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130901057,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100110" => inv <= conv_std_logic_vector(261430,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6651056,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(60072032,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101100111" => inv <= conv_std_logic_vector(261428,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6716771,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(124194644,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101000" => inv <= conv_std_logic_vector(261426,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6782487,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(54835943,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101001" => inv <= conv_std_logic_vector(261424,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6848203,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120433383,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101010" => inv <= conv_std_logic_vector(261422,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6913920,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(52552996,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101011" => inv <= conv_std_logic_vector(261421,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(6946778,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203440839,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101100" => inv <= conv_std_logic_vector(261419,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7012496,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(69566203,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101101" => inv <= conv_std_logic_vector(261417,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7078214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70654699,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101110" => inv <= conv_std_logic_vector(261415,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7143932,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(206708322,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101101111" => inv <= conv_std_logic_vector(261413,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7209651,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209294124,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110000" => inv <= conv_std_logic_vector(261411,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7275371,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(78413591,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110001" => inv <= conv_std_logic_vector(261409,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7341091,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82505197,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110010" => inv <= conv_std_logic_vector(261407,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7406811,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(221569406,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110011" => inv <= conv_std_logic_vector(261405,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7472532,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(227174289,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110100" => inv <= conv_std_logic_vector(261403,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7538254,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99321843,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110101" => inv <= conv_std_logic_vector(261401,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7603976,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(106448498,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110110" => inv <= conv_std_logic_vector(261399,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7669698,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248557271,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101110111" => inv <= conv_std_logic_vector(261397,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7735421,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(257214192,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111000" => inv <= conv_std_logic_vector(261395,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7801145,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132421765,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111001" => inv <= conv_std_logic_vector(261393,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7866869,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(142616931,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111010" => inv <= conv_std_logic_vector(261391,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7932594,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19367251,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111011" => inv <= conv_std_logic_vector(261389,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(7998319,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(31109665,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111100" => inv <= conv_std_logic_vector(261387,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8064044,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(177846168,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111101" => inv <= conv_std_logic_vector(261385,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8129770,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(191143299,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111110" => inv <= conv_std_logic_vector(261383,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8195497,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71003562,28); logexp <= conv_std_logic_vector(1014,11); WHEN "101111111" => inv <= conv_std_logic_vector(261381,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8261224,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85863897,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000000" => inv <= conv_std_logic_vector(261379,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8326951,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(235726809,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000001" => inv <= conv_std_logic_vector(261377,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8392679,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(252159347,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000010" => inv <= conv_std_logic_vector(261375,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8458408,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135162483,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000011" => inv <= conv_std_logic_vector(261373,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8524137,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153174178,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000100" => inv <= conv_std_logic_vector(261371,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8589867,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(37761480,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000101" => inv <= conv_std_logic_vector(261369,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8655597,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57361328,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000110" => inv <= conv_std_logic_vector(261367,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8721327,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(211976226,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110000111" => inv <= conv_std_logic_vector(261365,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8787058,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(233172711,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001000" => inv <= conv_std_logic_vector(261363,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8852790,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120952266,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001001" => inv <= conv_std_logic_vector(261361,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8918522,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(143753360,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001010" => inv <= conv_std_logic_vector(261359,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(8984255,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(33142020,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001011" => inv <= conv_std_logic_vector(261357,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9049988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57555694,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001100" => inv <= conv_std_logic_vector(261355,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9115721,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(216996886,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001101" => inv <= conv_std_logic_vector(261353,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9181455,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(243031622,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001110" => inv <= conv_std_logic_vector(261351,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9247190,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(135662403,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110001111" => inv <= conv_std_logic_vector(261349,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9312925,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(163326679,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010000" => inv <= conv_std_logic_vector(261347,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9378661,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57590984,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010001" => inv <= conv_std_logic_vector(261345,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9444397,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(86893278,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010010" => inv <= conv_std_logic_vector(261343,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9510133,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(251234532,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010011" => inv <= conv_std_logic_vector(261341,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9575871,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(13747355,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010100" => inv <= conv_std_logic_vector(261339,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9641608,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(179738576,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010101" => inv <= conv_std_logic_vector(261337,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9707346,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212340806,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010110" => inv <= conv_std_logic_vector(261335,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9773085,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(111555525,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110010111" => inv <= conv_std_logic_vector(261333,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9838824,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145820180,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011000" => inv <= conv_std_logic_vector(261331,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9904564,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(46701306,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011001" => inv <= conv_std_logic_vector(261329,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(9970304,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(82636350,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011010" => inv <= conv_std_logic_vector(261327,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10036044,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(253627813,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011011" => inv <= conv_std_logic_vector(261325,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10101786,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(22806772,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011100" => inv <= conv_std_logic_vector(261323,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10167527,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195481587,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011101" => inv <= conv_std_logic_vector(261321,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10233269,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(234782825,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011110" => inv <= conv_std_logic_vector(261319,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10299012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(140713496,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110011111" => inv <= conv_std_logic_vector(261317,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10364755,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(181710537,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100000" => inv <= conv_std_logic_vector(261315,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10430499,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(89340991,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100001" => inv <= conv_std_logic_vector(261313,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10496243,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132041793,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100010" => inv <= conv_std_logic_vector(261311,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10561988,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(41379987,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100011" => inv <= conv_std_logic_vector(261309,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10627733,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(85793018,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100100" => inv <= conv_std_logic_vector(261307,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10693478,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(265282876,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100101" => inv <= conv_std_logic_vector(261305,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10759225,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42980638,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100110" => inv <= conv_std_logic_vector(261303,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10824971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(224195170,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110100111" => inv <= conv_std_logic_vector(261301,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10890719,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3621583,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101000" => inv <= conv_std_logic_vector(261299,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(10956466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186568744,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101001" => inv <= conv_std_logic_vector(261297,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11022214,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(236167729,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101010" => inv <= conv_std_logic_vector(261295,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11087963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(152420527,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101011" => inv <= conv_std_logic_vector(261293,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11153712,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(203764581,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101100" => inv <= conv_std_logic_vector(261291,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11219462,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(121766424,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101101" => inv <= conv_std_logic_vector(261289,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11285212,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(174864010,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101110" => inv <= conv_std_logic_vector(261287,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11350963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94623359,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110101111" => inv <= conv_std_logic_vector(261285,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11416714,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(149482427,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110000" => inv <= conv_std_logic_vector(261283,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11482466,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(71008255,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110001" => inv <= conv_std_logic_vector(261281,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11548218,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(127637265,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110010" => inv <= conv_std_logic_vector(261279,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11613971,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50936498,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110011" => inv <= conv_std_logic_vector(261277,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11679724,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(109344419,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110100" => inv <= conv_std_logic_vector(261275,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11745478,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(34426028,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110101" => inv <= conv_std_logic_vector(261273,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11811232,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94620297,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110110" => inv <= conv_std_logic_vector(261271,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11876987,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21492737,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110110111" => inv <= conv_std_logic_vector(261269,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(11942742,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(83481301,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111000" => inv <= conv_std_logic_vector(261267,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12008498,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(12153029,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111001" => inv <= conv_std_logic_vector(261265,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12074254,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(75944853,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111010" => inv <= conv_std_logic_vector(261263,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12140011,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(6423814,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111011" => inv <= conv_std_logic_vector(261261,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12205768,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(72026842,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111100" => inv <= conv_std_logic_vector(261259,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12271526,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(4320978,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111101" => inv <= conv_std_logic_vector(261258,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12304405,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(21141383,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111110" => inv <= conv_std_logic_vector(261256,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12370163,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(156129342,28); logexp <= conv_std_logic_vector(1014,11); WHEN "110111111" => inv <= conv_std_logic_vector(261254,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12435922,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(157813374,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000000" => inv <= conv_std_logic_vector(261252,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12501682,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(26195972,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000001" => inv <= conv_std_logic_vector(261250,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12567442,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(29714068,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000010" => inv <= conv_std_logic_vector(261248,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12633202,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(168370156,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000011" => inv <= conv_std_logic_vector(261246,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12698963,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(173730767,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000100" => inv <= conv_std_logic_vector(261244,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12764725,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(45797884,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000101" => inv <= conv_std_logic_vector(261242,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12830487,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(53009458,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000110" => inv <= conv_std_logic_vector(261240,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12896249,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195366963,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111000111" => inv <= conv_std_logic_vector(261238,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(12962012,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(204436928,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001000" => inv <= conv_std_logic_vector(261236,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13027776,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(80222356,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001001" => inv <= conv_std_logic_vector(261234,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13093540,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(91159668,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001010" => inv <= conv_std_logic_vector(261232,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13159304,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(237251358,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001011" => inv <= conv_std_logic_vector(261230,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13225069,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(250064462,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001100" => inv <= conv_std_logic_vector(261228,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13290835,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(129600456,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001101" => inv <= conv_std_logic_vector(261226,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13356601,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(144297287,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001110" => inv <= conv_std_logic_vector(261224,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13422368,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(25721484,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111001111" => inv <= conv_std_logic_vector(261222,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13488135,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(42309975,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010000" => inv <= conv_std_logic_vector(261220,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13553902,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(194065764,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010001" => inv <= conv_std_logic_vector(261218,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13619670,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(212554867,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010010" => inv <= conv_std_logic_vector(261216,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13685439,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(97779777,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010011" => inv <= conv_std_logic_vector(261214,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13751208,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(118177423,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010100" => inv <= conv_std_logic_vector(261212,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13816978,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5314840,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010101" => inv <= conv_std_logic_vector(261210,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13882748,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(27629467,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010110" => inv <= conv_std_logic_vector(261208,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(13948518,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(185123287,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111010111" => inv <= conv_std_logic_vector(261206,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14014289,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(209363335,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011000" => inv <= conv_std_logic_vector(261204,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14080061,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(100351083,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011001" => inv <= conv_std_logic_vector(261202,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14145833,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(126524479,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011010" => inv <= conv_std_logic_vector(261200,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14211606,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(19449539,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011011" => inv <= conv_std_logic_vector(261198,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14277379,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(47564719,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011100" => inv <= conv_std_logic_vector(261196,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14343152,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210871490,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011101" => inv <= conv_std_logic_vector(261194,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14408926,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(240936379,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011110" => inv <= conv_std_logic_vector(261192,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14474701,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(137761877,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111011111" => inv <= conv_std_logic_vector(261190,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14540476,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(169784908,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100000" => inv <= conv_std_logic_vector(261188,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14606252,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(68573020,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100001" => inv <= conv_std_logic_vector(261186,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14672028,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(102562628,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100010" => inv <= conv_std_logic_vector(261184,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14737805,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(3321276,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100011" => inv <= conv_std_logic_vector(261182,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14803582,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(39285891,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100100" => inv <= conv_std_logic_vector(261180,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14869359,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(210458963,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100101" => inv <= conv_std_logic_vector(261178,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(14935137,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(248407016,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100110" => inv <= conv_std_logic_vector(261176,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15000916,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(153132030,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111100111" => inv <= conv_std_logic_vector(261174,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15066695,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(193071440,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101000" => inv <= conv_std_logic_vector(261172,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15132475,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(99791770,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101001" => inv <= conv_std_logic_vector(261170,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15198255,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(141730965,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101010" => inv <= conv_std_logic_vector(261168,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15264036,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(50455039,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101011" => inv <= conv_std_logic_vector(261166,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15329817,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(94401937,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101100" => inv <= conv_std_logic_vector(261164,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15395599,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(5138692,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101101" => inv <= conv_std_logic_vector(261162,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15461381,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(51101718,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101110" => inv <= conv_std_logic_vector(261160,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15527163,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(232294014,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111101111" => inv <= conv_std_logic_vector(261158,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15592947,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(11846647,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110000" => inv <= conv_std_logic_vector(261156,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15658730,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(195067454,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110001" => inv <= conv_std_logic_vector(261154,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15724514,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(245088520,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110010" => inv <= conv_std_logic_vector(261152,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15790299,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(161910803,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110011" => inv <= conv_std_logic_vector(261150,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15856084,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(213972758,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110100" => inv <= conv_std_logic_vector(261148,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15921870,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(132840397,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110101" => inv <= conv_std_logic_vector(261146,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(15987656,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(186951663,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110110" => inv <= conv_std_logic_vector(261144,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16053443,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(107873077,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111110111" => inv <= conv_std_logic_vector(261142,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16119230,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(164042073,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111000" => inv <= conv_std_logic_vector(261140,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16185018,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(87025173,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111001" => inv <= conv_std_logic_vector(261138,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16250806,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(145260319,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111010" => inv <= conv_std_logic_vector(261136,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16316595,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(70314033,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111011" => inv <= conv_std_logic_vector(261134,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16382384,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(130623237,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111100" => inv <= conv_std_logic_vector(261132,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16448174,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(57754962,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111101" => inv <= conv_std_logic_vector(261130,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16513964,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(120146640,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111110" => inv <= conv_std_logic_vector(261128,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16579755,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(49365303,28); logexp <= conv_std_logic_vector(1014,11); WHEN "111111111" => inv <= conv_std_logic_vector(261126,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(16645546,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(113847871,28); logexp <= conv_std_logic_vector(1014,11); WHEN others => inv <= conv_std_logic_vector(0,18); logman(52 DOWNTO 29) <= conv_std_logic_vector(0,24); logman(28 DOWNTO 1) <= conv_std_logic_vector(0,28); logexp <= conv_std_logic_vector(0,11); END CASE; END PROCESS; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_alufp1x.vhd

10

10539

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_ALUFP1X.VHD *** --*** *** --*** Function: Single Precision Floating Point *** --*** Adder *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_alufp1x IS GENERIC ( mantissa : positive := 36; shiftspeed : integer := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; addsub : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip : IN STD_LOGIC; bb : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); bbsat, bbzip : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip : OUT STD_LOGIC ); END hcc_alufp1x; ARCHITECTURE rtl OF hcc_alufp1x IS type expbasefftype IS ARRAY (3+shiftspeed DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); type aluleftdelfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal aaff, bbff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal aasatff, aazipff, bbsatff, bbzipff : STD_LOGIC; signal ccsatff, cczipff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1); signal addsubff : STD_LOGIC_VECTOR (3+shiftspeed DOWNTO 1); signal manleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal shiftbusnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal manrightff, manalignff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal invertleftff, invertrightff : STD_LOGIC; signal invertleftdelff, invertrightdelff : STD_LOGIC; signal invertleftnode, invertrightnode : STD_LOGIC; signal aluff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aluleftnode, alurightnode, alucarrynode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aluleftff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aluleftdelff : aluleftdelfftype; signal subexpone, subexptwo : STD_LOGIC_VECTOR (10 DOWNTO 1); signal expshiftff : STD_LOGIC_VECTOR (10 DOWNTO 1); signal switch : STD_LOGIC; signal expzerochk : STD_LOGIC_VECTOR (10 DOWNTO 1); signal expzerochkff : STD_LOGIC; signal expzerochknode : STD_LOGIC; signal expbaseff : expbasefftype; signal aaexp, bbexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, bbman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_rsftpipe32 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; component hcc_rsftpipe36 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component hcc_rsftcomb32 PORT ( inbus : IN STD_LOGIC_VECTOR (32 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (5 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (32 DOWNTO 1) ); end component; component hcc_rsftcomb36 PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; paa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; bbff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP manleftff(k) <= '0'; manrightff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP expshiftff(k) <= '0'; END LOOP; FOR k IN 1 TO 3+shiftspeed LOOP FOR j IN 1 TO 10 LOOP expbaseff(k)(j) <= '0'; END LOOP; END LOOP; invertleftff <= '0'; invertrightff <= '0'; FOR k IN 1 TO mantissa LOOP manalignff(k) <= '0'; aluff(k) <= '0'; END LOOP; FOR k IN 1 TO 3+shiftspeed LOOP addsubff(k) <= '0'; ccsatff(k) <= '0'; cczipff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN --*** LEVEL 1 *** aaff <= aa; bbff <= bb; aasatff <= aasat; bbsatff <= bbsat; aazipff <= aazip; bbzipff <= bbzip; addsubff(1) <= addsub; FOR k IN 2 TO 3+shiftspeed LOOP addsubff(k) <= addsubff(k-1); END LOOP; --*** LEVEL 2 *** FOR k IN 1 TO mantissa LOOP manleftff(k) <= (aaff(k+10) AND NOT(switch)) OR (bbff(k+10) AND switch); manrightff(k) <= (bbff(k+10) AND NOT(switch)) OR (aaff(k+10) AND switch); END LOOP; FOR k IN 1 TO 10 LOOP expshiftff(k) <= (subexpone(k) AND NOT(switch)) OR (subexptwo(k) AND switch); END LOOP; FOR k IN 1 TO 10 LOOP expbaseff(1)(k) <= (aaff(k) AND NOT(switch)) OR (bbff(k) AND switch); END LOOP; FOR k IN 2 TO 3+shiftspeed LOOP expbaseff(k)(10 DOWNTO 1) <= expbaseff(k-1)(10 DOWNTO 1); END LOOP; invertleftff <= addsubff(1) AND switch; invertrightff <= addsubff(1) AND NOT(switch); ccsatff(1) <= aasatff OR bbsatff; cczipff(1) <= aazipff AND bbzipff; FOR k IN 2 TO 3+shiftspeed LOOP ccsatff(k) <= ccsatff(k-1); cczipff(k) <= cczipff(k-1); END LOOP; --*** LEVEL 3 or 4 *** FOR k IN 1 TO mantissa LOOP manalignff(k) <= (shiftbusnode(k) XOR invertrightnode) AND expzerochknode; END LOOP; --*** LEVEL 4 or 5 *** aluff <= aluleftnode + alurightnode + alucarrynode; END IF; END IF; END PROCESS; gssa: IF (shiftspeed = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa LOOP aluleftff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO mantissa LOOP aluleftff(k) <= manleftff(k) XOR invertleftnode; END LOOP; END IF; END IF; END PROCESS; invertleftnode <= invertleftff; invertrightnode <= invertrightff; expzerochknode <= expzerochk(10); aluleftnode <= aluleftff; alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(3); END GENERATE; gssb: IF (shiftspeed = 1) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa LOOP aluleftdelff(1)(k) <= '0'; aluleftdelff(2)(k) <= '0'; END LOOP; invertleftdelff <= '0'; invertrightdelff <= '0'; expzerochkff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aluleftdelff(1)(mantissa DOWNTO 1) <= manleftff; FOR k IN 1 TO mantissa LOOP aluleftdelff(2)(k) <= aluleftdelff(1)(k) XOR invertleftnode; END LOOP; invertleftdelff <= invertleftff; invertrightdelff <= invertrightff; expzerochkff <= expzerochk(10); END IF; END IF; END PROCESS; invertleftnode <= invertleftdelff; invertrightnode <= invertrightdelff; expzerochknode <= expzerochkff; aluleftnode <= aluleftdelff(2)(mantissa DOWNTO 1); alucarrynode <= zerovec(mantissa-1 DOWNTO 1) & addsubff(4); END GENERATE; alurightnode <= manalignff; subexpone <= aaff(10 DOWNTO 1) - bbff(10 DOWNTO 1); subexptwo <= bbff(10 DOWNTO 1) - aaff(10 DOWNTO 1); switch <= subexpone(10); gsa: IF (mantissa = 32) GENERATE expzerochk <= expshiftff - "0000100000"; -- 31 ok, 32 not gsb: IF (shiftspeed = 0) GENERATE shiftone: hcc_rsftcomb32 PORT MAP (inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; gsc: IF (shiftspeed = 1) GENERATE shifttwo: hcc_rsftpipe32 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>manrightff,shift=>expshiftff(5 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; END GENERATE; gsd: IF (mantissa = 36) GENERATE expzerochk <= expshiftff - "0000100100"; -- 35 ok, 36 not gse: IF (shiftspeed = 0) GENERATE shiftone: hcc_rsftcomb36 PORT MAP (inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; gsf: IF (shiftspeed = 1) GENERATE shifttwo: hcc_rsftpipe36 PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, inbus=>manrightff,shift=>expshiftff(6 DOWNTO 1), outbus=>shiftbusnode); END GENERATE; END GENERATE; --*** OUTPUT *** cc <= aluff & expbaseff(3+shiftspeed)(10 DOWNTO 1); ccsat <= ccsatff(3+shiftspeed); cczip <= cczipff(3+shiftspeed); --*** DEBUG SECTION *** aaexp <= aa(10 DOWNTO 1); bbexp <= bb(10 DOWNTO 1); ccexp <= expbaseff(3+shiftspeed)(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); bbman <= bb(mantissa+10 DOWNTO 11); ccman <= aluff; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_exprnd.vhd

10

7830

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_EXPRND.VHD *** --*** *** --*** Function: FP Exponent Output Block - *** --*** Rounded *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 18/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_exprnd IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentexp : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaexp : IN STD_LOGIC_VECTOR (24 DOWNTO 1); -- includes roundbit nanin : IN STD_LOGIC; rangeerror : IN STD_LOGIC; signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); END fp_exprnd; ARCHITECTURE rtl OF fp_exprnd IS constant expwidth : positive := 8; constant manwidth : positive := 23; type exponentfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (manwidth-1 DOWNTO 1); signal nanff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal rangeerrorff : STD_LOGIC; signal overflownode, underflownode : STD_LOGIC; signal overflowff, underflowff : STD_LOGIC_VECTOR (2 DOWNTO 1); signal manoverflowbitff : STD_LOGIC; signal roundmantissaff, mantissaff : STD_LOGIC_VECTOR (manwidth DOWNTO 1); signal exponentnode : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponentoneff : STD_LOGIC_VECTOR (expwidth+2 DOWNTO 1); signal exponenttwoff : STD_LOGIC_VECTOR (expwidth DOWNTO 1); signal manoverflow : STD_LOGIC_VECTOR (manwidth+1 DOWNTO 1); signal infinitygen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal zerogen : STD_LOGIC_VECTOR (expwidth+1 DOWNTO 1); signal setmanzero, setmanmax : STD_LOGIC; signal setexpzero, setexpmax : STD_LOGIC; BEGIN gzv: FOR k IN 1 TO manwidth-1 GENERATE zerovec(k) <= '0'; END GENERATE; pra: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN nanff <= "00"; rangeerrorff <= '0'; overflowff <= "00"; underflowff <= "00"; manoverflowbitff <= '0'; FOR k IN 1 TO manwidth LOOP roundmantissaff(k) <= '0'; mantissaff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth+2 LOOP exponentoneff(k) <= '0'; END LOOP; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF(enable = '1') THEN nanff(1) <= nanin; nanff(2) <= nanff(1); rangeerrorff <= rangeerror; overflowff(1) <= overflownode; overflowff(2) <= overflowff(1); underflowff(1) <= underflownode; underflowff(2) <= underflowff(1); manoverflowbitff <= manoverflow(manwidth+1); roundmantissaff <= mantissaexp(manwidth+1 DOWNTO 2) + (zerovec & mantissaexp(1)); -- nan takes precedence (set max) -- nan takes precedence (set max) FOR k IN 1 TO manwidth LOOP mantissaff(k) <= (roundmantissaff(k) AND setmanzero) OR setmanmax; END LOOP; exponentoneff(expwidth+2 DOWNTO 1) <= "00" & exponentexp; FOR k IN 1 TO expwidth LOOP exponenttwoff(k) <= (exponentnode(k) AND setexpzero) OR setexpmax; END LOOP; END IF; END IF; END PROCESS; exponentnode <= exponentoneff(expwidth+2 DOWNTO 1) + (zerovec(expwidth+1 DOWNTO 1) & manoverflowbitff); --********************************* --*** PREDICT MANTISSA OVERFLOW *** --********************************* manoverflow(1) <= mantissaexp(1); gmoa: FOR k IN 2 TO manwidth+1 GENERATE manoverflow(k) <= manoverflow(k-1) AND mantissaexp(k); END GENERATE; --********************************** --*** CHECK GENERATED CONDITIONS *** --********************************** -- infinity if exponent == 255 infinitygen(1) <= exponentnode(1); gia: FOR k IN 2 TO expwidth GENERATE infinitygen(k) <= infinitygen(k-1) AND exponentnode(k); END GENERATE; infinitygen(expwidth+1) <= infinitygen(expwidth) OR (exponentnode(expwidth+1) AND NOT(exponentnode(expwidth+2))); -- '1' if infinity -- zero if exponent == 0 zerogen(1) <= exponentnode(1); gza: FOR k IN 2 TO expwidth GENERATE zerogen(k) <= zerogen(k-1) OR exponentnode(k); END GENERATE; zerogen(expwidth+1) <= zerogen(expwidth) AND NOT(exponentnode(expwidth+2)); -- '0' if zero -- trap any other overflow errors -- when sign = 0 and rangeerror = 1, overflow -- when sign = 1 and rangeerror = 1, underflow overflownode <= NOT(signin) AND rangeerror; underflownode <= signin AND rangeerror; -- set mantissa to 0 when infinity or zero condition setmanzero <= NOT(infinitygen(expwidth+1)) AND zerogen(expwidth+1) AND NOT(rangeerrorff); -- setmantissa to "11..11" when nan setmanmax <= nanin; -- set exponent to 0 when zero condition setexpzero <= zerogen(expwidth+1); -- set exponent to "11..11" when nan, infinity, or divide by 0 setexpmax <= nanin OR infinitygen(expwidth+1) OR rangeerrorff; --*************** --*** OUTPUTS *** --*************** signout <= '0'; mantissaout <= mantissaff; exponentout <= exponenttwoff; ----------------------------------------------- nanout <= nanff(2); overflowout <= overflowff(2); underflowout <= underflowff(2); END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_atan.vhd

10

17028

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_ATAN.VHD *** --*** *** --*** Function: Single Precision Floating Point *** --*** ArcTangent *** --*** *** --*** 23/12/09 ML *** --*** *** --*** (c) 2009 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** NOTES *** --*************************************************** -- slight improvement when "roundbit" is used i.e. round up from -- X.4999 - exact number of bits to be used needs to be tweaked ENTITY fp_atan IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); END fp_atan; ARCHITECTURE rtl OF fp_atan IS constant coredepth : positive := 12; constant b_precision : positive := 10; type exponentinfftype IS ARRAY (coredepth-2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); type exponenttopfftype IS ARRAY (coredepth-3 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); type mantissabpfftype IS ARRAY (2*coredepth+10 DOWNTO 1) OF STD_LOGIC_VECTOR (23 DOWNTO 1); -- SPR: 380600 type termfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (36 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1); signal pi_over_two : STD_LOGIC_VECTOR (36 DOWNTO 1); signal inputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1); signal delinputnumber : STD_LOGIC_VECTOR (36 DOWNTO 1); signal topquotient : STD_LOGIC_VECTOR (36 DOWNTO 1); signal topquotientnumber : STD_LOGIC_VECTOR (36 DOWNTO 1); signal exponentoffset : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exponentinff : exponentinfftype; signal idselectff : STD_LOGIC_VECTOR (2*coredepth+10 DOWNTO 1); -- SPR: 380600 signal pathselectff : STD_LOGIC_VECTOR (2*coredepth+9 DOWNTO 1); signal exponenttopff : exponenttopfftype; signal forward_shiftff, inverse_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1); signal a_shiftff : STD_LOGIC_VECTOR (10 DOWNTO 1); signal a_fixedpointff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal a_fixedpointbus : STD_LOGIC_VECTOR (36 DOWNTO 1); signal a_mantissanode : STD_LOGIC_VECTOR (36 DOWNTO 1); signal pathcheck : STD_LOGIC_VECTOR (9 DOWNTO 1); signal a_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1); signal b_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1); signal c_fixedpoint : STD_LOGIC_VECTOR (36 DOWNTO 1); signal ab_fixedpoint : STD_LOGIC_VECTOR (37 DOWNTO 1); signal ab_plusone : STD_LOGIC_VECTOR (36 DOWNTO 1); signal numerator, denominator : STD_LOGIC_VECTOR (36 DOWNTO 1); signal addterm : STD_LOGIC_VECTOR (36 DOWNTO 1); signal b_address : STD_LOGIC_VECTOR (10 DOWNTO 1); signal lutterm : STD_LOGIC_VECTOR (36 DOWNTO 1); signal dellutterm : STD_LOGIC_VECTOR (36 DOWNTO 1); signal signff : STD_LOGIC_VECTOR (2*coredepth+11 DOWNTO 1); signal mantissabpff : mantissabpfftype; -- SPR: 380600 signal atantermff : termfftype; signal large_atanff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal small_mantissa, small_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal large_mantissa, large_mantissaff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal mux_mantissa : STD_LOGIC_VECTOR (36 DOWNTO 1); signal small_count, small_countff : STD_LOGIC_VECTOR (6 DOWNTO 1); signal small_overflowbus, large_overflowbus : STD_LOGIC_VECTOR (24 DOWNTO 1); signal small_overflowff, large_overflowff : STD_LOGIC; signal mux_overflow : STD_LOGIC; signal roundbit : STD_LOGIC; signal mantissa_roundff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal mantissa_bypass : STD_LOGIC_VECTOR (23 DOWNTO 1); signal exponent_outff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal small_exponent_adjust, large_exponent_adjust : STD_LOGIC_VECTOR (8 DOWNTO 1); signal exponent_adjust, exponent_adjustff : STD_LOGIC_VECTOR (8 DOWNTO 1); -- SPR: 380600 signal expinzero : STD_LOGIC_VECTOR (8 DOWNTO 1); signal expzero : STD_LOGIC; component fp_inv_core GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1); quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_rsft36 PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_del GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_fxmul GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_atanlut PORT ( add : IN STD_LOGIC_VECTOR (10 DOWNTO 1); data : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_clz36 PORT ( mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1); leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1) ); end component; component fp_lsft36 IS PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO 36 GENERATE zerovec(k) <= '0'; END GENERATE; pi_over_two <= x"C90FDAA22"; -- 1.57... --*** Invert Input *** inputnumber <= '1' & mantissain & "000000000000"; -- will give output between 0.5 and 0.99999... -- will always need to be normalized invcore: fp_inv_core PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>inputnumber, quotient=>topquotient); exponentoffset <= conv_std_logic_vector (127,10); pinx: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO coredepth-2 LOOP FOR j IN 1 TO 8 LOOP exponentinff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO 2*coredepth+9 LOOP pathselectff(k) <= '0'; END LOOP; -- SPR: 380600 FOR k IN 1 TO 2*coredepth+10 LOOP idselectff(k) <= '0'; END LOOP; FOR k IN 1 TO coredepth-3 LOOP FOR j IN 1 TO 10 LOOP exponenttopff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO 10 LOOP forward_shiftff(k) <= '0'; inverse_shiftff(k) <= '0'; a_shiftff(k) <= '0'; END LOOP; FOR k IN 1 TO 36 LOOP a_fixedpointff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN exponentinff(1)(8 DOWNTO 1) <= exponentin; FOR k IN 2 TO coredepth-2 LOOP exponentinff(k)(8 DOWNTO 1) <= exponentinff(k-1)(8 DOWNTO 1); END LOOP; pathselectff(1) <= pathcheck(9); FOR k IN 2 TO 2*coredepth+9 LOOP pathselectff(k) <= pathselectff(k-1); END LOOP; -- SPR: 380600 idselectff(1) <= expzero; FOR k IN 2 TO 2*coredepth+10 LOOP idselectff(k) <= idselectff(k-1); END LOOP; -- exponent for inverse, used when exponent > 126 exponenttopff(1)(10 DOWNTO 1) <= exponentoffset - ("00" & exponentinff(1)(8 DOWNTO 1)); exponenttopff(2)(10 DOWNTO 1) <= exponenttopff(1)(10 DOWNTO 1) + exponentoffset; exponenttopff(3)(10 DOWNTO 1) <= exponenttopff(2)(10 DOWNTO 1) - 1; -- inverse always less than 1, decrement exponent FOR k IN 4 TO coredepth-3 LOOP exponenttopff(k)(10 DOWNTO 1) <= exponenttopff(k-1)(10 DOWNTO 1); END LOOP; forward_shiftff <= "0001111111" - ("00" & exponentinff(coredepth-2)(8 DOWNTO 1)); inverse_shiftff <= "0001111111" - exponenttopff(coredepth-3)(10 DOWNTO 1); FOR k IN 1 TO 6 LOOP a_shiftff(k) <= (forward_shiftff(k) AND NOT(pathselectff(coredepth-2))) OR (inverse_shiftff(k) AND pathselectff(coredepth-2)); END LOOP; a_fixedpointff <= a_fixedpointbus; END IF; END IF; END PROCESS; -- if <=126 (<= 0.999999), use atan(x) path, else use (pi/2-atan(1/x)) path pathcheck <= "001111110" - ('0' & exponentinff(1)(8 DOWNTO 1)); cdma: fp_del GENERIC MAP (width=>36,pipes=>coredepth) -- 12 for inv_core PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>inputnumber, cc=>delinputnumber); topquotientnumber <= topquotient(35 DOWNTO 1) & '0'; gma: FOR k IN 1 TO 36 GENERATE a_mantissanode(k) <= (delinputnumber(k) AND NOT(pathselectff(coredepth-1))) OR (topquotientnumber(k) AND pathselectff(coredepth-1)); END GENERATE; casr: fp_rsft36 PORT MAP (inbus=>a_mantissanode,shift=>a_shiftff(6 DOWNTO 1), outbus=>a_fixedpointbus); a_fixedpoint <= a_fixedpointff; b_fixedpoint <= a_fixedpointff(36 DOWNTO 37-b_precision) & zerovec(36-b_precision DOWNTO 1); c_fixedpoint <= a_fixedpointff(36-b_precision DOWNTO 1) & zerovec(b_precision DOWNTO 1); cmone: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>37, pipes=>3) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>a_fixedpoint,databb=>b_fixedpoint, result=>ab_fixedpoint); ab_plusone <= '1' & ab_fixedpoint(35 DOWNTO 1); -- ab_fixedpoint always 1/4 true value invtwo: fp_inv_core PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>ab_plusone, quotient=>denominator); cdc: fp_del GENERIC MAP (width=>36,pipes=>coredepth+3) -- inv_core and 3 for 36*36 mult PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>c_fixedpoint, cc=>numerator); cmtwo: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>36, pipes=>3) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>numerator,databb=>denominator, result=>addterm); b_address <= a_fixedpoint(36 DOWNTO 37-b_precision); clut: fp_atanlut PORT MAP (add=>b_address, data=>lutterm); cdlut: fp_del GENERIC MAP (width=>36,pipes=>18) -- 12 for inv_core and 3 for 36*36 mult PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>lutterm, cc=>dellutterm); pimo: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 2*coredepth+11 LOOP signff(k) <= '0'; END LOOP; -- SPR: 380600 FOR k IN 1 TO 2*coredepth+10 LOOP FOR j IN 1 TO 23 LOOP mantissabpff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO 36 LOOP atantermff(1)(k) <= '0'; atantermff(2)(k) <= '0'; large_atanff(k) <= '0'; small_mantissaff(k) <= '0'; large_mantissaff(k) <= '0'; END LOOP; FOR k IN 1 TO 6 LOOP small_countff(k) <= '0'; END LOOP; small_overflowff <= '0'; large_overflowff <= '0'; FOR k IN 1 TO 23 LOOP mantissa_roundff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP exponent_outff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN signff(1) <= signin; mantissabpff(1)(23 DOWNTO 1) <= mantissain(23 DOWNTO 1); FOR k IN 2 TO 2*coredepth+11 LOOP signff(k) <= signff(k-1); END LOOP; -- SPR: 380600 FOR k IN 2 TO 2*coredepth+10 LOOP mantissabpff(k)(23 DOWNTO 1) <= mantissabpff(k-1)(23 DOWNTO 1); END LOOP; atantermff(1)(36 DOWNTO 1) <= dellutterm + (zerovec(9 DOWNTO 1) & addterm(36 DOWNTO 10)); atantermff(2)(36 DOWNTO 1) <= atantermff(1)(36 DOWNTO 1); -- always in the range 0.78 to pi/2 large_atanff(36 DOWNTO 1) <= pi_over_two - atantermff(1)(36 DOWNTO 1); small_countff <= small_count; large_mantissaff <= large_mantissa; small_mantissaff <= small_mantissa; small_overflowff <= small_overflowbus(24); large_overflowff <= large_overflowbus(24); exponent_adjustff <= exponent_adjust; --mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + mux_mantissa(12); mantissa_roundff <= mux_mantissa(35 DOWNTO 13) + roundbit; exponent_outff <= "01111111" - exponent_adjustff + mux_overflow; END IF; END IF; END PROCESS; roundbit <= mux_mantissa(12) OR (mux_mantissa(11) AND mux_mantissa(10) AND mux_mantissa(9) AND mux_mantissa(8) AND mux_mantissa(7) AND mux_mantissa(6) AND mux_mantissa(5) AND mux_mantissa(4) AND mux_mantissa(3) AND mux_mantissa(2)); ccsat: fp_clz36 PORT MAP (mantissa=>atantermff(1)(36 DOWNTO 1), leading=>small_count); cssat: fp_lsft36 PORT MAP (inbus=>atantermff(2)(36 DOWNTO 1),shift=>small_countff, outbus=>small_mantissa); small_overflowbus(1) <= small_mantissa(12); gova: FOR k IN 2 TO 24 GENERATE small_overflowbus(k) <= small_overflowbus(k-1) AND small_mantissa(k+11); END GENERATE; glma: FOR k IN 1 TO 35 GENERATE large_mantissa(k+1) <= (large_atanff(k) AND NOT(large_atanff(36))) OR (large_atanff(k+1) AND large_atanff(36)); END GENERATE; large_mantissa(1) <= '0'; large_overflowbus(1) <= large_mantissa(12); govb: FOR k IN 2 TO 24 GENERATE large_overflowbus(k) <= large_overflowbus(k-1) AND large_mantissa(k+11); END GENERATE; gmma: FOR k IN 1 TO 36 GENERATE mux_mantissa(k) <= (small_mantissaff(k) AND NOT(pathselectff(2*coredepth+9))) OR (large_mantissaff(k) AND pathselectff(2*coredepth+9)); END GENERATE; mux_overflow <= (small_overflowff AND NOT(pathselectff(2*coredepth+9))) OR (large_overflowff AND pathselectff(2*coredepth+9)); large_exponent_adjust <= "0000000" & NOT(large_atanff(36)); small_exponent_adjust <= "00" & small_countff; gxa: FOR k IN 1 TO 8 GENERATE exponent_adjust(k) <= (small_exponent_adjust(k) AND NOT(pathselectff(2*coredepth+8))) OR (large_exponent_adjust(k) AND pathselectff(2*coredepth+8)); END GENERATE; -- SPR: 380600 bypass: FOR k IN 1 TO 23 GENERATE mantissa_bypass(k) <= (mantissa_roundff(k) AND NOT(idselectff(2*coredepth+10))) OR (mantissabpff(2*coredepth+10)(k) AND idselectff(2*coredepth+10)); END GENERATE; -- SPR: 380600 expinzero(1) <= exponentinff(1)(1); gxza: FOR k IN 2 TO 8 GENERATE expinzero(k) <= expinzero(k-1) OR exponentinff(1)(k); END GENERATE; expzero <= NOT(expinzero(8)); -- '0' when zero --*** OUTPUTS *** signout <= signff(2*coredepth+11); exponentout <= (others => '0') when idselectff(2*coredepth+10) = '1' else exponent_outff; -- SPR: 380600 mantissaout <= mantissa_bypass; end rtl;

mit

ou-cse-378/vhdl-tetris

datastack.vhd

1

3086

-- ================================================================================= -- // Name: Bryan Mason, James Batcheler, & Brad McMahon -- // File: Datastack.vhd -- // Date: 12/9/2004 -- // Description: Datastack -- // Class: CSE 378 -- ================================================================================= library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity datastack is port ( TLoad : in std_logic; y1 : in STD_LOGIC_VECTOR(15 downto 0); nsel : in STD_LOGIC_VECTOR(1 downto 0); nload : in STD_LOGIC; ssel : in STD_LOGIC; clk : in STD_LOGIC; clr : in STD_LOGIC; dpush : in STD_LOGIC; dpop : in STD_LOGIC; Tin : in STD_LOGIC_VECTOR(15 downto 0); T : out STD_LOGIC_VECTOR(15 downto 0); N : out STD_LOGIC_VECTOR(15 downto 0); N2 : out STD_LOGIC_VECTOR(15 downto 0) ); end datastack; architecture Behavioral of datastack is component stack32x16 port ( d : in STD_LOGIC_VECTOR(15 downto 0); clk : in STD_LOGIC; clr : in STD_LOGIC; push : in STD_LOGIC; pop : in STD_LOGIC; full : out STD_LOGIC; empty : out STD_LOGIC; q : out STD_LOGIC_VECTOR(15 downto 0) ); END component; component mux2g generic(width:positive); Port ( a : in std_logic_vector(width-1 downto 0); b : in std_logic_vector(width-1 downto 0); sel : in std_logic; y : out std_logic_vector(width-1 downto 0) ); end component; component mux4g generic(width:positive); Port ( a : in std_logic_vector(width-1 downto 0); b : in std_logic_vector(width-1 downto 0); c : in std_logic_vector(width-1 downto 0); d : in std_logic_vector(width-1 downto 0); sel : in std_logic_vector(1 downto 0); y : out std_logic_vector(width-1 downto 0) ); end component; component reg generic(width: positive); port ( d : in STD_LOGIC_VECTOR (width-1 downto 0); load : in STD_LOGIC; clr : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR (width-1 downto 0) ); end component; constant bus_width: positive := 16; signal T1: std_logic_vector(15 downto 0); signal N1: std_logic_vector(15 downto 0); signal NS: std_logic_vector(15 downto 0); signal D: std_logic_vector(15 downto 0); signal NIN: std_logic_vector(15 downto 0); signal FULL: std_logic; signal EMPTY: std_logic; begin T <= T1; N <= N1; N2 <= NS; SWtreg : reg generic map (width => bus_width) port map ( d => TIN, load => TLOAD, clr => CLR, clk => CLK, q => T1 ); SWnreg : reg generic map (width => bus_width) port map ( d => NIN, load => NLOAD, clr => CLR, clk => CLK, q => N1 ); SWmux2g: mux2g generic map (width => bus_width) port map ( a => N1, b => T1, sel => SSEL, y => D ); SWmux4g: mux4g generic map (width => bus_width) port map ( a => T1, b => NS, c => Y1, d=> Y1, sel => NSEL, y => NIN ); SWstack32x16: stack32x16 port map ( d => D, clk => CLK, clr => CLR, push => DPUSH, pop => DPOP, full => FULL, empty => EMPTY, q => NS ); end behavioral;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_inv_core.vhd

10

6144

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** SINGLE PRECISION INVERSE - CORE *** --*** *** --*** FP_INV_CORE.VHD *** --*** *** --*** Function: 36 bit Inverse *** --*** (multiplicative iterative algorithm) *** --*** *** --*** 09/12/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** Notes: Latency = 12 *** --*************************************************** ENTITY fp_inv_core IS GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (36 DOWNTO 1); quotient : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); END fp_inv_core; ARCHITECTURE rtl OF fp_inv_core IS signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1); signal divisordel : STD_LOGIC_VECTOR (36 DOWNTO 1); signal invdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1); signal delinvdivisor : STD_LOGIC_VECTOR (18 DOWNTO 1); signal scaleden : STD_LOGIC_VECTOR (36 DOWNTO 1); signal twonode : STD_LOGIC_VECTOR (37 DOWNTO 1); signal nextguessff : STD_LOGIC_VECTOR (37 DOWNTO 1); signal quotientnode : STD_LOGIC_VECTOR (36 DOWNTO 1); component fp_div_est IS PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; divisor : IN STD_LOGIC_VECTOR (19 DOWNTO 1); invdivisor : OUT STD_LOGIC_VECTOR (18 DOWNTO 1) ); end component; component fp_fxmul IS GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_del GENERIC ( width : positive := 64; pipes : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO 36 GENERATE zerovec(k) <= '0'; END GENERATE; invcore: fp_div_est PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, divisor=>divisor(36 DOWNTO 18),invdivisor=>invdivisor); delinone: fp_del GENERIC MAP (width=>36,pipes=>5) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>divisor,cc=>divisordel); --********************************** --*** ITERATION 0 - SCALE INPUTS *** --********************************** -- in level 5, out level 8 mulscaleone: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36, pipes=>3,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>divisordel,databb=>invdivisor, result=>scaleden); --******************** --*** ITERATION 1 *** --******************** twonode <= '1' & zerovec(36 DOWNTO 1); pita: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 37 LOOP nextguessff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN nextguessff <= twonode - ('0' & scaleden); -- level 9 END IF; END IF; END PROCESS; deloneone: fp_del GENERIC MAP (width=>18,pipes=>4) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>invdivisor, cc=>delinvdivisor); -- in level 9, out level 12 muloneone: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>18,widthcc=>36, pipes=>3,synthesize=>synthesize) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>nextguessff(36 DOWNTO 1),databb=>delinvdivisor, result=>quotientnode); quotient <= quotientnode(36 DOWNTO 1); END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_sum36x18.vhd

10

18695

-- megafunction wizard: %ALTMULT_ADD% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: ALTMULT_ADD -- ============================================================ -- File Name: sum36x18.vhd -- Megafunction Name(s): -- ALTMULT_ADD -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 8.1 Build 163 10/28/2008 SJ Full Version -- ************************************************************ --Copyright (C) 1991-2008 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY altera_mf; USE altera_mf.all; ENTITY fp_sum36x18 IS PORT ( aclr3 : IN STD_LOGIC := '0'; clock0 : IN STD_LOGIC := '1'; dataa_0 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0'); dataa_1 : IN STD_LOGIC_VECTOR (17 DOWNTO 0) := (OTHERS => '0'); datab_0 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0'); datab_1 : IN STD_LOGIC_VECTOR (35 DOWNTO 0) := (OTHERS => '0'); ena0 : IN STD_LOGIC := '1'; result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0) ); END fp_sum36x18; ARCHITECTURE SYN OF fp_sum36x18 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (54 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (17 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC_VECTOR (35 DOWNTO 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (17 DOWNTO 0); SIGNAL sub_wire4 : STD_LOGIC_VECTOR (35 DOWNTO 0); SIGNAL sub_wire5 : STD_LOGIC_VECTOR (71 DOWNTO 0); SIGNAL sub_wire6 : STD_LOGIC_VECTOR (35 DOWNTO 0); COMPONENT altmult_add GENERIC ( accumulator : STRING; addnsub_multiplier_aclr1 : STRING; addnsub_multiplier_pipeline_aclr1 : STRING; addnsub_multiplier_pipeline_register1 : STRING; addnsub_multiplier_register1 : STRING; chainout_adder : STRING; chainout_register : STRING; dedicated_multiplier_circuitry : STRING; input_aclr_a0 : STRING; input_aclr_a1 : STRING; input_aclr_b0 : STRING; input_aclr_b1 : STRING; input_register_a0 : STRING; input_register_a1 : STRING; input_register_b0 : STRING; input_register_b1 : STRING; input_source_a0 : STRING; input_source_a1 : STRING; input_source_b0 : STRING; input_source_b1 : STRING; intended_device_family : STRING; lpm_type : STRING; multiplier1_direction : STRING; multiplier_aclr0 : STRING; multiplier_aclr1 : STRING; multiplier_register0 : STRING; multiplier_register1 : STRING; number_of_multipliers : NATURAL; output_aclr : STRING; output_register : STRING; port_addnsub1 : STRING; port_signa : STRING; port_signb : STRING; representation_a : STRING; representation_b : STRING; signed_aclr_a : STRING; signed_aclr_b : STRING; signed_pipeline_aclr_a : STRING; signed_pipeline_aclr_b : STRING; signed_pipeline_register_a : STRING; signed_pipeline_register_b : STRING; signed_register_a : STRING; signed_register_b : STRING; width_a : NATURAL; width_b : NATURAL; width_chainin : NATURAL; width_result : NATURAL; zero_chainout_output_aclr : STRING; zero_chainout_output_register : STRING; zero_loopback_aclr : STRING; zero_loopback_output_aclr : STRING; zero_loopback_output_register : STRING; zero_loopback_pipeline_aclr : STRING; zero_loopback_pipeline_register : STRING; zero_loopback_register : STRING ); PORT ( dataa : IN STD_LOGIC_VECTOR (35 DOWNTO 0); datab : IN STD_LOGIC_VECTOR (71 DOWNTO 0); clock0 : IN STD_LOGIC ; aclr3 : IN STD_LOGIC ; ena0 : IN STD_LOGIC ; result : OUT STD_LOGIC_VECTOR (54 DOWNTO 0) ); END COMPONENT; BEGIN sub_wire6 <= datab_1(35 DOWNTO 0); sub_wire3 <= dataa_1(17 DOWNTO 0); result <= sub_wire0(54 DOWNTO 0); sub_wire1 <= dataa_0(17 DOWNTO 0); sub_wire2 <= sub_wire3(17 DOWNTO 0) & sub_wire1(17 DOWNTO 0); sub_wire4 <= datab_0(35 DOWNTO 0); sub_wire5 <= sub_wire6(35 DOWNTO 0) & sub_wire4(35 DOWNTO 0); ALTMULT_ADD_component : ALTMULT_ADD GENERIC MAP ( accumulator => "NO", addnsub_multiplier_aclr1 => "ACLR3", addnsub_multiplier_pipeline_aclr1 => "ACLR3", addnsub_multiplier_pipeline_register1 => "CLOCK0", addnsub_multiplier_register1 => "CLOCK0", chainout_adder => "NO", chainout_register => "UNREGISTERED", dedicated_multiplier_circuitry => "AUTO", input_aclr_a0 => "ACLR3", input_aclr_a1 => "ACLR3", input_aclr_b0 => "ACLR3", input_aclr_b1 => "ACLR3", input_register_a0 => "CLOCK0", input_register_a1 => "CLOCK0", input_register_b0 => "CLOCK0", input_register_b1 => "CLOCK0", input_source_a0 => "DATAA", input_source_a1 => "DATAA", input_source_b0 => "DATAB", input_source_b1 => "DATAB", intended_device_family => "Stratix III", lpm_type => "altmult_add", multiplier1_direction => "ADD", multiplier_aclr0 => "ACLR3", multiplier_aclr1 => "ACLR3", multiplier_register0 => "CLOCK0", multiplier_register1 => "CLOCK0", number_of_multipliers => 2, output_aclr => "ACLR3", output_register => "CLOCK0", port_addnsub1 => "PORT_UNUSED", port_signa => "PORT_UNUSED", port_signb => "PORT_UNUSED", representation_a => "UNSIGNED", representation_b => "UNSIGNED", signed_aclr_a => "ACLR3", signed_aclr_b => "ACLR3", signed_pipeline_aclr_a => "ACLR3", signed_pipeline_aclr_b => "ACLR3", signed_pipeline_register_a => "CLOCK0", signed_pipeline_register_b => "CLOCK0", signed_register_a => "CLOCK0", signed_register_b => "CLOCK0", width_a => 18, width_b => 36, width_chainin => 1, width_result => 55, zero_chainout_output_aclr => "ACLR3", zero_chainout_output_register => "CLOCK0", zero_loopback_aclr => "ACLR3", zero_loopback_output_aclr => "ACLR3", zero_loopback_output_register => "CLOCK0", zero_loopback_pipeline_aclr => "ACLR3", zero_loopback_pipeline_register => "CLOCK0", zero_loopback_register => "CLOCK0" ) PORT MAP ( dataa => sub_wire2, datab => sub_wire5, clock0 => clock0, aclr3 => aclr3, ena0 => ena0, result => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACCUM_DIRECTION STRING "Add" -- Retrieval info: PRIVATE: ACCUM_SLOAD_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ACCUM_SLOAD_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ACCUM_SLOAD_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ACCUM_SLOAD_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB1_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB1_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB1_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB1_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB3_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB3_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ADDNSUB3_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ADDNSUB3_REG STRING "1" -- Retrieval info: PRIVATE: ADD_ENABLE NUMERIC "1" -- Retrieval info: PRIVATE: ALL_REG_ACLR NUMERIC "1" -- Retrieval info: PRIVATE: A_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: A_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: B_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: B_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_ACLR NUMERIC "3" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REG STRING "0" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTER NUMERIC "0" -- Retrieval info: PRIVATE: CHAINOUT_OUTPUT_REGISTERED NUMERIC "0" -- Retrieval info: PRIVATE: CHAS_ZERO_CHAINOUT NUMERIC "1" -- Retrieval info: PRIVATE: HAS_ACCUMULATOR NUMERIC "0" -- Retrieval info: PRIVATE: HAS_ACUMM_SLOAD NUMERIC "0" -- Retrieval info: PRIVATE: HAS_CHAININ_PORT NUMERIC "0" -- Retrieval info: PRIVATE: HAS_CHAINOUT_ADDER NUMERIC "0" -- Retrieval info: PRIVATE: HAS_LOOPBACK NUMERIC "0" -- Retrieval info: PRIVATE: HAS_MAC STRING "0" -- Retrieval info: PRIVATE: HAS_SAT_ROUND STRING "0" -- Retrieval info: PRIVATE: HAS_ZERO_LOOPBACK NUMERIC "0" -- Retrieval info: PRIVATE: IMPL_STYLE_DEDICATED NUMERIC "0" -- Retrieval info: PRIVATE: IMPL_STYLE_DEFAULT NUMERIC "1" -- Retrieval info: PRIVATE: IMPL_STYLE_LCELL NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix III" -- Retrieval info: PRIVATE: MULT_REGA0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_REGB0 NUMERIC "1" -- Retrieval info: PRIVATE: MULT_REGOUT0 NUMERIC "1" -- Retrieval info: PRIVATE: NUM_MULT STRING "2" -- Retrieval info: PRIVATE: OP1 STRING "Add" -- Retrieval info: PRIVATE: OP3 STRING "Add" -- Retrieval info: PRIVATE: OUTPUT_EXTRA_LAT NUMERIC "0" -- Retrieval info: PRIVATE: OUTPUT_REG_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: OUTPUT_REG_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: Q_ACLR_SRC_MULT0 NUMERIC "3" -- Retrieval info: PRIVATE: Q_CLK_SRC_MULT0 NUMERIC "0" -- Retrieval info: PRIVATE: REG_OUT NUMERIC "1" -- Retrieval info: PRIVATE: RNFORMAT STRING "55" -- Retrieval info: PRIVATE: ROTATE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ROTATE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ROTATE_OUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ROTATE_OUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ROTATE_OUT_REG STRING "1" -- Retrieval info: PRIVATE: ROTATE_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ROTATE_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ROTATE_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ROTATE_REG STRING "1" -- Retrieval info: PRIVATE: RQFORMAT STRING "Q1.15" -- Retrieval info: PRIVATE: RTS_WIDTH STRING "55" -- Retrieval info: PRIVATE: SAME_CONFIG NUMERIC "1" -- Retrieval info: PRIVATE: SAME_CONTROL_SRC_A0 NUMERIC "1" -- Retrieval info: PRIVATE: SAME_CONTROL_SRC_B0 NUMERIC "1" -- Retrieval info: PRIVATE: SCANOUTA NUMERIC "0" -- Retrieval info: PRIVATE: SCANOUTB NUMERIC "0" -- Retrieval info: PRIVATE: SHIFTOUTA_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFTOUTA_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFTOUTA_REG STRING "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFT_RIGHT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_OUT_REG STRING "1" -- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SHIFT_RIGHT_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: SHIFT_RIGHT_REG STRING "1" -- Retrieval info: PRIVATE: SHIFT_ROTATE_MODE STRING "None" -- Retrieval info: PRIVATE: SIGNA STRING "Unsigned" -- Retrieval info: PRIVATE: SIGNA_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNA_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNA_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNA_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNA_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: SIGNA_REG STRING "1" -- Retrieval info: PRIVATE: SIGNB STRING "Unsigned" -- Retrieval info: PRIVATE: SIGNB_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNB_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNB_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: SIGNB_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: SIGNB_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: SIGNB_REG STRING "1" -- Retrieval info: PRIVATE: SRCA0 STRING "Multiplier input" -- Retrieval info: PRIVATE: SRCB0 STRING "Multiplier input" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: WIDTHA STRING "18" -- Retrieval info: PRIVATE: WIDTHB STRING "36" -- Retrieval info: PRIVATE: ZERO_CHAINOUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_CHAINOUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_CHAINOUT_REG STRING "1" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_OUT_REG STRING "1" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_ACLR_SRC NUMERIC "3" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_CLK_SRC NUMERIC "0" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_PIPE_REG STRING "1" -- Retrieval info: PRIVATE: ZERO_LOOPBACK_REG STRING "1" -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: CONSTANT: ACCUMULATOR STRING "NO" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_ACLR1 STRING "ACLR3" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_ACLR1 STRING "ACLR3" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_PIPELINE_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: ADDNSUB_MULTIPLIER_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: CHAINOUT_ADDER STRING "NO" -- Retrieval info: CONSTANT: CHAINOUT_REGISTER STRING "UNREGISTERED" -- Retrieval info: CONSTANT: DEDICATED_MULTIPLIER_CIRCUITRY STRING "AUTO" -- Retrieval info: CONSTANT: INPUT_ACLR_A0 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_ACLR_A1 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_ACLR_B0 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_ACLR_B1 STRING "ACLR3" -- Retrieval info: CONSTANT: INPUT_REGISTER_A0 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_REGISTER_A1 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_REGISTER_B0 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_REGISTER_B1 STRING "CLOCK0" -- Retrieval info: CONSTANT: INPUT_SOURCE_A0 STRING "DATAA" -- Retrieval info: CONSTANT: INPUT_SOURCE_A1 STRING "DATAA" -- Retrieval info: CONSTANT: INPUT_SOURCE_B0 STRING "DATAB" -- Retrieval info: CONSTANT: INPUT_SOURCE_B1 STRING "DATAB" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altmult_add" -- Retrieval info: CONSTANT: MULTIPLIER1_DIRECTION STRING "ADD" -- Retrieval info: CONSTANT: MULTIPLIER_ACLR0 STRING "ACLR3" -- Retrieval info: CONSTANT: MULTIPLIER_ACLR1 STRING "ACLR3" -- Retrieval info: CONSTANT: MULTIPLIER_REGISTER0 STRING "CLOCK0" -- Retrieval info: CONSTANT: MULTIPLIER_REGISTER1 STRING "CLOCK0" -- Retrieval info: CONSTANT: NUMBER_OF_MULTIPLIERS NUMERIC "2" -- Retrieval info: CONSTANT: OUTPUT_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: OUTPUT_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: PORT_ADDNSUB1 STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SIGNA STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: PORT_SIGNB STRING "PORT_UNUSED" -- Retrieval info: CONSTANT: REPRESENTATION_A STRING "UNSIGNED" -- Retrieval info: CONSTANT: REPRESENTATION_B STRING "UNSIGNED" -- Retrieval info: CONSTANT: SIGNED_ACLR_A STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_ACLR_B STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_A STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_ACLR_B STRING "ACLR3" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_A STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_PIPELINE_REGISTER_B STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_REGISTER_A STRING "CLOCK0" -- Retrieval info: CONSTANT: SIGNED_REGISTER_B STRING "CLOCK0" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "18" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "36" -- Retrieval info: CONSTANT: WIDTH_CHAININ NUMERIC "1" -- Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "55" -- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_CHAINOUT_OUTPUT_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_OUTPUT_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_ACLR STRING "ACLR3" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_PIPELINE_REGISTER STRING "CLOCK0" -- Retrieval info: CONSTANT: ZERO_LOOPBACK_REGISTER STRING "CLOCK0" -- Retrieval info: USED_PORT: aclr3 0 0 0 0 INPUT GND "aclr3" -- Retrieval info: USED_PORT: clock0 0 0 0 0 INPUT VCC "clock0" -- Retrieval info: USED_PORT: dataa_0 0 0 18 0 INPUT GND "dataa_0[17..0]" -- Retrieval info: USED_PORT: dataa_1 0 0 18 0 INPUT GND "dataa_1[17..0]" -- Retrieval info: USED_PORT: datab_0 0 0 36 0 INPUT GND "datab_0[35..0]" -- Retrieval info: USED_PORT: datab_1 0 0 36 0 INPUT GND "datab_1[35..0]" -- Retrieval info: USED_PORT: ena0 0 0 0 0 INPUT VCC "ena0" -- Retrieval info: USED_PORT: result 0 0 55 0 OUTPUT GND "result[54..0]" -- Retrieval info: CONNECT: @datab 0 0 36 36 datab_1 0 0 36 0 -- Retrieval info: CONNECT: @aclr3 0 0 0 0 aclr3 0 0 0 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock0 0 0 0 0 -- Retrieval info: CONNECT: result 0 0 55 0 @result 0 0 55 0 -- Retrieval info: CONNECT: @dataa 0 0 18 0 dataa_0 0 0 18 0 -- Retrieval info: CONNECT: @dataa 0 0 18 18 dataa_1 0 0 18 0 -- Retrieval info: CONNECT: @ena0 0 0 0 0 ena0 0 0 0 0 -- Retrieval info: CONNECT: @datab 0 0 36 0 datab_0 0 0 36 0 -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.vhd TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.inc FALSE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.cmp TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18.bsf FALSE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_inst.vhd FALSE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_waveforms.html TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL sum36x18_wave*.jpg FALSE FALSE -- Retrieval info: LIB_FILE: altera_mf

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_tanlut1.vhd

10

94202

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_TANLUT1.VHD *** --*** *** --*** Function: Tangent Look Up Table *** --*** (Generated by MATLAB Utility) *** --*** *** --*** 22/12/09 ML *** --*** *** --*** (c) 2009 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_tanlut1 IS PORT ( add : IN STD_LOGIC_VECTOR (9 DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (36 DOWNTO 1); exponent : OUT STD_LOGIC_VECTOR (5 DOWNTO 1) ); END fp_tanlut1; ARCHITECTURE rtl OF fp_tanlut1 IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "000000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5); WHEN "000000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131072,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174764,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5); WHEN "000000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131074,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174780,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5); WHEN "000000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196617,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(1,5); WHEN "000000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131082,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175036,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163860,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219287,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196644,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2074,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229433,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(2,5); WHEN "000001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131114,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179133,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147516,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(204485,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163923,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(100723,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180334,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261788,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196752,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33207,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213175,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71403,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229604,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246559,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246041,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166927,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(3,5); WHEN "000010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131242,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244778,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139469,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18368,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147699,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126224,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155934,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110829,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164174,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39099,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172418,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240249,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180668,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257224,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188924,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157429,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197186,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(8449,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205453,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140199,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213727,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96362,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222007,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(207256,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230295,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16983,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238589,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118443,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246891,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(56191,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255200,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161457,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(4,5); WHEN "000100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131758,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251787,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135921,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182851,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140088,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170994,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144259,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(251287,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148435,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196795,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152616,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(42877,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156801,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87190,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160991,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103258,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165186,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126910,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169386,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194144,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173592,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78984,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177803,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79918,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182019,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233473,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186242,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52073,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190470,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96910,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194704,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142940,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198944,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227466,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203191,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125851,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207444,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137961,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211704,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39590,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215970,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131044,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220243,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188568,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224523,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(250786,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228811,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94417,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233106,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20713,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69033,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241718,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16848,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246035,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166180,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250361,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32888,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254694,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181681,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259036,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128971,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(5,5); WHEN "000111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131693,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88946,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133872,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184862,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110880,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138244,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150087,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140437,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61438,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142634,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(128336,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144836,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110058,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147043,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(28193,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149254,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(166641,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151471,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(23046,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153692,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(143802,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155919,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(26909,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158150,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219127,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160387,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218828,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162630,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48862,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164877,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256563,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167131,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78745,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169390,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63145,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171654,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(233418,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173925,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89145,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176201,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178694,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178484,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(2082,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180772,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108121,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183066,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259423,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185367,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218831,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187675,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11570,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189988,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187394,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192308,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247729,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194635,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218538,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(196969,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126042,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199309,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258866,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201657,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119470,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204011,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(259160,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206373,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180942,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208742,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174537,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211119,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5664,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213502,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226767,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215894,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79866,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218293,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118006,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220700,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108111,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223115,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79560,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225538,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62056,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227969,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85630,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180644,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232856,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115658,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235312,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183865,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237777,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154523,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240251,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(59395,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242733,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192751,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(245225,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62806,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(247725,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(226729,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250235,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(193502,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252754,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(258933,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255283,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194946,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257822,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36018,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260370,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(79189,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(6,5); WHEN "001110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131464,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(48818,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132748,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63557,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134037,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101912,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135331,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182207,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136631,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60853,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137936,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(18783,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139246,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(75024,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140561,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248849,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "001111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141883,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(35488,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143209,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241146,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144542,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99421,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145880,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(154894,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147224,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(165983,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148574,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153522,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149930,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138624,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(151292,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142687,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152660,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(187397,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154035,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32592,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155415,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(224845,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156803,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(313,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158196,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168333,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159596,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(227841,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161003,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202385,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162417,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(115847,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163837,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(254593,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165265,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118901,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166699,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(257978,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168141,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172818,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(169590,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(151210,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171046,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219176,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172510,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140977,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173981,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205552,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175460,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177949,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176947,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85768,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178441,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(219166,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179944,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(82294,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181454,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(228309,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182973,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(162236,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184500,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175979,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186036,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37616,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187580,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39982,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189132,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214250,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190694,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(67791,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192264,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(157055,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193843,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252568,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195432,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125382,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197030,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71365,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198637,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(124791,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200254,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(58341,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(201880,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169556,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(203516,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(232268,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205163,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(20904,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(206819,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(96928,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208485,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235993,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210162,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214385,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211850,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71183,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213548,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(108271,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215257,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(103923,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216977,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(99249,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218708,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(136066,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220450,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(256917,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222204,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242940,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223970,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(138174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(225747,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249580,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(227537,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(98477,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229338,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(255571,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231152,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(243824,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(232979,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111333,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(234818,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169210,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236670,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(205169,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(238536,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7833,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240414,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153192,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "010111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(242306,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169612,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244212,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(110728,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246132,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248065,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248754,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(250014,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33745,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251976,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230368,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253954,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111078,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(255946,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(260182,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(257954,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(214570,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259978,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36603,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(262017,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52004,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(7,5); WHEN "011001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132036,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31728,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133071,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199603,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134115,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(170119,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135167,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(239798,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136228,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(181565,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137298,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(31195,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138376,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(87334,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139463,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125082,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(140559,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(182447,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141665,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36078,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142779,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249858,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143904,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77779,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145038,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85397,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(146182,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52708,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147336,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(22748,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148500,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(39467,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149674,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(147762,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150859,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(131351,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152055,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37096,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153261,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(175023,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154479,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69779,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155708,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33524,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(156948,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117385,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158200,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111488,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159464,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(69279,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160740,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45413,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162028,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95789,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(163329,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(15442,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164642,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125012,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165968,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222206,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167308,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(106129,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168661,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(101608,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170028,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10664,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161129,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172803,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(95974,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174212,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(146219,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175636,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(120264,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(177075,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90370,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178529,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(130571,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179999,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54581,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(181484,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202287,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182986,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(129087,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(184504,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(178815,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(186039,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173083,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187591,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197786,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189161,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78873,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(190748,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(168858,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192354,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36174,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(193978,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38109,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(195621,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(10173,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197283,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(52606,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198965,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6187,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(200666,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238745,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "011111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202389,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(72398,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204132,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142943,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205897,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(40664,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207683,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145442,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(209492,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(54008,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(211323,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(152917,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213178,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45809,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(215056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126393,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216959,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5720,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218886,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(85177,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(220838,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(245917,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(222817,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(111146,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224822,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94854,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226854,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91265,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(228913,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(261427,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231001,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(246970,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233118,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218857,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(235265,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(91152,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237442,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(45510,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(239650,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(7099,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(241889,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(169116,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244161,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(206583,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246467,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(63025,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248806,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(212871,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251181,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(88861,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(253591,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(179473,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256038,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(194218,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258523,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(112522,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(261046,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184058,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(8,5); WHEN "100011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(131804,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202396,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(133106,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(127604,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134429,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(5700,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(135772,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241668,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(137138,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196914,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138527,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(24498,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139938,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(145076,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141373,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(198575,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(142833,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(93021,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144318,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(4818,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(145828,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116886,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147365,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94683,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148929,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(135102,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(150521,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180373,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152142,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(180573,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(153793,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(94005,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155474,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149742,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(157187,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61623,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158932,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(77284,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(160710,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(192200,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(162523,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(150199,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(164371,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230433,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166256,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(199372,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168179,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(97853,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(170140,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(241724,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172142,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173961,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(174185,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(238269,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(176272,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(6999,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(178402,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(116996,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180578,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(173338,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(182802,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(61011,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(185074,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(208074,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(187398,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(13879,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189773,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(209544,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192203,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237754,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "100111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(194690,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89118,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197235,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(41457,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(199840,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(137068,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202508,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(184378,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(205242,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(21881,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(208043,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(44347,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(210914,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156319,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(213859,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(36498,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(216879,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(188732,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(219979,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(109619,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(223161,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(126346,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(226429,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(89021,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229786,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(160435,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233237,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(33224,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(236784,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(244509,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(240434,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83006,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244189,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(215105,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(248056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(68494,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(252038,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(196984,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(256142,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(189406,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(260373,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(249093,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(9,5); WHEN "101010100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132369,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(76283,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101010101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134621,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153043,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101010110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(136947,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(90777,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101010111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(139350,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(80594,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(141834,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(118724,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(144404,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(12410,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147063,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(172855,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(149818,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(49588,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(152672,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(235640,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(155633,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(117182,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(158705,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(242792,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101011111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(161896,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(237423,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(165213,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(125600,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(168663,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(83253,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172254,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191313,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(175996,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191297,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(179899,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(29637,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(183972,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(142533,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188228,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(171026,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101100111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(192680,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(38953,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(197340,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(248662,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(202226,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(84469,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207353,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16170,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(212739,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(177173,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218406,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(161382,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(224376,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(140334,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(230674,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(156722,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101101111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(237328,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218000,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244370,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(144312,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(251834,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(222783,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259761,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(51093,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(10,5); WHEN "101110011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(134097,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(16112,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138592,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(11144,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(143394,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(60483,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148536,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(104003,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101110111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(154056,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(37731,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159996,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(218457,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(166408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191255,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(173350,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(113148,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(180890,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(176944,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(189110,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(163200,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(198106,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(211327,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207994,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(247747,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "101111111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(218914,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(252397,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(231037,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(174172,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(244573,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(197553,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(259786,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(53842,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(11,5); WHEN "110000011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(138503,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(202780,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(148332,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(62994,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(159656,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(230897,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(172847,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(240508,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110000111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(188408,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(183509,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(207041,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(119228,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(229756,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(71260,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(258060,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(153597,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(12,5); WHEN "110001011" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(147154,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(32322,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001100" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(171195,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(78299,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001101" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(204618,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(105365,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001110" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(254248,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(141622,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(13,5); WHEN "110001111" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(167825,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(19278,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5); WHEN "110010000" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(246850,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(149873,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(14,5); WHEN "110010001" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(233251,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(216105,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(15,5); WHEN "110010010" => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(132278,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(191927,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(19,5); WHEN others => mantissa(36 DOWNTO 19) <= conv_std_logic_vector(0,18); mantissa(18 DOWNTO 1) <= conv_std_logic_vector(0,18); exponent(5 DOWNTO 1) <= conv_std_logic_vector(0,5); END CASE; END PROCESS; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_pos52.vhd

10

6864

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_POS52.VHD *** --*** *** --*** Function: 6 Bit Count Leading Zeros *** --*** Component *** --*** *** --*** 22/12/09 ML *** --*** *** --*** (c) 2009 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_pos52 IS GENERIC (start : integer := 10); PORT ( ingroup : IN STD_LOGIC_VECTOR (6 DOWNTO 1); position : OUT STD_LOGIC_VECTOR (6 DOWNTO 1) ); END fp_pos52; ARCHITECTURE sss of fp_pos52 IS BEGIN ptab: PROCESS (ingroup) BEGIN CASE ingroup IS WHEN "000000" => position <= conv_std_logic_vector(0,6); WHEN "000001" => position <= conv_std_logic_vector(start+5,6); WHEN "000010" => position <= conv_std_logic_vector(start+4,6); WHEN "000011" => position <= conv_std_logic_vector(start+4,6); WHEN "000100" => position <= conv_std_logic_vector(start+3,6); WHEN "000101" => position <= conv_std_logic_vector(start+3,6); WHEN "000110" => position <= conv_std_logic_vector(start+3,6); WHEN "000111" => position <= conv_std_logic_vector(start+3,6); WHEN "001000" => position <= conv_std_logic_vector(start+2,6); WHEN "001001" => position <= conv_std_logic_vector(start+2,6); WHEN "001010" => position <= conv_std_logic_vector(start+2,6); WHEN "001011" => position <= conv_std_logic_vector(start+2,6); WHEN "001100" => position <= conv_std_logic_vector(start+2,6); WHEN "001101" => position <= conv_std_logic_vector(start+2,6); WHEN "001110" => position <= conv_std_logic_vector(start+2,6); WHEN "001111" => position <= conv_std_logic_vector(start+2,6); WHEN "010000" => position <= conv_std_logic_vector(start+1,6); WHEN "010001" => position <= conv_std_logic_vector(start+1,6); WHEN "010010" => position <= conv_std_logic_vector(start+1,6); WHEN "010011" => position <= conv_std_logic_vector(start+1,6); WHEN "010100" => position <= conv_std_logic_vector(start+1,6); WHEN "010101" => position <= conv_std_logic_vector(start+1,6); WHEN "010110" => position <= conv_std_logic_vector(start+1,6); WHEN "010111" => position <= conv_std_logic_vector(start+1,6); WHEN "011000" => position <= conv_std_logic_vector(start+1,6); WHEN "011001" => position <= conv_std_logic_vector(start+1,6); WHEN "011010" => position <= conv_std_logic_vector(start+1,6); WHEN "011011" => position <= conv_std_logic_vector(start+1,6); WHEN "011100" => position <= conv_std_logic_vector(start+1,6); WHEN "011101" => position <= conv_std_logic_vector(start+1,6); WHEN "011110" => position <= conv_std_logic_vector(start+1,6); WHEN "011111" => position <= conv_std_logic_vector(start+1,6); WHEN "100000" => position <= conv_std_logic_vector(start,6); WHEN "100001" => position <= conv_std_logic_vector(start,6); WHEN "100010" => position <= conv_std_logic_vector(start,6); WHEN "100011" => position <= conv_std_logic_vector(start,6); WHEN "100100" => position <= conv_std_logic_vector(start,6); WHEN "100101" => position <= conv_std_logic_vector(start,6); WHEN "100110" => position <= conv_std_logic_vector(start,6); WHEN "100111" => position <= conv_std_logic_vector(start,6); WHEN "101000" => position <= conv_std_logic_vector(start,6); WHEN "101001" => position <= conv_std_logic_vector(start,6); WHEN "101010" => position <= conv_std_logic_vector(start,6); WHEN "101011" => position <= conv_std_logic_vector(start,6); WHEN "101100" => position <= conv_std_logic_vector(start,6); WHEN "101101" => position <= conv_std_logic_vector(start,6); WHEN "101110" => position <= conv_std_logic_vector(start,6); WHEN "101111" => position <= conv_std_logic_vector(start,6); WHEN "110000" => position <= conv_std_logic_vector(start,6); WHEN "110001" => position <= conv_std_logic_vector(start,6); WHEN "110010" => position <= conv_std_logic_vector(start,6); WHEN "110011" => position <= conv_std_logic_vector(start,6); WHEN "110100" => position <= conv_std_logic_vector(start,6); WHEN "110101" => position <= conv_std_logic_vector(start,6); WHEN "110110" => position <= conv_std_logic_vector(start,6); WHEN "110111" => position <= conv_std_logic_vector(start,6); WHEN "111000" => position <= conv_std_logic_vector(start,6); WHEN "111001" => position <= conv_std_logic_vector(start,6); WHEN "111010" => position <= conv_std_logic_vector(start,6); WHEN "111011" => position <= conv_std_logic_vector(start,6); WHEN "111100" => position <= conv_std_logic_vector(start,6); WHEN "111101" => position <= conv_std_logic_vector(start,6); WHEN "111110" => position <= conv_std_logic_vector(start,6); WHEN "111111" => position <= conv_std_logic_vector(start,6); WHEN others => position <= conv_std_logic_vector(0,6); END CASE; END PROCESS; END sss;

mit

Reiuiji/ECE368-Lab

Lab 1/MealyFSM/mealy-testbench.vhd

1

2187

--------------------------------------------------- -- School: University of Massachusetts Dartmouth -- Department: Computer and Electrical Engineering -- Engineer: Daniel Noyes -- -- Create Date: SPRING 2016 -- Module Name: MEALY TestBench -- Project Name: MEALY MACHINE -- Target Devices: Spartan-3E -- Tool versions: Xilinx ISE 14.7 -- Description: Mealy -- Finite State Machine (FSM) -- Mealy: The Output is a function of a present -- state and inputs --------------------------------------------------- LIBRARY ieee; USE ieee.STD_LOGIC_1164.ALL; USE ieee.STD_LOGIC_unsigned.all; USE ieee.numeric_std.ALL; entity mealy_tb is end mealy_tb; architecture io_test of mealy_tb is component mealy port ( CLK: in BIT; RST: in BIT; X: in BIT; Z: out BIT); end component; signal CLK_TEST: BIT := '0'; signal RESET_TEST: BIT := '0'; signal X_IN_TEST: BIT := '0'; signal Z_OUT_TEST: BIT; -- Constants -- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2 constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2 -- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2 begin -- Instantiate the Unit Under Testing (UUT) uut: mealy port map( CLK => CLK_TEST, RST => RESET_TEST, X => X_IN_TEST, Z => Z_OUT_TEST ); --Another Method of Port Map --uut: mealy port map(CLK_TEST,RESET_TEST,X_IN_TEST,Z_OUT_TEST); CLK_Process: process begin CLK_TEST <= '0'; wait for period; CLK_TEST <= '1'; wait for period; end process CLK_Process; tb : process begin wait for 100 ns; report "Starting mealy Test Bench" severity NOTE; ----- Unit Test ----- --Reset RESET_TEST <= '1'; wait for period; RESET_TEST <= '0'; wait for period; X_IN_TEST <= '0'; wait for 50 ns; X_IN_TEST <= '1'; wait for 90 ns; X_IN_TEST <= '0'; wait for 130 ns; X_IN_TEST <= '0'; wait for 170 ns; X_IN_TEST <= '1'; wait for 210 ns; X_IN_TEST <= '1'; wait for 250 ns; X_IN_TEST <= '0'; end process; end;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/math_package.vhd

20

16832

-- (C) 2010 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_LIBRARY_PACKAGE.VHD *** --*** *** --*** Function: Component Declarations of *** --*** compiler instantiated library functions *** --*** *** --*** 06/02/08 ML *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** PACKAGE math_package IS --*********************************** --*** SINGLE PRECISION COMPONENTS *** --*********************************** component fp_inv GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component fp_invsqr GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin: IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component fp_sqr PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component fp_exp GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); end component; component fp_log GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component fp_ldexp PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component fp_fabs PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component fp_neg PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component fp_sin GENERIC ( device : integer := 0; width : positive := 30; depth : positive := 18; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_cos GENERIC ( device : integer := 0; width : positive := 30; depth : positive := 18; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_tan PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_asin GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_acos GENERIC (synthesize : integer := 1); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; component fp_atan PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); end component; --*********************************** --*** DOUBLE PRECISION COMPONENTS *** --*********************************** component dp_inv GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC; dividebyzeroout : OUT STD_LOGIC ); end component; component dp_invsqr GENERIC ( doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin: IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component dp_sqr PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; invalidout : OUT STD_LOGIC ); end component; component dp_exp GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doubleaccuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; underflowout : OUT STD_LOGIC ); end component; component dp_log GENERIC ( roundconvert : integer := 0; -- 0 = no round, 1 = round doublespeed : integer := 0; -- 0/1 device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 1 -- 0/1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); -------------------------------------------------- nanout : OUT STD_LOGIC; overflowout : OUT STD_LOGIC; zeroout : OUT STD_LOGIC ); end component; component dp_ldexp PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); bb : IN STD_LOGIC_VECTOR (32 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component dp_fabs PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component dp_neg PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (11 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (52 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (11 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (52 DOWNTO 1); satout, zeroout, nanout : OUT STD_LOGIC ); end component; component dp_fixfloat IS GENERIC ( unsigned : integer := 0; -- unsigned = 0, signed = 1 decimal : integer := 18; fractional : integer := 14; precision : integer := 0; -- single = 0, double = 1 speed : integer := 0 -- low speed = 0, high speed = 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fixed_number : IN STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1); sign : OUT STD_LOGIC; exponent : OUT STD_LOGIC_VECTOR (8+3*precision DOWNTO 1); mantissa : OUT STD_LOGIC_VECTOR (23+29*precision DOWNTO 1) ); END component; component dp_floatfix IS GENERIC ( unsigned : integer := 1; -- unsigned = 0, signed = 1 decimal : integer := 14; fractional : integer := 6; precision : integer := 0; -- single = 0, double = 1 speed : integer := 0 -- low speed = 0, high speed = 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; sign : IN STD_LOGIC; exponent : IN STD_LOGIC_VECTOR (8+3*precision DOWNTO 1); mantissa : IN STD_LOGIC_VECTOR (23+29*precision DOWNTO 1); fixed_number : OUT STD_LOGIC_VECTOR (decimal+fractional DOWNTO 1) ); END component; END math_package;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_rsftcomb64.vhd

10

4574

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_RSFTCOMB64.VHD *** --*** *** --*** Function: Combinatorial arithmetic right *** --*** shift for a 64 bit number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_rsftcomb64 IS PORT ( inbus : IN STD_LOGIC_VECTOR (64 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); END hcc_rsftcomb64; ARCHITECTURE rtl OF hcc_rsftcomb64 IS signal levzip, levone, levtwo, levthr : STD_LOGIC_VECTOR (64 DOWNTO 1); BEGIN levzip <= inbus; -- shift by 0,1,2,3 gaa: FOR k IN 1 TO 61 GENERATE levone(k) <= (levzip(k) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(k+1) AND NOT(shift(2)) AND shift(1)) OR (levzip(k+2) AND shift(2) AND NOT(shift(1))) OR (levzip(k+3) AND shift(2) AND shift(1)); END GENERATE; levone(62) <= (levzip(62) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(63) AND NOT(shift(2)) AND shift(1)) OR (levzip(64) AND shift(2)); levone(63) <= (levzip(63) AND NOT(shift(2)) AND NOT(shift(1))) OR (levzip(64) AND ((shift(2)) OR shift(1))); levone(64) <= levzip(64); -- shift by 0,4,8,12 gba: FOR k IN 1 TO 52 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k+4) AND NOT(shift(4)) AND shift(3)) OR (levone(k+8) AND shift(4) AND NOT(shift(3))) OR (levone(k+12) AND shift(4) AND shift(3)); END GENERATE; gbb: FOR k IN 53 TO 56 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k+4) AND NOT(shift(4)) AND shift(3)) OR (levone(k+8) AND shift(4) AND NOT(shift(3))) OR (levone(64) AND shift(4) AND shift(3)); END GENERATE; gbc: FOR k IN 57 TO 60 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(k+4) AND NOT(shift(4)) AND shift(3)) OR (levone(64) AND shift(4)); END GENERATE; gbd: FOR k IN 61 TO 63 GENERATE levtwo(k) <= (levone(k) AND NOT(shift(4)) AND NOT(shift(3))) OR (levone(64) AND (shift(4) OR shift(3))); END GENERATE; levtwo(64) <= levone(64); gca: FOR k IN 1 TO 16 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR (levtwo(k+48) AND shift(6) AND shift(5)); END GENERATE; gcb: FOR k IN 17 TO 32 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(k+32) AND shift(6) AND NOT(shift(5))) OR (levtwo(64) AND shift(6) AND shift(5)); END GENERATE; gcc: FOR k IN 33 TO 48 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(k+16) AND NOT(shift(6)) AND shift(5)) OR (levtwo(64) AND shift(6) ); END GENERATE; gcd: FOR k IN 49 TO 63 GENERATE levthr(k) <= (levtwo(k) AND NOT(shift(6)) AND NOT(shift(5))) OR (levtwo(64) AND (shift(6) OR shift(5))); END GENERATE; levthr(64) <= levtwo(64); outbus <= levthr; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_lnlutpow.vhd

10

19605

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_LNLUTPOW.VHD *** --*** *** --*** Function: Look Up Table - LN() *** --*** *** --*** Generated by MATLAB Utility *** --*** *** --*** 22/02/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_lnlutpow IS PORT ( add : IN STD_LOGIC_VECTOR (7 DOWNTO 1); logman : OUT STD_LOGIC_VECTOR (23 DOWNTO 1); logexp : OUT STD_LOGIC_VECTOR (8 DOWNTO 1) ); END fp_lnlutpow; ARCHITECTURE rtl OF fp_lnlutpow IS BEGIN pca: PROCESS (add) BEGIN CASE add IS WHEN "0000000" => logman <= conv_std_logic_vector(0,23); logexp <= conv_std_logic_vector(0,8); WHEN "0000001" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(126,8); WHEN "0000010" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(127,8); WHEN "0000011" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(128,8); WHEN "0000100" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(128,8); WHEN "0000101" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(128,8); WHEN "0000110" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(129,8); WHEN "0000111" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001001" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001010" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001011" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(129,8); WHEN "0001100" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(130,8); WHEN "0001101" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(130,8); WHEN "0001110" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(130,8); WHEN "0001111" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010001" => logman <= conv_std_logic_vector(3967289,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010010" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010011" => logman <= conv_std_logic_vector(5420924,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010100" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010101" => logman <= conv_std_logic_vector(6874559,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010110" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(130,8); WHEN "0010111" => logman <= conv_std_logic_vector(8328194,23); logexp <= conv_std_logic_vector(130,8); WHEN "0011000" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011001" => logman <= conv_std_logic_vector(696611,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011010" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011011" => logman <= conv_std_logic_vector(1423428,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011100" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011101" => logman <= conv_std_logic_vector(2150246,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011110" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(131,8); WHEN "0011111" => logman <= conv_std_logic_vector(2877063,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100001" => logman <= conv_std_logic_vector(3603881,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100010" => logman <= conv_std_logic_vector(3967289,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100011" => logman <= conv_std_logic_vector(4330698,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100100" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100101" => logman <= conv_std_logic_vector(5057516,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100110" => logman <= conv_std_logic_vector(5420924,23); logexp <= conv_std_logic_vector(131,8); WHEN "0100111" => logman <= conv_std_logic_vector(5784333,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101000" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101001" => logman <= conv_std_logic_vector(6511151,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101010" => logman <= conv_std_logic_vector(6874559,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101011" => logman <= conv_std_logic_vector(7237968,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101100" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101101" => logman <= conv_std_logic_vector(7964786,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101110" => logman <= conv_std_logic_vector(8328194,23); logexp <= conv_std_logic_vector(131,8); WHEN "0101111" => logman <= conv_std_logic_vector(151498,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110000" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110001" => logman <= conv_std_logic_vector(514906,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110010" => logman <= conv_std_logic_vector(696611,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110011" => logman <= conv_std_logic_vector(878315,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110100" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110101" => logman <= conv_std_logic_vector(1241724,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110110" => logman <= conv_std_logic_vector(1423428,23); logexp <= conv_std_logic_vector(132,8); WHEN "0110111" => logman <= conv_std_logic_vector(1605133,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111000" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111001" => logman <= conv_std_logic_vector(1968541,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111010" => logman <= conv_std_logic_vector(2150246,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111011" => logman <= conv_std_logic_vector(2331950,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111100" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111101" => logman <= conv_std_logic_vector(2695359,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111110" => logman <= conv_std_logic_vector(2877063,23); logexp <= conv_std_logic_vector(132,8); WHEN "0111111" => logman <= conv_std_logic_vector(3058768,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000000" => logman <= conv_std_logic_vector(3240472,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000001" => logman <= conv_std_logic_vector(3422176,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000010" => logman <= conv_std_logic_vector(3603881,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000011" => logman <= conv_std_logic_vector(3785585,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000100" => logman <= conv_std_logic_vector(3967289,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000101" => logman <= conv_std_logic_vector(4148994,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000110" => logman <= conv_std_logic_vector(4330698,23); logexp <= conv_std_logic_vector(132,8); WHEN "1000111" => logman <= conv_std_logic_vector(4512403,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001000" => logman <= conv_std_logic_vector(4694107,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001001" => logman <= conv_std_logic_vector(4875811,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001010" => logman <= conv_std_logic_vector(5057516,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001011" => logman <= conv_std_logic_vector(5239220,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001100" => logman <= conv_std_logic_vector(5420924,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001101" => logman <= conv_std_logic_vector(5602629,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001110" => logman <= conv_std_logic_vector(5784333,23); logexp <= conv_std_logic_vector(132,8); WHEN "1001111" => logman <= conv_std_logic_vector(5966038,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010000" => logman <= conv_std_logic_vector(6147742,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010001" => logman <= conv_std_logic_vector(6329446,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010010" => logman <= conv_std_logic_vector(6511151,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010011" => logman <= conv_std_logic_vector(6692855,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010100" => logman <= conv_std_logic_vector(6874559,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010101" => logman <= conv_std_logic_vector(7056264,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010110" => logman <= conv_std_logic_vector(7237968,23); logexp <= conv_std_logic_vector(132,8); WHEN "1010111" => logman <= conv_std_logic_vector(7419673,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011000" => logman <= conv_std_logic_vector(7601377,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011001" => logman <= conv_std_logic_vector(7783081,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011010" => logman <= conv_std_logic_vector(7964786,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011011" => logman <= conv_std_logic_vector(8146490,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011100" => logman <= conv_std_logic_vector(8328194,23); logexp <= conv_std_logic_vector(132,8); WHEN "1011101" => logman <= conv_std_logic_vector(60645,23); logexp <= conv_std_logic_vector(133,8); WHEN "1011110" => logman <= conv_std_logic_vector(151498,23); logexp <= conv_std_logic_vector(133,8); WHEN "1011111" => logman <= conv_std_logic_vector(242350,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100000" => logman <= conv_std_logic_vector(333202,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100001" => logman <= conv_std_logic_vector(424054,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100010" => logman <= conv_std_logic_vector(514906,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100011" => logman <= conv_std_logic_vector(605759,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100100" => logman <= conv_std_logic_vector(696611,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100101" => logman <= conv_std_logic_vector(787463,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100110" => logman <= conv_std_logic_vector(878315,23); logexp <= conv_std_logic_vector(133,8); WHEN "1100111" => logman <= conv_std_logic_vector(969167,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101000" => logman <= conv_std_logic_vector(1060019,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101001" => logman <= conv_std_logic_vector(1150872,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101010" => logman <= conv_std_logic_vector(1241724,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101011" => logman <= conv_std_logic_vector(1332576,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101100" => logman <= conv_std_logic_vector(1423428,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101101" => logman <= conv_std_logic_vector(1514280,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101110" => logman <= conv_std_logic_vector(1605133,23); logexp <= conv_std_logic_vector(133,8); WHEN "1101111" => logman <= conv_std_logic_vector(1695985,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110000" => logman <= conv_std_logic_vector(1786837,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110001" => logman <= conv_std_logic_vector(1877689,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110010" => logman <= conv_std_logic_vector(1968541,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110011" => logman <= conv_std_logic_vector(2059394,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110100" => logman <= conv_std_logic_vector(2150246,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110101" => logman <= conv_std_logic_vector(2241098,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110110" => logman <= conv_std_logic_vector(2331950,23); logexp <= conv_std_logic_vector(133,8); WHEN "1110111" => logman <= conv_std_logic_vector(2422802,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111000" => logman <= conv_std_logic_vector(2513654,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111001" => logman <= conv_std_logic_vector(2604507,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111010" => logman <= conv_std_logic_vector(2695359,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111011" => logman <= conv_std_logic_vector(2786211,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111100" => logman <= conv_std_logic_vector(2877063,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111101" => logman <= conv_std_logic_vector(2967915,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111110" => logman <= conv_std_logic_vector(3058768,23); logexp <= conv_std_logic_vector(133,8); WHEN "1111111" => logman <= conv_std_logic_vector(3149620,23); logexp <= conv_std_logic_vector(133,8); WHEN others => logman <= conv_std_logic_vector(0,23); logexp <= conv_std_logic_vector(0,8); END CASE; END PROCESS; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_delay.vhd

10

3399

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_DELAY.VHD *** --*** *** --*** Function: Delay an arbitrary width an *** --*** arbitrary number of stages *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY hcc_delay IS GENERIC ( width : positive := 32; delay : positive := 10; synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END hcc_delay; ARCHITECTURE rtl OF hcc_delay IS type delmemfftype IS ARRAY (delay DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1); signal delmemff : delmemfftype; signal delinff, deloutff : STD_LOGIC_VECTOR (width DOWNTO 1); component hcc_delmem GENERIC ( width : positive := 64; delay : positive := 18 ); PORT ( sysclk : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN gda: IF (delay = 1) GENERATE pone: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delinff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delinff <= aa; END IF; END IF; END PROCESS; cc <= delinff; END GENERATE; gdb: IF ( ((delay > 1) AND (delay < 5) AND synthesize = 1) OR ((delay > 1) AND synthesize = 0)) GENERATE ptwo: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR j IN 1 TO delay LOOP FOR k IN 1 TO width LOOP delmemff(j)(k) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delmemff(1)(width DOWNTO 1) <= aa; FOR k IN 2 TO delay LOOP delmemff(k)(width DOWNTO 1) <= delmemff(k-1)(width DOWNTO 1); END LOOP; END IF; END IF; END PROCESS; cc <= delmemff(delay)(width DOWNTO 1); END GENERATE; gdc: IF (delay > 4 AND synthesize = 1) GENERATE core: hcc_delmem GENERIC MAP (width=>width,delay=>delay) PORT MAP (sysclk=>sysclk,enable=>enable, aa=>aa,cc=>cc); END GENERATE; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_del.vhd

10

3579

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_DEL.VHD *** --*** *** --*** Function: Generic Bus Delay *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_del IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_del; ARCHITECTURE rtl OF fp_del IS component fp_del_one IS GENERIC (width : positive := 64); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_del_var IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN genone: IF (pipes = 1) GENERATE delone: fp_del_one GENERIC MAP (width=>width) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; genvar: IF (pipes > 1) GENERATE delvar: fp_del_var GENERIC MAP (width=>width,pipes=>pipes) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aa,cc=>cc); END GENERATE; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp1x_sv.vhd

10

12224

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP1X.VHD *** --*** *** --*** Function: Normalize single precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 28/12/07 - divider target uses all of *** --*** mantissa width *** --*** 06/02/08 - fix divider norm *** --*** 21/03/08 - fix add tree output norm *** --*** 16/04/09 - add NAN support *** --*** 08/11/10 - +0,-0 mantissa case *** --*** *** --*************************************************** --*************************************************** --*** LATENCY : *** --*************************************************** --*************************************************** --*** NOTES: *** --*** normalize signed numbers (x input format) *** --*** for 1x multipliers *** --*** format signed32/36 bit mantissa and 10 bit *** --*** exponent *** --*** unsigned numbers for divider (S,1,23 bit *** --*** mantissa for divider) divider packed into *** --*** 32/36bit mantissa + exponent *** --*************************************************** ENTITY hcc_normfp1x IS GENERIC ( mantissa : positive := 32; -- 32 or 36 inputnormalize : integer := 1; -- 0 = scale, 1 = normalize roundnormalize : integer := 1; normspeed : positive := 2; -- 1 or 2 target : integer := 0 -- 0 = mult target (signed), 1 = divider target (unsigned), 2 adder tree ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); aasat, aazip, aanan : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); ccsat, cczip, ccnan : OUT STD_LOGIC ); END hcc_normfp1x; ARCHITECTURE rtl OF hcc_normfp1x IS type expfftype IS ARRAY (2 DOWNTO 1) OF STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); signal ccnode : STD_LOGIC_VECTOR (mantissa+10 DOWNTO 1); -- scale signal aasatff, aazipff, aananff : STD_LOGIC; signal countaa : STD_LOGIC_VECTOR (3 DOWNTO 1); -- normalize signal zerovec : STD_LOGIC_VECTOR (mantissa-1 DOWNTO 1); signal normfracnode, normnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal normfracff, normff : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal countadjust : STD_LOGIC_VECTOR (10 DOWNTO 1); signal exptopff, expbotff : expfftype; signal maximumnumberff : STD_LOGIC; signal zeroexponent, zeroexponentff : STD_LOGIC; signal exponentmiddle : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aasatdelff, aazipdelff, aanandelff : STD_LOGIC_VECTOR (5 DOWNTO 1); signal countsign : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normsignnode : STD_LOGIC_VECTOR (mantissa DOWNTO 1); signal aaexp, ccexp : STD_LOGIC_VECTOR (10 DOWNTO 1); signal aaman, ccman : STD_LOGIC_VECTOR (mantissa DOWNTO 1); component hcc_normsgn3236 GENERIC ( mantissa : positive := 32; normspeed : positive := 1 -- 1 or 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1) ); end component; component hcc_scmul3236 GENERIC (mantissa : positive := 32); PORT ( frac : IN STD_LOGIC_VECTOR (mantissa DOWNTO 1); scaled : OUT STD_LOGIC_VECTOR (mantissa DOWNTO 1); count : OUT STD_LOGIC_VECTOR (3 DOWNTO 1) ); end component; BEGIN --******************************************************** --*** scale multiplier *** --*** multiplier format [S][1][mantissa....] *** --*** one clock latency *** --******************************************************** -- make sure right format & adjust exponent gsa: IF (inputnormalize = 0) GENERATE psa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; aasatff <= '0'; aazipff <= '0'; aananff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; aasatff <= aasat; aazipff <= aazip; aananff <= aanan; END IF; END IF; END PROCESS; -- no rounding when scaling sma: hcc_scmul3236 GENERIC MAP (mantissa=>mantissa) PORT MAP (frac=>aaff(mantissa+10 DOWNTO 11), scaled=>ccnode(mantissa+10 DOWNTO 11),count=>countaa); ccnode(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + ("0000000" & countaa); cc <= ccnode; ccsat <= aasatff; cczip <= aazipff; ccnan <= aananff; END GENERATE; --******************************************************** --*** full normalization of input - 4 stages *** --*** unlike double, no round required on output, as *** --*** no information lost *** --******************************************************** gna: IF (inputnormalize = 1) GENERATE -- normalize gza: FOR k IN 1 TO mantissa-1 GENERATE zerovec(k) <= '0'; END GENERATE; -- if multiplier, "1" which is nominally in position 27, is shifted to position 31 -- add 4 to exponent when multiplier, 0 for adder gxa: IF (target < 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; gxb: IF (target = 2) GENERATE countadjust <= conv_std_logic_vector (4,10); END GENERATE; pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO mantissa+10 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO mantissa LOOP normfracff(k) <= '0'; normff(k) <= '0'; END LOOP; FOR k IN 1 TO 10 LOOP exptopff(1)(k) <= '0'; exptopff(2)(k) <= '0'; expbotff(1)(k) <= '0'; expbotff(2)(k) <= '0'; END LOOP; maximumnumberff <= '0'; zeroexponentff <= '0'; FOR k IN 1 TO 5 LOOP aasatdelff(k) <= '0'; aazipdelff(k) <= '0'; aanandelff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; normfracff <= normfracnode; --might not get used normff <= normnode; exptopff(1)(10 DOWNTO 1) <= aaff(10 DOWNTO 1) + countadjust; exptopff(2)(10 DOWNTO 1) <= exptopff(1)(10 DOWNTO 1) - ("0000" & countsign); --might not get used expbotff(1)(10 DOWNTO 1) <= exponentmiddle; expbotff(2)(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); -- 08/11/09 maximumnumberff <= aaff(mantissa+10) XOR aaff(mantissa+9); zeroexponentff <= zeroexponent; aasatdelff(1) <= aasat; aazipdelff(1) <= aazip; aanandelff(1) <= aanan; FOR k IN 2 TO 5 LOOP -- 4&5 might not get used aasatdelff(k) <= aasatdelff(k-1); aazipdelff(k) <= aazipdelff(k-1); aanandelff(k) <= aanandelff(k-1); END LOOP; END IF; END IF; END PROCESS; nrmc: hcc_normsgn3236 GENERIC MAP (mantissa=>mantissa,normspeed=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaff(mantissa+10 DOWNTO 11), countout=>countsign, -- stage 1 or 2 fracout=>normfracnode); -- stage 2 or 3 -- 08/11/10 - also where exponentmiddle is used -- '1' if true : if countsign 0, then "111...111" (-0) or "000...000" (+0) case, zero exponent output zeroexponent <= NOT(countsign(6) OR countsign(5) OR countsign(4) OR countsign(3) OR countsign(2) OR countsign(1) OR maximumnumberff); gen_exp_mid: FOR k IN 1 TO 10 GENERATE exponentmiddle(k) <= exptopff(2)(k) AND NOT(zeroexponentff); END GENERATE; gnb: IF (target = 1) GENERATE gnc: FOR k IN 1 TO mantissa GENERATE normsignnode(k) <= normfracff(k) XOR normfracff(mantissa); END GENERATE; normnode(mantissa-1 DOWNTO 1) <= normsignnode(mantissa-1 DOWNTO 1) + (zerovec(mantissa-2 DOWNTO 1) & normfracff(mantissa)); -- 06/02/08 make sure signbit is packed with the mantissa normnode(mantissa) <= normfracff(mantissa); --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normff; ccnode(10 DOWNTO 1) <= expbotff(normspeed)(10 DOWNTO 1); ccsat <= aasatdelff(3+normspeed); cczip <= aazipdelff(3+normspeed); ccnan <= aanandelff(3+normspeed); END GENERATE; gnc: IF (target = 0) GENERATE --*** OUTPUTS *** ccnode(mantissa+10 DOWNTO 11) <= normfracff; gma: IF (normspeed = 1) GENERATE ccnode(10 DOWNTO 1) <= exponentmiddle; END GENERATE; gmb: IF (normspeed > 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed); cczip <= aazipdelff(2+normspeed); ccnan <= aanandelff(2+normspeed); END GENERATE; gnd: IF (target = 2) GENERATE gaa: IF (roundnormalize = 1) GENERATE normnode <= (normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5)) + (zerovec(mantissa-1 DOWNTO 1) & normfracff(4)); END GENERATE; --*** OUTPUTS *** gab: IF (roundnormalize = 0) GENERATE -- 21/03/08 fixed this to SSSSS1XXXXX ccnode(mantissa+10 DOWNTO 11) <= normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa) & normfracff(mantissa DOWNTO 5); END GENERATE; gac: IF (roundnormalize = 1) GENERATE ccnode(mantissa+10 DOWNTO 11) <= normff; END GENERATE; gad: IF (normspeed = 1 AND roundnormalize = 0) GENERATE ccnode(10 DOWNTO 1) <= exponentmiddle; END GENERATE; gae: IF ((normspeed = 2 AND roundnormalize = 0) OR (normspeed = 1 AND roundnormalize = 1)) GENERATE ccnode(10 DOWNTO 1) <= expbotff(1)(10 DOWNTO 1); END GENERATE; gaf: IF (normspeed = 2 AND roundnormalize = 1) GENERATE ccnode(10 DOWNTO 1) <= expbotff(2)(10 DOWNTO 1); END GENERATE; ccsat <= aasatdelff(2+normspeed+roundnormalize); cczip <= aazipdelff(2+normspeed+roundnormalize); ccnan <= aanandelff(2+normspeed+roundnormalize); END GENERATE; cc <= ccnode; END GENERATE; --*** DEBUG *** aaexp <= aa(10 DOWNTO 1); aaman <= aa(mantissa+10 DOWNTO 11); ccexp <= ccnode(10 DOWNTO 1); ccman <= ccnode(mantissa+10 DOWNTO 11); END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/fp_cordic_start1.vhd

10

3284

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_signed.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_CORDIC_START1.VHD *** --*** *** --*** Function: Table for Initial Value of X *** --*** for SIN and COS CORDIC Core *** --*** *** --*** 22/12/09 ML *** --*** *** --*** (c) 2009 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*************************************************** ENTITY fp_cordic_start1 IS GENERIC (width : positive := 36); PORT ( index : IN STD_LOGIC_VECTOR (4 DOWNTO 1); value : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END fp_cordic_start1; ARCHITECTURE rtl of fp_cordic_start1 IS signal valuenode : STD_LOGIC_VECTOR (36 DOWNTO 1); BEGIN pva: PROCESS (index) BEGIN CASE index IS WHEN "0000" => valuenode <= x"26DD3B6A1"; WHEN "0001" => valuenode <= x"36F656C5A"; WHEN "0010" => valuenode <= x"3D731DFFB"; WHEN "0011" => valuenode <= x"3F5743B24"; WHEN "0100" => valuenode <= x"3FD574860"; WHEN "0101" => valuenode <= x"3FF557499"; WHEN "0110" => valuenode <= x"3FFD5574A"; WHEN "0111" => valuenode <= x"3FFF55575"; WHEN "1000" => valuenode <= x"3FFFD5557"; WHEN "1001" => valuenode <= x"3FFFF5555"; WHEN "1010" => valuenode <= x"3FFFFD555"; WHEN "1011" => valuenode <= x"3FFFFF555"; WHEN "1101" => valuenode <= x"3FFFFFD55"; WHEN "1100" => valuenode <= x"3FFFFFF55"; WHEN "1111" => valuenode <= x"3FFFFFFD5"; WHEN "1110" => valuenode <= x"3FFFFFFF5"; WHEN others => valuenode <= x"000000000"; END CASE; END PROCESS; value <= valuenode (36 DOWNTO 37-width); END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

Gaussian_Filter/ip/Gaussian_Filter/dp_addb.vhd

10

2971

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** DOUBLE PRECISION CORE LIBRARY *** --*** *** --*** DP_ADDB.VHD *** --*** *** --*** Function: Behavioral Fixed Point Adder *** --*** *** --*** 31/01/08 ML *** --*** *** --*** (c) 2008 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*** *** --*** *** --*************************************************** ENTITY dp_addb IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); END dp_addb; ARCHITECTURE rtl OF dp_addb IS type pipefftype IS ARRAY (pipes DOWNTO 1) OF STD_LOGIC_VECTOR (width DOWNTO 1); signal delff : STD_LOGIC_VECTOR (width DOWNTO 1); signal pipeff : pipefftype; signal ccnode : STD_LOGIC_VECTOR (width DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (width-1 DOWNTO 1); BEGIN gza: FOR k IN 1 TO width-1 GENERATE zerovec(k) <= '0'; END GENERATE; ccnode <= aa + bb + (zerovec & carryin); gda: IF (pipes = 1) GENERATE pda: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO width LOOP delff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN delff <= ccnode; END IF; END IF; END PROCESS; cc <= delff; END GENERATE; gpa: IF (pipes > 1) GENERATE ppa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO pipes LOOP FOR j IN 1 TO width LOOP pipeff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN pipeff(1)(width DOWNTO 1) <= ccnode; FOR k IN 2 TO pipes LOOP pipeff(k)(width DOWNTO 1) <= pipeff(k-1)(width DOWNTO 1); END LOOP; END IF; END IF; END PROCESS; cc <= pipeff(pipes)(width DOWNTO 1); END GENERATE; END rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/hcc_normfp2x_sv.vhd

10

15740

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** ALTERA FLOATING POINT DATAPATH COMPILER *** --*** *** --*** HCC_NORMFP2X.VHD *** --*** *** --*** Function: Normalize double precision *** --*** number *** --*** *** --*** 14/07/07 ML *** --*** *** --*** (c) 2007 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** 05/03/08 - correct expbotffdepth constant *** --*** 20/04/09 - add NAN support, add overflow *** --*** check in target=0 code *** --*** *** --*** *** --*************************************************** ENTITY hcc_normfp2x IS GENERIC ( roundconvert : integer := 1; -- global switch - round all ieee<=>x conversion when '1' roundnormalize : integer := 1; -- global switch - round all normalizations when '1' normspeed : positive := 3; -- 1,2, or 3 pipes for norm core doublespeed : integer := 1; -- global switch - '0' unpiped adders, '1' piped adders for doubles target : integer := 1; -- 1(internal), 0 (multiplier, divider) synthesize : integer := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1); aasat, aazip, aanan : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (67+10*target DOWNTO 1); ccsat, cczip, ccnan : OUT STD_LOGIC ); END hcc_normfp2x; ARCHITECTURE rtl OF hcc_normfp2x IS constant latency : positive := 3 + normspeed + (roundconvert*doublespeed) + (roundnormalize + roundnormalize*doublespeed); constant exptopffdepth : positive := 2 + roundconvert*doublespeed; constant expbotffdepth : positive := normspeed + roundnormalize*(1+doublespeed); -- 05/03/08 -- if internal format, need to turn back to signed at this point constant invertpoint : positive := 1 + normspeed + (roundconvert*doublespeed); type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1); type expbotfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1); signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1); signal exptopff : exptopfftype; signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1); signal expbotdelff : expbotfftype; signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1); signal adjustexp : STD_LOGIC_VECTOR (13 DOWNTO 1); signal aasatff, aazipff, aananff : STD_LOGIC_VECTOR (latency DOWNTO 1); signal mulsignff : STD_LOGIC_VECTOR (latency-1 DOWNTO 1); signal aainvnode, aaabsnode, aaabsff, aaabs : STD_LOGIC_VECTOR (64 DOWNTO 1); signal normalaa : STD_LOGIC_VECTOR (64 DOWNTO 1); signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1); signal normalaaff : STD_LOGIC_VECTOR (55+9*target DOWNTO 1); signal overflowbitnode : STD_LOGIC_VECTOR (55 DOWNTO 1); signal overflowcondition : STD_LOGIC; signal overflowconditionff : STD_LOGIC; signal mantissa : STD_LOGIC_VECTOR (54+10*target DOWNTO 1); signal aamannode : STD_LOGIC_VECTOR (54+10*target DOWNTO 1); signal aamanff : STD_LOGIC_VECTOR (54+10*target DOWNTO 1); signal sign : STD_LOGIC; component hcc_addpipeb GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component hcc_addpipes GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1); carryin : IN STD_LOGIC; cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component hcc_normus64 IS GENERIC (pipes : positive := 1); -- currently 1 or 3 PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1); countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1); fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1) ); end component; BEGIN gza: FOR k IN 1 TO 64 GENERATE zerovec(k) <= '0'; END GENERATE; --*** INPUT REGISTER *** pna: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 77 LOOP aaff(k) <= '0'; END LOOP; FOR k IN 1 TO exptopffdepth LOOP FOR j IN 1 TO 13 LOOP exptopff(k)(j) <= '0'; END LOOP; END LOOP; FOR k IN 1 TO latency LOOP aasatff(k) <= '0'; aazipff(k) <= '0'; END LOOP; FOR k IN 1 TO latency-1 LOOP mulsignff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaff <= aa; exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + adjustexp; FOR k IN 2 TO exptopffdepth LOOP exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1); END LOOP; aasatff(1) <= aasat; aazipff(1) <= aazip; aananff(1) <= aanan; FOR k IN 2 TO latency LOOP aasatff(k) <= aasatff(k-1); aazipff(k) <= aazipff(k-1); aananff(k) <= aananff(k-1); END LOOP; mulsignff(1) <= aaff(77); FOR k IN 2 TO latency-1 LOOP mulsignff(k) <= mulsignff(k-1); END LOOP; END IF; END IF; END PROCESS; -- exponent bottom half gxa: IF (expbotffdepth = 1) GENERATE pxa: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 13 LOOP expbotff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm); END IF; END IF; END PROCESS; exponent <= expbotff; END GENERATE; gxb: IF (expbotffdepth = 2) GENERATE pxb: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 2 LOOP FOR j IN 1 TO 13 LOOP expbotdelff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm); expbotdelff(2)(13 DOWNTO 1) <= expbotdelff(1)(13 DOWNTO 1) + ("000000000000" & overflowcondition); END IF; END IF; END PROCESS; exponent <= expbotdelff(2)(13 DOWNTO 1); END GENERATE; gxc: IF (expbotffdepth > 2) GENERATE pxb: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO expbotffdepth LOOP FOR j IN 1 TO 13 LOOP expbotdelff(k)(j) <= '0'; END LOOP; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm); FOR k IN 2 TO expbotffdepth-1 LOOP expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1); END LOOP; expbotdelff(expbotffdepth)(13 DOWNTO 1) <= expbotdelff(expbotffdepth-1)(13 DOWNTO 1) + ("000000000000" & overflowcondition); END IF; END IF; END PROCESS; exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1); END GENERATE; -- add 4, because Y format is SSSSS1XXXX, seem to need this for both targets adjustexp <= "0000000000100"; gna: FOR k IN 1 TO 64 GENERATE aainvnode(k) <= aaff(k+13) XOR aaff(77); END GENERATE; --*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) *** gnb: IF ((roundconvert = 0) OR (roundconvert = 1 AND doublespeed = 0)) GENERATE gnc: IF (roundconvert = 0) GENERATE aaabsnode <= aainvnode; END GENERATE; gnd: IF (roundconvert = 1) GENERATE aaabsnode <= aainvnode + (zerovec(63 DOWNTO 1) & aaff(77)); END GENERATE; pnb: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP aaabsff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aaabsff <= aaabsnode; END IF; END IF; END PROCESS; aaabs <= aaabsff; END GENERATE; gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE gsa: IF (synthesize = 0) GENERATE absone: hcc_addpipeb GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aainvnode,bb=>zerovec,carryin=>aaff(77), cc=>aaabs); END GENERATE; gsb: IF (synthesize = 1) GENERATE abstwo: hcc_addpipes GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>aainvnode,bb=>zerovec,carryin=>aaff(77), cc=>aaabs); END GENERATE; END GENERATE; --*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) normcore: hcc_normus64 GENERIC MAP (pipes=>normspeed) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, fracin=>aaabs, countout=>countnorm,fracout=>normalaa); gta: IF (target = 0) GENERATE pnc: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 54 LOOP normalaaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN normalaaff <= normalaa(64 DOWNTO 10); END IF; END IF; END PROCESS; --*** ROUND NORMALIZED VALUE (IF REQUIRED)*** --*** note: normal output is 64 bits gne: IF (roundnormalize = 0) GENERATE mantissa <= normalaaff(55 DOWNTO 2); overflowcondition <= '0'; -- 20/05/09 used in exponent calculation END GENERATE; gnf: IF (roundnormalize = 1) GENERATE overflowbitnode(1) <= normalaaff(1); gova: FOR k IN 2 TO 55 GENERATE overflowbitnode(k) <= overflowbitnode(k-1) AND normalaaff(k); END GENERATE; gng: IF (doublespeed = 0) GENERATE overflowcondition <= overflowbitnode(55); aamannode <= normalaaff(55 DOWNTO 2) + (zerovec(53 DOWNTO 1) & normalaaff(1)); pnd: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 54 LOOP aamanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aamanff <= aamannode; END IF; END IF; END PROCESS; mantissa <= aamanff; END GENERATE; gnh: IF (doublespeed = 1) GENERATE pne: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN overflowconditionff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN overflowconditionff <= overflowbitnode(55); END IF; END IF; END PROCESS; overflowcondition <= overflowconditionff; gra: IF (synthesize = 0) GENERATE rndone: hcc_addpipeb GENERIC MAP (width=>54,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1), cc=>mantissa); END GENERATE; grb: IF (synthesize = 1) GENERATE rndtwo: hcc_addpipes GENERIC MAP (width=>54,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff(55 DOWNTO 2),bb=>zerovec(54 DOWNTO 1),carryin=>normalaaff(1), cc=>mantissa); END GENERATE; END GENERATE; END GENERATE; sign <= mulsignff(latency-1); cc <= sign & (mantissa(54) OR mantissa(53)) & mantissa(52 DOWNTO 1) & exponent; ccsat <= aasatff(latency); cczip <= aazipff(latency); ccnan <= aananff(latency); END GENERATE; gtb: IF (target = 1) GENERATE -- overflow cannot happen here, dont insert overflowcondition <= '0'; -- 20/05/09 used for exponent pnf: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP normalaaff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN FOR k IN 1 TO 59 LOOP normalaaff(k) <= normalaa(k+4) XOR mulsignff(invertpoint); END LOOP; normalaaff(60) <= mulsignff(invertpoint); normalaaff(61) <= mulsignff(invertpoint); normalaaff(62) <= mulsignff(invertpoint); normalaaff(63) <= mulsignff(invertpoint); normalaaff(64) <= mulsignff(invertpoint); END IF; END IF; END PROCESS; gni: IF (roundnormalize = 0) GENERATE mantissa <= normalaaff; -- 1's complement END GENERATE; gnj: IF (roundnormalize = 1) GENERATE gnk: IF (doublespeed = 0) GENERATE aamannode <= normalaaff + (zerovec(63 DOWNTO 1) & mulsignff(invertpoint+1)); png: PROCESS (sysclk, reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 64 LOOP aamanff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN aamanff <= aamannode; END IF; END IF; END PROCESS; mantissa <= aamanff; END GENERATE; gnl: IF (doublespeed = 1) GENERATE grc: IF (synthesize = 0) GENERATE rndone: hcc_addpipeb GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1), cc=>mantissa); END GENERATE; grd: IF (synthesize = 1) GENERATE rndtwo: hcc_addpipes GENERIC MAP (width=>64,pipes=>2) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>normalaaff,bb=>zerovec(64 DOWNTO 1),carryin=>mulsignff(invertpoint+1), cc=>mantissa); END GENERATE; END GENERATE; END GENERATE; cc <= mantissa(64 DOWNTO 1) & exponent; ccsat <= aasatff(latency); cczip <= aazipff(latency); ccnan <= aananff(latency); END GENERATE; end rtl;

mit

Given-Jiang/Gaussian_Filter_Altera_OpenCL_DE1-SoC

bin_Gaussian_Filter/ip/Gaussian_Filter/fp_sin.vhd

10

14482

-- (C) 1992-2014 Altera Corporation. All rights reserved. -- Your use of Altera Corporation's design tools, logic functions and other -- software and tools, and its AMPP partner logic functions, and any output -- files any of the foregoing (including device programming or simulation -- files), and any associated documentation or information are expressly subject -- to the terms and conditions of the Altera Program License Subscription -- Agreement, Altera MegaCore Function License Agreement, or other applicable -- license agreement, including, without limitation, that your use is for the -- sole purpose of programming logic devices manufactured by Altera and sold by -- Altera or its authorized distributors. Please refer to the applicable -- agreement for further details. LIBRARY ieee; LIBRARY work; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; --*************************************************** --*** *** --*** FLOATING POINT CORE LIBRARY *** --*** *** --*** FP_SIN.VHD *** --*** *** --*** Function: Single Precision SIN Core *** --*** *** --*** 10/01/10 ML *** --*** *** --*** (c) 2010 Altera Corporation *** --*** *** --*** Change History *** --*** *** --*** *** --*** *** --*************************************************** --*************************************************** --*** Notes: *** --*** 1. Input < 0.5 radians, take cos(pi/2-input)*** --*** 2. latency = depth + range_depth (11) + 7 *** --*** (1 more than cos) *** --*************************************************** ENTITY fp_sin IS GENERIC ( device : integer := 0; width : positive := 30; depth : positive := 18; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); signout : OUT STD_LOGIC; exponentout : OUT STD_LOGIC_VECTOR (8 DOWNTO 1); mantissaout : OUT STD_LOGIC_VECTOR (23 DOWNTO 1) ); END fp_sin; ARCHITECTURE rtl of fp_sin IS constant cordic_width : positive := width; constant cordic_depth : positive := depth; constant range_depth : positive := 11; signal piovertwo : STD_LOGIC_VECTOR (36 DOWNTO 1); signal zerovec : STD_LOGIC_VECTOR (36 DOWNTO 1); signal input_number : STD_LOGIC_VECTOR (32 DOWNTO 1); signal input_number_delay : STD_LOGIC_VECTOR (32 DOWNTO 1); signal exponentinff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal exponentcheck : STD_LOGIC_VECTOR (9 DOWNTO 1); -- range reduction signal circle : STD_LOGIC_VECTOR (36 DOWNTO 1); signal negcircle : STD_LOGIC_VECTOR (36 DOWNTO 1); signal quadrantsign, quadrantselect : STD_LOGIC; signal positive_quadrant, negative_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1); signal fraction_quadrant : STD_LOGIC_VECTOR (36 DOWNTO 1); signal one_term : STD_LOGIC_VECTOR (36 DOWNTO 1); signal quadrant : STD_LOGIC_VECTOR (34 DOWNTO 1); -- circle to radians mult signal radiansnode : STD_LOGIC_VECTOR (cordic_width DOWNTO 1); signal indexcheck : STD_LOGIC_VECTOR (16 DOWNTO 1); signal indexbit : STD_LOGIC; signal signinff : STD_LOGIC_VECTOR (range_depth DOWNTO 1); signal selectoutputff : STD_LOGIC_VECTOR (range_depth+cordic_depth+5 DOWNTO 1); signal signcalcff : STD_LOGIC_VECTOR (cordic_depth+6 DOWNTO 1); signal quadrant_sumff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal select_sincosff : STD_LOGIC_VECTOR (4 DOWNTO 1); signal fixed_sincos : STD_LOGIC_VECTOR (cordic_width DOWNTO 1); signal fixed_sincosnode : STD_LOGIC_VECTOR (36 DOWNTO 1); signal fixed_sincosff : STD_LOGIC_VECTOR (36 DOWNTO 1); signal countnode : STD_LOGIC_VECTOR (6 DOWNTO 1); signal countff : STD_LOGIC_VECTOR (6 DOWNTO 1); signal mantissanormnode : STD_LOGIC_VECTOR (36 DOWNTO 1); signal mantissanormff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal exponentnormnode : STD_LOGIC_VECTOR (8 DOWNTO 1); signal exponentnormff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal overflownode : STD_LOGIC_VECTOR (24 DOWNTO 1); signal mantissaoutff : STD_LOGIC_VECTOR (23 DOWNTO 1); signal exponentoutff : STD_LOGIC_VECTOR (8 DOWNTO 1); signal signoutff : STD_LOGIC; component fp_range1 GENERIC (device : integer); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; signin : IN STD_LOGIC; exponentin : IN STD_LOGIC_VECTOR (8 DOWNTO 1); mantissain : IN STD_LOGIC_VECTOR (23 DOWNTO 1); circle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1); negcircle : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_cordic_m1 GENERIC ( width : positive := 36; depth : positive := 20; indexpoint : positive := 2 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; radians : IN STD_LOGIC_VECTOR (width DOWNTO 1); --'0'&[width-1:1] indexbit : IN STD_LOGIC; sincosbit : IN STD_LOGIC; sincos : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; component fp_clz36 IS PORT ( mantissa : IN STD_LOGIC_VECTOR (36 DOWNTO 1); leading : OUT STD_LOGIC_VECTOR (6 DOWNTO 1) ); end component; component fp_lsft36 IS PORT ( inbus : IN STD_LOGIC_VECTOR (36 DOWNTO 1); shift : IN STD_LOGIC_VECTOR (6 DOWNTO 1); outbus : OUT STD_LOGIC_VECTOR (36 DOWNTO 1) ); end component; component fp_fxmul GENERIC ( widthaa : positive := 18; widthbb : positive := 18; widthcc : positive := 36; pipes : positive := 1; accuracy : integer := 0; -- 0 = pruned multiplier, 1 = normal multiplier device : integer := 0; -- 0 = "Stratix II", 1 = "Stratix III" (also 4) synthesize : integer := 0 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; dataaa : IN STD_LOGIC_VECTOR (widthaa DOWNTO 1); databb : IN STD_LOGIC_VECTOR (widthbb DOWNTO 1); result : OUT STD_LOGIC_VECTOR (widthcc DOWNTO 1) ); end component; component fp_del IS GENERIC ( width : positive := 64; pipes : positive := 1 ); PORT ( sysclk : IN STD_LOGIC; reset : IN STD_LOGIC; enable : IN STD_LOGIC; aa : IN STD_LOGIC_VECTOR (width DOWNTO 1); cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1) ); end component; BEGIN -- pi/2 = 1.57 piovertwo <= x"c90fdaa22"; zerovec <= x"000000000"; --*** SIN(X) = X when exponent < 115 *** input_number <= signin & exponentin & mantissain; -- level 1 in, level range_depth+cordic_depth+7 out cdin: fp_del GENERIC MAP (width=>32,pipes=>range_depth+cordic_depth+6) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, aa=>input_number, cc=>input_number_delay); --*** RANGE REDUCTION *** crr: fp_range1 GENERIC MAP(device=>device) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, signin=>signin,exponentin=>exponentin,mantissain=>mantissain, circle=>circle,negcircle=>negcircle); quadrantsign <= circle(36); -- sin negative in quadrants 3&4 quadrantselect <= circle(35); -- sin (1-x) in quadants 2&4 gra: FOR k IN 1 TO 34 GENERATE quadrant(k) <= (circle(k) AND NOT(quadrantselect)) OR (negcircle(k) AND quadrantselect); END GENERATE; -- if quadrant >0.5 (when quadrant(34) = 1), use quadrant, else use 1-quadrant, and take cos rather than sin positive_quadrant <= '0' & quadrant & '0'; gnqa: FOR k IN 1 TO 36 GENERATE negative_quadrant(k) <= NOT(positive_quadrant(k)); fraction_quadrant(k) <= (positive_quadrant(k) AND quadrant(34)) OR (negative_quadrant(k) AND NOT(quadrant(34))); END GENERATE; one_term <= NOT(quadrant(34)) & zerovec(35 DOWNTO 1); -- 0 if positive quadrant pfa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO range_depth LOOP signinff(k) <= '0'; END LOOP; FOR k IN 1 TO cordic_depth+6 LOOP signcalcff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP exponentinff(k) <= '0'; END LOOP; FOR k IN 1 TO range_depth+cordic_depth+5 LOOP selectoutputff(k) <= '0'; END LOOP; FOR k IN 1 TO 36 LOOP quadrant_sumff(k) <= '0'; END LOOP; FOR k IN 1 TO 4 LOOP select_sincosff(k) <= '0'; END LOOP; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN signinff(1) <= signin; FOR k IN 2 TO range_depth LOOP signinff(k) <= signinff(k-1); END LOOP; -- level range_depth+1 to range_depth+cordic_depth+6 signcalcff(1) <= quadrantsign XOR signinff(range_depth); FOR k IN 2 TO cordic_depth+6 LOOP signcalcff(k) <= signcalcff(k-1); END LOOP; exponentinff <= exponentin; -- level 1 selectoutputff(1) <= exponentcheck(9); -- level 2 to range_depth+cordic_depth+6 FOR k IN 2 TO range_depth+cordic_depth+5 LOOP selectoutputff(k) <= selectoutputff(k-1); END LOOP; -- range 0-0.9999 quadrant_sumff <= one_term + fraction_quadrant + NOT(quadrant(34)); -- level range_depth+1 -- level range depth+1 to range_depth+4 select_sincosff(1) <= quadrant(34); FOR k IN 2 TO 4 LOOP select_sincosff(k) <= select_sincosff(k-1); END LOOP; END IF; END IF; END PROCESS; -- if exponent < 115, sin = input exponentcheck <= ('0' & exponentinff) - ('0' & x"73"); -- levels range_depth+2,3,4 cmul: fp_fxmul GENERIC MAP (widthaa=>36,widthbb=>36,widthcc=>cordic_width, pipes=>3,synthesize=>1) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, dataaa=>quadrant_sumff,databb=>piovertwo, result=>radiansnode); indexcheck(1) <= radiansnode(cordic_width-1); gica: FOR k IN 2 TO 16 GENERATE indexcheck(k) <= indexcheck(k-1) OR radiansnode(cordic_width-k); END GENERATE; -- for safety, give an extra bit of space indexbit <= NOT(indexcheck(indexpoint+1)); ccc: fp_cordic_m1 GENERIC MAP (width=>cordic_width,depth=>cordic_depth,indexpoint=>indexpoint) PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable, radians=>radiansnode, indexbit=>indexbit, sincosbit=>select_sincosff(4), sincos=>fixed_sincos); gfxa: IF (width < 36) GENERATE fixed_sincosnode <= fixed_sincos & zerovec(36-width DOWNTO 1); END GENERATE; gfxb: IF (width = 36) GENERATE fixed_sincosnode <= fixed_sincos; END GENERATE; clz: fp_clz36 PORT MAP (mantissa=>fixed_sincosnode,leading=>countnode); sft: fp_lsft36 PORT MAP (inbus=>fixed_sincosff,shift=>countff, outbus=>mantissanormnode); -- maximum sin or cos = 1.0 = 1.0e127 single precision -- 1e128 - 1 (leading one) gives correct number exponentnormnode <= "10000000" - ("00" & countff); overflownode(1) <= mantissanormnode(12); gova: FOR k IN 2 TO 24 GENERATE overflownode(k) <= mantissanormnode(k+11) AND overflownode(k-1); END GENERATE; -- OUTPUT poa: PROCESS (sysclk,reset) BEGIN IF (reset = '1') THEN FOR k IN 1 TO 36 LOOP fixed_sincosff(k) <= '0'; END LOOP; countff <= "000000"; FOR k IN 1 TO 23 LOOP mantissanormff(k) <= '0'; mantissaoutff(k) <= '0'; END LOOP; FOR k IN 1 TO 8 LOOP exponentnormff(k) <= '0'; exponentoutff(k) <= '0'; END LOOP; signoutff <= '0'; ELSIF (rising_edge(sysclk)) THEN IF (enable = '1') THEN fixed_sincosff <= fixed_sincosnode; -- level range_depth+cordic_depth+5 countff <= countnode; -- level range_depth+4+cordic_depth+5 -- level range_depth+cordic_depth+6 mantissanormff <= mantissanormnode(35 DOWNTO 13) + mantissanormnode(12); exponentnormff <= exponentnormnode(8 DOWNTO 1) + overflownode(24); -- level range_depth+cordic_depth+7 FOR k IN 1 TO 23 LOOP mantissaoutff(k) <= (mantissanormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR (input_number_delay(k) AND selectoutputff(range_depth+cordic_depth+5)); END LOOP; FOR k IN 1 TO 8 LOOP exponentoutff(k) <= (exponentnormff(k) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR (input_number_delay(k+23) AND selectoutputff(range_depth+cordic_depth+5)); END LOOP; signoutff <= (signcalcff(cordic_depth+6) AND NOT(selectoutputff(range_depth+cordic_depth+5))) OR (input_number_delay(32) AND selectoutputff(range_depth+cordic_depth+5)); END IF; END IF; END PROCESS; mantissaout <= mantissaoutff; exponentout <= exponentoutff; signout <= signoutff; END rtl;

mit

lfmunoz/vhdl

ip_blocks/sip_router_async_s1d2_x4_b/src/sip_router_async_s1d2_x4_b_stellar_cmd.vhd

1

11535

-------------------------------------------------------------------------------- -- file name : sip_router_async_s1d2_x4_b_stellar_cmd.vhd -- -- author : e. barhorst -- -- company : 4dsp -- -- item : number -- -- units : entity -sip_router_async_s1d2_x4_b_stellar_cmd -- arch_itecture - arch_sip_router_async_s1d2_x4_b_stellar_cmd -- -- language : vhdl -- -------------------------------------------------------------------------------- -- description -- =========== -- -- -- notes: -------------------------------------------------------------------------------- -- -- disclaimer: limited warranty and disclaimer. these designs are -- provided to you as is. 4dsp specifically disclaims any -- implied warranties of merchantability, non-infringement, or -- fitness for a particular purpose. 4dsp does not warrant that -- the functions contained in these designs will meet your -- requirements, or that the operation of these designs will be -- uninterrupted or error free, or that defects in the designs -- will be corrected. furthermore, 4dsp does not warrant or -- make any representations regarding use or the results of the -- use of the designs in terms of correctness, accuracy, -- reliability, or otherwise. -- -- limitation of liability. in no event will 4dsp or its -- licensors be liable for any loss of data, lost profits, cost -- or procurement of substitute goods or services, or for any -- special, incidental, consequential, or indirect damages -- arising from the use or operation of the designs or -- accompanying documentation, however caused and on any theory -- of liability. this limitation will apply even if 4dsp -- has been advised of the possibility of such damage. this -- limitation shall apply not-withstanding the failure of the -- essential purpose of any limited remedies herein. -- -- from -- ver pcb mod date changes -- === ======= ======== ======= -- -- 0.0 0 19-01-2009 new version -- 31-08-2009 added the mailbox input port ---------------------------------------------- -- -------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- specify libraries. -------------------------------------------------------------------------------- library ieee ; use ieee.std_logic_unsigned.all ; use ieee.std_logic_misc.all ; use ieee.std_logic_arith.all ; use ieee.std_logic_1164.all ; -------------------------------------------------------------------------------- -- entity declaration -------------------------------------------------------------------------------- entity sip_router_async_s1d2_x4_b_stellar_cmd is generic ( start_addr :std_logic_vector(27 downto 0):=x"0000000"; stop_addr :std_logic_vector(27 downto 0):=x"0000010" ); port ( reset :in std_logic; --command if clk_cmd :in std_logic; --cmd_in and cmd_out are synchronous to this clock; out_cmd :out std_logic_vector(63 downto 0); out_cmd_val :out std_logic; in_cmd :in std_logic_vector(63 downto 0); in_cmd_val :in std_logic; --register interface clk_reg :in std_logic; --register interface is synchronous to this clock out_reg :out std_logic_vector(31 downto 0);--caries the out register data out_reg_val :out std_logic; --the out_reg has valid data (pulse) out_reg_addr :out std_logic_vector(27 downto 0);--out register address in_reg :in std_logic_vector(31 downto 0);--requested register data is placed on this bus in_reg_val :in std_logic; --pulse to indicate requested register is valid in_reg_req :out std_logic; --pulse to request data in_reg_addr :out std_logic_vector(27 downto 0); --requested address --mailbox interface mbx_out_reg :out std_logic_vector(31 downto 0);--value of the mailbox to send mbx_out_val :out std_logic; mbx_in_reg :in std_logic_vector(31 downto 0);--value of the mailbox to send mbx_in_val :in std_logic --pulse to indicate mailbox is valid ); end entity sip_router_async_s1d2_x4_b_stellar_cmd ; -------------------------------------------------------------------------------- -- arch_itecture declaration -------------------------------------------------------------------------------- architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd of sip_router_async_s1d2_x4_b_stellar_cmd is ----------------------------------------------------------------------------------- --constant declarations ----------------------------------------------------------------------------------- constant cmd_mbx :std_logic_vector(3 downto 0) :=x"0"; constant cmd_rd :std_logic_vector(3 downto 0) :=x"2"; constant cmd_wr :std_logic_vector(3 downto 0) :=x"1"; constant cmd_rd_ack :std_logic_vector(3 downto 0) :=x"4"; ----------------------------------------------------------------------------------- --signal declarations ----------------------------------------------------------------------------------- signal register_wr :std_logic; signal register_rd :std_logic; signal out_cmd_val_sig :std_logic; signal in_reg_addr_sig :std_logic_vector(27 downto 0); signal mbx_in_val_sig :std_logic; signal mbx_received :std_logic; signal mbx_out_val_sig :std_logic; ----------------------------------------------------------------------------------- --component declarations ----------------------------------------------------------------------------------- component pulse2pulse port ( in_clk :in std_logic; out_clk :in std_logic; rst :in std_logic; pulsein :in std_logic; inbusy :out std_logic; pulseout :out std_logic ); end component; begin ----------------------------------------------------------------------------------- --component instantiations ----------------------------------------------------------------------------------- p2p0: pulse2pulse port map ( in_clk =>clk_cmd, out_clk =>clk_reg, rst =>reset, pulsein =>register_wr, inbusy =>open, pulseout =>out_reg_val ); p2p1: pulse2pulse port map ( in_clk =>clk_cmd, out_clk =>clk_reg, rst =>reset, pulsein =>register_rd, inbusy =>open, pulseout =>in_reg_req ); p2p2: pulse2pulse port map ( in_clk =>clk_reg, out_clk =>clk_cmd , rst =>reset, pulsein =>in_reg_val, inbusy =>open, pulseout =>out_cmd_val_sig ); p2p3: pulse2pulse port map ( in_clk =>clk_reg, out_clk =>clk_cmd , rst =>reset, pulsein =>mbx_in_val, inbusy =>open, pulseout =>mbx_in_val_sig ); p2p4: pulse2pulse port map ( in_clk =>clk_cmd, out_clk =>clk_reg , rst =>reset, pulsein =>mbx_out_val_sig, inbusy =>open, pulseout =>mbx_out_val ); ----------------------------------------------------------------------------------- --synchronous processes ----------------------------------------------------------------------------------- in_reg_proc: process(clk_cmd ) begin if(clk_cmd'event and clk_cmd='1') then --register the requested address when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then in_reg_addr_sig <= in_cmd(59 downto 32)-start_addr; end if; --generate the read req pulse when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_rd and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then register_rd <= '1'; else register_rd <= '0'; end if; --mailbox has less priority then command acknowledge --create the output packet if (out_cmd_val_sig='1' and mbx_in_val_sig='1') then mbx_received <= '1'; elsif( mbx_received ='1' and out_cmd_val_sig = '0') then mbx_received <= '0'; end if; if (out_cmd_val_sig='1') then out_cmd(31 downto 0) <=in_reg; out_cmd(59 downto 32)<=in_reg_addr_sig+start_addr; out_cmd(63 downto 60)<=cmd_rd_ack; elsif (mbx_in_val_sig='1' or mbx_received='1' ) then out_cmd(31 downto 0) <=mbx_in_reg; out_cmd(59 downto 32)<=start_addr; out_cmd(63 downto 60)<=cmd_mbx; else out_cmd(63 downto 0)<=(others=>'0'); end if; if (out_cmd_val_sig='1') then out_cmd_val <= '1'; elsif (mbx_in_val_sig='1' or mbx_received='1' ) then out_cmd_val <= '1'; else out_cmd_val <= '0'; end if; end if; end process; out_reg_proc: process(clk_cmd ) begin if(clk_cmd'event and clk_cmd='1') then --register the requested address when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then out_reg_addr <= in_cmd(59 downto 32)-start_addr; out_reg <= in_cmd(31 downto 0); end if; --generate the write req pulse when the address is in the modules range if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_wr and in_cmd(59 downto 32) >=start_addr and in_cmd(59 downto 32) <=stop_addr) then register_wr <= '1'; else register_wr <= '0'; end if; if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx) then mbx_out_reg <= in_cmd(31 downto 0); end if; if (in_cmd_val = '1' and in_cmd(63 downto 60) = cmd_mbx ) then mbx_out_val_sig <= '1'; else mbx_out_val_sig <= '0'; end if; end if; end process; ----------------------------------------------------------------------------------- --asynchronous processes ----------------------------------------------------------------------------------- ----------------------------------------------------------------------------------- --asynchronous mapping ----------------------------------------------------------------------------------- in_reg_addr <= in_reg_addr_sig; end architecture arch_sip_router_async_s1d2_x4_b_stellar_cmd ; -- of sip_router_async_s1d2_x4_b_stellar_cmd

mit

lfmunoz/vhdl

types.vhd

1

5888

-- -- Package File Template -- -- Purpose: This package defines supplemental types, subtypes, -- constants, and functions -- -- To use any of the example code shown below, uncomment the lines and modify as necessary -- -- -- -- -- How to use? --note this line.The package is compiled to this directory by default. --so don't forget to include this directory. --library work; --this line also is must.This includes the particular package into your program. --use work.test_pkg.all; -- -- -- -- ---------------------------------------------------------------------------------------------------- -- LIBRARIES ---------------------------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.all; ---------------------------------------------------------------------------------------------------- -- PACKGE ---------------------------------------------------------------------------------------------------- package types is type bus002 is array(natural range <>) of std_logic_vector( 1 downto 0); type bus004 is array(natural range <>) of std_logic_vector( 3 downto 0); type bus005 is array(natural range <>) of std_logic_vector( 4 downto 0); type bus006 is array(natural range <>) of std_logic_vector( 5 downto 0); type bus007 is array(natural range <>) of std_logic_vector( 6 downto 0); type bus008 is array(natural range <>) of std_logic_vector( 7 downto 0); type bus009 is array(natural range <>) of std_logic_vector( 8 downto 0); type bus010 is array(natural range <>) of std_logic_vector( 9 downto 0); type bus011 is array(natural range <>) of std_logic_vector( 10 downto 0); type bus012 is array(natural range <>) of std_logic_vector( 11 downto 0); type bus013 is array(natural range <>) of std_logic_vector( 12 downto 0); type bus014 is array(natural range <>) of std_logic_vector( 13 downto 0); type bus015 is array(natural range <>) of std_logic_vector( 14 downto 0); type bus016 is array(natural range <>) of std_logic_vector( 15 downto 0); type bus017 is array(natural range <>) of std_logic_vector( 16 downto 0); type bus018 is array(natural range <>) of std_logic_vector( 17 downto 0); type bus019 is array(natural range <>) of std_logic_vector( 18 downto 0); type bus020 is array(natural range <>) of std_logic_vector( 19 downto 0); type bus021 is array(natural range <>) of std_logic_vector( 20 downto 0); type bus022 is array(natural range <>) of std_logic_vector( 21 downto 0); type bus023 is array(natural range <>) of std_logic_vector( 22 downto 0); type bus024 is array(natural range <>) of std_logic_vector( 23 downto 0); type bus025 is array(natural range <>) of std_logic_vector( 24 downto 0); type bus026 is array(natural range <>) of std_logic_vector( 25 downto 0); type bus027 is array(natural range <>) of std_logic_vector( 26 downto 0); type bus028 is array(natural range <>) of std_logic_vector( 27 downto 0); type bus029 is array(natural range <>) of std_logic_vector( 28 downto 0); type bus030 is array(natural range <>) of std_logic_vector( 29 downto 0); type bus031 is array(natural range <>) of std_logic_vector( 30 downto 0); type bus032 is array(natural range <>) of std_logic_vector( 31 downto 0); type bus064 is array(natural range <>) of std_logic_vector( 63 downto 0); type bus128 is array(natural range <>) of std_logic_vector(127 downto 0); type bus256 is array(natural range <>) of std_logic_vector(255 downto 0); -- type <new_type> is -- record -- <type_name> : std_logic_vector( 7 downto 0); -- <type_name> : std_logic; -- end record; -- -- Declare constants -- -- constant <constant_name> : time := <time_unit> ns; -- constant <constant_name> : integer := <value; -- -- Declare functions and procedure -- -- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>; -- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>); -- --*************************************************************************************************** end types; --*************************************************************************************************** ---------------------------------------------------------------------------------------------------- -- PACKGE BODY ---------------------------------------------------------------------------------------------------- package body types is function reverse_any_vector (a: in std_logic_vector) return std_logic_vector is variable result: std_logic_vector(a'RANGE); alias aa: std_logic_vector(a'REVERSE_RANGE) is a; begin for i in aa'RANGE loop result(i) := aa(i); end loop; return result; end; ---- Example 1 -- function <function_name> (signal <signal_name> : in <type_declaration> ) return <type_declaration> is -- variable <variable_name> : <type_declaration>; -- begin -- <variable_name> := <signal_name> xor <signal_name>; -- return <variable_name>; -- end <function_name>; ---- Example 2 -- function <function_name> (signal <signal_name> : in <type_declaration>; -- signal <signal_name> : in <type_declaration> ) return <type_declaration> is -- begin -- if (<signal_name> = '1') then -- return <signal_name>; -- else -- return 'Z'; -- end if; -- end <function_name>; ---- Procedure Example -- procedure <procedure_name> (<type_declaration> <constant_name> : in <type_declaration>) is -- -- begin -- -- end <procedure_name>; --************************************************************************************************** end types; --***************************************************************************************************

mit

stanford-ppl/spatial-lang

spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_sys_id/ghrd_10as066n2_sys_id_inst.vhd

1

660

component ghrd_10as066n2_sys_id is port ( clock : in std_logic := 'X'; -- clk readdata : out std_logic_vector(31 downto 0); -- readdata address : in std_logic := 'X'; -- address reset_n : in std_logic := 'X' -- reset_n ); end component ghrd_10as066n2_sys_id; u0 : component ghrd_10as066n2_sys_id port map ( clock => CONNECTED_TO_clock, -- clk.clk readdata => CONNECTED_TO_readdata, -- control_slave.readdata address => CONNECTED_TO_address, -- .address reset_n => CONNECTED_TO_reset_n -- reset.reset_n );

mit

hubertokf/VHDL-Fast-Adders

CLAH/CLA2bits/8bits/CLAH8bits/CLA2bits.vhd

4

760

LIBRARY Ieee; USE ieee.std_logic_1164.all; ENTITY CLA2bits IS PORT ( val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0); SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); CarryIn: IN STD_LOGIC; CarryOut: OUT STD_LOGIC; P, G: OUT STD_LOGIC ); END CLA2bits; ARCHITECTURE strc_cla2bits of CLA2bits is SIGNAL Sum,Gen,Prop,Carry:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN -- soma dos valores e propagação do carry -- Sum<=val1 xor val2; Prop<=val1 or val2; Gen<=val1 and val2; PROCESS (Gen,Prop,Carry) BEGIN Carry(1) <= Gen(0) OR (Prop(0) AND CarryIn); END PROCESS; SomaResult(0) <= Sum(0) XOR CarryIn; SomaResult(1) <= Sum(1) XOR Carry(1); P <= Prop(1) AND Prop(0); G <= Gen(1) OR (Prop(1) AND Gen(0)); END strc_cla2bits;

mit

stanford-ppl/spatial-lang

spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/ghrd_10as066n2/ghrd_10as066n2_f2sdram0_m/ghrd_10as066n2_f2sdram0_m_inst.vhd

1

2111

component ghrd_10as066n2_f2sdram0_m is port ( clk_clk : in std_logic := 'X'; -- clk clk_reset_reset : in std_logic := 'X'; -- reset master_address : out std_logic_vector(31 downto 0); -- address master_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata master_read : out std_logic; -- read master_write : out std_logic; -- write master_writedata : out std_logic_vector(31 downto 0); -- writedata master_waitrequest : in std_logic := 'X'; -- waitrequest master_readdatavalid : in std_logic := 'X'; -- readdatavalid master_byteenable : out std_logic_vector(3 downto 0); -- byteenable master_reset_reset : out std_logic -- reset ); end component ghrd_10as066n2_f2sdram0_m; u0 : component ghrd_10as066n2_f2sdram0_m port map ( clk_clk => CONNECTED_TO_clk_clk, -- clk.clk clk_reset_reset => CONNECTED_TO_clk_reset_reset, -- clk_reset.reset master_address => CONNECTED_TO_master_address, -- master.address master_readdata => CONNECTED_TO_master_readdata, -- .readdata master_read => CONNECTED_TO_master_read, -- .read master_write => CONNECTED_TO_master_write, -- .write master_writedata => CONNECTED_TO_master_writedata, -- .writedata master_waitrequest => CONNECTED_TO_master_waitrequest, -- .waitrequest master_readdatavalid => CONNECTED_TO_master_readdatavalid, -- .readdatavalid master_byteenable => CONNECTED_TO_master_byteenable, -- .byteenable master_reset_reset => CONNECTED_TO_master_reset_reset -- master_reset.reset );

mit

DE5Amigos/SylvesterTheDE2Bot

DE2Botv3Fall16Main/DAC_BEEP.vhd

1

2398

LIBRARY IEEE; LIBRARY ALTERA_MF; LIBRARY LPM; USE ALTERA_MF.ALTERA_MF_COMPONENTS.ALL; USE LPM.LPM_COMPONENTS.ALL; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DAC_BEEP IS PORT( RESETN : IN STD_LOGIC; FSEL : IN STD_LOGIC_VECTOR(7 DOWNTO 0); DURATION : IN STD_LOGIC_VECTOR(7 DOWNTO 0); CS : IN STD_LOGIC; CLK_32Hz : IN STD_LOGIC; DAC_WCLK : IN STD_LOGIC; DAC_BCLK : IN STD_LOGIC; DAC_DAT : OUT STD_LOGIC ); END DAC_BEEP; ARCHITECTURE a OF DAC_BEEP IS signal timer : std_logic_vector(15 downto 0); signal phase : std_logic_vector(15 downto 0); signal step : std_logic_vector(7 downto 0); signal sounddata : std_logic_vector(15 downto 0); BEGIN -- ROM to hold the waveform SOUND_LUT : altsyncram GENERIC MAP ( lpm_type => "altsyncram", width_a => 16, numwords_a => 512, widthad_a => 9, init_file => "SOUND.mif", intended_device_family => "Cyclone II", lpm_hint => "ENABLE_RUNTIME_MOD=NO", operation_mode => "ROM", outdata_aclr_a => "NONE", outdata_reg_a => "UNREGISTERED", power_up_uninitialized => "FALSE" ) PORT MAP ( clock0 => NOT(DAC_WCLK), address_a => phase(10 DOWNTO 2), -- input is angle q_a => sounddata -- output is amplitude ); -- shift register to serialize the data to the DAC DAC_SHIFT : lpm_shiftreg GENERIC MAP ( lpm_direction => "LEFT", lpm_type => "LPM_SHIFTREG", lpm_width => 32 ) PORT MAP ( load => DAC_WCLK, clock => NOT(DAC_BCLK), data => sounddata & sounddata, shiftout => DAC_DAT ); -- process to perform DDS PROCESS(RESETN, CS) BEGIN IF RESETN = '0' THEN phase <= x"0000"; ELSIF RISING_EDGE(DAC_WCLK) THEN IF step = x"00" THEN phase <= x"0000"; ELSE phase <= phase + step; -- increment the phase END IF; END IF; END PROCESS; -- process to catch data from SCOMP and run the timer PROCESS(RESETN, CS, CLK_32Hz) BEGIN IF RESETN = '0' THEN timer <= x"0000"; step <= x"00"; ELSIF CS = '1' THEN timer <= ("000000"&DURATION&"00")-1; -- -1 so that 0 is infinite step <= FSEL; ELSIF RISING_EDGE(CLK_32Hz) THEN IF timer /= x"FFFF" THEN timer <= timer - 1; IF timer = x"0000" THEN step <= x"00"; END IF; END IF; END IF; END PROCESS; END a;

mit

hubertokf/VHDL-Fast-Adders

CLAH/CLA2bits/32bits/CLAH32bits/CLAH32bits.vhd

1

6893

LIBRARY Ieee; USE ieee.std_logic_1164.all; ENTITY CLAH32bits IS PORT ( val1,val2: IN STD_LOGIC_VECTOR(31 DOWNTO 0); CarryIn: IN STD_LOGIC; CarryOut: OUT STD_LOGIC; clk: IN STD_LOGIC; rst: IN STD_LOGIC; SomaResult:OUT STD_LOGIC_VECTOR(31 DOWNTO 0) ); END CLAH32bits; ARCHITECTURE strc_CLAH32bits of CLAH32bits is SIGNAL Cin_sig, Cout_sig: STD_LOGIC; SIGNAL P0_sig, P1_sig, P2_sig, P3_sig, P4_sig, P5_sig, P6_sig, P7_sig, P8_sig, P9_sig, P10_sig, P11_sig, P12_sig, P13_sig, P14_sig, P15_sig: STD_LOGIC; SIGNAL G0_sig, G1_sig, G2_sig, G3_sig, G4_sig, G5_sig, G6_sig, G7_sig, G8_sig, G9_sig, G10_sig, G11_sig, G12_sig, G13_sig, G14_sig, G15_sig: STD_LOGIC; SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig, Cout4_temp_sig, Cout5_temp_sig, Cout6_temp_sig, Cout7_temp_sig: STD_LOGIC; SIGNAL Cout8_temp_sig, Cout9_temp_sig, Cout10_temp_sig, Cout11_temp_sig, Cout12_temp_sig, Cout13_temp_sig, Cout14_temp_sig, Cout15_temp_sig: STD_LOGIC; SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL SomaT1,SomaT2,SomaT3,SomaT4,SomaT5,SomaT6,SomaT7,SomaT8,SomaT9,SomaT10,SomaT11,SomaT12,SomaT13,SomaT14,SomaT15,SomaT16:STD_LOGIC_VECTOR(1 DOWNTO 0); Component CLA2bits PORT ( val1,val2: IN STD_LOGIC_VECTOR(1 DOWNTO 0); SomaResult:OUT STD_LOGIC_VECTOR(1 DOWNTO 0); CarryIn: IN STD_LOGIC; P, G: OUT STD_LOGIC ); end component; Component Reg1Bit PORT ( valIn: in std_logic; clk: in std_logic; rst: in std_logic; valOut: out std_logic ); end component; Component Reg32Bit PORT ( valIn: in std_logic_vector(31 downto 0); clk: in std_logic; rst: in std_logic; valOut: out std_logic_vector(31 downto 0) ); end component; Component CLGB PORT ( P0, P1, G0, G1, Cin: IN STD_LOGIC; Cout1, Cout2: OUT STD_LOGIC ); end component; BEGIN --registradores-- Reg_CarryIn: Reg1Bit PORT MAP ( valIn=>CarryIn, clk=>clk, rst=>rst, valOut=>Cin_sig ); Reg_A: Reg32Bit PORT MAP ( valIn=>val1, clk=>clk, rst=>rst, valOut=>A_sig ); Reg_B: Reg32Bit PORT MAP ( valIn=>val2, clk=>clk, rst=>rst, valOut=>B_sig ); Reg_CarryOut: Reg1Bit PORT MAP ( valIn=>Cout_sig, clk=>clk, rst=>rst, valOut=>CarryOut ); Reg_Ssoma: Reg32Bit PORT MAP ( valIn=>Out_sig, clk=>clk, rst=>rst, valOut=>SomaResult ); Som1: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(1 DOWNTO 0), val2(1 DOWNTO 0) => B_sig(1 DOWNTO 0), CarryIn=>Cin_sig, P=>P0_sig, G=>G0_sig, SomaResult=>SomaT1 ); CLGB1: CLGB PORT MAP( P0=>P0_sig, G0=>G0_sig, P1=>P1_sig, G1=>G1_sig, Cin=>Cin_sig, Cout1=>Cout1_temp_sig, Cout2=>Cout2_temp_sig ); Som2: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(3 DOWNTO 2), val2(1 DOWNTO 0) => B_sig(3 DOWNTO 2), CarryIn=>Cout1_temp_sig, P=>P1_sig, G=>G1_sig, SomaResult=>SomaT2 ); Som3: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(5 DOWNTO 4), val2(1 DOWNTO 0) => B_sig(5 DOWNTO 4), CarryIn=>Cout2_temp_sig, P=>P2_sig, G=>G2_sig, SomaResult=>SomaT3 ); CLGB2: CLGB PORT MAP( P0=>P2_sig, G0=>G2_sig, P1=>P3_sig, G1=>G3_sig, Cin=>Cout2_temp_sig, Cout1=>Cout3_temp_sig, Cout2=>Cout4_temp_sig ); Som4: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(7 DOWNTO 6), val2(1 DOWNTO 0) => B_sig(7 DOWNTO 6), CarryIn=>Cout3_temp_sig, P=>P3_sig, G=>G3_sig, SomaResult=>SomaT4 ); --novoooooooo-- Som5: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(9 DOWNTO 8), val2(1 DOWNTO 0) => B_sig(9 DOWNTO 8), CarryIn=>Cout4_temp_sig, P=>P4_sig, G=>G4_sig, SomaResult=>SomaT5 ); CLGB3: CLGB PORT MAP( P0=>P4_sig, G0=>G4_sig, P1=>P5_sig, G1=>G5_sig, Cin=>Cout4_temp_sig, Cout1=>Cout5_temp_sig, Cout2=>Cout6_temp_sig ); Som6: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(11 DOWNTO 10), val2(1 DOWNTO 0) => B_sig(11 DOWNTO 10), CarryIn=>Cout5_temp_sig, P=>P5_sig, G=>G5_sig, SomaResult=>SomaT6 ); Som7: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(13 DOWNTO 12), val2(1 DOWNTO 0) => B_sig(13 DOWNTO 12), CarryIn=>Cout6_temp_sig, P=>P6_sig, G=>G6_sig, SomaResult=>SomaT7 ); CLGB4: CLGB PORT MAP( P0=>P6_sig, G0=>G6_sig, P1=>P7_sig, G1=>G7_sig, Cin=>Cout6_temp_sig, Cout1=>Cout7_temp_sig, Cout2=>Cout8_temp_sig ); Som8: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(15 DOWNTO 14), val2(1 DOWNTO 0) => B_sig(15 DOWNTO 14), CarryIn=>Cout7_temp_sig, P=>P7_sig, G=>G7_sig, SomaResult=>SomaT8 ); --novoooooooo-- Som9: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(17 DOWNTO 16), val2(1 DOWNTO 0) => B_sig(17 DOWNTO 16), CarryIn=>Cout8_temp_sig, P=>P8_sig, G=>G8_sig, SomaResult=>SomaT9 ); CLGB5: CLGB PORT MAP( P0=>P8_sig, G0=>G8_sig, P1=>P9_sig, G1=>G9_sig, Cin=>Cout8_temp_sig, Cout1=>Cout9_temp_sig, Cout2=>Cout10_temp_sig ); Som10: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(19 DOWNTO 18), val2(1 DOWNTO 0) => B_sig(19 DOWNTO 18), CarryIn=>Cout9_temp_sig, P=>P9_sig, G=>G9_sig, SomaResult=>SomaT10 ); Som11: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(21 DOWNTO 20), val2(1 DOWNTO 0) => B_sig(21 DOWNTO 20), CarryIn=>Cout10_temp_sig, P=>P10_sig, G=>G10_sig, SomaResult=>SomaT11 ); CLGB6: CLGB PORT MAP( P0=>P10_sig, G0=>G10_sig, P1=>P11_sig, G1=>G11_sig, Cin=>Cout10_temp_sig, Cout1=>Cout11_temp_sig, Cout2=>Cout12_temp_sig ); Som12: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(23 DOWNTO 22), val2(1 DOWNTO 0) => B_sig(23 DOWNTO 22), CarryIn=>Cout11_temp_sig, P=>P11_sig, G=>G11_sig, SomaResult=>SomaT12 ); --novoooooooo-- Som13: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(25 DOWNTO 24), val2(1 DOWNTO 0) => B_sig(25 DOWNTO 24), CarryIn=>Cout12_temp_sig, P=>P12_sig, G=>G12_sig, SomaResult=>SomaT13 ); CLGB7: CLGB PORT MAP( P0=>P12_sig, G0=>G12_sig, P1=>P13_sig, G1=>G13_sig, Cin=>Cout12_temp_sig, Cout1=>Cout13_temp_sig, Cout2=>Cout14_temp_sig ); Som14: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(27 DOWNTO 26), val2(1 DOWNTO 0) => B_sig(27 DOWNTO 26), CarryIn=>Cout13_temp_sig, P=>P13_sig, G=>G13_sig, SomaResult=>SomaT14 ); Som15: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(29 DOWNTO 28), val2(1 DOWNTO 0) => B_sig(29 DOWNTO 28), CarryIn=>Cout14_temp_sig, P=>P14_sig, G=>G14_sig, SomaResult=>SomaT15 ); CLGB8: CLGB PORT MAP( P0=>P14_sig, G0=>G14_sig, P1=>P15_sig, G1=>G15_sig, Cin=>Cout14_temp_sig, Cout1=>Cout15_temp_sig, Cout2=>Cout_sig ); Som16: CLA2bits PORT MAP( val1(1 DOWNTO 0) => A_sig(31 DOWNTO 30), val2(1 DOWNTO 0) => B_sig(31 DOWNTO 30), CarryIn=>Cout15_temp_sig, P=>P15_sig, G=>G15_sig, SomaResult=>SomaT16 ); Out_sig <= SomaT16 & SomaT15 & SomaT14 & SomaT13 & SomaT12 & SomaT11 & SomaT10 & SomaT9 & SomaT8 & SomaT7 & SomaT6 & SomaT5 & SomaT4 & SomaT3 & SomaT2 & SomaT1; END strc_CLAH32bits;

mit

DE5Amigos/SylvesterTheDE2Bot

DE2Botv3Fall16Main/lpm_shiftreg_db0.vhd

1

4514

-- megafunction wizard: %LPM_SHIFTREG% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: lpm_shiftreg -- ============================================================ -- File Name: lpm_shiftreg_db0.vhd -- Megafunction Name(s): -- lpm_shiftreg -- -- Simulation Library Files(s): -- lpm -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY lpm; USE lpm.all; ENTITY lpm_shiftreg_db0 IS PORT ( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); load : IN STD_LOGIC ; shiftout : OUT STD_LOGIC ); END lpm_shiftreg_db0; ARCHITECTURE SYN OF lpm_shiftreg_db0 IS SIGNAL sub_wire0 : STD_LOGIC ; COMPONENT lpm_shiftreg GENERIC ( lpm_direction : STRING; lpm_type : STRING; lpm_width : NATURAL ); PORT ( load : IN STD_LOGIC ; clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (31 DOWNTO 0); shiftout : OUT STD_LOGIC ); END COMPONENT; BEGIN shiftout <= sub_wire0; lpm_shiftreg_component : lpm_shiftreg GENERIC MAP ( lpm_direction => "LEFT", lpm_type => "LPM_SHIFTREG", lpm_width => 32 ) PORT MAP ( load => load, clock => clock, data => data, shiftout => sub_wire0 ); END SYN; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ACLR NUMERIC "0" -- Retrieval info: PRIVATE: ALOAD NUMERIC "0" -- Retrieval info: PRIVATE: ASET NUMERIC "0" -- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: CLK_EN NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" -- Retrieval info: PRIVATE: LeftShift NUMERIC "1" -- Retrieval info: PRIVATE: ParallelDataInput NUMERIC "1" -- Retrieval info: PRIVATE: Q_OUT NUMERIC "0" -- Retrieval info: PRIVATE: SCLR NUMERIC "0" -- Retrieval info: PRIVATE: SLOAD NUMERIC "1" -- Retrieval info: PRIVATE: SSET NUMERIC "0" -- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: SerialShiftInput NUMERIC "0" -- Retrieval info: PRIVATE: SerialShiftOutput NUMERIC "1" -- Retrieval info: PRIVATE: nBit NUMERIC "32" -- Retrieval info: CONSTANT: LPM_DIRECTION STRING "LEFT" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_SHIFTREG" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" -- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock -- Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0] -- Retrieval info: USED_PORT: load 0 0 0 0 INPUT NODEFVAL load -- Retrieval info: USED_PORT: shiftout 0 0 0 0 OUTPUT NODEFVAL shiftout -- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 -- Retrieval info: CONNECT: shiftout 0 0 0 0 @shiftout 0 0 0 0 -- Retrieval info: CONNECT: @load 0 0 0 0 load 0 0 0 0 -- Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0 -- Retrieval info: LIBRARY: lpm lpm.lpm_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.vhd TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.cmp TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0.bsf TRUE FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_shiftreg_db0_inst.vhd FALSE -- Retrieval info: LIB_FILE: lpm

mit

lfmunoz/vhdl

ip_blocks/sip_router_async_s1d2_x4_b/src/fifo_async_fwft_64x513_v8_2/fifo_generator_v8_2.vhd

1

341898

------------------------------------------------------------------------------- -- -- FIFO Generator - VHDL Behavioral Model -- ------------------------------------------------------------------------------- -- (c) Copyright 1995 - 2009 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- -- Filename: fifo_generator_v8_2.vhd -- -- Author : Xilinx -- ------------------------------------------------------------------------------- -- Structure: -- -- fifo_generator_v8_2.vhd -- | -- +-fifo_generator_v8_2_conv -- | -- +-fifo_generator_v8_2_bhv_as -- | -- +-fifo_generator_v8_2_bhv_ss -- | -- +-fifo_generator_v8_2_bhv_preload0 -- ------------------------------------------------------------------------------- -- Description: -- -- The VHDL behavioral model for the FIFO Generator. -- -- The behavioral model has three parts: -- - The behavioral model for independent clocks FIFOs (_as) -- - The behavioral model for common clock FIFOs (_ss) -- - The "preload logic" block which implements First-word Fall-through -- ------------------------------------------------------------------------------- --############################################################################# --############################################################################# -- Independent Clocks FIFO Behavioral Model --############################################################################# --############################################################################# ------------------------------------------------------------------------------- -- Library Declaration ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------------------------------------------------------- -- Independent Clocks Entity Declaration - This is NOT the top-level entity ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2_bhv_as IS GENERIC ( --------------------------------------------------------------------------- -- Generic Declarations --------------------------------------------------------------------------- C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 2; C_HAS_RST : integer := 1; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 2; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( --------------------------------------------------------------------------- -- Input and Output Declarations --------------------------------------------------------------------------- RST : IN std_logic; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; WR_RST : IN std_logic; RD_RST : IN std_logic; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); RD_CLK : IN std_logic; RD_EN : IN std_logic; RD_EN_USER : IN std_logic; WR_CLK : IN std_logic; WR_EN : IN std_logic; PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; USER_EMPTY_FB : IN std_logic := '1'; EMPTY : OUT std_logic := '1'; FULL : OUT std_logic := '0'; ALMOST_EMPTY : OUT std_logic := '1'; ALMOST_FULL : OUT std_logic := '0'; PROG_EMPTY : OUT std_logic := '1'; PROG_FULL : OUT std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); VALID : OUT std_logic := '0'; WR_ACK : OUT std_logic := '0'; UNDERFLOW : OUT std_logic := '0'; OVERFLOW : OUT std_logic := '0'; RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_bhv_as; ------------------------------------------------------------------------------- -- Architecture Heading ------------------------------------------------------------------------------- ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_as IS ----------------------------------------------------------------------------- -- FUNCTION actual_fifo_depth -- Returns the actual depth of the FIFO (may differ from what the user -- specified) -- -- The FIFO depth is always represented as 2^n (16,32,64,128,256) -- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain -- options. This function returns the actual depth of the fifo, as seen by -- the user. ------------------------------------------------------------------------------- FUNCTION actual_fifo_depth( C_FIFO_DEPTH : integer; C_PRELOAD_REGS : integer; C_PRELOAD_LATENCY : integer) RETURN integer IS BEGIN RETURN C_FIFO_DEPTH - 1; END actual_fifo_depth; ----------------------------------------------------------------------------- -- FUNCTION div_roundup -- Returns data_value / divisor, with the result rounded-up (if fractional) ------------------------------------------------------------------------------- FUNCTION divroundup ( data_value : integer; divisor : integer) RETURN integer IS VARIABLE div : integer; BEGIN div := data_value/divisor; IF ( (data_value MOD divisor) /= 0) THEN div := div+1; END IF; RETURN div; END divroundup; ----------------------------------------------------------------------------- -- FUNCTION int_2_std_logic -- Returns a single bit (as std_logic) from an integer 1/0 value. ------------------------------------------------------------------------------- FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS BEGIN IF (value=1) THEN RETURN '1'; ELSE RETURN '0'; END IF; END int_2_std_logic; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ----------------------------------------------------------------------------- -- FUNCTION hexstr_to_std_logic_vec -- Returns a std_logic_vector for a hexadecimal string ------------------------------------------------------------------------------- FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index*4)+j < size THEN result((index*4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; ----------------------------------------------------------------------------- -- FUNCTION get_lesser -- Returns a minimum value ------------------------------------------------------------------------------- FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a < b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; ----------------------------------------------------------------------------- -- Derived Constants ----------------------------------------------------------------------------- CONSTANT C_FIFO_WR_DEPTH : integer := actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY); CONSTANT C_FIFO_RD_DEPTH : integer := actual_fifo_depth(C_RD_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY); CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH); CONSTANT C_DEPTH_RATIO_WR : integer := if_then_else( (C_WR_DEPTH > C_RD_DEPTH), (C_WR_DEPTH/C_RD_DEPTH), 1); CONSTANT C_DEPTH_RATIO_RD : integer := if_then_else( (C_RD_DEPTH > C_WR_DEPTH), (C_RD_DEPTH/C_WR_DEPTH), 1); -- "Extra Words" is the number of write words which fit into the two -- first-word fall-through output register stages (if using FWFT). -- For ratios of 1:4 and 1:8, the fractional result is rounded up to 1. -- This value is used to calculate the adjusted PROG_FULL threshold -- value for FWFT. -- EXTRA_WORDS = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD -- WR_DEPTH : RD_DEPTH = 1:2 => EXTRA_WORDS = 1 -- WR_DEPTH : RD_DEPTH = 1:4 => EXTRA_WORDS = 1 (rounded to ceiling) -- WR_DEPTH : RD_DEPTH = 2:1 => EXTRA_WORDS = 4 -- WR_DEPTH : RD_DEPTH = 4:1 => EXTRA_WORDS = 8 CONSTANT EXTRA_WORDS : integer := divroundup(2 * C_DEPTH_RATIO_WR, C_DEPTH_RATIO_RD); -- "Extra words dc" is used for calculating the adjusted WR_DATA_COUNT -- value for the core when using FWFT. -- extra_words_dc = 2 * C_DEPTH_RATIO_WR / C_DEPTH_RATIO_RD -- C_DEPTH_RATIO_WR | C_DEPTH_RATIO_RD | C_PNTR_WIDTH | EXTRA_WORDS_DC -- -----------------|------------------|-----------------|--------------- -- 1 | 8 | C_RD_PNTR_WIDTH | 2 -- 1 | 4 | C_RD_PNTR_WIDTH | 2 -- 1 | 2 | C_RD_PNTR_WIDTH | 2 -- 1 | 1 | C_WR_PNTR_WIDTH | 2 -- 2 | 1 | C_WR_PNTR_WIDTH | 4 -- 4 | 1 | C_WR_PNTR_WIDTH | 8 -- 8 | 1 | C_WR_PNTR_WIDTH | 16 CONSTANT EXTRA_WORDS_DC : integer := if_then_else ((C_DEPTH_RATIO_WR = 1),2, (2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD)); CONSTANT C_PE_THR_ASSERT_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, --FWFT C_PROG_EMPTY_THRESH_ASSERT_VAL ); --NO FWFT CONSTANT C_PE_THR_NEGATE_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, --FWFT C_PROG_EMPTY_THRESH_NEGATE_VAL); --NO FWFT CONSTANT C_PE_THR_ASSERT_VAL_I : integer := C_PE_THR_ASSERT_ADJUSTED; CONSTANT C_PE_THR_NEGATE_VAL_I : integer := C_PE_THR_NEGATE_ADJUSTED; CONSTANT C_PF_THR_ASSERT_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_FULL_THRESH_ASSERT_VAL - EXTRA_WORDS_DC, --FWFT C_PROG_FULL_THRESH_ASSERT_VAL ); --NO FWFT CONSTANT C_PF_THR_NEGATE_ADJUSTED : integer :=if_then_else((C_PRELOAD_REGS=1 and C_PRELOAD_LATENCY=0), C_PROG_FULL_THRESH_NEGATE_VAL - EXTRA_WORDS_DC, --FWFT C_PROG_FULL_THRESH_NEGATE_VAL); --NO FWFT -- NO_ERR_INJECTION will be 1 if ECC is OFF or ECC is ON but no error -- injection is selected. CONSTANT NO_ERR_INJECTION : integer := if_then_else(C_USE_ECC = 0,1, if_then_else(C_ERROR_INJECTION_TYPE = 0,1,0)); -- SBIT_ERR_INJECTION will be 1 if ECC is ON and single bit error injection -- is selected. CONSTANT SBIT_ERR_INJECTION : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 1),1,0); -- DBIT_ERR_INJECTION will be 1 if ECC is ON and double bit error injection -- is selected. CONSTANT DBIT_ERR_INJECTION : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 2),1,0); -- BOTH_ERR_INJECTION will be 1 if ECC is ON and both single and double bit -- error injection are selected. CONSTANT BOTH_ERR_INJECTION : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE = 3),1,0); CONSTANT C_DATA_WIDTH : integer := if_then_else(NO_ERR_INJECTION = 1, C_DIN_WIDTH, C_DIN_WIDTH+2); ------------------------------------------------------------------------------- -- Signals Declaration ------------------------------------------------------------------------------- SIGNAL wr_point : integer := 0; SIGNAL rd_point : integer := 0; SIGNAL wr_point_d1 : integer := 0; SIGNAL rd_point_d1 : integer := 0; SIGNAL num_wr_words : integer := 0; SIGNAL num_rd_words : integer := 0; SIGNAL adj_wr_point : integer := 0; SIGNAL adj_rd_point : integer := 0; SIGNAL adj_wr_point_d1: integer := 0; SIGNAL adj_rd_point_d1: integer := 0; SIGNAL wr_rst_i : std_logic := '0'; SIGNAL rd_rst_i : std_logic := '0'; SIGNAL wr_rst_d1 : std_logic := '0'; SIGNAL wr_ack_i : std_logic := '0'; SIGNAL overflow_i : std_logic := '0'; SIGNAL valid_i : std_logic := '0'; SIGNAL valid_d1 : std_logic := '0'; SIGNAL valid_out : std_logic := '0'; SIGNAL underflow_i : std_logic := '0'; SIGNAL prog_full_reg : std_logic := '0'; SIGNAL prog_empty_reg : std_logic := '1'; SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL width_gt1 : std_logic := '0'; SIGNAL sbiterr_i : std_logic := '0'; SIGNAL dbiterr_i : std_logic := '0'; SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd1 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd2 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd3 : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_pntr_rd : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL adj_wr_pntr_rd : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL wr_data_count_int : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS=>'0'); SIGNAL wdc_fwft_ext_as : std_logic_vector(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS=>'0'); SIGNAL rdc_fwft_ext_as : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d1 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d2 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d3 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr_d4 : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_wr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL adj_rd_pntr_wr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_data_count_int : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS=>'0'); SIGNAL empty_int : boolean := TRUE; SIGNAL empty_comb : std_logic := '1'; SIGNAL ram_rd_en : std_logic := '0'; SIGNAL ram_rd_en_d1 : std_logic := '0'; SIGNAL empty_comb_d1 : std_logic := '1'; SIGNAL almost_empty_int : boolean := TRUE; SIGNAL full_int : boolean := FALSE; SIGNAL full_comb : std_logic := '0'; SIGNAL ram_wr_en : std_logic := '0'; SIGNAL almost_full_int : boolean := FALSE; SIGNAL rd_fwft_cnt : std_logic_vector(3 downto 0) := (others=>'0'); SIGNAL stage1_valid : std_logic := '0'; SIGNAL stage2_valid : std_logic := '0'; SIGNAL diff_pntr_wr : integer := 0; SIGNAL diff_pntr_rd : integer := 0; SIGNAL pf_input_thr_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL pf_input_thr_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); ------------------------------------------------------------------------------- --Linked List types ------------------------------------------------------------------------------- TYPE listtyp; TYPE listptr IS ACCESS listtyp; TYPE listtyp IS RECORD data : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0); older : listptr; newer : listptr; END RECORD; ------------------------------------------------------------------------------- --Processes for linked list implementation. The functions are --1. "newlist" - Create a new linked list --2. "add" - Add a data element to a linked list --3. "read" - Read the data from the tail of the linked list --4. "remove" - Remove the tail from the linked list --5. "sizeof" - Calculate the size of the linked list ------------------------------------------------------------------------------- --1. Create a new linked list PROCEDURE newlist ( head : INOUT listptr; tail : INOUT listptr; cntr : INOUT integer) IS BEGIN head := NULL; tail := NULL; cntr := 0; END; --2. Add a data element to a linked list PROCEDURE add ( head : INOUT listptr; tail : INOUT listptr; data : IN std_logic_vector; cntr : INOUT integer; inj_err : IN std_logic_vector(2 DOWNTO 0) ) IS VARIABLE oldhead : listptr; VARIABLE newhead : listptr; VARIABLE corrupted_data : std_logic_vector(1 DOWNTO 0); BEGIN -------------------------------------------------------------------------- --a. Create a pointer to the existing head, if applicable --b. Create a new node for the list --c. Make the new node point to the old head --d. Make the old head point back to the new node (for doubly-linked list) --e. Put the data into the new head node --f. If the new head we just created is the only node in the list, -- make the tail point to it --g. Return the new head pointer -------------------------------------------------------------------------- IF (head /= NULL) THEN oldhead := head; END IF; newhead := NEW listtyp; newhead.older := oldhead; IF (head /= NULL) THEN oldhead.newer := newhead; END IF; CASE (inj_err(1 DOWNTO 0)) IS -- For both error injection, pass only the double bit error injection -- as dbit error has priority over single bit error injection WHEN "11" => newhead.data := inj_err(1) & '0' & data; WHEN "10" => newhead.data := inj_err(1) & '0' & data; WHEN "01" => newhead.data := '0' & inj_err(0) & data; WHEN OTHERS => newhead.data := '0' & '0' & data; END CASE; -- Increment the counter when data is added to the list cntr := cntr + 1; IF (newhead.older = NULL) THEN tail := newhead; END IF; head := newhead; END; --3. Read the data from the tail of the linked list PROCEDURE read ( tail : INOUT listptr; data : OUT std_logic_vector; err_type : OUT std_logic_vector(1 DOWNTO 0) ) IS VARIABLE data_int : std_logic_vector(C_SMALLER_DATA_WIDTH + 1 DOWNTO 0) := (OTHERS => '0'); VARIABLE err_type_int : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); BEGIN data_int := tail.data; -- MSB two bits carry the error injection type. err_type_int := data_int(data_int'high DOWNTO C_SMALLER_DATA_WIDTH); IF (err_type_int(1) = '0') THEN data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0); ELSIF (C_DOUT_WIDTH = 2) THEN data := NOT data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0); ELSIF (C_DOUT_WIDTH > 2) THEN data := NOT data_int(data_int'high-2) & NOT data_int(data_int'high-3) & data_int(data_int'high-4 DOWNTO 0); ELSE data := data_int(C_SMALLER_DATA_WIDTH - 1 DOWNTO 0); END IF; err_type := err_type_int; END; --4. Remove the tail from the linked list PROCEDURE remove ( head : INOUT listptr; tail : INOUT listptr; cntr : INOUT integer) IS VARIABLE oldtail : listptr; VARIABLE newtail : listptr; BEGIN -------------------------------------------------------------------------- --Make a copy of the old tail pointer --a. If there is no newer node, then set the tail pointer to nothing -- (list is empty) -- otherwise, make the next newer node the new tail, and make it point -- to nothing older --b. Clean up the memory for the old tail node --c. If the new tail is nothing, then we have an empty list, and head -- should also be set to nothing --d. Return the new tail -------------------------------------------------------------------------- oldtail := tail; IF (oldtail.newer = NULL) THEN newtail := NULL; ELSE newtail := oldtail.newer; newtail.older := NULL; END IF; DEALLOCATE(oldtail); IF (newtail = NULL) THEN head := NULL; END IF; tail := newtail; -- Decrement the counter when data is removed from the list cntr := cntr - 1; END; --5. Calculate the size of the linked list PROCEDURE sizeof (head : INOUT listptr; size : OUT integer) IS VARIABLE curlink : listptr; VARIABLE tmpsize : integer := 0; BEGIN -------------------------------------------------------------------------- --a. If head is null, then there is nothing in the list to traverse -- start with the head node (which implies at least one node exists) -- Loop through each node until you find the one that points to nothing -- (the tail) --b. Return the number of nodes -------------------------------------------------------------------------- IF (head /= NULL) THEN curlink := head; tmpsize := 1; WHILE (curlink.older /= NULL) LOOP tmpsize := tmpsize + 1; curlink := curlink.older; END LOOP; END IF; size := tmpsize; END; ----------------------------------------------------------------------------- -- converts integer to specified length std_logic_vector : dropping least -- significant bits if integer is bigger than what can be represented by -- the vector ----------------------------------------------------------------------------- FUNCTION count( fifo_count : IN integer; pointer_width : IN integer; counter_width : IN integer) RETURN std_logic_vector IS VARIABLE temp : std_logic_vector(pointer_width-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE output : std_logic_vector(counter_width - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN temp := CONV_STD_LOGIC_VECTOR(fifo_count, pointer_width); IF (counter_width <= pointer_width) THEN output := temp(pointer_width - 1 DOWNTO pointer_width - counter_width); ELSE output := temp(counter_width - 1 DOWNTO 0); END IF; RETURN output; END count; ------------------------------------------------------------------------------- -- architecture begins here ------------------------------------------------------------------------------- BEGIN ------------------------------------------------------------------------------- -- Asynchronous FIFO ------------------------------------------------------------------------------- gnll_afifo: IF (C_FIFO_TYPE /= 3) GENERATE wr_pntr <= conv_std_logic_vector(wr_point,C_WR_PNTR_WIDTH); rd_pntr <= conv_std_logic_vector(rd_point,C_RD_PNTR_WIDTH); wr_rst_i <= WR_RST; rd_rst_i <= RD_RST; ------------------------------------------------------------------------------- -- calculate number of words in wr and rd domain according to the deepest port -- -- These steps circumvent the linked-list data structure and keep track of -- wr_point and rd_point pointers much like the core itself does. The behavioral -- model uses these to calculate WR_DATA_COUNT and RD_DATA_COUNT. This was done -- because the sizeof() function always returns the exact number of words in -- the linked list, and can not account for delays when crossing clock domains. ------------------------------------------------------------------------------- adj_wr_point <= wr_point * C_DEPTH_RATIO_RD; adj_rd_point <= rd_point * C_DEPTH_RATIO_WR; adj_wr_point_d1<= wr_point_d1 * C_DEPTH_RATIO_RD; adj_rd_point_d1<= rd_point_d1 * C_DEPTH_RATIO_WR; width_gt1 <= '1' WHEN (C_DIN_WIDTH = 2) ELSE '0'; PROCESS (adj_wr_point, adj_wr_point_d1, adj_rd_point, adj_rd_point_d1) BEGIN IF (adj_wr_point >= adj_rd_point_d1) THEN num_wr_words <= adj_wr_point - adj_rd_point_d1; ELSE num_wr_words <= C_WR_DEPTH*C_DEPTH_RATIO_RD + adj_wr_point - adj_rd_point_d1; END IF; IF (adj_wr_point_d1 >= adj_rd_point) THEN num_rd_words <= adj_wr_point_d1 - adj_rd_point; ELSE num_rd_words <= C_RD_DEPTH*C_DEPTH_RATIO_WR + adj_wr_point_d1 - adj_rd_point; END IF; END PROCESS; ------------------------------------------------------------------------------- --Calculate WR_ACK based on C_WR_ACK_LOW parameters ------------------------------------------------------------------------------- gwalow : IF (C_WR_ACK_LOW = 0) GENERATE WR_ACK <= wr_ack_i; END GENERATE gwalow; gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE WR_ACK <= NOT wr_ack_i; END GENERATE gwahgh; ------------------------------------------------------------------------------- --Calculate OVERFLOW based on C_OVERFLOW_LOW parameters ------------------------------------------------------------------------------- govlow : IF (C_OVERFLOW_LOW = 0) GENERATE OVERFLOW <= overflow_i; END GENERATE govlow; govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE OVERFLOW <= NOT overflow_i; END GENERATE govhgh; ------------------------------------------------------------------------------- --Calculate VALID based on C_VALID_LOW ------------------------------------------------------------------------------- gnvl : IF (C_VALID_LOW = 0) GENERATE VALID <= valid_out; END GENERATE gnvl; gnvh : IF (C_VALID_LOW = 1) GENERATE VALID <= NOT valid_out; END GENERATE gnvh; ------------------------------------------------------------------------------- --Calculate UNDERFLOW based on C_UNDERFLOW_LOW ------------------------------------------------------------------------------- gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE UNDERFLOW <= underflow_i; END GENERATE gnul; gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE UNDERFLOW <= NOT underflow_i; END GENERATE gnuh; ------------------------------------------------------------------------------- --Assign PROG_FULL and PROG_EMPTY ------------------------------------------------------------------------------- PROG_FULL <= prog_full_reg; PROG_EMPTY <= prog_empty_reg; ------------------------------------------------------------------------------- --Assign RD_DATA_COUNT and WR_DATA_COUNT ------------------------------------------------------------------------------- rdc: IF (C_HAS_RD_DATA_COUNT=1) GENERATE grdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE RD_DATA_COUNT <= rdc_fwft_ext_as(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH); END GENERATE grdc_fwft_ext; gnrdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE RD_DATA_COUNT <= rd_data_count_int(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH+1-C_RD_DATA_COUNT_WIDTH); END GENERATE gnrdc_fwft_ext; END GENERATE rdc; nrdc: IF (C_HAS_RD_DATA_COUNT=0) GENERATE RD_DATA_COUNT <= (OTHERS=>'0'); END GENERATE nrdc; wdc: IF (C_HAS_WR_DATA_COUNT = 1) GENERATE gwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 1) GENERATE WR_DATA_COUNT <= wdc_fwft_ext_as(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH); END GENERATE gwdc_fwft_ext; gnwdc_fwft_ext: IF (C_USE_FWFT_DATA_COUNT = 0) GENERATE WR_DATA_COUNT <= wr_data_count_int(C_WR_PNTR_WIDTH DOWNTO C_WR_PNTR_WIDTH+1-C_WR_DATA_COUNT_WIDTH); END GENERATE gnwdc_fwft_ext; END GENERATE wdc; nwdc: IF (C_HAS_WR_DATA_COUNT=0) GENERATE WR_DATA_COUNT <= (OTHERS=>'0'); END GENERATE nwdc; ------------------------------------------------------------------------------- -- Write data count calculation if Use Extra Logic option is used ------------------------------------------------------------------------------- wdc_fwft_ext: IF (C_HAS_WR_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE CONSTANT C_PNTR_WIDTH : integer := if_then_else ((C_WR_PNTR_WIDTH>=C_RD_PNTR_WIDTH), C_WR_PNTR_WIDTH, C_RD_PNTR_WIDTH); SIGNAL adjusted_wr_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL adjusted_rd_pntr : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); CONSTANT EXTRA_WORDS : std_logic_vector (C_PNTR_WIDTH DOWNTO 0) := conv_std_logic_vector( if_then_else ((C_DEPTH_RATIO_WR=1),2 ,(2 * C_DEPTH_RATIO_WR/C_DEPTH_RATIO_RD)) ,C_PNTR_WIDTH+1); SIGNAL diff_wr_rd_tmp : std_logic_vector (C_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL diff_wr_rd : std_logic_vector (C_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL wr_data_count_i : std_logic_vector (C_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); BEGIN ----------------------------------------------------------------------------- --Adjust write and read pointer to the deepest port width ----------------------------------------------------------------------------- --C_PNTR_WIDTH=C_WR_PNTR_WIDTH gpadr: IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE adjusted_wr_pntr <= wr_pntr; adjusted_rd_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr_wr; adjusted_rd_pntr(C_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0'); END GENERATE gpadr; --C_PNTR_WIDTH=C_RD_PNTR_WIDTH gpadw: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE adjusted_wr_pntr(C_PNTR_WIDTH-1 DOWNTO C_PNTR_WIDTH-C_WR_PNTR_WIDTH) <= wr_pntr; adjusted_wr_pntr(C_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0)<=(OTHERS=>'0'); adjusted_rd_pntr <= rd_pntr_wr; END GENERATE gpadw; --C_PNTR_WIDTH=C_WR_PNTR_WIDTH=C_RD_PNTR_WIDTH ngpad: IF (C_WR_PNTR_WIDTH = C_RD_PNTR_WIDTH) GENERATE adjusted_wr_pntr <= wr_pntr; adjusted_rd_pntr <= rd_pntr_wr; END GENERATE ngpad; ----------------------------------------------------------------------------- --Calculate words in write domain ----------------------------------------------------------------------------- --Subtract the pointers to get the number of words in the RAM, *THEN* pad --the result diff_wr_rd_tmp <= adjusted_wr_pntr - adjusted_rd_pntr; diff_wr_rd <= '0' & diff_wr_rd_tmp; pwdc : PROCESS (WR_CLK, wr_rst_i) BEGIN IF (wr_rst_i = '1') THEN wr_data_count_i <= (OTHERS=>'0'); ELSIF (WR_CLK'event AND WR_CLK = '1') THEN wr_data_count_i <= diff_wr_rd + extra_words; END IF; END PROCESS pwdc; gdc0: IF (C_WR_PNTR_WIDTH >= C_RD_PNTR_WIDTH) GENERATE wdc_fwft_ext_as <= wr_data_count_i(C_PNTR_WIDTH DOWNTO 0); END GENERATE gdc0; gdc1: IF (C_WR_PNTR_WIDTH < C_RD_PNTR_WIDTH) GENERATE wdc_fwft_ext_as <= wr_data_count_i(C_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH); END GENERATE gdc1; END GENERATE wdc_fwft_ext; ------------------------------------------------------------------------------- -- Read data count calculation if Use Extra Logic option is used ------------------------------------------------------------------------------- rdc_fwft_ext: IF (C_HAS_RD_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE SIGNAL diff_wr_rd_tmp : std_logic_vector (C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL diff_wr_rd : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL zero : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL one : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := conv_std_logic_vector(1, C_RD_PNTR_WIDTH+1); SIGNAL two : std_logic_vector (C_RD_PNTR_WIDTH DOWNTO 0) := conv_std_logic_vector(2, C_RD_PNTR_WIDTH+1); SIGNAL adjusted_wr_pntr_r : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); BEGIN ---------------------------------------------------------------------------- -- If write depth is smaller than read depth, pad write pointer. -- If write depth is bigger than read depth, trim write pointer. ---------------------------------------------------------------------------- gpad : IF (C_RD_PNTR_WIDTH>C_WR_PNTR_WIDTH) GENERATE adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH) <= WR_PNTR_RD; adjusted_wr_pntr_r(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0'); END GENERATE gpad; gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE adjusted_wr_pntr_r <= WR_PNTR_RD(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH); END GENERATE gtrim; ----------------------------------------------------------------------------- -- This accounts for preload 0 by explicitly handling the preload states -- which do not have both output stages filled. As a result, the rd_data_count -- produced will always accurately reflect the number of READABLE words at -- a given time. ----------------------------------------------------------------------------- diff_wr_rd_tmp <= adjusted_wr_pntr_r - RD_PNTR; diff_wr_rd <= '0' & diff_wr_rd_tmp; prdc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN rdc_fwft_ext_as <= zero; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN IF (stage2_valid = '0') THEN rdc_fwft_ext_as <= zero; ELSIF (stage2_valid = '1' AND stage1_valid = '0') THEN rdc_fwft_ext_as <= one; ELSE rdc_fwft_ext_as <= diff_wr_rd + two; END IF; END IF; END PROCESS prdc; END GENERATE rdc_fwft_ext; ------------------------------------------------------------------------------- -- Write pointer adjustment based on pointers width for EMPTY/ALMOST_EMPTY generation ------------------------------------------------------------------------------- gpad : IF (C_RD_PNTR_WIDTH > C_WR_PNTR_WIDTH) GENERATE adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH) <= wr_pntr_rd; adj_wr_pntr_rd(C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0'); END GENERATE gpad; gtrim : IF (C_RD_PNTR_WIDTH<=C_WR_PNTR_WIDTH) GENERATE adj_wr_pntr_rd <= wr_pntr_rd(C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH); END GENERATE gtrim; ------------------------------------------------------------------------------- -- Generate Empty ------------------------------------------------------------------------------- -- ram_rd_en used to determine EMPTY should depend on the EMPTY. ram_rd_en <= RD_EN AND (NOT empty_comb); empty_int <= ((adj_wr_pntr_rd = rd_pntr) OR (ram_rd_en = '1' AND (adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Generate Almost Empty ------------------------------------------------------------------------------- almost_empty_int <= ((adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+1),C_RD_PNTR_WIDTH)) OR (ram_rd_en = '1' AND (adj_wr_pntr_rd = conv_std_logic_vector((conv_integer(rd_pntr)+2),C_RD_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Registering Empty & Almost Empty -- Generate read data count if Use Extra Logic is not selected. ------------------------------------------------------------------------------- empty_proc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN empty_comb <= '1' AFTER C_TCQ; empty_comb_d1 <= '1' AFTER C_TCQ; ALMOST_EMPTY <= '1' AFTER C_TCQ; rd_data_count_int <= (OTHERS => '0') AFTER C_TCQ; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN rd_data_count_int <= ((adj_wr_pntr_rd(C_RD_PNTR_WIDTH-1 DOWNTO 0) - rd_pntr(C_RD_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ; empty_comb_d1 <= empty_comb AFTER C_TCQ; IF (empty_int) THEN empty_comb <= '1' AFTER C_TCQ; ELSE empty_comb <= '0' AFTER C_TCQ; END IF; IF (empty_comb = '0') THEN IF (almost_empty_int) THEN ALMOST_EMPTY <= '1' AFTER C_TCQ; ELSE ALMOST_EMPTY <= '0' AFTER C_TCQ; END IF; END IF; END IF; END PROCESS empty_proc; ------------------------------------------------------------------------------- -- Read pointer adjustment based on pointers width for FULL/ALMOST_FULL generation ------------------------------------------------------------------------------- gfpad : IF (C_WR_PNTR_WIDTH > C_RD_PNTR_WIDTH) GENERATE adj_rd_pntr_wr (C_WR_PNTR_WIDTH-1 DOWNTO C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH) <= rd_pntr_wr; adj_rd_pntr_wr(C_WR_PNTR_WIDTH-C_RD_PNTR_WIDTH-1 DOWNTO 0) <= (OTHERS => '0'); END GENERATE gfpad; gftrim : IF (C_WR_PNTR_WIDTH <= C_RD_PNTR_WIDTH) GENERATE adj_rd_pntr_wr <= rd_pntr_wr(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_WR_PNTR_WIDTH); END GENERATE gftrim; ------------------------------------------------------------------------------- -- Generate Full ------------------------------------------------------------------------------- -- ram_wr_en used to determine FULL should depend on the FULL. ram_wr_en <= WR_EN AND (NOT full_comb); full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+1),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND (adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Generate Almost Full ------------------------------------------------------------------------------- almost_full_int <= ((adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+2),C_WR_PNTR_WIDTH)) OR (ram_wr_en = '1' AND (adj_rd_pntr_wr = conv_std_logic_vector((conv_integer(wr_pntr)+3),C_WR_PNTR_WIDTH)))); ------------------------------------------------------------------------------- -- Registering Full & Almost Full -- Generate write data count if Use Extra Logic is not selected. ------------------------------------------------------------------------------- full_proc : PROCESS (WR_CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN full_comb <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ALMOST_FULL <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; wr_data_count_int <= (OTHERS => '0') AFTER C_TCQ; ELSIF (WR_CLK'event AND WR_CLK = '1') THEN wr_data_count_int <= ((wr_pntr(C_WR_PNTR_WIDTH-1 DOWNTO 0) - adj_rd_pntr_wr(C_WR_PNTR_WIDTH-1 DOWNTO 0)) & '0') AFTER C_TCQ; IF (full_int) THEN full_comb <= '1' AFTER C_TCQ; ELSE full_comb <= '0' AFTER C_TCQ; END IF; IF (RST_FULL_GEN = '1') THEN ALMOST_FULL <= '0' AFTER C_TCQ; ELSIF (full_comb = '0') THEN IF (almost_full_int) THEN ALMOST_FULL <= '1' AFTER C_TCQ; ELSE ALMOST_FULL <= '0' AFTER C_TCQ; END IF; END IF; END IF; END PROCESS full_proc; ------------------------------------------------------------------------------- -- Counter that determines the FWFT read duration. ------------------------------------------------------------------------------- -- C_PRELOAD_LATENCY will be 0 for Non-Built-in FIFO with FWFT. grd_fwft: IF (C_PRELOAD_LATENCY = 0) GENERATE SIGNAL user_empty_fb_d1 : std_logic := '1'; BEGIN grd_fwft_proc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN rd_fwft_cnt <= (others => '0'); user_empty_fb_d1 <= '1'; stage1_valid <= '0'; stage2_valid <= '0'; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN user_empty_fb_d1 <= USER_EMPTY_FB; IF (user_empty_fb_d1 = '0' AND USER_EMPTY_FB = '1') THEN rd_fwft_cnt <= (others => '0') AFTER C_TCQ; ELSIF (empty_comb = '0') THEN IF (RD_EN = '1' AND rd_fwft_cnt < X"5") THEN rd_fwft_cnt <= rd_fwft_cnt + "1" AFTER C_TCQ; END IF; END IF; IF (stage1_valid = '0' AND stage2_valid = '0') THEN IF (empty_comb = '0') THEN stage1_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '0' AFTER C_TCQ; END IF; ELSIF (stage1_valid = '1' AND stage2_valid = '0') THEN IF (empty_comb = '1') THEN stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; END IF; ELSIF (stage1_valid = '0' AND stage2_valid = '1') THEN IF (empty_comb = '1' AND RD_EN_USER = '1') THEN stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '0' AFTER C_TCQ; ELSIF (empty_comb = '0' AND RD_EN_USER = '1') THEN stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '0' AFTER C_TCQ; ELSIF (empty_comb = '0' AND RD_EN_USER = '0') THEN stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; END IF; ELSIF (stage1_valid = '1' AND stage2_valid = '1') THEN IF (empty_comb = '1' AND RD_EN_USER = '1') THEN stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; ELSE stage1_valid <= '1' AFTER C_TCQ; stage2_valid <= '1' AFTER C_TCQ; END IF; ELSE stage1_valid <= '0' AFTER C_TCQ; stage2_valid <= '0' AFTER C_TCQ; END IF; END IF; END PROCESS grd_fwft_proc; END GENERATE grd_fwft; gnrd_fwft: IF (C_PRELOAD_LATENCY > 0) GENERATE rd_fwft_cnt <= X"2"; END GENERATE gnrd_fwft; ------------------------------------------------------------------------------- -- Assign FULL, EMPTY, ALMOST_FULL and ALMOST_EMPTY ------------------------------------------------------------------------------- FULL <= full_comb; EMPTY <= empty_comb; ------------------------------------------------------------------------------- -- Asynchronous FIFO using linked lists ------------------------------------------------------------------------------- FIFO_PROC : PROCESS (WR_CLK, RD_CLK, rd_rst_i, wr_rst_i) --Declare the linked-list head/tail pointers and the size value VARIABLE head : listptr; VARIABLE tail : listptr; VARIABLE size : integer := 0; VARIABLE cntr : integer := 0; VARIABLE cntr_size_var_int : integer := 0; --Data is the internal version of the DOUT bus VARIABLE data : std_logic_vector(c_dout_width - 1 DOWNTO 0) := hexstr_to_std_logic_vec( C_DOUT_RST_VAL, c_dout_width); VARIABLE err_type : std_logic_vector(1 DOWNTO 0) := (OTHERS => '0'); --Temporary values for calculating adjusted prog_empty/prog_full thresholds VARIABLE prog_empty_actual_assert_thresh : integer := 0; VARIABLE prog_empty_actual_negate_thresh : integer := 0; VARIABLE prog_full_actual_assert_thresh : integer := 0; VARIABLE prog_full_actual_negate_thresh : integer := 0; VARIABLE diff_pntr : integer := 0; BEGIN -- Calculate the current contents of the FIFO (size) -- Warning: This value should only be calculated once each time this -- process is entered. -- It is updated instantaneously for both write and read operations, -- so it is not ideal to use for signals which must consider the -- latency of crossing clock domains. -- cntr_size_var_int is updated only once when the process is entered -- This variable is used in the conditions instead of cntr which has the -- latest value. cntr_size_var_int := cntr; -- RESET CONDITIONS IF wr_rst_i = '1' THEN wr_point <= 0 after C_TCQ; wr_point_d1 <= 0 after C_TCQ; wr_pntr_rd1 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr_d2 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr_d3 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr_d4 <= (OTHERS => '0') after C_TCQ; rd_pntr_wr <= (OTHERS => '0') after C_TCQ; --Create new linked list newlist(head, tail,cntr); diff_pntr := 0; --------------------------------------------------------------------------- -- Write to FIFO --------------------------------------------------------------------------- ELSIF WR_CLK'event AND WR_CLK = '1' THEN -- Delay the write pointer before passing to RD_CLK domain to accommodate -- the binary to gray converion wr_pntr_rd1 <= wr_pntr after C_TCQ; -- Read pointer synchronization in WR_CLK domain rd_pntr_wr_d2 <= rd_pntr_wr_d1 after C_TCQ; rd_pntr_wr_d3 <= rd_pntr_wr_d2 after C_TCQ; rd_pntr_wr_d4 <= rd_pntr_wr_d2 after C_TCQ; -- Delay the synchronized read pointer to accommodate the gray to binary -- converion in WR_CLK domain rd_pntr_wr <= rd_pntr_wr_d4 after C_TCQ; wr_point_d1 <= wr_point after C_TCQ; --The following IF statement setup default values of full_i and almost_full_i. --The values might be overwritten in the next IF statement. --If writing, then it is not possible to predict how many --words will actually be in the FIFO after the write concludes --(because the number of reads which happen in this time can -- not be determined). --Therefore, treat it pessimistically and always assume that -- the write will happen without a read (assume the FIFO is -- C_DEPTH_RATIO_RD fuller than it is). --Note: --1. cntr_size_var_int is the deepest depth between write depth and read depth -- cntr_size_var_int/C_DEPTH_RATIO_RD is number of words in the write domain. --2. cntr_size_var_int+C_DEPTH_RATIO_RD: number of write words in the next clock cycle -- if wr_en=1 (C_DEPTH_RATIO_RD=one write word) --3. For asymmetric FIFO, if write width is narrower than read width. Don't -- have to consider partial words. --4. For asymmetric FIFO, if read width is narrower than write width, -- the worse case that FIFO is going to full is depicted in the following -- diagram. Both rd_pntr_a and rd_pntr_b will cause FIFO full. rd_pntr_a -- is the worse case. Therefore, in the calculation, actual FIFO depth is -- substarcted to one write word and added one read word. -- ------- -- | | | -- wr_pntr-->| |--- -- | | | -- ---|--- -- | | | -- | |--- -- | | | -- ---|--- -- | | |<--rd_pntr_a -- | |--- -- | | |<--rd_pntr_b -- ---|--- -- Update full_i and almost_full_i if user is writing to the FIFO. -- Assign overflow and wr_ack. IF WR_EN = '1' THEN IF full_comb /= '1' THEN -- User is writing to a FIFO which is NOT reporting FULL IF cntr_size_var_int/C_DEPTH_RATIO_RD = C_FIFO_WR_DEPTH THEN -- FIFO really is Full --Report Overflow and do not acknowledge the write ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 1 = C_FIFO_WR_DEPTH THEN -- FIFO is almost full -- This write will succeed, and FIFO will go FULL FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP add(head, tail, DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr, (width_gt1 & INJECTDBITERR & INJECTSBITERR)); END LOOP; wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ; ELSIF cntr_size_var_int/C_DEPTH_RATIO_RD + 2 = C_FIFO_WR_DEPTH THEN -- FIFO is one away from almost full -- This write will succeed, and FIFO will go almost_full_i FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP add(head, tail, DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr, (width_gt1 & INJECTDBITERR & INJECTSBITERR)); END LOOP; wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ; ELSE -- FIFO is no where near FULL --Write will succeed, no change in status FOR h IN C_DEPTH_RATIO_RD DOWNTO 1 LOOP add(head, tail, DIN((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)),cntr, (width_gt1 & INJECTDBITERR & INJECTSBITERR)); END LOOP; wr_point <= (wr_point + 1) MOD C_WR_DEPTH after C_TCQ; END IF; ELSE --IF full_i = '1' -- User is writing to a FIFO which IS reporting FULL --Write will fail END IF; --full_i ELSE --WR_EN/='1' --No write attempted, so neither overflow or acknowledge END IF; --WR_EN END IF; --WR_CLK --------------------------------------------------------------------------- -- Read from FIFO --------------------------------------------------------------------------- IF rd_rst_i = '1' THEN -- Whenever user is attempting to read from -- an EMPTY FIFO, the core should report an underflow error, even if -- the core is in a RESET condition. rd_point <= 0 after C_TCQ; rd_point_d1 <= 0 after C_TCQ; rd_pntr_wr_d1 <= (OTHERS => '0') after C_TCQ; wr_pntr_rd2 <= (OTHERS => '0') after C_TCQ; wr_pntr_rd3 <= (OTHERS => '0') after C_TCQ; wr_pntr_rd <= (OTHERS => '0') after C_TCQ; -- DRAM resets asynchronously IF (C_MEMORY_TYPE = 2 AND C_USE_DOUT_RST = 1) THEN data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); END IF; -- BRAM resets synchronously IF (C_MEMORY_TYPE < 2 AND C_USE_DOUT_RST = 1) THEN IF (RD_CLK'event AND RD_CLK = '1') THEN data := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); END IF; END IF; -- Reset only if ECC is not selected as ECC does not support reset. IF (C_USE_ECC = 0) THEN err_type := (OTHERS => '0'); END IF ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- Delay the read pointer before passing to WR_CLK domain to accommodate -- the binary to gray converion rd_pntr_wr_d1 <= rd_pntr after C_TCQ; -- Write pointer synchronization in RD_CLK domain wr_pntr_rd2 <= wr_pntr_rd1 after C_TCQ; wr_pntr_rd3 <= wr_pntr_rd2 after C_TCQ; -- Delay the synchronized write pointer to accommodate the gray to binary -- converion in RD_CLK domain wr_pntr_rd <= wr_pntr_rd3 after C_TCQ; rd_point_d1 <= rd_point after C_TCQ; --------------------------------------------------------------------------- -- Read Latency 1 --------------------------------------------------------------------------- --The following IF statement setup default values of empty_i and --almost_empty_i. The values might be overwritten in the next IF statement. --Note: --cntr_size_var_int/C_DEPTH_RATIO_WR : number of words in read domain. IF (ram_rd_en = '1') THEN IF empty_comb /= '1' THEN IF cntr_size_var_int/C_DEPTH_RATIO_WR = 2 THEN --FIFO is going almost empty FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP read(tail, data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)), err_type); remove(head, tail,cntr); END LOOP; rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ; ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 1 THEN --FIFO is going empty FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP read(tail, data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)), err_type); remove(head, tail,cntr); END LOOP; rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ; ELSIF cntr_size_var_int/C_DEPTH_RATIO_WR = 0 THEN --FIFO is empty ELSE --FIFO is not empty FOR h IN C_DEPTH_RATIO_WR DOWNTO 1 LOOP read(tail, data((C_SMALLER_DATA_WIDTH*h)-1 DOWNTO C_SMALLER_DATA_WIDTH*(h-1)), err_type); remove(head, tail,cntr); END LOOP; rd_point <= (rd_point + 1) MOD C_RD_DEPTH after C_TCQ; END IF; ELSE --FIFO is empty END IF; END IF; --RD_EN END IF; --RD_CLK dout_i <= data after C_TCQ; sbiterr_i <= err_type(0) after C_TCQ; dbiterr_i <= err_type(1) after C_TCQ; END PROCESS; ----------------------------------------------------------------------------- -- Programmable FULL flags ----------------------------------------------------------------------------- proc_pf_input: PROCESS(PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT,PROG_FULL_THRESH_NEGATE) BEGIN IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input pf_input_thr_assert_val <= PROG_FULL_THRESH - conv_integer(EXTRA_WORDS_DC); ELSE -- Multiple threshold inputs pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH); pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE - conv_std_logic_vector(EXTRA_WORDS_DC,C_WR_PNTR_WIDTH); END IF; ELSE -- STD IF (C_PROG_FULL_TYPE = 3) THEN -- Single threshold input pf_input_thr_assert_val <= PROG_FULL_THRESH; ELSE -- Multiple threshold inputs pf_input_thr_assert_val <= PROG_FULL_THRESH_ASSERT; pf_input_thr_negate_val <= PROG_FULL_THRESH_NEGATE; END IF; END IF; END PROCESS proc_pf_input; proc_pf: PROCESS(WR_CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_reg <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); diff_pntr_wr <= 0; ELSIF (WR_CLK'event AND WR_CLK = '1') THEN IF (ram_wr_en = '0') THEN diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) after C_TCQ; ELSIF (ram_wr_en = '1') THEN diff_pntr_wr <= conv_integer(wr_pntr - adj_rd_pntr_wr) + 1 after C_TCQ; END IF; IF (RST_FULL_GEN = '1') THEN prog_full_reg <= '0' after C_TCQ; ELSIF (C_PROG_FULL_TYPE = 1) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN prog_full_reg <= '1' after C_TCQ; ELSE prog_full_reg <= '0' after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSIF (C_PROG_FULL_TYPE = 2) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= C_PF_THR_ASSERT_ADJUSTED) THEN prog_full_reg <= '1' after C_TCQ; ELSIF (diff_pntr_wr < C_PF_THR_NEGATE_ADJUSTED) THEN prog_full_reg <= '0' after C_TCQ; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSIF (C_PROG_FULL_TYPE = 3) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN prog_full_reg <= '1' after C_TCQ; ELSE prog_full_reg <= '0' after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSIF (C_PROG_FULL_TYPE = 4) THEN IF (full_comb = '0') THEN IF (diff_pntr_wr >= conv_integer(pf_input_thr_assert_val)) THEN prog_full_reg <= '1' after C_TCQ; ELSIF (diff_pntr_wr < conv_integer(pf_input_thr_negate_val)) THEN prog_full_reg <= '0' after C_TCQ; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; ELSE prog_full_reg <= prog_full_reg after C_TCQ; END IF; END IF; --C_PROG_FULL_TYPE END IF; -- WR_CLK END PROCESS proc_pf; --------------------------------------------------------------------------- -- Programmable EMPTY Flags --------------------------------------------------------------------------- proc_pe: PROCESS(RD_CLK, rd_rst_i) VARIABLE pe_thr_assert_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE pe_thr_negate_val : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN IF (rd_rst_i = '1') THEN diff_pntr_rd <= 0; prog_empty_reg <= '1'; pe_thr_assert_val := (OTHERS => '0'); pe_thr_negate_val := (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK = '1') THEN IF (ram_rd_en = '0') THEN diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) after C_TCQ; ELSIF (ram_rd_en = '1') THEN diff_pntr_rd <= conv_integer(adj_wr_pntr_rd - rd_pntr) - 1 after C_TCQ; ELSE diff_pntr_rd <= diff_pntr_rd after C_TCQ; END IF; IF (C_PROG_EMPTY_TYPE = 1) THEN IF (empty_comb = '0') THEN IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN prog_empty_reg <= '1' after C_TCQ; ELSE prog_empty_reg <= '0' after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSIF (C_PROG_EMPTY_TYPE = 2) THEN IF (empty_comb = '0') THEN IF (diff_pntr_rd <= C_PE_THR_ASSERT_VAL_I) THEN prog_empty_reg <= '1' after C_TCQ; ELSIF (diff_pntr_rd > C_PE_THR_NEGATE_VAL_I) THEN prog_empty_reg <= '0' after C_TCQ; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSIF (C_PROG_EMPTY_TYPE = 3) THEN -- If empty input threshold is selected, then subtract 2 for FWFT to -- compensate the FWFT stage, otherwise assign the input value. IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT pe_thr_assert_val := PROG_EMPTY_THRESH - "10"; ELSE pe_thr_assert_val := PROG_EMPTY_THRESH; END IF; IF (empty_comb = '0') THEN IF (diff_pntr_rd <= pe_thr_assert_val) THEN prog_empty_reg <= '1' after C_TCQ; ELSE prog_empty_reg <= '0' after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSIF (C_PROG_EMPTY_TYPE = 4) THEN -- If empty input threshold is selected, then subtract 2 for FWFT to -- compensate the FWFT stage, otherwise assign the input value. IF (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0) THEN -- FWFT pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT - "10"; pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE - "10"; ELSE pe_thr_assert_val := PROG_EMPTY_THRESH_ASSERT; pe_thr_negate_val := PROG_EMPTY_THRESH_NEGATE; END IF; IF (empty_comb = '0') THEN IF (diff_pntr_rd <= conv_integer(pe_thr_assert_val)) THEN prog_empty_reg <= '1' after C_TCQ; ELSIF (diff_pntr_rd > conv_integer(pe_thr_negate_val)) THEN prog_empty_reg <= '0' after C_TCQ; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; ELSE prog_empty_reg <= prog_empty_reg after C_TCQ; END IF; END IF; --C_PROG_EMPTY_TYPE END IF; -- RD_CLK END PROCESS proc_pe; ----------------------------------------------------------------------------- -- overflow_i generation: Asynchronous FIFO ----------------------------------------------------------------------------- govflw: IF (C_HAS_OVERFLOW = 1) GENERATE povflw: PROCESS (WR_CLK) BEGIN IF WR_CLK'event AND WR_CLK = '1' THEN overflow_i <= full_comb AND WR_EN after C_TCQ; END IF; END PROCESS povflw; END GENERATE govflw; ----------------------------------------------------------------------------- -- underflow_i generation: Asynchronous FIFO ----------------------------------------------------------------------------- gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE punflw: PROCESS (RD_CLK) BEGIN IF RD_CLK'event AND RD_CLK = '1' THEN underflow_i <= empty_comb and RD_EN after C_TCQ; END IF; END PROCESS punflw; END GENERATE gunflw; ----------------------------------------------------------------------------- -- wr_ack_i generation: Asynchronous FIFO ----------------------------------------------------------------------------- gwack: IF (C_HAS_WR_ACK = 1) GENERATE pwack: PROCESS (WR_CLK,wr_rst_i) BEGIN IF wr_rst_i = '1' THEN wr_ack_i <= '0' after C_TCQ; ELSIF WR_CLK'event AND WR_CLK = '1' THEN wr_ack_i <= '0' after C_TCQ; IF WR_EN = '1' THEN IF full_comb /= '1' THEN wr_ack_i <= '1' after C_TCQ; END IF; END IF; END IF; END PROCESS pwack; END GENERATE gwack; ---------------------------------------------------------------------------- -- valid_i generation: Asynchronous FIFO ---------------------------------------------------------------------------- gvld_i: IF (C_HAS_VALID = 1) GENERATE PROCESS (rd_rst_i , RD_CLK ) BEGIN IF rd_rst_i = '1' THEN valid_i <= '0' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN valid_i <= '0' after C_TCQ; IF RD_EN = '1' THEN IF empty_comb /= '1' THEN valid_i <= '1' after C_TCQ; END IF; END IF; END IF; END PROCESS; ----------------------------------------------------------------- -- Delay valid_d1 --if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1 ----------------------------------------------------------------- gv0_as: IF (C_USE_EMBEDDED_REG=1 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE PROCESS (rd_rst_i , RD_CLK ) BEGIN IF rd_rst_i = '1' THEN valid_d1 <= '0' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN valid_d1 <= valid_i after C_TCQ; END IF; END PROCESS; END GENERATE gv0_as; gv1_as: IF NOT (C_USE_EMBEDDED_REG=1 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE valid_d1 <= valid_i; END GENERATE gv1_as; END GENERATE gvld_i; ----------------------------------------------------------------------------- --Use delayed Valid AND DOUT if we have a LATENCY=2 configurations -- ( if C_MEMORY_TYPE=0 or 1, C_PRELOAD_REGS=0, C_USE_EMBEDDED_REG=1 ) --Otherwise, connect the valid and DOUT values up directly, with no --additional latency. ----------------------------------------------------------------------------- gv0: IF (C_PRELOAD_LATENCY=2 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE gv1: IF (C_HAS_VALID = 1) GENERATE valid_out <= valid_d1; END GENERATE gv1; PROCESS (rd_rst_i , RD_CLK ) BEGIN IF (rd_rst_i = '1') THEN -- BRAM resets synchronously IF (C_USE_DOUT_RST = 1) THEN IF (RD_CLK 'event AND RD_CLK = '1') THEN DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; END IF; IF (C_USE_ECC = 0) THEN SBITERR <= '0' after C_TCQ; DBITERR <= '0' after C_TCQ; END IF; ram_rd_en_d1 <= '0' after C_TCQ; ELSIF (RD_CLK 'event AND RD_CLK = '1') THEN ram_rd_en_d1 <= ram_rd_en after C_TCQ; IF (ram_rd_en_d1 = '1') THEN DOUT <= dout_i after C_TCQ; SBITERR <= sbiterr_i after C_TCQ; DBITERR <= dbiterr_i after C_TCQ; END IF; END IF; END PROCESS; END GENERATE gv0; gv1: IF NOT (C_PRELOAD_LATENCY=2 AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE gv2a: IF (C_HAS_VALID = 1) GENERATE valid_out <= valid_i; END GENERATE gv2a; DOUT <= dout_i; SBITERR <= sbiterr_i after C_TCQ; DBITERR <= dbiterr_i after C_TCQ; END GENERATE gv1; END GENERATE gnll_afifo; ------------------------------------------------------------------------------- -- Low Latency Asynchronous FIFO ------------------------------------------------------------------------------- gll_afifo: IF (C_FIFO_TYPE = 3) GENERATE TYPE mem_array IS ARRAY (0 TO C_WR_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0')); SIGNAL write_allow : std_logic := '0'; SIGNAL read_allow : std_logic := '0'; SIGNAL wr_pntr_ll_afifo : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_ll_afifo : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL rd_pntr_ll_afifo_q : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS=>'0'); SIGNAL ll_afifo_full : std_logic := '0'; SIGNAL ll_afifo_empty : std_logic := '1'; SIGNAL wr_pntr_eq_rd_pntr : std_logic := '0'; SIGNAL wr_pntr_eq_rd_pntr_plus1 : std_logic := '0'; SIGNAL rd_pntr_eq_wr_pntr_plus1 : std_logic := '0'; SIGNAL rd_pntr_eq_wr_pntr_plus2 : std_logic := '0'; BEGIN wr_rst_i <= WR_RST; rd_rst_i <= RD_RST; write_allow <= WR_EN AND (NOT ll_afifo_full); read_allow <= RD_EN AND (NOT ll_afifo_empty); wrptr_proc : PROCESS (WR_CLK,wr_rst_i) BEGIN IF (wr_rst_i = '1') THEN wr_pntr_ll_afifo <= (OTHERS => '0'); ELSIF (WR_CLK'event AND WR_CLK = '1') THEN IF (write_allow = '1') THEN wr_pntr_ll_afifo <= wr_pntr_ll_afifo + "1" AFTER C_TCQ; END IF; END IF; END PROCESS wrptr_proc; ------------------------------------------------------------------------------- -- Fill the Memory ------------------------------------------------------------------------------- wr_mem : PROCESS (WR_CLK) BEGIN IF (WR_CLK'event AND WR_CLK = '1') THEN IF (write_allow = '1') THEN memory(conv_integer(wr_pntr_ll_afifo)) <= DIN AFTER C_TCQ; END IF; END IF; END PROCESS wr_mem; rdptr_proc : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN rd_pntr_ll_afifo_q <= (OTHERS => '0'); ELSIF (RD_CLK'event AND RD_CLK = '1') THEN rd_pntr_ll_afifo_q <= rd_pntr_ll_afifo AFTER C_TCQ; END IF; END PROCESS rdptr_proc; rd_pntr_ll_afifo <= rd_pntr_ll_afifo_q + "1" WHEN (read_allow = '1') ELSE rd_pntr_ll_afifo_q; ------------------------------------------------------------------------------- -- Generate DOUT for DRAM ------------------------------------------------------------------------------- rd_mem : PROCESS (RD_CLK) BEGIN IF (RD_CLK'event AND RD_CLK = '1') THEN DOUT <= memory(conv_integer(rd_pntr_ll_afifo)) AFTER C_TCQ; END IF; END PROCESS rd_mem; ------------------------------------------------------------------------------- -- Generate EMPTY ------------------------------------------------------------------------------- wr_pntr_eq_rd_pntr <= '1' WHEN (wr_pntr_ll_afifo = rd_pntr_ll_afifo_q) ELSE '0'; wr_pntr_eq_rd_pntr_plus1 <= '1' WHEN (wr_pntr_ll_afifo = conv_std_logic_vector( (conv_integer(rd_pntr_ll_afifo_q)+1), C_RD_PNTR_WIDTH)) ELSE '0'; proc_empty : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN ll_afifo_empty <= '1'; ELSIF (RD_CLK'event AND RD_CLK = '1') THEN ll_afifo_empty <= wr_pntr_eq_rd_pntr OR (read_allow AND wr_pntr_eq_rd_pntr_plus1) AFTER C_TCQ; END IF; END PROCESS proc_empty; ------------------------------------------------------------------------------- -- Generate FULL ------------------------------------------------------------------------------- rd_pntr_eq_wr_pntr_plus1 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector( (conv_integer(wr_pntr_ll_afifo)+1), C_WR_PNTR_WIDTH)) ELSE '0'; rd_pntr_eq_wr_pntr_plus2 <= '1' WHEN (rd_pntr_ll_afifo_q = conv_std_logic_vector( (conv_integer(wr_pntr_ll_afifo)+2), C_WR_PNTR_WIDTH)) ELSE '0'; proc_full : PROCESS (WR_CLK, wr_rst_i) BEGIN IF (wr_rst_i = '1') THEN ll_afifo_full <= '1'; ELSIF (WR_CLK'event AND WR_CLK = '1') THEN ll_afifo_full <= rd_pntr_eq_wr_pntr_plus1 OR (write_allow AND rd_pntr_eq_wr_pntr_plus2) AFTER C_TCQ; END IF; END PROCESS proc_full; EMPTY <= ll_afifo_empty; FULL <= ll_afifo_full; END GENERATE gll_afifo; END behavioral; --############################################################################# --############################################################################# -- Common Clock FIFO Behavioral Model --############################################################################# --############################################################################# ------------------------------------------------------------------------------- -- Library Declaration ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ------------------------------------------------------------------------------- -- Common-Clock Entity Declaration - This is NOT the top-level entity ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2_bhv_ss IS GENERIC ( -------------------------------------------------------------------------------- -- Generic Declarations (alphabetical) -------------------------------------------------------------------------------- C_DATA_COUNT_WIDTH : integer := 2; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RST : integer := 0; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); RD_EN : IN std_logic := '0'; WR_EN : IN std_logic := '0'; PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); EMPTY : OUT std_logic := '1'; FULL : OUT std_logic := '0'; ALMOST_EMPTY : OUT std_logic := '1'; ALMOST_FULL : OUT std_logic := '0'; PROG_EMPTY : OUT std_logic := '1'; PROG_FULL : OUT std_logic := '0'; OVERFLOW : OUT std_logic := '0'; WR_ACK : OUT std_logic := '0'; VALID : OUT std_logic := '0'; UNDERFLOW : OUT std_logic := '0'; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_bhv_ss; ------------------------------------------------------------------------------- -- Architecture Heading ------------------------------------------------------------------------------- ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_ss IS ----------------------------------------------------------------------------- -- FUNCTION actual_fifo_depth -- Returns the actual depth of the FIFO (may differ from what the user -- specified) -- -- The FIFO depth is always represented as 2^n (16,32,64,128,256) -- However, the ACTUAL fifo depth may be 2^n+1 or 2^n-1 depending on certain -- options. This function returns the actual depth of the fifo, as seen by -- the user. ------------------------------------------------------------------------------- FUNCTION actual_fifo_depth( C_FIFO_DEPTH : integer; C_PRELOAD_REGS : integer; C_PRELOAD_LATENCY : integer; C_COMMON_CLOCK : integer) RETURN integer IS BEGIN RETURN C_FIFO_DEPTH; END actual_fifo_depth; ----------------------------------------------------------------------------- -- FUNCTION int_2_std_logic -- Returns a single bit (as std_logic) from an integer 1/0 value. ------------------------------------------------------------------------------- FUNCTION int_2_std_logic(value : integer) RETURN std_logic IS BEGIN IF (value=1) THEN RETURN '1'; ELSE RETURN '0'; END IF; END int_2_std_logic; ----------------------------------------------------------------------------- -- FUNCTION hexstr_to_std_logic_vec -- Returns a std_logic_vector for a hexadecimal string ------------------------------------------------------------------------------- FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index*4)+j < size THEN result((index*4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; ----------------------------------------------------------------------------- -- FUNCTION get_lesser -- Returns a minimum value ------------------------------------------------------------------------------- FUNCTION get_lesser(a: INTEGER; b: INTEGER) RETURN INTEGER IS BEGIN IF (a < b) THEN RETURN a; ELSE RETURN b; END IF; END FUNCTION; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; -------------------------------------------------------------------------------- -- Constant Declaration -------------------------------------------------------------------------------- CONSTANT C_FIFO_WR_DEPTH : integer := actual_fifo_depth(C_WR_DEPTH, C_PRELOAD_REGS, C_PRELOAD_LATENCY, 1); CONSTANT C_SMALLER_DATA_WIDTH : integer := get_lesser(C_DIN_WIDTH, C_DOUT_WIDTH); CONSTANT C_FIFO_DEPTH : integer := C_WR_DEPTH; CONSTANT C_DATA_WIDTH : integer := if_then_else((C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0), C_DIN_WIDTH+2, C_DIN_WIDTH); TYPE mem_array IS ARRAY (0 TO C_FIFO_DEPTH-1) OF STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); ------------------------------------------------------------------------------- -- Internal Signals ------------------------------------------------------------------------------- SIGNAL memory : mem_array := (OTHERS => (OTHERS => '0')); SIGNAL wr_pntr : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rd_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL write_allow : std_logic := '0'; SIGNAL read_allow : std_logic := '0'; SIGNAL empty_i : std_logic := '1'; SIGNAL full_i : std_logic := '0'; SIGNAL almost_empty_i : std_logic := '1'; SIGNAL almost_full_i : std_logic := '0'; SIGNAL rst_asreg : std_logic := '0'; SIGNAL rst_asreg_d1 : std_logic := '0'; SIGNAL rst_asreg_d2 : std_logic := '0'; SIGNAL rst_comb : std_logic := '0'; SIGNAL rst_reg : std_logic := '0'; SIGNAL rst_i : std_logic := '0'; SIGNAL srst_i : std_logic := '0'; -- FULL_FLAG_RESET value given for SRST as well. SIGNAL srst_i_d1 : std_logic := '0'; SIGNAL srst_i_d2 : std_logic := '0'; SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wr_ack_i : std_logic := '0'; SIGNAL overflow_i : std_logic := '0'; SIGNAL valid_i : std_logic := '0'; SIGNAL valid_d1 : std_logic := '0'; SIGNAL underflow_i : std_logic := '0'; --The delayed reset is used to deassert prog_full SIGNAL rst_q : std_logic := '0'; SIGNAL prog_full_reg : std_logic := '0'; SIGNAL prog_full_noreg : std_logic := '0'; SIGNAL prog_empty_reg : std_logic := '1'; SIGNAL prog_empty_noreg: std_logic := '1'; SIGNAL dout_i : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL sbiterr_i : std_logic := '0'; SIGNAL dbiterr_i : std_logic := '0'; SIGNAL ram_rd_en_d1 : std_logic := '0'; SIGNAL mem_pntr : integer := 0; SIGNAL ram_wr_en_i : std_logic := '0'; SIGNAL ram_rd_en_i : std_logic := '0'; SIGNAL comp1 : std_logic := '0'; SIGNAL comp0 : std_logic := '0'; SIGNAL going_full : std_logic := '0'; SIGNAL leaving_full : std_logic := '0'; SIGNAL ram_full_comb : std_logic := '0'; SIGNAL ecomp1 : std_logic := '0'; SIGNAL ecomp0 : std_logic := '0'; SIGNAL going_empty : std_logic := '0'; SIGNAL leaving_empty : std_logic := '0'; SIGNAL ram_empty_comb : std_logic := '0'; ------------------------------------------------------------------------------- -- architecture begins here ------------------------------------------------------------------------------- BEGIN rst_i <= RST; --SRST gsrst : IF (C_HAS_SRST=1) GENERATE srst_i <= SRST; END GENERATE gsrst; --No SRST nosrst : IF (C_HAS_SRST=0) GENERATE srst_i <= '0'; END GENERATE nosrst; gdc : IF (C_HAS_DATA_COUNT = 1) GENERATE SIGNAL diff_count : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN diff_count <= wr_pntr - rd_pntr; gdcb : IF (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) GENERATE DATA_COUNT(C_RD_PNTR_WIDTH-1 DOWNTO 0) <= diff_count; DATA_COUNT(C_DATA_COUNT_WIDTH-1) <= '0' ; END GENERATE; gdcs : IF (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) GENERATE DATA_COUNT <= diff_count(C_RD_PNTR_WIDTH-1 DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH); END GENERATE; END GENERATE gdc; gndc : IF (C_HAS_DATA_COUNT = 0) GENERATE DATA_COUNT <= (OTHERS => '0'); END GENERATE gndc; ------------------------------------------------------------------------------- --Calculate WR_ACK based on C_WR_ACK_LOW parameters ------------------------------------------------------------------------------- gwalow : IF (C_WR_ACK_LOW = 0) GENERATE WR_ACK <= wr_ack_i; END GENERATE gwalow; gwahgh : IF (C_WR_ACK_LOW = 1) GENERATE WR_ACK <= NOT wr_ack_i; END GENERATE gwahgh; ------------------------------------------------------------------------------- --Calculate OVERFLOW based on C_OVERFLOW_LOW parameters ------------------------------------------------------------------------------- govlow : IF (C_OVERFLOW_LOW = 0) GENERATE OVERFLOW <= overflow_i; END GENERATE govlow; govhgh : IF (C_OVERFLOW_LOW = 1) GENERATE OVERFLOW <= NOT overflow_i; END GENERATE govhgh; ------------------------------------------------------------------------------- --Calculate VALID based on C_PRELOAD_LATENCY and C_VALID_LOW settings ------------------------------------------------------------------------------- gvlat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE gnvl : IF (C_VALID_LOW = 0) GENERATE VALID <= valid_d1; END GENERATE gnvl; gnvh : IF (C_VALID_LOW = 1) GENERATE VALID <= NOT valid_d1; END GENERATE gnvh; END GENERATE gvlat1; ------------------------------------------------------------------------------- -- Calculate UNDERFLOW based on C_PRELOAD_LATENCY and C_UNDERFLOW_LOW settings ------------------------------------------------------------------------------- guflat1 : IF (C_PRELOAD_LATENCY = 1 OR C_PRELOAD_LATENCY=2) GENERATE gnul : IF (C_UNDERFLOW_LOW = 0) GENERATE UNDERFLOW <= underflow_i; END GENERATE gnul; gnuh : IF (C_UNDERFLOW_LOW = 1) GENERATE UNDERFLOW <= NOT underflow_i; END GENERATE gnuh; END GENERATE guflat1; FULL <= full_i; ALMOST_FULL <= almost_full_i; EMPTY <= empty_i; ALMOST_EMPTY <= almost_empty_i; write_allow <= WR_EN AND (NOT full_i); read_allow <= RD_EN AND (NOT empty_i); wrptr_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN wr_pntr <= (OTHERS => '0'); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN wr_pntr <= (OTHERS => '0') AFTER C_TCQ; ELSIF (write_allow = '1') THEN wr_pntr <= wr_pntr + "1" AFTER C_TCQ; END IF; END IF; END PROCESS wrptr_proc; gecc_mem: IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE wr_mem : PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF (write_allow = '1') THEN memory(conv_integer(wr_pntr)) <= INJECTDBITERR & INJECTSBITERR & DIN AFTER C_TCQ; END IF; END IF; END PROCESS wr_mem; END GENERATE gecc_mem; gnecc_mem: IF NOT (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) GENERATE wr_mem : PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN IF (write_allow = '1') THEN memory(conv_integer(wr_pntr)) <= DIN AFTER C_TCQ; END IF; END IF; END PROCESS wr_mem; END GENERATE gnecc_mem; rdptr_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN rd_pntr <= (OTHERS => '0'); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN rd_pntr <= (OTHERS => '0') AFTER C_TCQ; ELSIF (read_allow = '1') THEN rd_pntr <= rd_pntr + "1" AFTER C_TCQ; END IF; END IF; END PROCESS rdptr_proc; ------------------------------------------------------------------------------- -- Generate DOUT for common clock low latency FIFO ------------------------------------------------------------------------------- gll_dout: IF(C_FIFO_TYPE = 2) GENERATE SIGNAL dout_q : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN dout_i <= memory(conv_integer(rd_pntr)) when (read_allow = '1') else dout_q; dout_reg : PROCESS (CLK) BEGIN IF (CLK'event AND CLK = '1') THEN dout_q <= dout_i AFTER C_TCQ; END IF; END PROCESS dout_reg; END GENERATE gll_dout; gnll_dout: IF (C_FIFO_TYPE < 2) GENERATE ------------------------------------------------------------------------------- -- Generate DOUT for BRAM ------------------------------------------------------------------------------- gbm_dout: IF (C_MEMORY_TYPE < 2) GENERATE BEGIN rd_mem : PROCESS (CLK) VARIABLE dout_tmp : STD_LOGIC_VECTOR(C_DATA_WIDTH - 1 DOWNTO 0) := (OTHERS => '0'); BEGIN IF (CLK'event AND CLK = '1') THEN IF (RST_FULL_FF = '1' OR srst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ; END IF; ELSIF (read_allow = '1') THEN dout_tmp := memory(conv_integer(rd_pntr)); IF (C_USE_ECC = 1 AND C_ERROR_INJECTION_TYPE /= 0) THEN IF (dout_tmp(dout_tmp'high) = '1') THEN IF (C_DOUT_WIDTH > 2) THEN dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 2) & NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ; ELSIF (C_DOUT_WIDTH = 2) THEN dout_i <= NOT dout_tmp(1 DOWNTO 0) AFTER C_TCQ; ELSE dout_i(0) <= dout_tmp(0) AFTER C_TCQ; END IF; dbiterr_i <= dout_tmp(dout_tmp'high) AFTER C_TCQ; sbiterr_i <= '0' AFTER C_TCQ; ELSE dout_i <= dout_tmp(C_DOUT_WIDTH-1 DOWNTO 0) AFTER C_TCQ; sbiterr_i <= dout_tmp(dout_tmp'high-1) AFTER C_TCQ; dbiterr_i <= '0' AFTER C_TCQ; END IF; ELSE dout_i <= dout_tmp AFTER C_TCQ; END IF; END IF; END IF; END PROCESS rd_mem; END GENERATE gbm_dout; ------------------------------------------------------------------------------- -- Generate DOUT for DRAM ------------------------------------------------------------------------------- gdm_dout: IF (C_MEMORY_TYPE = 2 OR C_MEMORY_TYPE = 3) GENERATE rd_mem : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN IF (C_USE_DOUT_RST = 1) THEN dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); END IF; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN dout_i <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) AFTER C_TCQ; END IF; ELSIF (read_allow = '1') THEN dout_i <= memory(conv_integer(rd_pntr)) AFTER C_TCQ; END IF; END IF; END PROCESS rd_mem; END GENERATE gdm_dout; END GENERATE gnll_dout; ------------------------------------------------------------------------------- -- Generate FULL flag ------------------------------------------------------------------------------- comp1 <= '1' WHEN (rd_pntr = (wr_pntr + "1")) ELSE '0'; comp0 <= '1' WHEN (rd_pntr = wr_pntr) ELSE '0'; going_full <= (comp1 AND write_allow AND NOT read_allow); leaving_full <= (comp0 AND read_allow) OR RST_FULL_GEN; ram_full_comb <= going_full OR (NOT leaving_full AND full_i); full_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSE full_i <= ram_full_comb AFTER C_TCQ; END IF; END IF; END PROCESS full_proc; ------------------------------------------------------------------------------- -- Generate ALMOST_FULL flag ------------------------------------------------------------------------------- gaf_ss: IF (C_HAS_ALMOST_FULL = 1 OR C_PROG_FULL_TYPE > 2 OR C_PROG_EMPTY_TYPE > 2) GENERATE SIGNAL fcomp2 : std_logic := '0'; SIGNAL going_afull : std_logic := '0'; SIGNAL leaving_afull : std_logic := '0'; SIGNAL ram_afull_comb : std_logic := '0'; BEGIN fcomp2 <= '1' WHEN (rd_pntr = (wr_pntr + "10")) ELSE '0'; going_afull <= (fcomp2 AND write_allow AND NOT read_allow); leaving_afull <= (comp1 AND read_allow AND NOT write_allow) OR RST_FULL_GEN; ram_afull_comb <= going_afull OR (NOT leaving_afull AND almost_full_i); af_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN almost_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSE almost_full_i <= ram_afull_comb AFTER C_TCQ; END IF; END IF; END PROCESS af_proc; END GENERATE gaf_ss; ------------------------------------------------------------------------------- -- Generate EMPTY flag ------------------------------------------------------------------------------- ecomp1 <= '1' WHEN (wr_pntr = (rd_pntr + "1")) ELSE '0'; ecomp0 <= '1' WHEN (wr_pntr = rd_pntr) ELSE '0'; going_empty <= (ecomp1 AND NOT write_allow AND read_allow); leaving_empty <= (ecomp0 AND write_allow); ram_empty_comb <= going_empty OR (NOT leaving_empty AND empty_i); empty_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN empty_i <= '1' AFTER C_TCQ; ELSE empty_i <= ram_empty_comb AFTER C_TCQ; END IF; END IF; END PROCESS empty_proc; ------------------------------------------------------------------------------- -- Generate ALMOST_EMPTY flag ------------------------------------------------------------------------------- gae_ss: IF (C_HAS_ALMOST_EMPTY = 1) GENERATE SIGNAL ecomp2 : std_logic := '0'; SIGNAL going_aempty : std_logic := '0'; SIGNAL leaving_aempty : std_logic := '0'; SIGNAL ram_aempty_comb : std_logic := '1'; BEGIN ecomp2 <= '1' WHEN (wr_pntr = (rd_pntr + "10")) ELSE '0'; going_aempty <= (ecomp2 AND NOT write_allow AND read_allow); leaving_aempty <= (ecomp1 AND write_allow AND NOT read_allow); ram_aempty_comb <= going_aempty OR (NOT leaving_aempty AND almost_empty_i); ae_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN almost_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN almost_empty_i <= '1' AFTER C_TCQ; ELSE almost_empty_i <= ram_aempty_comb AFTER C_TCQ; END IF; END IF; END PROCESS ae_proc; END GENERATE gae_ss; ------------------------------------------------------------------------------- -- Generate PROG_FULL and PROG_EMPTY flags ------------------------------------------------------------------------------- gpf_pe: IF (C_PROG_FULL_TYPE /= 0 OR C_PROG_EMPTY_TYPE /= 0) GENERATE SIGNAL diff_pntr : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL diff_pntr_pe : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL write_allow_q : std_logic := '0'; SIGNAL read_allow_q : std_logic := '0'; SIGNAL write_only : std_logic := '0'; SIGNAL write_only_q : std_logic := '0'; SIGNAL read_only : std_logic := '0'; SIGNAL read_only_q : std_logic := '0'; SIGNAL prog_full_i : std_logic := int_2_std_logic(C_FULL_FLAGS_RST_VAL); SIGNAL prog_empty_i : std_logic := '1'; CONSTANT C_PF_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_FULL_THRESH_ASSERT_VAL - 2, -- FWFT C_PROG_FULL_THRESH_ASSERT_VAL); -- STD CONSTANT C_PF_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_FULL_THRESH_NEGATE_VAL - 2, -- FWFT C_PROG_FULL_THRESH_NEGATE_VAL); -- STD CONSTANT C_PE_ASSERT_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_EMPTY_THRESH_ASSERT_VAL - 2, C_PROG_EMPTY_THRESH_ASSERT_VAL); CONSTANT C_PE_NEGATE_VAL : integer := if_then_else(C_PRELOAD_LATENCY = 0, C_PROG_EMPTY_THRESH_NEGATE_VAL - 2, C_PROG_EMPTY_THRESH_NEGATE_VAL); BEGIN write_only <= write_allow AND NOT read_allow; write_only_q <= write_allow_q AND NOT read_allow_q; read_only <= read_allow AND NOT write_allow; read_only_q <= read_allow_q AND NOT write_allow_q; wr_rd_q_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN write_allow_q <= '0'; read_allow_q <= '0'; diff_pntr <= (OTHERS => '0'); diff_pntr_pe <= (OTHERS => '0'); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1' OR srst_i_d1 = '1' OR srst_i_d2 = '1') THEN write_allow_q <= '0' AFTER C_TCQ; read_allow_q <= '0' AFTER C_TCQ; diff_pntr <= (OTHERS => '0') AFTER C_TCQ; diff_pntr_pe <= (OTHERS => '0') AFTER C_TCQ; ELSE write_allow_q <= write_allow AFTER C_TCQ; read_allow_q <= read_allow AFTER C_TCQ; -- Add 1 to the difference pointer value when only write happens. IF (write_only = '1') THEN diff_pntr <= wr_pntr - rd_pntr + "1" AFTER C_TCQ; ELSE diff_pntr <= wr_pntr - rd_pntr AFTER C_TCQ; END IF; -- Add 1 to the difference pointer value when write or both write & read or no write & read happen. IF (read_only = '1') THEN diff_pntr_pe <= wr_pntr - rd_pntr - "1" AFTER C_TCQ; ELSE diff_pntr_pe <= wr_pntr - rd_pntr AFTER C_TCQ; END IF; END IF; END IF; END PROCESS wr_rd_q_proc; ------------------------------------------------------------------------------- -- Generate PROG_FULL flag ------------------------------------------------------------------------------- gpf: IF (C_PROG_FULL_TYPE /= 0) GENERATE ------------------------------------------------------------------------------- -- Generate PROG_FULL for single programmable threshold constant ------------------------------------------------------------------------------- gpf1: IF (C_PROG_FULL_TYPE = 1) GENERATE pf1_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND read_only_q = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf1_proc; END GENERATE gpf1; ------------------------------------------------------------------------------- -- Generate PROG_FULL for multiple programmable threshold constants ------------------------------------------------------------------------------- gpf2: IF (C_PROG_FULL_TYPE = 2) GENERATE pf2_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_ASSERT_VAL) AND write_only_q = '1') THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr) = C_PF_NEGATE_VAL) AND read_only_q = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf2_proc; END GENERATE gpf2; ------------------------------------------------------------------------------- -- Generate PROG_FULL for single programmable threshold input port ------------------------------------------------------------------------------- gpf3: IF (C_PROG_FULL_TYPE = 3) GENERATE SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pf_assert_val <= PROG_FULL_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH; pf3_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr) > pf_assert_val) THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF (conv_integer(diff_pntr) = pf_assert_val) THEN IF (read_only_q = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= '1' AFTER C_TCQ; END IF; ELSE prog_full_i <= '0' AFTER C_TCQ; END IF; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf3_proc; END GENERATE gpf3; ------------------------------------------------------------------------------- -- Generate PROG_FULL for multiple programmable threshold input ports ------------------------------------------------------------------------------- gpf4: IF (C_PROG_FULL_TYPE = 4) GENERATE SIGNAL pf_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL pf_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pf_assert_val <= PROG_FULL_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_ASSERT; pf_negate_val <= PROG_FULL_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_FULL_THRESH_NEGATE; pf4_proc : PROCESS (CLK, RST_FULL_FF) BEGIN IF (RST_FULL_FF = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL); ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_full_i <= int_2_std_logic(C_FULL_FLAGS_RST_VAL) AFTER C_TCQ; ELSIF (RST_FULL_GEN = '1') THEN prog_full_i <= '0' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr) >= pf_assert_val) THEN prog_full_i <= '1' AFTER C_TCQ; ELSIF (((conv_integer(diff_pntr) = pf_negate_val) AND read_only_q = '1') OR (conv_integer(diff_pntr) < pf_negate_val)) THEN prog_full_i <= '0' AFTER C_TCQ; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; ELSE prog_full_i <= prog_full_i AFTER C_TCQ; END IF; END IF; END PROCESS pf4_proc; END GENERATE gpf4; PROG_FULL <= prog_full_i; END GENERATE gpf; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY flag ------------------------------------------------------------------------------- gpe: IF (C_PROG_EMPTY_TYPE /= 0) GENERATE ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for single programmable threshold constant ------------------------------------------------------------------------------- gpe1: IF (C_PROG_EMPTY_TYPE = 1) GENERATE pe1_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND write_only_q = '1') THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe1_proc; END GENERATE gpe1; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for multiple programmable threshold constants ------------------------------------------------------------------------------- gpe2: IF (C_PROG_EMPTY_TYPE = 2) GENERATE pe2_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_ASSERT_VAL) AND read_only_q = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF ((conv_integer(diff_pntr_pe) = C_PE_NEGATE_VAL) AND write_only_q = '1') THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe2_proc; END GENERATE gpe2; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for single programmable threshold input port ------------------------------------------------------------------------------- gpe3: IF (C_PROG_EMPTY_TYPE = 3) GENERATE SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pe_assert_val <= PROG_EMPTY_THRESH - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH; pe3_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr_pe) < pe_assert_val) THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (conv_integer(diff_pntr_pe) = pe_assert_val) THEN IF (write_only_q = '1') THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= '1' AFTER C_TCQ; END IF; ELSE prog_empty_i <= '0' AFTER C_TCQ; END IF; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe3_proc; END GENERATE gpe3; ------------------------------------------------------------------------------- -- Generate PROG_EMPTY for multiple programmable threshold input ports ------------------------------------------------------------------------------- gpe4: IF (C_PROG_EMPTY_TYPE = 4) GENERATE SIGNAL pe_assert_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL pe_negate_val : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); BEGIN pe_assert_val <= PROG_EMPTY_THRESH_ASSERT - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_ASSERT; pe_negate_val <= PROG_EMPTY_THRESH_NEGATE - "10" WHEN (C_PRELOAD_LATENCY = 0) ELSE PROG_EMPTY_THRESH_NEGATE; pe4_proc : PROCESS (CLK, rst_i) BEGIN IF (rst_i = '1') THEN prog_empty_i <= '1'; ELSIF (CLK'event AND CLK = '1') THEN IF (srst_i = '1') THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (almost_full_i = '0') THEN IF (conv_integer(diff_pntr_pe) <= pe_assert_val) THEN prog_empty_i <= '1' AFTER C_TCQ; ELSIF (((conv_integer(diff_pntr_pe) = pe_negate_val) AND write_only_q = '1') OR (conv_integer(diff_pntr_pe) > pe_negate_val)) THEN prog_empty_i <= '0' AFTER C_TCQ; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; ELSE prog_empty_i <= prog_empty_i AFTER C_TCQ; END IF; END IF; END PROCESS pe4_proc; END GENERATE gpe4; PROG_EMPTY <= prog_empty_i; END GENERATE gpe; END GENERATE gpf_pe; ------------------------------------------------------------------------------- -- overflow_i generation: Synchronous FIFO ------------------------------------------------------------------------------- govflw: IF (C_HAS_OVERFLOW = 1) GENERATE povflw: PROCESS (CLK) BEGIN IF CLK'event AND CLK = '1' THEN overflow_i <= full_i AND WR_EN after C_TCQ; END IF; END PROCESS povflw; END GENERATE govflw; ------------------------------------------------------------------------------- -- underflow_i generation: Synchronous FIFO ------------------------------------------------------------------------------- gunflw: IF (C_HAS_UNDERFLOW = 1) GENERATE punflw: PROCESS (CLK) BEGIN IF CLK'event AND CLK = '1' THEN underflow_i <= empty_i and RD_EN after C_TCQ; END IF; END PROCESS punflw; END GENERATE gunflw; ------------------------------------------------------------------------------- -- wr_ack_i generation: Synchronous FIFO ------------------------------------------------------------------------------- gwack: IF (C_HAS_WR_ACK = 1) GENERATE pwack: PROCESS (CLK,rst_i) BEGIN IF rst_i = '1' THEN wr_ack_i <= '0' after C_TCQ; ELSIF CLK'event AND CLK = '1' THEN wr_ack_i <= '0' after C_TCQ; IF srst_i = '1' THEN wr_ack_i <= '0' after C_TCQ; ELSIF WR_EN = '1' THEN IF full_i /= '1' THEN wr_ack_i <= '1' after C_TCQ; END IF; END IF; END IF; END PROCESS pwack; END GENERATE gwack; ----------------------------------------------------------------------------- -- valid_i generation: Synchronous FIFO ----------------------------------------------------------------------------- gvld_i: IF (C_HAS_VALID = 1) GENERATE PROCESS (rst_i , CLK ) BEGIN IF rst_i = '1' THEN valid_i <= '0' after C_TCQ; ELSIF CLK'event AND CLK = '1' THEN IF srst_i = '1' THEN valid_i <= '0' after C_TCQ; ELSE --srst_i=0 -- Setup default value for underflow and valid valid_i <= '0' after C_TCQ; IF RD_EN = '1' THEN IF empty_i /= '1' THEN valid_i <= '1' after C_TCQ; END IF; END IF; END IF; END IF; END PROCESS; END GENERATE gvld_i; ----------------------------------------------------------------------------- --Delay Valid AND DOUT --if C_MEMORY_TYPE=0 or 1, C_USE_EMBEDDED_REG=1, STD ----------------------------------------------------------------------------- gnll_fifo1: IF (C_FIFO_TYPE < 2) GENERATE gv0: IF (C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0)) AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)) GENERATE PROCESS (rst_i , CLK ) BEGIN IF (rst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN IF (CLK'event AND CLK = '1') THEN DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; END IF; IF (C_USE_ECC = 0) THEN SBITERR <= '0' after C_TCQ; DBITERR <= '0' after C_TCQ; END IF; ram_rd_en_d1 <= '0' after C_TCQ; valid_d1 <= '0' after C_TCQ; ELSIF (CLK 'event AND CLK = '1') THEN ram_rd_en_d1 <= RD_EN AND (NOT empty_i) after C_TCQ; valid_d1 <= valid_i after C_TCQ; IF (srst_i = '1') THEN IF (C_USE_DOUT_RST = 1) THEN DOUT <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; ram_rd_en_d1 <= '0' after C_TCQ; valid_d1 <= '0' after C_TCQ; ELSIF (ram_rd_en_d1 = '1') THEN DOUT <= dout_i after C_TCQ; SBITERR <= sbiterr_i after C_TCQ; DBITERR <= dbiterr_i after C_TCQ; END IF; END IF; END PROCESS; END GENERATE gv0; END GENERATE gnll_fifo1; gv1: IF (C_FIFO_TYPE = 2 OR (NOT(C_USE_EMBEDDED_REG=1 AND (NOT (C_PRELOAD_REGS = 1 AND C_PRELOAD_LATENCY = 0)) AND (C_MEMORY_TYPE=0 OR C_MEMORY_TYPE=1)))) GENERATE valid_d1 <= valid_i; DOUT <= dout_i; SBITERR <= sbiterr_i; DBITERR <= dbiterr_i; END GENERATE gv1; END behavioral; --############################################################################# --############################################################################# -- Preload Latency 0 (First-Word Fall-Through) Module --############################################################################# --############################################################################# LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY fifo_generator_v8_2_bhv_preload0 IS GENERIC ( C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_HAS_RST : integer := 0; C_HAS_SRST : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USERVALID_LOW : integer := 0; C_USERUNDERFLOW_LOW : integer := 0; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT ( RD_CLK : IN std_logic; RD_RST : IN std_logic; SRST : IN std_logic; RD_EN : IN std_logic; FIFOEMPTY : IN std_logic; FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FIFOSBITERR : IN std_logic; FIFODBITERR : IN std_logic; USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); USERVALID : OUT std_logic; USERUNDERFLOW : OUT std_logic; USEREMPTY : OUT std_logic; USERALMOSTEMPTY : OUT std_logic; RAMVALID : OUT std_logic; FIFORDEN : OUT std_logic; USERSBITERR : OUT std_logic := '0'; USERDBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_bhv_preload0; ARCHITECTURE behavioral OF fifo_generator_v8_2_bhv_preload0 IS ----------------------------------------------------------------------------- -- FUNCTION hexstr_to_std_logic_vec -- Returns a std_logic_vector for a hexadecimal string ------------------------------------------------------------------------------- FUNCTION hexstr_to_std_logic_vec( arg1 : string; size : integer ) RETURN std_logic_vector IS VARIABLE result : std_logic_vector(size-1 DOWNTO 0) := (OTHERS => '0'); VARIABLE bin : std_logic_vector(3 DOWNTO 0); VARIABLE index : integer := 0; BEGIN FOR i IN arg1'reverse_range LOOP CASE arg1(i) IS WHEN '0' => bin := (OTHERS => '0'); WHEN '1' => bin := (0 => '1', OTHERS => '0'); WHEN '2' => bin := (1 => '1', OTHERS => '0'); WHEN '3' => bin := (0 => '1', 1 => '1', OTHERS => '0'); WHEN '4' => bin := (2 => '1', OTHERS => '0'); WHEN '5' => bin := (0 => '1', 2 => '1', OTHERS => '0'); WHEN '6' => bin := (1 => '1', 2 => '1', OTHERS => '0'); WHEN '7' => bin := (3 => '0', OTHERS => '1'); WHEN '8' => bin := (3 => '1', OTHERS => '0'); WHEN '9' => bin := (0 => '1', 3 => '1', OTHERS => '0'); WHEN 'A' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'a' => bin := (0 => '0', 2 => '0', OTHERS => '1'); WHEN 'B' => bin := (2 => '0', OTHERS => '1'); WHEN 'b' => bin := (2 => '0', OTHERS => '1'); WHEN 'C' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'c' => bin := (0 => '0', 1 => '0', OTHERS => '1'); WHEN 'D' => bin := (1 => '0', OTHERS => '1'); WHEN 'd' => bin := (1 => '0', OTHERS => '1'); WHEN 'E' => bin := (0 => '0', OTHERS => '1'); WHEN 'e' => bin := (0 => '0', OTHERS => '1'); WHEN 'F' => bin := (OTHERS => '1'); WHEN 'f' => bin := (OTHERS => '1'); WHEN OTHERS => FOR j IN 0 TO 3 LOOP bin(j) := 'X'; END LOOP; END CASE; FOR j IN 0 TO 3 LOOP IF (index*4)+j < size THEN result((index*4)+j) := bin(j); END IF; END LOOP; index := index + 1; END LOOP; RETURN result; END hexstr_to_std_logic_vec; SIGNAL USERDATA_int : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0) := hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH); SIGNAL preloadstage1 : std_logic := '0'; SIGNAL preloadstage2 : std_logic := '0'; SIGNAL ram_valid_i : std_logic := '0'; SIGNAL read_data_valid_i : std_logic := '0'; SIGNAL ram_regout_en : std_logic := '0'; SIGNAL ram_rd_en : std_logic := '0'; SIGNAL empty_i : std_logic := '1'; SIGNAL empty_q : std_logic := '1'; SIGNAL rd_en_q : std_logic := '0'; SIGNAL almost_empty_i : std_logic := '1'; SIGNAL almost_empty_q : std_logic := '1'; SIGNAL rd_rst_i : std_logic := '0'; SIGNAL srst_i : std_logic := '0'; BEGIN -- behavioral grst: IF (C_HAS_RST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE rd_rst_i <= RD_RST; end generate grst; ngrst: IF (C_HAS_RST = 0 AND C_ENABLE_RST_SYNC = 1) GENERATE rd_rst_i <= '0'; END GENERATE ngrst; --SRST gsrst : IF (C_HAS_SRST=1) GENERATE srst_i <= SRST; END GENERATE gsrst; --SRST ngsrst : IF (C_HAS_SRST=0) GENERATE srst_i <= '0'; END GENERATE ngsrst; gnll_fifo: IF (C_FIFO_TYPE /= 2) GENERATE -------------------------------------------------------------------------------- -- preloadstage2 indicates that stage2 needs to be updated. This is true -- whenever read_data_valid is false, and RAM_valid is true. -------------------------------------------------------------------------------- preloadstage2 <= ram_valid_i AND (NOT read_data_valid_i OR RD_EN); -------------------------------------------------------------------------------- -- preloadstage1 indicates that stage1 needs to be updated. This is true -- whenever the RAM has data (RAM_EMPTY is false), and either RAM_Valid is -- false (indicating that Stage1 needs updating), or preloadstage2 is active -- (indicating that Stage2 is going to update, so Stage1, therefore, must -- also be updated to keep it valid. -------------------------------------------------------------------------------- preloadstage1 <= (((NOT ram_valid_i) OR preloadstage2) AND (NOT FIFOEMPTY)); -------------------------------------------------------------------------------- -- Calculate RAM_REGOUT_EN -- The output registers are controlled by the ram_regout_en signal. -- These registers should be updated either when the output in Stage2 is -- invalid (preloadstage2), OR when the user is reading, in which case the -- Stage2 value will go invalid unless it is replenished. -------------------------------------------------------------------------------- ram_regout_en <= preloadstage2; -------------------------------------------------------------------------------- -- Calculate RAM_RD_EN -- RAM_RD_EN will be asserted whenever the RAM needs to be read in order to -- update the value in Stage1. -- One case when this happens is when preloadstage1=true, which indicates -- that the data in Stage1 or Stage2 is invalid, and needs to automatically -- be updated. -- The other case is when the user is reading from the FIFO, which guarantees -- that Stage1 or Stage2 will be invalid on the next clock cycle, unless it is -- replinished by data from the memory. So, as long as the RAM has data in it, -- a read of the RAM should occur. -------------------------------------------------------------------------------- ram_rd_en <= (RD_EN AND NOT FIFOEMPTY) OR preloadstage1; END GENERATE gnll_fifo; gll_fifo: IF (C_FIFO_TYPE = 2) GENERATE SIGNAL empty_d1 : STD_LOGIC := '1'; SIGNAL fe_of_empty : STD_LOGIC := '0'; SIGNAL curr_state : STD_LOGIC := '0'; SIGNAL next_state : STD_LOGIC := '0'; SIGNAL leaving_empty_fwft : STD_LOGIC := '0'; SIGNAL going_empty_fwft : STD_LOGIC := '0'; BEGIN fsm_proc: PROCESS (curr_state, FIFOEMPTY, RD_EN) BEGIN CASE curr_state IS WHEN '0' => IF (FIFOEMPTY = '0') THEN next_state <= '1'; ELSE next_state <= '0'; END IF; WHEN '1' => IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN next_state <= '0'; ELSE next_state <= '1'; END IF; WHEN OTHERS => next_state <= '0'; END CASE; END PROCESS fsm_proc; empty_reg: PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i = '1') THEN empty_d1 <= '1'; empty_i <= '1'; ram_valid_i <= '0'; curr_state <= '0'; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (srst_i = '1') THEN empty_d1 <= '1' AFTER C_TCQ; empty_i <= '1' AFTER C_TCQ; ram_valid_i <= '0' AFTER C_TCQ; curr_state <= '0' AFTER C_TCQ; ELSE empty_d1 <= FIFOEMPTY AFTER C_TCQ; curr_state <= next_state AFTER C_TCQ; empty_i <= going_empty_fwft OR (NOT leaving_empty_fwft AND empty_i) AFTER C_TCQ; ram_valid_i <= next_state AFTER C_TCQ; END IF; END IF; END PROCESS empty_reg; fe_of_empty <= empty_d1 AND (NOT FIFOEMPTY); prege: PROCESS (curr_state, FIFOEMPTY, RD_EN) BEGIN CASE curr_state IS WHEN '0' => IF (FIFOEMPTY = '0') THEN ram_regout_en <= '1'; ram_rd_en <= '1'; ELSE ram_regout_en <= '0'; ram_rd_en <= '0'; END IF; WHEN '1' => IF (FIFOEMPTY = '0' AND RD_EN = '1') THEN ram_regout_en <= '1'; ram_rd_en <= '1'; ELSE ram_regout_en <= '0'; ram_rd_en <= '0'; END IF; WHEN OTHERS => ram_regout_en <= '0'; ram_rd_en <= '0'; END CASE; END PROCESS prege; ple: PROCESS (curr_state, fe_of_empty) -- Leaving Empty BEGIN CASE curr_state IS WHEN '0' => leaving_empty_fwft <= fe_of_empty; WHEN '1' => leaving_empty_fwft <= '1'; WHEN OTHERS => leaving_empty_fwft <= '0'; END CASE; END PROCESS ple; pge: PROCESS (curr_state, FIFOEMPTY, RD_EN) -- Going Empty BEGIN CASE curr_state IS WHEN '1' => IF (FIFOEMPTY = '1' AND RD_EN = '1') THEN going_empty_fwft <= '1'; ELSE going_empty_fwft <= '0'; END IF; WHEN OTHERS => going_empty_fwft <= '0'; END CASE; END PROCESS pge; END GENERATE gll_fifo; -------------------------------------------------------------------------------- -- Calculate ram_valid -- ram_valid indicates that the data in Stage1 is valid. -- -- If the RAM is being read from on this clock cycle (ram_rd_en=1), then -- ram_valid is certainly going to be true. -- If the RAM is not being read from, but the output registers are being -- updated to fill Stage2 (ram_regout_en=1), then Stage1 will be emptying, -- therefore causing ram_valid to be false. -- Otherwise, ram_valid will remain unchanged. -------------------------------------------------------------------------------- gvalid: IF (C_FIFO_TYPE < 2) GENERATE regout_valid: PROCESS (RD_CLK, rd_rst_i) BEGIN -- PROCESS regout_valid IF rd_rst_i = '1' THEN -- asynchronous reset (active high) ram_valid_i <= '0' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge IF srst_i = '1' THEN -- synchronous reset (active high) ram_valid_i <= '0' after C_TCQ; ELSE IF ram_rd_en = '1' THEN ram_valid_i <= '1' after C_TCQ; ELSE IF ram_regout_en = '1' THEN ram_valid_i <= '0' after C_TCQ; ELSE ram_valid_i <= ram_valid_i after C_TCQ; END IF; END IF; END IF; END IF; END PROCESS regout_valid; END GENERATE gvalid; -------------------------------------------------------------------------------- -- Calculate READ_DATA_VALID -- READ_DATA_VALID indicates whether the value in Stage2 is valid or not. -- Stage2 has valid data whenever Stage1 had valid data and ram_regout_en_i=1, -- such that the data in Stage1 is propogated into Stage2. -------------------------------------------------------------------------------- regout_dvalid : PROCESS (RD_CLK, rd_rst_i) BEGIN IF (rd_rst_i='1') THEN read_data_valid_i <= '0' after C_TCQ; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (srst_i='1') THEN read_data_valid_i <= '0' after C_TCQ; ELSE read_data_valid_i <= ram_valid_i OR (read_data_valid_i AND NOT RD_EN) after C_TCQ; END IF; END IF; --RD_CLK END PROCESS regout_dvalid; ------------------------------------------------------------------------------- -- Calculate EMPTY -- Defined as the inverse of READ_DATA_VALID -- -- Description: -- -- If read_data_valid_i indicates that the output is not valid, -- and there is no valid data on the output of the ram to preload it -- with, then we will report empty. -- -- If there is no valid data on the output of the ram and we are -- reading, then the FIFO will go empty. -- ------------------------------------------------------------------------------- gempty: IF (C_FIFO_TYPE < 2) GENERATE regout_empty : PROCESS (RD_CLK, rd_rst_i) --This is equivalent to (NOT read_data_valid_i) BEGIN IF (rd_rst_i='1') THEN empty_i <= '1' after C_TCQ; ELSIF (RD_CLK'event AND RD_CLK='1') THEN IF (srst_i='1') THEN empty_i <= '1' after C_TCQ; ELSE empty_i <= (NOT ram_valid_i AND NOT read_data_valid_i) OR (NOT ram_valid_i AND RD_EN) after C_TCQ; END IF; END IF; --RD_CLK END PROCESS regout_empty; END GENERATE gempty; regout_empty_q: PROCESS (RD_CLK) BEGIN -- PROCESS regout_rd_en IF RD_CLK'event AND RD_CLK = '1' THEN -- empty_q <= empty_i after C_TCQ; END IF; END PROCESS regout_empty_q; regout_rd_en: PROCESS (RD_CLK) BEGIN -- PROCESS regout_rd_en IF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge rd_en_q <= RD_EN after C_TCQ; END IF; END PROCESS regout_rd_en; ------------------------------------------------------------------------------- -- Calculate user_almost_empty -- user_almost_empty is defined such that, unless more words are written -- to the FIFO, the next read will cause the FIFO to go EMPTY. -- -- In most cases, whenever the output registers are updated (due to a user -- read or a preload condition), then user_almost_empty will update to -- whatever RAM_EMPTY is. -- -- The exception is when the output is valid, the user is not reading, and -- Stage1 is not empty. In this condition, Stage1 will be preloaded from the -- memory, so we need to make sure user_almost_empty deasserts properly under -- this condition. ------------------------------------------------------------------------------- regout_aempty: PROCESS (RD_CLK, rd_rst_i) BEGIN -- PROCESS regout_empty IF rd_rst_i = '1' THEN -- asynchronous reset (active high) almost_empty_i <= '1' after C_TCQ; almost_empty_q <= '1' after C_TCQ; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge IF srst_i = '1' THEN -- synchronous reset (active high) almost_empty_i <= '1' after C_TCQ; almost_empty_q <= '1' after C_TCQ; ELSE IF ((ram_regout_en = '1') OR (FIFOEMPTY = '0' AND read_data_valid_i = '1' AND RD_EN='0')) THEN almost_empty_i <= FIFOEMPTY after C_TCQ; END IF; almost_empty_q <= almost_empty_i after C_TCQ; END IF; END IF; END PROCESS regout_aempty; USEREMPTY <= empty_i; USERALMOSTEMPTY <= almost_empty_i; FIFORDEN <= ram_rd_en; RAMVALID <= ram_valid_i; guvh: IF C_USERVALID_LOW=0 GENERATE USERVALID <= read_data_valid_i; END GENERATE guvh; guvl: if C_USERVALID_LOW=1 GENERATE USERVALID <= NOT read_data_valid_i; END GENERATE guvl; gufh: IF C_USERUNDERFLOW_LOW=0 GENERATE USERUNDERFLOW <= empty_q AND rd_en_q; END GENERATE gufh; gufl: if C_USERUNDERFLOW_LOW=1 GENERATE USERUNDERFLOW <= NOT (empty_q AND rd_en_q); END GENERATE gufl; regout_lat0: PROCESS (RD_CLK, rd_rst_i) BEGIN -- PROCESS regout_lat0 IF (rd_rst_i = '1') THEN -- asynchronous reset (active high) IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF USERSBITERR <= '0' after C_TCQ; USERDBITERR <= '0' after C_TCQ; END IF; -- DRAM resets asynchronously IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE = 2) THEN USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; -- BRAM resets synchronously IF (C_USE_DOUT_RST = 1 AND C_MEMORY_TYPE < 2) THEN IF (RD_CLK'event AND RD_CLK = '1') THEN USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; END IF; ELSIF RD_CLK'event AND RD_CLK = '1' THEN -- rising clock edge IF (srst_i = '1') THEN -- synchronous reset (active high) IF (C_USE_ECC = 0) THEN -- Reset S/DBITERR only if ECC is OFF USERSBITERR <= '0' after C_TCQ; USERDBITERR <= '0' after C_TCQ; END IF; IF (C_USE_DOUT_RST = 1) THEN -- synchronous reset (active high) USERDATA_int <= hexstr_to_std_logic_vec(C_DOUT_RST_VAL, C_DOUT_WIDTH) after C_TCQ; END IF; ELSE IF (ram_regout_en = '1') THEN USERDATA_int <= FIFODATA after C_TCQ; USERSBITERR <= FIFOSBITERR after C_TCQ; USERDBITERR <= FIFODBITERR after C_TCQ; END IF; END IF; END IF; END PROCESS regout_lat0; USERDATA <= USERDATA_int ; -- rle, fixed bug R62 END behavioral; ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Top-level Behavioral Model for Conventional FIFO ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY XilinxCoreLib; USE XilinxCoreLib.fifo_generator_v8_2_bhv_as; USE XilinxCoreLib.fifo_generator_v8_2_bhv_ss; ------------------------------------------------------------------------------- -- Top-level Entity Declaration - This is the top-level of the conventional -- FIFO Bhv Model ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2_conv IS GENERIC ( --------------------------------------------------------------------------- -- Generic Declarations --------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; --not used C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; --not used C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; --not used C_FAMILY : string := ""; --not used in bhv model C_FULL_FLAGS_RST_VAL : integer := 0; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; --not used C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; --not used in bhv model C_HAS_MEMINIT_FILE : integer := 0; --not used C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; --not used C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; --not used C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; --not used C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; --not used C_OPTIMIZATION_MODE : integer := 0; --not used C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; --not used in bhv model C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; --not used in bhv model C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; --not used C_MSGON_VAL : integer := 1; --not used in bhv model C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- BACKUP : IN std_logic := '0'; BACKUP_MARKER : IN std_logic := '0'; CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_CLK : IN std_logic := '0'; WR_RST : IN std_logic := '0'; RD_CLK : IN std_logic := '0'; RD_RST : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); -- WR_EN : IN std_logic; --Mandatory input RD_EN : IN std_logic; --Mandatory input --Mandatory input PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INT_CLK : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FULL : OUT std_logic; ALMOST_FULL : OUT std_logic; WR_ACK : OUT std_logic; OVERFLOW : OUT std_logic; EMPTY : OUT std_logic; ALMOST_EMPTY : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); PROG_FULL : OUT std_logic; PROG_EMPTY : OUT std_logic; SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END fifo_generator_v8_2_conv; ------------------------------------------------------------------------------- -- Definition of Parameters ------------------------------------------------------------------------------- -- C_COMMON_CLOCK : Common Clock (1), Independent Clocks (0) -- C_COUNT_TYPE : --not used -- C_DATA_COUNT_WIDTH : Width of DATA_COUNT bus -- C_DEFAULT_VALUE : --not used -- C_DIN_WIDTH : Width of DIN bus -- C_DOUT_RST_VAL : Reset value of DOUT -- C_DOUT_WIDTH : Width of DOUT bus -- C_ENABLE_RLOCS : --not used -- C_FAMILY : not used in bhv model -- C_FULL_FLAGS_RST_VAL : Full flags rst val (0 or 1) -- C_HAS_ALMOST_EMPTY : 1=Core has ALMOST_EMPTY flag -- C_HAS_ALMOST_FULL : 1=Core has ALMOST_FULL flag -- C_HAS_BACKUP : --not used -- C_HAS_DATA_COUNT : 1=Core has DATA_COUNT bus -- C_HAS_INT_CLK : not used in bhv model -- C_HAS_MEMINIT_FILE : --not used -- C_HAS_OVERFLOW : 1=Core has OVERFLOW flag -- C_HAS_RD_DATA_COUNT : 1=Core has RD_DATA_COUNT bus -- C_HAS_RD_RST : --not used -- C_HAS_RST : 1=Core has Async Rst -- C_HAS_SRST : 1=Core has Sync Rst -- C_HAS_UNDERFLOW : 1=Core has UNDERFLOW flag -- C_HAS_VALID : 1=Core has VALID flag -- C_HAS_WR_ACK : 1=Core has WR_ACK flag -- C_HAS_WR_DATA_COUNT : 1=Core has WR_DATA_COUNT bus -- C_HAS_WR_RST : --not used -- C_IMPLEMENTATION_TYPE : 0=Common-Clock Bram/Dram -- 1=Common-Clock ShiftRam -- 2=Indep. Clocks Bram/Dram -- 3=Virtex-4 Built-in -- 4=Virtex-5 Built-in -- C_INIT_WR_PNTR_VAL : --not used -- C_MEMORY_TYPE : 1=Block RAM -- 2=Distributed RAM -- 3=Shift RAM -- 4=Built-in FIFO -- C_MIF_FILE_NAME : --not used -- C_OPTIMIZATION_MODE : --not used -- C_OVERFLOW_LOW : 1=OVERFLOW active low -- C_PRELOAD_LATENCY : Latency of read: 0, 1, 2 -- C_PRELOAD_REGS : 1=Use output registers -- C_PRIM_FIFO_TYPE : not used in bhv model -- C_PROG_EMPTY_THRESH_ASSERT_VAL: PROG_EMPTY assert threshold -- C_PROG_EMPTY_THRESH_NEGATE_VAL: PROG_EMPTY negate threshold -- C_PROG_EMPTY_TYPE : 0=No programmable empty -- 1=Single prog empty thresh constant -- 2=Multiple prog empty thresh constants -- 3=Single prog empty thresh input -- 4=Multiple prog empty thresh inputs -- C_PROG_FULL_THRESH_ASSERT_VAL : PROG_FULL assert threshold -- C_PROG_FULL_THRESH_NEGATE_VAL : PROG_FULL negate threshold -- C_PROG_FULL_TYPE : 0=No prog full -- 1=Single prog full thresh constant -- 2=Multiple prog full thresh constants -- 3=Single prog full thresh input -- 4=Multiple prog full thresh inputs -- C_RD_DATA_COUNT_WIDTH : Width of RD_DATA_COUNT bus -- C_RD_DEPTH : Depth of read interface (2^N) -- C_RD_FREQ : not used in bhv model -- C_RD_PNTR_WIDTH : always log2(C_RD_DEPTH) -- C_UNDERFLOW_LOW : 1=UNDERFLOW active low -- C_USE_DOUT_RST : 1=Resets DOUT on RST -- C_USE_ECC : not used in bhv model -- C_USE_EMBEDDED_REG : 1=Use BRAM embedded output register -- C_USE_FIFO16_FLAGS : not used in bhv model -- C_USE_FWFT_DATA_COUNT : 1=Use extra logic for FWFT data count -- C_VALID_LOW : 1=VALID active low -- C_WR_ACK_LOW : 1=WR_ACK active low -- C_WR_DATA_COUNT_WIDTH : Width of WR_DATA_COUNT bus -- C_WR_DEPTH : Depth of write interface (2^N) -- C_WR_FREQ : not used in bhv model -- C_WR_PNTR_WIDTH : always log2(C_WR_DEPTH) -- C_WR_RESPONSE_LATENCY : --not used ------------------------------------------------------------------------------- -- Definition of Ports ------------------------------------------------------------------------------- -- BACKUP : Not used -- BACKUP_MARKER: Not used -- CLK : Clock -- DIN : Input data bus -- PROG_EMPTY_THRESH : Threshold for Programmable Empty Flag -- PROG_EMPTY_THRESH_ASSERT: Threshold for Programmable Empty Flag -- PROG_EMPTY_THRESH_NEGATE: Threshold for Programmable Empty Flag -- PROG_FULL_THRESH : Threshold for Programmable Full Flag -- PROG_FULL_THRESH_ASSERT : Threshold for Programmable Full Flag -- PROG_FULL_THRESH_NEGATE : Threshold for Programmable Full Flag -- RD_CLK : Read Domain Clock -- RD_EN : Read enable -- RD_RST : Not used -- RST : Asynchronous Reset -- SRST : Synchronous Reset -- WR_CLK : Write Domain Clock -- WR_EN : Write enable -- WR_RST : Not used -- INT_CLK : Internal Clock -- ALMOST_EMPTY : One word remaining in FIFO -- ALMOST_FULL : One empty space remaining in FIFO -- DATA_COUNT : Number of data words in fifo( synchronous to CLK) -- DOUT : Output data bus -- EMPTY : Empty flag -- FULL : Full flag -- OVERFLOW : Last write rejected -- PROG_EMPTY : Programmable Empty Flag -- PROG_FULL : Programmable Full Flag -- RD_DATA_COUNT: Number of data words in fifo (synchronous to RD_CLK) -- UNDERFLOW : Last read rejected -- VALID : Last read acknowledged, DOUT bus VALID -- WR_ACK : Last write acknowledged -- WR_DATA_COUNT: Number of data words in fifo (synchronous to WR_CLK) -- SBITERR : Single Bit ECC Error Detected -- DBITERR : Double Bit ECC Error Detected ------------------------------------------------------------------------------- ARCHITECTURE behavioral OF fifo_generator_v8_2_conv IS ----------------------------------------------------------------------------- -- FUNCTION two_comp -- Returns a 2's complement value ------------------------------------------------------------------------------- FUNCTION two_comp( vect : std_logic_vector) RETURN std_logic_vector IS VARIABLE local_vect : std_logic_vector(vect'high DOWNTO 0); VARIABLE toggle : integer := 0; BEGIN FOR i IN 0 TO vect'high LOOP IF (toggle = 1) THEN IF (vect(i) = '0') THEN local_vect(i) := '1'; ELSE local_vect(i) := '0'; END IF; ELSE local_vect(i) := vect(i); IF (vect(i) = '1') THEN toggle := 1; END IF; END IF; END LOOP; RETURN local_vect; END two_comp; ----------------------------------------------------------------------------- -- FUNCTION int_2_std_logic_vector -- Returns a std_logic_vector for an integer value for a given width. ------------------------------------------------------------------------------- FUNCTION int_2_std_logic_vector( value, bitwidth : integer ) RETURN std_logic_vector IS VARIABLE running_value : integer := value; VARIABLE running_result : std_logic_vector(bitwidth-1 DOWNTO 0); BEGIN IF (value < 0) THEN running_value := -1 * value; END IF; FOR i IN 0 TO bitwidth-1 LOOP IF running_value MOD 2 = 0 THEN running_result(i) := '0'; ELSE running_result(i) := '1'; END IF; running_value := running_value/2; END LOOP; IF (value < 0) THEN -- find the 2s complement RETURN two_comp(running_result); ELSE RETURN running_result; END IF; END int_2_std_logic_vector; COMPONENT fifo_generator_v8_2_bhv_as GENERIC ( -------------------------------------------------------------------------------- -- Generic Declarations -------------------------------------------------------------------------------- C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 2; C_HAS_RST : integer := 1; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 2; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0); RD_CLK : IN std_logic; RD_EN : IN std_logic; RD_EN_USER : IN std_logic; RST : IN std_logic; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; WR_RST : IN std_logic; RD_RST : IN std_logic; WR_CLK : IN std_logic; WR_EN : IN std_logic; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; USER_EMPTY_FB : IN std_logic := '1'; ALMOST_EMPTY : OUT std_logic; ALMOST_FULL : OUT std_logic; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); EMPTY : OUT std_logic; FULL : OUT std_logic; OVERFLOW : OUT std_logic; PROG_EMPTY : OUT std_logic; PROG_FULL : OUT std_logic; VALID : OUT std_logic; RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); UNDERFLOW : OUT std_logic; WR_ACK : OUT std_logic; WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); DBITERR : OUT std_logic := '0'; SBITERR : OUT std_logic := '0' ); END COMPONENT; COMPONENT fifo_generator_v8_2_bhv_ss GENERIC ( -------------------------------------------------------------------------------- -- Generic Declarations (alphabetical) -------------------------------------------------------------------------------- C_DATA_COUNT_WIDTH : integer := 2; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RST : integer := 0; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_MEMORY_TYPE : integer := 1; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DEPTH : integer := 256; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_ECC : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DEPTH : integer := 256; C_WR_PNTR_WIDTH : integer := 8; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- CLK : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); RD_EN : IN std_logic := '0'; RST : IN std_logic := '0'; RST_FULL_GEN : IN std_logic := '0'; RST_FULL_FF : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_EN : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; ALMOST_EMPTY : OUT std_logic; ALMOST_FULL : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); EMPTY : OUT std_logic; FULL : OUT std_logic; OVERFLOW : OUT std_logic; PROG_EMPTY : OUT std_logic; PROG_FULL : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; WR_ACK : OUT std_logic; DBITERR : OUT std_logic := '0'; SBITERR : OUT std_logic := '0' ); END COMPONENT; COMPONENT fifo_generator_v8_2_bhv_preload0 GENERIC ( C_DOUT_RST_VAL : string; C_DOUT_WIDTH : integer; C_HAS_RST : integer; C_HAS_SRST : integer; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USERVALID_LOW : integer := 0; C_USERUNDERFLOW_LOW : integer := 0; C_TCQ : time := 100 ps; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_MEMORY_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT ( RD_CLK : IN std_logic; RD_RST : IN std_logic; SRST : IN std_logic; RD_EN : IN std_logic; FIFOEMPTY : IN std_logic; FIFODATA : IN std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FIFOSBITERR : IN std_logic; FIFODBITERR : IN std_logic; USERDATA : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); USERVALID : OUT std_logic; USERUNDERFLOW : OUT std_logic; USEREMPTY : OUT std_logic; USERALMOSTEMPTY : OUT std_logic; RAMVALID : OUT std_logic; FIFORDEN : OUT std_logic; USERSBITERR : OUT std_logic; USERDBITERR : OUT std_logic ); END COMPONENT; -- Constant to have clock to register delay CONSTANT C_TCQ : time := 100 ps; SIGNAL zero : std_logic := '0'; SIGNAL CLK_INT : std_logic := '0'; ----------------------------------------------------------------------------- -- Internal Signals for delayed input signals -- All the input signals except Clock are delayed by 100 ps and then given to -- the models. ----------------------------------------------------------------------------- SIGNAL rst_delayed : std_logic := '0'; SIGNAL srst_delayed : std_logic := '0'; SIGNAL wr_rst_delayed : std_logic := '0'; SIGNAL rd_rst_delayed : std_logic := '0'; SIGNAL din_delayed : std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wr_en_delayed : std_logic := '0'; SIGNAL rd_en_delayed : std_logic := '0'; SIGNAL prog_empty_thresh_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_empty_thresh_assert_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_empty_thresh_negate_delayed : std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_full_thresh_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_full_thresh_assert_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL prog_full_thresh_negate_delayed : std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL injectdbiterr_delayed : std_logic := '0'; SIGNAL injectsbiterr_delayed : std_logic := '0'; ----------------------------------------------------------------------------- -- Internal Signals -- In the normal case, these signals tie directly to the FIFO's inputs and -- outputs. -- In the case of Preload Latency 0 or 1, these are the intermediate -- signals between the internal FIFO and the preload logic. ----------------------------------------------------------------------------- SIGNAL rd_en_fifo_in : std_logic; SIGNAL dout_fifo_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); SIGNAL empty_fifo_out : std_logic; SIGNAL almost_empty_fifo_out : std_logic; SIGNAL valid_fifo_out : std_logic; SIGNAL underflow_fifo_out : std_logic; SIGNAL rd_data_count_fifo_out : std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); SIGNAL wr_data_count_fifo_out : std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); SIGNAL data_count_fifo_out : std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); SIGNAL DATA_COUNT_FWFT : std_logic_vector(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0'); SIGNAL SS_FWFT_RD : std_logic := '0' ; SIGNAL SS_FWFT_WR : std_logic := '0' ; SIGNAL FULL_int : std_logic ; SIGNAL dout_p0_out : std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); signal valid_p0_out : std_logic; signal empty_p0_out : std_logic; signal underflow_p0_out : std_logic; signal almost_empty_p0_out : std_logic; signal empty_p0_out_q : std_logic; signal almost_empty_p0_out_q : std_logic; SIGNAL ram_valid : std_logic; --Internal signal used to monitor the --ram_valid state signal rst_fwft : std_logic; signal sbiterr_fifo_out : std_logic; signal dbiterr_fifo_out : std_logic; signal wr_rst_i : std_logic := '0'; signal rd_rst_i : std_logic := '0'; signal rst_i : std_logic := '0'; signal rst_full_gen_i : std_logic := '0'; signal rst_full_ff_i : std_logic := '0'; signal rst_2_sync : std_logic := '0'; signal clk_2_sync : std_logic := '0'; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ----------------------------------------------------------------------------- -- FUNCTION log2roundup -- Returns a log2 of the input value ----------------------------------------------------------------------------- FUNCTION log2roundup ( data_value : integer) RETURN integer IS VARIABLE width : integer := 0; VARIABLE cnt : integer := 1; BEGIN IF (data_value <= 1) THEN width := 0; ELSE WHILE (cnt < data_value) LOOP width := width + 1; cnt := cnt *2; END LOOP; END IF; RETURN width; END log2roundup; CONSTANT FULL_FLAGS_RST_VAL : integer := if_then_else((C_HAS_SRST = 1),0,C_FULL_FLAGS_RST_VAL); CONSTANT IS_WR_PNTR_WIDTH_CORRECT : integer := if_then_else((C_WR_PNTR_WIDTH = log2roundup(C_WR_DEPTH)),1,0); CONSTANT IS_RD_PNTR_WIDTH_CORRECT : integer := if_then_else((C_RD_PNTR_WIDTH = log2roundup(C_RD_DEPTH)),1,0); BEGIN rst_delayed <= RST AFTER C_TCQ; srst_delayed <= SRST AFTER C_TCQ; wr_rst_delayed <= WR_RST AFTER C_TCQ; rd_rst_delayed <= RD_RST AFTER C_TCQ; din_delayed <= DIN AFTER C_TCQ; wr_en_delayed <= WR_EN AFTER C_TCQ; rd_en_delayed <= RD_EN AFTER C_TCQ; prog_empty_thresh_delayed <= PROG_EMPTY_THRESH AFTER C_TCQ; prog_empty_thresh_assert_delayed <= PROG_EMPTY_THRESH_ASSERT AFTER C_TCQ; prog_empty_thresh_negate_delayed <= PROG_EMPTY_THRESH_NEGATE AFTER C_TCQ; prog_full_thresh_delayed <= PROG_FULL_THRESH AFTER C_TCQ; prog_full_thresh_assert_delayed <= PROG_FULL_THRESH_ASSERT AFTER C_TCQ; prog_full_thresh_negate_delayed <= PROG_FULL_THRESH_NEGATE AFTER C_TCQ; injectdbiterr_delayed <= INJECTDBITERR AFTER C_TCQ; injectsbiterr_delayed <= INJECTSBITERR AFTER C_TCQ; --Assign Ground Signal zero <= '0'; ASSERT (C_MEMORY_TYPE /= 4) REPORT "FAILURE : Behavioral models for Virtex-4, Virtex-5, Virtex-6 and 7-Series FPGA's built-in FIFO configurations is currently not supported. Please select the structural simulation model option in CORE Generator. You can enable this in CORE Generator by selecting Project -> Project Options -> Generation tab -> Structural Simulation. See the FIFO Generator User Guide for more information." SEVERITY FAILURE; -- ASSERT (C_IMPLEMENTATION_TYPE /= 2) REPORT "WARNING: Behavioral models for independent clock FIFO configurations do not model synchronization delays. The behavioral models are functionally correct, and will represent the behavior of the configured FIFO. See the FIFO Generator User Guide for more information." SEVERITY NOTE; ASSERT (IS_WR_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_WR_PNTR_WIDTH is not log2 of C_WR_DEPTH." SEVERITY FAILURE; ASSERT (IS_RD_PNTR_WIDTH_CORRECT /= 0) REPORT "FAILURE : C_RD_PNTR_WIDTH is not log2 of C_RD_DEPTH." SEVERITY FAILURE; gen_ss : IF ((C_IMPLEMENTATION_TYPE = 0) OR (C_IMPLEMENTATION_TYPE = 1)) GENERATE fgss : fifo_generator_v8_2_bhv_ss GENERIC MAP ( C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_DIN_WIDTH => C_DIN_WIDTH, C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => C_DOUT_WIDTH, C_FULL_FLAGS_RST_VAL => FULL_FLAGS_RST_VAL, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_HAS_RST => C_HAS_RST, C_HAS_SRST => C_HAS_SRST, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_HAS_VALID => C_HAS_VALID, C_HAS_WR_ACK => C_HAS_WR_ACK, C_MEMORY_TYPE => C_MEMORY_TYPE, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL, C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE, C_RD_DEPTH => C_RD_DEPTH, C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_USE_ECC => C_USE_ECC, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, C_VALID_LOW => C_VALID_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DEPTH => C_WR_DEPTH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH, C_TCQ => C_TCQ, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_FIFO_TYPE => C_FIFO_TYPE ) PORT MAP( --Inputs CLK => CLK, DIN => din_delayed, PROG_EMPTY_THRESH => prog_empty_thresh_delayed, PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed, PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed, PROG_FULL_THRESH => prog_full_thresh_delayed, PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed, PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed, RD_EN => rd_en_fifo_in, RST => rst_i, SRST => srst_delayed, RST_FULL_GEN => rst_full_gen_i, RST_FULL_FF => rst_full_ff_i, WR_EN => wr_en_delayed, INJECTDBITERR => injectdbiterr_delayed, INJECTSBITERR => injectsbiterr_delayed, --Outputs ALMOST_EMPTY => almost_empty_fifo_out, ALMOST_FULL => ALMOST_FULL, DATA_COUNT => data_count_fifo_out, DOUT => dout_fifo_out, EMPTY => empty_fifo_out, FULL => FULL_int, OVERFLOW => OVERFLOW, PROG_EMPTY => PROG_EMPTY, PROG_FULL => PROG_FULL, UNDERFLOW => underflow_fifo_out, VALID => valid_fifo_out, WR_ACK => WR_ACK, DBITERR => dbiterr_fifo_out, SBITERR => sbiterr_fifo_out ); END GENERATE gen_ss; gen_as : IF (C_IMPLEMENTATION_TYPE = 2 OR C_FIFO_TYPE = 3) GENERATE fgas : fifo_generator_v8_2_bhv_as GENERIC MAP ( C_DIN_WIDTH => C_DIN_WIDTH, C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => C_DOUT_WIDTH, C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT, C_HAS_RST => C_HAS_RST, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_HAS_VALID => C_HAS_VALID, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT, C_MEMORY_TYPE => C_MEMORY_TYPE, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL, C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE, C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH, C_RD_DEPTH => C_RD_DEPTH, C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_USE_ECC => C_USE_ECC, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, C_VALID_LOW => C_VALID_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH, C_WR_DEPTH => C_WR_DEPTH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH, C_TCQ => C_TCQ, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_FIFO_TYPE => C_FIFO_TYPE ) PORT MAP( --Inputs WR_CLK => WR_CLK, RD_CLK => RD_CLK, RST => rst_i, RST_FULL_GEN => rst_full_gen_i, RST_FULL_FF => rst_full_ff_i, WR_RST => wr_rst_i, RD_RST => rd_rst_i, DIN => din_delayed, RD_EN => rd_en_fifo_in, WR_EN => wr_en_delayed, RD_EN_USER => rd_en_delayed, PROG_FULL_THRESH => prog_full_thresh_delayed, PROG_EMPTY_THRESH_ASSERT => prog_empty_thresh_assert_delayed, PROG_EMPTY_THRESH_NEGATE => prog_empty_thresh_negate_delayed, PROG_EMPTY_THRESH => prog_empty_thresh_delayed, PROG_FULL_THRESH_ASSERT => prog_full_thresh_assert_delayed, PROG_FULL_THRESH_NEGATE => prog_full_thresh_negate_delayed, INJECTDBITERR => injectdbiterr_delayed, INJECTSBITERR => injectsbiterr_delayed, USER_EMPTY_FB => empty_p0_out, --Outputs DOUT => dout_fifo_out, FULL => FULL_int, ALMOST_FULL => ALMOST_FULL, WR_ACK => WR_ACK, OVERFLOW => OVERFLOW, EMPTY => empty_fifo_out, ALMOST_EMPTY => almost_empty_fifo_out, VALID => valid_fifo_out, UNDERFLOW => underflow_fifo_out, RD_DATA_COUNT => rd_data_count_fifo_out, WR_DATA_COUNT => wr_data_count_fifo_out, PROG_FULL => PROG_FULL, PROG_EMPTY => PROG_EMPTY, DBITERR => dbiterr_fifo_out, SBITERR => sbiterr_fifo_out ); END GENERATE gen_as; ------------------------------------------------------------------------- -- Connect internal clock used for FWFT logic based on C_COMMON_CLOCK --- ------------------------------------------------------------------------- clock_fwft_common: IF (C_COMMON_CLOCK=1 ) GENERATE CLK_INT <= CLK; END GENERATE clock_fwft_common; clock_fwft: IF (C_COMMON_CLOCK= 0 ) GENERATE CLK_INT <= RD_CLK; END GENERATE clock_fwft; ----------------------------------------------------------------------------- -- Connect Internal Signals -- In the normal case, these signals tie directly to the FIFO's inputs and -- outputs. -- In the case of Preload Latency 0 or 1, these are the intermediate -- signals between the internal FIFO and the preload logic. ----------------------------------------------------------------------------- latnrm: IF (C_PRELOAD_LATENCY=1 OR C_PRELOAD_LATENCY=2 OR C_FIFO_TYPE = 3) GENERATE rd_en_fifo_in <= rd_en_delayed; DOUT <= dout_fifo_out; VALID <= valid_fifo_out; EMPTY <= empty_fifo_out; ALMOST_EMPTY <= almost_empty_fifo_out; UNDERFLOW <= underflow_fifo_out; RD_DATA_COUNT <= rd_data_count_fifo_out; WR_DATA_COUNT <= wr_data_count_fifo_out; SBITERR <= sbiterr_fifo_out; DBITERR <= dbiterr_fifo_out; END GENERATE latnrm; lat0: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND C_FIFO_TYPE /= 3) GENERATE rst_fwft <= rd_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i WHEN (C_HAS_RST = 1) ELSE '0'; lat0logic : fifo_generator_v8_2_bhv_preload0 GENERIC MAP ( C_DOUT_RST_VAL => C_DOUT_RST_VAL, C_DOUT_WIDTH => C_DOUT_WIDTH, C_HAS_RST => C_HAS_RST, C_HAS_SRST => C_HAS_SRST, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_ECC => C_USE_ECC, C_USERVALID_LOW => C_VALID_LOW, C_USERUNDERFLOW_LOW => C_UNDERFLOW_LOW, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, C_MEMORY_TYPE => C_MEMORY_TYPE, C_FIFO_TYPE => C_FIFO_TYPE ) PORT MAP ( RD_CLK => CLK_INT, RD_RST => rst_fwft, SRST => srst_delayed, RD_EN => rd_en_delayed, FIFOEMPTY => empty_fifo_out, FIFODATA => dout_fifo_out, FIFOSBITERR => sbiterr_fifo_out, FIFODBITERR => dbiterr_fifo_out, USERDATA => dout_p0_out, USERVALID => valid_p0_out, USEREMPTY => empty_p0_out, USERALMOSTEMPTY => almost_empty_p0_out, USERUNDERFLOW => underflow_p0_out, RAMVALID => ram_valid, --Used for observing the state of the ram_valid FIFORDEN => rd_en_fifo_in, USERSBITERR => SBITERR, USERDBITERR => DBITERR ); rdcg: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH)) GENERATE eclk: PROCESS (CLK_INT,rst_fwft) BEGIN -- process eclk IF (rst_fwft='1') THEN empty_p0_out_q <= '1' after C_TCQ; almost_empty_p0_out_q <= '1' after C_TCQ; ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge empty_p0_out_q <= empty_p0_out after C_TCQ; almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ; END IF; END PROCESS eclk; rcsproc: PROCESS (rd_data_count_fifo_out, empty_p0_out_q, almost_empty_p0_out_q,rst_fwft) BEGIN -- process rcsproc IF (empty_p0_out_q='1' OR rst_fwft='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH); ELSIF (almost_empty_p0_out_q='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(1, C_RD_DATA_COUNT_WIDTH); ELSE RD_DATA_COUNT <= rd_data_count_fifo_out ; END IF; END PROCESS rcsproc; END GENERATE rdcg; rdcg1: IF (C_USE_FWFT_DATA_COUNT=1 AND (C_RD_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH)) GENERATE eclk1: PROCESS (CLK_INT,rst_fwft) BEGIN -- process eclk IF (rst_fwft='1') THEN empty_p0_out_q <= '1' after C_TCQ; almost_empty_p0_out_q <= '1' after C_TCQ; ELSIF CLK_INT'event AND CLK_INT = '1' THEN -- rising clock edge empty_p0_out_q <= empty_p0_out after C_TCQ; almost_empty_p0_out_q <= almost_empty_p0_out after C_TCQ; END IF; END PROCESS eclk1; rcsproc1: PROCESS (rd_data_count_fifo_out, empty_p0_out_q, almost_empty_p0_out_q,rst_fwft) BEGIN -- process rcsproc IF (empty_p0_out_q='1' OR rst_fwft='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH); ELSIF (almost_empty_p0_out_q='1') THEN RD_DATA_COUNT <= int_2_std_logic_vector(0, C_RD_DATA_COUNT_WIDTH); ELSE RD_DATA_COUNT <= rd_data_count_fifo_out ; END IF; END PROCESS rcsproc1; END GENERATE rdcg1; nrdcg: IF (C_USE_FWFT_DATA_COUNT=0) GENERATE RD_DATA_COUNT <= rd_data_count_fifo_out; END GENERATE nrdcg; WR_DATA_COUNT <= wr_data_count_fifo_out; --------------------------------------------------- -- logics for common-clock data count with fwft -- For common-clock FIFOs with FWFT, data count -- is calculated as an up-down counter to maintain -- accuracy. --------------------------------------------------- gfwft_rd: IF (C_VALID_LOW = 0) GENERATE SS_FWFT_RD <= rd_en_delayed AND valid_p0_out ; END GENERATE gfwft_rd; ngfwft_rd: IF (C_VALID_LOW = 1) GENERATE SS_FWFT_RD <= rd_en_delayed AND NOT valid_p0_out ; END GENERATE ngfwft_rd; SS_FWFT_WR <= wr_en_delayed AND (NOT FULL_int) ; cc_data_cnt: IF (C_HAS_DATA_COUNT = 1 AND C_USE_FWFT_DATA_COUNT = 1) GENERATE count_fwft: PROCESS (CLK, rst_fwft) BEGIN IF (rst_fwft = '1' AND C_HAS_RST=1) THEN DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ; ELSIF CLK'event AND CLK = '1' THEN IF (srst_delayed='1' AND C_HAS_SRST=1) THEN DATA_COUNT_FWFT <= (OTHERS=>'0') after C_TCQ; ELSE IF (SS_FWFT_WR = '0' and SS_FWFT_RD ='0') THEN DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ; ELSIF (SS_FWFT_WR = '0' and SS_FWFT_RD ='1') THEN DATA_COUNT_FWFT <= DATA_COUNT_FWFT - 1 after C_TCQ; ELSIF (SS_FWFT_WR = '1' and SS_FWFT_RD ='0') THEN DATA_COUNT_FWFT <= DATA_COUNT_FWFT + 1 after C_TCQ; ELSE DATA_COUNT_FWFT <= DATA_COUNT_FWFT after C_TCQ; END IF ; END IF; END IF; END PROCESS count_fwft; END GENERATE cc_data_cnt; ---------------------------------------------- DOUT <= dout_p0_out; VALID <= valid_p0_out; EMPTY <= empty_p0_out; ALMOST_EMPTY <= almost_empty_p0_out; UNDERFLOW <= underflow_p0_out; END GENERATE lat0; gdc_fwft: IF (C_HAS_DATA_COUNT = 1) GENERATE begin ss_count: IF ((NOT ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0)) ) OR (C_USE_FWFT_DATA_COUNT = 0) )GENERATE begin DATA_COUNT <= data_count_fifo_out ; end generate ss_count ; ss_count_fwft1: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND (C_DATA_COUNT_WIDTH > C_RD_PNTR_WIDTH) AND (C_USE_FWFT_DATA_COUNT = 1) ) GENERATE begin DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO 0) ; end generate ss_count_fwft1 ; ss_count_fwft2: IF ((C_PRELOAD_REGS = 1) AND (C_PRELOAD_LATENCY = 0) AND (C_DATA_COUNT_WIDTH <= C_RD_PNTR_WIDTH) AND (C_USE_FWFT_DATA_COUNT = 1)) GENERATE begin DATA_COUNT <= DATA_COUNT_FWFT(C_RD_PNTR_WIDTH DOWNTO C_RD_PNTR_WIDTH-C_DATA_COUNT_WIDTH+1) ; end generate ss_count_fwft2 ; end generate gdc_fwft; FULL <= FULL_int; ------------------------------------------------------------------------------- -- If there is a reset input, generate internal reset signals -- The latency of reset will match the core behavior ------------------------------------------------------------------------------- --Single RST grst_sync : IF (C_ENABLE_RST_SYNC = 1 OR C_FIFO_TYPE = 3) GENERATE grst : IF (C_HAS_RST = 1) GENERATE gic_rst : IF (C_COMMON_CLOCK = 0 OR C_FIFO_TYPE = 3) GENERATE SIGNAL rd_rst_asreg : std_logic:= '0'; SIGNAL rd_rst_asreg_d1 : std_logic:= '0'; SIGNAL rd_rst_asreg_d2 : std_logic:= '0'; SIGNAL rd_rst_comb : std_logic:= '0'; SIGNAL rd_rst_reg : std_logic:= '0'; SIGNAL wr_rst_asreg : std_logic:= '0'; SIGNAL wr_rst_asreg_d1 : std_logic:= '0'; SIGNAL wr_rst_asreg_d2 : std_logic:= '0'; SIGNAL wr_rst_comb : std_logic:= '0'; SIGNAL wr_rst_reg : std_logic:= '0'; BEGIN PROCESS (WR_CLK, rst_delayed) BEGIN IF (rst_delayed = '1') THEN wr_rst_asreg <= '1' after C_TCQ; ELSIF (WR_CLK'event and WR_CLK = '1') THEN IF (wr_rst_asreg_d1 = '1') THEN wr_rst_asreg <= '0' after C_TCQ; END IF; END IF; IF (WR_CLK'event and WR_CLK = '1') THEN wr_rst_asreg_d1 <= wr_rst_asreg after C_TCQ; wr_rst_asreg_d2 <= wr_rst_asreg_d1 after C_TCQ; END IF; END PROCESS; PROCESS (wr_rst_asreg, wr_rst_asreg_d2) BEGIN wr_rst_comb <= NOT wr_rst_asreg_d2 AND wr_rst_asreg; END PROCESS; PROCESS (WR_CLK, wr_rst_comb) BEGIN IF (wr_rst_comb = '1') THEN wr_rst_reg <= '1' after C_TCQ; ELSIF (WR_CLK'event and WR_CLK = '1') THEN wr_rst_reg <= '0' after C_TCQ; END IF; END PROCESS; PROCESS (RD_CLK, rst_delayed) BEGIN IF (rst_delayed = '1') THEN rd_rst_asreg <= '1' after C_TCQ; ELSIF (RD_CLK'event and RD_CLK = '1') THEN IF (rd_rst_asreg_d1 = '1') THEN rd_rst_asreg <= '0' after C_TCQ; END IF; END IF; IF (RD_CLK'event and RD_CLK = '1') THEN rd_rst_asreg_d1 <= rd_rst_asreg after C_TCQ; rd_rst_asreg_d2 <= rd_rst_asreg_d1 after C_TCQ; END IF; END PROCESS; PROCESS (rd_rst_asreg, rd_rst_asreg_d2) BEGIN rd_rst_comb <= NOT rd_rst_asreg_d2 AND rd_rst_asreg; END PROCESS; PROCESS (RD_CLK, rd_rst_comb) BEGIN IF (rd_rst_comb = '1') THEN rd_rst_reg <= '1' after C_TCQ; ELSIF (RD_CLK'event and RD_CLK = '1') THEN rd_rst_reg <= '0' after C_TCQ; END IF; END PROCESS; wr_rst_i <= wr_rst_reg; rd_rst_i <= rd_rst_reg; END GENERATE gic_rst; gcc_rst : IF (C_COMMON_CLOCK = 1) GENERATE SIGNAL rst_asreg : std_logic := '0'; SIGNAL rst_asreg_d1 : std_logic := '0'; SIGNAL rst_asreg_d2 : std_logic := '0'; SIGNAL rst_comb : std_logic := '0'; SIGNAL rst_reg : std_logic := '0'; BEGIN PROCESS (CLK, rst_delayed) BEGIN IF (rst_delayed = '1') THEN rst_asreg <= '1' after C_TCQ; ELSIF (CLK'event and CLK = '1') THEN IF (rst_asreg_d1 = '1') THEN rst_asreg <= '0' after C_TCQ; ELSE rst_asreg <= rst_asreg after C_TCQ; END IF; END IF; IF (CLK'event and CLK = '1') THEN rst_asreg_d1 <= rst_asreg after C_TCQ; rst_asreg_d2 <= rst_asreg_d1 after C_TCQ; END IF; END PROCESS; PROCESS (rst_asreg, rst_asreg_d2) BEGIN rst_comb <= NOT rst_asreg_d2 AND rst_asreg; END PROCESS; PROCESS (CLK, rst_comb) BEGIN IF (rst_comb = '1') THEN rst_reg <= '1' after C_TCQ; ELSIF (CLK'event and CLK = '1') THEN rst_reg <= '0' after C_TCQ; END IF; END PROCESS; rst_i <= rst_reg; END GENERATE gcc_rst; END GENERATE grst; gnrst : IF (C_HAS_RST = 0) GENERATE wr_rst_i <= '0'; rd_rst_i <= '0'; rst_i <= '0'; END GENERATE gnrst; END GENERATE grst_sync; gnrst_sync : IF (C_ENABLE_RST_SYNC = 0) GENERATE wr_rst_i <= wr_rst_delayed; rd_rst_i <= rd_rst_delayed; rst_i <= '0'; END GENERATE gnrst_sync; rst_2_sync <= rst_delayed WHEN (C_ENABLE_RST_SYNC = 1) ELSE wr_rst_delayed; clk_2_sync <= CLK WHEN (C_COMMON_CLOCK = 1) ELSE WR_CLK; grstd1 : IF (C_HAS_RST = 1 OR C_HAS_SRST = 1 OR C_ENABLE_RST_SYNC = 0) GENERATE -- RST_FULL_GEN replaces the reset falling edge detection used to de-assert -- FULL, ALMOST_FULL & PROG_FULL flags if C_FULL_FLAGS_RST_VAL = 1. -- RST_FULL_FF goes to the reset pin of the final flop of FULL, ALMOST_FULL & -- PROG_FULL grst_full: IF (C_FULL_FLAGS_RST_VAL = 1) GENERATE SIGNAL rst_d1 : STD_LOGIC := '1'; SIGNAL rst_d2 : STD_LOGIC := '1'; SIGNAL rst_d3 : STD_LOGIC := '1'; BEGIN grst_f: IF (C_HAS_SRST = 0) GENERATE prst: PROCESS (rst_2_sync, clk_2_sync) BEGIN IF (rst_2_sync = '1') THEN rst_d1 <= '1'; rst_d2 <= '1'; rst_d3 <= '1'; rst_full_gen_i <= '0'; ELSIF (clk_2_sync'event AND clk_2_sync = '1') THEN rst_d1 <= '0' AFTER C_TCQ; rst_d2 <= rst_d1 AFTER C_TCQ; rst_d3 <= rst_d2 AFTER C_TCQ; rst_full_gen_i <= rst_d3 AFTER C_TCQ; END IF; END PROCESS prst; rst_full_ff_i <= rst_d2; END GENERATE grst_f; ngrst_f: IF (C_HAS_SRST = 1) GENERATE prst: PROCESS (clk_2_sync) BEGIN IF (clk_2_sync'event AND clk_2_sync = '1') THEN IF (srst_delayed = '1') THEN rst_d1 <= '1' AFTER C_TCQ; rst_d2 <= '1' AFTER C_TCQ; rst_d3 <= '1' AFTER C_TCQ; rst_full_gen_i <= '0' AFTER C_TCQ; ELSE rst_d1 <= '0' AFTER C_TCQ; rst_d2 <= rst_d1 AFTER C_TCQ; rst_d3 <= rst_d2 AFTER C_TCQ; rst_full_gen_i <= rst_d3 AFTER C_TCQ; END IF; END IF; END PROCESS prst; rst_full_ff_i <= '0'; END GENERATE ngrst_f; END GENERATE grst_full; gnrst_full: IF (C_FULL_FLAGS_RST_VAL = 0) GENERATE rst_full_gen_i <= '0'; rst_full_ff_i <= wr_rst_i WHEN (C_COMMON_CLOCK = 0) ELSE rst_i; END GENERATE gnrst_full; END GENERATE grstd1; END behavioral; ------------------------------------------------------------------------------- -- -- Register Slice -- Register one AXI channel on forward and/or reverse signal path -- ---------------------------------------------------------------------------- -- -- Structure: -- reg_slice -- ---------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY fifo_generator_v8_2_axic_reg_slice IS GENERIC ( C_FAMILY : string := ""; C_DATA_WIDTH : integer := 32; C_REG_CONFIG : integer := 0 ); PORT ( -- System Signals ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; -- Slave side S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC := '0'; -- Master side M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_VALID : OUT STD_LOGIC := '0'; M_READY : IN STD_LOGIC ); END fifo_generator_v8_2_axic_reg_slice; ARCHITECTURE xilinx OF fifo_generator_v8_2_axic_reg_slice IS SIGNAL storage_data1 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL s_ready_i : STD_LOGIC := '0'; -- local signal of output SIGNAL m_valid_i : STD_LOGIC := '0'; -- local signal of output SIGNAL areset_d1 : STD_LOGIC := '0'; -- Reset delay register -- Constant to have clock to register delay CONSTANT TFF : time := 100 ps; BEGIN -------------------------------------------------------------------- -- -- Both FWD and REV mode -- -------------------------------------------------------------------- gfwd_rev: IF (C_REG_CONFIG = 0) GENERATE CONSTANT ZERO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "10"; CONSTANT ONE : STD_LOGIC_VECTOR(1 DOWNTO 0) := "11"; CONSTANT TWO : STD_LOGIC_VECTOR(1 DOWNTO 0) := "01"; SIGNAL state : STD_LOGIC_VECTOR(1 DOWNTO 0); SIGNAL storage_data2 : STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL load_s1 : STD_LOGIC; SIGNAL load_s2 : STD_LOGIC; SIGNAL load_s1_from_s2 : BOOLEAN; BEGIN -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; -- Reset delay register PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN areset_d1 <= ARESET AFTER TFF; END IF; END PROCESS; -- Load storage1 with either slave side data or from storage2 PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (load_s1 = '1') THEN IF (load_s1_from_s2) THEN storage_data1 <= storage_data2 AFTER TFF; ELSE storage_data1 <= S_PAYLOAD_DATA AFTER TFF; END IF; END IF; END IF; END PROCESS; -- Load storage2 with slave side data PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (load_s2 = '1') THEN storage_data2 <= S_PAYLOAD_DATA AFTER TFF; END IF; END IF; END PROCESS; M_PAYLOAD_DATA <= storage_data1; -- Always load s2 on a valid transaction even if it's unnecessary load_s2 <= S_VALID AND s_ready_i; -- Loading s1 PROCESS(state,S_VALID,M_READY) BEGIN IF ((state = ZERO AND S_VALID = '1') OR -- Load when empty on slave transaction -- Load when ONE if we both have read and write at the same time (state = ONE AND S_VALID = '1' AND M_READY = '1') OR -- Load when TWO and we have a transaction on Master side (state = TWO AND M_READY = '1')) THEN load_s1 <= '1'; ELSE load_s1 <= '0'; END IF; END PROCESS; load_s1_from_s2 <= (state = TWO); -- State Machine for handling output signals PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (ARESET = '1') THEN s_ready_i <= '0' AFTER TFF; state <= ZERO AFTER TFF; ELSIF (areset_d1 = '1') THEN s_ready_i <= '1' AFTER TFF; ELSE CASE (state) IS WHEN ZERO => -- No transaction stored locally IF (S_VALID = '1') THEN -- Got one so move to ONE state <= ONE AFTER TFF; END IF; WHEN ONE => -- One transaction stored locally IF (M_READY = '1' AND S_VALID = '0') THEN -- Read out one so move to ZERO state <= ZERO AFTER TFF; END IF; IF (M_READY = '0' AND S_VALID = '1') THEN -- Got another one so move to TWO state <= TWO AFTER TFF; s_ready_i <= '0' AFTER TFF; END IF; WHEN TWO => -- TWO transaction stored locally IF (M_READY = '1') THEN -- Read out one so move to ONE state <= ONE AFTER TFF; s_ready_i <= '1' AFTER TFF; END IF; WHEN OTHERS => state <= state AFTER TFF; END CASE; END IF; END IF; END PROCESS; -- s_ready_i <= state(1); m_valid_i <= state(0); END GENERATE gfwd_rev; -------------------------------------------------------------------- -- -- C_REG_CONFIG = 1 -- Light-weight mode. -- 1-stage pipeline register with bubble cycle, both FWD and REV pipelining -- Operates same as 1-deep FIFO -- -------------------------------------------------------------------- gfwd_rev_pipeline1: IF (C_REG_CONFIG = 1) GENERATE -- assign local signal to its output signal S_READY <= s_ready_i; M_VALID <= m_valid_i; -- Reset delay register PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN areset_d1 <= ARESET AFTER TFF; END IF; END PROCESS; -- Load storage1 with slave side data PROCESS(ACLK) BEGIN IF (ACLK'event AND ACLK = '1') THEN IF (ARESET = '1') THEN s_ready_i <= '0' AFTER TFF; m_valid_i <= '0' AFTER TFF; ELSIF (areset_d1 = '1') THEN s_ready_i <= '1' AFTER TFF; ELSIF (m_valid_i = '1' AND M_READY = '1') THEN s_ready_i <= '1' AFTER TFF; m_valid_i <= '0' AFTER TFF; ELSIF (S_VALID = '1' AND s_ready_i = '1') THEN s_ready_i <= '0' AFTER TFF; m_valid_i <= '1' AFTER TFF; END IF; IF (m_valid_i = '0') THEN storage_data1 <= S_PAYLOAD_DATA AFTER TFF; END IF; END IF; END PROCESS; M_PAYLOAD_DATA <= storage_data1; END GENERATE gfwd_rev_pipeline1; end xilinx;-- reg_slice ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- -- Top-level Behavioral Model for AXI ------------------------------------------------------------------------------- ------------------------------------------------------------------------------- LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_arith.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; LIBRARY XilinxCoreLib; USE XilinxCoreLib.fifo_generator_v8_2_conv; ------------------------------------------------------------------------------- -- Top-level Entity Declaration - This is the top-level of the AXI FIFO Bhv Model ------------------------------------------------------------------------------- ENTITY fifo_generator_v8_2 IS GENERIC ( ------------------------------------------------------------------------- -- Generic Declarations ------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; C_FAMILY : string := ""; C_FULL_FLAGS_RST_VAL : integer := 1; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; C_HAS_MEMINIT_FILE : integer := 0; C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; C_OPTIMIZATION_MODE : integer := 0; C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; C_PROG_EMPTY_THRESH_ASSERT_VAL : integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL : integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; C_MSGON_VAL : integer := 1; C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; -- AXI Interface related parameters start here C_INTERFACE_TYPE : integer := 0; -- 0: Native Interface; 1: AXI Interface C_AXI_TYPE : integer := 0; -- 0: AXI Stream; 1: AXI Full; 2: AXI Lite C_HAS_AXI_WR_CHANNEL : integer := 0; C_HAS_AXI_RD_CHANNEL : integer := 0; C_HAS_SLAVE_CE : integer := 0; C_HAS_MASTER_CE : integer := 0; C_ADD_NGC_CONSTRAINT : integer := 0; C_USE_COMMON_OVERFLOW : integer := 0; C_USE_COMMON_UNDERFLOW : integer := 0; C_USE_DEFAULT_SETTINGS : integer := 0; -- AXI Full/Lite C_AXI_ID_WIDTH : integer := 0; C_AXI_ADDR_WIDTH : integer := 0; C_AXI_DATA_WIDTH : integer := 0; C_HAS_AXI_AWUSER : integer := 0; C_HAS_AXI_WUSER : integer := 0; C_HAS_AXI_BUSER : integer := 0; C_HAS_AXI_ARUSER : integer := 0; C_HAS_AXI_RUSER : integer := 0; C_AXI_ARUSER_WIDTH : integer := 0; C_AXI_AWUSER_WIDTH : integer := 0; C_AXI_WUSER_WIDTH : integer := 0; C_AXI_BUSER_WIDTH : integer := 0; C_AXI_RUSER_WIDTH : integer := 0; -- AXI Streaming C_HAS_AXIS_TDATA : integer := 0; C_HAS_AXIS_TID : integer := 0; C_HAS_AXIS_TDEST : integer := 0; C_HAS_AXIS_TUSER : integer := 0; C_HAS_AXIS_TREADY : integer := 0; C_HAS_AXIS_TLAST : integer := 0; C_HAS_AXIS_TSTRB : integer := 0; C_HAS_AXIS_TKEEP : integer := 0; C_AXIS_TDATA_WIDTH : integer := 1; C_AXIS_TID_WIDTH : integer := 1; C_AXIS_TDEST_WIDTH : integer := 1; C_AXIS_TUSER_WIDTH : integer := 1; C_AXIS_TSTRB_WIDTH : integer := 1; C_AXIS_TKEEP_WIDTH : integer := 1; -- AXI Channel Type -- WACH --> Write Address Channel -- WDCH --> Write Data Channel -- WRCH --> Write Response Channel -- RACH --> Read Address Channel -- RDCH --> Read Data Channel -- AXIS --> AXI Streaming C_WACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logic C_WDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_WRCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RACH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_RDCH_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie C_AXIS_TYPE : integer := 0; -- 0 = FIFO; 1 = Register Slice; 2 = Pass Through Logie -- AXI Implementation Type -- 1 = Common Clock Block RAM FIFO -- 2 = Common Clock Distributed RAM FIFO -- 11 = Independent Clock Block RAM FIFO -- 12 = Independent Clock Distributed RAM FIFO C_IMPLEMENTATION_TYPE_WACH : integer := 0; C_IMPLEMENTATION_TYPE_WDCH : integer := 0; C_IMPLEMENTATION_TYPE_WRCH : integer := 0; C_IMPLEMENTATION_TYPE_RACH : integer := 0; C_IMPLEMENTATION_TYPE_RDCH : integer := 0; C_IMPLEMENTATION_TYPE_AXIS : integer := 0; -- AXI FIFO Type -- 0 = Data FIFO -- 1 = Packet FIFO -- 2 = Low Latency Sync FIFO -- 3 = Low Latency Async FIFO C_APPLICATION_TYPE_WACH : integer := 0; C_APPLICATION_TYPE_WDCH : integer := 0; C_APPLICATION_TYPE_WRCH : integer := 0; C_APPLICATION_TYPE_RACH : integer := 0; C_APPLICATION_TYPE_RDCH : integer := 0; C_APPLICATION_TYPE_AXIS : integer := 0; -- Enable ECC -- 0 = ECC disabled -- 1 = ECC enabled C_USE_ECC_WACH : integer := 0; C_USE_ECC_WDCH : integer := 0; C_USE_ECC_WRCH : integer := 0; C_USE_ECC_RACH : integer := 0; C_USE_ECC_RDCH : integer := 0; C_USE_ECC_AXIS : integer := 0; -- ECC Error Injection Type -- 0 = No Error Injection -- 1 = Single Bit Error Injection -- 2 = Double Bit Error Injection -- 3 = Single Bit and Double Bit Error Injection C_ERROR_INJECTION_TYPE_WACH : integer := 0; C_ERROR_INJECTION_TYPE_WDCH : integer := 0; C_ERROR_INJECTION_TYPE_WRCH : integer := 0; C_ERROR_INJECTION_TYPE_RACH : integer := 0; C_ERROR_INJECTION_TYPE_RDCH : integer := 0; C_ERROR_INJECTION_TYPE_AXIS : integer := 0; -- Input Data Width -- Accumulation of all AXI input signal's width C_DIN_WIDTH_WACH : integer := 1; C_DIN_WIDTH_WDCH : integer := 1; C_DIN_WIDTH_WRCH : integer := 1; C_DIN_WIDTH_RACH : integer := 1; C_DIN_WIDTH_RDCH : integer := 1; C_DIN_WIDTH_AXIS : integer := 1; C_WR_DEPTH_WACH : integer := 16; C_WR_DEPTH_WDCH : integer := 16; C_WR_DEPTH_WRCH : integer := 16; C_WR_DEPTH_RACH : integer := 16; C_WR_DEPTH_RDCH : integer := 16; C_WR_DEPTH_AXIS : integer := 16; C_WR_PNTR_WIDTH_WACH : integer := 4; C_WR_PNTR_WIDTH_WDCH : integer := 4; C_WR_PNTR_WIDTH_WRCH : integer := 4; C_WR_PNTR_WIDTH_RACH : integer := 4; C_WR_PNTR_WIDTH_RDCH : integer := 4; C_WR_PNTR_WIDTH_AXIS : integer := 4; C_HAS_DATA_COUNTS_WACH : integer := 0; C_HAS_DATA_COUNTS_WDCH : integer := 0; C_HAS_DATA_COUNTS_WRCH : integer := 0; C_HAS_DATA_COUNTS_RACH : integer := 0; C_HAS_DATA_COUNTS_RDCH : integer := 0; C_HAS_DATA_COUNTS_AXIS : integer := 0; C_HAS_PROG_FLAGS_WACH : integer := 0; C_HAS_PROG_FLAGS_WDCH : integer := 0; C_HAS_PROG_FLAGS_WRCH : integer := 0; C_HAS_PROG_FLAGS_RACH : integer := 0; C_HAS_PROG_FLAGS_RDCH : integer := 0; C_HAS_PROG_FLAGS_AXIS : integer := 0; C_PROG_FULL_TYPE_WACH : integer := 0; C_PROG_FULL_TYPE_WDCH : integer := 0; C_PROG_FULL_TYPE_WRCH : integer := 0; C_PROG_FULL_TYPE_RACH : integer := 0; C_PROG_FULL_TYPE_RDCH : integer := 0; C_PROG_FULL_TYPE_AXIS : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer := 0; C_PROG_EMPTY_TYPE_WACH : integer := 0; C_PROG_EMPTY_TYPE_WDCH : integer := 0; C_PROG_EMPTY_TYPE_WRCH : integer := 0; C_PROG_EMPTY_TYPE_RACH : integer := 0; C_PROG_EMPTY_TYPE_RDCH : integer := 0; C_PROG_EMPTY_TYPE_AXIS : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer := 0; C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer := 0; C_REG_SLICE_MODE_WACH : integer := 0; C_REG_SLICE_MODE_WDCH : integer := 0; C_REG_SLICE_MODE_WRCH : integer := 0; C_REG_SLICE_MODE_RACH : integer := 0; C_REG_SLICE_MODE_RDCH : integer := 0; C_REG_SLICE_MODE_AXIS : integer := 0 ); PORT( ------------------------------------------------------------------------------ -- Input and Output Declarations ------------------------------------------------------------------------------ -- Conventional FIFO Interface Signals BACKUP : IN std_logic := '0'; BACKUP_MARKER : IN std_logic := '0'; CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_CLK : IN std_logic := '0'; WR_RST : IN std_logic := '0'; RD_CLK : IN std_logic := '0'; RD_RST : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); WR_EN : IN std_logic := '0'; RD_EN : IN std_logic := '0'; -- Optional inputs PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INT_CLK : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FULL : OUT std_logic; ALMOST_FULL : OUT std_logic; WR_ACK : OUT std_logic; OVERFLOW : OUT std_logic; EMPTY : OUT std_logic; ALMOST_EMPTY : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); PROG_FULL : OUT std_logic; PROG_EMPTY : OUT std_logic; SBITERR : OUT std_logic; DBITERR : OUT std_logic; -- AXI Global Signal M_ACLK : IN std_logic := '0'; S_ACLK : IN std_logic := '0'; S_ARESETN : IN std_logic := '0'; M_ACLK_EN : IN std_logic := '0'; S_ACLK_EN : IN std_logic := '0'; -- AXI Full/Lite Slave Write Channel (write side) S_AXI_AWID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWUSER : IN std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_AWVALID : IN std_logic := '0'; S_AXI_AWREADY : OUT std_logic; S_AXI_WID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WSTRB : IN std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WLAST : IN std_logic := '0'; S_AXI_WUSER : IN std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_WVALID : IN std_logic := '0'; S_AXI_WREADY : OUT std_logic; S_AXI_BID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0); S_AXI_BUSER : OUT std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0); S_AXI_BVALID : OUT std_logic; S_AXI_BREADY : IN std_logic := '0'; -- AXI Full/Lite Master Write Channel (Read side) M_AXI_AWID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); M_AXI_AWADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0); M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_AWUSER : OUT std_logic_vector(C_AXI_AWUSER_WIDTH-1 DOWNTO 0); M_AXI_AWVALID : OUT std_logic; M_AXI_AWREADY : IN std_logic := '0'; M_AXI_WID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); M_AXI_WDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); M_AXI_WSTRB : OUT std_logic_vector(C_AXI_DATA_WIDTH/8-1 DOWNTO 0); M_AXI_WLAST : OUT std_logic; M_AXI_WUSER : OUT std_logic_vector(C_AXI_WUSER_WIDTH-1 DOWNTO 0); M_AXI_WVALID : OUT std_logic; M_AXI_WREADY : IN std_logic := '0'; M_AXI_BID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_BUSER : IN std_logic_vector(C_AXI_BUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_BVALID : IN std_logic := '0'; M_AXI_BREADY : OUT std_logic; -- AXI Full/Lite Slave Read Channel (Write side) S_AXI_ARID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARADDR : IN std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARUSER : IN std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXI_ARVALID : IN std_logic := '0'; S_AXI_ARREADY : OUT std_logic; S_AXI_RID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); S_AXI_RDATA : OUT std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0); S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0); S_AXI_RLAST : OUT std_logic; S_AXI_RUSER : OUT std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0); S_AXI_RVALID : OUT std_logic; S_AXI_RREADY : IN std_logic := '0'; -- AXI Full/Lite Master Read Channel (Read side) M_AXI_ARID : OUT std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0); M_AXI_ARADDR : OUT std_logic_vector(C_AXI_ADDR_WIDTH-1 DOWNTO 0); M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0); M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0); M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0); M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0); M_AXI_ARUSER : OUT std_logic_vector(C_AXI_ARUSER_WIDTH-1 DOWNTO 0); M_AXI_ARVALID : OUT std_logic; M_AXI_ARREADY : IN std_logic := '0'; M_AXI_RID : IN std_logic_vector(C_AXI_ID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RDATA : IN std_logic_vector(C_AXI_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RLAST : IN std_logic := '0'; M_AXI_RUSER : IN std_logic_vector(C_AXI_RUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_AXI_RVALID : IN std_logic := '0'; M_AXI_RREADY : OUT std_logic; -- AXI Streaming Slave Signals (Write side) S_AXIS_TVALID : IN std_logic := '0'; S_AXIS_TREADY : OUT std_logic; S_AXIS_TDATA : IN std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TSTRB : IN std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TKEEP : IN std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TLAST : IN std_logic := '0'; S_AXIS_TID : IN std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TDEST : IN std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); S_AXIS_TUSER : IN std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); -- AXI Streaming Master Signals (Read side) M_AXIS_TVALID : OUT std_logic; M_AXIS_TREADY : IN std_logic := '0'; M_AXIS_TDATA : OUT std_logic_vector(C_AXIS_TDATA_WIDTH-1 DOWNTO 0); M_AXIS_TSTRB : OUT std_logic_vector(C_AXIS_TSTRB_WIDTH-1 DOWNTO 0); M_AXIS_TKEEP : OUT std_logic_vector(C_AXIS_TKEEP_WIDTH-1 DOWNTO 0); M_AXIS_TLAST : OUT std_logic; M_AXIS_TID : OUT std_logic_vector(C_AXIS_TID_WIDTH-1 DOWNTO 0); M_AXIS_TDEST : OUT std_logic_vector(C_AXIS_TDEST_WIDTH-1 DOWNTO 0); M_AXIS_TUSER : OUT std_logic_vector(C_AXIS_TUSER_WIDTH-1 DOWNTO 0); -- AXI Full/Lite Write Address Channel Signals AXI_AW_INJECTSBITERR : IN std_logic := '0'; AXI_AW_INJECTDBITERR : IN std_logic := '0'; AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AW_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WACH DOWNTO 0); AXI_AW_SBITERR : OUT std_logic; AXI_AW_DBITERR : OUT std_logic; AXI_AW_OVERFLOW : OUT std_logic; AXI_AW_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Write Data Channel Signals AXI_W_INJECTSBITERR : IN std_logic := '0'; AXI_W_INJECTDBITERR : IN std_logic := '0'; AXI_W_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_W_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); AXI_W_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); AXI_W_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WDCH DOWNTO 0); AXI_W_SBITERR : OUT std_logic; AXI_W_DBITERR : OUT std_logic; AXI_W_OVERFLOW : OUT std_logic; AXI_W_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Write Response Channel Signals AXI_B_INJECTSBITERR : IN std_logic := '0'; AXI_B_INJECTDBITERR : IN std_logic := '0'; AXI_B_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_B_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); AXI_B_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); AXI_B_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_WRCH DOWNTO 0); AXI_B_SBITERR : OUT std_logic; AXI_B_DBITERR : OUT std_logic; AXI_B_OVERFLOW : OUT std_logic; AXI_B_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Read Address Channel Signals AXI_AR_INJECTSBITERR : IN std_logic := '0'; AXI_AR_INJECTDBITERR : IN std_logic := '0'; AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); AXI_AR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RACH DOWNTO 0); AXI_AR_SBITERR : OUT std_logic; AXI_AR_DBITERR : OUT std_logic; AXI_AR_OVERFLOW : OUT std_logic; AXI_AR_UNDERFLOW : OUT std_logic; -- AXI Full/Lite Read Data Channel Signals AXI_R_INJECTSBITERR : IN std_logic := '0'; AXI_R_INJECTDBITERR : IN std_logic := '0'; AXI_R_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); AXI_R_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); AXI_R_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); AXI_R_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_RDCH DOWNTO 0); AXI_R_SBITERR : OUT std_logic; AXI_R_DBITERR : OUT std_logic; AXI_R_OVERFLOW : OUT std_logic; AXI_R_UNDERFLOW : OUT std_logic; -- AXI Streaming FIFO Related Signals AXIS_INJECTSBITERR : IN std_logic := '0'; AXIS_INJECTDBITERR : IN std_logic := '0'; AXIS_PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); AXIS_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); AXIS_WR_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); AXIS_RD_DATA_COUNT : OUT std_logic_vector(C_WR_PNTR_WIDTH_AXIS DOWNTO 0); AXIS_SBITERR : OUT std_logic; AXIS_DBITERR : OUT std_logic; AXIS_OVERFLOW : OUT std_logic; AXIS_UNDERFLOW : OUT std_logic ); END fifo_generator_v8_2; ARCHITECTURE behavioral OF fifo_generator_v8_2 IS COMPONENT fifo_generator_v8_2_conv IS GENERIC ( --------------------------------------------------------------------------- -- Generic Declarations --------------------------------------------------------------------------- C_COMMON_CLOCK : integer := 0; C_COUNT_TYPE : integer := 0; --not used C_DATA_COUNT_WIDTH : integer := 2; C_DEFAULT_VALUE : string := ""; --not used C_DIN_WIDTH : integer := 8; C_DOUT_RST_VAL : string := ""; C_DOUT_WIDTH : integer := 8; C_ENABLE_RLOCS : integer := 0; --not used C_FAMILY : string := ""; --not used in bhv model C_FULL_FLAGS_RST_VAL : integer := 0; C_HAS_ALMOST_EMPTY : integer := 0; C_HAS_ALMOST_FULL : integer := 0; C_HAS_BACKUP : integer := 0; --not used C_HAS_DATA_COUNT : integer := 0; C_HAS_INT_CLK : integer := 0; --not used in bhv model C_HAS_MEMINIT_FILE : integer := 0; --not used C_HAS_OVERFLOW : integer := 0; C_HAS_RD_DATA_COUNT : integer := 0; C_HAS_RD_RST : integer := 0; --not used C_HAS_RST : integer := 1; C_HAS_SRST : integer := 0; C_HAS_UNDERFLOW : integer := 0; C_HAS_VALID : integer := 0; C_HAS_WR_ACK : integer := 0; C_HAS_WR_DATA_COUNT : integer := 0; C_HAS_WR_RST : integer := 0; --not used C_IMPLEMENTATION_TYPE : integer := 0; C_INIT_WR_PNTR_VAL : integer := 0; --not used C_MEMORY_TYPE : integer := 1; C_MIF_FILE_NAME : string := ""; --not used C_OPTIMIZATION_MODE : integer := 0; --not used C_OVERFLOW_LOW : integer := 0; C_PRELOAD_LATENCY : integer := 1; C_PRELOAD_REGS : integer := 0; C_PRIM_FIFO_TYPE : string := "4kx4"; --not used in bhv model C_PROG_EMPTY_THRESH_ASSERT_VAL: integer := 0; C_PROG_EMPTY_THRESH_NEGATE_VAL: integer := 0; C_PROG_EMPTY_TYPE : integer := 0; C_PROG_FULL_THRESH_ASSERT_VAL : integer := 0; C_PROG_FULL_THRESH_NEGATE_VAL : integer := 0; C_PROG_FULL_TYPE : integer := 0; C_RD_DATA_COUNT_WIDTH : integer := 2; C_RD_DEPTH : integer := 256; C_RD_FREQ : integer := 1; --not used in bhv model C_RD_PNTR_WIDTH : integer := 8; C_UNDERFLOW_LOW : integer := 0; C_USE_DOUT_RST : integer := 0; C_USE_ECC : integer := 0; C_USE_EMBEDDED_REG : integer := 0; C_USE_FIFO16_FLAGS : integer := 0; --not used in bhv model C_USE_FWFT_DATA_COUNT : integer := 0; C_VALID_LOW : integer := 0; C_WR_ACK_LOW : integer := 0; C_WR_DATA_COUNT_WIDTH : integer := 2; C_WR_DEPTH : integer := 256; C_WR_FREQ : integer := 1; --not used in bhv model C_WR_PNTR_WIDTH : integer := 8; C_WR_RESPONSE_LATENCY : integer := 1; --not used C_MSGON_VAL : integer := 1; --not used in bhv model C_ENABLE_RST_SYNC : integer := 1; C_ERROR_INJECTION_TYPE : integer := 0; C_FIFO_TYPE : integer := 0 ); PORT( -------------------------------------------------------------------------------- -- Input and Output Declarations -------------------------------------------------------------------------------- BACKUP : IN std_logic := '0'; BACKUP_MARKER : IN std_logic := '0'; CLK : IN std_logic := '0'; RST : IN std_logic := '0'; SRST : IN std_logic := '0'; WR_CLK : IN std_logic := '0'; WR_RST : IN std_logic := '0'; RD_CLK : IN std_logic := '0'; RD_RST : IN std_logic := '0'; DIN : IN std_logic_vector(C_DIN_WIDTH-1 DOWNTO 0); -- WR_EN : IN std_logic; --Mandatory input RD_EN : IN std_logic; --Mandatory input --Mandatory input PROG_EMPTY_THRESH : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_ASSERT : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_EMPTY_THRESH_NEGATE : IN std_logic_vector(C_RD_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_ASSERT : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); PROG_FULL_THRESH_NEGATE : IN std_logic_vector(C_WR_PNTR_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); INT_CLK : IN std_logic := '0'; INJECTDBITERR : IN std_logic := '0'; INJECTSBITERR : IN std_logic := '0'; DOUT : OUT std_logic_vector(C_DOUT_WIDTH-1 DOWNTO 0); FULL : OUT std_logic; ALMOST_FULL : OUT std_logic; WR_ACK : OUT std_logic; OVERFLOW : OUT std_logic; EMPTY : OUT std_logic; ALMOST_EMPTY : OUT std_logic; VALID : OUT std_logic; UNDERFLOW : OUT std_logic; DATA_COUNT : OUT std_logic_vector(C_DATA_COUNT_WIDTH-1 DOWNTO 0); RD_DATA_COUNT : OUT std_logic_vector(C_RD_DATA_COUNT_WIDTH-1 DOWNTO 0); WR_DATA_COUNT : OUT std_logic_vector(C_WR_DATA_COUNT_WIDTH-1 DOWNTO 0); PROG_FULL : OUT std_logic; PROG_EMPTY : OUT std_logic; SBITERR : OUT std_logic := '0'; DBITERR : OUT std_logic := '0' ); END COMPONENT; COMPONENT fifo_generator_v8_2_axic_reg_slice IS GENERIC ( C_FAMILY : string := ""; C_DATA_WIDTH : integer := 32; C_REG_CONFIG : integer := 0 ); PORT ( -- System Signals ACLK : IN STD_LOGIC; ARESET : IN STD_LOGIC; -- Slave side S_PAYLOAD_DATA : IN STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0); S_VALID : IN STD_LOGIC; S_READY : OUT STD_LOGIC := '0'; -- Master side M_PAYLOAD_DATA : OUT STD_LOGIC_VECTOR(C_DATA_WIDTH-1 DOWNTO 0) := (OTHERS => '0'); M_VALID : OUT STD_LOGIC := '0'; M_READY : IN STD_LOGIC ); END COMPONENT; CONSTANT C_AXI_LEN_WIDTH : integer := 8; CONSTANT C_AXI_SIZE_WIDTH : integer := 3; CONSTANT C_AXI_BURST_WIDTH : integer := 2; CONSTANT C_AXI_LOCK_WIDTH : integer := 2; CONSTANT C_AXI_CACHE_WIDTH : integer := 4; CONSTANT C_AXI_PROT_WIDTH : integer := 3; CONSTANT C_AXI_QOS_WIDTH : integer := 4; CONSTANT C_AXI_REGION_WIDTH : integer := 4; CONSTANT C_AXI_BRESP_WIDTH : integer := 2; CONSTANT C_AXI_RRESP_WIDTH : integer := 2; ----------------------------------------------------------------------------- -- FUNCTION if_then_else -- Returns a true case or flase case based on the condition ------------------------------------------------------------------------------- FUNCTION if_then_else ( condition : boolean; true_case : integer; false_case : integer) RETURN integer IS VARIABLE retval : integer := 0; BEGIN IF NOT condition THEN retval:=false_case; ELSE retval:=true_case; END IF; RETURN retval; END if_then_else; ------------------------------------------------------------------------------ -- This function is used to implement an IF..THEN when such a statement is not -- allowed and returns string. ------------------------------------------------------------------------------ FUNCTION if_then_else ( condition : boolean; true_case : string; false_case : string) RETURN string IS BEGIN IF NOT condition THEN RETURN false_case; ELSE RETURN true_case; END IF; END if_then_else; -------------------------------------------------------- -- FUNCION : map_ready_valid -- Returns the READY signal that is mapped out of FULL or ALMOST_FULL or PROG_FULL -- Returns the VALID signal that is mapped out of EMPTY or ALMOST_EMPTY or PROG_EMPTY -------------------------------------------------------- FUNCTION map_ready_valid( pf_pe_type : integer; full_empty : std_logic; af_ae : std_logic; pf_pe : std_logic) RETURN std_logic IS BEGIN IF (pf_pe_type = 5) THEN RETURN NOT full_empty; ELSIF (pf_pe_type = 6) THEN RETURN NOT af_ae; ELSE RETURN NOT pf_pe; END IF; END map_ready_valid; SIGNAL inverted_reset : std_logic := '0'; BEGIN inverted_reset <= NOT S_ARESETN; --------------------------------------------------------------------------- -- Top level instance for Conventional FIFO. --------------------------------------------------------------------------- gconvfifo: IF (C_INTERFACE_TYPE = 0) GENERATE inst_conv_fifo: fifo_generator_v8_2_conv GENERIC map( C_COMMON_CLOCK => C_COMMON_CLOCK, C_COUNT_TYPE => C_COUNT_TYPE, C_DATA_COUNT_WIDTH => C_DATA_COUNT_WIDTH, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_DIN_WIDTH => C_DIN_WIDTH, C_DOUT_RST_VAL => if_then_else(C_USE_DOUT_RST = 1, C_DOUT_RST_VAL, "0"), C_DOUT_WIDTH => C_DOUT_WIDTH, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_FAMILY => C_FAMILY, C_FULL_FLAGS_RST_VAL => C_FULL_FLAGS_RST_VAL, C_HAS_ALMOST_EMPTY => C_HAS_ALMOST_EMPTY, C_HAS_ALMOST_FULL => C_HAS_ALMOST_FULL, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_DATA_COUNT => C_HAS_DATA_COUNT, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_HAS_RD_DATA_COUNT => C_HAS_RD_DATA_COUNT, C_HAS_RD_RST => C_HAS_RD_RST, C_HAS_RST => C_HAS_RST, C_HAS_SRST => C_HAS_SRST, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_HAS_VALID => C_HAS_VALID, C_HAS_WR_ACK => C_HAS_WR_ACK, C_HAS_WR_DATA_COUNT => C_HAS_WR_DATA_COUNT, C_HAS_WR_RST => C_HAS_WR_RST, C_IMPLEMENTATION_TYPE => C_IMPLEMENTATION_TYPE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MEMORY_TYPE => C_MEMORY_TYPE, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_PRELOAD_LATENCY => C_PRELOAD_LATENCY, C_PRELOAD_REGS => C_PRELOAD_REGS, C_PRIM_FIFO_TYPE => C_PRIM_FIFO_TYPE, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL, C_PROG_EMPTY_THRESH_NEGATE_VAL => C_PROG_EMPTY_THRESH_NEGATE_VAL, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL, C_PROG_FULL_THRESH_NEGATE_VAL => C_PROG_FULL_THRESH_NEGATE_VAL, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE, C_RD_DATA_COUNT_WIDTH => C_RD_DATA_COUNT_WIDTH, C_RD_DEPTH => C_RD_DEPTH, C_RD_FREQ => C_RD_FREQ, C_RD_PNTR_WIDTH => C_RD_PNTR_WIDTH, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_USE_DOUT_RST => C_USE_DOUT_RST, C_USE_ECC => C_USE_ECC, C_USE_EMBEDDED_REG => C_USE_EMBEDDED_REG, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_USE_FWFT_DATA_COUNT => C_USE_FWFT_DATA_COUNT, C_VALID_LOW => C_VALID_LOW, C_WR_ACK_LOW => C_WR_ACK_LOW, C_WR_DATA_COUNT_WIDTH => C_WR_DATA_COUNT_WIDTH, C_WR_DEPTH => C_WR_DEPTH, C_WR_FREQ => C_WR_FREQ, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => C_ENABLE_RST_SYNC, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE, -- Enable Distributed RAM Low latency FIFO for FWFT Built-in FIFO, otherwise use Distributed RAM C_FIFO_TYPE => if_then_else((C_PRELOAD_LATENCY /= 0 AND C_MEMORY_TYPE = 4), 1,if_then_else((C_IMPLEMENTATION_TYPE > 2), 2, 0)) ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, CLK => CLK, RST => RST, SRST => SRST, WR_CLK => WR_CLK, WR_RST => WR_RST, RD_CLK => RD_CLK, RD_RST => RD_RST, DIN => DIN, WR_EN => WR_EN, RD_EN => RD_EN, PROG_EMPTY_THRESH => PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => PROG_EMPTY_THRESH_ASSERT, PROG_EMPTY_THRESH_NEGATE => PROG_EMPTY_THRESH_NEGATE, PROG_FULL_THRESH => PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => PROG_FULL_THRESH_ASSERT, PROG_FULL_THRESH_NEGATE => PROG_FULL_THRESH_NEGATE, INT_CLK => INT_CLK, INJECTDBITERR => INJECTDBITERR, INJECTSBITERR => INJECTSBITERR, --Outputs DOUT => DOUT, FULL => FULL, ALMOST_FULL => ALMOST_FULL, WR_ACK => WR_ACK, OVERFLOW => OVERFLOW, EMPTY => EMPTY, ALMOST_EMPTY => ALMOST_EMPTY, VALID => VALID, UNDERFLOW => UNDERFLOW, DATA_COUNT => DATA_COUNT, RD_DATA_COUNT => RD_DATA_COUNT, WR_DATA_COUNT => WR_DATA_COUNT, PROG_FULL => PROG_FULL, PROG_EMPTY => PROG_EMPTY, SBITERR => SBITERR, DBITERR => DBITERR ); END GENERATE gconvfifo; -- End of conventional FIFO --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Top level instance for ramfifo in AXI Streaming FIFO core. It implements: -- * BRAM based FIFO -- * Dist RAM based FIFO --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- gaxis_fifo: IF ((C_INTERFACE_TYPE = 1) AND (C_AXI_TYPE = 0) AND (C_AXIS_TYPE < 2)) GENERATE SIGNAL axis_din : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL axis_dout : std_logic_vector(C_DIN_WIDTH_AXIS-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL axis_full : std_logic := '0'; SIGNAL axis_almost_full : std_logic := '0'; SIGNAL axis_prog_full : std_logic := '0'; SIGNAL axis_empty : std_logic := '0'; SIGNAL axis_almost_empty : std_logic := '0'; SIGNAL axis_prog_empty : std_logic := '0'; SIGNAL axis_s_axis_tready : std_logic := '0'; SIGNAL axis_m_axis_tvalid : std_logic := '0'; SIGNAL axis_wr_en : std_logic := '0'; SIGNAL axis_rd_en : std_logic := '0'; CONSTANT TDATA_OFFSET : integer := if_then_else(C_HAS_AXIS_TDATA = 1,C_DIN_WIDTH_AXIS-C_AXIS_TDATA_WIDTH,C_DIN_WIDTH_AXIS); CONSTANT TSTRB_OFFSET : integer := if_then_else(C_HAS_AXIS_TSTRB = 1,TDATA_OFFSET-C_AXIS_TSTRB_WIDTH,TDATA_OFFSET); CONSTANT TKEEP_OFFSET : integer := if_then_else(C_HAS_AXIS_TKEEP = 1,TSTRB_OFFSET-C_AXIS_TKEEP_WIDTH,TSTRB_OFFSET); CONSTANT TID_OFFSET : integer := if_then_else(C_HAS_AXIS_TID = 1,TKEEP_OFFSET-C_AXIS_TID_WIDTH,TKEEP_OFFSET); CONSTANT TDEST_OFFSET : integer := if_then_else(C_HAS_AXIS_TDEST = 1,TID_OFFSET-C_AXIS_TDEST_WIDTH,TID_OFFSET); CONSTANT TUSER_OFFSET : integer := if_then_else(C_HAS_AXIS_TUSER = 1,TDEST_OFFSET-C_AXIS_TUSER_WIDTH,TDEST_OFFSET); BEGIN -- Generate the DIN to FIFO by concatinating the AXIS optional ports gdin1: IF (C_HAS_AXIS_TDATA = 1) GENERATE axis_din(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET) <= S_AXIS_TDATA; M_AXIS_TDATA <= axis_dout(C_DIN_WIDTH_AXIS-1 DOWNTO TDATA_OFFSET); END GENERATE gdin1; gdin2: IF (C_HAS_AXIS_TSTRB = 1) GENERATE axis_din(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET) <= S_AXIS_TSTRB; M_AXIS_TSTRB <= axis_dout(TDATA_OFFSET-1 DOWNTO TSTRB_OFFSET); END GENERATE gdin2; gdin3: IF (C_HAS_AXIS_TKEEP = 1) GENERATE axis_din(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET) <= S_AXIS_TKEEP; M_AXIS_TKEEP <= axis_dout(TSTRB_OFFSET-1 DOWNTO TKEEP_OFFSET); END GENERATE gdin3; gdin4: IF (C_HAS_AXIS_TID = 1) GENERATE axis_din(TKEEP_OFFSET-1 DOWNTO TID_OFFSET) <= S_AXIS_TID; M_AXIS_TID <= axis_dout(TKEEP_OFFSET-1 DOWNTO TID_OFFSET); END GENERATE gdin4; gdin5: IF (C_HAS_AXIS_TDEST = 1) GENERATE axis_din(TID_OFFSET-1 DOWNTO TDEST_OFFSET) <= S_AXIS_TDEST; M_AXIS_TDEST <= axis_dout(TID_OFFSET-1 DOWNTO TDEST_OFFSET); END GENERATE gdin5; gdin6: IF (C_HAS_AXIS_TUSER = 1) GENERATE axis_din(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET) <= S_AXIS_TUSER; M_AXIS_TUSER <= axis_dout(TDEST_OFFSET-1 DOWNTO TUSER_OFFSET); END GENERATE gdin6; gdin7: IF (C_HAS_AXIS_TLAST = 1) GENERATE axis_din(0) <= S_AXIS_TLAST; M_AXIS_TLAST <= axis_dout(0); END GENERATE gdin7; -- Write protection -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gaxis_wr_en1: IF (C_PROG_FULL_TYPE_AXIS = 5) GENERATE axis_wr_en <= S_AXIS_TVALID; END GENERATE gaxis_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gaxis_wr_en2: IF (C_PROG_FULL_TYPE_AXIS /= 5) GENERATE axis_wr_en <= axis_s_axis_tready AND S_AXIS_TVALID; END GENERATE gaxis_wr_en2; -- Read protection -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gaxis_rd_en1: IF (C_PROG_EMPTY_TYPE_AXIS = 5) GENERATE axis_rd_en <= M_AXIS_TREADY; END GENERATE gaxis_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gaxis_rd_en2: IF (C_PROG_EMPTY_TYPE_AXIS /= 5) GENERATE axis_rd_en <= axis_m_axis_tvalid AND M_AXIS_TREADY; END GENERATE gaxis_rd_en2; gaxisf: IF (C_AXIS_TYPE = 0) GENERATE axisf : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS = 1 OR C_IMPLEMENTATION_TYPE_AXIS = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_AXIS <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_AXIS, C_WR_DEPTH => C_WR_DEPTH_AXIS, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS, C_DOUT_WIDTH => C_DIN_WIDTH_AXIS, C_RD_DEPTH => C_WR_DEPTH_AXIS, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_AXIS, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_AXIS, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_AXIS, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_AXIS, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS, C_USE_ECC => C_USE_ECC_AXIS, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_AXIS, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_AXIS = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_AXIS = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_AXIS, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => C_HAS_SLAVE_CE, -- C_USE_OUTPUT_CE => C_HAS_MASTER_CE, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => 0, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => 0, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_AXIS = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_AXIS+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => axis_wr_en,--S_AXIS_TVALID, RD_EN => axis_rd_en,--M_AXIS_TREADY, PROG_FULL_THRESH => AXIS_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXIS_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXIS_INJECTDBITERR, INJECTSBITERR => AXIS_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => S_ACLK_EN, -- OUTPUT_CE => M_ACLK_EN, -- END_OF_PACKET => '0', -- BYTE_STROBE => (OTHERS => '0'), DIN => axis_din, DOUT => axis_dout, FULL => axis_full, ALMOST_FULL => axis_almost_full, PROG_FULL => axis_prog_full, EMPTY => axis_empty, ALMOST_EMPTY => axis_almost_empty, PROG_EMPTY => axis_prog_empty, WR_ACK => OPEN, OVERFLOW => AXIS_OVERFLOW, VALID => OPEN, UNDERFLOW => AXIS_UNDERFLOW, DATA_COUNT => AXIS_DATA_COUNT, RD_DATA_COUNT => AXIS_RD_DATA_COUNT, WR_DATA_COUNT => AXIS_WR_DATA_COUNT, SBITERR => AXIS_SBITERR, DBITERR => AXIS_DBITERR ); axis_s_axis_tready <= map_ready_valid(C_PROG_FULL_TYPE_AXIS,axis_full,axis_almost_full,axis_prog_full); axis_m_axis_tvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_AXIS,axis_empty,axis_almost_empty,axis_prog_empty); S_AXIS_TREADY <= axis_s_axis_tready;--map_ready_valid(C_PROG_FULL_TYPE_AXIS,axis_full,axis_almost_full,axis_prog_full); M_AXIS_TVALID <= axis_m_axis_tvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_AXIS,axis_empty,axis_almost_empty,axis_prog_empty); END GENERATE gaxisf; -- Register Slice for AXI Streaming gaxis_reg_slice: IF (C_AXIS_TYPE = 1) GENERATE axis_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_AXIS, C_REG_CONFIG => C_REG_SLICE_MODE_AXIS ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => axis_din, S_VALID => S_AXIS_TVALID, S_READY => S_AXIS_TREADY, -- Master side M_PAYLOAD_DATA => axis_dout, M_VALID => M_AXIS_TVALID, M_READY => M_AXIS_TREADY ); END GENERATE gaxis_reg_slice; END GENERATE gaxis_fifo; gaxifull: IF (C_INTERFACE_TYPE = 1) AND (C_AXI_TYPE /= 0) GENERATE SIGNAL axi_rd_underflow_i : std_logic := '0'; SIGNAL axi_rd_overflow_i : std_logic := '0'; SIGNAL axi_wr_underflow_i : std_logic := '0'; SIGNAL axi_wr_overflow_i : std_logic := '0'; BEGIN gwrch: IF (C_HAS_AXI_WR_CHANNEL = 1) GENERATE SIGNAL wach_din : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wach_dout : std_logic_vector(C_DIN_WIDTH_WACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wach_full : std_logic := '0'; SIGNAL wach_almost_full : std_logic := '0'; SIGNAL wach_prog_full : std_logic := '0'; SIGNAL wach_empty : std_logic := '0'; SIGNAL wach_almost_empty : std_logic := '0'; SIGNAL wach_prog_empty : std_logic := '0'; SIGNAL wdch_din : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wdch_dout : std_logic_vector(C_DIN_WIDTH_WDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wdch_full : std_logic := '0'; SIGNAL wdch_almost_full : std_logic := '0'; SIGNAL wdch_prog_full : std_logic := '0'; SIGNAL wdch_empty : std_logic := '0'; SIGNAL wdch_almost_empty : std_logic := '0'; SIGNAL wdch_prog_empty : std_logic := '0'; SIGNAL wrch_din : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wrch_dout : std_logic_vector(C_DIN_WIDTH_WRCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL wrch_full : std_logic := '0'; SIGNAL wrch_almost_full : std_logic := '0'; SIGNAL wrch_prog_full : std_logic := '0'; SIGNAL wrch_empty : std_logic := '0'; SIGNAL wrch_almost_empty : std_logic := '0'; SIGNAL wrch_prog_empty : std_logic := '0'; SIGNAL axi_aw_underflow_i : std_logic := '0'; SIGNAL axi_w_underflow_i : std_logic := '0'; SIGNAL axi_b_underflow_i : std_logic := '0'; SIGNAL axi_aw_overflow_i : std_logic := '0'; SIGNAL axi_w_overflow_i : std_logic := '0'; SIGNAL axi_b_overflow_i : std_logic := '0'; SIGNAL wach_s_axi_awready : std_logic := '0'; SIGNAL wach_m_axi_awvalid : std_logic := '0'; SIGNAL wach_wr_en : std_logic := '0'; SIGNAL wach_rd_en : std_logic := '0'; SIGNAL wdch_s_axi_wready : std_logic := '0'; SIGNAL wdch_m_axi_wvalid : std_logic := '0'; SIGNAL wdch_wr_en : std_logic := '0'; SIGNAL wdch_rd_en : std_logic := '0'; SIGNAL wrch_s_axi_bvalid : std_logic := '0'; SIGNAL wrch_m_axi_bready : std_logic := '0'; SIGNAL wrch_wr_en : std_logic := '0'; SIGNAL wrch_rd_en : std_logic := '0'; CONSTANT AWID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WACH); CONSTANT AWADDR_OFFSET : integer := AWID_OFFSET - C_AXI_ADDR_WIDTH; CONSTANT AWLEN_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWADDR_OFFSET - C_AXI_LEN_WIDTH,AWADDR_OFFSET); CONSTANT AWSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWLEN_OFFSET - C_AXI_SIZE_WIDTH,AWLEN_OFFSET); CONSTANT AWBURST_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWSIZE_OFFSET - C_AXI_BURST_WIDTH,AWSIZE_OFFSET); CONSTANT AWLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWBURST_OFFSET - C_AXI_LOCK_WIDTH,AWBURST_OFFSET); CONSTANT AWCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,AWLOCK_OFFSET - C_AXI_CACHE_WIDTH,AWLOCK_OFFSET); CONSTANT AWPROT_OFFSET : integer := AWCACHE_OFFSET - C_AXI_PROT_WIDTH; CONSTANT AWQOS_OFFSET : integer := AWPROT_OFFSET - C_AXI_QOS_WIDTH; CONSTANT AWREGION_OFFSET : integer := AWQOS_OFFSET - C_AXI_REGION_WIDTH; CONSTANT AWUSER_OFFSET : integer := if_then_else(C_HAS_AXI_AWUSER = 1,AWREGION_OFFSET-C_AXI_AWUSER_WIDTH,AWREGION_OFFSET); CONSTANT WID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WDCH); CONSTANT WDATA_OFFSET : integer := WID_OFFSET - C_AXI_DATA_WIDTH; CONSTANT WSTRB_OFFSET : integer := WDATA_OFFSET - C_AXI_DATA_WIDTH/8; CONSTANT WUSER_OFFSET : integer := if_then_else(C_HAS_AXI_WUSER = 1,WSTRB_OFFSET-C_AXI_WUSER_WIDTH,WSTRB_OFFSET); CONSTANT BID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_WRCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_WRCH); CONSTANT BRESP_OFFSET : integer := BID_OFFSET - C_AXI_BRESP_WIDTH; CONSTANT BUSER_OFFSET : integer := if_then_else(C_HAS_AXI_BUSER = 1,BRESP_OFFSET-C_AXI_BUSER_WIDTH,BRESP_OFFSET); BEGIN -- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports axi_full_din_wr_ch: IF (C_AXI_TYPE = 1) GENERATE gwach1: IF (C_WACH_TYPE < 2) GENERATE gwach_din1: IF (C_HAS_AXI_AWUSER = 1) GENERATE wach_din <= S_AXI_AWID & S_AXI_AWADDR & S_AXI_AWLEN & S_AXI_AWSIZE & S_AXI_AWBURST & S_AXI_AWLOCK & S_AXI_AWCACHE & S_AXI_AWPROT & S_AXI_AWQOS & S_AXI_AWREGION & S_AXI_AWUSER; M_AXI_AWUSER <= wach_dout(AWREGION_OFFSET-1 DOWNTO AWUSER_OFFSET); END GENERATE gwach_din1; gwach_din2: IF (C_HAS_AXI_AWUSER = 0) GENERATE wach_din <= S_AXI_AWID & S_AXI_AWADDR & S_AXI_AWLEN & S_AXI_AWSIZE & S_AXI_AWBURST & S_AXI_AWLOCK & S_AXI_AWCACHE & S_AXI_AWPROT & S_AXI_AWQOS & S_AXI_AWREGION; M_AXI_AWUSER <= (OTHERS => '0'); END GENERATE gwach_din2; M_AXI_AWID <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWID_OFFSET); M_AXI_AWADDR <= wach_dout(AWID_OFFSET-1 DOWNTO AWADDR_OFFSET); M_AXI_AWLEN <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWLEN_OFFSET); M_AXI_AWSIZE <= wach_dout(AWLEN_OFFSET-1 DOWNTO AWSIZE_OFFSET); M_AXI_AWBURST <= wach_dout(AWSIZE_OFFSET-1 DOWNTO AWBURST_OFFSET); M_AXI_AWLOCK <= wach_dout(AWBURST_OFFSET-1 DOWNTO AWLOCK_OFFSET); M_AXI_AWCACHE <= wach_dout(AWLOCK_OFFSET-1 DOWNTO AWCACHE_OFFSET); M_AXI_AWPROT <= wach_dout(AWCACHE_OFFSET-1 DOWNTO AWPROT_OFFSET); M_AXI_AWQOS <= wach_dout(AWPROT_OFFSET-1 DOWNTO AWQOS_OFFSET); M_AXI_AWREGION <= wach_dout(AWQOS_OFFSET-1 DOWNTO AWREGION_OFFSET); END GENERATE gwach1; -- Generate the DIN to FIFO by concatinating the AXI Full Write Data Channel optional ports gwdch1: IF (C_WDCH_TYPE < 2) GENERATE gwdch_din1: IF (C_HAS_AXI_WUSER = 1) GENERATE wdch_din <= S_AXI_WID & S_AXI_WDATA & S_AXI_WSTRB & S_AXI_WUSER & S_AXI_WLAST; M_AXI_WLAST <= wdch_dout(0); M_AXI_WUSER <= wdch_dout(WSTRB_OFFSET-1 DOWNTO WUSER_OFFSET); END GENERATE gwdch_din1; gwdch_din2: IF (C_HAS_AXI_WUSER = 0) GENERATE wdch_din <= S_AXI_WID & S_AXI_WDATA & S_AXI_WSTRB & S_AXI_WLAST; M_AXI_WLAST <= wdch_dout(0); M_AXI_WUSER <= (OTHERS => '0'); END GENERATE gwdch_din2; M_AXI_WID <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WID_OFFSET); M_AXI_WDATA <= wdch_dout(WID_OFFSET-1 DOWNTO WDATA_OFFSET); M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET); END GENERATE gwdch1; -- Generate the DIN to FIFO by concatinating the AXI Full Write Response Channel optional ports gwrch1: IF (C_WRCH_TYPE < 2) GENERATE gwrch_din1: IF (C_HAS_AXI_BUSER = 1) GENERATE wrch_din <= M_AXI_BID & M_AXI_BRESP & M_AXI_BUSER; S_AXI_BUSER <= wrch_dout(BRESP_OFFSET-1 DOWNTO BUSER_OFFSET); END GENERATE gwrch_din1; gwrch_din2: IF (C_HAS_AXI_BUSER = 0) GENERATE wrch_din <= M_AXI_BID & M_AXI_BRESP; S_AXI_BUSER <= (OTHERS => '0'); END GENERATE gwrch_din2; S_AXI_BID <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BID_OFFSET); S_AXI_BRESP <= wrch_dout(BID_OFFSET-1 DOWNTO BRESP_OFFSET); END GENERATE gwrch1; END GENERATE axi_full_din_wr_ch; -- Form the DIN to FIFO by concatinating the AXI Lite Write Address Channel optional ports axi_lite_din_wr_ch: IF (C_AXI_TYPE = 2) GENERATE gwach1: IF (C_WACH_TYPE < 2) GENERATE wach_din <= S_AXI_AWADDR & S_AXI_AWPROT; M_AXI_AWADDR <= wach_dout(C_DIN_WIDTH_WACH-1 DOWNTO AWADDR_OFFSET); M_AXI_AWPROT <= wach_dout(AWADDR_OFFSET-1 DOWNTO AWPROT_OFFSET); END GENERATE gwach1; gwdch1: IF (C_WDCH_TYPE < 2) GENERATE wdch_din <= S_AXI_WDATA & S_AXI_WSTRB; M_AXI_WDATA <= wdch_dout(C_DIN_WIDTH_WDCH-1 DOWNTO WDATA_OFFSET); M_AXI_WSTRB <= wdch_dout(WDATA_OFFSET-1 DOWNTO WSTRB_OFFSET); END GENERATE gwdch1; gwrch1: IF (C_WRCH_TYPE < 2) GENERATE wrch_din <= M_AXI_BRESP; S_AXI_BRESP <= wrch_dout(C_DIN_WIDTH_WRCH-1 DOWNTO BRESP_OFFSET); END GENERATE gwrch1; END GENERATE axi_lite_din_wr_ch; -- Write protection for Write Address Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gwach_wr_en1: IF (C_PROG_FULL_TYPE_WACH = 5) GENERATE wach_wr_en <= S_AXI_AWVALID; END GENERATE gwach_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gwach_wr_en2: IF (C_PROG_FULL_TYPE_WACH /= 5) GENERATE wach_wr_en <= wach_s_axi_awready AND S_AXI_AWVALID; END GENERATE gwach_wr_en2; -- Write protection for Write Data Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gwdch_wr_en1: IF (C_PROG_FULL_TYPE_WDCH = 5) GENERATE wdch_wr_en <= S_AXI_WVALID; END GENERATE gwdch_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gwdch_wr_en2: IF (C_PROG_FULL_TYPE_WDCH /= 5) GENERATE wdch_wr_en <= wdch_s_axi_wready AND S_AXI_WVALID; END GENERATE gwdch_wr_en2; -- Write protection for Write Response Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt gwrch_wr_en1: IF (C_PROG_FULL_TYPE_WRCH = 5) GENERATE wrch_wr_en <= M_AXI_BVALID; END GENERATE gwrch_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL gwrch_wr_en2: IF (C_PROG_FULL_TYPE_WRCH /= 5) GENERATE wrch_wr_en <= wrch_m_axi_bready AND M_AXI_BVALID; END GENERATE gwrch_wr_en2; -- Read protection for Write Address Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gwach_rd_en1: IF (C_PROG_EMPTY_TYPE_WACH = 5) GENERATE wach_rd_en <= M_AXI_AWREADY; END GENERATE gwach_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gwach_rd_en2: IF (C_PROG_EMPTY_TYPE_WACH /= 5) GENERATE wach_rd_en <= wach_m_axi_awvalid AND M_AXI_AWREADY; END GENERATE gwach_rd_en2; -- Read protection for Write Data Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gwdch_rd_en1: IF (C_PROG_EMPTY_TYPE_WDCH = 5) GENERATE wdch_rd_en <= M_AXI_WREADY; END GENERATE gwdch_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gwdch_rd_en2: IF (C_PROG_EMPTY_TYPE_WDCH /= 5) GENERATE wdch_rd_en <= wdch_m_axi_wvalid AND M_AXI_WREADY; END GENERATE gwdch_rd_en2; -- Read protection for Write Response Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt gwrch_rd_en1: IF (C_PROG_EMPTY_TYPE_WRCH = 5) GENERATE wrch_rd_en <= S_AXI_BREADY; END GENERATE gwrch_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY gwrch_rd_en2: IF (C_PROG_EMPTY_TYPE_WRCH /= 5) GENERATE wrch_rd_en <= wrch_s_axi_bvalid AND S_AXI_BREADY; END GENERATE gwrch_rd_en2; gwach2: IF (C_WACH_TYPE = 0) GENERATE axi_wach : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH = 1 OR C_IMPLEMENTATION_TYPE_WACH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WACH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_WACH, C_WR_DEPTH => C_WR_DEPTH_WACH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH, C_DOUT_WIDTH => C_DIN_WIDTH_WACH, C_RD_DEPTH => C_WR_DEPTH_WACH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WACH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WACH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WACH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WACH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH, C_USE_ECC => C_USE_ECC_WACH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WACH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WACH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WACH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_WACH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WACH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WACH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => wach_wr_en,--S_AXI_AWVALID, RD_EN => wach_rd_en,--M_AXI_AWREADY, PROG_FULL_THRESH => AXI_AW_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_AW_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_AW_INJECTDBITERR, INJECTSBITERR => AXI_AW_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_AW_INPUT_CE, -- OUTPUT_CE => AXI_AW_OUTPUT_CE, -- END_OF_PACKET => AXI_AW_END_OF_PACKET, -- BYTE_STROBE => AXI_AW_BYTE_STROBE, DIN => wach_din, DOUT => wach_dout, FULL => wach_full, ALMOST_FULL => wach_almost_full, PROG_FULL => wach_prog_full, EMPTY => wach_empty, ALMOST_EMPTY => wach_almost_empty, PROG_EMPTY => wach_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_aw_overflow_i, VALID => OPEN, UNDERFLOW => axi_aw_underflow_i, DATA_COUNT => AXI_AW_DATA_COUNT, RD_DATA_COUNT => AXI_AW_RD_DATA_COUNT, WR_DATA_COUNT => AXI_AW_WR_DATA_COUNT, SBITERR => AXI_AW_SBITERR, DBITERR => AXI_AW_DBITERR ); wach_s_axi_awready <= map_ready_valid(C_PROG_FULL_TYPE_WACH,wach_full,wach_almost_full,wach_prog_full); wach_m_axi_awvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WACH,wach_empty,wach_almost_empty,wach_prog_empty); S_AXI_AWREADY <= wach_s_axi_awready;--map_ready_valid(C_PROG_FULL_TYPE_WACH,wach_full,wach_almost_full,wach_prog_full); M_AXI_AWVALID <= wach_m_axi_awvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WACH,wach_empty,wach_almost_empty,wach_prog_empty); gaxi_wr_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_AW_UNDERFLOW <= axi_aw_underflow_i; END GENERATE gaxi_wr_ch_uf1; gaxi_wr_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_AW_OVERFLOW <= axi_aw_overflow_i; END GENERATE gaxi_wr_ch_of1; END GENERATE gwach2; -- Register Slice for Write Address Channel gwach_reg_slice: IF (C_WACH_TYPE = 1) GENERATE wach_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_WACH, C_REG_CONFIG => C_REG_SLICE_MODE_WACH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => wach_din, S_VALID => S_AXI_AWVALID, S_READY => S_AXI_AWREADY, -- Master side M_PAYLOAD_DATA => wach_dout, M_VALID => M_AXI_AWVALID, M_READY => M_AXI_AWREADY ); END GENERATE gwach_reg_slice; gwdch2: IF (C_WDCH_TYPE = 0) GENERATE axi_wdch : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH = 1 OR C_IMPLEMENTATION_TYPE_WDCH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WDCH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_WDCH, C_WR_DEPTH => C_WR_DEPTH_WDCH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH, C_DOUT_WIDTH => C_DIN_WIDTH_WDCH, C_RD_DEPTH => C_WR_DEPTH_WDCH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WDCH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WDCH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WDCH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WDCH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH, C_USE_ECC => C_USE_ECC_WDCH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WDCH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WDCH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WDCH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_WDCH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WDCH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WDCH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => wdch_wr_en,--S_AXI_WVALID, RD_EN => wdch_rd_en,--M_AXI_WREADY, PROG_FULL_THRESH => AXI_W_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_W_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_W_INJECTDBITERR, INJECTSBITERR => AXI_W_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_W_INPUT_CE, -- OUTPUT_CE => AXI_W_OUTPUT_CE, -- END_OF_PACKET => AXI_W_END_OF_PACKET, -- BYTE_STROBE => AXI_W_BYTE_STROBE, DIN => wdch_din, DOUT => wdch_dout, FULL => wdch_full, ALMOST_FULL => wdch_almost_full, PROG_FULL => wdch_prog_full, EMPTY => wdch_empty, ALMOST_EMPTY => wdch_almost_empty, PROG_EMPTY => wdch_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_w_overflow_i, VALID => OPEN, UNDERFLOW => axi_w_underflow_i, DATA_COUNT => AXI_W_DATA_COUNT, RD_DATA_COUNT => AXI_W_RD_DATA_COUNT, WR_DATA_COUNT => AXI_W_WR_DATA_COUNT, SBITERR => AXI_W_SBITERR, DBITERR => AXI_W_DBITERR ); wdch_s_axi_wready <= map_ready_valid(C_PROG_FULL_TYPE_WDCH,wdch_full,wdch_almost_full,wdch_prog_full); wdch_m_axi_wvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WDCH,wdch_empty,wdch_almost_empty,wdch_prog_empty); S_AXI_WREADY <= wdch_s_axi_wready;--map_ready_valid(C_PROG_FULL_TYPE_WDCH,wdch_full,wdch_almost_full,wdch_prog_full); M_AXI_WVALID <= wdch_m_axi_wvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WDCH,wdch_empty,wdch_almost_empty,wdch_prog_empty); gaxi_wr_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_W_UNDERFLOW <= axi_w_underflow_i; END GENERATE gaxi_wr_ch_uf2; gaxi_wr_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_W_OVERFLOW <= axi_w_overflow_i; END GENERATE gaxi_wr_ch_of2; END GENERATE gwdch2; -- Register Slice for Write Data Channel gwdch_reg_slice: IF (C_WDCH_TYPE = 1) GENERATE wdch_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_WDCH, C_REG_CONFIG => C_REG_SLICE_MODE_WDCH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => wdch_din, S_VALID => S_AXI_WVALID, S_READY => S_AXI_WREADY, -- Master side M_PAYLOAD_DATA => wdch_dout, M_VALID => M_AXI_WVALID, M_READY => M_AXI_WREADY ); END GENERATE gwdch_reg_slice; gwrch2: IF (C_WRCH_TYPE = 0) GENERATE axi_wrch : fifo_generator_v8_2_conv -- Write Response Channel GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH = 1 OR C_IMPLEMENTATION_TYPE_WRCH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_WRCH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_WRCH, C_WR_DEPTH => C_WR_DEPTH_WRCH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH, C_DOUT_WIDTH => C_DIN_WIDTH_WRCH, C_RD_DEPTH => C_WR_DEPTH_WRCH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_WRCH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_WRCH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_WRCH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_WRCH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH, C_USE_ECC => C_USE_ECC_WRCH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_WRCH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_WRCH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_WRCH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_WRCH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_WRCH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_WRCH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_RD_FREQ => C_RD_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_WR_FREQ => C_WR_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => wrch_wr_en,--M_AXI_BVALID, RD_EN => wrch_rd_en,--S_AXI_BREADY, PROG_FULL_THRESH => AXI_B_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_B_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_B_INJECTDBITERR, INJECTSBITERR => AXI_B_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_B_INPUT_CE, -- OUTPUT_CE => AXI_B_OUTPUT_CE, -- END_OF_PACKET => AXI_B_END_OF_PACKET, -- BYTE_STROBE => AXI_B_BYTE_STROBE, DIN => wrch_din, DOUT => wrch_dout, FULL => wrch_full, ALMOST_FULL => wrch_almost_full, PROG_FULL => wrch_prog_full, EMPTY => wrch_empty, ALMOST_EMPTY => wrch_almost_empty, PROG_EMPTY => wrch_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_b_overflow_i, VALID => OPEN, UNDERFLOW => axi_b_underflow_i, DATA_COUNT => AXI_B_DATA_COUNT, RD_DATA_COUNT => AXI_B_RD_DATA_COUNT, WR_DATA_COUNT => AXI_B_WR_DATA_COUNT, SBITERR => AXI_B_SBITERR, DBITERR => AXI_B_DBITERR ); wrch_s_axi_bvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_WRCH,wrch_empty,wrch_almost_empty,wrch_prog_empty); wrch_m_axi_bready <= map_ready_valid(C_PROG_FULL_TYPE_WRCH,wrch_full,wrch_almost_full,wrch_prog_full); S_AXI_BVALID <= wrch_s_axi_bvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_WRCH,wrch_empty,wrch_almost_empty,wrch_prog_empty); M_AXI_BREADY <= wrch_m_axi_bready;--map_ready_valid(C_PROG_FULL_TYPE_WRCH,wrch_full,wrch_almost_full,wrch_prog_full); gaxi_wr_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_B_UNDERFLOW <= axi_b_underflow_i; END GENERATE gaxi_wr_ch_uf3; gaxi_wr_ch_of3: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_B_OVERFLOW <= axi_b_overflow_i; END GENERATE gaxi_wr_ch_of3; END GENERATE gwrch2; -- Register Slice for Write Response Channel gwrch_reg_slice: IF (C_WRCH_TYPE = 1) GENERATE wrch_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_WRCH, C_REG_CONFIG => C_REG_SLICE_MODE_WRCH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => wrch_din, S_VALID => M_AXI_BVALID, S_READY => M_AXI_BREADY, -- Master side M_PAYLOAD_DATA => wrch_dout, M_VALID => S_AXI_BVALID, M_READY => S_AXI_BREADY ); END GENERATE gwrch_reg_slice; gaxi_wr_ch_uf4: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE axi_wr_underflow_i <= axi_aw_underflow_i OR axi_w_underflow_i OR axi_b_underflow_i; END GENERATE gaxi_wr_ch_uf4; gaxi_wr_ch_of4: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE axi_wr_overflow_i <= axi_aw_overflow_i OR axi_w_overflow_i OR axi_b_overflow_i; END GENERATE gaxi_wr_ch_of4; END GENERATE gwrch; grdch: IF (C_HAS_AXI_RD_CHANNEL = 1) GENERATE SIGNAL rach_din : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rach_dout : std_logic_vector(C_DIN_WIDTH_RACH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rach_full : std_logic := '0'; SIGNAL rach_almost_full : std_logic := '0'; SIGNAL rach_prog_full : std_logic := '0'; SIGNAL rach_empty : std_logic := '0'; SIGNAL rach_almost_empty : std_logic := '0'; SIGNAL rach_prog_empty : std_logic := '0'; SIGNAL rdch_din : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdch_dout : std_logic_vector(C_DIN_WIDTH_RDCH-1 DOWNTO 0) := (OTHERS => '0'); SIGNAL rdch_full : std_logic := '0'; SIGNAL rdch_almost_full : std_logic := '0'; SIGNAL rdch_prog_full : std_logic := '0'; SIGNAL rdch_empty : std_logic := '0'; SIGNAL rdch_almost_empty : std_logic := '0'; SIGNAL rdch_prog_empty : std_logic := '0'; SIGNAL axi_ar_underflow_i : std_logic := '0'; SIGNAL axi_ar_overflow_i : std_logic := '0'; SIGNAL axi_r_underflow_i : std_logic := '0'; SIGNAL axi_r_overflow_i : std_logic := '0'; SIGNAL rach_s_axi_arready : std_logic := '0'; SIGNAL rach_m_axi_arvalid : std_logic := '0'; SIGNAL rach_wr_en : std_logic := '0'; SIGNAL rach_rd_en : std_logic := '0'; SIGNAL rdch_m_axi_rready : std_logic := '0'; SIGNAL rdch_s_axi_rvalid : std_logic := '0'; SIGNAL rdch_wr_en : std_logic := '0'; SIGNAL rdch_rd_en : std_logic := '0'; CONSTANT ARID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_RACH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RACH); CONSTANT ARADDR_OFFSET : integer := ARID_OFFSET - C_AXI_ADDR_WIDTH; CONSTANT ARLEN_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARADDR_OFFSET - C_AXI_LEN_WIDTH,ARADDR_OFFSET); CONSTANT ARSIZE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARLEN_OFFSET - C_AXI_SIZE_WIDTH,ARLEN_OFFSET); CONSTANT ARBURST_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARSIZE_OFFSET - C_AXI_BURST_WIDTH,ARSIZE_OFFSET); CONSTANT ARLOCK_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARBURST_OFFSET - C_AXI_LOCK_WIDTH,ARBURST_OFFSET); CONSTANT ARCACHE_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,ARLOCK_OFFSET - C_AXI_CACHE_WIDTH,ARLOCK_OFFSET); CONSTANT ARPROT_OFFSET : integer := ARCACHE_OFFSET - C_AXI_PROT_WIDTH; CONSTANT ARQOS_OFFSET : integer := ARPROT_OFFSET - C_AXI_QOS_WIDTH; CONSTANT ARREGION_OFFSET : integer := ARQOS_OFFSET - C_AXI_REGION_WIDTH; CONSTANT ARUSER_OFFSET : integer := if_then_else(C_HAS_AXI_ARUSER = 1,ARREGION_OFFSET-C_AXI_ARUSER_WIDTH,ARREGION_OFFSET); CONSTANT RID_OFFSET : integer := if_then_else(C_AXI_TYPE = 1,C_DIN_WIDTH_RDCH - C_AXI_ID_WIDTH,C_DIN_WIDTH_RDCH); CONSTANT RDATA_OFFSET : integer := RID_OFFSET - C_AXI_DATA_WIDTH; CONSTANT RRESP_OFFSET : integer := RDATA_OFFSET - C_AXI_RRESP_WIDTH; CONSTANT RUSER_OFFSET : integer := if_then_else(C_HAS_AXI_RUSER = 1,RRESP_OFFSET-C_AXI_RUSER_WIDTH,RRESP_OFFSET); BEGIN -- Form the DIN to FIFO by concatinating the AXI Full Write Address Channel optional ports axi_full_din_rd_ch: IF (C_AXI_TYPE = 1) GENERATE grach1: IF (C_RACH_TYPE < 2) GENERATE grach_din1: IF (C_HAS_AXI_ARUSER = 1) GENERATE rach_din <= S_AXI_ARID & S_AXI_ARADDR & S_AXI_ARLEN & S_AXI_ARSIZE & S_AXI_ARBURST & S_AXI_ARLOCK & S_AXI_ARCACHE & S_AXI_ARPROT & S_AXI_ARQOS & S_AXI_ARREGION & S_AXI_ARUSER; M_AXI_ARUSER <= rach_dout(ARREGION_OFFSET-1 DOWNTO ARUSER_OFFSET); END GENERATE grach_din1; grach_din2: IF (C_HAS_AXI_ARUSER = 0) GENERATE rach_din <= S_AXI_ARID & S_AXI_ARADDR & S_AXI_ARLEN & S_AXI_ARSIZE & S_AXI_ARBURST & S_AXI_ARLOCK & S_AXI_ARCACHE & S_AXI_ARPROT & S_AXI_ARQOS & S_AXI_ARREGION; M_AXI_ARUSER <= (OTHERS => '0'); END GENERATE grach_din2; M_AXI_ARID <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARID_OFFSET); M_AXI_ARADDR <= rach_dout(ARID_OFFSET-1 DOWNTO ARADDR_OFFSET); M_AXI_ARLEN <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARLEN_OFFSET); M_AXI_ARSIZE <= rach_dout(ARLEN_OFFSET-1 DOWNTO ARSIZE_OFFSET); M_AXI_ARBURST <= rach_dout(ARSIZE_OFFSET-1 DOWNTO ARBURST_OFFSET); M_AXI_ARLOCK <= rach_dout(ARBURST_OFFSET-1 DOWNTO ARLOCK_OFFSET); M_AXI_ARCACHE <= rach_dout(ARLOCK_OFFSET-1 DOWNTO ARCACHE_OFFSET); M_AXI_ARPROT <= rach_dout(ARCACHE_OFFSET-1 DOWNTO ARPROT_OFFSET); M_AXI_ARQOS <= rach_dout(ARPROT_OFFSET-1 DOWNTO ARQOS_OFFSET); M_AXI_ARREGION <= rach_dout(ARQOS_OFFSET-1 DOWNTO ARREGION_OFFSET); END GENERATE grach1; -- Generate the DIN to FIFO by concatinating the AXI Full Read Data Channel optional ports grdch1: IF (C_RDCH_TYPE < 2) GENERATE grdch_din1: IF (C_HAS_AXI_RUSER = 1) GENERATE rdch_din <= M_AXI_RID & M_AXI_RDATA & M_AXI_RRESP & M_AXI_RUSER & M_AXI_RLAST; S_AXI_RLAST <= rdch_dout(0); S_AXI_RUSER <= rdch_dout(RRESP_OFFSET-1 DOWNTO RUSER_OFFSET); END GENERATE grdch_din1; grdch_din2: IF (C_HAS_AXI_RUSER = 0) GENERATE rdch_din <= M_AXI_RID & M_AXI_RDATA & M_AXI_RRESP & M_AXI_RLAST; S_AXI_RLAST <= rdch_dout(0); S_AXI_RUSER <= (OTHERS => '0'); END GENERATE grdch_din2; S_AXI_RID <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RID_OFFSET); S_AXI_RDATA <= rdch_dout(RID_OFFSET-1 DOWNTO RDATA_OFFSET); S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET); END GENERATE grdch1; END GENERATE axi_full_din_rd_ch; -- Form the DIN to FIFO by concatinating the AXI Lite Read Address Channel optional ports axi_lite_din_rd_ch: IF (C_AXI_TYPE = 2) GENERATE grach1: IF (C_RACH_TYPE < 2) GENERATE rach_din <= S_AXI_ARADDR & S_AXI_ARPROT; M_AXI_ARADDR <= rach_dout(C_DIN_WIDTH_RACH-1 DOWNTO ARADDR_OFFSET); M_AXI_ARPROT <= rach_dout(ARADDR_OFFSET-1 DOWNTO ARPROT_OFFSET); END GENERATE grach1; grdch1: IF (C_RDCH_TYPE < 2) GENERATE rdch_din <= M_AXI_RDATA & M_AXI_RRESP; S_AXI_RDATA <= rdch_dout(C_DIN_WIDTH_RDCH-1 DOWNTO RDATA_OFFSET); S_AXI_RRESP <= rdch_dout(RDATA_OFFSET-1 DOWNTO RRESP_OFFSET); END GENERATE grdch1; END GENERATE axi_lite_din_rd_ch; -- Write protection for Read Address Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt grach_wr_en1: IF (C_PROG_FULL_TYPE_RACH = 5) GENERATE rach_wr_en <= S_AXI_ARVALID; END GENERATE grach_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL grach_wr_en2: IF (C_PROG_FULL_TYPE_RACH /= 5) GENERATE rach_wr_en <= rach_s_axi_arready AND S_AXI_ARVALID; END GENERATE grach_wr_en2; -- Write protection for Read Data Channel -- When FULL is high, pass VALID as a WR_EN to the FIFO to get OVERFLOW interrupt grdch_wr_en1: IF (C_PROG_FULL_TYPE_RDCH = 5) GENERATE rdch_wr_en <= M_AXI_RVALID; END GENERATE grdch_wr_en1; -- When ALMOST_FULL or PROG_FULL is high, then shield the FIFO from becoming FULL grdch_wr_en2: IF (C_PROG_FULL_TYPE_RDCH /= 5) GENERATE rdch_wr_en <= rdch_m_axi_rready AND M_AXI_RVALID; END GENERATE grdch_wr_en2; -- Read protection for Read Address Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt grach_rd_en1: IF (C_PROG_EMPTY_TYPE_RACH = 5) GENERATE rach_rd_en <= M_AXI_ARREADY; END GENERATE grach_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY grach_rd_en2: IF (C_PROG_EMPTY_TYPE_RACH /= 5) GENERATE rach_rd_en <= rach_m_axi_arvalid AND M_AXI_ARREADY; END GENERATE grach_rd_en2; -- Read protection for Read Data Channel -- When EMPTY is low, pass READY as a RD_EN to the FIFO to get UNDERFLOW interrupt grdch_rd_en1: IF (C_PROG_EMPTY_TYPE_RDCH = 5) GENERATE rdch_rd_en <= S_AXI_RREADY; END GENERATE grdch_rd_en1; -- When ALMOST_EMPTY or PROG_EMPTY is low, then shield the FIFO from becoming EMPTY grdch_rd_en2: IF (C_PROG_EMPTY_TYPE_RDCH /= 5) GENERATE rdch_rd_en <= rdch_s_axi_rvalid AND S_AXI_RREADY; END GENERATE grdch_rd_en2; grach2: IF (C_RACH_TYPE = 0) GENERATE axi_rach : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH = 1 OR C_IMPLEMENTATION_TYPE_RACH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RACH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_RACH, C_WR_DEPTH => C_WR_DEPTH_RACH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH, C_DOUT_WIDTH => C_DIN_WIDTH_RACH, C_RD_DEPTH => C_WR_DEPTH_RACH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RACH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RACH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RACH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RACH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH, C_USE_ECC => C_USE_ECC_RACH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RACH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_RACH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_RACH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_RACH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RACH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RACH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_WR_FREQ => C_WR_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_RD_FREQ => C_RD_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => rach_wr_en,--S_AXI_ARVALID, RD_EN => rach_rd_en,--M_AXI_ARREADY, PROG_FULL_THRESH => AXI_AR_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_AR_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_AR_INJECTDBITERR, INJECTSBITERR => AXI_AR_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_AR_INPUT_CE, -- OUTPUT_CE => AXI_AR_OUTPUT_CE, -- END_OF_PACKET => AXI_AR_END_OF_PACKET, -- BYTE_STROBE => AXI_AR_BYTE_STROBE, DIN => rach_din, DOUT => rach_dout, FULL => rach_full, ALMOST_FULL => rach_almost_full, PROG_FULL => rach_prog_full, EMPTY => rach_empty, ALMOST_EMPTY => rach_almost_empty, PROG_EMPTY => rach_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_ar_overflow_i, VALID => OPEN, UNDERFLOW => axi_ar_underflow_i, DATA_COUNT => AXI_AR_DATA_COUNT, RD_DATA_COUNT => AXI_AR_RD_DATA_COUNT, WR_DATA_COUNT => AXI_AR_WR_DATA_COUNT, SBITERR => AXI_AR_SBITERR, DBITERR => AXI_AR_DBITERR ); rach_s_axi_arready <= map_ready_valid(C_PROG_FULL_TYPE_RACH,rach_full,rach_almost_full,rach_prog_full); rach_m_axi_arvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RACH,rach_empty,rach_almost_empty,rach_prog_empty); S_AXI_ARREADY <= rach_s_axi_arready;--map_ready_valid(C_PROG_FULL_TYPE_RACH,rach_full,rach_almost_full,rach_prog_full); M_AXI_ARVALID <= rach_m_axi_arvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_RACH,rach_empty,rach_almost_empty,rach_prog_empty); gaxi_rd_ch_uf1: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_AR_UNDERFLOW <= axi_ar_underflow_i; END GENERATE gaxi_rd_ch_uf1; gaxi_rd_ch_of1: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_AR_OVERFLOW <= axi_ar_overflow_i; END GENERATE gaxi_rd_ch_of1; END GENERATE grach2; -- Register Slice for Read Address Channel grach_reg_slice: IF (C_RACH_TYPE = 1) GENERATE rach_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_RACH, C_REG_CONFIG => C_REG_SLICE_MODE_RACH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => rach_din, S_VALID => S_AXI_ARVALID, S_READY => S_AXI_ARREADY, -- Master side M_PAYLOAD_DATA => rach_dout, M_VALID => M_AXI_ARVALID, M_READY => M_AXI_ARREADY ); END GENERATE grach_reg_slice; grdch2: IF (C_RDCH_TYPE = 0) GENERATE axi_rdch : fifo_generator_v8_2_conv GENERIC MAP ( C_FAMILY => C_FAMILY, C_COMMON_CLOCK => C_COMMON_CLOCK, C_MEMORY_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH = 1 OR C_IMPLEMENTATION_TYPE_RDCH = 11),1,2), C_IMPLEMENTATION_TYPE => if_then_else((C_IMPLEMENTATION_TYPE_RDCH <= 6),0,2), -- CCBI C_PRELOAD_REGS => 1, -- Always FWFT for AXI C_PRELOAD_LATENCY => 0, -- Always FWFT for AXI C_DIN_WIDTH => C_DIN_WIDTH_RDCH, C_WR_DEPTH => C_WR_DEPTH_RDCH, C_WR_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH, C_DOUT_WIDTH => C_DIN_WIDTH_RDCH, C_RD_DEPTH => C_WR_DEPTH_RDCH, C_RD_PNTR_WIDTH => C_WR_PNTR_WIDTH_RDCH, C_PROG_FULL_TYPE => C_PROG_FULL_TYPE_RDCH, C_PROG_FULL_THRESH_ASSERT_VAL => C_PROG_FULL_THRESH_ASSERT_VAL_RDCH, C_PROG_EMPTY_TYPE => C_PROG_EMPTY_TYPE_RDCH, C_PROG_EMPTY_THRESH_ASSERT_VAL => C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH, C_USE_ECC => C_USE_ECC_RDCH, C_ERROR_INJECTION_TYPE => C_ERROR_INJECTION_TYPE_RDCH, C_HAS_ALMOST_EMPTY => if_then_else((C_PROG_EMPTY_TYPE_RDCH = 6), 1, 0), C_HAS_ALMOST_FULL => if_then_else((C_PROG_FULL_TYPE_RDCH = 6), 1, 0), -- Enable Low Latency Sync FIFO for Common Clock Built-in FIFO C_FIFO_TYPE => C_APPLICATION_TYPE_RDCH, -- Place holder parameters for the new features -- C_USE_SYNC_CLK => 0, -- C_BYTE_STRB_WIDTH => 8, -- C_USE_INPUT_CE => 0, -- C_USE_OUTPUT_CE => 0, C_HAS_WR_RST => 0, C_HAS_RD_RST => 0, C_HAS_RST => 1, C_HAS_SRST => 0, C_DOUT_RST_VAL => "0", C_HAS_VALID => C_HAS_VALID, C_VALID_LOW => C_VALID_LOW, C_HAS_UNDERFLOW => C_HAS_UNDERFLOW, C_UNDERFLOW_LOW => C_UNDERFLOW_LOW, C_HAS_WR_ACK => C_HAS_WR_ACK, C_WR_ACK_LOW => C_WR_ACK_LOW, C_HAS_OVERFLOW => C_HAS_OVERFLOW, C_OVERFLOW_LOW => C_OVERFLOW_LOW, C_HAS_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 1 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0), C_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1, C_HAS_RD_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0), C_RD_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1, C_USE_FWFT_DATA_COUNT => 1, -- use extra logic is always true C_HAS_WR_DATA_COUNT => if_then_else((C_COMMON_CLOCK = 0 AND C_HAS_DATA_COUNTS_RDCH = 1), 1, 0), C_WR_DATA_COUNT_WIDTH => C_WR_PNTR_WIDTH_RDCH+1, C_FULL_FLAGS_RST_VAL => 1, C_USE_EMBEDDED_REG => 0, C_USE_DOUT_RST => 0, C_MSGON_VAL => C_MSGON_VAL, C_ENABLE_RST_SYNC => 1, C_COUNT_TYPE => C_COUNT_TYPE, C_DEFAULT_VALUE => C_DEFAULT_VALUE, C_ENABLE_RLOCS => C_ENABLE_RLOCS, C_HAS_BACKUP => C_HAS_BACKUP, C_HAS_INT_CLK => C_HAS_INT_CLK, C_HAS_MEMINIT_FILE => C_HAS_MEMINIT_FILE, C_INIT_WR_PNTR_VAL => C_INIT_WR_PNTR_VAL, C_MIF_FILE_NAME => C_MIF_FILE_NAME, C_OPTIMIZATION_MODE => C_OPTIMIZATION_MODE, C_WR_FREQ => C_WR_FREQ, C_USE_FIFO16_FLAGS => C_USE_FIFO16_FLAGS, C_RD_FREQ => C_RD_FREQ, C_WR_RESPONSE_LATENCY => C_WR_RESPONSE_LATENCY ) PORT MAP( --Inputs BACKUP => BACKUP, BACKUP_MARKER => BACKUP_MARKER, INT_CLK => INT_CLK, CLK => S_ACLK, WR_CLK => S_ACLK, RD_CLK => M_ACLK, RST => inverted_reset, SRST => '0', WR_RST => inverted_reset, RD_RST => inverted_reset, WR_EN => rdch_wr_en,--M_AXI_RVALID, RD_EN => rdch_rd_en,--S_AXI_RREADY, PROG_FULL_THRESH => AXI_R_PROG_FULL_THRESH, PROG_FULL_THRESH_ASSERT => (OTHERS => '0'), PROG_FULL_THRESH_NEGATE => (OTHERS => '0'), PROG_EMPTY_THRESH => AXI_R_PROG_EMPTY_THRESH, PROG_EMPTY_THRESH_ASSERT => (OTHERS => '0'), PROG_EMPTY_THRESH_NEGATE => (OTHERS => '0'), INJECTDBITERR => AXI_R_INJECTDBITERR, INJECTSBITERR => AXI_R_INJECTSBITERR, -- Place holder parameters for the new features -- INPUT_CE => AXI_R_INPUT_CE, -- OUTPUT_CE => AXI_R_OUTPUT_CE, -- END_OF_PACKET => AXI_R_END_OF_PACKET, -- BYTE_STROBE => AXI_R_BYTE_STROBE, DIN => rdch_din, DOUT => rdch_dout, FULL => rdch_full, ALMOST_FULL => rdch_almost_full, PROG_FULL => rdch_prog_full, EMPTY => rdch_empty, ALMOST_EMPTY => rdch_almost_empty, PROG_EMPTY => rdch_prog_empty, WR_ACK => OPEN, OVERFLOW => axi_r_overflow_i, VALID => OPEN, UNDERFLOW => axi_r_underflow_i, DATA_COUNT => AXI_R_DATA_COUNT, RD_DATA_COUNT => AXI_R_RD_DATA_COUNT, WR_DATA_COUNT => AXI_R_WR_DATA_COUNT, SBITERR => AXI_R_SBITERR, DBITERR => AXI_R_DBITERR ); rdch_s_axi_rvalid <= map_ready_valid(C_PROG_EMPTY_TYPE_RDCH,rdch_empty,rdch_almost_empty,rdch_prog_empty); rdch_m_axi_rready <= map_ready_valid(C_PROG_FULL_TYPE_RDCH,rdch_full,rdch_almost_full,rdch_prog_full); S_AXI_RVALID <= rdch_s_axi_rvalid;--map_ready_valid(C_PROG_EMPTY_TYPE_RDCH,rdch_empty,rdch_almost_empty,rdch_prog_empty); M_AXI_RREADY <= rdch_m_axi_rready;--map_ready_valid(C_PROG_FULL_TYPE_RDCH,rdch_full,rdch_almost_full,rdch_prog_full); gaxi_rd_ch_uf2: IF (C_USE_COMMON_UNDERFLOW = 0) GENERATE AXI_R_UNDERFLOW <= axi_r_underflow_i; END GENERATE gaxi_rd_ch_uf2; gaxi_rd_ch_of2: IF (C_USE_COMMON_OVERFLOW = 0) GENERATE AXI_R_OVERFLOW <= axi_r_overflow_i; END GENERATE gaxi_rd_ch_of2; END GENERATE grdch2; -- Register Slice for Read Data Channel grdch_reg_slice: IF (C_RDCH_TYPE = 1) GENERATE rdch_reg_slice: fifo_generator_v8_2_axic_reg_slice GENERIC MAP ( C_FAMILY => C_FAMILY, C_DATA_WIDTH => C_DIN_WIDTH_RDCH, C_REG_CONFIG => C_REG_SLICE_MODE_RDCH ) PORT MAP( -- System Signals ACLK => S_ACLK, ARESET => inverted_reset, -- Slave side S_PAYLOAD_DATA => rdch_din, S_VALID => M_AXI_RVALID, S_READY => M_AXI_RREADY, -- Master side M_PAYLOAD_DATA => rdch_dout, M_VALID => S_AXI_RVALID, M_READY => S_AXI_RREADY ); END GENERATE grdch_reg_slice; gaxi_rd_ch_uf3: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE axi_rd_underflow_i <= axi_ar_underflow_i OR axi_r_underflow_i; END GENERATE gaxi_rd_ch_uf3; gaxi_rd_ch_of3: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE axi_rd_overflow_i <= axi_ar_overflow_i OR axi_r_overflow_i; END GENERATE gaxi_rd_ch_of3; END GENERATE grdch; gaxi_comm_uf: IF (C_USE_COMMON_UNDERFLOW = 1) GENERATE grdwr_uf1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE UNDERFLOW <= axi_wr_underflow_i OR axi_rd_underflow_i; END GENERATE grdwr_uf1; grdwr_uf2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE UNDERFLOW <= axi_wr_underflow_i; END GENERATE grdwr_uf2; grdwr_uf3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE UNDERFLOW <= axi_rd_underflow_i; END GENERATE grdwr_uf3; END GENERATE gaxi_comm_uf; gaxi_comm_of: IF (C_USE_COMMON_OVERFLOW = 1) GENERATE grdwr_of1: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE OVERFLOW <= axi_wr_overflow_i OR axi_rd_overflow_i; END GENERATE grdwr_of1; grdwr_of2: IF (C_HAS_AXI_WR_CHANNEL = 1 AND C_HAS_AXI_RD_CHANNEL = 0) GENERATE OVERFLOW <= axi_wr_overflow_i; END GENERATE grdwr_of2; grdwr_of3: IF (C_HAS_AXI_WR_CHANNEL = 0 AND C_HAS_AXI_RD_CHANNEL = 1) GENERATE OVERFLOW <= axi_rd_overflow_i; END GENERATE grdwr_of3; END GENERATE gaxi_comm_of; END GENERATE gaxifull; --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- -- Pass Through Logic or Wiring Logic --------------------------------------------------------------------------- --------------------------------------------------------------------------- --------------------------------------------------------------------------- gaxi_pass_through: IF (C_WACH_TYPE = 2 OR C_WDCH_TYPE = 2 OR C_WRCH_TYPE = 2 OR C_RACH_TYPE = 2 OR C_RDCH_TYPE = 2 OR C_AXIS_TYPE = 2) GENERATE gwach_pass_through: IF (C_WACH_TYPE = 2) GENERATE -- Wiring logic for Write Address Channel M_AXI_AWID <= S_AXI_AWID; M_AXI_AWADDR <= S_AXI_AWADDR; M_AXI_AWLEN <= S_AXI_AWLEN; M_AXI_AWSIZE <= S_AXI_AWSIZE; M_AXI_AWBURST <= S_AXI_AWBURST; M_AXI_AWLOCK <= S_AXI_AWLOCK; M_AXI_AWCACHE <= S_AXI_AWCACHE; M_AXI_AWPROT <= S_AXI_AWPROT; M_AXI_AWQOS <= S_AXI_AWQOS; M_AXI_AWREGION <= S_AXI_AWREGION; M_AXI_AWUSER <= S_AXI_AWUSER; S_AXI_AWREADY <= M_AXI_AWREADY; M_AXI_AWVALID <= S_AXI_AWVALID; END GENERATE gwach_pass_through; -- Wiring logic for Write Data Channel gwdch_pass_through: IF (C_WDCH_TYPE = 2) GENERATE M_AXI_WID <= S_AXI_WID; M_AXI_WDATA <= S_AXI_WDATA; M_AXI_WSTRB <= S_AXI_WSTRB; M_AXI_WLAST <= S_AXI_WLAST; M_AXI_WUSER <= S_AXI_WUSER; S_AXI_WREADY <= M_AXI_WREADY; M_AXI_WVALID <= S_AXI_WVALID; END GENERATE gwdch_pass_through; -- Wiring logic for Write Response Channel gwrch_pass_through: IF (C_WRCH_TYPE = 2) GENERATE S_AXI_BID <= M_AXI_BID; S_AXI_BRESP <= M_AXI_BRESP; S_AXI_BUSER <= M_AXI_BUSER; M_AXI_BREADY <= S_AXI_BREADY; S_AXI_BVALID <= M_AXI_BVALID; END GENERATE gwrch_pass_through; -- Pass Through Logic for Read Channel grach_pass_through: IF (C_RACH_TYPE = 2) GENERATE -- Wiring logic for Read Address Channel M_AXI_ARID <= S_AXI_ARID; M_AXI_ARADDR <= S_AXI_ARADDR; M_AXI_ARLEN <= S_AXI_ARLEN; M_AXI_ARSIZE <= S_AXI_ARSIZE; M_AXI_ARBURST <= S_AXI_ARBURST; M_AXI_ARLOCK <= S_AXI_ARLOCK; M_AXI_ARCACHE <= S_AXI_ARCACHE; M_AXI_ARPROT <= S_AXI_ARPROT; M_AXI_ARQOS <= S_AXI_ARQOS; M_AXI_ARREGION <= S_AXI_ARREGION; M_AXI_ARUSER <= S_AXI_ARUSER; S_AXI_ARREADY <= M_AXI_ARREADY; M_AXI_ARVALID <= S_AXI_ARVALID; END GENERATE grach_pass_through; grdch_pass_through: IF (C_RDCH_TYPE = 2) GENERATE -- Wiring logic for Read Data Channel S_AXI_RID <= M_AXI_RID; S_AXI_RLAST <= M_AXI_RLAST; S_AXI_RUSER <= M_AXI_RUSER; S_AXI_RDATA <= M_AXI_RDATA; S_AXI_RRESP <= M_AXI_RRESP; S_AXI_RVALID <= M_AXI_RVALID; M_AXI_RREADY <= S_AXI_RREADY; END GENERATE grdch_pass_through; gaxis_pass_through: IF (C_AXIS_TYPE = 2) GENERATE -- Wiring logic for AXI Streaming M_AXIS_TDATA <= S_AXIS_TDATA; M_AXIS_TSTRB <= S_AXIS_TSTRB; M_AXIS_TKEEP <= S_AXIS_TKEEP; M_AXIS_TID <= S_AXIS_TID; M_AXIS_TDEST <= S_AXIS_TDEST; M_AXIS_TUSER <= S_AXIS_TUSER; M_AXIS_TLAST <= S_AXIS_TLAST; S_AXIS_TREADY <= M_AXIS_TREADY; M_AXIS_TVALID <= S_AXIS_TVALID; END GENERATE gaxis_pass_through; END GENERATE gaxi_pass_through; END behavioral;

mit

stanford-ppl/spatial-lang

spatial/core/resources/chiselgen/template-level/fringeArria10/build/ip/pr_region_default/pr_region_default_mm_bridge_1/pr_region_default_mm_bridge_1_inst.vhd

1

4666

component pr_region_default_mm_bridge_1 is generic ( DATA_WIDTH : integer := 32; SYMBOL_WIDTH : integer := 8; HDL_ADDR_WIDTH : integer := 10; BURSTCOUNT_WIDTH : integer := 1; PIPELINE_COMMAND : integer := 1; PIPELINE_RESPONSE : integer := 1 ); port ( clk : in std_logic := 'X'; -- clk m0_waitrequest : in std_logic := 'X'; -- waitrequest m0_readdata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- readdata m0_readdatavalid : in std_logic := 'X'; -- readdatavalid m0_burstcount : out std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0); -- burstcount m0_writedata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- writedata m0_address : out std_logic_vector(HDL_ADDR_WIDTH-1 downto 0); -- address m0_write : out std_logic; -- write m0_read : out std_logic; -- read m0_byteenable : out std_logic_vector(63 downto 0); -- byteenable m0_debugaccess : out std_logic; -- debugaccess reset : in std_logic := 'X'; -- reset s0_waitrequest : out std_logic; -- waitrequest s0_readdata : out std_logic_vector(DATA_WIDTH-1 downto 0); -- readdata s0_readdatavalid : out std_logic; -- readdatavalid s0_burstcount : in std_logic_vector(BURSTCOUNT_WIDTH-1 downto 0) := (others => 'X'); -- burstcount s0_writedata : in std_logic_vector(DATA_WIDTH-1 downto 0) := (others => 'X'); -- writedata s0_address : in std_logic_vector(HDL_ADDR_WIDTH-1 downto 0) := (others => 'X'); -- address s0_write : in std_logic := 'X'; -- write s0_read : in std_logic := 'X'; -- read s0_byteenable : in std_logic_vector(63 downto 0) := (others => 'X'); -- byteenable s0_debugaccess : in std_logic := 'X' -- debugaccess ); end component pr_region_default_mm_bridge_1; u0 : component pr_region_default_mm_bridge_1 generic map ( DATA_WIDTH => INTEGER_VALUE_FOR_DATA_WIDTH, SYMBOL_WIDTH => INTEGER_VALUE_FOR_SYMBOL_WIDTH, HDL_ADDR_WIDTH => INTEGER_VALUE_FOR_HDL_ADDR_WIDTH, BURSTCOUNT_WIDTH => INTEGER_VALUE_FOR_BURSTCOUNT_WIDTH, PIPELINE_COMMAND => INTEGER_VALUE_FOR_PIPELINE_COMMAND, PIPELINE_RESPONSE => INTEGER_VALUE_FOR_PIPELINE_RESPONSE ) port map ( clk => CONNECTED_TO_clk, -- clk.clk m0_waitrequest => CONNECTED_TO_m0_waitrequest, -- m0.waitrequest m0_readdata => CONNECTED_TO_m0_readdata, -- .readdata m0_readdatavalid => CONNECTED_TO_m0_readdatavalid, -- .readdatavalid m0_burstcount => CONNECTED_TO_m0_burstcount, -- .burstcount m0_writedata => CONNECTED_TO_m0_writedata, -- .writedata m0_address => CONNECTED_TO_m0_address, -- .address m0_write => CONNECTED_TO_m0_write, -- .write m0_read => CONNECTED_TO_m0_read, -- .read m0_byteenable => CONNECTED_TO_m0_byteenable, -- .byteenable m0_debugaccess => CONNECTED_TO_m0_debugaccess, -- .debugaccess reset => CONNECTED_TO_reset, -- reset.reset s0_waitrequest => CONNECTED_TO_s0_waitrequest, -- s0.waitrequest s0_readdata => CONNECTED_TO_s0_readdata, -- .readdata s0_readdatavalid => CONNECTED_TO_s0_readdatavalid, -- .readdatavalid s0_burstcount => CONNECTED_TO_s0_burstcount, -- .burstcount s0_writedata => CONNECTED_TO_s0_writedata, -- .writedata s0_address => CONNECTED_TO_s0_address, -- .address s0_write => CONNECTED_TO_s0_write, -- .write s0_read => CONNECTED_TO_s0_read, -- .read s0_byteenable => CONNECTED_TO_s0_byteenable, -- .byteenable s0_debugaccess => CONNECTED_TO_s0_debugaccess -- .debugaccess );

mit

lfmunoz/vhdl

ip_blocks/packer_12bit/packer_128.vhd

1

6929

------------------------------------------------------------------------------------- -- FILE NAME : packer_128.vhd -- AUTHOR : Luis -- COMPANY : -- UNITS : Entity - packer_128 -- Architecture - Behavioral -- LANGUAGE : VHDL -- DATE : Jan 10, 2015 ------------------------------------------------------------------------------------- -- ------------------------------------------------------------------------------------- -- DESCRIPTION -- =========== -- 16-bits as 8 samples =128-bits -- 12-bits as 8 samples =96-bits -- 12-bits * 8 samples * 4 cycles = 384-bits -- 16-bits * 8 samples * 3 cycles = 384-bits -- When val_in = '1', this entity will accept 4 chuncks of 128-bits unpacked and output -- 3 chucks of 128-bits packed. -- -- ------------------------------------------------------------------------------------- ------------------------------------------------------------------------------------- -- LIBRARIES ------------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_misc.all; use ieee.std_logic_arith.all; Library UNISIM; use UNISIM.vcomponents.all; ------------------------------------------------------------------------------------- -- ENTITY ------------------------------------------------------------------------------------- entity packer_128 is port ( clk_in : in std_logic; rst_in : in std_logic; val_in : in std_logic; data_in : in std_logic_vector(127 downto 0); val_out : out std_logic; data_out : out std_logic_vector(127 downto 0); test_mode : in std_logic ); end packer_128; ------------------------------------------------------------------------------------- -- ARCHITECTURE ------------------------------------------------------------------------------------- architecture Behavioral of packer_128 is ------------------------------------------------------------------------------------- -- CONSTANTS ------------------------------------------------------------------------------------- type state_machine is (state0, state1, state2, state3); ------------------------------------------------------------------------------------- -- SIGNALS ------------------------------------------------------------------------------------- signal sm_reg : state_machine; signal reg0 : std_logic_vector(127 downto 0); signal sample0 : std_logic_vector(11 downto 0); signal sample1 : std_logic_vector(11 downto 0); signal sample2 : std_logic_vector(11 downto 0); signal sample3 : std_logic_vector(11 downto 0); signal sample4 : std_logic_vector(11 downto 0); signal sample5 : std_logic_vector(11 downto 0); signal sample6 : std_logic_vector(11 downto 0); signal sample7 : std_logic_vector(11 downto 0); signal sample0_cnt : std_logic_vector(11 downto 0); signal sample1_cnt : std_logic_vector(11 downto 0); signal sample2_cnt : std_logic_vector(11 downto 0); signal sample3_cnt : std_logic_vector(11 downto 0); signal sample4_cnt : std_logic_vector(11 downto 0); signal sample5_cnt : std_logic_vector(11 downto 0); signal sample6_cnt : std_logic_vector(11 downto 0); signal sample7_cnt : std_logic_vector(11 downto 0); signal counter : std_logic_vector(11 downto 0); signal valid_reg : std_logic; signal zero_32 : std_logic_vector(31 downto 0); signal zero_64 : std_logic_vector(63 downto 0); signal zero_96 : std_logic_vector(95 downto 0); --*********************************************************************************** begin --*********************************************************************************** zero_96 <= (others=>'0'); zero_64 <= (others=>'0'); zero_32 <= (others=>'0'); -- Genereate a counting test pattern process(clk_in, rst_in) begin if rst_in = '1' then counter <= (others=>'0'); elsif rising_edge(clk_in) then if val_in = '1' then counter <= counter + 8; end if; end if; end process; sample0_cnt <= counter + 0; sample1_cnt <= counter + 1; sample2_cnt <= counter + 2; sample3_cnt <= counter + 3; sample4_cnt <= counter + 4; sample5_cnt <= counter + 5; sample6_cnt <= counter + 6; sample7_cnt <= counter + 7; -- select between test pattern or input data process(clk_in) begin if rising_edge(clk_in) then valid_reg <= val_in; if test_mode = '0' then sample0 <= data_in(11 downto 0); sample1 <= data_in(27 downto 16); sample2 <= data_in(43 downto 32); sample3 <= data_in(59 downto 48); sample4 <= data_in(75 downto 64); sample5 <= data_in(91 downto 80); sample6 <= data_in(107 downto 96); sample7 <= data_in(123 downto 112); else sample0 <= sample0_cnt; sample1 <= sample1_cnt; sample2 <= sample2_cnt; sample3 <= sample3_cnt; sample4 <= sample4_cnt; sample5 <= sample5_cnt; sample6 <= sample6_cnt; sample7 <= sample7_cnt; end if; end if; end process; -- packing state machine process(clk_in, rst_in) begin if rising_edge(clk_in) then if rst_in = '1' then data_out <= (others=>'0'); val_out <= '0'; reg0 <= (others=>'0'); sm_reg <= state0; else --default val_out <= '0'; case sm_reg is when state0 => if valid_reg = '1' then sm_reg <= state1; reg0 <= zero_32 & sample7 & sample6 & sample5 & sample4 & sample3 & sample2 & sample1 & sample0; end if; when state1 => sm_reg <= state2; val_out <= '1'; data_out <= sample2(7 downto 0) & sample1 & sample0 & reg0(95 downto 0); reg0 <= zero_64 & sample7 & sample6 & sample5 & sample4 & sample3 & sample2(11 downto 8); when state2 => sm_reg <= state3; val_out <= '1'; data_out <= sample5(3 downto 0) & sample4 & sample3 & sample2 & sample1 & sample0 & reg0(63 downto 0); reg0 <= zero_96 & sample7 & sample6 & sample5(11 downto 4); when state3 => sm_reg <= state0; val_out <= '1'; data_out <= sample7 & sample6 & sample5 & sample4 & sample3 & sample2 & sample1 & sample0 & reg0(31 downto 0); when others => sm_reg <= state0; end case; end if; end if; end process; --*********************************************************************************** end architecture Behavioral; --***********************************************************************************

mit

AlexMitakos/DES-in-VHDL

testbenches/test_right_shift_by_1.vhdl

1

474

library ieee; use ieee.std_logic_1164.all; use work.all; entity test_right_shift_by_1 is end test_right_shift_by_1; architecture behavior of test_right_shift_by_1 is signal data_in: std_logic_vector(0 to 27); signal data_out: std_logic_vector(0 to 27); begin uut: entity right_shift_by_1 port map (data_in, data_out); testprocess: process is begin data_in<="0111111111111111111111111110"; wait for 10 ns; end process testprocess; end architecture behavior;

mit

AlexMitakos/DES-in-VHDL

testbenches/test_round.vhdl

1

741

library ieee; use ieee.std_logic_1164.all; use work.all; entity test_round is end test_round; architecture behavior of test_round is signal left_plain: std_logic_vector(0 to 31); signal right_plain: std_logic_vector(0 to 31); signal subkey: std_logic_vector(0 to 47); signal left_data_out: std_logic_vector(0 to 31); signal right_data_out: std_logic_vector(0 to 31); begin uut: entity round port map(left_plain,right_plain,subkey,left_data_out,right_data_out); testprocess: process is begin left_plain<="00000000000000000000000000000000"; right_plain<="00000000000000000000000000000000"; subkey<="000000000000000000000000000000000000000000000000"; wait for 10 ns; end process testprocess; end architecture behavior;

mit

MrDoomBringer/DSD-Labs

Lab 8/reaction.vhd

1

4056

-- FPGA reaction time tester for Altera DE-2 board -- Cliff Chapman -- 10/27/2013 -- -- Lab 8 - Digital Systems Design LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE ieee.std_logic_signed.ALL; ENTITY reaction IS PORT ( -- Reset system rst : IN STD_LOGIC; -- Set time interval set : IN STD_LOGIC_VECTOR (7 DOWNTO 0); -- Trigger button trig : IN STD_LOGIC; -- 50 Mhz external clock clk : IN STD_LOGIC; -- Sevenseg displays d_HEX0 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX1 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); d_HEX3 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0); -- Trigger light LEDR : OUT STD_LOGIC ); END reaction; ARCHITECTURE rtl OF reaction IS COMPONENT sevenseg_bcd_display PORT ( r : IN STD_LOGIC_VECTOR (7 DOWNTO 0); s : IN STD_LOGIC := '1'; -- Select tied to '1' by default to show numeric values HEX0, HEX1, HEX2 : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) ); END COMPONENT; -- This feels like a GREAT way to screw yourself over with -- overloading common names. Maybe that's just me. -- Either way that's why we have the _s hungarian postfix on these. TYPE state_type IS (idle_s, wait_s, runprep_s, run_s, hold_s); SIGNAL state : state_type; SIGNAL clock_1 : STD_LOGIC := '0'; SIGNAL cnt_rst : STD_LOGIC; SIGNAL disp_buf: STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL mil_cnt : STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL cnt : STD_LOGIC_VECTOR (15 DOWNTO 0) := x"0000"; SIGNAL cnt_div :STD_LOGIC_VECTOR (31 DOWNTO 0) := x"00000000"; BEGIN -- Milliseconds elapsed display disp_low: sevenseg_bcd_display PORT MAP ( r => disp_buf (15 DOWNTO 8), s => '0', HEX2 => OPEN, HEX1 => d_hex3, HEX0 => d_hex2 ); disp_high: sevenseg_bcd_display PORT MAP ( r => disp_buf (7 DOWNTO 0), s => '0', HEX2 => OPEN, HEX1 => d_hex1, HEX0 => d_hex0 ); -- Clock divider for millisecond from 50Mhz clock_div: PROCESS (clk, rst) BEGIN IF (rising_edge(clk)) THEN IF (cnt_div >= x"61A7") THEN cnt_div <= x"00000000"; clock_1 <= NOT clock_1; ELSE cnt_div <= cnt_div+1; END IF; END IF; END PROCESS clock_div; -- Counter for milliseconds timer mil_clock : PROCESS (clock_1, cnt_rst, state, cnt) BEGIN IF (cnt_rst = '0') THEN cnt <= x"0000"; ELSIF (rising_edge(clock_1) AND cnt_rst = '1') THEN cnt <= cnt + '1'; ELSE cnt <= cnt; END IF; mil_cnt <= cnt; END PROCESS mil_clock; state_monitor: PROCESS (state, clk, rst) BEGIN IF (rst = '0') THEN state <= idle_s; ELSIF (rising_edge(clk) AND rst = '1') THEN CASE state IS WHEN idle_s => IF (trig = '0') THEN state <= wait_s; ELSE state <= idle_s; END IF; WHEN wait_s => IF (mil_cnt >= ((x"00" & set) * x"3E8")) THEN state <= runprep_s; ELSE state <= wait_s; END IF; WHEN runprep_s => IF (mil_cnt = x"0000") THEN state <= run_s; ELSE state <= runprep_s; END IF; WHEN run_s => IF (trig = '0') THEN state <= hold_s; ELSE state <= run_s; END IF; WHEN hold_s => state <= hold_s; WHEN OTHERS => state <= idle_s; END CASE; END IF; END PROCESS state_monitor; output_monitor: PROCESS (state, clk, rst, mil_cnt) BEGIN IF (rst = '0') THEN cnt_rst <= '0'; LEDR <= '0'; disp_buf <= x"0000"; ELSIF (rst = '1' AND rising_edge(clk)) THEN CASE (state) IS WHEN idle_s => LEDR <= '0'; cnt_rst <= '0'; disp_buf <= x"0000"; WHEN wait_s => LEDR <= '1'; cnt_rst <= '1'; disp_buf <= x"0000"; WHEN runprep_s => LEDR <= '1'; cnt_rst <= '0'; disp_buf <= x"0000"; WHEN run_s => LEDR <= '0'; cnt_rst <= '1'; disp_buf <= mil_cnt; WHEN hold_s => LEDR <= '0'; cnt_rst <= '1'; disp_buf <= disp_buf; WHEN OTHERS => cnt_rst <= '0'; LEDR <= '0'; disp_buf <= x"0000"; END CASE; END IF; END PROCESS output_monitor; END ARCHITECTURE;

mit

Given-Jiang/Binarization

Binarization_dspbuilder/db/alt_dspbuilder_vcc_GN.vhd

20

373

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_vcc_GN is port( output : out std_logic); end entity; architecture rtl of alt_dspbuilder_vcc_GN is Begin output <= '1'; end architecture;

mit

Given-Jiang/Binarization

tb_Binarization/db/alt_dspbuilder_ASAT.vhd

20

3282

-------------------------------------------------------------------------------------------- -- DSP Builder (Version 9.1) -- Quartus II development tool and MATLAB/Simulink Interface -- -- Legal Notice: © 2001 Altera Corporation. All rights reserved. Your use of Altera -- Corporation's design tools, logic functions and other software and tools, and its -- AMPP partner logic functions, and any output files any of the foregoing -- (including device programming or simulation files), and any associated -- documentation or information are expressly subject to the terms and conditions -- of the Altera Program License Subscription Agreement, Altera MegaCore Function -- License Agreement, or other applicable license agreement, including, without -- limitation, that your use is for the sole purpose of programming logic devices -- manufactured by Altera and sold by Altera or its authorized distributors. -- Please refer to the applicable agreement for further details. -------------------------------------------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_signed.all; library altera; use altera.alt_dspbuilder_package.all; entity alt_dspbuilder_ASAT is generic ( widthin : natural :=8; widthout : natural :=4; lpm_signed : BusArithm :=BusIsSigned ); port ( xin : in std_logic_vector(widthin-1 downto 0); yout : out std_logic_vector(widthout-1 downto 0) ); end alt_dspbuilder_ASAT; architecture ASAT_SYNTH of alt_dspbuilder_ASAT is function GetWidthUsgn(win: natural;wout: natural ) return natural is variable res : natural; begin if (win-wout>0) then res :=win-wout-1; else res := 0; end if; return res; end ; signal msbone : std_logic_vector(widthin-widthout downto 0); signal msbzero : std_logic_vector(widthin-widthout downto 0); signal Unsignedmsbzero : std_logic_vector(GetWidthUsgn(widthin,widthout) downto 0); signal MsbOverFlow : std_logic; begin ev:if widthin=widthout generate yout <= xin; end generate ev; sat:if (widthin>widthout) generate Gs : if lpm_signed=BusIsSigned generate msbone <= (others=>'1'); msbzero <= (others=>'0'); MsbOverFlow <= '0' when (xin(widthin-1 downto widthout-1) = msbone or xin(widthin-1 downto widthout-1) = msbzero) else '1'; process(xin,MsbOverFlow) begin if (MsbOverFlow='0') then yout(widthout-1 downto 0) <= xin(widthout-1 downto 0); else if (xin(widthin-1)='0') then for i in 0 to widthout-2 loop yout(i) <= '1'; -- max positif end loop; yout(widthout-1) <='0'; else for i in 0 to widthout-2 loop yout(i) <= '0'; -- max Negatif end loop; yout(widthout-1) <='1'; end if; end if; end process; end generate Gs; Gus : if lpm_signed=BusIsUnsigned generate Unsignedmsbzero <= (others=>'0'); MsbOverFlow <= '0' when xin(widthin-1 downto widthout) = Unsignedmsbzero else '1'; process(xin,MsbOverFlow) begin if (MsbOverFlow='0') then yout(widthout-1 downto 0) <= xin(widthout-1 downto 0); else yout <=(others=>'1'); -- Max Positive end if; end process; end generate Gus; end generate sat; end ASAT_SYNTH;

mit

Given-Jiang/Binarization

Binarization_dspbuilder/hdl/alt_dspbuilder_decoder_GNSCEXJCJK.vhd

13

947

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;

mit

Given-Jiang/Binarization

Binarization_dspbuilder/db/alt_dspbuilder_decoder_GNSCEXJCJK.vhd

13

947

library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; library altera; use altera.alt_dspbuilder_package.all; library lpm; use lpm.lpm_components.all; entity alt_dspbuilder_decoder_GNSCEXJCJK is generic ( decode : string := "000000000000000000001111"; pipeline : natural := 0; width : natural := 24); port( aclr : in std_logic; clock : in std_logic; data : in std_logic_vector((width)-1 downto 0); dec : out std_logic; ena : in std_logic; sclr : in std_logic); end entity; architecture rtl of alt_dspbuilder_decoder_GNSCEXJCJK is Begin -- DSP Builder Block - Simulink Block "Decoder" Decoderi : alt_dspbuilder_sdecoderaltr Generic map ( width => 24, decode => "000000000000000000001111", pipeline => 0) port map ( aclr => aclr, user_aclr => '0', sclr => sclr, clock => clock, data => data, dec => dec); end architecture;

mit

benjmarshall/hls_scratchpad

hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_sitodp_4_no_dsp_32/hdl/xbip_bram18k_v3_0_vh_rfs.vhd

20

103154

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AbrLtZEWaMZ9QRIEqn+KbGJaY9tnAHwhbFbsPC7WH49ehpa1EbqXv+qkeNRGupFwZ63XKanLVUyO My0fDcdlyQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jBjvZpZ5ZMxrEO8+CEfz6CEl8aMhkYM5vXXCdl+QFohneB/4ao6UdzksCSxNPxkQX54YmGSOciXP wgiPEkvihckzTQ7V+IwmdcU3758CZsJi1jYV4WKld6YxfbWBrziJy4pEooel9pwm0aG1jMx1yNUM erFXjNZfwKELIgXdp9g= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bNlKYiiGIQP+R/ChMF9YxWObkJMdPWBzZKUDypAuNCvFSKj2ODeFkzLXYHokfw+rz7RZe5YojYmq 4UkICxShbV1k/N1YYli9QKFi7npsW0xHaRa8L0tSoNNqAKETg1msjVmjBV5kKgQ78l19v/4te7qL zUqdthBriU3NcZYre5k= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0gJe90X6qrVRqoGU7iK/i5s05zq/0GlJ22Kt2H/04aXbES5oZ4I0aGRfiLSYUCL8istn1JleJ/n3 1/LRSIHwjesRoSy/6j9iedPDLLSSnKq+N+ZcvCJl8gg/L6B9ChU+h5YNE7HqJVfqJzqKWKPqsHB4 WVtjQ/Uh+QwxJp4Q/GXnPw1qlnDs2s6lJ8EK8000R7Any16QZ06T5S1IW5s5v9bKhWJj2Oj7lmWo 6QSr9mTUFxCIV/m+pXzsIOsSgFWqsBmD8jksQw5AorgxI1HaqEa3+sl/imtv2p//6lwEVtz8coiR PUlfIUpZ3ecBYh1Zuc/GrakwiRgEs/Yjfe+jCA== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ux0aTH3zrSOSGrjxNBhNJ8nXWhxNzkLj/DcKiIgChJ1nxm8i4YMzp0L+VdbHtn6L3ZPNF7NTEh1P v7Gcx16JuF2FM4sw/t6m+FCjX3oHl0zUFDs/HfDB1IEXz+2hsgoR9SYF+bXbSth9Ql5SVw6WlbpS yFwlhS2eW7RGdfH7yFg8yRwWXcYySMv+L+udV6VzSwe0SODgbmC4o26VRMdm0RBQjLnYxl3eT+4N Qf9DbWnbFLLU2LtQWORMV3hNidJEmt4J99c08slF3izsh110Cv87/wiU6Xuvi2AB6jI3wVkno8/h 1xSxQBnRHm/fJHMh/8PrydoVk8qMhMXs9UM3dA== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block A3eq7CQ1ZEC2Oz4Co0wE9eavdVVL5N2w7vnxu/t08WjNVvgkDcorbVB3GWcUKigHFQo0FHxElw0D PA15/K+npi+dagAdVUmv5cfV+KYrdhCLG+Kvl0Tcm6fhXM4RH49frRlov9a41BctZWlMEXzlO2Ei 69nxF8+cDN/RPLjSUoKp8oVTX2g6+udi83fdCBYaBZQYCaaDSNeGqephcoL2zlXyK7vU9KpsDUWJ oZshHV12Yw5hL+4YuSmKv1aODQadN1UJ8qyFc0vRYTAqwP+hcDUwxiR48olGBo7U7czJnFk4AkkD qULDB9rPKRIK3YJacz6Pp3GAHUDGm2JO78Eg8A== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224) `protect data_block JcYdUx53b3OsTtOdv/P3/dHcfx3utNQitl84Eb3aQ6aN2AhKiDHBCYuvObX/v/9/q30o29Voi9Xv 1eu+5HrxgmBEFCpVYOVqTx+/1TnGsOn7DKuzvOHcne9bSxaTDrHQUCa38xlkHitY67JkqOSIhVm4 jpO7JF5H+JCbmXDt6F2T2wcpFyMe6Oyq6RJfEQlANaFqDnOQOn74eKDH4FfNR3DAsyf+4EzHf5OG TW+7XXmSI6vfomJkezPGmHNVoROjvgFnK7TnF0VmsgNYiKlql/PnEKKsUxo7PMuYq6GHoxcRo6tI +AJMZXAcc5avne6SU/2mOc1O1rYlDfuMOYM72e7no1V5trXotFkDNz5Yw9t1TNO5PzYih/V3YVbU NDBobDLVy/wQ7ecc0PsBimCh2Y7dqxU/EZO5RSJamz23VZJzVUVgJ45yBITzYoilSrt0WNdaFHyC PWPFiPnYKP0yDw05pHULxNgTnxK3YRDelWlT8Le5QF60m/HLUi8Nyi4fLPTjArMLSc5DKmg658jh JSjyTrQq++qYQaFFjKBUDtVvAWZYVhPnCexdXjRceDsgeTaL1yHhb8dS3xjv6QOjRzHBL3HR2Ob5 H+AbHQEQSXdGVxRnFCXi/TKUvtom8R7+JjrA+0H8CcmsD19UbQmxBAIgVidUDxKPApBiSOboEK1x FB7wxHjCEI+8HPUeIwoxSg1FWY9CWrNhv4GbD+j0JemUcvG9HF+3zIwWbp/5UG1Z4uD4VYnIGsT7 ozoOFMVqAbZ9MVvvKWapv0P5mEIR6VlYk3l75W/7tanWiiOn2mFXHWzb40Nep2bXDj+PtAa317DY eJIwtVGdN/D22e6H24LqEMCT5OepE3aFof4S5dNwpe/x93UfOQs30Ddd+SejlVq1yxXLn0H6PsBG 2LJDA1F5NhqqlcVCkAuKwjG2QTvH5xG2s2mBjJsZDcB5mVc2E341U9VvVXgaof5srM2G8VPHbjwv DXh5h2kfGC+1flf2tSWIBfCB9zePvwkF/0HWgEUaLfu9AKO9sJBs+saKvXtVjYY3AmDruCCXM26z hl4STPxaAahx5qIMIXOmXmFBD9wypKP7t90uopZxOSL37I7VO78QjxQB0+h89IrOPr/h3l7Stls3 ewOcb6q5Gu0IOyJEW7lb+6eXgSWd6x0g3hzg/N/0fHiWVO+zcwfulD3tlAEoE9KyD4i0vdFlepNu nehaW4Kl/Hhl/1NzQ/03nZP9nkSMADlhZm6pW4XVN1+sZ2EXsC3fe1zc08URdBUVJy52cj/GAK5+ 2r2x64XO8C9VxmE1bQzv8MFRwuIYwXfn5XQLCu7rRvRxHn1nhqdbNOfyQkaftCvt6pn3YYMqCEsh NaCh/3weMZZ4R+2N4RQjrFQJ0LGf6cr9DluL4GBsTewvbZWsSk1RPYOSofv5WBejf1lv4vjZeYKx RT0N6mYldxbDlWR3AdlUyhsionLdPrjCVil218uZBhEBmIUJjEj+IIixWvDe9zXMdMXAfVeqpZe5 iqQSeghvfFX5u+6aI2+Ysjs6Ee6x2Z4Sl4txYDlqsF71hPL2hXSc6O6Lu6rePadCuS7gF4Rym8ap yTKLTCVQAgHEZym5o0HsXcbzF/5aPPlp31wgnRZmfNLo2MAbQRLWMxImz74O29tn8MGcexq3D763 RrcOOFbske3p1O7voWsQMf3AsMCkdnbqqLGvM/KVFvjqoISK583P/ZBvCj/dKJWuQjiHORGHhex+ CJk6OvfiOuxlB11yDfvQf9E/gaw2yiIbz0M7scZ69+/8as+HhFR3umpKPNlaPOvlqBl73MtouusL kxQKrCgQpSj7Qz9TERJ471PsJouLReRBseMZ5wZBc9oD/lblzy0p0qnJaa7AAmUfPxj6GfEm2BtD Ltq3GUYuAqcA5UHCxOS7a4jFsBN3Em6nYBPNTjIQ1GoTDASpjgEbjJ94V8PqXr46HFPrZbhAJoh6 BC7jmwzTPL1boaxSsIHZiq5XkWjiG0Fl2kMRo9pnxn2Djx1GRrzI9JCNWjeGEje8mNA7/sMq2xGf JoX60sufhWSY6pdJOLeF5ykh3P46LEqWul5krASGOygQ8jsElx0mqMqjwb+rcDi+Bjvk8Mpz+TMB uvf2Kp7Y/jjNDWbMbS362U1Rz1ik69PIdnDDFhoPs6s+CW6/XvFssTPUPaudKJ9nNu0oEDYW7cjn dgkTk8++gdo8oLTSQtn/RF2U4FWmN2FPMb9oDXTciVWpMl+r7AfNJpuQ/2qFis4h+iRY615JsAJ7 NrGL/DTL4CzkpsLzb44Im1Le6aGOw6z5DZBueGX2rWkGPbDzW7IdyY0X+JRZlgLcNV0VUYOjrg1i Q9UCKpY7g3KEHrFiBjrZkPVrmQQWHqhyiTEAjTDTMgaxk5M5wWGtMAe9erd1WbNWN877pjT6GkKD oR2tonp7V0nHHp2Y9wkittxj4vvtES4nMKMle3rQNn7xz3s5/5wYLOcyKn+J9FybgXezdTbch+3d nnmF+yZPBt4R71KvlR+NWPI2QTnnFME2T0xXQOpkX9Rm7meHqjpI6cUHaDWKNDxSbZwH7ABw2MZQ JAFoCu4cHJXWp9PzgxPtuaDrEgxrisO+kyIDzYu0bhr0sE1euNGSHpE7jR2flPgvS3d8F6mzkSsG LrhGYr5DYGHY3XyRT9mbTgCpgq9+vDOAHnOPh+s5IK7xC2BcD/aL5NLUWbvxtaAjHPhAVXoJdwup RK3PBpnBswLbjodqVTjZaL4FH79yg8rOmiOGwbOcEaU1+7vhBSX9+Dk6xqZontADrIkL/mI6/lqc 3Ojb8VdJOdxhWKZ0w53OFUYxCLecLiCeye9ZFo6Uh6ZncDqgz3jJFTXhS0tH1j5aHfXiImxrPp4I /Qmpiw0ZKIaqkGBKYY9368wMcMQNLfEms1B0JJsmahj1namwvs5DE8cHOO1LlHvPOiPm/qFRWTsp YULmolXqQN3/c/nT2N5bOilFSAj+w0cMfxlWIsnGtGt6x59GN0AsG8PvKo30zEsrjlGc5gii/dwv 6XUuMnvKl+CoOytiFqMjMFV2IaP42joEd4iocd8r/iIOf6IYliossSyQRPFgyMTvcEpKf/AMNPN4 AtaJ8dUn630dEokCmuq1ydM51QFUmf28+9Hy7V7sBhKaMz0J48hve1vluXF+5yy/IpIO+KRooQYO V0mXcy1Y/RCsmzVk6NKI70DO7/CeSJbZVMig7igFkjxDoi2NzqRTkpd4zAjDpUnIwfjnXZBhtraG VjPyVRAydV231L3nsz86ywAEQwWGBC7je45ybk7MjxHAN6D/lieDBBVyq2DVXo3qTL7bhVylE4CW uWfebqqYrXBCii7/pXCvLhvW3SCziIQc8S8wqpaq+J3BoH/fnmtv+53dEN2zhD2Jrki5jpxVMNWH SCaBDh2r0jwRJ4zkidB+kCuNyteD9V6rH5a7BbKEw/PwqFZB5vQScCy2rz8LJ4lMvDcl937sCcXW cpcm21xpoSSrEibBkSeZvqz2EdAvqiAHGMzjdDbfQXMnW/sivNDSxFCxvXndmzYZwvOUArLN2t0R aQZwzyfYWHVx3+rGhSePGi/njGN9N6sBQA9Jl8EMOwt/2rTVzvgNamWDldYkkwTKdWN/pR9tt7J9 y6YlakfarE3ffId0LW7zpmneR0naXLxJBPT9GqkXEy5aYx2UzAm50SWVM2Pbm8i/s7JQDfBSog/J O44R/R7AEHGp5iIRokL/fQqohmHLNJmc1iQ3Ne7fAXlOH5MOgBlbbZyTy4PQxZ+1dJLhSHy7aHoT BcQeS5aAZrRMtoGRVL9w8dofqnynherR7FMfx3nLQlUZqgKvuzXIRHZEEH+2gZooyUn8c6z8r9/W bbz3HVmF+J5ytAYVq6TAm5Jp6bwZ+YJRaNXxiaqQTWLYDeyamHQeZ4PVMP7Tel0iibLAKkHZ/yTM L1cnxFm7TXC470HHRqomxUoDy7YMsBvZdPOwL4zTCDupNCS51ljfcwj73VPL+deuBxkEeMlh1npP OVNqxyQ2K3WUbFFMZaCcf9NI+db6FQAm//ghHe1mIOJHwUmAUwnAOoYKeysyzLQiWF66UuQ0vHfe oeeb6X7UmQyIitKPXi9/8vZo1QMrU3bKeUOfv/Phvaz2ykHcnLaexeXHY0odDTeA/wbmLLMbnU1Z F14963JOnWa8EI8xVIBOVCndXGs7dHcGUBecRU6D27/gP+MIcbUyu+MomX5Edpzw/RlQMeTRUv+X gVCepP5hOwpqNENL8PQoEd1+l3QN+CmDrpqxKuDbMruCH1klQGi2KyURrk0xW3tvRx78BzADC6z/ e4krry4RIbgpjKpCMZ36KJhZhOJ4XrMNQOASJHrs/tvs4uubgKfELrt5ffESa0A8mbpQBU4diU/O jEtRKd4epHxn41mOiRYaHTqpSDWcwv6ETHyqceJCAzmPi5GhHZ0aUYiz3CIV7bOvynVTC6iTkNvY Fjc16r6Y1AF4aON5OX0kVZO4WQCBVK/j9xz+kFdZtK0WUb96KOXdn8+99oQp/XiLXzlmFCTVa1hk YeOIbueyaNdKmfjdONFE0ucCtf7MOuHzR7+0E7n9J1cqzYbsW6LMHq0kqwSrE3z80zKDhaPL3ZST V89l/yh7jw5kkbSnMy0QJLDrU+9YWKdtI2UHS5hLThDdgcMhLv8XU0W81bhsd53nwoI/xPyUKmee lueOrrko18nZgmGewHoRSJErs+j48xiYcWr0OGSVq1E/EXQp/I0rnG26R6ZMDUS1UlC0M+yzSUKC KeNa0JnstdmEiAcc2NbqwAkyf6zikHbOmZu7fq0kHO92qH1uIsXGUtn1PPV//e6upK0jNPwS4JG6 W+fAmEd5Wz/lmsUiSgf9YXz44Z2i5CbWP2RuFFTBNbyD9LFni/ox6MuVOkBxtuFhmstwNT9gqMEd lDbiRGAzlHSBvDfYmvS6pt8YtlIsL4v2RdpKzxu9okBFcaL4dSPCNv9Nde8Cr8h7DgZ5ohreqfr9 r+hYLwBRTUd7nyROUSNYtamBNa8gFFkrWX4gEkuCTz4RW9i9sIVfKRQJ6QN6IticXRe5Ik1GzcO/ AC+Wv6GYuGFVlU5ymWRhL//1GQ0aspVTyq27DhWucO1AQmEH2Le4QTUJzg1zzS2qAIB0TN1lfzRV qz8RrNO37JkB0SfFFeqMRwoEpRkx6p41enKF7KhvYyLK439yo37yRaQtdIgoWEjrGq743/rj3eMa XfbwzE1IBPNONtBtmfAm8RhCZDJyGluA7z56GXCnPdm9fNReTlz7L4m2BfO8oaUUr1WevXuYAF/Q HrxDyxC6BKRD6JWGGNRN6x03NgBssWWLrfVqn4lX85iBN3A6pug+7r6Y5ZNkfKU8FVrbuOqsHlBI PAaZ0qYincGQoNZs604N10cwNrizRdHbbygRGdqZrrjOX0y788Fa7UrL9KR2mtaO4x+emY/LamW+ /GUGaVhUYUu4SP0mGdFvy9IBl7ORg9VWvzGPQArn2YJwA+a6byIv3fJkkn09rPQxk2EzeSJ7VdO0 2qT/qYJhZoOb0fBEESWBEAGYed+4pgpc/xPo6vdGPYRmxQOcevPZFCuS9f12/LBx976Lq5E4GdKE BnfH9oHmho57b4VcG6afOLk4VfiqgDpH0oe8+09JtJvIXfzbAHZuNc+OPKf1cgMv7jXQjMhMwkzW 8EA+ZRCMwXy7HedH0b7Lriy/zl5fVlMDRnzmi9cQbE6FPQ8KWLfYNK7tU4xsTaKOHOLDvmuGVpTH ePdwPKG+N3CqkoXNTM2mfLtow7XbNKflv8klPybOpGPRLXBNlQoXyz2oxIRPAPtIHp1EBciJSDaW nlm+7Ykx9BI4mAecCUSiyCUGdOhzIA+myCSX02+Q5R8U/4PSFhNgbZo0PVJSs7xBdgq23eVrYHPl EvhwBx9wyxbasow6R6plTcXdLVyxaVVNat98d77Yi67juUARbex2GWyi/VakJtF47wRT0izyf/fy B601vCy+lGibHhtljMWAm59ahjCseUxcXcY2mif00YPlwzzgR6mMzEBC97KyNB2bvknFAvEXENP3 1UqCTPvZFCzxiiO0TqRi2Vu7SPI7RKcJhzh2gZSXBbHjUBtKheRR7HKqdQBYG99XmSWwg+DOfq0B xPCoFTLUzkSuRQl3CWs1gSCw4WaDaN8INIFw5NX4CPiQtmu72WOpCEjqaZOLS+UFqQX5i2Z5lWMF KMBLc/2dQt5mw0aXUCDvBTgkpZJV7/hejuiGISy5l3doCfteWxAplUsqitu+ykMLdMjqIXuAyFLq ETohUWC+tHJ+VY0kNxhk/1uSSlzx12cvV/z9lic18VYylN6pzktvG+jRrhBVo73eIDgIIv14BPrw I+lptJAlOlGsafAJPMuYvP9Fw5WYky2Y1AqW1VQ7a/TfAHjn01q02r2Db/DtzJQ8DRnVEsNr1rnF boJhSaFcZbmi/Kx4/wlSQBpqA+AJWAS1SP3eDPdv9TA112Oa22AUIQvIalRfsM7LxvT8eCgi+jy6 XJ1azPffzo0+yjdl1ZT4r4RQ8TB4x2g+RAJNx05n1M5fXymF2Y/YR5X17uGfyQC9zuB7kXZACMFQ D+x6zkLjhZankOAqjdTeikgRRitfIf0urJf9MgP/anRKHIUiG045w6kykistBjUIeQ3XmRT6Xll8 KeE+lRMdmwh5fpGykkGVqdOG4syihTbZ48iNXfpv57sq3D7V0bWkIRAh/pi51PQXWQL06zUeO7r/ DnqH16ELZfkt9Y9+cxFiHNVASWV9LH+ytec/7jJilZovfl+OMm5syDPatNIjxS9KkAVITSJTo5lO J2usU4984wQ3QRmJW5QHCj1tl1P7E6aVVxBnNvUE7+LbULBIM8hwbcwsnYR2eGZrV+krufP78VXy b0YVkqUVqu6QPS6AlfPLtllcBMKY7o/ahkMR0mPLUqwUTOt54NFhkGz+qcX6B+d0Via9QyD74ira CU6sVmDJkm7Ce5UkQz8cYFZRQ/w2LrT2Ed4/zV0s44qhChpbDKHN/XLpG2k8PWf3IDInJpR0J/HR NCkInRjOI5skGW48TGGODnJpfi1vUawK8EZW4fpSlSQO2GYUaL1YmiyECRD7EfD/ag/pW5ecJHmt UNqo676wBpztAKd5JcFwFnNLA+WXgotD1W4EbO//gXt/rEJ1z0S/L0CDCtVyJK0E4qJ9CQE8NxJp wxgdNgL+Iw3C8MRK6ty/XYIeFSvudQ+BWxBp5ZVdnBYAGzEuTxES5650IFL17dwAGQ+aTywCXI6P adhoH8ADojBD9cN8qOaBoLI+xOhY7BFeCrsdRZELLmDYHNgSBR7P/iMoewh7mHqVkzdXGq0V18PM 8fR2kB8odtL1WYIzgeoJeo4lNfL30glLNQhgEQOa/eaOJnS8cZHacut338uG6+8Fs2FEjy+aFHJY ETIWZn+hnhvFaZLhTyqQM9URooPYhJ5Czpj/l2RvPed63LMNULVRalShMU9+jNbPxeYxYOTzQ/rB f9krblIuZE3TZYYPNhwldp4cj0ggSkjdf28lF3219361YkXf9J7ghLDCxBk/WzcTJlWHmRhp/np8 mWRyZsmsKoBzBdCamBk0p4QkIpJJRvIZpc5+Sso/OffOtwyXjjtr4hYCsIXWPRAz8EjxUTshP2QR aSoKIchtBRHpA02q1SEmWRSs7OMDm8uXxgN/VaXhaPa6wCqbKDL0fk8tZaP3xxSWKU4vuqLutX9h Dnm8xXrdk/o3Kvy61T8s3WFtVYxP0Q/o0vvlZ1Hnrobw7HxUxuneE/bN1QDXzGVTu0UrlGYd7Bpx qtkkAr//N5c4wlMGrzT8HYPzYKLG6fpv3sVxoRPZNmD3Bxc8I0+/f4F+Q87NIisF/zU0qALx957A LufULMilHM1kCVN4BY7Q+LB3Pdn3M/bZb+n3vzJ5dqI8PXZs1sm2Ryfm672gKiOKHTghStPmrMzY 5MLrmhRn7QFHYv6u1aQ/9ETQDgaLrF7RGwoyVk4x1cdlw+VvPLV7BXjUjPsI4e594MK22t2/QiVF tspBL8yFduk1taZhJ7PDwB+bm7xTWUWC417C50aOqQ5H5A/F2m7faSP7g8kRlqytknbkL5pRol06 MeBV1jyUz6DuDyf2plkgn/DDOIxUdOIw4/YyJv1VZ2emWnkTKlEh5lCkVXy9H5mYTKWilBQ9zBAo lUsNnDI8aD4S3z36IW7T5AuD+NQiPyg78T1QiwpUuq9hr/2ocrU4vhexSz+cP6diumwEQnzs97R5 p379+2H71G5pQQEM+KJiB3nvMG+d7EqTDH6U+iLtCpvbqYCscGkAvGQ2D/uwrK1I0xFQ/5HM7QPS zUTJibf5t/XIH4mvjKmGobAbqZkRmPxfCdTk76wwpy8tFca2/5yLehDfE773G1apqZXK6DuDySNo 4RzwtVJLKjuVl+wBts4y3dqY647qoKr1lWi0Nyl1KIH/Cn3Efv5/L1XjjGj0L9UxsXpxNcQbrZoS tbnc6s3M9h1YhYkLknJggmZ8y7elf5iKpzrBvqdeltXAZ5SD3xr21im5/RCxsOe+JA9ORkzw2C70 eAsPcBt5A0WqXqSQ2xbvPOXHrzgjrLlU+TXmAoCFM1i1El0Y4ylbdaLusiLdAM4uwsPuc5UCxoy0 ljVYY/RFA7wMbK/JaiKALb8gUpdmGTs1wfJgxKIwAM8yZNS1klu5fJ1HY7JFsqF62DJcivymTMnM nf3gCJ5vfg+LoAStQKYKCgP4Xv/jkPavOJ/SL/cEclAum2Ykz/HmFCBIC+bd8u7yT7W5SePoxJEw KEgCpNPn27kQTJyDgYWF4hHNLKf2E7L7AR5IHw2c49E00gwuW1WuISObl0c5aZgltrb60GsYxvEC knKA1oD8BAUfNFMGNa66ej7jRlrbbzMY2L9hdHMEA+p3VLEx8Au9b3I19PjOUzPa1FEeFY7b3tp4 wgDW8yOEqcLW1nmz/8mDKQUtm9MM9fAVi5DsVNfKoRhf6uL+5qK+u0/2mHJu6HMSoSBzfpWpZVNB i+otpbVNBOrkX3nKfwMPhmFjfkJ0nQ81rcFeO2QUUC8LGKal/1Wsyw9eIVanJt8d4u3rweSnd8/b eB4KYEaa6pIruitbg7RmnZOS8CSb79Ut8NMGoiOl7LT3kQnO7/4fgg5VNeVCHobiXVCEiXEQWrSb XfImRKyx8+zu5otLSggxzNiym9h2v8E9ivBQsbWTooJjX7+2poHqVzyVTn4HwbKcAksTBwWPcpJz GYEH1RIvBJZ+iqX4Z+9GsxKOs/J/FZMwFcaNZM/BvHGNfgQzN8grdFihcBaiiTZFf3CvN935mvSd wwOsoLgCFZsL75LDt1vmXHytDMPpPTQ0cDv2U6baB74MBU1aFp4auUJ1gg9INJZswLRqEPxjhxT7 pvqyXzxEugYYb08I9PIKRTa9WsC1ZU50HEcNzYH7YB5dMbYTVVlQlIi9R9AnN697NzQLc4nOImjK mUezr2B3YOd3qvT8SpVISiZb5PTFIrqUi/SCsQNuQwWZZa/TD8BjsLRxARC4twUHG1XrBIVR2gpW 8pFuVJZ4+5XJZcZqu7np+fxFzGx279Re+CRJ6OzDed6LvKJoz3QHpJsarYpUJN/ZREIuyLDpPsDO ju/nMmkkhGuBK2E/pLNJTnSrNIirAlWWU3pEyOTM+kv/3uR3mqrAPPXMkHHaWe33GKulRioUI+jW syslOFL77lyYEc8gULqjJkGD1kdEs+aXCjG/1D5RrxMQ+sRWLnyxWYKuCQdk/3emZ19XI0KDph/7 p23cMw1QHvd7vJYhcF041ZaoDhoeEaIJ8XmYgmNI9PUc2U3EiwV31U/uBwDCpoYGXGyojA19pwt8 ZNHUMPmI9pSVYYY2NvpsBuX6+koHR4SYS1YiXSGo/CLHKYWoKE/swVSeR9R2J3X5tDHa9e464wgT aUd8ArB5HWs6Mxgmi+eglAVeIwYmMODHD/0ERj9LHA5AOBeeenieACCywwu3YaHgqUVLirc0b3od QbpSiZdV72iCzUxKiJF/nnCPPeL4WmZ9dggPJuWSa4UiiRAkc22NHu9ZbuATZDJJK1xY/KLM44c0 19d8aqVLkyYr8XJ0VxCpfQtoEgyGL9BNW+E7Y6rJbzOSC2RPNW80IrIfSQ1Jxahd8mQDBGIjgz2B LSa/iitquayrmOMwY1NnmVve3zzW1f3WtuIWJFYIhGGnx345jyarn1vOS3Xj9p674sTITMaZiVpR 7pI3JJ9U/MWkbAjTv455xlDdsFMXDfNVs9VkRAwqaNx6KtT/VNytZqyUCaFRSDWsitwmQdr0kSif IbwcRmuAxF1cLZgKgAg7qBKCva29KuARigz5TcIv9TDuwnFZxgC9u65AxFtNVH3RkBvD0rPD77pf maxYisgU3WJOvCoYRg3xJ0BZ4nTGlrAS2gqqMLqWEKTNpaF3EHZHGOkADS0DXhXHqOOjz3S98dAo 6Dm9WcOvhv7d6l7JsqujYrVevdWtzFbSuJAYSaQIla/pOWRqAsr5Z+CutTwQX88MWNgT11jrOMkM sI1ZpRGpTtisritvFIxnR/2l+sZwlW94qoj4pgIfvW6DLQ4xMKU3TSvp9OWCrYu+YLULCZbDIwVE xIaI5OEcOAJG7r0SZtE6X12Yt74R+4hQcE1VJjRbrcQrs3v5gJ63KrDQnXGr0U/9fpm9mwxBzn9y 4U6iGmw68kCfqv94cG110M7TYvBVexdMiRYH3gE12bLE6aS6BWXq0uS/ThsucyScEGTXRQQicIAK 7IDvIbuQ69ErdJ8+JTZe8hKbfGACRHuuogoL8yxY8Qmmn3p8zSs/QxPfARNH6NRwP6xd5QTWRSU1 /6F2t+CPp6Jdge12ieWnJrYdQRPsieOL5QtMOsLTltHt/AUwRxdsG0NTvdY6sH4daZ1JrbPWQZ1e ba8fjhsgT2uMXjiai6sM9zvbXhYvc+ekq/6EnzOJ4SYZj139ygCvK+FsLxvihrWe9wp+rhUlNkai ZhAQ7AhJ0He2berfZrFTPCBWNpH6ey30tkTo6FzsvvCdXnqiBcUTaPc4dKyVr+WJ7S1ApSz6GKH9 MCgyAnSGAXw/J7dbl769zy+AUeTk5bjK54sD46dXM/2tRMT2UtLdA2KPHrkjq9lBh+39412Q+pyQ mOZrpp161lq7/lVVz0nsyAl48sif1RhhAV26x9/I5vIfQ2oF+WDuBIZoggVUF2cQ5NrdW47tTzD2 0cncagjmIgdzMTSGXsgnZRW8+NV0dN4wC7PWxgySUYaIEwmWJXDa+cbnfe1vUN4XMrDHvPY2Q94g ymEPVfCj1DPMhxsdKJteB4IvgCisPRUBAlOG5rZvhN9sV8AkokorL+2bsyq1RvyDMVAG52zGuYgs Yk0LeDPZt26Qp/lKQlwyd7S6k/Z6l2kGfkqBAyPUSNaDdyVUUJZuRk1B0XW4FsxAMfB9SJThPrq5 bguvqBKfceLelr+Dz/qlXIam1Z0ZeGXoh/grHfJy8Z3Grh46CXKlYFAECzSn3qBmFfgNDP7IHx+X DlAj29MklmzDJt49muk8qRTiRDBsQ6Ncre/EpqW+mgLvGWwyQS9uvaAkOSHewnijoVwQPhJUzG8g lrryRx8V+m6sBE0N7OEiUT2FJofYL62FpV5M8RAAUzbQ1Axnz+qoy9sKUQly2sbPrdb9Cdn7KAek p4De0gHdIeI1gfOcYC9m3IrJ+zOaarxywNN9nMptAgCmzM2MwVO+Jw+Tdd1OR/vbcIICIhIo2doV vwN4s+HbR7n68+v/jkG+JEBoxvpPiW6uDtd2pDR5tsJqwHrQWsZ6pvJZDSUwkj4XSrCZBhhwwurz O9A2K0VNCFfR/2YAP0GcnqKD7G0zqqfeexODeCifmWoKvryXu+BcBGnuRIpefnlhT+in8FVF1YN9 ZOYJY89AuhdE8DW3mtEFyPpyEdghzBmt0LhR5lUHj9JrY05fyD8TCV70Wg+u7W2Fe0dKLUV7Ki/+ kvPPb7V6EjWAFIk+MGOAv4o9A7SzzhWs8beqhYfAObTEmDEZqa1gKUGcPnJJo+y4qPYJplmqAbLQ 7+uxBNRjqoYYCYPhq6bdiKY+lqMWnOr8cCgdplkYZKxrbIyCFO3/8X0b4CzoumCs2fO5EsIceGQE ImryN3EjWshlFGDnocxKObgxpsKRPoGDPVJoIhfS+8u0bA3AC4TauUsKJypkyohhsEEU+Fcir/yM uamx3cY/LwNyOE1JqZg0fz5ZeyAxLADrLGeUtKS1IjzWTiNBXWeNeOx48kk2L8jThLBNqP+UlZYk J6MoCz3puRlkf6pC/v1dnvJvcLK0jeR2dt9EHdz+joD7/VoGXA8CW0WjRuE9JypFb97D17ZZi9iI 4z12ubW2sLjwei6XIetG/cGRoRCmGjp0KA16L8XrrlZclGYtIE65YHw15YVdwFZWLbMTKErOXkQa MyQbduPRSja1RMfVtN9tIg4HMXMcUZTC6+z7lKRjx922S7B0fHkAszrLZdVmhCKO8WzvTOXRG7an QbWoRzU0hVZqj3xVe2VPBePUFEfD2nHTBNUHjl68osL5YlQpgShYk/1eojJkxtYZuOMVAiDgYfdM l+LAphuHNK1EQjchqQRaZdV4m4M/DVakoH8f3JOi8lY6HQDeB3VPC6OMeGYTyNx/9JpvxNiY6Gd2 ck9XazVm5BRSauFViMRvGT2uy627TiKMM/JMtTKCPUkraQM9ZoNNePAVW41eze52GvjONGrXFkrk akjotj7v3x7qG3kUQc9Rd1S8qdq1T3Pbz4V9X/lEm6i1el/NrTcVrVQWr3RCxXIGzG1brM7BH8qp tpO4C7xfstbzSvgxVWtxSLFp9iP1QV1BP9uJ5KZ4yxtH/F8J28r5kDGgxwszNvtH4+FfS13SBKuA Uv64P3f10hddaZJIMf33Og2tBH8QE06xOhFKOZEaig0wnI8f4UieZKZRUqmQtNEuAiGo5kVQKBSB awFbyHqyje58KFujQxFYYOmv+5y/RcifbaDMo0rbI4cl5WYg8QQ6+mbSFfJRU/yVBjEgy4FZlRm4 0hLIJvDwRn76XySt6LRXBeDb0tCmPPZEkCSe7AnVsbG4R/UbFt2DKjKbl4URmSvqzQYeI1/fw9Yr xRpSdi8P8CQWgbKCt45eINwGzab4sr7cSOnhHVHwMdGARVF+FSmX089gP+U+cmQK+8bWgjeucltf 89ZwZNXNSru6dM1S/KwBkBh+04Vmyln5SF/DDM3PuSXhYBl5FPRv+BxEs0AnP2+dC3Z60ytddep1 iJFCERgqzsTG/73OBNeGZi2D+hJ+Hn70qKtnJy3jtNuq7jPGgWM0ifgj4DVL78hzOb3eUPQy1M1W vRUQruEyOmZf3FAwNpQJnKEm2Xf3BeW6ajE5VkIq0M9VDFEgtjC2wuRg7v9vc81EIIuIhQYtktCY 19Cn6E52ToW/pmHsGujHwgzVpaQsTvWiQlo9xdW/IBdKW5LlJE7KdxsCxZV46+TGokXVVuByXnab ky7XEeBEkFwtLPxHkEcVoE0u5oAbH7StocuhSuj/45c8+lppu2csOBRjeRhNU+WP4Ca4nmWPUCTj qQZYcYC+sXEsy5E7qFy9GvPqGtXAUx8fVsG0OCWEj+qERsXfS5gMM3HK16R6eQtKuOCeV09A3EkW +vM9y+eNQL8dG3Fi4SuKjdD5ZyiaZT7yRw75YSy7euLpbBu9JuVj53tl/wXNVLs3r7B5w2+8KPSy mWyVOI4FLGN9wWyy7E9bwaBw1VRmXECID8mllSc+e1W9DT4OYJE3gkfjPHeAe/eh3kb/tvb8m6zQ QDQPrN1yHJP4CoPX+dwr7Ott2AerFjgPgMCmPgXeXe4B3d3VNctfvYVPcChKZi3OgkIWJdLjiNNm h3TzngBkmOGbPwv100TVzJcl7gzVHi1B6DbV43IwICvL4Bv5ljKfTHch+57iXykuz9HNTUcpJEg9 l1gajgzcSNwU3jnROTUuD8KSfwUHMwQoglnunc9GQIDqQtxCqzLvGPuQf/WeHxgUHFY0OGw+/SYo FaFBA6vX3d0T/T0GvV3GCNWQQ0/1IZ62AWedi/l8CR/IG4ymQ4q9iMQ1kWh46NY8ujo+4c3vGG9Y rWj17IrnVuEdMvpfKBpvifAYOxTk4f90xGVgl0srnhWjFhWJCKODlxaFdvm+gSnpJAoecINNyM6X h4xtsNbzGa77eDLiWc+r2GcafI/l+F9aTTn40OdNJl8u7lz7MG6Hj4TBgAWGXyrboeMP+Hmonwyb wWMVRuqC2Fj/X95901o7T73hJJAOlUSWuor9ilpcIpy/bzR7Tf2KCnm/JS5X3Thd5m/KgcIzzxiP 3/gb9OHU2y0SlrGcqSDBkGTQvqVjEtav7WL0noGT3C54XiKGlIbbytZoKNLe5fbJY260WBI9EjJ+ AEkGnSzYXcsjjRv0TdedQUOCrhqFMtS4wXPQFx6M/VmBiMrsF2Uaa7nqfxaRRsyVj5ih7zAutcYc ehrvYTJous7+AxAotI97YRYRcoweGIwywE3seKuOia1iroengMLFyb9kYZOQkMQG3/QPL+qijt7b ipOPv2KK+aIn6XRCdgHmXOXTuP9uhPiAmYpLSyqsQsmnl5+kWGPgsig/lWB46DiJHyGlJ0/BdCwy +Pm6mwINdDIPWqAu763b2qhTbnYdu8UYW+5m4lSWf8l+iZbZidb5XeSPg3k7IqNDKJpH8/XacAgw G0yC6xiJe7IaoqahzZzsWswmrjLoTIhM9LbKFtQaza1Ntd8+BiAVuoYAbWbM/AnWLUXz6rqudqzq 03pICqagICTZS/0R1Z35Qpyl45SJUOh1SS6WizvdBWnTpvNUzeJt5vtCgiPxuevJNkcS3f1//UOU PKpOowqBZH6c/vjg9u2G+0lVQc6wwDGlI62yBdejy0uIDOr72Y7e56xe+IloQAMckshvrrtEOmA6 0mKiCNdRVsoOMKH4VB8iO/0ZRtU4x/cvp5r3FYviaG5/t76Silqzz17b8u3HHVXXrTQnnaCXmQGc qydebcQ2IcCuFInPWJmDKCVHYY2hpXgYohE6x6uN30Aoz4j+3sEpOlxq3T7OitRYUHi/KOXQQ+NN t6Nl3/E8t+YhU921JnOWSvOFPd+LfwOBXFcqQSTfEe2rO554H9m19jMUpBGrVuXH7vePL9ibIYQy Gy39BB05M9RCvhM1L37KTtkRfZv/M3DJ7VgyHAYW6TEFjtYA4Feut0m9fJgbyf2BhFhB/7Rs8cxB TgjXxacFR2xRLP1T6uFkGbvCZDfllnhqqIhy9dp1gNz0XKOBwv/rQhrSfP4p1wfvapouBg01O71h W/oCXDGmVKVFcnCxlWOdT4z03K8L8TKqnGZ2gDc2UDxfXbIFhNLM1+EUjedcf/wfyg+Iaoup9iUV Pb8f1C31P2+d8IOmtDFW/aKLcT63oF8xgMIQ5kDNDf1cXhOAsKqahR0JGmmjinJDgQZUh/8xJSMz 8ncCzHJmJAvJR2SQc5Smowi1caGTYSrDqIPmMHWMCUSSOkhDKFhMdxz0YEsC0qleBQtyICVWm2IM xDa6DZvDZQ4GBGuPNtBFXdTiFVKJrhpnf0heLBsAxkBuUbF0BhZLm/asrAX/emp9eFl5U/pliQQ/ be748yAL7TtinA5NoEY2gCsCPw/vpr6D1Tl8BTnUktJQfsJSseuH2gcvM+6d78Cfji/+meOLHL7m NQO+fBrdlvmZi/Jzt+whMwM5ZhxDGgPbllaNrEg9siYK3NZCZ9IeadHUg6USFU9oyWwHrLxrDpvO ufoh9QA94CDxoDpN9AOCBCRdbxHYvOkwIACNupqKuE7IPIM5hP1WLT2hUQIigveMYruSXIbz5cc2 lwbv5pguB9eznThFkBfoYWfpWHS6PDtf/yRqD/YsSikxSvm48M/IH1t36foasHtH8Av5maQeAWdv WUPt8J5EpE1vq7b9/mfXiX3kFPrse31lSKOQwkxg6YdajXLYjbxokNf/JBgUfbwoS4E4oDhrocTV SZ2BSCiYqtq9sr0eEQs4zvY5w1UR0zCp0fw6EMA/Gi+GkXyR72BjD/h9pcvElZg4VpebVZSDeDLF 0/sEiYko/lLI2J+82jyIwfdIy0wkwHUe0gsdrzlKf0Yz2NrtCMZkjjv5llJFgagcfSS5lD1mNxtS W4KY1qkjf8BdFe4q98WFg7sbnpybNL7bTeUlFgGRZFfFKRFYOfAKqFXvv51laNJlqC1hzuLDKVl6 ZPj9EuTAvaMmRNryR6bKHC4A6GtztdvgCvK88XEiI6irfRhG07wqakIehn5Nk92iRR0e0UdMYPWR qae9UPpViTtCyo6GYP902hPo7yvozwxtoKZvvRwNYP6fviOWHfyFvu61GJ1prsU/rmo2RAbNVWhi yrJxtbJZuHcRV3Z7Roj9AjFWPD/CcDIo7nKmxOEJStSBXtEvAJEgGnCVzEYFNX/+PkAHxON9hdxr smrCMa5VP+Kp7IraLz15Bl2lb29wYUo/9loS++BWMm5Z0d5kdzv4r3AOrhy7LZ26QhncntOL5kd1 CiwdMbsNkfnrwscqHi8g5s4ojWWTpskA/T4ekWj5TthdnbWy0t8KbaoWvgWBwqZr5o6v4HnPrW/J uoXEvNZ473ASwOPEqRNqQ+SlLeVEm/aSiyi4z4xhn1CNhCik9zc/XzJfs2pb53SkondFMWGpsR4m 84GgGc5wIFoVUjcwUDclfL2xByM6MXMwKR4z1sG+dnlMZYUGB+lkwupDW5xNqdlUEoxVcajmYlDv mrVtaeXhNAin0u6pOCPT5ofhFbyQVB9mAaAR7f/ZGIdWt43x7Pc27aX6Aa6P8c8V6lb3QJ396VNN 1u9HiN/ywU2SU2yV+7J19l2M3FW9B48g1bJgGLI6EsNXf6sLQWs94L+nZZ2yAu9f4M6MzPEF6+E+ DI9skMZfnbgz+1f0//1Bji4bVZtJWRX6Tpo7h9qFiYi3h1VMyNk3uKqGvyMvjzeW/vhVbre72xv/ umJrFxV5pAeQ5IXoLdWPl1MpvbO6+7B0aPFD3Yi8KlS+nWW/PW6RMY1IaMdhBU0g6FcpHiTEqwQH icS3CuqvOerSkdniXboBC8llqmQlpgymLB99445lQ7LXy+6T+rxqzGG76DjV8j72+Fv+lRReSUwy n9TX9mxrXyv0+T6eH4D3JIfKD83g2By1qAJIGo2+Z2ZlRVGBJic3HVwMbGq52wFIMM5i2UIzHgoN Ei/VHQFLKiTGBBhEyayJwDFeu9WezVibxW0gNZXOAYVbDgltbKjwbYmclogxPm6yJAk3wj4vjwfY aUwEx3S8sP0yySxtLwVrawhVkDi3nEB8gy8h6hRwts2W9+X9jImXQcp1kkcouPf4J2S8M8oJ31sg Ob+he6XOCj8bQYsvR9FLmhgLQGyIOFZdsyru1T6wMqF+Y0G0JfSzpFuipfRwBP8/oAbCiq8sC6T7 U9VsHFxHXh4c8+Ozd65JWq2h6IdMizWSc3S4Zh8tyqiDgoRq1y9feRb0Im15shQs8WhGdmHwWx6U UngO4UBkHYB6mYV/RAd7uI3/Ia78hxj5wqXMNW9rsOBisp19fk1YGuxLl9WRidJp5xs1bqv2+5ME COvyBScinwQ5sYOG3HsUCp8xvI7IxO7YoUYnn4xNng47eL5x07DfCvN8RgiXwede068/tBXvAMbu S+gTG5EJJnQ3/hu5NIokqwKcd41Nq+U+uEglWS/AJQ+S0TYofj9tDxZAcK/r2WZNAUVr5+6aXFz2 J/E221v964+iz1qcx/t57YTdYnxWLJeekToI/IZ7jinteFjAxadwilw2RZF/y6ZrzI9ujuOU3waA 5/ix7IfcC9rn+jtpfEw71qXrjzJvHsuAtQTAxMoAUQty5e5shU0hmRoOEYdLN9OWZmlAbh7wO3k4 FhBc6ZJiYiWjq0f1orgWRt+ilNyb/Fy4+uXe6XrvySx3mJJ5Wy8NJxgmKP/XWXAgsJfJUVYch6rD zBrxtANsDssp2lA8IrvzCvmty3iQz3Hv3xClBdW5hJHj2hWY50gaCzIgspntTRVRO3NEtA7+7nHN bJepMGUoRXoFq0/Cx/csKzXgIf/hddibsT3c9p3j8txs5i2y7PI9xllpXocnmVHYaSqeHJimEmeh U+vYrW3UYGuEXYkhU3AhJ/vE/ouboLHOhPWW0pI3x47r+kqMbg99VEDpUg9+jk9La4Pwa8wtDH9d Bt76gHiOxJgqHINu+91wqcahDkCALo4u89VudqE+8ddPLCUK8j+pqFlpHWskAiLY0vVPaJfaXWsh JPysgyqXWcnCNA5dosPnZWKvAeUPuFxehPN9oZZGAlLVJHuAk/Y53n3OC5451k+zsqUjN6Izn11a RRNDq17VRuWMDul8yh8ysoXtJGcNwStKmKnxki/dB+dsroBnIW1pST9UpqR97RKhbQi9EAcC7J+v hKS1+GPPVpYP21G0BWEPLSgFNNcDOPw0t6fvu6/2hwuVe3RVWFYARNR5p0voiVXFGs2HBrm0Pu4d ZSAu8wORtialobZun3MY9oWE94t2yCPRLCBQnjlDdms60alo1JYYB8RH4Aqleb/hl2B9mHf89mUC ovHA0m4SgMgLBTtQfpUun/Wg1pk19oL3wBptABgQTXJXkhxNS54RLxb78KleuLZzJhqWfPt0liDk nkwYzY61VXCWUtVTxmJT8Kyp6IANR5eOC3m6NKL6bioU+kFK/wss/jV42kdthYzrPUGnoSPhR64+ 1aldq+HCfJReK0kqHDqodXrdEFPnRuwUsIRcWOP9dhnitn/gYbZedWoU/1Vv6sp9/DiABPaZWs4R i7AmD9XTedIUW0y5Dqtwe4HQ2eoqtiD5uOiSd6iuJtMtBHE1JRY8RhkHiCj++zPGpKPh2Ftb6dKS 1PSvqnMLq04cqsTTdd7ABbhYbQOi72uwaIUtXinVfCdDnD5HBvK4FMiczAoYM8KZYTk4uk4EnFC6 4b0fG2n35x+9Gz+vWKXSvmVNaPpsJA3AlK39bDUxItaRNuHvKnUv9GjjHJyO09N+wcgK7dTDEjur rE1+Prw+oUaJUgYsKnOCdIVrm9WEZiIy+oQzj33r7FUb5yFpedWvFD/iWiQ6fMouJMa43JqR+8zd /7i/q8wR4rsi4qjQvkYOMX/o0HAx4VNboooRxzf9ACcjbgtOFzd7Fl/kMhprIS91hAAm0QakOo+k jBLNVN4NZeOw0iOVUl4iOj7422aigqUk0UeK03BwrV9+9Jg5twRVJW3zj6XaVX0TA2ZtvE7FRKI7 hLzBohap7EbqZCFcJa3HrMynH16mj/E7nsbwyLlapwM85rq84bjHkKOKaEL1b7j/s6jUEiduZgEU kLUwjrc+NcqETsCAk86V2QlJzO3b1OJK3XvVeonOiiAGKnCKFmOzuwLJxsAoqAQIGuodd9vtppdn NS/BsZCuPrqAchkCRGQ8wHDvYqBrT66TSAEktDN47QaH+WC3gCK4hlnC7uRZP0SgweiXhjkhbk4s J+cYRr4ChIWpc9iofjskI+y+dTmjKnKp4Ttdcdk/vgwafgBqWXjOb0TuU77P5kOAjs4kAJJqeRjw MsSHX8n3B03k/i3vI7oZZAg54dHJZNr5ObZswhL66ATMJSTod3l6dULK9rGp+PDRDXjrxzVqQutP +aCalU9rG9/fwtV+jqK/eaRQtzWTCZtW8zxbhjzC6xwyaoXz9T41gf+iG/Z49yRm/ZxrhyIC/pK5 HtFmYzX4KsPKhQs/1LKJQp7TJf2GXzJxbtKknSEe4clk+M33q2zSRVT8vN5qHMcVENgQenKW9hHK dba7l+SrAbIL3r2i/OPRZCCYe9M+kTZvHu2CTGNymu/Mm0ocwbE0kFt8Gr5ZZnPgjur3iLxe/rpx SZaolNHKGDo09pFuxER0a9s0Ey/dqzV9ShJuDKzxtT38q0Um+KwK2zqEidJSGu3FiIoYD8uh11Xp vn7/MwrGepHge9vM2fwIxke00DL1sZuHWJ9L93z/sSuDbotkRHL13ep7D6qGbxdCMYOrB0vXh5YI 2KGzRzIPVJErb2gF7jmO42Y8AtsNiB86lUmTEH6uBMrCQlKRrUeBkgJMc70qWmZFUus6bXJYuO2V M90Li8UCkinY6O9O9hrSGPziTPy6hksfNIp+L70MwaWiQxZql0uKjEW/bkeCpsoZFCa0efuOZO1/ Tf5+ykHiKHxyuvM0z2A0+sJpzdiUk92VEmo+0V/QL6XfPcNUxJItK5iooHx0WsSwRyjCYqccjhWo 7FWmQ2+UBQG++x8Sz9yrNOHZLWfAX09pVwfyhnF/OEgvUUe7wASxJI0DjYTbtMgixglat49aiCxp 5WiF4J2plpe96n8id01/o4+o3MweVdgzSbKnqt1aWO7yD0ZHfSmsEtiQoBoPnFNL/pOJ4oAYCObf u63eMZ8zkoikYbSI7R/5iy/Y38uHSYvjHUwCDeZh6Thq3HCafz6fOxF9HXYg/9MBTbp90JAviNIy QLnnPOgi5aCaMUbwDWjXMhkiN0FTklVjvT/2ILkavaR7nmeEyR5gbuxsk0MF0BPfessdk6WiExHY SZNR4nQWFNxvXuHWFmKuP0HYVm87WoAcnyURd00oSrJH550NZnv6be6Z/8ZzkI2fJoym9XKNcl8w JTN0Tf4m1+afImS/biLsqn6ZGlSGdcU1acQ6A6h36jmesM8Z8HFDJ1V3Pge8hz/+WKkLaW+2UEhM kNjGblptVGd/Qr8FU2EuHTqV5rm3GakYe3iZSbZRp2Ukc2hmsVOoB7yW64dT34KtR1NyxcAm88cx 54hnZ4BP9jTo5zrrLXsWKeEIA3YGFp2d4dy/PGX3G/IMJgNypWL/1qDFoCk1Gno0nhFFlVISn7pc OhkCWlBxOFyj7l/crIfJBmr0UnxP1HsXbfmk8WPbYvgiHNOTjvS1Sydkdt2oaqWwr943rkopufn5 5LR/bn9noscx5eDXLkPalAjEY1a3Rgxh/oG8aONhi4ILldP4SC/trUDNh+BrFpBOpAc9F8knNZ15 pE9+vsauP801fz9anjnnMy/ailfhtSO8dwUA22dbULLga20HIBY66l9Q4+LhZK0BSwyXCeCH1QM0 WD8Xv3SHvSW9PZuHvVFMxvtW1sqR208UcGbJ+EBtPP+sljvAEAlj9PxciO+a1hTTQbczyZFQePRL AlT+y5Iic5FZ25dvi/T7iwYTSoDXQP8LZzxquum7yzE/XxeyHXzzrqNlvC8aSqC4V9wki94+3dyp SNv8HdNiIsNtaKRzVVZvMgeuLNkj2IDuTMxZ1ndpit2SANlNRRvuEzRVLWdcpbYXEVKl8LlANMkv KUB13U+mUEPciyFG72DMDEVNpXwLY+AZNmmmKS0hCujH0lb8SjYNy6b79aVmXTY1D7YS48QJiz0B FOr5XjzWUQT4ADBLeM6KvW3VKPDynh+V5xyPbQ7bGSpPndkj0801bfTb7zTd2XZsmq63jTZhr3zV aSPYsnHE0KVofOX4haAaAyA3gSdaYk0kjO7zZc3E9PyHzfGS+ewhRrUh7+sentiuDB9h0gP2dCMr gsTfpK9rVGMIsTsVlAiS/8OK77JfINdt7/l19yinmEVxONDpOVfHi0zBjaf6VbiS/tDh0F2EizNc TryoJpofOOQIBhndUchFK4YRp1W9jU7ux3UlUnMBGaYhEOwOvzLXS4/o2QP/nNUuBwntYLYrY8sg 0fqMlbaivsPLkskyGQab0xsVMVtayALuTrCOO06CpKzioAUPc/UsFHcRzDN17HQ3j6Pb6k1tEIuv jhA5ExHgz0jk1tE58qzhn2WwUUzcmxLL/j61nKdXTt5keTfcps+Nfg5XkVyu0h7uQ8TE5aOMMQVi ZREwi+S1/b9K3vBqk7iMaSVBdYwzo1FgpRXpqxgywq1XDhbpzHl3FcxIahnZPcue9uTYssm/Y8W2 6yMPnrOSdA2AiVkfnGTivAsPbd6PbnCAll/lNP7vpZiMsEfTFR0ee+GppwhmtAVSjOY8oS9aO2xP 8IeubCAsMOtzgn5HeMoUi2jjY7211I+ocZxFQET0YLGtuqFPOtNJr7kZdlPGxL8CwzK8N87gf54C 11wra4TUqGJyg0Y+V7ju8t4Z0gaKkopOncDZgBrUasti1q/xGxoIRwpEdbwyAYv1FfSvjokT+kQf ToA+XU4I5Rlpz79RVX8iv3OkDfAcwBnxB8e1v228VT4AmuK9oqomllObsNzPJVGOexEFKMAjowk4 ITGY/PyzrVEtkKmyppLmdYzs0ITjbKhRgV7U66eOL/4AdwkqHrxQzZaia04Zy7EAojs9jfLmUbtE 5gIdSDXUon5idj0jtw6NFs2uiBV2+VXVgWp5vB9qYngt4/uv4nI8zSXPb3LKSEplQ2d7vEj8PZO9 JAY2/G66HByS8FwPVujFpYFqGNS5dEB8uOP7ms3CfcHKnJR3/2oKujsiPV4+XIed9XZN28aASgE6 7fyisT/3GDtXdJKnWnlLJEawUeoEoukwjPh/DQbUl+Z0M1chMw24wTZq5lz2tPZDRWlM8xHL6raQ TtsT/uVlXrqPbsfloPiuqvp3e40YL55A5UB5XE2mGf/SBFk4uqWsqq46BFo2P3WC7U112cSyUrFR TZuV67kuH8dL/0dTBQjnOHmX7yC2ty5nnjs1xcZ92u60UHn6I3HDNY6sgQxQpTrR+ISJONcuxsMu 6/xQqroaaOc0ZOx+55iJPUfw18QgdU25ay/vdSuH90hFgjqEQyuUsBTFkJImAb+MUZ8oxNnWGp8O 1ViKxkHag1FJgKUwfKJEyduSwyYez/aWQ36NVYywkQHTXTRDR0L7N3rn57nzaeqmsst/Noev/se7 2TTVQ4MJV3cAgAWT5Dq7Zumnf0m9k3Jk8MW0w/o+s3mbKlYLhrEbOHBxH2ozh54JHuEEFwHo0HEg Tycr+G1RlUlzFvNfLVs2pUe7NMKQQkKnCevDjdIAsi0ffRtWR0jYIZW9H+wAO1XRl+P90NGChKdH Bl3b9+gmvgREe+pqyakstahfkONGxGxNRIxOV0BXyRt3Izmw+zup5Lu0+hc3YwjQQKg1wykjqiLu 4pNcO7rs52jmQleIA7G//vFTKYxpVk/bJMWixmsnDGuRYDCVgfJFanvLAgHTNUSe1fuuIsot+3Lg V+qALuYrh5Jgz/8C1RCjbKSR2FZWB9S18syGFareYAL6dDOM+fr08lWsi00xxg9r522/EBpY3Yue vU/52s6GHe4vbbpmSh32FNZL5G8MlOWt61VWdcG0vjAplbsh6HvnFeEF45nwgnzHQUkXOxO74jbb mYkX4EI71u0/1UF+5UTwCCmvhdSO63dFPW5YtU2WvxY5cmBFsyoJ6mZ/iqaObMJvyuixnaIx6gFf aeSkD1cNImwVEVfWWi+ubzNscfLjo2/99x5IrRLCwXNP/ExoS9qWEZrJkExq4qJPMGoJVtPXFj7V Bqq7bufAWu98R2TOGw9vDu6NqKultKWjKY27t+gZ3tijKgwLsJzYhJrItBG1qrQ4TSzzHMXZKIlr 0NVKSD1WDGWgMt2kFmDmRT72j1GAdZ1frH9s+4dfNV4Kf3IoCFyrRJnE0GEzw/ykmEFu7/o/7KYS uWaSmb/qQ0zvOdV8b9+I0MiYXkOkrm2ZxieF3PTvo0GmjRYVUV847NSX2sC1LSjRDlH8nhf+kIWH RWKY4oxb6KXmNJpQNRaPdYbvUDuTy9JchpBseSkvPnrh+IOwFT/Zc9MO3WYytpRtc6szXYWkSKiW W9/Kqt6NI6qlVWSyvPQ0AcEGT59azpkixzpk5suHLIxcomxnVpUON3IXSg2diaNh93BJSv+ub8qc RpypAWa1kKqvWLXOt2FnT8gpTMSqxBB4qPF7+QG27Cpb9zM5wrLaBBImdUQ5MuibloXTA/hoLZSN Vp5LeRJSpYUTv9qxjQqcnwVt3PEXyUlAXCgLb+Ti/82GVqFbkVQA+d8KUtLcD7mNQC5+Z8VbgnI1 OQsIiUDDe/DMJ7JJ8NnRT964TLnteBQyiYwU0phA5fZNDfKJsEYQN7ZkmEcZOr9BE6SpJwVXqoZS PMXFUn6lMFQYRUwA5vXTrRZBPjIebW0vxA+orK3q/yFYDvGnYpV0a2edNiV3QLFUc2nTO2/IpZxB rH7FjB+uOTCWmFhCE4rqakY4ZSPIkEIKRMNkY+1DtbrK09vkS/FLUuoEC3IK6OytJVuzvWOqHxeW 8efbN03HEQuuFkh8yZE6Iot53inpEX5ONwi9mL8zd18IDU8Nb2FHJaRgfv6OMoxEP4drU1esT9Xz /+ozcTxEB7W//lx4W5QgxVsNWv0woSZY3mpgvVpDjMUS3tq8yeRDmyG6Gxi3cQwzumGs/p7NeZRb 3RLDw1d0vWawYakltUa3tcQSlk8xs/6zVr9luaLtrBwe6k7gKQLrs5dpPHVZBAL8rtJOw4c5NO4M eM2WSptEp9vaqhQ5w98+j2bFPUxKyQz2dTn1u6XZWe0Ts09nQKyeQW3ymI1mbaEcwDd8HWucirug As7ZMY2BjsnoGcILZquembUEf6I8z60LMExgpRrHTIA+kMdOjI8+lLim/oa+A2FN5r8KldwCAqhz ATsb5jI3k+/E29BeFfAa/lJ0wZcw716JxuZgLqUFy5Xe3vQUSEj/t/vSjV8DhGkcYVEoi/uBfnhQ eyOiil3arT5B1bx9J4xIyjHNBywD6MiDh+/34Op0mr/J78F3SKEcDdJaCM7w9x98TDKSMBTKHxoX BKCz3z9UN8OXYwciOsvmlEaY5Pg/v2UtLHzP8NHhjKFOqSv8NIfbAySBRzMKA3naBJxhUYwR2Nv/ jS7FOajSP1CcmZuaxigETBEOS34AinoJ9EosbtyDTVj+YqZo/w3v9LU7Jtv4RQLC9HaKk7MCUwVC XuDiEjD2WoUfs0hlOtKfOMTtaEnrc1v4QKSwGsDPbeNRXeDGuUbzvEXUor7Zv5ScfPQJTHI6FdbT r2Njr36r/aBPH9m2cj6/pJTEG8X/J+ALiVoXwLu/VFn/NADKhveLKRdY7rziWvdxTaAyWloQ0lsS JGIkqLOuHRKIH88LNlIgmBFtB7hHeU/PlrIghKLsA5/RK7IoGsarmPmQJTNtzaDDpb1dClIUN3Si IHy4fxqS5ayxXkMo9jg5T3aUb6DqozsZX9PA2nMmgBM+OYnLBh6zi1jctWVyon5cEYesqze1a0vT Az9P/yCslfcU7IeY9wKGM7npwmxDN2EjYQlLAZDKxfXg0OQJs58cpwoMDcDIJwicxtViL0NOFdYU zacnZMtFF6oCFUMNkmYnBjFAe5zoEUKbNBHFqeQmMiF3ySg44YzCY6PdGzBOcfpU7TbXHKIAjjfx 4iGSLtyrK0qsrCeYuiw5qxfzyib0THOpR0JareWvFpNhR02knNi8IxM/M3N9bDsubF4lmnoaz3K7 syNU51C3FB9boPG/S5pvUk9coc18NBQINRDUIhGv66YIy0ADrOChMagkvAwwXGy3ZUbPmIjt6kr2 kD4JBS0cDC3GqoT60emMpdhrFnA4cfjO7zAJtouXKq/fdk6n/b0Snp3n78oyC76p4a6dN7XuaohK otDhcAreQFuGogwzR8MlLaj235eRh1/UxIANiMPk5L5NRV0tZy5i8PYoQnvlDgIh7aOjLj46eGbl 2HDV4c00YfAaxjUHiH43wYlIk2AcD/1Aa1QadopBJu5NEVuzZbTa2wvns9v4afIipf/XCcALOlwz 1p7kvcR/Wj+cgIeZvVHGWo/6bVReYckXotW3WTQd8V8QBMzcn8MtTGIfXIxuSDfaCTLgJ9reoCEV qWNyJwhpptvBTk3pPQewRLsFpzyKsC3Nr4KTXNWqiWiEvHkmALK/Ee62lx9j+rJneTw4kzoF+4+p iBxVNHcs9X/lTL1KC8cNTEJLtoqjSjpvU6HryF1sTYF5O/XR7taqb0x5oPsF/s37hKDhPJsIfPlX Qg1hXpeIQPpOXSTXcZtIJuFlyNt0QXjCOds0SDQeWoJuu/U7zS9iJX+xNz+xhNUF0Y1DgyYejMRN UvNcXSswFEAnYOPP4EVWLT+14hCIm/S+4A1pPCuZAtfLbtyuqNik7ks2Bify49C6dg7ygrF5zbTG LD0lEt6hDiXGVSatg+ZtV516iAFPsMucPtA2c/P69vn00GluiH+WvKD+Lh87ebzLI7E5TFSDDGBx 37nHnJCvOj6zu0og/t+wlAcp4t9udZnXnriEzXWcvAM6av5TKKdZhvmYdDmQYmp1Z8erxd7L8STb R55qmdkqR99WC4a1J7h5ib6V2o1aGpPa9wXIBpJNtkIRRBkzNvr5oOBP5pjQNrclnSfRWggHIWV5 uTlT04rQEFX/QYDJzRlpnpYOhs6nVasWh/Jjp4OXcP0edFoMZZLjMA9tpotHwDx4N/n5mXEenq1M w9n0uBE8IPjEWmdn71m6s+HaQAk47qY6Pzv/82Wlha9xeFGaFehUqf6W99ejSM27rGW47Wi7xcJV P9BzQi/Q5hVLZogzznHgLWYxihaY4HX1TvhrXZaMV2kRZyivknsbis/Oqn5VKkqqG2+BgsGS/9MD EDFnNcLJ8taEIZG3p6hEnMzfaJLFoX2EVXfmCuCMOsKGj9FM81kDdmaLfLuzZfodJ4t5+NdvC8/W Tgnqbx9MHb/+Gviuj7w7WjyZLGFKBRMtCkTtTxzA/BxM88sC0PhUavwo1L6F48tI8PB96bhFAvUO u5crPyhYpsmAP31pxWM3LmY8mflmuEUl/X2XrOgn5lji3njnYqzQwm8+bH70mKuM5vha5urkTwwQ 6zcQvtQJak8U/QLVuZAkfiZHeLywfbFftr20/r8wfnvzmPeI+RAZ8G5nalKddAN/tlylLPwYEiDK NGBDSVvkBfWPmUJyxlB1NWKDISN8wXKbTRAD4JY5d5g68rLLBVln4Wnu0RZyIrgWfs5n8mlAFOmq e+WClNYeFVt0ZYQQ7PyHt5vyiNYKV6gbglx/tsPxhxF/yYFtGSF4frQPg1wbQulhkFd+pu6TRBku PYhnsWpfiNhKwES86XCAsVPEwZQoBdC7IiRjf111iCQFQvPfjUqBrNZl9MvzcA9cbGoZPH+cHz9D AmWPRxdFKbDCA7K/iBtiP0WYGsUQrLFwVGw9/52NGFOpYde4KUhSDcIZ5yYZPIniOrhvbCIWCxJD ids6ppAiUNd/i8vE4Fqfd6ZrD0f1RErevu4cWsN9rRu1jlGUNBO8BxRRudxgCHh2/qzl89Wg9zP3 E09bWqsjdZ2tHZDf/zLYgOmU29t8ZOVCHx2QHoydzNVvqaf3ZJrVSKJ0cmi73nctfuSp4XEMN2Fr lb6wxlGylV/WUEHoBoq29paVKJcVXCxc/sNq9++vxHF4R8jj4GSBLI2zDnACgCYxgFJaZMb8Ycv7 S742ELy9UpjAE4Y8aS5XTdk+B1ekQPs2GZtGLYJ31j1PIwLr36Kf6trFjBjPxtjuDmXyi4FW6mIK BSQF5j5z5WyTPhexpL2RjKZ/jHbLr30cd7y0JSuNvKTR7Jw9m0+Xkj67yBIISFb0tt2upnVyiIoV LOgqMezaQHte/7Z/6l0wPtAF6plYik0SI4VWRNysDVu/mdnaA18erS0sDUKSEsfzmbapbBJbEk1A ManysZ9hrJgzDTJlJLXTsCMUBTUqIuRTWjsA+M5QCgva8cvxa9rDWijhEfhmhCFsYVxHVv4UJ5G9 J0QmrupeBVV69fyEBRA/HV24qtE0ARMun00mZ1KXWgTCvCXKEpbG8KLqjm3vD1OatqBX5BqQr5Ve 640Gq4pWfYYV+orEikvP4ScBOgklYJxgneTuaLrNmPDeeNPlyNLBxZRMm7lqt/hBYpRiWa+FCTQk uBfLdofT6fPSjlaVEO7Rbaiyb8ymJykwX477xPFQjiwXBD4P5wfM/+beKSaxe2BsK3o8niKJu/I4 8elImV4s1drTGzgv/0dVMFnfb+7kwR2EnhPkTDmHebhoay0gukDuidQs4NsTtLuJJFD2CwFJvA4O 5XL0id4r3hkkNGw9FKiLN+WxYwkNORL0aCTePlOuC9pZ1HKZT8I9ejkBmQ13Q0zaoTdGU3zsnV5s 4tqGIpTAnZcCbF+CIS0VKKTEF7FMplYDblgMUC93H1uFax+cEIb+njDAV276nYuTVLkOwCxtZCyn N12y9fAmeFqamZ2g4t/LplOL2AvqfgONtGH3EqOT8oVbiue7DNAFdtdcwPV9xMFxPIwrUt6bmwvk xMNRMBn4/OrqejycRhEybd3Ywm+B/woBdiLr2Ktw3dOXc2iflDYttFf2ws9DqT3uadZmLmHf/pUo /kXoFtTUPHt6GNUgW8XSloUponHW9obMsYAWpS9qe5+G51DLSQVDlxLpT6jiLACfVnPZrvrS6dm/ MNwyzR5PrIJMrDLdKhBZJqIzEO9AAU8jiXY5m2Ka7UMRT5OD6WeukwdL1okJQt3v1CzVkHc2wT7+ g0TTwgiK0EoNZUSwV2TdttzH7709amBBgIOnu7vzyH/6SBfMykGu7Vl8H6GShvRlw+/xrN7L46Bc abIl6d+pq+exwqdFcvMf0EvswOw+MXWj/bU/7tJsdJor6V4OeyQU2EjGpedbYeiF2r/HpdZV42G0 jxtYYUOwUJAtPJheXTmqRA0AUMWQitVunA3PAedGBNs2KyyJVh+OtmDcixRS1PshFxW/pO1Bbfrf 1UxN4WqfdpwCrO5MVpa6/l6indAxqrzQXqNzPkaY7hQ1J1l9JePTV69r3v3W1zoMP7O9tRn6tEWW EsC6NoWDV/9FrVsBIkYL6ORrCFvU/RJBj455gPpHJ7WOduLhCFxOv2rj7wapzxxnpxLGND0pBW5h duPiaelmmv+x2ImrhbNv/F3uzBGcwGyj0qediEK0614CPOhijYxmvGcrMgjMAT5WQFC5qefe+qAQ Gtlt938yxRyb+21FLS/Q571ySk6BOIW6OL5f7iuK/g1LUhp9Y6rPQaq9mRmEqfwaK1T7+ErzIqEA ZghsUajqkU8SFUd5mZVYBWdCrzj6NCkT2DS+/ilOiqbNPjWOAB8xIKlTI+uTxg4iayhWLqMiHu1I 7QOIcbNf4aO6ey6wXPntUrAwTBQk1LphLtjErVLgLNU8MdSPobT1PUmdGr2MDfuAvc/TMm7KR29j XCDC02LiwmZcISn1Q5qiKK3SyTbEfhWk0w/2JVOwikO06mwFlFDpc/O3ALgOcGThkB+PDjnW8i3W 1UJ9lyrT7JMhmvFhNJFAIDg4WS3VXKv4kNiNDPlJPx15dT3/CgM43S8AW9PqylubaLdb3MJTNbAu PCVBWYTKesrSwOPlZbqVvEixA6ep7lVh8y4/nV5vjR6BELXnC5qaaXH9V21l/4bO/qhHh9Cl/8tV eLYvjhuNlgc/dX6RRAEghKLeT+53soVTPwob2rAiknUpaR2do4faxSQ2HWE9hTyJOjH9yakByfua WYqCY3X5TaQtV+PCEilMBQ8OqSvLWRf5jP2m0yPUy2Kkae+1XOg6D9fPbsziVvjcwyZUuUgeCLEM Xuuve+jyghEdtLECcyJK62CfadbntXuKg54KQ25PYg6f9H1gaouP+HtR17KoKxbgLYqe9eDkbMPy rD2hIcUOZtX3kcnF5IdX0rv0wWhOruHqnqZ9ME+cTI8X1EC1YIunJUN+gFuT00tIKXDNstNKw6su BycG9B/+hB/au795mTAjoCM65dzYMd56dG6cGLiJZFRecpdcGfIF06y0tZa7Oyotv7+fY+xokXWM v7lmxMeG2oOtXER1NzwASIzLTdfxLGr3r/Dy8xYADtN4MfcgOChBLN+ilmPNm4vN84vfbwUiQmNa GwCIIm3Uk0UEsnb/YvNOCX+W9ZTU6V9DDFvDrUS0kpVZA1uRjzg8dGRa08oMeM9Uq/jE3qhB5lE6 4oPKboavpRv+UvPr/+VE8dxM6QjPGPO00UUv1r7OePBP9z2dj+NaQEvhFJ+Yr6eEVdUnQNjtOuwX lutMH7CHBcNBO15ZzYMOIKYR+H82Ik8thKplf4Sj5bj0KPCjKDIbdlbnWbsRs6JQjE1Sxb1ASD1V 55XcTNqVGCtjytL9P2Igs4d/I7o0kHNHYSM3qTSfqT0n/2af44wxMS0tMkTZ/yBXO4phoohkBPgU 2Ry5d+IjKz3b615ovPgLuMxjNkvxNdwzxyGaJ5X34erQbGceijCNoUm3T+kKnv9kAes82GK9j0wD ZyhPQgadKNzyhHqmUkhgxy1s4/dOzuqG+Qo79OPMP2SsS4YN6btVfYltRBCmMwh7PpV/+cO3UA7y /a1NrMCEtnowCKcwTe3AykvN7HCXTy4UnTcZCweezj5obmuu8BMO5+45mtwkx6W5YT7akrFisVNX PXhtoNSIOqxMyxA89ETyVlbI3X/zSgP746i5QJdJvNM23YuWQYqSBnnnABa9m7SVuY0fVXlg4qX/ CcC1sfUxhImH98IwWMm8fMaIllfQKwH241xNMXiRLytWlRUmr5OvHsW0i8j/GPGDHoH232Ra3aND e0hUJoLP9ZXkkS10knD8uDS/aYiYzR7epJmoSTG3s4jcDdfV7Qn8qJ7SnvAopX+8hWRUTUwmZRRr 05pqH/yePxZ+o5zUH7U81pMG+HsUqAIMfmKXrNQ7a9bLIYyE29bnnFhEVV6XLIAO7Lzui14xiYy3 g1/fU4Vkl6qmHchC0IyPZDbCbJOz7fKq8rssv1jMajLElN0EJ6T39wlyw7zesFyEqLctPU1vS1mH 0JFNOxW1EotSwd1Da6OzXB1hUBgZmr+GVgfrJsohmQP2RnPu6mZ1kQYHLpAVRpBgqSL/RZ52c5a5 wp0MFvXYmIpE8PtIefjH0rBtsCL6ErOgXPMcXjDDIKIgFc7DgkEdhIK/mmVfNvAhytA2Ey/KnyR8 AVwpUVyaIvJjVCzCSCRaULbd9zbHNtVes4Lbm0gXvtnN2lr1Sza/Hrlu0M48O32UmBgQ2p+xRqK9 A6aj1kSObrADfUXkGLm7dS6qhgtxzMrLnEi8g2q39TI4gF0KpGBefEydA6JVwoXRa8gAYANL7eBF 2NHy2t4VEbFGZFK/LpLWzuGmQZI5cJo4gTBg8zvomqdk7pD/AK+c+4z6SszxPcy0cR+ACx4hh0xG 8A9tPzscgcGlePtc9b0Fu4O0SLWeQyB2PM65tAZxx7wzyYgui2XV5GAGlCd9g/XWAhfRrJ7eWAO9 i9wUYtEVN4yFjW+scVzob86FPHScMMZmFF+SAU+abK7G/QhrTMgden8RtGS4R02xAQeivML5VI6i RckU49wZGGf5xhz/soopFFLZ7AcBOE3p0P5x34TdXAoAv368r+I079Gi7lKsDPfmBiIi6yHIAFkq cAbZx8jJ8BRiRV5ZeF2nBK3HhN/APY67i43TeN+fKmH3RAx2R4GN/QPn9QNgkjNKMrTvygWOnEnR QcRfrnundGIXj9+v5tEYaMni0MlxQNEQJyWB96qf+aoGVJMpBXGwHKHQy2oyPsaptJ41HfD1XDds wvVIo8rrnkwZ15uKLf42D12MnUpqskHgaHVYrp5GTr9Ws5+fpz6gYocBTWGqc7dp/AARIET358C6 fPkmNPtCyQhSFUEbfuR3iqIV7p6ke/Hgc/SruFGRktq3UVtg4z3DoFsqVWI0qZ5H1Gc1w0728Chy rq+rftj9cUsBv9DcnHc4YgzbprxJKJ48yf8QUL+DeZBxCaQvTVOIQ00CgBXTfGyQX4oBE+inwOuy 6vTiJDuvEDd2MGjEDJyutinU/DrH1GvVcAKAtqTps6FobhCxMXH/gL0vBOjdRPWdouEEpqVl4393 kQ9htDEzO09lyyncAK+ePkUBWKw3l2fIPuT6wx01rjqGE963Irodp9mqUenGr9QHtsJyciinCDqz cFlPVVN90AWRkzn9saGtUuXoRq7+B4WxDmcS/JKvw79At5bULnrK685eU6yTMDt5L2st667zkOZx FJyXU21eJiu913FKK2R0PepblyToKQvUhivCWt3ye3TcotMprOh6xE7WkPes/UA/WFS2Xqtk4064 HvsCAMeH0nVQZmzbueZ5JurbJquQQZriyO/RHRBQWM++62RNGHKMwAD7Axg3kIrG9kqu/SUvPY3e j8BKWQm1uDasV7r426Wdcj5tYRkhgSLPaD+Y2Tp08oN4+FVzeoxHkMOTFG5JvD0Lb1AVBT/UHDSr odIFrf4hOzlMU00EJdXWHRIN8wwCHEAGxgUcjtfew9WEElK6E+EgbTHQCOAiuK3yOcLZmRpXYQ0J tXpvJ4gNxPnU9pX411n8DnHNkwm1sjk37MGi3x4EjGyv4lIewJ3w+Sp5X8wyTesMXSlZzxsD5X19 ntvkpHe+VSeDtHrR/qAnS/Z3y0eYuuFbb3/DzKskRWNaQt0NGvVzgf0zcTTJnSelgyH55lupbXIY oiAIxpKrrYtxwF4z0F+5+nXBcIx+v2KE/z3rlEyWe0uk1cMg05IzNEKgmJvgqIOyCC0E7+u1MB85 bWJmUmNH2vafWtypvdINF4QqqebqmBjUEbPtHCZmVoJhA/rdapoo1EGS4G4+J66qtMNj9uoMnctK wGwijsQNKCPXjJDd/9FViY1/uKC9GlkO4vTGgvSW9DcPMLvGXfqRl4h0h1xAGf3KNmZxkrJC0sAm w/FrHvHG1yZweBpZ4chjsHFgP6kvE54eIlPX0jsln9n5ZnBUXoJT/KruAP1DOv9ba4nuMoZ0HP0z pupqquuKlO/exnFF3tyBczHhSHjg0gIR/vBVeIlOCGYZY5r+GbI0UNTIXNnD3u14fVV163OXHKxM cz/74k2ZCGMPS1SoyDVRfDWr+PFrTxC7761FS1zSyWzG6+rn6FJuCNhicpU2DVcWG9NqdZUKqu4N HgiozMOn6o6KNm17gB6cMuwmYYtEyc59f8IwvBExic/+aKpcNnPr5lYN5Xvc5q7fb7MFuJPMFYI6 9paPOR98ouaUJn2vWfCBoKo/VWJ6d9osaduaaxqoDG2dlAfHVxDO3DjyAcV0V3dJtJygroxaOaH8 CCIoVsj6pQtvIE/sdbzZwt/eiHN+swel0fF5dTDF7vUiN3CjZnOh9HpFTB9rFyKEyjuJH217Xsvr 5xcyl0DWL2mzeqXtIb27ZVP/bulHf/cIbtF33AkidKwXhWFVPkf8EM4YfkyTJuggIYr00n76J9l1 kR7Otss6h428b/iOJ5NHfuRxEYqVvvO9OTn+H2nitqs4Qx+wVnT9r0csYpmbCAc2fTF8WzqjR34q EpQgP6JmDxqAW06SWJJr+2jp1x1YQ5wAzcODROjaHuIFJngkWDYo4reog233QnJjiy0E8t5CPuOJ EtVMwG2P5MW3GhrejUw1WNBRKbrwjV/KuSpjGlzm9Hg2Pdqa/7Nf2WqeuG4c9jO5Tbsc1wdNzmhW jKc3pvU8lSlGZacx6JjcedP2oLIomqb4ZPSkrWkheVjQEs710wbTekvjmcnf9CL8pJMrbknYfkyo DYzTNUG4xRHa3CWcqmMKTA6EqFr13Qx3iACcHmBVYcsr+vx0DTtVRlN03Cl/Iw8CUuTGg1V3dI8h IhrelZOMjdgoWK0Fs9Ltk1hWGTpFYuyY0+nvaWg3XyaWpMtM6xJTPP8W+X8o3q455CcEzaP7PYZl +vCpl6gorY61d/3jRFKw+Kh5PFUIRLIJV+YU0CvD+AU13Ccvzxqff7x9j7+rsVtLpImo35HmWuZH LrOXSJUEcr507N5jgWSiYXPFTIkLjicElSwT9b1MccIDj7lF/gM6bq/z4ROPPuwljwrFh02f2Z7B kLmeCnmhO4dASSl9aLc8MWH7C/0Mnplq5NYKxeZl8kDoavG0spJrELRSN17q4GnUakmUy3vAxuPR cSRZPdRsvIBa1WtZIVMPxUD9LpC1zw6GCpUdJ0DN759Mdqs1lxcHHt8aukPrlODrA+yv43ENtYTf 7QqpLRSuQApl8Q0RJ3BHFYt2xRzLM4HgTNdoIVn4Rj16V+qbfmXxZPCV285MWqwz5+2Ccy4dS5LW KDhgkKriC6kbjCwDpDxhDJj7ADs0AVFHInYM41acNjfE5xc39oeFNpVd3hD9/bFZ7gDPXXK8OWl8 DIh8XfC0vkDfTklL6K6COI+jcZQZJ+TCFrNOSbp1bH1F1hwCV8i0miUeaUNyCLGfC+8sclONgmqR IiyyP6eDJXnOiGXaG2NxSNK1Hp9R04V3iruF9uBTc23Azg3bOmfKMXY6N7byUvdMWkLpPgLW5JF3 ggmE31zEx1YsYbD5dfXTXjQFcRK1IdH7tQZQmOalz/jppKy4NqfMxB2DWh/tayxREXZG4Ehxphjv FL/iIIC40edpLfiYpHKBK120M96DHFXn4g1nYj++hGOY7jvo1OS+TiqJ2XY1w3A3KtaKKCtBRIT9 9RYcnnLoSHV/wCL+xxIgoHIkx/gJOKK0OmftIfzzg/+UUbe+xKB8xg2Nex9juDEVdKMQuPR/JVAE CqIiDI10UPhZHx/fKaIj5DlW9OWs+s1a/hKhUTdCNM9f19ArVoNbKxTyi9QdkdbEZwIalC+9RIpx P8QWgAV+UGD9hyVHlety0xejX/VOVusvoIqtiUaX/LvI1Jln0oo2k43GRtOBGsWX3vGPngOJSgCP hHmetkbcNAmYQrd+XRiGD0ecUgyCPwNaZwOHuhccj0hxMmkMsIhpqqBpSf65xDPR/ddpZ5RSddOu MKgyiFwOUXZa+6lDuJeupeMTbXETCWf6seoTKKd2yyp4UHwLysVkVA22hSJPKsy7jWiWzHMtK932 tN51Twsl1K3NWHsGognKRpb+XakBjFhuD5Lt0AFVoFFvWhd5cdLUgMKfFiZwCVGP9WL22uDNlEH2 1Ek1c4S+YfIQ3WoVjKGrCUMhK6JSvd3T0l6SQZ7LE+DkgM5ohL1FZstuaSmmf0V4mJaV4QX1vCdK E+DmWh1uYRWu8WrtFyhN2K77XhlwfcCMQ/LpE2Ej4JXGsqCD5I8zWr9p0Zt8ljeXmdqdDQ5ebcxK 6DUEfJ+uPnwlYWDhmL47YNg/ArHvoaT2mStqNd/48mWzFOv9zC3aaPeedIJOzJnsCLlIMXDCH/X+ 7WXOhwmXkKlPRBdSEDBTEZljKy5d4nj3oAUOUzGyvVzw0BQTzTY5d4EYIu7JNj8AeX7A0uQ+zAF2 iAfWb6DxrjzWdCDCvjLU2amBR7lNxGBrA/QvAGgXJK55rEJ+F86vm5grc+576E3MR9CLlYHtDqzU khjZlMYuiyhkpIZsV67dSPh1fUQ3nD74ADzATffPT4UPNV9ZLRp+B3u2Zb1SbcB2SGnCVAsWnabL 3U+lUCygOh3WbS0k7QC6OzEKCnPqv3XxjajdjovOCM2Xo/6DqHgZ5J+tpIX2z8DspfzkDHbW9KEL p7swoE+8+mQvlifd3ieNZco9zVPwIi0T+x9Hllut4SoQi5qvAuq5FSQtkoQCLiGzb4X2iBSq9wxl jyuHLzb2fFfmaTQ3afsZtGr3Ud19TE6GaP9MYVHpWyImm2fkE0ItStlnTFTxoIALdqfribgETNp7 rv2PwNAFIk6wFiMg+Ikx0VgYz8tJmTNmF+nE+XmXpDKYRFEWvHeuOHtWfgh3UNwcg/0ySbjGHp0I YycB/g71RGJP1uufXjox6s9WjwrqfkAejHAxXXTjHyB75YUF1mQ8dbrzbcpNXuo/ILoyOMvLITnX ZU2ghMGAzTuDfGCyw43kzyaz7deLIKZt/x48d9oo4zpibODCK3w7cffiYCst9VqNlSY/gnqyBFXR wMR1pXtOZz8mJLDczxeNgqNUeZbcHEjNxkS3rudh7yVoXKgJkXhBVYdk20prq45ZBvSbJRLDSSkK PcC80XfhRukSSGP/FwR+UrDOpH1yqMyQkW2jEF8+Qkwh4aH3Zhbno5+QoymNQ8RDhRta+g0NsoAF YVGWef/NGuM8BiTiPA7zBf49qhphvfXDZ70Ip6urDkHluymW2UKcqzn5IeqwgP5Y7g/I1YSaPF2d fwXE45Ev4B1ATnaLk5npuJkerYr24ZTVX8ou6YQJKI/i+eu3aMM12Ze7Ldqtm78v5acjtkLnX/5H lluYy74RzJILe107n4B3Q0F4GnOFFPJgT6TkA6XPjfgMzcvFPx8G0HJJJLMb28ZFNkS9WGtWC4eQ k+NQoMfzoEVz+103+4kg4STS/+daiHtbn/eTLgWL06QlEhymZUT2f93MjxQH+ylP10TRIdFJSzWA Q/DhcptHVKj+k6ce51OgIzoJKIE8gXpbucbiJD40YjlQdC123vhNb/TXeyP8F4I3xDc8wQRpugli i10oQz5m73qFJlJdK1VfEa71VDXW6VwJcVW3qRbAhCWSeV3C4m9Lr00WqU4mduNmEH53I0wZKi0W Od2gLkBnO+Z/VMw1i+hAGaeVMDBJRxYBtzhssZArz0D4b7ZDOHWU1A5UE3LMaq6DUgYN4K+h7zAX S0Rl6Y8/ATsVd1h3yCVHCQ6Jherir1WxxhXTZ2b7V0egzWX/1Hntp/nl2AR/2jp7ctbkWgect3HZ wSA9YrPuLsWgRx53VxqQ8fGaJB0YdFtBWRsrwr8JnPHq2g/gi9g7pZdDm0i5eGPqV+z4klRtlOfr EJchIncBfY9xWREsXauOrEEVrX14JzdKEPzoO8piGN/vZhZCWXBh+eOVFNo1RpsGz87WLbr/24EC O+SR1A8ELIN/JzW/y+WbKoXHxEitycEPhKPlfdQ7kYo/3eBEwGsrUYlnwSkrWo3x8PDZcAdNoOlJ HfFuBwn4KEp8UWYqyd012KPIyuGnS/9PmwUYjiPZz5ORPcIaPL2R4Hf8WTorSOLqsnm8sIduUq4J xm8O9inkW1SlnTW3AYvpUiBGo1Vt2u7UKSprmuwQmAlVhFtOLIc9nf2ZZFm61Fzm8W69fs/Hn4Vk ix1gDvrQwKrKVlgraaG7px8GKcsrRgHTxDrlwsjAwHmtGgf7Rqmbkeuf3+JzSzkNaonBEqTdWKiX ESNl1X+YoSsdaqyhOsDdynBmdqyiB0hxO4pxd8BPPDWJYwuzXdwweWldYOcmsryqhP5g8zQeoBGo WjQTPr9JYUnc+QTT9PbLWR+p7+Fxa+97EpviP6VAAxnYLOkallfFRm9fSuS9HcnjyIw13DYSgHRg igGtUqGWaHuBuGlv0hTf8ity4I8EcuREjE6Gac8P4936sSH3uFE20slRZVFgzaziO1xK2apZ8RT/ LQkVf5Pd+Y3wmEdY+iUAuWgeeZe0XZeQLRwqAZc25gKEWKk7X1iI6p4RXtuwDKQPDwauo4fLS5xZ wm4190/QOMBnxkAan2xVnCLRX2rLzCbeNNioABs9qNFJG/aHEtnNFqbYa0/BeZRZxX9ZC83dTDxu JTgDi2pxKE8xIWBtcyyaNjAgO6YTmqhl5uvjcO3oRvg+LIg1SivFLZXN2OfTmFbPw003a83M+KuT eTlX2Yd3ju9bfNqb84MMGgA58fUn/t8LQdNKFjNczd8zAMEI+QFl3BeEtbfAtkEtSVubPWiBIQ+N Lv0S99GgYOi+V0FmB39XDQTcZOkz2yi4Hf9kCqAhr7fowfyQpCFmHSjFsq6qQXhJy7Bnn16qqwJ2 NcrloXZYxBbbcvb7weFDd0+0bkCskAGxOvoP0YKmDZoKjxspU7njulXc5iFkVLTq5XvAgUWsVasx 220ZCGe4qbR6akR+TT9mwxjO7wkKk6zOU6AlTcWtIlAXYhiqQ0vdjQgSqaYKbeMfO4SfPzxAeF1O 3XIEV9SiirXPXTFM12ZfSZgzxFezATUP0K0SpNK5uhTPEj7XyVnn+/3a2i6Ijh3XOQYoFgnGaW/P pvwbninyoVIDktGheg8EivLF86+JPNe9Deq4KN5zXolVW1A/Xa7tqKpEGTgJoIn5nG/B5uSH+Qa9 KvnZIfA5aIv+eOj0HFCJ6fEHye289t+YCHZ6VY5WOFkEOSjAFniC25Mu+SaCowS67uQwWkj1qXbs LO0C83nnNkN5Nc6qGRDqwAzGFe1bTW4o/QbJOtydiOpWi7IHNnmYt0LQPZ1lb6ufHG0zRvdrrE08 /GhsTksUSXLvENRJ288JyGDTfjH/8FL3SqZ1gS31VtNcGBB2Ls8uSZCGfSvXg5TUX/aDEAJxLAhM c3qiwR4gj6wFDjlWrNIK+6tmxtK3UKiaF2GJRvm/HI3xcaawy2Q8VfG0PFXbhuFl90ghosQpDg8t rxeuFmG0tsLdKeWML3SV29zeXi+iyyXpRplsIrzjvGSEw9KYgXByIfWulP+tFHw0iQtve6tbz2d8 FZaMWtLmD8Su0I8g0gD99l2zHzkfvTiPAy8gXuSA2EWyA6L7n4+bhaZ9Wt3KOqh44D+Cix8w4G8I lkuL3dAOz+MMOUIxA48LxWwzsLHg5oA2CPSDlhoz+LGQafS0DAY+sVKhyjchsuZxKOMYf9tauYRX GnkV1F6s3RGqlzDQPHjI2nwQrnfGVHrOkfZo6AtlfAwiiyi48l8SGMyd7leUKldxnrdBCD1fhons 18TDCkl3ysy6x1baXYTOaDoqTLTY4EVDTs+nVbTu2LzDB+3j4tjjxQLu/FyppjPcO4RqALlnBZ0D 9fU7UAckW/0ycyYA/B0V6cEJbo86zpZthMXxzQZloRoFp/3iIUgiDWbxNSYDLevwFI6sKS3wm1v7 MlZzFejQ6olrykPjPoFpT6WMpOdeR0AJyTrEshDwfe0RFN1iwbAYqQkAuR8SUrLj98dQXuFF07EF Yt0YD1cqx0Jj38ycQKdmMm3Mcu3oCqN/WyXyO8vgoyCV0jReh34jbG4oS7zkvZJRu2SPYvQr74aR W1GM5/v4rmGmqLhEKnNSQUwumJENNM7NgJO18bXx1Y18CF0r64ZsDayERq07BDog7yPoUTGpXkX+ IsmtYx9KP/rHNLSgXPVNbm3sYPbgGEJzlwKgXo6OrBzvqb+zej7CvXKWkStq7uqbsOLzlTxKsjYI qvLtzh+O4XmmPr+ka5eW4kZhh3mmk/Qb9xeb+jgMp36M661v/I2yPz6QbF9nSjGV4LyEnbxlKKx6 xDJw3iXK7AhJSbqIPtU6KxTPMgdfcekwQ4r9k2H1C3T/Jj9JHSt/icQQZzhY2rLbBbdc5E5YkCB8 4YYhRWm/si8h4QkK6UtQLi16fNoLwKbCEWEriaKBDfwyudstWczJxvk/Bk5VhvAPm9MEOrNeKG/i ucMOunfl2zwdWh60OlqUtRgp3QTzEPiRSO0NIntjwg5RA40Vi8VlcmLcpHdEW6+7E08lyyvM5YDU VBTKg7efweWx6cNd32BKMNQg4QIHjeUHYA+zPerxlw03RuQVSnEfTSOXQwRC9kJjCl0J4bY17w4L trFyBkcaXkbxDEAUx7GTEeFIGh/SLPwwDb8pwtlCqnDnfLWreFxYfrtQTA19LYKilWcWyWwdGXbn HDyeSP9bkMerEkOw4yMMmcmQNr+FbY3R5oda2gnvrmJhednMsN8rG5rh+/LZdX/nMywXdnWu3xRi axHLL2LOoO2awVaaK/GtmSpLBQgCZJTg3suIoOSiINCcF32s8L0l3aB+kNJVUEOCvXXzjcvGPi9I i4cYCUUe8T25pDV7NIfAQJyZ3zBeBtuzeaTEYJZ1tr7iuu+JeD4vG+eYhLOi7fnyogSIfmftd8HQ NM7btqMZZPFOmav9VmLyGHaHILNfCA+clxXrQRAqvGiFwKa40ZlDG1O3sxt0BH9Tw8MdqprmEMga Kqs+aOZkcrCTf3F5byI8oPK/Wh1wGHoPFvHGOgqXTALkw7jjxNhmxhY7sass0+v5vOqFpmAp8sXq wmbeeC8nP91G8d2gH4+WKm+WzJ1XvzXfbOvs1g/AuszVwAZUt5L9uyGZav/PW1+A5wfOjc7qj1jJ 2wFV6pF6uM1KOoi7jd/xoLb0YGrdhMO09MaWQbaYohG+wLePnP5OO8bVN9p+ISytVzm9AAyM0NRP Lmri/rwMl60E9vpIgzrYteh1Kdfn4Du0SfgOebaAsA4xAX60i0y6Uk1HuWgMji072wK2Ws2r7mN/ zbtaWPizAYvCyXW5kt8fRvEqXDvPj2T8bcGnMfsZnrpKGZas19gWPsl3pswMwg449B4cc2TiR4h2 eikMS9abDkgOd9/v9Sy3FWQOb0WISIBG0mcIP9Dh+I7FITX4na9W5SnmLUNmcxE9oZYGZXHR44sJ Nywu7tBr78jktNamLCLjuMeYPKoUEkpOtxipIspT98nDQ72Sau4ZCmEtV7BpDG/DmXd0NzOQ1MlJ YKwiF3N2vkYq0p+un249STq5N+FbcImCW6Xr5QYgoHAA33CE7Gus+jTQZpDl9+OmIMn+2l+SLF5A Vl+2mE1MEXT9SgM76qn+SccGRIgj01jqeSm6YEge03X6btjDu48J/1Pd0Li/Wn/89G30yFD4g/e0 qSwxPbwO/oeQer99PFovwC0FFqxnopzBoGBbVcXfL5L7sfwxHipHXgfa6PQNsV64+TBRXTB67CdZ 2FOr0v9ZIi1JqDSWmUBbwCgDpNSUfik7P/CMpjzU5hmAI2Bo2Ty5b2dXWewpCACARI1/WfOtCo80 QrRcoJ9Y0wltQgykfavoQCm3fViJ8htEBmeUG4Si4X+/2E8vzAMtXTQHtJp8D5bCnPn7LPWvT08Z Efw9zYIebaSx1gP18kpI7Neo0fHB2i3AUFtI55EVwDL8AK3XxxbklLOGv5zYxlVmFnLhj+a0cIwv s6NrjoHKzXDGpGU2Fw9kVZ8tSw40Ozz1vy8omLthVP2582iyrtQI/H4m+DcQ6D6MkYHnvZ9EVK+p 0Z2wpwqkW/HtO2uc1T2kfoT5meHZZdbFdDktKw/bpuDiH6xd4QUDjaGBxrvhbYjFnAU56OpkBY1s s/pQNMFEpbyjDMnKQDtqlz3Nc/23gyipg3hY5vxezcS+8jmcs7adkUryri3xNa66Yc2HFyXj/0bb 9SGSr6ILB6LGwhlavV3PUUSS20mTI0hM3Tr0yIY8xEAvAav1yMi4yPw8WyzCr87/5KGl94z/qW89 5+jn2UERedMvFzE3ImY97iWzToHSxrAurctmcUk7SUmRRWlfODtINpL43dJAtuZiGcGHluHwJTy2 2EmDUQy+MyNU9C57Y/zK0poIkTkpaXOrPyZveRTqtCNyT1+LXMaOFZGmbGOXjl7naPHqzOguhHAn tHrLvy7tzL4r9Oe+gC8yhZj8MX8GZQce+/4N3//cj5+ZRvAvuNtBqQimL9ZJ+bLwIOb/ZRc0/FoE owcVPXt/2qJpFVWdyhjqZ0sQwxRBiTey+6Xnf08B8SbBjLPBj8RXI77u2yEuadizrLnhWykVaLcP 933eGpEl/kP3TP5AtBUtzqNcqr18nZaq/Q9I/5vPhe/UbinkAGAatqR5k0OuRL71mI21g3b6AlxA 74Pzd7wNX6IIMNOdhUMKZBF/LzXiD8KgOzkpHk3cK/OJTbtTf8aL3KBG9zezq/YPS5Ayg1tVsIXg syW/EBG0ompYtIWSwglVmNefWw3brPChoEGkq/qvkWXsF7Ji89RdnmfKJWrLY9j62QlLbHMp26U8 zjlKLHASH3kCsXQsiX52fuix5WBu/u4Sv/cc3Z1iayR9Bolj+KrFYrEtCAGiX/3HGLNsLK6D7oLx b2Ep+X3HVMpWvap0VCgOJL49K9ENmT9JvNPkx7xgdTqtMTZofPvUvWk7/VWOyLqVUfpVL56VZ5OT TgG3VrXBjHIo0Mv6AyH0eCYCylFJu2dutb2cJUTUB5IZAFA+/X3/EvsoG/m/9TAi7w2yTudUePju opI8jF9+eJ24QF8jpFnwLFinN5aLUk0y5YKTEMT5atp0+EOrjxPTKXt1BirJkcGJdAIjjfS9D7MX d7Blxb+u1WmYO4JqlKlR7XCQe7y9/aGlSQiZpy1mqyvsmadktBY0ofbiPQpSzvwER6utZ+XB8FsD yhjdCxembGWggYoZKEtW5fQPVHJ55JuY/uE4ZwYMxuFdy+AD3rdBmqy/DF7k74xlOzHYAgJwVjML O14jsakRzlAoWLFeL3Nq61BZL551K7TF1vfEWqHZ1W6AvihkdrxZXyTomwMUPydU2EUvHHhFU+Tp x+LgaZcdxXwJAuCCBegktMeUKVVFiFTwfxEUMOF2/9eZmFzq3W0+a1gAeExVgqyc7C4sC40S5f5y HibJ5GXri1UnEHsUKHy+6/poZO96UAOcRP6ORc/b3uPjvJUYQx/kUsmZ0P+j0SzmDgmBJeSHS4ji oa+ffdDn9nhqnXM/MvxlBsYZRfWvuGpyc1cU7Wb54Pc1CDTCpM3eW3/xQdZsaX4BUohQu4+n7ijT Mz6lMnqhf2Q4kpDO4QrT1Ur77RUYMVDfdmJb80qhzcVqmR76KExX7ykYXIKl/zl9HqxbQ8rpD3G6 v0wsAGh5/YkWNno0TCXcwcYVW873shkAZUrBO7hPiiwlZKbw/1EGMs2zTvqRAOc9+2KjFHhF7s6m FasnXJuPYEvVDfXNW3EpnnnieLO1E+ozUvYuImC/0k6L8bYsWfrYtTBHeDYADKCvgqmP+PkppdpJ 5U3EitGQf1tKpaO4n5Mo6EwddWml/fe5HFo18wUf723Ei0i1bp8tHP23Hav5ghbQ+kCug/ysnr9Q joZZrPyksBNNQGTkOFvBLtUsbss6+7KStG0lBRbm6Y96wyq0mfJiPOEUn6nFeOu+AsVRN6MhFMjY zZcdUpJOEqhlKSh5uzj0a1mmTzl7dg9s/bh1xDDnNG1nUUocdm/IYT7r7dzb/NVf9UiU0m2mcc6A z/ia4nMTJhrGWsMuz1MSkoR/VDFhD4kOQukdMvjufLbA73LWHtcZ07AQnQe+KsoljAh4pm+DTcAH FJQLcJUzE9DHGjUHBdU00QRoRpF4xFEKVM0rMH4mx8LyYQZS6glbiwzJTLGTCJ4/qHJ9DWhSd0MX 7vIgZYUuUQM9FOV9FBZNFPwNEU/Csn7lMyIc9VTWrKKeL93XDhOMbwhBqaF3Pwavgb//o9xoP0e5 Lq5UcVs5ejRaPIViEEmyzBEJiAg9M+2RGVgRrMpKzoUhnrcSyw4BG+VEODdet0ARJ9q4SxNCcXgN UTEoPdBnU51TvqwCm0S6Kr/3+n8vDdaboUJ0er3OC3GNmYDUxwvhNhlXBH30JZsx2YNjSWqX6UCk NoIoj564qIg8VejW7Mz+arqBBbPGdhFy6dZcCSJzFeflPQ48/H4HkMjaCTc1UegGN1QR9osJiYO1 vAQ+Ois+fFFoAXfnHC+8Hepg6GicksHC+GU1R/wnYXoWcscVo0I18FL+X9RzykcsoC6kAuT0Tp/S Z2GDt342lDnenYogqGNcMGrE31UWWv8d07dpWYTz3y1BORFP7/zRYzPiu31xqGVbnwel9/NRdM2Z Pr6iHkhWw2BS4wKb7fxcnW7Q8lH+LIVkTotQBaOj/w+gWb8geHX0JaI8xEWPXVYo1cN5+F1Zx5Rd 9sRk9FOzyTBYyVtv4JFMgDshdzrnSr5zhlTm68OeLBTiCXLcyLzdh8SlMyaHWdqjifU50wNK1zCb WWtQyI0y/L0LNOSGwc4WWpm/5P1/KBCI038oO9JAcHWrjFZb0C4fFP1UNoRzULzKQMW751IJIq3z PCFjacsdC2BmXJgjF0sqfiAP9DaY/otd5/HURsXnRnXU3oOPI675p97mZSVg67cLCtu3cvyFYpwL hR0eFmMEoYSmijsHCuVsSN3BARHd9ShMpHaxnB8RGWJHOgJOT1Xt7ZPUeU9oOcH2QlK1ajGdFI5T vvRAlME0sa39Rqm1Efkgcecqe6bjL9QbjFoa9P2C1Hgbp4O6W1qctoUCdAp8qzH05cW3Fk9Ty/k0 s1BTbhgkgoOCIt3f+wWceIn5ylJAOT45jFeUS+1eON6ywwy75PytMkyfOaGh/QJTE+nsVRaviN1u gz61wl57YrRaTfvV0KthhL4aDr4qt7O2Dg09Du6XKdtQPSiSEfDKx8gRPPXxoVTeFqDUDKyml4+p lLPfHmrFXlMFcTVPZo06rY0tdexhr0SVmriNxJ9fmx2lZSTY1HuL/trsXB7k9oVFXJjxVwcrjuAH HmDolKQbQ5fcMutlE3utHcnpkilighsoqpLnk8l5aSKHt7DYmbpZP6eHp73VhkZ5gLuoBKzBQ4jS FBYNDxcS9evnq/KZlhYuGqCIGdfYbDpZsIltccYWI1gTlPb2x8OFQiHzFUoRZ4EX5MDM8/gsEHp5 E02vKn76cj+V2D5zO+dZi3plAgkYE0Hb7C7823eFY9wgmBhz25thJQIsduD6ZsL+JC6tAunp8a8H xm6SSwiglEIDzKx5TfhPMDJ5Ow6mvQ0NTD5olo4EZ10OAjOrSO84T0y8oQZsC6gXz2hF7NbDIRxl 1I1H45gB+Y3ULBrxRWKPlZa5sULVKJ9obTc2AQQOR9iwPcZoOcSAl9ej8H3MpjZAmZOHCgs3xeiK S/Uz3fNQdeBk06FeE2f4vJZXFqljFZ5yoNCYvDPOYtxMh/NDxANDNPpCyN5Lnd4VNzYEtlLD8QON iqOOde4e2QyNEaIkqb31GiC4che++Ka7VkeWmPr3ub3fRzpDy/zCKGEl7MbrGQbL4pSz/GlAbyyx FXY2HvO8VoXZdwwhxJA20/Gt+t6XNosy99A6d/7C/O7sfH5+nvT5t4luhF4LHdntFy4Xhp/omPnO EE1EpEs4Dc1S5M+O10OSzlKrqKzFdWhncYkjAAvtDLT3LLnYYvBJxvb8XACM/Qh7vPektdIa1Lre Apl/hFv76p//8pG9iTq4WTLT7CX0doHt/UYEysKLfYA+CJL/3z0Rerxar1nOizYKVSnXTs/cnQNO vBFRR7oGDQz8RGlt3s87UcvWPL0zf9pQEKFGIINRrZdOiU4xoLz2dXBxM9TyxbjLUbfWb0DJXM/3 LFuWSoJUwwFQD4CiqxfIKtRXtdhHAj5J/kzJPSb2+3adZzowsuof8KNfv63eZ1TuX26fiDH7IedB SqlYpPGnYqIc18CpLaXUbldFr4dLWB43UXHU5K+PvmT8fCSQfC9KdXqsuTnNGwBfMbvuUtYRfcAF pwAj0FUPTueRO+2Hh85/SVKbUVcw7o6TEUaAYpOrbvDKxQo2yTEcYSl1XOTVK2LNmtHjCSxGA/58 BEes/7B+1a1osSKyS5cEKfx28UWpK9LQY0pVW8MHPFrfWCNmhdsbRFgQtk1A6WmIX6ANJx5HE327 wFseJPX07m9RDRLBjhbcBY42uyDxX50VXkoYN8/5KgZbt4sRgnAJbnEGyS9wVMrGboCwbFA7zhH6 u7B/zRTuWtBiq3dC4JHchbXUi7Nv+82SkCOMY3Q4DNTm+ziSZdHIttfHv5xi/SmO4e8HSy+44bp4 ofqSxOOYPA4fiJc+ZkwohMbJihDwdioz+K5WEJFD2dnsx2CxULBCqL2Em6AvKvcD5sxC2sN9PjEn l0yz5UzFZMCWa1Wy0Br+U7N/h+rc1ScicVY3f+HnxmQ6HgxRYMVdR+0SWjtckeTApzqZAambAGUs 7/CfsvwaOk0Z+qMBJsMFVP1GVQirwKaviUKzmpdGS4hLqpB1MN45zOMS/fSFIoFRmuNZqmEXW0eL dqB6McE0p1aWyYFGAXjRZWOSazRdZWvWo6BaFgiqhD5hBujDwh6ftXkvpawSRoqnEjiiFo8iHyR6 TnLci6OeR2aRe1ZAiJCddIwOFEmeZXQJbYE6fQ1yn0OEJLPRX4gDuuHI5utM2vfqRY75/d4AO8I3 s8kHn6Isyf1YnrbQr5qNKjahUSm47QroTnuJIfwLp69aqut7slXUuJeaSlG+jdX3o48TVnwmHWDc 4c29Q+qw2SzzdVj+jWAcVxlvJyLynD/6CVk8uaLZvyyJQ/gUp6cVPC3kl3yjuF9dc8bKRC5NXz4S 7u1jzBFJeXVkvysUE3qJabG1D+fB5Ea0seir84n0WdOdCzvQFwg72fiowp7yIpDIOAA2q1B+G4/I HP3/HAWsApK9MZJQTNeirqsyuSRYADD3dPe43nH6Mol4JtKzKAVsiuZKxujv5kIWYPazO+ngVkK8 aUsFy+f9jRHk+bP8qyyKaHFcCg7f39VihoCOxEhrufS6oJ2xJNIp75rRPmG4uWHWlCr/zlCT8FQM R3w0QCyQpIb7hSzZdU0CMa+AQIUwe6VUzWSeeftmvWdgTQEVb+13oTN4BeQ6LtUkKidxxtTPdTDM 1quBR4kp2BM+F8ONwroVNmQ9Q0OOJMcddJnFB40UClVQzypPS6wGwAW07w6Rlq8pXcX5FsLlNRRH 1S3VNDv5Fu7hHYLA/nTCOI6sSr2LdidIa+vPpWRy01gJaG0mJg5AkTWfMofsOsEIAWSBwR/7ycL5 0mEXBV6IcGXOrPrE8fjPCkgPbbf6+0/XKktS0RUBfppbPBAboXzbSYcfhKidsj6VPqvbwQ26jR/m hZWQHqRAdo9I2PvSZ1ZHFY3hoevySU0p9CkEYfAIDep9Ql56pdsIYhRr07MP02wpXPBnOY//fdEx Pc4pu1Rgh8CL6pFjLvX2m0ieAa/2inprumTRuQEVq5h2ketyqyTxVxSZAWkIdUWVx4T8CmQE2qiv pXkyVPrcgyABLXW59T2LFwfQxDWxKZC0nLRK8rto/gAlUr45aK9BMuJkbQbxKmwsB/2m7Vw4UppB QpFDeEXr1BxUy6uc00L3gvL6zU2oZXaWIMUIHR6HRihOyr9M5ir7GqwAiXkJnA2zHzkY1rU9u/QN lKxZezUZFwRAlotukmkQQ6tTv7SXFN6NJMQ27yhNFaifVV1/lpdjKLNluAnjrmDJxwEcygJtN/Rt 1bJ90rNP3/n6R9nMvCZYsmyT/zU7qxnWnE2RAh5b2zEvkqkz/I3Y0YReZRsZI3c4ATdAduzyu5rN 4TH2iSddiF+r5CIkjXZOmZ4AG1q5CKyQbTnDO/7LzC6eaXLipyAhy1Sg1oNnJctEMaxPiQ4vK5TD Xy/IeksOflwI4boMSH6xcMeyHTz0bN5ctlqkHEjDhPNm+QxD1UHex77dXo0cdqlQIQTUFFHC59U9 lxd3RYteF8xaqPJvO3LOT1bwQU+4CCG/DkzwdPa8dywHV92hkn+aX3i3IZU0cgNw2B0veQDfxz2P Hxhh3mMDhbtOH5xozu/K9r26nTTyliL6MEcBZK/9YfqgRtDvv25wby9ucfQZNPDgUcuagMBkYEr0 ofMfnXGe/K4p4sOtCQA8538w2Qy6LgDAPg+dJj4ZzeQmEEpOFh+uxx1NAHYlHvMG9NpyalH49ntO 8MClgFW56KxGH4R+DLXY1ciZq8y2PZus1qc1NlCHnV6dBAR2xV++6sE8kmx6BZv9OKNZ72og6S51 xFOkAd3+WgLechTDpzBj219CbfIKvvL1//ZE51Th2uDWZRMHH2sMsZdwPgbsZtN+Gv97QyHW8HF3 SgYqJLvCMczAkAzSX8vRxgT6u0qgrUKKPcDDIHvTgsd6MpVnHGGm9ocTcAcXvqiYUvl8ls0ChwAX 2QWLP4NuK4NRykQ/hdIHAFfZ1gK4sWr21HxGBZAgSxIzlMtpOmCsdI/PWXI0EY/rAwv6nKjtjeS1 DZqdywBDcyXz8EvA65WVTO326/NitSEFiIXONx9ErPkuUSozHJc/S3MaHIqKl3Dng0Fs5L5/wqiF 0QtOGqpFYz/vueX+L4Esq+BdDLG7qzoUTbh2s7rLcPhRT2Mrw19sx0MmOSk1YwgPaw318I9hRIzW KpX2q1gv61I7bHOwvVat2JM2I9EamMwLbRRldHB0eBlemUUtRT/pRCNVsWtloeYAGGUD1N+YNy49 H7WiBt8BU+dzR7Tn7NuO+s9NkzGNB6DkswwO4ky6RMsSQj0Rh2c0qHkdgf7C75Tco5/8a+MyYy8F wshWV3H82GFvGVwkZI19Oa2m6yPWAx53JC1TcvUyCfATkbaxzQ+IRq9+A+6cKD8HwfzKoqoBtde6 oDdGWCs25dPvf9c1W/I3wCNwIscBpelFMgEu9uDlc89ze9h96TYCVZXdpBazP8U9uQvN254Q9M/w FOOomAW9RWTEV6h67m7CMTkd8BKughYlDNDqbMQ+luDfNNkpdyGhgMKlIaFG21JD3fpiOnfFM0Qu D0WTDx1G81r0yY7/WKVFrnCZZXPyv1mAhjQch71Bo8y4eFRY9rzrgISeJJslqHzNvjNQW7980mxx 5ViQAmcmH+EEVhMKDFp5rHB8E2Bhnt+25yczcukO6RIHvS+LB0hceLgh20o+MT/GYuTduwtFZ0H5 wlk0t/t6dFbQCVf3/WhIygdaapdF4uuhneVc/AHUXEzS8aFSxZ4Oi+8++6Hqu067yPNu+mKQs3mY 0e1rD88FvSjS+sRRgOtbT33LHm4jiB5ZYWX1RTcOwYXTXnCw2s9/uYF/QV1HVMH269ZIjyLvWWK+ Q12YpXE+auPrL9F29XXoGL+RDIrUT1waUUjruBaHkbxTR1UQxuvrIxdBAIA4oZvhFF3YJ2wtcz+m 7hyAHZxG0F3+54Os6g4MQ+9m8bHZWLiHnhpNhsrUJeCB66Wylx82g7stIN6L6OXMo8VhNeY84BMu NayLxgyL8aPkzluUDJb535P6q6quaiEFezt/rXrLkFj/BdfK/LDPTYpJMPCsvjmG9Ho9TEBS20Zh 463xx9zLcDizsQlUtrh62kJ83Tex9NlQ+meaQ3rkq8Hym2ZgxZwh9C27Dil/8xJCr52uUKx5lSVn ryTrRdTt2SObsfaHGHoNZJXzeFZh4W2UpYCr8wkYTV+CnevGQTw9V0hNSs7Yls4fx5Qh2jkNjD4X c87k2WRilCkU/2fr8+z8kMhrBdLfJUItCb6CuvbjpGsqB52mZ04J7Hg6rb70o3cQFewjbPsOkp/T ue6Lpmw0Nvfn3PnO8r0j+XzTRgV5uj+lUSoHI7GkCZ9hi7BRvSrzfv2SAZ3H24eeyB2NJ8plq3p2 gNhxLMqF22yfifwAkDfBuoSwMIHqD9PJwHAX2XZn0RH2XdThhtP399XQ6E5Nl8+i23ZRkHuW0O4Q cvp1HOsZvwA1vDTL8gjEYzIj9X4jYjuZ3aXy2rLw81SWKjSAuma42BmrxeqkUgYxgug8voHusaDI Vdvu/579wO5tgPcrJaWvvtXGQ+uts1hWFkP6qsFuGORKBDY9kNAR1Ay/qhW9LVap1DNiz7HWe2FC JT7GDf/B+JuAEp+QM0rX+o9bW0JYzTeQZNbDp+V0XzE8hDu178TTF0ub7iWBwq9/peJefPreQK28 O76g9DdUQ5fnaELd+ln2g/l7rq/hnyBQbWc2yw6Erw34+9uXvX7Wa8Kb8tEC/b5VTrE1xFyvXr0U BtMS3wZIneycyEkQLgjtlnZ289fj1gBbg8vwbzlpn27Od7h0BJnq5+NOayjoC4F7zSG3aow04CQu cW/tpSq8q709ZqEIlGCnR/FZJKLvTyKeimyxOgujo7GDJMmjkTQVhbn8SPj3dJqDIpR1H303W1oc JTXF5Az+uMZjREOYp3bXsM3U73CeoUt9ZJiY1GsYJLuLgeztOTtG1+r7R7WPriszEk6M6avKUQlp N95YcpUBTTPTNNNSUjUsz2CuYZSCesUNrel3zwwre6rXJtoEAc6tkJJxUnjAVCT/tSklaRHPvFYz 442GzDsVpIsCs9cNT6T6NA0wejygO0UeV9sjbNcX5NDpLfxSSPqgclgUqb6EfR3BTpoxfW+ENjDp LD81JWgTIooRjVt7dXawsTpG1Y+Jk88rf823M7AsRW3go7DPI+4cMBwZrnZK7VpUiSKV9qRjU7tl t4AOAdbEBgF/eykfHkoyxdh3BWKsx5VVcFDMHcY8TMqUUJZr82bhDfF9xxHAbO9GS2+fUfLoDPNT 68uXYvS6Es6PkDuAN2GVydk9r1iiUlA7W22MEexGc5T53AVgmUdtHDpXk/GjHHRoCtftYH+qn+3F tI34kkZiVFbeHOKMQEy/6DDaLX7NV66yBJZf5s4gxCY/qn9COOywvWnQ02ZNqsqNywLx6TtbO5Gn RJL/5JkRq1kD8ylSiD1VyQ5Fx7Y9hc/e9hEFkJGe24Il4rTQgCKb/r43qoiSA4q3/B/OuWhyeceX 7HbDj+Zsv+DWS0FVDxaPFcr9h5od1zukwI9w2qETcakq6LI23AeHLdiw0vB1EjPwO4+TNsS0D3bC gjZHWTsRqHfuvio5v72+TnHV3HPYGvIPeu7xeDSFm9yiSRUEejmHIaG4pUSvGa17D/CaVQ/DmpKE lXzpKMqzj3pWbBYWYp9hSoVD4Wsnkw1HMhyfBSzaFGByXzFv3np1yO645NA7GU/77Y7jvOHPsCQj /gcwUFbqDcYlUA1rxJKpDmTQu3RiIaxI/obNIPJZ7hQKSoRYAVJLchoXWLFO46r6SyL5iVsVfBnX wf0LmCU5LgMR1s3gs4rJyTsDnhlWXVoJkRaEQw8eD70h8ppa1cirM4aGcJiQRFX39h/5bvMtsEYk ixJStE4AoTBK59EQfi5m1M+gFOVZ/vQRfGHMI0MQ6xVBoGTKdy432El4BR0JnagOkThbROQfQeQX b97F4cwiPjI6G66awm1Rv7Ebc7OdeN9guJ1oUwRvVZBcfdxLV8oWQeCjYlq65HtgIj/oT7izngQH RftDGj4gCR3OVjjKeWebVi36vYmseBnZAZzgn82keFilAujllNsnjrOtzEJlYL1wZayFkiPSiUIR Y/x73KIuhaljPdIAQ/0xUXerotqH+GvV4H9efxnr/v4qOnO4QnHPCo/PTwz/zh0JhsrwqH3a8R7G c0zWkYsELO1daIOjDNZ2+YdHcWVuhEB6isQo1aWy2Q+HI9m8ir0kF2+Dr36uWuiqnJVZwJcSHwtY 7SGHHtE91tGVbdM36zSaenQT2xPQnP6OmyXo3tewcmn1nQu+d5KmLQ5PYddrMFfejVEdfszeI5wX GoVGEBKuy2LEocZYM7gaOwpn5Uvbgl/eSNOrup3OZC6B05lAAtxKK/WS7ui1qMGVPt22reS7VfVz zBlzYEkVPW8Hii5uH32zPiOcntupE/DQCkleRsFF6ZcQygfF6m/s2dQKLTPnxWVXL0WBu6RUfrIP xn5c8sEZpKg9vaiaZNW86IOXCBDNiJ0jkLIaUrTgC18doL6c6efIdPj3xTk9hRg/O7WN5bn8ma7Z FCV3CkMcGGa9ziduBnZ3tY/WSutLDaVWDcdsK+il3svkvu0BwoBkQHfGSL88XYjZCRWIO75PR9RE ebhcxwS8v9QARNJ6Jnqir7d5zXMLhFkqba5cholsgKgGeSdUaKJVmFUrsTfnmsMJnLuDK9txXGWd mFQ71Ae6iLwY1k0Gylhu1BBrXNvvvfV3TnFTC00CF8s0HQb9bJzCHiLQg5nkFFEiJZTE5o5b1sKW NjEvyHb+LiSSC2HMZQL/UA98IMvFeWdnxXkOsManQ5aOkV4ddp/Qp8qvgREQXxPShi/2xRIRV21a ajdjvKxyzZQGf0TFjW2/6EQ3uKGCurpwixf6cYayTUhnYmPg1OAClp9lQRbE97qyfVBgmZ4+VpE0 LqcdYby05FaK0djpzk/P523sQ1g9jdTCL8pjT1EpfbI+GOOBT0XXpo74h+lJy4DijYi3l0ZDqNSX yeUq1S9l8u+qdv1DTTvBy1HWfyVz27MM1hCYqnaGBKJwO60md9VtvKjogCjv8MF8zTciKRKqX/Pg Js1euJiif1HcpCz8yhDklgEMeaJMUkVDRUQdmv0Citu4RvGXiF4HXlLw10bpZu5tqctxcPxxeHr7 hN4+B0ysrhlw52gu/ZD1rsgBtQvm8eJ/tlPyMP9ftIyjNqqSaH5jeAp1d7qzyBgay97PleLvDzgH LH7VDeX3rp3k9t+AutsX0/z0o7OLe3WCDt0Xws2jB4+AYAiNvAY4k1wrtf4Lp2/XN4miS+YRXtb1 36ixpGO7uZB0z8k3RHHmXdRsNmtmp10NRhP7mjV2DwWjPT/hyrOlwK5svcU2TEtpL19+k756SNnk BLR4A9/jV2LzD/P0nrxTT5VMhUfCxoJGsw3n0kokn33uIO9OuHH294wDJ4No/WQzCPJVJ9ea7bcJ uSf7oC09rzeoeXigauvIDNXlEAnEKHNX1XuPKqP3ExytCkrBA2b4DluNhKoFDuH6Axygs1fB5ezN XAINtXIuHjqmSnj0KbqBFHjVTgPv31c0zbXDz/vrBAL3dLS3aXOmDf+SpZzeM3vwMDo4bE2cBhZe dBLMpqU2JXGTL34nDcXC8FOZMEvA++RStcEQsP+XupigK1SN53eNq9earYQ0uDawWmCBT78E84IS EsVLWrfxz7cZ2noqRc0DGb/Fok/OVZgzRfbuTz/rsQDD5wskIgv/jOywP3JsM4Ww0qoBkq1oEz57 X+Z6Km0CDONgFQAIRM+niVFQMeBvXVWCcoLo0bB27JiOEySz7Z9CSrCohAkx3l/IdDgaknyy4iFW TAb57iyTGBZI87oKKdqH5lV0K2DHhn3+wIKL4ej/X62l9DrdpyCM1lI/Of9ciZ6WaSYnrRVrc+HX r3ZKptmWeviqoqpaR5igIiGSTZmXuCSw2bhSZwypQCkJ5MJZonwT42CmL+ZZPHfbCcVvt9i0UIK+ 5gn4ZldCirv0QJTFB1lABazTSH8vX6ga0TyfEOLb4+YaffqT2IEdTGPhwPzKcG4/7OWie+jHfVGW BpEN3B5OW3g3j12fu+3fzUwc9h/ozTknvbeFEoKwfXct7Zz4pSECLMcSYf4NOJ7dHa+/TN3iurcN FvPQojozHXRT5axSheUxPvGiW/8xqmXgDoFeoGr3IJTqM6xX4VDOrpi63bxnB+zXI3vXu26JydVF O4WinZ+ZohAomQuqF/wD+ZCiU4iK5bjQHDPEvIe/pLeXKJs5QzJg2xN0Ou9g9YHujBBY2WeFQz+U XXvT15EOs3Lj3NGQuBUS1WMCHGeUs2EMt7ilgSz9lD4wjimiS6UD/HOJZesW+gywvaS7hiKxeZ3O Qg9LtskAR/x5CWAaT9Il7jHC0e3OrH71oGugkOEkBU8dSaqqbddjczbU0Y0T+677aOl5C9xzO2im P5t+5+eOc4Ob+33LSwG8KOESrGgQUC0vb1wmI7Plk+yGbeel21+TsBCLch7VZqp4V062CF23Fi7s 8PL/c1hfWm2WUWSfX+y4U0KvH3SKlXJ+s2kH8AFVg8RrKHiSkzfBUJULIdSsbAiJi0VIrNFe/mom 13MSNJ+tHLX0a7t9dVeFBAgVSqF3br82xf6fkeV+9TmNxCHUyXpCWMoj8jghoC0toSt3/ucWyzCW JvLQm6OR0Dpnn4/osSLPoGtBK9o5CRXx5EgPQ8INB/+rtK0xXdYVSwL7lANv3/2wZEzw8s2e9kdq LHvcEGWs9qijtqlrNHaoQYwA24ndb9TFjwP/tZeXQYLIWJZJC1OFJQ7dgfTKBvTpZ7DYVCUyeDaP EN0ixM/HLBfiBImEhPC3H/SOHNwOAmvcvJYMZocQSFr8Ph/wi/JcpJthBgOmZa6ay6/fN6aF0AQS RPsvcYkA6uC+x42orQNwTdh7ncZpexrPDTeCwek8DvOQYAzY7egtwqtGmjfUnVxv/ZBe2Oj+jnv2 Pi5vpxcR1YnhENCfLu62lJwPAIMUqjrf31Of6LbuPh5ncivVZ11/J8MAnjV9lZZFQSg59ToNd6Da BUthyVjSb+irW6olZP9z3qlfkr8EoXzSJw+BCAahdO2pxQkYMetyyBM+LYDXX4xn0YcD5I7hg2t9 5QAgPOqY1dfmE/R9x09uzXlXF1aeXH+G4/Fc6qXkrRWjXDakSYsF20T1CcfZ5XSVsZuJ/c9enV5W Hnt6vdyQYDwTwpakkMUVh598WBvEpX4rSI1tNK9gAcVXdUsXI2aJQaq+Q7YhlbWXablT7UypxQxU M32MorDxQ0jjPFsqRgPg3t6YVdgiq8LmhYLPbKOO7mxOBk0kU2Z4PfkKro9GuYd3ttVzD10vo8f8 p4obbxd95E19Mq54iIrm5r5ze3gThH4yvvmZy7699m4El41qxm92zowdCab/c0z8ifTOuwJGw5my CIyy6ogOWwFYIwN6v7SCayvGS9OTqGuLSlpsjdy2SHH0gh31UxepsOsivhhHy3ipNymQ0xpXSJWv Jx/hz36YAdrcum71jCHw5Axf5AC6arSFQ8ifXjagf4/tgTMfBxfBaSi4LZ9IAx7gQ3oFDnuU628Q oMloT5KbskXWcbmgIKjMTA1rpByvhOpUOG7h6pv4iLkUsrdrV1GyojnwMlT3OH5sbGPARoTCYMqt qVKRpLMdowKixUSgprWwrVcY6IxMBhSc+1wpFslUIXPlWNcTsvb80qjPJbOWQKgelsyCVYlWvbK1 Kx9+6GwAV/2KrPhyhQS3+LppIuFSIC02kvD63FGFF+8FZ5NdO2iER9vMvq+SJYlA4I7jUb0tKEwz ZZF09Oomn504oZ+zSN1jucg9h67Sfh1XcD1jxHBjXJBb71HGcA3cc+HWCum8WC4EFvsWEK4JFojc DGKGZJofbg/mhPAKwQxKuzJ3MqM7A7fDeyCfyXvFEMbwWzcn9lcIUdoODlWZOmNjXycrUrUNAmH1 F4WHbRSxi/6fn6yJO6Lvay4lQEkx8LT2ykmKO1m8CgqIL/sTzqVzbabu23bnA2yUnT+J4bkR/18N dR3zwK0y1rYoV4pLoLJNkte8k0RKMjKLhvZMDpxBrnZC+JlP2AdyNQI56EweOUJNimj2teskTwC7 uil7RiTPkFBhepCWYmQPSmqpLqlWoSOro3hf0tcpFcgBikBDZ9pX8H5D6J7s/XZ8WxpKwa7kKz64 qgi2HE5cG+jXRIt4lPrK+ShWeQKcBmMYjTnj3p6Hvkl2ayiEWZCSY30JMuiyUIr1TlrL4VdE7Hux /d8oMRRUNIOrDs+TQSLXcELaGe7qtYRlkpdnYrmlsjuF+Aam0YR6yeShFxn/AEn1DaoOLS0uXWbx QY2ppeadhzmSEowQ2PBl85zhjNsUkuML7BC1G4RSXxaHcF1DR9gTXdF5ntyJS+GF/pYkm2FQnk5h mvbkKZ8uf7WG2lM0QX5wm9gtVkxXWZ4LwJ3T5x+I6/fxL6VQ76VOweb/dO/L/KYWk6i1jXKPv6Ff wlUG2f3s+tkI8YM/Q09+FJVKnC2YqQ0C7MiqJJWQIAjbCZ4bUVfrKUQPYNiNlnQe5m5Ox8uLt1Wu 8UM78mZvH8OLTUs9IwkFuJjLYgdNhVx6074rrbH1C+rYdw1xv/4avEr654KtpDE/XlmOoCQFb9g1 6a2Ih5M36TimpF4IvcQ5wVAKprJbdfjNhp6ISyNrSqU5rLwAzXv+eypRFMK2yIrdMtYzfhQIzazh fruLpVnUASGW9TWcGLlK0oFAHRjAq/T9KR3Fh2T2fo+LrX7de+i6Q800d9gtkndcrb+i8Fxk0fCs kb/13H9OdKVQYARWOoT7CYBCKGHMc/d6VTcnTDgcFXZd+S4TPKvtTWENA+B76+Pfc1UTjhqArWab EIy9NBHn4PQzH1kAhNEADG+FafDgZb0iUcqhqJ1ZgMZssBrbHsJTzBsWSX23lV6pyY5KDHsnI7+C 3ojVactNevU6H6le04ZFe1k5be21s2rPYsngJUBrV87UL5bQALxY59gYN5uqp3ZMoVjzVIaUn1iK OHXaQ8vKeQfWvI5G9ncFuXonyla6K3MddPVGhLyVQ5hFB7kY3sfcQMneHo2GpWGB0kfGCGcwZrex ZnGerLk3HZpWIT8qQhIiwbCigrB2MFpCjoQXl2AZgYMrafu1sq39+db52WbLfbd9fskL92zIG++a 5OSC9jSqHgzifHaKf6fAWL764PeT0Yf2XdDR+XXPobdS494mILS1YAXgrLCHwPNEQsQHMbllzw10 OcX9qiszTjUOtxkZSPG2Q1ps6OYiXHy61aekw8eXLOx1xHoDQBDeEW3A0Pc8XMOkjhWMN8lfz4Dj 2j9AK4Ybr40HDys+cVXSYR5tdW7gPabErvs8oO5bBwx2duq/rRxs8YaRg0sy6cbQSKepiTBu1y3/ 0v1XgX1DNxOwnoKYJixLsU1Ym3TdNtqZJPzkVsh9Wxhpp0cXx6D95FfZgJJZOYv79kVSs9Xog3kf IEOav2ebcHrgU9lcP1AiqRYg3+qdIF0TpYS7ay0KKHBLSwriNh7hy7OuLHHfhpN2sJED3jTPz9j/ vEKD9Pm8FlOozUdZfhE0qt9qA88X0Uq23owvREqB1JA+D+6W/D0OAmRKX1xqqzwqxdoj9EasxUN+ s/VNa8dFg8PTyxs8rpwzcc7R4CJ3gHBQ2Ua4CN6tAk9GDZ/YXekSGtJy6WYBy76ay38njky/NXHq pzc7QlHSeWtwfH4TPPd8H1pf0Y5KqveGW+MlLrrzK1u0E5i54UatunIUqaTubgNW9GCpGf5eZB0y lPPiH94/Y/3AEDGukMxGTF6sFr56Mju/0pw04/ul8PsN8DQZdUq3Wmx2JhjRotg30PPqp2IceV2u Lqw35qx3OElp3t2SixGcfvM7h8pN0362GfUZnnMqZSYquo4LLvet2dAjiCx9q0eZFg7hvH26T+Fw VXFY8b0fDAPOJVYzkYGEbbnwYVejX5BCajmYLqTwUvEELINozu9DmPv4Vj4oC2PI2a6lKW2JCtT3 6ytr7zvEuVpY7geyBjQFvMpQ6UO4jkIkp82FKqLXOOKIZKovgeEthR6sjaz6DikurOgnzxFrPTju 5lcjS26BP2W+zAKGf+PQkWhjgkKX3l/hvKOjVL/fq5ybUWyTTYgyiHx0Fx8B0KK1P+KmyTfQEjgT 43OiwZpEsCgrdlysg3wa1ms7RL60tKTeARAKWgQk4i6Gpjqs1RpCDG3XxWbPP+9kF0JEbnqNL5x4 PaL9wnQmFLZGoWLrX6uDQCA9cv05WhhOdkXydNSY0VAr8zr8EZQhwwMh+EgqEdqiyfTh3fWX3OXD leWwpcDJ0roLU8EeUkoW9MPd5i3KvSARXLxXdiJZMcHDFsj7NQ7o4CbrVUT43S1L3gbyIgaCatQ6 CtrhA3iHEm9isqGZIT7b8VnAUI36nP2J5Dv8dh7EG06azh9m8Nrzbv1s8Jh+MsPahaBSaou/xMw9 p0YPi5gX/1iqqdgoqekY1E/TIovnIYHKwKTnNb7j5V8NKJ9UKEhqE9ne9Jhd6Iyz0ZxXJnB2RQ/2 nShnsgEDR9xJ8+OfzvAV6AaLOrEaeCGc+PRiOHO+F4uOg0VXNoKkEUi0peggrmthcs4teQUvCdKl CtNs9xc3PDavbHgUHQBN+qwYjwn5gAQk2bTs78NG+h7HyGKenk0Muo3ixQ9yA8uzS6MFvrA58i5W cDe64M+eD3tDRTH58UdSUYYUWW5IEUX+/sNvfkF8P6srCBq3eWrWAGfLi7Gnr20MUOzMjYXiHIXQ t/vecvxuKG55ktQWM4EZut9XF8ibyD32PLYMRI4UcHH2xuAaZDdjGtR+JXf8VZfTCkEwr1Skm08e mll1yk8ykyR/QSchWw3P4UPDL+dyyntaxf/aB6eqAEkT4KqdGK5LCT/szsbhe3nDJ9Muhg+whH9x Z7q1fPlCDlMKvWqmWiTpgim7I2W7PNuIzWKjt61XkieW1LnuJmSWYfsLBK3L3QdfTaDTJ3xFgtu6 IIBLLs6egMbT0jbds5DOUVeg1a7emKSzSTYjx3KOzeyPXnFdFV8rLzT68MUFZOAvuP0xVcjVucaS 47ion9yLa05LwFyXv1Zv2pvaBcBlZVx1iPgMovOQnw1D7n/8iLCKEEJXMa5MkYslWZ2xRnDyjf7M E+JUrOD1uu9K/JjeXUI1QfSKmftXbz7gkzCqyDRH32nqqGh3nfLWkU29/H+5gU3GeilfhmunfeTP I4/FJR3ITlz+oFU9mWuAjVPHekDkvZgHyL5LfQakkwWU/IlS57p1yzbNx7X935lAXaTvztaGvcfv yF105bFxE9Wz094EB1FeVU+hAp6u2dlbIHwEUBWXPrWhU3WQ7TZ+l03olTJ/gNEKonuC5YC8PnSi kuhlxHKvyS8FtnvVXUmPKsFOYUTdl6BaGWbd5zeKS7ysOsZpd6eX6/bEP+pC20j4bUEhDUHTCjEJ 8HCFe4O9yAsTPGtOJNcj8mIv925AXGaJMSqLLRDVyHht3HKdgfhE/2IAd5Gn6gTplGT57DaJhdq6 2diyDmzZzbNVp+4ICtITyhsUVm7bUy5IWmQfw5C4Visqeva8GJVZ9pWs41K2rY2AX7LxdN8NPaR+ TIYm/hk9qcMza9F85bZG53snKW3HJL7IcqaVVgexXvKh3Sq3d8GByixBfSL7aIDESlu8et9TKr0I 1n9AFo4DZsQLWIvwyNVVnFQS0gROYLwI7GZTceP34dukxl0RxGCPjONp9FBRvAjPqqkgz7VDUVdX uaXM711VA2H1ylG2PN4sDdQvE1vJb1ghvhdVOGd9LxahGor18+14XWfAyeh1FKkqBecbdn5hpMhz lMZ42NE13JzOPHwJeudYsuSvOICWB9xjJPlcTkB5C4ujndeGnsmost0H6VD6Wjg2KU83i6kQXEHl lJas6WF3hRVDVFnZKwUoaJ7e7aNQ0nYdVh/6Z8mIjXUD0Y8ar9VHayfTmIb9YGA5WdLWJRhRe4GU 4CYeJzjv6JfvqsTgAICY1h/N69C3xXBFX3/mBzlBl7co5zB8TTY9u8OQgEtIof/UvaRXFJXx/TfP 7uRHErGPLGfDYzUCzS95YoOujORyBL2v2xMAALt5RRTKvy/yDJ/tGhwP6E9hPpxaDldIl/AMnw1L caeMp0vNIgNDuZdIDqdzBujJw6XiaHC8xc1EBWwmO00qLsugM3Y6EZZUTMPdenB1ISeS7Ce8+oYg P4QVkiZUEtMmKEPqYvlFzwQh8OMMctGPr+qpM3ipmgDeiLAtuCWQz1Ti3mQMVypEWWcnVG4u/ZEn z9P40eT1mylU3u7Im5jceSso8uvbUdv5TC6pe6sWsCAWimerhvKKaoTxhJN5QrD8Rf4tbLPIna53 LRqeTd8351CtkHHMgmUkV7lmKgShtgDHHZeMyxQpKf1z91OOd0VF54rtUQqUDD4HfPpQe+oiva4u Of+GBJiiXL14aO1qERb+y1J5TZHGuTBV7q6QL7hjDMdfv5baWeBUGEcI6GZnXPLZcXUr55SmWSS4 PoUxxP9AAn8O0cmGOe58iONeKHv5cVNh9SXGpuTcUZf6GNcl4fGdMg10c5SIgNZl9ZV5I0Mp7GHV viiE+FGS+jQVgsnDbEL6qRyfVgMrFwVH3xa5/Yfzo0SRfFcw/4pSO+97EtogwPzeK923LJ1BPPhZ rPLftm8pFXD4ibW8iUI7VAzOAy0QTjkrK7KA0XcaUo6WGp9At/4Xm3XQ07tF3U1FKf5iNIuM3wc0 zjlAuqlaKkT9awEJsM7DZreZFWDjVctmFSWlIO3RAzAEt+KtGk/EXOyy/7FlH0Vy1He0UtiuQ0Fd U/wQEVyJimcLJemexlD3eokvGiLwXjzrwQ6HmNKBgaDpRojs/32ZMn+yqyBmcBglyerqiJuEoMh6 CuaX5sWOopHriiYZpeM4ckpisYmwcS5+u5If1OXXLfYdOJ4dxrOdlt5h2+nrny+KoRZedB9ViKBL TysKMHl1DERORuAfe2AXyeB08DrfnXSFUwO0xUXeGhBJm4m9brd8JdoNgRFY71O3SZ44WFoVl9XR svOoFtSBqHimcWdopybuDHE+08LVV6qtWG76IzmjNrCQbYV6xGzMn/iL1S/rPFTltHADz2doaCkO b4QPuttNZhGYxuLI4CqUC7p4NRXkIht8fxcJAkf2l6SG5jnT4VDeAb0OEaUmrrv3HE6M0qFdW2QH HNgNWQkO72mObUfDYou3O9QIhedP/4V+gzhxs6v7PYgJGI6HDEBaT4xp+Mczls8e+zx37HZx8nIR 0CVtPCRVPJm773hJ8TK4252dneew4xNgiVWqOt282QvxVrAxB7VYdNMK5Q8BmMIwX9vt4XM7dq9f BNAb9M4rZozVttUK6J+pDSQlmX/OaU/HaoQLcYDryFq1QgBN2R/xJox7X5DkO+IGDxgKkxiUBI52 PrHBFLDAdtM3hbs7+CDczXmx2DHtKxVCGG2qb6h0XR52CESwkvjScP4LmMea/W/F90yDM6I7tDFR FR2SN9OrEPAbMUPLuVkjoUJKj17vbLwYS3/u1FyziQTMiACkZvQpWyMORpRtSmuv23Hj6wF/sRKk XA+bJGFIs1xO8HUaWfRUkWR2qhzyHyGnITTsfTaSHsoJHeL8GDqoHrxyIpKHbat/idRYfG6ahYBP uuEZ1Eb1B/0WhlQrFam8jZkhshg61hyiHdcONpIHrAMXOYvZQ8Yd67Wr0fBAZYQi6ICpmX+vB4cd nGwmOJJ8LscIUlFCPcsmmgfD3VvvEL5bpj5zqxtF3QegUzTXUf6iWIC97mvQadVO7zHYclEosd7p 0ESrfT8yW8POSvPtWRgQ1wxTPwdpk+4Kjr13kppWwyvk0dgawAVLFBkGBMxCZ4TBabR+1Trrffdx cv39qio39/NexKsOnmENzDUwDZSyDFX1eupwnEUdGDKFozQooLyNyCNeEkMVdwz3MxQL8dXlVxzP TcBIzkYX9f9r/rDuZp7Sn2l/dZRCfkb4zDMQL+Bt9zpWK9TYPeAMRuTc6FVbkK5Sv+Ry5u0H6cnG 9KvSymICqvmtWGZK5+ghF0+xaKVKqkt0D9gnZ5G9/vEjXdg1MaF/wIomJjBfnLUg3h/3AjxnYMxq gXNkePdDkxenPAoeBW9xdLUqhJgdRsTNyJiYykg7RnOo26naQ9XyLsPZ+XDuGBnxSi8OB2+baqwL oHwWxCdtFQjdxNGapq541Y5N/osAiz41Yj1enxY/HzRPcgQTVSU3pFFXLh1Pk8bzVeMr4PLN1DYO JxDCIoFinhh6pLtil+AgvqU6ewMkkelRu7eXEX+j3MfJFhEeenb/v8Vs6rTv17FXhSeRTB65xoIv w7coEumoxrHvv6Fr/8rTJLMr4NM2UC/rPiEjjoDAaTIkVszglCChoqQcDxaszCmD1ICnsjnC0662 +jmJX54iBcoYOnQXfjvgtOxa8jV+YnnCT/0qKGkw2d0oPLY63JSYKyFDiLhHxMTiEBx23fTXkk0B qGa1GMJJhshnAMxWgC+CCqCIfZ3k9nTxiHOS3DSablSDx9kaUWnxSxa8H5ic044JA6InFQ6rOSUD m7uxBJxs47U/c9h4mnhKs7K2y8YVPy7Xt4o3FxRcj15e21Z5ZDH7KmvxQjpmg/kNelAQf6VVNmbt meg8hah/ZxrnPPdoMMc2oXeRvU4BlJnMDx1Q84KdCv8hetoZL+J/wLrU6d+0PnW2j88pQaKuaqrm AiKCAu0U2NK2qIGIex7Z4puzkruoqv25kBksiz8hS8YiFnrq96WxGLj+LO/aOE6ozgwlYNbCXLlg dxVXcNIwaEG49YvfHTu+MHUlcXKj4c7K6vz8TnC/03La7EfcZFlnGUzFAubnV7DW0NVutm3bf5H7 asRaGz8fM5f4nEkFvzyIuCo9FgCmtICoIcUqGggZ+slfJMap9gP2vNbn47CWPKRb4fvQU+NFIDaG 7qS2ATZ7h9BepRD9OsAmC7JOxPlvMFZVl4kmTAlVgQHinFJGby6cx50qlWfzZeiEgNDHz1JaWJyi jOuX+LRjO/FdjpUnnTOhQmDnf3lfHZ40dWgc1fnC4xG+9i1n4+9Axxgs8JrbVRGssHVA1eJQCl21 qx8USmhdsmtdNUL+tQKs+/YSDBxn1rMzN4KTiraW5ZPIc9SIun7Aa+XQGx0Pkgk6RRCPgTJGvZ+d tfKkTDJwirValli26rMaL5aLXLkgbzcz//FP1mjWE2TW53d0NJMGCKZWw6BdVCYfW3DHOhZjCdh9 hOlLBDvh459MkHMYw8nuAjZpB7re3i73/QXYFA1SoJ2JlhF7oTfv1+XHTt/iziFmjgeq9Mxs7EQZ j4Ue0oWPXd6cguoTjAdcC2pqWhMVixnOdoz0KTyeaIOeX1LxmjpOhW6bP5DI6VKcTQPZJ11JF4f1 tAGMMrW2zDKI/iqbH5CNeAzS5OGVpLIaJvgtlj0Sty0b9yUGd+Le1taSixxWU4zTLtjbzvSYaY6t qGGOre1GttadWk3iE4hlzLBw29GJLQZ2ru68Bf4FnT0faAMzmipTKBe1R1SCW/hwmtWMRAG4Dr/f ScOABTku9VhUC0ij3AIxhz62DjKVrsDXQPI3+7M1hFSPHOfIq9niz8BEgAE7TJE/i033LgDjt+mT QBkIMtfuEOkTXXDu+77rYakxC1qx/DtsnqKwOHAAcXV5LzWJ19NNVSNT15ovRJcotaXU9Ddaa/Tz YU7ylF6Q3diAvywrIgon6NMVccz7IOCd26R0AtdczifyiqJwBxG8MS5CrKkkMes7JpWt7UK7oIeC eLF9rZAQFK8T7Mim+ry7T6EIvWOQaCsICI7UaoPbLOuogzzQMVEztn0duhVRHIcEnWnHe/OWDrFS 5BVfBorWISmTd/6VR2CWAQuGeSMQ7Iav5uwtUwLb4830jtqtenZO2f6HrB9k6IESwo9+6FF3Tqh0 TvbkBa+9JLofHICPJlGywit9cjwlUm0/DDgll71Nfkx+t8lAVAl8F90GIkktQYmBA4CRIZH7XyQT vQ9p12q4YQj+/2u03X5KsVP1dShJSBbt/OcS306e0uxOvreaieGGjvP8ctc6QDK3Pa22JxHfttQa r1jroQraOtNENsxDDQZXdIsZYGNiliTEl49lmA5oroNbW3+GA7YPf0WbmKQbg+xWe2D7dO/9d2te PzUSgDhL71WYh9O1X2Zm3XgpTHQ7sFzHA9jfnCXc1ydd1YKtGFJlal9hbGLZr0yazrf2KDhIqjz0 FaD+6eGMmAlsM3q6636jkS6DqyFEcFXD+f9JyRiThqRnBISRsDC0VMTmVPBEjOkUybPtZGvd2y9G dIeUg2ovaAcCieFBM42HQgREZxTsIFMhdilNV0vRwMRxYJty3cKuUzcuJTGgIQXnbrFcu4Ny+VYU JVe8rfpaZL0ILkChA29wZEZkjS94269i9Sh41YG7ZHU+KRbG2FEyEpaa0P3zZx+ZxpHrGSRowH+h QzQd70B2YqKP3fM7Inroz3aJ4ohrJZWf9Kwi9y6ll1qxpH4KIbi/wbwdVKcz4rTm7+SDzKoCjv9s glKvC7hTbt9Wl0LG2VYbqV38tanvGSByLxnl24nykTg4VRVemKaXdeUsG5PyK7YR724rbXjZaRgc 3uddMvAFqHddnmUYfbeeACvyAZ4p29sPgStyTMD7MGWe2UTqDBRvnhMsI/tGGMDQxHLx2J6WT/Q4 yfpuSxbrTFF1UgUGGds071GCQXBV5kLrnjM+0prZFCpUJejuH2+Ac5rh1Md9jTr9TSYI33vXn7lC kcrgIoOX26zo190a+0oaJK0ImO+DcSpmlsn2uqEpUh8xGYWQWVeSP+WGiCPC2ZcxqyMBucZ5kTFm 2h/A4DOz+T3UC++NJQUWUXhlkK+Xc9n55U7eQMr/54bAo92xmMjIlRBxOceC8aDdz1D4YGLwxzuJ hHtFFI/yY8BwlqhCWIb0An2E51Q9cm1W0JfhlaGnrmIuyoMIK0vjcZG3hWWwOiWGL4jJfetgX+tx uf4Yup2VH6bkpOuW9jAOebjGn2mm9mDxmMkXinnKkVfNCOlxCMc7xyrJ4a63p90RrdAR+WgHpdvu jfAe5+elkbTuL7XtJQiJF1JjBlqq3ZKgD6JAY1XS59Pkaumz6RpPl7Rn+ansfz9JCJBE+e4Tfa9v PIqEnRnYgbwB7MuKqW1rHq6hLk1ebhFXQIYc/dOca11UMtiy7nc0tAwF7DTxVF57ZuqWvBOoSOBl QxEZhmSdoRyzsdXIle3VblvZYaVRNz1xvMVNhqxIZmMTN0x52Qc1eZVkcMVlyXDXIBwi97vZdnjf PxZQvt6U5sUGbtquSIbvm6qTtmhNtiVJf785RRQUtrmA0kOz+Sp2/1yksd+SI+ZMgQgTwUtiLf4P NwZdT6KPBofQoA94WSshgWk/OSJhGXC5v36ZpnTaVJsCndu1u/apLjyJaTRqOyO0PsMFrxt4/hmh REPz4mB3xZlcwf23enemQzvUYGQYHqp1p1SD9LasBqU6aBoRuei8mAuWpmeY/phNPTg+w+HKnWTf 2YsTpJ2jSBs0Desf04Dv9X5VhjZiqubcRRGHrngEQgk2lJzTY9+9dCv6VrW+MwS5CfSHZ+FxnKsk 4skSVz9uzH8AkgtVZbpYF54St0mM3EnL3m6w6VL0p/V0NWDUgCXc0UB/Q8OvLM1ulsmDFAlaFB5k bQCpe6fcT8WBXNrXqwb51Nmx4cFiYvw97O10dwMgg/8kGOBcQI6PzJBM77npaOy8fHNppnrnhdRU RrAm4ywoIOXLwX6rAqELvuq3TmlxdUdUD0FOL/v7/t8ukAETPxPeufpXKG/Xblh8m6GKhPq12Nix mh19qzJ9CWIkvDDmdeDZpPxiBVJwqVeBRi6fwac7HsBfahtOqeozYNBlbQhVHVNTwC8hZx275/jN EcelVFZDQ99muBHkPGSLrojq9YuYjqKfSPGJSdvXMeujQfG95OeEnyfTBkfE8+iVRU7MEQv6XBXW zO6iPxmGPURneoyEd74bOSi4AqDkob8n9MdjJC7qb/qfyw5qT9Bk2h5cYVGHvyfxuFAw9dejYhqa vTf0Q05b90Od8KC9Vax3F1g8xw2vZIby8MXp6C24agehdSn7poR7ZGmaLGLxbwtxs62XsSAsM1/Q HaDwNrSYNKkjYnXuif7Npo6swcs8nMFcpKsSvRYksOA65Wqiw/I+cXjPADDXCdHB25vhW1NJuDU/ F422a+5d/6kw+cieHtJzjKlW9HZm34NCEx7KxoOXaGi1hVlMGgwss+o/BQETkc9BJ4XNxaCThbUg +BdvMh/aaMWF07cBMrHJLEj1nOeI33TjKmmSt0zSvUk7k1u+1zj0OoZNl9vDBK5gukb3P13kDXVQ DS8dd1VSoZLY8WPIxzTR/TEPoQjTQcmr3K3fg3GEWYNTPjMyv11osqECfNwAqdg+XlMQvjwesdFW WBwyJFt1c5fWEH4LIWQQKpXdo+ci1x/QsIixFScVICsphhLqmia0mR/zDIv1VtKJNRIBJV+M0vIM c/VghBZkMwntgGyq3lg9EysaOv2/UYoW77OiznDHNB4iODF0PolRbnDaUdx3i3UP3MAe4Bj/kvxs d6mbClcidRPcnJbUsPjzP30JqwEmOJVAzTHgo8bHADM2n+ZvV5SYyZvTnkmRrSN7jbY1pf0VEFwf 7/rUb1XC7W/dwZCQifVvVjmgNZX6l5mNHvQZFgSQ5W/mPYQQdcK57TWh+RblrlaW7Vjv9FXty9M6 +tbkT1E6jyyEFY2vra2dLVRkShEq70f14MKsinFCh+HDaL/cz1jWyYidt69ZuUpAjHPgR2V3uOJg 5WaaVqssETdfLok60Fro/KU3FFIaUBGA+BzwU5mjXX/MSkvmNakbzG4u+zpieKI3/aagug8sr+GV kvBSSmYuH4Gh3PeAo8rZxvABo+JmsjRwWHS1Hr5J+j3fO7UJFLcbWvok0H5gX4aFf+MOJfsrtomE 75V3Pt908j1XkUe5kznFkMHL/fhxKVkJAbDaDOkEpthdoofvUNnmxZO+Tk0v49nfZO5SJRXff2yz 3rEOM9/13GQUC+qjqkkO6RxzMsN5KEv/jaxuyNU3pdKoDxhidWNYRRxRKrsc0/XPyOzbgkUheN6F YJChK23Cuxbf8TVCX0YAJhcz6Hv9EkzJDh2fAXjZOT+CwCfKn7HtwOKsjCPv+CnP5tjwjmExCM9k JmG9y7TJL2p7xG+9C0XB6XX9Xhz+JRL2QSlNMc7PmuoXiZFXHbht41uI9024wUkcbwLg9KWWzyZX 9n8z1cU+i6bkd4mEIzPriYJLA0d/hwxFkpZYI05ClbeN5v8GMYhiKwb221mvAkenNgxsvpInzZtl 3FaSTEaiQoJ0YcHxL3cClUm71pE0AKOQQhkWB2glb+8nAfxcb7MYYC4n5tMbviRqjhCXXGLcDGeK ralBjbLrQNHu/VQYRDISVdwBmVAcCgbZlk1HA1Ljau280IlHs0T51R9Na+lAZt18l3ewhU2lHC2Y MkVGUkEo82rRD1igb82OiUzFNPEXnFHlLlZRDUfmswmu7ixrSDGu1Zuj9iWTTsTPqK4blQlBo/+s v+RCc1Fi6cIJKXbZdzPtKpVAYPGm7aJKpaYV7TQ4cKtXAkoonwck0kzfS7i3W53OTBjCrWgdCpSq jKMW4jDq1gdu7vwACpnSWOHuG0fe1LyyT7V6l/bdg17yWTsNxZ3IOLehuviLvB3DAYUSacoJamaS LFKlKD7ObNwXIPbLVcWvplpy76dMith/4aO4dokS6/hEjfUjEgHeXLNAgzvhjmIiKn1dC4v3H95W bWq4on1R+jjRtjaSsC4AiFlaWj9jmfMOlrYFmw71uaqXe18ZS/K1Z9p6VCiA0lyViVp8OxjTqsIq HsO8vmDxXJ20/ROXgXG3K18gMvbBhooPtnS13ijhKguNKrw8yryuhroyiZVJZIu7CuO7oyO75UmW DICJin1EZi7wxrZM88+eFyL4wyKi9st2HYJap60WzPM0MvhlaTUT9+6cThLLu1OQgM3TzO7CwXJ2 NzoHYLEdXbB0/oMmArPcOP78QQk1TCafcpUbmzEXcIWM7EoucqfMX8OB9C3piexkI8odlqkXNLPm r96IXLvc2k0TqE7DGZxMAbtgGYtbHtJsI1wrGn0lFpFe0sqcaCwMV3nfzoTBgQjqlr1apY1X2xFz Xfyxh/mBdAK68eLFgG5WC+mgUvBo0KlodQT/9wpVsN/MDyDZMHbT9YtpT4i2CgnIqGSVJNH1VKer c2feMAlV6K6owW04Qoml7XaaywjC9D5fYt6Z1fledV6B036hwLiOyxDqPW8vh4qPtBd3mic9bWlW 7wgrrVTSF2aHtILvojTtcxFIrQdRZQp2seCRWbG2BkrTv3/1bKZYnGQeaPoJ8cwmNqnnaVolla6b lUsQOEWia9hB2dZeuE8cuwBqhHcgVoVvvr6bYfCUvY8Q3No6t8prA5eH0SBMStRt5cEdzz/pOLdI 5R6hEOMw6JtbUfYBLPyrTmxSPjZTJPWdRQDzvIi3z0+Pyv5oIFxbSjvT9Vgz5+YJuJFTh0rVfg+l 5DDQsr0aEqpBoajvIUfxU734qOF+R2c3uBoWMNtJUdYn57ygEU3MeH/2MTutznAyClgNDWTWjybg 0tTvEeyV2mNZaQC+nGCAcMqPX4fmU9yuasTmHcuo/tLiXZxDE2heILAzPogw2fCaA8Mbcj7q7qQW Ut8KSZSNTPiLK6lxSnInN/WYWGikumoBf/w1bkSRgmjhvtLYnKwYnuBrtZLbQ3q3gMrK9Om3J3x5 FoORawc0pin4AzVIQQdWn0Wd0E87+lpqBzjh0tBv69gzK+jfpHDlXnlZFqrDh0zfFqm8nojOe9yY qiscPhyp8ezAlgS8tQFR7pTF/ysS5udL3GVEEWHCfc2ylNpo/vJodv04tWLe0iW7rRCDcbSUbx09 NMukphcqf38Th+uE8TjBENAj+DbwgXf1/M9lp4dh7+BnSB51fsvRIeoXaEtAAOYMaljNjUE+o8Qi 6GZHX8IeT0o30xHl8ST/hJ5c5z9g8Hm5n5GAlhXn7WXyNrtu4qREdeADPOIAQi9/aN5Fiol75Eam fYc7aVJwu0SeJdWr0bU4xhTmNKbDmakaUP9SIaeR0ehoitOTkizOLpeHdgoRg/64c9SLaQPsCe3I ajfoHR8NUe6wmEVSHVco2STg4EPYgqlGx8kXUquWilIgKhdY3MUgn7NNPOKR4IpnIVyy1cv61tqj x4Pp4Bz0SaBcEsOhuPJNJc2cVR2kQoHtrdhZbcEalbzknYH6DE8VOom2xW+2AY5Ub3vyQCbzbvJk plWdfFaFqQUjcaLHXEulCNE6D2FMhyV/8PmPPuXh7i+vDiDv6pUngNfrWXgP9SkTKhnK4KSyZt+e EBU1QO+nGhCUJcbzi60wYvswafRk5BTw1k/6fDffzT+o5Dbt2Fm0yxJshVrqMvwBBrebEpWeL3gf R1BqbOihhyZvklkwzLChYb6yL1CaB+4LAekiJhhZDRLNP6Ek6PZHoNOW0/sjC/A7pPreTPT97yw5 Ut9Y7FWKji3w4nLPRn+Byy+TuVpjwGZ+/PPWouMentg8vOtNtY8FgvaqzBYc6QclXCpzwlNKGnux V7tMV5qOrk4K2fdXApTFebb1GZhdGUMGwdSGMq9GyMRIvcNgNo8gzV4w91KRInuPS4Mvl+THKVZ3 SSotRtj+iKGjEodWYJlfA8Sxdgggncagc9jP1Kl6Tx03LBPwdOthrhgsv6ufLS2A4VjYzJ/kzJ/H 3Z6f7I54dGK9cziOyjLGya7EJYcOPzBzfQvEoBtRcoOU3gmIX7APf2IUaFWfC7+IPHxkKBDmwnKN QCt5LTIgj7DYUTg2c4hAh9qTQwh3XhlzYrhTaxY3zmJzJm27YtaTPwTw9ldCjutK5NaICodvM+0w pbIzS6ZzGkmQHHfq4sejqsx4uOgRfIhq8pnNm+hcGoQIJzQ8HQTnEOwNSF0SrKt9Fm8yDgvm9Qs3 dONOhdkJFKVcRgtKIf88Xc6eqXpRsgKgY3zZytgoiViuD7JK/cRh2wpSWVT76BCLWC2Qcj4XOag3 1Q+unlrh1HKJ6uhSUZrsuV6UO3s9qH2qr2T9fPPkFhsN/ey0ybR0QaOaBR4+7j/2YNM65CCnlo5t ZTKfkn+plwTZ1Ks8N2AGOQ+fp7aT0pXOaz8CsZycI7/trB8kbDD1adHIxskNDECBRYjJDKVaecD+ lZj4NmnpqTMimMS/ZcNtOsYNcx2nEu+EJDR3vFc3quPtdVzBmckq6yYC0O20ECe3YLGaKhLIXvMC X8BLzfskMNaJXNrM9FSV472T1deF8YyB57ZHHwDoTqKFzZPoVNluAk+DZtFGb5lpp1j9J3/8F/nt 6tlkF34T8zLeCIzi2aYAo4Gc7/RIPJxo0FWdPDmwiw73YWTbZjQxQaGs+WbgGT7ntAjf6w2at1/0 ZMsaL9gPS4ToF0st7+MnALnohj3drJ5eKw9GYq7RNt/f2ajsEWacBef/ms3UMzU9cQ9LOidiOTqe gJ6AsKAQLF4rubIuTVfNSepahE80jU2121xtAuw9WTUex+I3gQ1xYDNBNiIlVaFrrRnVO3Ie1viw SnJsnntvFxr1PqXLeSXLmDnfdpxD2kF4MOLTK7l4HSa0TQaJucPGBY1Yd63Tie7FYOzFIPkRdG1X O+olnYxE74o8+yRy+1GmmWGO5f54JREM1MuJUzUU4HLN926nSekVE62AbCS1TLu9El65PiPanD2O p7UDDjnd93dh0Olynh3OWdUP3jfc00NIZK6NQq/gwJCbmhmFSU/H2AEpXjlWBnNhFmS/TEFS7N/g 8A2LzSW9NclZ5UH+3IbjiukUBhdkm1yrVUz6sl6vW2MBs/IKMXLFyWx6ko/oyBipHDHNgqFkw59A sG5zX0qzzaCmFJssU2WyCdgVhmHo+7lDnNUO4EyuiV5iJL5fjcpRdmuNsYKJ2Zles7wk9CoDsonC tHcOeHe8JxgoS3H0jVjB5tIkvtv2SuNhNiD+wbdYX75C8iTFqLqZwks0DYp4ZDeQkLiNWy5am7G2 jG4bvtJxFuiq4l0xnugPkEp51PlkIAwKcT3Fb8jOLG3x1N4e8laXimPKGwvAhyH32BGSADBwl4eH zSuSMkcm0vx8MZxYgx1AAA74iaHcDdh7sqUpy6wbo/zI6+I/0n3a97U0XB8LuPXlbPSZyoPlzCJE 40/rS89rSHtRKIta/QyiIHEE4tqOa1v9sm5Y7CnFEvkOxcYWbstILv9nRjV9zujaMsUBJASlKI8M bNkSMQwL2MjEOjtr/H3g378+wTkhwCTBsOJFjbLJ+qByEuVhpaNKpSjPpmnH+94xJHFyqPRs1kWs 4MxBKvTv8kQ3Eir82t2r5dyX0zknU6ZL305y0oZ2yVfhK3yN2xsKjPS+itoPgCFNkqkhLbfG4PE3 TC+5unStJdO0/yiL56FcnuerhOTr5zYS6F2hB1SLUNlMQsl1VMR+UlqTXQr02bobT6PlbKtlOMg/ R9DOROOQpkjjkVMPNdUFJU7s5xhoe39uJ+W885D1/6N91sgg9P4NH5UKJb5UKYGNT5ACYJ+WeN4m hUWxU3c3OCsZp2CqiWrLMKtgPmCEzCHzUHACnEmc/mA17yGzUAtHXS/0lZmc5lonuDuQHTsnZXhm MD8243MFed664GMIhCQ/clcsBwnaXCapV8IhoKfPNhIorialVLv+boBc5WVcs/WGk1iCajozJORx 7lA+dG4AltS9k2Ge9WD2iGGixCXOPC8VDMSa0o8r0is8qGCKoZtD+Oujp+ZC4XGkS7hhjTqsIlAv ++LH0nWmsMkNSzxzbxMAmNX3B4SfQnlrugHtdb2vj5CLNwhkCqx4mP0HD5Iut4mAKvPRxP8nwOKM UzLu5MRGpEwZMGFeGrsJrzv8n23Ja+gAuqF9g14BPNxSJKJIsKdwkBJoVAcio/pvYeeVzgV/4kon 10tCymIlvNLfX+LzBaqe4yoINSL7N/mvRUnkPFhvLyEk30BZfNvWyuzF/7dU1RrGXRERMg1m3BDK 23XKt7pL/fyrKY97g2OPmnzVSLtaLomgLHAGKRlp+ZlggW5NniK7DtyZDcHNvZxHeSqlvpo5qgZM EgcqTZKphDPI5NhtFCqD8GjJKd+WPgkPQJtaHe5HhbgrbH8vEzju4Vbt3fzCv2S9e3eNPHXYaEg4 15LeGAkCtEVosWO/1dozVGOORUc0U1WkMy+B1Vr28ivrprjLJ7dkUmIKH9eVSLHOiyyoE0vvTwM/ D+WHswrw1tMnL5YJ90qsyLzMmpRzc0upQDDgAAV0JIdOiH86ANnxIKvsqJCfY3lL4P/fsaxu5fge sR5uDYpR3FT+3N+8zv021EdUIsbz3oiHdGE/hTkg72jHqi5xNLVv59IK71a9VDSxqH8NsO699C6R iPC4aSXayg10r5K627IwAHs0LVglCF1Iw4mH2WqTKlfnnAh2r65AQe5IHOAuLG8mQCDEUbwArEoI HeeNTtB20aVmsPVdZBPD4uGFj2N2qkchCkcgGeZMPXyaHyrOpkexBeU0OfbQ2Ww5w9cHmkLPw1hl cJFbh9mk9gClfpZOrD04iXNViVkXzoa+vqAmpTJ4nz0HxdSjW+6px5B3MMUG7hQs7+pIBGyTVofZ /PVfJuSNdbuZdPZR3IU02eeastc764i+lT482wQ/WADKpjax0F3yn+i7BIYG80p4nvbqEcJ22NHX tGA4rC/TPv8gWFULr++TGX3eNNjovlGAYD3qtn5SEwKQjfzMAiB6mwHaCO8OG0WwfiZOitP9kBY/ 7sS9VKi1oDefj2r4+TZDsrMS8/+R8hKU7L/Bh/ZmtwPik7nPDe5c1pftGVaj/PVY3/vC/uX+QaJf XRx0R+TQ3zeChjDIm0vwuIy6BUPl08JaOCOSoD0DC3f65KRQgIK21iiSKVqt8ERiPQWL651s48oC Qxz6RphQFU7aaGLZ54LZxcWpEhCutR5mTpaeN7anbdI0k4URgw0esgrhzfdmxcGNPODKT+/Nq9ux QHQE0E6+nNoAHi27JUZednXllXRoXRXORFUS9v7BAw0OBP/wgsuwRrdmYAhGYMhx/Wckiudiamae vADcBib0JxaNUGnxqYIX0cpRTyJxuNoCOEek79VNBttYwxkvBFL1+rD3sMHTWjbcR6zkZfgFiOHj KoWikxX+99t5mwHZ3NVB592rOgllSdU0NzrgKhpYgvjBmY7wJaKUBATd7qpL2cgrqMwt+cOqetU5 n8/dxiABLZxPxEeZdjinU4cHKBswkkkhpHgslYC7UpGtThyU60rf2mdvx50nWKfL0RO9qoKJeH8L WhKnhUyZ0H+ywXD64rGDt8yDdFMLzvnax9h/lJd61uQYLMdOCMAvmUY6A2bLChe+DOsnU526VfDj QXDzsY9HFT4ssiuvVy/9KfOrwqYAFnUOSrQS2xppt6dhsIoVAxjOl4YsjnPaxMVEVyMHZyaG5kPf TyCWmZAg5dX41gxeQ8T8XJvPVHgGm44Q49+ZAuvS8uFlyFpXNUgKNRRIUyxC5jaM7t6+nz9J3jPW Ji+CVHc+hMnZHGe0JNIxuHF6RRr07YAJ4gmGrdtKJoRwxWkE4xEnQqotiAwC8+aEFJZHTJk+oWCP sMohJd3cl93x6hmcjtv2b0wcCyKYYnnE1HjPbP8gXFxPn6zeFL4rpsSAjCdvmPgzBDxFo1pB0HBR EnHOBQAwXTdhXrRuy/s9xyfAnFTK2oV5330UzqiMYinSRGYs5o+gIk+B8ZASk52Aq2IehCaD/b2e uKX0/AHiyCwZyYng/b4NIPE62yWcQruNl2oQUKglwveZH3k/tCQZW9ekoXF0sLHPVLsisidkbB6M pFVmkc/x0RZlwf6enpxuJtVZy6Ud9oji/GkBg1JutRsfFG131cT1L6bk9aaFBihw9RJOoGQcyM4y CPWSrnbF7zwTEXjoax0fgspMr4JvunDuu+CRm5cU48t1lyLl+v+uEWOU++NdPjxxML6YMriGpefm NKt01j1ekgJcLxdCtH3Gyc2m5B6Jq9X6Qn9saon8jXEVwQ17425oITHQ3rY/gpUC/MjwetmF090Y yBdwDuzB/CgZqfgajquEmLrafICyyxv4c2IPht2gzj8jB8k7FGQfKsbROKTZ+AhSVrLvMSZaXjSK whEkLTIphoUUtho9Sg+XzGe6ZeDe06aRBwTd/gDodntK8O63taufoD71nmZYPIGfmZ4MnAfjVwkP wvgkAJVyhOHZD+iZpPHHoQXi58viQ8YMrLq9DUVUPpnqGO+eD5iZFIYAuFC3b8IySlD6jlLeTSuX Un3dObXeIOsNAohnX4SzvTzuID5U2a8U0WQgZsF7I1eQFW8jQ2GHtgdiqeOZvo4KTR6K7/cJq1Sx aKpdqlAQNWAjzfFy18O2TPL94puULAszOVHU88IBkqN97nk+pdGddgp7aWDomchT3zFxVJWtSoGz UcOYVEXKluLUek2RH2KS0hFpHxCs0Pypcq2OXus74VEZpE23qNTpfoMfK2yhK+6hluniXgkYfls8 edE4X3lOrnDJf+ewrRMebvLGYcxwSfep8il6NzeO93DHH0Orr0mOwiVLs1ajXZvjmEBlLmIhlrLE orAYN03QC2nAa5uyXV4In0kTXxrz6y2ymU/okkMMOLLp/p5rXcVPWJaSjMdW3reZujP3/7u7mqZS iw9jAx6heCFgI50fNKDZT5FA1cb+pWCCRMpuxJ7KL3H3t+33ph+NBiLJMM/xAyF/YJgl90mFHmVS F2ySS7WKTxwKnCgQsd0BGfIWckd2tSqsIJrvRxY1HB0DtCiImC5I3YYRQoxMMXQFC2sFfIelOY8d DMM6P7Obs76wTZ3MycG005D1sAo2huDeoHywdIWd8uMek/TPUcCbSw+ZBQhvjhNZC2KWk/U8fREb fqfh83kBtbKfC7X2+pUmzjU77QjYyM4TXE76I7DIm7qWQ+cUpK9OyyZ77GJbA1a7cQrU/YJBNRMe aAP9Osgel1k3TJ6tJTzoR9UF2ylMH2NraeBsC2xda0jx1H1erNUGQyp76bnuTMiSfG7RFHs6667C XNqVyxG4TxlAoihMko0o3R/qpuS6w47gijGN8m4HabHnlwDK6ysSM2fwZmRD5NbpZIy7qsMN2gqE L6HkdLI+/JpQqLsxumsshhqL5rEaZ9SqI2Pxb9EYYWn/Mvhs/+EvdDL0CEQEsJMcK2NYyaHq3YuK Vnebrq2SJpSjVhfnsVyc9Izy9kMNKKyoNJNV4sQ7+vRRvcwPN+G17GYhbr/ISeqsvCadbITNDcIv aDL8vZoDI6woO3bQ4l9bPw76mjLrHJbjBjnX3OL5zCLcVEtFVH1c+MVZnqrVzLMVzG2c6XIIDMJ0 h2uwUOJvyBfVf4+IPsCaBp6zPz8gf7Fdle1/l52Qr56EdPdmEXe3Gg05HMSGSAkpnjjw+Z2+Dent e5qFVdMdLE8uSRc8JxZqUjbRBXpUxRBbskvIRe661HqqPufk1OZ4kb76pQwYUXJASgsCEe3aOVlm 9N9ICaL5jUOJedzSEoJmGTOcOZBckB+C22jt9W57bLbGO1RffVQJdMbhVgxCBklKmzAZ5Jdw1TbJ 80FxWhk3cPmaeMKxjSbOMH59FTbGgJw3Q4foE//W4LjV4kLmrUj6eQu9dcFde/aBgJFEMuuLvidi +2sdG6x+NT7rBHggz9Vw5S0xEF8aQL39PoupTaypkCJGkouDxAGnaHgUzohTqa6c5rnM4BwHCZ1O +75hgxyjOhwK26+D6XJHV5SMGBBkhSFLD02vumnzekjXL+0961TcEQRuUftjbbPwRufzGwfGFINe aOX2jjqXEep1pENciMWfiwijNn0SOdURwB3w+717xdzm/lI7hvnJfMZW3/U/RKR6mtoXDV+ijoyx qoH0NPCmhgW/EyWSKmSgvIQXG0sQ5VLypZLrRIBLU4c6aX75H86z64ovVTocoxnxhkw9EZNdkkw0 9RSXKg8KIwwC8HQBo3Jlv83LCxGSsRuw6MmHCTfJSpnTWCLJfRlLCi6GH6lt4/a1/TBfDLlLW7UN AhVzcMRCalDOScyHF+rQR13wrkJe0bjwGL8NLWx0Yit0ES/sN0fco7YJu6KjHFM0ViKvQUAuGeKx +EfgTGMkZJnzRV4B0WSDO2lmSfYkdl17EI/OxtXUyTpsu9TBR4XDyoCZJUaleWNaylpoMtIikfyp VCq+jANnG0Rzec6Mpk8c8Un1lSXBQPwJnZSEGPxnRG0dW/l3z24YxeYUIhzL0MvIVl+KltdQiB9V kbjZt1xoA7k0jy6GbN4+Izt79u3AcfGhnhJiaaNaiaQC50FkPT3uKDf5iRFZBxKEAWuoEL3Sl6fT I9yKXyYiD0w/kdZeqT+8Nmtix293rSnprterokk8DvrBzv3hWv89kved68N0iwvGLIp8rUtmCfJm fdHX4KMiXtHCNfOCTyF01K+JyGN+STeLLgr/AJpj7TociRxSXFqEY4z4Du2agOeT0LUUtuMSwlCg CimQlk8BCzIB3IRtc+YO6OpfnMNlBX8zGYhDA2qkrp0UsAIMafLWffTrRc1soPX+AJglxrXMjJVd c4ihyRZmp/aTOV4o0WET0MtXM2jh9f3Kfwsw9jwFtlptX9popMj8YMwOqammy4k78GdzGZFDNiO4 acSIflOA9t3CxLXmoKhHuVZ3c0g7tG9UjtNmB3LtFgfj1GEK9C3FCBCWhIxwsQIsWDgy7wR04qoM SKb2GYNsMmokkXRQP9+7YZaHp+0XrFlKyfcKJ4q3uW4HV9xL7Abl4glTNKM6csQpLkv03VqFZVQD QckLCzY31fNh//Vb7KftZPunp+Mpg60LUla+e+LIV/xf+VR0Ff6Dhu7YD/WO541ApBUK1s14XnaH BCkAKOSyCx6IQFnRzn2FjJEStpvloVpqWWJuGOrelvSsctoh9tWkJq3KQv43Mmv+lz/nQ1dtiFia Ak4eS/iBeHstcgUJfS9v3fKTl2dkSml6Kx8o2bUhoSFTU7h9r5HUoUIUBURGBJdbe+V/5aHUaaoC Q5A9sJBcGZu0swsS4zyWFPC6NEEPsAGlEBtIwpgieIslBQ6uU1ywSGB5A8wgrht9vt0zUf9nqwkj C1eatsez3G3h2tSMfoyj8799E3MjvSAPxsA/hzWtKF3505zN7Fxr1cmDpYgf+pOSSACBrvjFFQkC KXA8tlKC2Wu0cS7cCNknMUqs45l4Zg35F7nKNPcCchKCLE2kzxvEuU3976wVlTIttPV4+EcRjSil glcN+yqCeHO1CD4QaDWMAOIbkWretVW2Ul/iq6XDEkSuUuEAIwrYpCkcqURgO/X2nYVwd69tPTsn yXmkq4aKhhs1PfXw7g/BO0wCCe/uHbt7sLSQuc8/eJ/hhOekQbPB0xofiU24v8QqfbhuqjC3K3F5 hd5/n/ky8zk94NWNDzODnKtSF7Khy/lkLvQFE2tSesou4lTaLxp3PgKpPb7X+INZuI++P4ygNNO1 z43PhcdJJaVFDByXCu6YZXzKPclePEBhP+uP6R+IDO/iB6kY6TAm2BSTAw06xWEtmfhAtUO7G4Au cJIBPD0AeJ+MzxAup+RxcydOt88nfkBOVARCugQt9dSYKuVIZMCO2RiY0PXv9Fk5HsrCAmY0ZoPb CjLb1yiprP5+4t7dTgP75rhPPMd0OL+/8XmaJbGWI8p533imkQaRnDlTBI/34Gb4kAeIzsE3MfMX taPXdyr+oAMBOzCuVE5+UX+PsnjfVuy00Aejr0Jn01Lv0+PfNNltC9itVB+dYVPCFnqLp8xKnugO JXGMDAkwCAC1MbgaSQ7wvL0/88JXRdgy0+mGS/LbJquaIFIhPqO8/64yFx9NcLwxwnX5vSGGce6I xRba6k+SwQh0CFWBYx6YuUouPrwSMOAhPzK5P9SB3WM7d4LWPXsV11BMFKTyFIiBPJKWB7HaMqh5 EKaR/TNsz3AMGLX0t3ipCt2txRxWnGGlaMKwIWWk5hunJnxNpjBCCrkCwnKzuGy4BcfewKTbvCOS eOe6Jvw43Ds+2haAGePMinAt3X2rWFkDYI6WOQ43ntRfIbSeMXXWVVX/cXXW/TQOV2IWHOMexZgN Oy9jf6Xus8JF+bOOgD1qnPhD1YOp0rdMtnpY7rvP47uBkLzYSUiXb9KYlvm9jEZHOUgMsLsyrDn/ pZXehSAWGPewAhqxQ8Sd9cEhfZCmvylLc4crbDQXa2P9FclcCsvpEjaAcCoh8Rh0HhHUBKKLaDhL WHFGFVvbxBCq2sUjJYOX7S6OG7OkmsUPt8fzfNFS7DEzhMkTTklW4RnR5EccFakKdgp4C1+UPtkp rysaIcOVaNg33rxfysNHC+OByJCdfDmCzoPMmRuoh/wvHU1MJJJ7/1bSK7z41cfbG7HcClas/pEF KRlU9aCyt5JkcYU6sor5Vu6I3d6zRQE3dmQHnuiSys5ysbnQomnrekdvpMgQZU0lc0dVtqRfdu3P zE1VCpLmhYyatdz0h0UxCHjF6FjZYbTNCRWtIM/o4wMreU46OaD6HjizI7YYYzasx9w8zctdR8Ee 2pvYozDzwRKpfONtKbYpPp3MJji8rIR3cRDcSsMLpsPTKvlQTi9Kw7dwMFT6ScC4QblbFMr/XIp9 tCmN/7HJhjg5nRdX0evXISxfb3UezgVB7UCtd10X4USmwDZyej2Zwu/XQNV3KvbobeV6f7dk12p4 bmcJQQPi6NxaCJo7vFsTZ1omM2Y/T842JIh+Maw7H3v8vg8fYV/LJUwPvIMtwD7Mo6eKC05qVE/J 8NGesoyF7kc+0QdTrGJNzpa3rrTEWQu0xcbb6gwzclUqtNFmtA1vPsOWGohjwARJg42TMPX0OLFN PlIqKxmLI7WBDXSiifQac2utwZKa89s3TU6ALf04o+5VBHwwhL4ibqvF/3SGBV+j2ZDcaVNt8n5e UMX4FedHfh2LmFw5ro3avGU9jRGKOaimppMx5CNbIPdqd80lEcJvdFBRDvBi62TYcNehziSKP4uF swrBa8flp3cKDzFu9Kv7EyToPPv+YCfSM4U780S697VQ4FTx5jLHGsxCKn6scZ73gNwqxGgEN78U 26KVbGT4h427lnLUXN1XGu7rl9EdvoKF6Rb1a81CLeTpjfGEzlTLmBLumWx/8jPeR890EcfyCrBN UXIsJEdw9+Rh47hGzGTWQF8UEVIS7BQ2TQzCPMIfgC58BQ7V/u4Fv6yGA7bX3Z90nS2wKYwEjdrY 0ValpsKC/9BihAEcvDw3kNzVo74O9cXrWdNucexO0BYCblOINhMQqfHCa6nWZcMxuWO0R0VVkGEp VCEWLhWYJwKp2A6V4D7qM9rsswC9bkx8koGNr80vSMElxyyWFCjjBK6y70Nkb3PuCbhJwfVCLYK/ Li6gcMLYTf6y0PfIdJL05XHEAdNOplD7FaAv9GoT3HazeFdpBMCeJx1OQoJOSJbKttbsv/CkKPop UlpAyqEFrAoUTff8Pt2mx3JWRcajh/yUiPz0KenDn6ZeZs4xMSJugeac43qX/m6u9RZ6w6oeBLwr oXc1iClGd+3P1WVUPmkr4mmEodJtayc852BXGI0R9tcIEeb0q6jsGsn5y2g86GqTC5p4dvvbnhOa WvyMaq7Mo/0Z0oOcNsJt6A5owhYnAFoKWGQH5utsS64RebYDJnPdRBjQl34NcpSJC3YTcIP0IBlh cSHnTTUjiUmpk1Kb1AyPV6gsh62es7NwJxW2xedLuvfs5BGVqrpvhwQ/3qYv29D9zvMbEQRPk75x f5RNaQoGGAEY3GVCWwORWKozb18x5IyI5kWTQZp35JAIHGWMkUSnUUNAsB/UtRsWfy6/kSA5VoW9 bz4SE9ysxi+jc86lz84yU+Gt0uL0FSLVV4BaOGOyS1vLIlImtJHFXnaIAkre312kYki2awYZNCMa O7jsrp5eKNdRwlhuvGzrmn8o0ibppRXqXyJ9wpxAarKhWx4CbJrAAde14xvvlk5S1lI403K+glhx 5gyeNTuE/zedaOekbClJmuCb1BbkuDMHSFrDj8/6kaM67Zxnld8NS+RDdBvrhxqD8MFBizampZe6 86rNvhmHlPUMNbq0E4Hqr/3TQNjjY7+dRsrtTwzDjaHvjHPZyo53tVxnUqtAL4XuCZ5zN0aG4mQH 9brsEwDMUCBlOSTt5NGowseB93gC063tvKJm6f+dZyZ8KdbeczrWhQOKd0qeaKzcXJFE6Pio7Gao QMVJ5PYYXKCxSzELSV6Yfw1D64nr8MlqoaySLfXqB4pbeqk/jPE+bLPCsTGvcE/UA5RsZ1X2+SNa M6ba2xkt7MnGdn1c1J35nF3DUSp7g8QOjXGnZS5FqnX178tocs98lGJVJlN9ZUVYqylqm06dkgCA OghuC5vaTeWc9mKKQ3KY4U0bNEUAOD4RO4qOOEmnAbtCNjnjNux3khpS9OlQPQZPIGkY0s1Obd0n x0x5ymF3NJZOhutxiznyjYB+DwaQb7sExQUeamra/eXLjo9id2DkWc/x/YAqAlOxzCOdQ3hz4GNd 6P0b4ytPfXHpNvOhTAthKdi6f2QAm1q5I3Vj5fdSEGgsv5/RTiD/8xnxR+veX+IX1WDwBhKcVzpE YKPAaOvfhDul7t6pw81rCE8W59Pv3zVSXkVZnNYfOXROUBmmqpVb3WS1jxgnJSjxZkzlbDIxkG3B HrmQAFsGRIaaCyFNLAj/Tyoxix33eNk993inYagKzMnvbCKQRcCnjC+BmP8SnRbjyaygBV1anLW7 +zh3SHPmTvft1u8RTB17z+mCsIN+r7ZihT3wlEO/MoDfS/MqAeAk2qCsnOZ6HyUxz34W20uDRbGM mDRTuPqdDBEfXzcJAhFujZXtKdcV04kQga/sSqjqewsiAS+vckqjHqUOF/MgmuG96tT3OxLNXLV7 LhUS4+NZWsKbBiMdWc8OmiToPgMKlbY3bjUawARXMI0l2mAcAiorIvh69SBeN+ryOMq/N2cs7t+h CQsspEJ3Jv72/FY9mNinj6R/ormTmIvY1fpHFrYsWQO6Wxh6kEMNgE5Z2PgEAM9N5vxCEjgWRYrm NRnxZNKg1x7LB4clETjoMn4l7FeIQ9gcuUzh7F+pa+4Uw/e0zxuiw5H4hlOGnGm9MTCuaJOHh+PV IDObKFFWBe3JBd7WULEmLfHhhOgp4bPbkLmIZkNTfPUyB/StgutCotRT8mnNN45dKpZM24VvL3Gg nqyh+/yXOh+NMnw0TeqwLbmawaVjHU15rbJwAcLjBLA0yMvdcYlEIpsbqXwM4Uw1v8zKTaG/oyMM RYnC+hUxY29/TzY9HFJKY1PKB7F9A3pVRjIBba4d8Ca2KsbnKVZqy/HMYbqFtVws1uRVfB+6Mwi2 y84UZRltgaHIXU17dA+gaW18KBVHgx3k4LsLQu9nFz11Ak5dkdaEbWYZ8XqhjbHQIpWtLmp29yAd +g5Ez2oq4PUoy4M+9SHgAWYFu1HeZoj+3Or3FlNUFC63+FtTppcW2TL64uyNYehfBOTA6EMfWtjo o7CsBOv1kZguCm0UcvHs7eMtDb7ppyrYU2osSxE5+Yf8NArPBuhGk6nRD9lrcuwHCpOGl+1E+d87 XkForkIqDT1MphRc/FP1yLO+uDLpZRsVNvKNYJrnVmzO7FjVcNwxYOPUXt3DrWt0yslLoXUwjqH7 j+0o338J5SShaRn0MhWoj3kXwNTe2Ml7TTDbhKRyUomck+LX/0psqYhK1CAdPx79QNZxu9o8lhWj wL2xTNUjkj15pPgdpo5L0aibL7ne7D4RsoZfQXnqud7d/fh+ipncWKl7CuzSjOzt3FzcH8XZ7+ek kc4HCeZt7/h2RDSaYrqFCDNs/DiSS5LWmLbIZGvE33C4nE3DMFpksbp3ta6TTH2qmPoeMPu8SxDi PVG9bYEe1u3aBV4wzAvH7y5MjFpjIRfRRJVaTqWnK+jmEUVoZQWSMRXSvLHiAmaDAO1j4MQ02TLu Y2YbHyvzijizKVQLzRDXN3MNLGBH50+GyJyU+btH93OMRMeFLv0JPQ/kDVaeU/+kD1IolPJQFy+X AjOrge+nvVJvvWqMIOb8wT/el+6QQ7ERzpswB5dOctESdEERFTwl/DtJ0Lh+S1WGZY2roJ2f9bcF 9qUS19GMxNu6PmlKHpLKeu8dWJNxYTx8i5/9JNH/YeF8fbSjg+iPts5bCs7ZAYGtSX7lBxc0yTZY X5I5D2JO2AHErrUO30RJ7e32B9UKm01t4RBvRkMYJQkVLGjoozSoKtnACC1D27KxgoOnyGo15Amj uHBKyRnGb6ZAKZLZmnNv80yR/binSsc5+O8MUWL2MXmk2MnOBLFcLhcT5hq20WSZIDr/0arKHp+9 5zYIGCYZpQHwbaqbaQ/qg4CsgH5gH7+Y0ziEOfQ+8YTkFCWdYrtJsi5cP5010B1/0RZb3JPVC1rJ NaytL+Nx5wE6HuszU9OhS4lMQAO2P8McIpdsXWMQT9qEbcao4rgJAEUb79ZN/o0nuIasD0uQoXqm Jhsol7fxQUugHs3VOzhLmnIYdGljs6wwbCw1AiQtUAjZa8NGOp+IiCHaD9VbfSPl9xDkYx4vdJf8 oIhkd2/2WjEVRWU1qsVdtEpwa+zp+D8NaXiB5iJhAgvXEfdemv1d/igigKgyphGZcMlsyOgDrqIU wcJ9uFNtooYjDaMljuGuQCuLpGjb2ightuk+Qv8QV6ufs1SDJR2UNRdzqDyjGwL62FpK9fCNi/bA vw3JXQMMbg7EIv2MGBhyqlW8EBDUEYkG6p1JB9+ZjaemjSVID0IyJ26vkdSjffEUFkn3qWcemTfh cgHk6DUFQmiFkomG4ozWIqxK1GZIss/F7UQaYuJGXlNpNrCbJdPmHy2VisZsnIGDWwn9go9xkl+o AeJqPWFvbBBKcjTW5ZZfiVSJkzBZIc4GrCOJ+KdjP+0FneQop1Z/NJRpZw0SoMLEd92Ss9hhs/bs IYx/iVqaWEsLtcBnYlqBTHu0p22cPp6DcNL8zqmFNegXoh5zhVXVkr5atnKABU+IMriXCP6l4qfO xINykOD/H6oT1e8MEV5dzSn/iN/Ux05xX0DI4eNBpiqIyFFDJLWyGy1HdFzrSxmZiZIRxy7Ry21A RUD+YmXyZPOqfy6e2e2BqBve28frMLaNDeEw3VHDhMsl0au5qdR2mVk38Tj6aNil1Izlbd0HPVw+ UksrwLgNBOc5L+bzl/M9HwLOLBIPIDvGdRBTJFS69XioAFRelfKb1GXSa3o6aZ0hejfigUJ1+Ggd WFGsz1Gq0qrY/Mv7w8+/JbwLRVudGRSYkt592wm2qq5zDFFRhXZczrcqYpsnkuIvHEWU4Wjjopwo 0o/jxo9oyM0kipaIgdsCqLI17T8JlAfJK3C67vBLw0Cka1lIon2ndlsLTvhvuUwkRfo0iLPiC1ao RL+sieu2+DEgdlkwdW1Z0lKbBGg0K5QKy7np9l5s3VmlexU5ZDj/Y2O/A7HfqP4Cp3WkokOjSTsn ozRhdOdqIHW3xA6MQqGyBAeqsPEjyu4H1pLwNLVucAGUexbTc/Z+wnrkTMDL5b+QqgQhjj/CrW0e azUd+gtbrFH1q6h6MzKxSU0ynaPJfWLNGShz/h1zu+GRtj2Ty1OPeyY2mea1Xj9i5opy/9Kk/RYd /AgH7yH+cyNJOJvGBnsQ2+64K8z3q9JoW3CxZhRFUBxMVsd8jVnhPap3ZLL9weu03E6YryX9vrlB p7nIetGXoQOxBEr/nn33WRc9jQ/jnKMsK1wPnXrXXFk3dUTiiPdIFFt9LPO4s/w7LWpwzxubNWYX TRYcAZHLK8C1Ho8BMFUdPHXOXoKtmY/nnPKt8pHJcHO7WBb4MIPL6j6CZFuSiieOuK/9ZYZ54Pec xMmRWJNCsLICImadEOpU8X60EqqTeoQSE9Y6JcgdLl5c9FaAAoDyz9S+atK5lxeNbVZU2qMl+7sj XklnA2vYZKyYfdI7vWGoDzY5stVOxOPMaKJUTEa9qsJqPUJjr31GfuodK6Nsy9Oazfy2WwVqgib3 QOzy+dmoRt6/wu+i9X4ZArccPkUJkaEYBxHH5dduEd0tD/mjMU+Nhq7V5WcY2j0Y0Mz6simPqCQ1 uXLCXnI0s7UCUUymWvIQPSOtR8CRi2UQ8EHU8UXBA82RnY+NFqWutEXBZThBnvEbKPKNya/quAzN 2VYe4ekHWXqen72M4eY4Nzn3uzK3EYk9jJO036J3GHMHEPjy/424D0npyy7xHunNXFFJ+x0UmBSP QKR1k29YQI9i3YVDHSyDHZBFdjWIQK/unsjVF31gAkNW77hSJ2kVm/ownxZjv9Cz28WzN1SRJlVj qLT12PFsyR3ZGbF/OC8egx+jxI1rYYkNRwWFkgBv6bLobftwmNolXHSrM/K0gkOqmcaqhY2NuDDu KXZNue2oc4b77NeAC19M9L4kYPX1P1fOOCBiyJvgoN+BweWdcOpVixANYrEBE/coO75cZQ1X6lnv eE5GHgxE2rlxiThkDOZx0fMXWNM4xecuhuQ/pFRHH9MojD3NKZBD/4evxbA7yjSvxDEHOhtUMQ9A mAxkKyj3DH0oqmAm1FGDki9lHJsxnoN0suib0idfXZ2zf0d0FM9r21yJEM37NpkjaGIQoi7+WVW1 80Ovkt7q3RWhLa8DC3SPHVb2q2uaqSNauUkt9dttdzDH9XnsI2mnzkkkWO/+acCxg9BgWp/nO74R yKyE9sZJX4Ey48UkiWMD6EaDGKOpt/NXIANq7kMSqxOr3V+gjyd4kVEcsg3D78wD0fHffzQnCE0r 3pbUEFfj+DCgD4PX+Na2e1rIcP8F/nuAZeTWqyF2Ik86TvV+KUok2LdSANeoX8HFFB1TStzpsb7L Gutjiw+y6Gtk98dsDRPhsWOqftMoKXcGmX2W6S/edkQCWSfQ3i3MvwrJo1tbjOPETjP2i8QEzFBU ixnyJ4eScq7ahaki8URwaBjMMMZNUipzyD5+Bh538ljk2JoYH86RB/zWomKscLutZkaakfA9TnOU I8/lQ/F46PNpnW2oXIUt7HmlGM6DA8rDDqaHwFV3C2euLQAmU2ow1MfhwcqH9dMnWeuNURtetYHo A7GHaWJ80484zftZPtPkWW/f7TYl2H3BtPy1FV0z1NJjR8hw3hHb2/u3DzaAwSus83iv/RTfdY/u 8JdlPbGNfQ7NIOwooX4CmnydI5L2EfrSqRtOP9Xoh6wtyFIs7DwjMAk/5uStGQgQoJ58gpmxCBcd 7DQ2ifNTFEzuCiDXCmEF6u1AVPHDKBqhTDB3qKaNv+iXsrOZl/LPCZQlvPy61k8ZqBtTuxuHU6EU l/TzDz5v1OlIZtDHDuaybSffLfcx0XSlxE1DMaNy7epTRh8Qk3r7wQE7WAGLoIA0Ylkdso0rpMId 7OEY7axt36ImGEozcYuLaImlQfCtLT38/95F7BEzWcdabPue9qWBnFtsdAG+m/F/LMsK4PWszb/g wxsMODIxbxFySQA4nCxT3kwA5yAVRV+sbXNvX58qmORfGxl3P0WTGtuCcW3Itbo5rv8aHA5WoTwQ 6lgqaEPKH6KY0GiTw4UB/8ccpbRfgYyGUUYnGkRKWUG9iSmMZhgwf/wGl8x/dIMi5vpsyw2JwZux KIvO1yaR2v8kXHa/AMoJ/naKGBwXh1kwO8pUqPegP82Li8MlJ16T4o1WjuZnNVdveHE8Yv7NvkpC 1alYHfdsdQUsSbYhY8fApGNfvpg7xHWVw/8AxnORDD57BMepPd6nElIeGTa0WljH2scKgkcIDGHl 23ALnlKw5TdBfHplQuJOch5DkZcRQFOgx2K+rTVUbKh5CNi9CPgep09digSBB50bfyaFmQmGzLG8 XirbWarxPOz85fLxrwhwgQqzg0m6Br72I9Gf2ST+7qeprCheeSAjGuhGWIWDqwyVZafTlXN57RYr jc7V6jzI8/8y5wqO99depsyzcVK8t9zWZAeHsF7ZoihaWw5/WIyJ/UYfHgZYZ8HrGyuqRkC7U1Zb 2GDfzVjc9iEkPFHn2DPe+F0vZ9Tr/AqxBUJMmZFNtZ1zXllHZWvzxYnEfYWackE5CjwxCdzG9lFK bAOg98strHi9yroo43Nb05e9X8FYfQmn9wFx+/Gn6w/Coa6h4b4i2cGtSbeHL76kZPSpwDduF3gl UsQkixW5ttkebGvXNcTmxnHbMQHtqqMGi3tGEv1bvHKBbWVWs90WHeLpaCQy/eMqL8Bv8ABs19oj wSMoXXvx8khQ2/jhXUhf3JgsVWUbFYA1mMY9c2UDUB2//tKn7KssoI+5OHBN43r7O7j0Z16bNE5o jCrfoOjl7ud/2JcM+p7PNHyNGy9k8ZlyE31vHaRAaQHvVqvd6R01FhHBZet8ATaVPnVgSnyRaA1l 2jGgmxR42fXWuqAz2n8I1/+kIFQR0u4cuEHx1/+K0YhXgnh/ha8eEU3rpYGIo/HvV4otOZ2Le6Yl H2LAf0F56gel56jIYSHysr8vPK4/CoX8bR9+HfTDN24sWRbcU6aq3IoPh4BOEErwqb19dW2DLw5F M0VICtW+o7lZG2dknJCjWSXZzuNZWsHl2fefnUeVB7MXV9qxlglCEeig5cPunkVU39hme3N94HXK CEftN8sr+SS6gHZM61WQhU/wniPWZykSjBfG8oLS7+bzGcjx3aICJwIUWHYxddVRu15V8Lco8NhF C7iOM3fCQ94pHHI3nGEnt5uEVxSOmC888yNialsglB5covJ6cyRQxsDCsrwSqBd+2JIoGYSxeEzK LhrqBvlYmo/Q5xRPaSlx8XA2s+eUNagPmou0Q2h2cj4okfGBua0gbTAV/IuQZaIqtRa/xQeUoVRm XLUzMEX9En+Lv4PMjUPz18ypVbRrkqmxKwWotKSnL08aJxYjPvl6uos29VWnFBgHnApK3QgiB0Y3 ayCLNR+hO9Piq3IRHeK3AL+7Rz3lVWcmTWq5o1DXaeIRd7vqjcMjHaxvC9LxKspXGDrBxO/o1xMk WDbNSGx7zhNKrL0QZ/HNMMXOIQMYChLeXQXCRVjFp+6mR/Aq9Hx6KgVrAwF3c9tHupdc7SUeF37v X1hKkNKfcWDDxjI4cpnZgk8CJGE9vty2UmETgzeZ5jKjOj7J+b55+WxNSydFMBMlALsJV4XDq6Cj qZLaoE7ueykZZ+yO5Q2B3FhakL3aMlELbhluO5RZGJtSj0/BdfCXO2oAeYw3oS8xI854b98nOVOw 5dDMbs1ztejqClMrAtbou+AhUdCvcipiRMbB0FEIslHDXcJmJcsF4RuQuONpTn6lsN0uuLaijJe8 tou1iIfXdy5irD9nI4syBoNiYb++GTRsmMH3TnEr0dQlvfV2FvUOvbDpgAZPTvgP9qiiQBV2P3E3 6xcAViIK8bqVoCfMaD04QFn2w+zCHd3WE2LD7dgGyDNys/SuSw5+2mOiCw9UPJWeY/OtKBMItorW tLt8wUZe/hxTVimDedE9cRSq5IPgdZdLkWfhHqUrXzmGuR7vUMOJyzVXe43l4mvPztRfI2NvUSwm BEszSzt3sJ802rJLTvJd/fpyDg4DinD9sh/pv43hZYE5ZJn/B+a5IdV42ZLocdAFdB0LNDWQ10K6 rDQ4nBVbqL7a7kzuYhFxvZ5ORn6WGS7SWPFXRPTSjG0OtjapwJSjSHX+ASuiYrR4m6xgHWKyegmR FgD7tPpnH2JKrEGBEzWefAtae/E6x5GFb4Zpa/WBVvZzJpxy84M6/h0FTMWyHZYEvckOCvQtFr8g wKhE4JCdXKYZVkIpEQYCssqnIT4YI8zjl7VeJpDxbrYtMWo1xU0sXbGxUrIpzRUsAP9f8DvkAqmv 0ORwlnALsfqG6TRL5PY9ZC5d7LOTIUnRMxZipcZoGCbcHwCeJehBIHUiXH0X9Dv7AE19Z7B+plF4 OGUYm07gQQSK4eutQAa+qXf4yJIvSbQ1h0unoq9e7ILmx1DnJXf4miDyVrUBea3Puya3mLjKuCJJ Zh+xuod00/5opLHI5xq15wxQ99jG9tYxamEViRuPYZSeR5tAj+UsLpmzyy49IFxaHVSEJ+drClL+ DqooVhHBvhDUrbESJBA3Cz/fWFMoOG6s5MTs8HdTFqmSVd73U7DUY7kcpOY9QYtokvHSojwXhAO2 +XsZ2ZnOeLComdfDuSftP+35Y6gSSwxxk8e1xTfMUxMZbGHrCY6vEYkA3tOA0nwilriOWbd7kova rGSwOgwWmqi9Q8VkYgCJHhqz18neQsCtQt5N4z8Saeywcut5/rwIdckh3Bl9R2dy4Qx3/x/uATCx OCMVlYkhxF6j+hF6weAMBsvOErGUXnVmYwF5Mlyrwv9ZoLIabEkwPy+dKNfbMwKNtf6D+You4NQa 8W+Egcv4x4/eEqA/YOO13hQHKy8Ta+qEdT8tWc+TGK8GCgLah184lfiETn7LcK4QK6nHTXeVkDOj 1Mz6kvPVW+xf2b42VCQ1F+UougWt/6fzZf69bvgL6/OFQcAIZSFrcBIjiHRt+eBJ7OUS7y8FrWIY OZ8gKP4u2wm7WrD05mDxY9zZQUpVb5jJcTGELLLNF5aLwmeuzlKmg7VAwlb8r8me+Bj+F4O1Rwqy MNphW+ruqqP45r67R/Gq+r/WSl1G20kNyamdPfBCmIoWQ9NLdudro4dSdxR1lgillOeqocenye47 3nZyUAC1FXOVzFa/rzrE9Ja6Z6UMiL8HS0uSGqYJ8EbA4vJAaKpxjpJB24V1bB3J7opSdc55u5pq ueRIbvHHTYKgDlmHKla0pktyXTmWGQmo8ljcZjQcSESXZu8FkSL/HaYWVve13dOxTa0mTppXwkCE E0cTEhxaIR4EIeejr80/nLtNCIzdzs8cbW8L+p28Q6KRm+dh8SpRzR27QZqgHSRJm1kPUD+WBsav ONBBA6dQzg5qSqoYP7rR61rJltAHX8xbFUX/fVAHj0wS64gOmS8C89PFTEWpkfkXVu1/0NUhxz76 BgWlvDQ+9d/vyCnBkJC24ZS8vDZJtDi8NcXj4by7+iOET7GvaFAuirRVy9pdNaFt1DiGcKAAADGi vzGM2F9bjcGcXkeffREsAkVvq/gNO7ShdY80E0TeehOjpvjQOgc8WjHk7grbbBCqkcid4gSHWKBG MFpdBhStLECAqbqN61yvFfKfUjM7JqvQeEC2ql7h885ERvmhyS8V/2+baFv5o19HEHFngZBYlkD1 YxVOKjWTUo8dryl+08nSHS5EsosSAcmSeG1ufEVpwG3igz/PXCbR08FlslgJPAV1vz9TQIRqnGgv S4QtAVE9NKTHOuFGeQTHwR5txOTgEbnmPSJt884wlSL9+Y1KcPWlr5TOBO3K/61gD5CnpyLzOMD/ J1sw/uC+ZxeJhIu/LQZlSMPIOmM3w0pNYZFN4eG03UlLEzgBhYBLsTWYsSAGomIYQLNtL7p0YNTd AqfuwT1HML63UJzBhwCazcHLbW+I7DJs1Oo1ZlXxgrjIFAy2+Yw4/8d91pqzwbfhQiuiCTbv0rjE 18TYisfxAeLmdF9NGdm2cAMapCy6iGnJfaTM0fEAs8+3ZdVMk98jdONR44kCAChvY5fiPIt/RfIg YD+ILn+JFBKAsM1s0UehGoOKFx4R+gfEPSUByF4t23mA5B9IZbi3x8595JcURtGlS0sfdO8Yxibj jQYjgNX2KX3B5D35JmMVxpfXrzjo1AMo77FRRslmAu+Wa7Ylyi/6HppTyrZ4wwRKRISdY4ZT4y3p nVZAXjdciDM+3xjFkbQFOIA/koHHzWlkz3jiSsA9WH4U4nSipeNSiu49VXn4yz32ZcphWP6n9s5h BcD24LTD2wRRwZt6e9i7QWgppkc+hjZWDQZQVsKeXupucen+UBB+kanGUUEnj1JCgNSN1Wv4mTLB a1r8jziD2nNKAkDC/KqkqkOJGqgkz1JU76wWc7jvc0Hj6pBl468cj5Ang9TKh5/eZ4wGMnHJpnpK Zk0tIteA1Tgyz+vhzoZgUMWHL/32tm7jSwETiPDg9hG0tPTahzS75wMw4Y+hWOApAarQ5FiTcosi VNEyvjpK9VdzNbrYWcHpIb0+UG4ue9MxF87Lkjgx0Cjg0SoDcghY5CvXBll659q56lTbRurlcITn FYT9kPm9rfHjW8dlyiZmchnPt7ygnXqwcHEGzdZTGwJuw1UliAyxtZVFQAdoqz3s7AGgkg6G1uHO nPl52YAyE8ggX3LndvQnHVB4RUowiQIPwcoNgt9r5nJcCRcgoICV0tts8AJaJmLj42LAxs8puHSy rzFeItRbmxcj3Klq0iC9WJuYluBxV7//ubdisOI7hlrHU0gEZB9V2DaYRrb2KpcK26YdMPuRqveQ 6nmOaeLqC6CdZ7EzVnc7Ba0at0/kcD9D169Fkp9sDJ3ICpUAkeQKKYHbhpPGIwoDljNdLxjKWQa9 7g174s7SEpgcE6pKs5VE1gGqS8ftrlaU1TWOW78TZSr2tclzPW9cecWcq0dzs09z+/Gh3MXnL9eG LwbeM9RHZHGop3Ps3BAwVxwC30us+7zLivjxODTvKsr3un9q7OAqYLfbVMKnig1dauIFz7+SphTu dwXy4XBpzJwuwFbPXwCaJ+9Jttlm6nHNruHP0QMqr2NK0SPZ4BLfHlyHIkVTs/isyFpbUe437y9M EMdoP+HCyqi6RXdRylj1cyrUPLRYtr8FyxSyOkt2YfvZc0cwsdhO5CO+nDbKLJUIuuRoAm+xRdVX hXjNeIdCH5ULIXxoPMZi2eK+aaqn121NFXtur2XAfcRPOZfDmihSZk3vFanfBo4TbAJ5BNes8UIf 6VoapfUi3DG0lkNRX2GUXgHs7vLAWxhTx3b5xBXr9I8f9rhnrfEHWwhhhfCEr3D3gWftdQTdYMFj WjbEEo0hLQ3XQtcDwpJpGyg9I14rcLJqJ6vnnUz5Mr0QTfX0QCXNSNRmzQsAOP8liX8C8/8TMPaU evVnu/quhjCUSM6Acwe3r/sW28PVCTXZSdzeBWnBs3/CDnJH+xCRbU52a2W9ckKQnmblXr0/AdQi O0cEnSwJitssuzLa8m0tNC7T5K6WJ8HwJuMhJlS+uHgtWDQvG7NazeIC8MbZbaca3iDdnlyqppPD UHuhevws/U145fP9/i5sxXhTZ3SmwQWeiHtQT8jy4SxpOeZR3Oea/0yRstY3hG9gDs09UjxdOty9 tWHjKSmp9aX7dGTygQrw5IEGKYtHUQtYFuYFyhzmrcwOygK5bOyDBGr1j1R3Clkd9hkIRoEf2xyQ EQKS4qE99m2N11eGYyxtGUi3znW/3tgyDJPUj4YuMDBFQdCL05qG//c++1Przm9xV1nGw2YvTnI8 /GM5S+39mFJKMxaVZrcRxC3b5j93nXerGKgKZHLBopGi/bgbySKo4tODFXE03T8u4jpr4STiJPRt WN8q8zmUYJVU8OgckNVkCg/IyaWm+ghIm0BZPycbtatjy76nVTOOON/YcbtJ6y1TvS+5ESkYRys4 K6wOn0PpZLIUL0ASjcz/CEqwD5YeDbjBWUbXc/d0R+AJ1gJvcIXD0zcpaqn2qXwP9bF2gha9oDYY GIBg/geKmvp0TMcVD5TPLcn4oKW6fpZb1/m93NQ2XYC7EIX16f+Qk/vK1rcWCbc8IkmYCHTQsvbF AuvO7QNEOwEUUaX4KeIJo4FiKjrsqjm7L3i/LY0qieiQwR48HY+CZwv5WptZHRvoIxrT5fdoKqBW qVJz7s8sfV02XnlLFY0q0LXQKIXggR5yS1NzMqgzen2jSCBIz2dKSSYegYCxayAxS82WX2vMMWDU 8FCBJ+MY0Ey7qDB/riIuf2pQxLbIqOp7kwGitAjAjdE4+dS2hyc+Jco8hcA/AtGRW1UCPr7GEp4A iXU2xe+DITh6nthXbbfI8HDA6khXGQAIyHNrVyOAj9My5ZNRC5PACjwWOWLrjtgleTWIZ1+bo3p8 ZRnLWN8JbJWWI8cbMPftNmWTlgawWmRQrbCS33HJ1kz1lulcbCymETkuQHyhOG+fnJbiO6ECrTZN UEWcFO+OfpHvs+5CCU9rAfK2fJYKcOvd/olE3IBVz16N1UuFr0b4YmILFwe0aTu7I/mtYKB3wKfC ZgLiYT3Hy+dC3TNR2bqur7WBqZdQta5mhF/+1dlUofwU+zVbxArhCImQgLijPkRQ63/EOAZ1NE0F lE08VgGPgSPOE1YZRwhdR/+uI0HpliffDnwtqjc/L4+3ckwi1EEscIcVjxcDFBki9oItaUNQJ0iQ ty+KxIb0Bf1nszHNG++vQ+E84kb0WrHVpU96iUpglpx9j7m6t+ai5CZWeWI0GnSa7Q2/1p/z+Ck8 8pHGA9zL2qPmMpopYGFr8BfkIhea61X/skGR3EGTU0+r0as853nUxw2dCmS6ZDa2gP6yEwpfPR5R 9tTXg4gVMFLCgGSf0a4JsZaWq3kwNe+o7JD41h0seEf672thWFsMXmhS4Zlvacf4NxY4yhxntCPm bZKTgd4RG5YjntuUSQTp+yVgh0TaVlo9KYbgXZmxbbLJ60n3crHjLXOP5pS82YsgKGXDCYrXMQBD NhEec5cM8RAB/RtrA5MWoV6/PtsCIszyNNaqgxCBIo/9BDxTarwAWWH0TMYOxcXwAbFGKYzOqNh/ daakI9nDpnOp+gjwwfoF3wafMyVGGn4+Al++5+iV+BDell/nwMH6MgnDK17SySGRbKrv/8FToH5I k0q7SpkFgE3Rx0I+Kk40Oo3vbJyjC0usgBY7myLAdKlhZ0i8JZobEHP/lbmTuGxdw5DEwAFa6h32 ScHh/XGHtx68gfWx6S/k+hfEBORaIYVm6XaaoIBJCZwfivWtt1G2mv+5jdw5c6b5L/vfOCr7HirV 4A4XTx9HbJ5ItkStCqNVKR8VszYFmskIaHYR3FaQYQeUepjy+Fp50GeOzbajv+CbALc9v2r3iSNY UWyNy5vVjCytgI17cdmYoD+tAlvMFUczXjDxrHNVp3ejvrGNjSRC9MgRbGpE66bwF2GSw3Ir/gBP mt/wGuDYlvDM8xwGkJD8lNVNxN8eaKF+ZpsEuBkGIc/JpqKPCnl2KzgNbAzk3llkMuJn20xA2YM7 mGf0jvOPKsYDBWJeTa9DR8alQExzG/twaGPHjyxMAwfEHbkk/CnrsllFiWWzSAQl3WAZ6kCPmRLM PY8cjw42zUvFAvLMvutxpOB8X2nbXIGXObq4NI5Vu0sgVF+NAMng2UTQz766ROIl12D66Wf9tM2N RBDYzqigUC5n7uADSfRPKlhmBTlSXae4hLY3cmgYHibZjGCAHFaJ15CkGDCTYMbcsa6soiuOhFAh +C77GckZlRLkcQ7IQKlHgphNx6kPfuDQ9bmB4UFMswyfNYlfAPi+6qPYLaDtBreSHnjMYkEYFCs/ HOgIeEzD70pUj6uhk2pM7XEX5pv4aVvB6jgNyUQWDNhWi0rxcuFlSfRNyaCmOSlxC+DMrXwLGS9B O/WqZM5FdDbiOaklqSWzGVLBvE1qTpH8ZznZqeL9XvlI2b9YQ17MtuKx8dFp/sUbSOXFgQxDnQ9v 1vsoq9gq5W2SofygzSZX9krdHnwe3yYTOPRSl40OVsTBAjFrUmEk0KL7QkMv9+aTeXiD/ThJe156 ttTkdmyMf+DTCKXc4r+9SwBvss/1oA6BzY2c4Gvx0Cb5JwObv5VTiax0qsAXTyOJLp0q6PvEXVZP mzgRbXuo7BFY3g9p3w1EinOuF6uejvhCBPrE0HhF98ab4By8WCDdhdSs2gm7kVrFdC72P2gWqz60 Rjh+XaVKTj99kfVj3CwnIsJAVL8sEo0/aGRNE4bxzRP+qPL7rPXigMFWohFvwzqljMWFhLt9jk9F i17GPOqmQJ8rrgGCunoHsemrGOWhZVK8+GefndukrCO76cAGhXy/VUz/qtl4CVpuYWNCJT2Z/fAt y8fRuRKLTSTHjyC5stGwYpoeYZhTxvjKNcPC31AUGEIBUe0hNXZuR8vYA5c0YKak7MyCGdpx0vbb b74xSYZby4l2MezgKI7SWF2UjI/V7nlaME6AsgzHE2O+ygQ+0fuXpyYl7wZHP3FtUrXmsA/NJQyO joSqhzgn5HTPP27yGQgCt7yKJFxqbI/zTSh8jM73NHL0lIeecNMRzwlAl64gEXO+z6LcPhQAqZ2J KC6Am4PuKl6FG++MMaF6gUL+mDU+4dhLc/KWvNgIsHptCDdTr8pmbaO0epj6kRI0mp0bcYSsduy+ 9X0RVHES1G4qOyVLHZucw5chIsb1QvwEgu5tNTjLJjZx92+LArAvwPbZz3yzEkT6Ig2J99uzVpX6 xJFFtE6iNV/+bY7K7K45cmdtZM3u6CrR2QRYvTnGSz15xQ/FIHavicWVEl+6H8ttsMHIG3jK5lZN D6PH3aFWJ9EcOpuXvEYFDNz00lKDeL2yNKY4hprcU1oJfUAGldPU1/lDFxgBSUCBAwFHCT5dcRts PH54dBY44HQ37HEBXe2ueaPk6hSBTkZIhaYJxBQWUe+kKBMT8nLMMFrbOX/wt1lYSyrrB4RBk/k7 np1ZQ7x07UP+vWA6R4JHmtql43xB7q5jS7sy9LLYvWfStB7pmLfUAvOs6fRgXp3du03uhBAVPt8n QQp5wlghNW+iYz/cRhKlgHrFHftoK6dMTZW5jsowkGzBLLFnCpy3QLetJlEeOp1pqTJPL4i8JPFi aMSa16AyMyjBJmylF2aMMg/e4CecbXrtDsuRP0FCARXL4JnBm67DRr4Rmu7IuQaC/YsWZ4wiPEpS +S92cXXWEt3eElADDTrUt0Nxe4K82ptn3zPUGcqnUDItLBh7pGg4vCWnwtKXa5MidpGZCtYLXnEM yi1vSz4AbfqOkHc+UDx7wEPx8UwjLvxLxG6EH7j9DenqV67J2rOHWDjMLbWz+VNxisfCDhrR1WlW G7ZmppSyMIJw1jB/zQ3TiSiFrmXuIF7Ev/ujJZrTAb1rz98Ftorg1TL7Y+cAXOkd2M0elrk0Aidl TPUJPP2QOUunivrDKQbwhJILdhp1kEogh9raA5CP5wpfwp1B1M40EBDI7zjAFLWpefzUikG3H3YC 2JXS+cRMAjONzbb0CyTGaoHNcg1zxu6YcL7HUXzAoU7NpV/BqqehfwjgBmwIAcMd2gEyNrfcIOI9 wqfxGxeSQPfbTcAnZTGSazGxEq5YLUi1dhegw2eiARhMSOHBcy8SphcnHUv+gQnO5Z0gaxy/TdSo XiuXRjCVJebgbveZA1xehH6EweqyMjOfHV/dO88oongjrvB5RsVxUonE9RwKFB6si/uYQKKZYHuq 5dCv/AIjqeYv9rRYuJo/CHZDzZkso7ixFsIJRjJ9sTlSQO5V2UDBsI0oyPlSjb4avUizHQqnV58c jEkuk9UIszV2grOnn+voJI3rXCjTWJ9K4YfOFGDew7IvbDENO2vHvaM7UFp/lQ64BeUKU0XqRV0I qKIlu8MHLdLO5lV6BL2lqfRzQDLcs4xrQ7oBgoi18ePXR+ZLRoW6YvXyQhK75/7G49tZyQJfew3y 7D7nge3E6iUKzgim9VLZAfA1Sk5cnCMMXmkdWKIjI/iRe+1uMuNXnCoLKcU/mS/r+lgjUU1DBt24 Pyw+OP2KhRs+M3eNiVCItp+mmwca5i8uUxMrs9fCOO3lzLUekBrKR9L16q7xFzOyyd9FHgpDkNlR +TLGd/Q2sidn4AswKqzZ5Mnxqy66xie2TgaDtRmhru3x9OrIn4xBcV5Sh9b1G6mMRtSU/QTG5UVg 5u74HTdJwFsiyd8jLdhLTAuq9XkdsjdY+uP8euFv2yGOGTe4/1MBCZFMEQhLd2LhsZcLWZHr/Uco cNl0utq9z9p8yLbZbpAgoKonLbp7zpvY0VFswZyS2I6+AJ8GKSHuqDXKswrAs7Bb2JZGCFbT6g+v +Mtoz6ROhELjdEMw8azcamO8jTDUtTJrELXIpGPqXPkNzCnYe0JMQxWA4mjp+cBsZekBQkKiwJ+L auCCehdrR4eoyTfFJ67V5zzfhO6rTmPlrVCcqNAa8V/3S/q9T8kSJQFBhxFS93vaOTXJdlWe5oYb bx7k2l1uXnygqc9h8+AeJMxBRros+TZipVGFhzlyOepuUxAXXkitD3WYKPqQu7+t9q54LPd7LaiL njpR615OQiYxqzfVBXrP+UqxtW+PbvFHiMcl/VPuXNsukXM6fvo88UGYEQiYO2rzWKPCEneakZxM WHAY3qCjUl4xLDlTfRIOAyLTSNC/krZv61pMFvWHBkWL3b5e2/RwCCHfV+thmLsEq2FkA01mKi8I oPQe76p24/zzpENYLDjdyRXr8LWLuvjyH+N2H/b5lm7vUSOIgNbij7sHOfuP4rqMw5F4JFr//MoZ /gcKklt4nPd3pU60/0bBBZgtnlIOLgsljE244CpbaiPX6RxHMX2ikP4ZQf2FrhDFwJwriP/kKd/d Quh9ZeOIyGU4NUdS7TR7iUKV9ZvJlhrpFLlJmqsBMhrRSzAvre0C2xKqro1CBpc5203l6eMurV5c GoN6y+5xsdHMpjU0JDheAChhKa8XsZT0eaA5vAXf45Kpw2XH63HpoKvf6lwU2y4TRf2lYPsii94B h5HVe9SVaob2WiVA9A7B5r8HJWaih2hP4enj7yLZWNrmz4/Vl2KgDciPypOm8UIq/2YdR9GT3CNb 2rzIfqsAQR+Mu06iMoGuBUL1iAor+ZQJ6hehngkEzmWyEualg2tJBXagOWo7AfrL6DLno1U4vcS+ EUHCWT+FNDZBq+72G6AT+m9zNMPSoKNrmBh+93rsnnvXjL+56XUY01fkpHNPQgxFdPxXDCgZpWBb jlhJOD/Yp2OjxHdnmq3+9pMVSv9hhxo8swfrL7ehslv5b06Rt9iD/Ly1AF39L1dUDbvdM++2bYZ2 UrJILc35HIMryXNdebctAXSUjrm0txZSIaiN27IWXJMu0/v+X3LSICkb8GeUwgiA+SGEnT3kPAZm 77LIBh+SEcgA3P/26UMXWWCFgPelTI0Z5d2rPEAheDLX8gD7Xty5v7pOFN9GhCPI4lxt16VsUySY ZbIs5ACH+gET0eyAR06VPhg+1XTYdBACoqCsBlTW69p7T3yaAXgGURgkKApi1yMaktW3p5q6lIc0 fIms5bIhijKcsW+uKUwgKHZWhWsoy4L/5Zw4rg6e570S33p8pLHzBVqyUYrwZlFYpVbwGgs8MO24 Sg6XKmszqDq9cEu29/rKwW+okYQHDY+uyR2yeKCCVgv1YFUXmZ/fJJbNl9FI7aXJFErp5LgyLIX0 9hnGWT4bzmlTDp/1RjJRqQUObSc7PodApCx/d42YdNsvEjkQHNJaNnY+VDjMylAtAUX+1uENzemG hxl9qgMnd9Yqt4E93887zVF3jcNoDG9i8nYwcoozAR5r/dndUxfLBcTMqubD5tjogc5zSmCO/CAH 36XbjAd9+tKVGi6ENeroLtsTJ+cp9tGT/KzQrOl7j9Pekiey0X0DBjVceOYejUPpp2AY4oCjrhew u2fH8r6Nwz2r0x0OTqOdlGcDXo7CdV60uOXHMo7A5cmRWh84FuLKjds7sAfNbGXplVvpsLv/Ui1A Z6SqI2vPBuaCmf6coIYtWUCg5hUmvMIw6tXoJrURt35lfSyoNYi9nKE8aEXIxtLRoub6MugZN6+b ESEyoptewHrDIyFtJ5v2yGZ1u5MTXH18g1utVR9YllSiqb97eYvPqq+r8hT0uHhqIXgeU7tFa9Ze mKBMHQaKwvuTyQgMOIJ9cceRw/sz5yT9RS+ZAxOQwQL0nzxPNOjr8b2hP8D22jc16gTROyJFpThu efh1uTt9f7yW0jhjDpA8RoSgae1TBSGP0IEP1SNlzzSIbiCcwwfu9+1Tfp6V6n6jS4bVjCV0pKI6 aI+oEZg1iSjRZgsFzAkkfat6ZrDoFLZZjlG0q3z4sZ+CYBproa5tAsF7jvPdCpVqI2HG4717OWHw sUFQwsh+WVIk8BzF1R2C7n19C6FSiAx44dH7bPlK+BOiAE6qGqtIfP7t7FikgE3txmnSvKBQ1lez PSBbSGcORE7QoTSmThCIYi+I8rrGj26j6HUyMFSIchAdfGVG+xAWb1HlLTrUIHE4bgWlX0mWHD0D rqF5WwT7UUjvHaK9uG0iardgKd8+CjmRmuoMcRTa2sO5RtXAewZ9PUkUqKU1ku/L5+P3IMOtZdvi s748CeGByuL9/5oioEVQz81jCgl+PWeaBNKvrtBBKPPIa5ldBe1024sx5Kn8g1HKX8Pe/EkYxqyY YsgEBHxh/WjZj+TCXGS59aL5UqXv8tsMFOobSjWEds5a1uCENAlxxRw3BVeGxUiTIHGBhq9z1STy rgWh6XHS4pzFtjMAZ+FvxbsjE/OMbbGcvvHe84+5lLEN9PQgNQLnpPuwfyCcgMxzfMxo/WSVW3NO 7xXNVIeZGBzeI/DDq2wtFv/H8rwseFXMU7s85Y4jCYGDwtGBAbhl9cg1HFSIFMBIYLGQ5FehAJKe N9vphVrmPYk89pSkIIrC52QBQGZ/QKYkYRUU2IGC8M3EWmrmwybUcTUcOCdp6hDDgr7whY5qlvJ1 TS+u+tJEDY5pG3Pgl8eQtYPiM8TubY7yAWrXRVWNkNN5GhdUepf7Yi+VUYfd0GOMSubgGWjT974F 1I05PvFNG++87akoSEUgrKnNt1PsO+MpbHo5hmleLUur1GlRyIkxlflQWizEcYL0MJ+JFj8yWfMo m9C00gY93aRxtYN8PiIF7O3B+XSxH9tma94TToUATEQx2YAtWvsEl11/LQXoVAfsxx54g/+T9vB4 JOWhi4FumdtLsXz3uHECb5XZ0cuzvCd3izbpCPuTEQDShKKJKFcD1U+WFH79NmjoJHCNm0KOwiMa mlm5QLua/gk3JVM/CsloPfEj/2CKP0aE0cxeu9y01v3sKpCQGQ09m1fCgR+jCnC8phoX44ewhSdV FtJD4+IWAvr1ccQRmlG74dR86dcY8W74Y1bgdAgyXHhATYvxrlRhOocNRQLQ2QGy0sgYiGFhFYJP 2zNPdvB8mYuM28tFo8lX8PLm60X/2gDAXI7UP5J1/6kGHkOQCDkefrSDBuiLmFBDCY7oHSGa3TXN /Ahr8f1dULQU7wdSY+3GGRGmQRaGo0T0RF8FwrmmvsZTZlOo9H0SLGmbjy+i0/TWqWcTBm6ooyc+ dhj0Z7+gKi4hBscEXYkjV0Jgg1tFXj7YmkleVKYsh8h6S4M2chsoMMQL9J4lL4W08qcOuhVriuG7 P6beQbHl2OdfEx9cydi+/CUJe79GBJMSM1XE1mzeQy39hibl+tQlzVUmWG6anXim2CZaAnLdFTQU o3MrZ661NpbdJXh8I7vgnuDcRd0+vz7YjtOrPAr8DtjmnA5vOclmyml3xXWfx+kz4RRvNvBlaw6P OcN/4ZmcYMx+yLu8jeQpGy4iGSWktgJZBfZXNPHPPGZIeOn7xD0n+Y5rmjZSQl1Tp5fxsPqMmJzJ O43FGn4W2APEj5i8djzHccMcGjO5VhpvksNFgd3yk4dy4VWhZaFYJZLxiibiL+tXNKdZqasVLhjO pj4YHBpL6xgEA8QE2/2QgAKGKERUhlc5P9l/cSMZk0AutfiaHoxQbO9PIu/O21Df4Z7F13r8FsjN q2LGA29MgrsZIAYwRpjANNWqkHdgdN9X5Xro9n/BrOgTwn5cuN1sdbgct44iRT+MFBRXDKe+MFqY DRni/e3soqhJQXhNtWqYE+0JPwRG9nSEkcrLHOc8TEz6v/CXzEjKFMMncU3Yyj+QkT35fDO77k/A QJQiiZ95UcfEp27UnQ6wFWUX2/iLskvxmy2EnQbiAscN3OdUKHFXjX03aWZN0yJSvV4z1GkaCOQh yt8J2pGWkPV4X3258qAvxhJDBcNVsu0dTvwhJoPJpBySUl8JYuZFSwmB+WszptX49S05PqUt/Cfh MrJSVNozt667LWNfSzPArVFHfLYwQtSJ3tol+EQSWh4uKeKaNBJsbMXnin4GhIjRZXgZrDmMcvYX Rq/r5J+qB8DJrkHxZSipxsXEADYgqH2rbWIXFBL523siPLdmaL83WGhVt23pVjNFG+AxdhXikA8S e1A5VGAyxxOhUmspL2xeeY0n9S25euRZ4ryCgycMc7a5qSS+Be/blI39I36QgfrAozJpO5yJk2ka ybYXJIJRI23QcPOG3A2WKjm+LwxDvrCG5LrqT98RA11VUABt8NJdJ4JDoSQtPP5017X+xa05tH4v sDiTlJSUIl26HPJXubuO0ULvSG4EspM8OlGNNnK274jVaB5q6o9OXoDQhPmMrilOPdmIuPq7dwEt nxKGucabu7vdZw== `protect end_protected

mit

benjmarshall/hls_scratchpad

hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prjsrcs/sources_1/ip/sin_taylor_series_ap_dmul_4_max_dsp_64/hdl/xbip_bram18k_v3_0_vh_rfs.vhd

20

103154

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block AbrLtZEWaMZ9QRIEqn+KbGJaY9tnAHwhbFbsPC7WH49ehpa1EbqXv+qkeNRGupFwZ63XKanLVUyO My0fDcdlyQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block jBjvZpZ5ZMxrEO8+CEfz6CEl8aMhkYM5vXXCdl+QFohneB/4ao6UdzksCSxNPxkQX54YmGSOciXP wgiPEkvihckzTQ7V+IwmdcU3758CZsJi1jYV4WKld6YxfbWBrziJy4pEooel9pwm0aG1jMx1yNUM erFXjNZfwKELIgXdp9g= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block bNlKYiiGIQP+R/ChMF9YxWObkJMdPWBzZKUDypAuNCvFSKj2ODeFkzLXYHokfw+rz7RZe5YojYmq 4UkICxShbV1k/N1YYli9QKFi7npsW0xHaRa8L0tSoNNqAKETg1msjVmjBV5kKgQ78l19v/4te7qL zUqdthBriU3NcZYre5k= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block 0gJe90X6qrVRqoGU7iK/i5s05zq/0GlJ22Kt2H/04aXbES5oZ4I0aGRfiLSYUCL8istn1JleJ/n3 1/LRSIHwjesRoSy/6j9iedPDLLSSnKq+N+ZcvCJl8gg/L6B9ChU+h5YNE7HqJVfqJzqKWKPqsHB4 WVtjQ/Uh+QwxJp4Q/GXnPw1qlnDs2s6lJ8EK8000R7Any16QZ06T5S1IW5s5v9bKhWJj2Oj7lmWo 6QSr9mTUFxCIV/m+pXzsIOsSgFWqsBmD8jksQw5AorgxI1HaqEa3+sl/imtv2p//6lwEVtz8coiR PUlfIUpZ3ecBYh1Zuc/GrakwiRgEs/Yjfe+jCA== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ux0aTH3zrSOSGrjxNBhNJ8nXWhxNzkLj/DcKiIgChJ1nxm8i4YMzp0L+VdbHtn6L3ZPNF7NTEh1P v7Gcx16JuF2FM4sw/t6m+FCjX3oHl0zUFDs/HfDB1IEXz+2hsgoR9SYF+bXbSth9Ql5SVw6WlbpS yFwlhS2eW7RGdfH7yFg8yRwWXcYySMv+L+udV6VzSwe0SODgbmC4o26VRMdm0RBQjLnYxl3eT+4N Qf9DbWnbFLLU2LtQWORMV3hNidJEmt4J99c08slF3izsh110Cv87/wiU6Xuvi2AB6jI3wVkno8/h 1xSxQBnRHm/fJHMh/8PrydoVk8qMhMXs9UM3dA== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block A3eq7CQ1ZEC2Oz4Co0wE9eavdVVL5N2w7vnxu/t08WjNVvgkDcorbVB3GWcUKigHFQo0FHxElw0D PA15/K+npi+dagAdVUmv5cfV+KYrdhCLG+Kvl0Tcm6fhXM4RH49frRlov9a41BctZWlMEXzlO2Ei 69nxF8+cDN/RPLjSUoKp8oVTX2g6+udi83fdCBYaBZQYCaaDSNeGqephcoL2zlXyK7vU9KpsDUWJ oZshHV12Yw5hL+4YuSmKv1aODQadN1UJ8qyFc0vRYTAqwP+hcDUwxiR48olGBo7U7czJnFk4AkkD qULDB9rPKRIK3YJacz6Pp3GAHUDGm2JO78Eg8A== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 74224) `protect data_block JcYdUx53b3OsTtOdv/P3/dHcfx3utNQitl84Eb3aQ6aN2AhKiDHBCYuvObX/v/9/q30o29Voi9Xv 1eu+5HrxgmBEFCpVYOVqTx+/1TnGsOn7DKuzvOHcne9bSxaTDrHQUCa38xlkHitY67JkqOSIhVm4 jpO7JF5H+JCbmXDt6F2T2wcpFyMe6Oyq6RJfEQlANaFqDnOQOn74eKDH4FfNR3DAsyf+4EzHf5OG TW+7XXmSI6vfomJkezPGmHNVoROjvgFnK7TnF0VmsgNYiKlql/PnEKKsUxo7PMuYq6GHoxcRo6tI +AJMZXAcc5avne6SU/2mOc1O1rYlDfuMOYM72e7no1V5trXotFkDNz5Yw9t1TNO5PzYih/V3YVbU NDBobDLVy/wQ7ecc0PsBimCh2Y7dqxU/EZO5RSJamz23VZJzVUVgJ45yBITzYoilSrt0WNdaFHyC PWPFiPnYKP0yDw05pHULxNgTnxK3YRDelWlT8Le5QF60m/HLUi8Nyi4fLPTjArMLSc5DKmg658jh JSjyTrQq++qYQaFFjKBUDtVvAWZYVhPnCexdXjRceDsgeTaL1yHhb8dS3xjv6QOjRzHBL3HR2Ob5 H+AbHQEQSXdGVxRnFCXi/TKUvtom8R7+JjrA+0H8CcmsD19UbQmxBAIgVidUDxKPApBiSOboEK1x FB7wxHjCEI+8HPUeIwoxSg1FWY9CWrNhv4GbD+j0JemUcvG9HF+3zIwWbp/5UG1Z4uD4VYnIGsT7 ozoOFMVqAbZ9MVvvKWapv0P5mEIR6VlYk3l75W/7tanWiiOn2mFXHWzb40Nep2bXDj+PtAa317DY eJIwtVGdN/D22e6H24LqEMCT5OepE3aFof4S5dNwpe/x93UfOQs30Ddd+SejlVq1yxXLn0H6PsBG 2LJDA1F5NhqqlcVCkAuKwjG2QTvH5xG2s2mBjJsZDcB5mVc2E341U9VvVXgaof5srM2G8VPHbjwv DXh5h2kfGC+1flf2tSWIBfCB9zePvwkF/0HWgEUaLfu9AKO9sJBs+saKvXtVjYY3AmDruCCXM26z hl4STPxaAahx5qIMIXOmXmFBD9wypKP7t90uopZxOSL37I7VO78QjxQB0+h89IrOPr/h3l7Stls3 ewOcb6q5Gu0IOyJEW7lb+6eXgSWd6x0g3hzg/N/0fHiWVO+zcwfulD3tlAEoE9KyD4i0vdFlepNu nehaW4Kl/Hhl/1NzQ/03nZP9nkSMADlhZm6pW4XVN1+sZ2EXsC3fe1zc08URdBUVJy52cj/GAK5+ 2r2x64XO8C9VxmE1bQzv8MFRwuIYwXfn5XQLCu7rRvRxHn1nhqdbNOfyQkaftCvt6pn3YYMqCEsh NaCh/3weMZZ4R+2N4RQjrFQJ0LGf6cr9DluL4GBsTewvbZWsSk1RPYOSofv5WBejf1lv4vjZeYKx RT0N6mYldxbDlWR3AdlUyhsionLdPrjCVil218uZBhEBmIUJjEj+IIixWvDe9zXMdMXAfVeqpZe5 iqQSeghvfFX5u+6aI2+Ysjs6Ee6x2Z4Sl4txYDlqsF71hPL2hXSc6O6Lu6rePadCuS7gF4Rym8ap yTKLTCVQAgHEZym5o0HsXcbzF/5aPPlp31wgnRZmfNLo2MAbQRLWMxImz74O29tn8MGcexq3D763 RrcOOFbske3p1O7voWsQMf3AsMCkdnbqqLGvM/KVFvjqoISK583P/ZBvCj/dKJWuQjiHORGHhex+ CJk6OvfiOuxlB11yDfvQf9E/gaw2yiIbz0M7scZ69+/8as+HhFR3umpKPNlaPOvlqBl73MtouusL kxQKrCgQpSj7Qz9TERJ471PsJouLReRBseMZ5wZBc9oD/lblzy0p0qnJaa7AAmUfPxj6GfEm2BtD Ltq3GUYuAqcA5UHCxOS7a4jFsBN3Em6nYBPNTjIQ1GoTDASpjgEbjJ94V8PqXr46HFPrZbhAJoh6 BC7jmwzTPL1boaxSsIHZiq5XkWjiG0Fl2kMRo9pnxn2Djx1GRrzI9JCNWjeGEje8mNA7/sMq2xGf JoX60sufhWSY6pdJOLeF5ykh3P46LEqWul5krASGOygQ8jsElx0mqMqjwb+rcDi+Bjvk8Mpz+TMB uvf2Kp7Y/jjNDWbMbS362U1Rz1ik69PIdnDDFhoPs6s+CW6/XvFssTPUPaudKJ9nNu0oEDYW7cjn dgkTk8++gdo8oLTSQtn/RF2U4FWmN2FPMb9oDXTciVWpMl+r7AfNJpuQ/2qFis4h+iRY615JsAJ7 NrGL/DTL4CzkpsLzb44Im1Le6aGOw6z5DZBueGX2rWkGPbDzW7IdyY0X+JRZlgLcNV0VUYOjrg1i Q9UCKpY7g3KEHrFiBjrZkPVrmQQWHqhyiTEAjTDTMgaxk5M5wWGtMAe9erd1WbNWN877pjT6GkKD oR2tonp7V0nHHp2Y9wkittxj4vvtES4nMKMle3rQNn7xz3s5/5wYLOcyKn+J9FybgXezdTbch+3d nnmF+yZPBt4R71KvlR+NWPI2QTnnFME2T0xXQOpkX9Rm7meHqjpI6cUHaDWKNDxSbZwH7ABw2MZQ JAFoCu4cHJXWp9PzgxPtuaDrEgxrisO+kyIDzYu0bhr0sE1euNGSHpE7jR2flPgvS3d8F6mzkSsG LrhGYr5DYGHY3XyRT9mbTgCpgq9+vDOAHnOPh+s5IK7xC2BcD/aL5NLUWbvxtaAjHPhAVXoJdwup RK3PBpnBswLbjodqVTjZaL4FH79yg8rOmiOGwbOcEaU1+7vhBSX9+Dk6xqZontADrIkL/mI6/lqc 3Ojb8VdJOdxhWKZ0w53OFUYxCLecLiCeye9ZFo6Uh6ZncDqgz3jJFTXhS0tH1j5aHfXiImxrPp4I /Qmpiw0ZKIaqkGBKYY9368wMcMQNLfEms1B0JJsmahj1namwvs5DE8cHOO1LlHvPOiPm/qFRWTsp YULmolXqQN3/c/nT2N5bOilFSAj+w0cMfxlWIsnGtGt6x59GN0AsG8PvKo30zEsrjlGc5gii/dwv 6XUuMnvKl+CoOytiFqMjMFV2IaP42joEd4iocd8r/iIOf6IYliossSyQRPFgyMTvcEpKf/AMNPN4 AtaJ8dUn630dEokCmuq1ydM51QFUmf28+9Hy7V7sBhKaMz0J48hve1vluXF+5yy/IpIO+KRooQYO V0mXcy1Y/RCsmzVk6NKI70DO7/CeSJbZVMig7igFkjxDoi2NzqRTkpd4zAjDpUnIwfjnXZBhtraG VjPyVRAydV231L3nsz86ywAEQwWGBC7je45ybk7MjxHAN6D/lieDBBVyq2DVXo3qTL7bhVylE4CW uWfebqqYrXBCii7/pXCvLhvW3SCziIQc8S8wqpaq+J3BoH/fnmtv+53dEN2zhD2Jrki5jpxVMNWH SCaBDh2r0jwRJ4zkidB+kCuNyteD9V6rH5a7BbKEw/PwqFZB5vQScCy2rz8LJ4lMvDcl937sCcXW cpcm21xpoSSrEibBkSeZvqz2EdAvqiAHGMzjdDbfQXMnW/sivNDSxFCxvXndmzYZwvOUArLN2t0R aQZwzyfYWHVx3+rGhSePGi/njGN9N6sBQA9Jl8EMOwt/2rTVzvgNamWDldYkkwTKdWN/pR9tt7J9 y6YlakfarE3ffId0LW7zpmneR0naXLxJBPT9GqkXEy5aYx2UzAm50SWVM2Pbm8i/s7JQDfBSog/J O44R/R7AEHGp5iIRokL/fQqohmHLNJmc1iQ3Ne7fAXlOH5MOgBlbbZyTy4PQxZ+1dJLhSHy7aHoT BcQeS5aAZrRMtoGRVL9w8dofqnynherR7FMfx3nLQlUZqgKvuzXIRHZEEH+2gZooyUn8c6z8r9/W bbz3HVmF+J5ytAYVq6TAm5Jp6bwZ+YJRaNXxiaqQTWLYDeyamHQeZ4PVMP7Tel0iibLAKkHZ/yTM L1cnxFm7TXC470HHRqomxUoDy7YMsBvZdPOwL4zTCDupNCS51ljfcwj73VPL+deuBxkEeMlh1npP OVNqxyQ2K3WUbFFMZaCcf9NI+db6FQAm//ghHe1mIOJHwUmAUwnAOoYKeysyzLQiWF66UuQ0vHfe oeeb6X7UmQyIitKPXi9/8vZo1QMrU3bKeUOfv/Phvaz2ykHcnLaexeXHY0odDTeA/wbmLLMbnU1Z F14963JOnWa8EI8xVIBOVCndXGs7dHcGUBecRU6D27/gP+MIcbUyu+MomX5Edpzw/RlQMeTRUv+X gVCepP5hOwpqNENL8PQoEd1+l3QN+CmDrpqxKuDbMruCH1klQGi2KyURrk0xW3tvRx78BzADC6z/ e4krry4RIbgpjKpCMZ36KJhZhOJ4XrMNQOASJHrs/tvs4uubgKfELrt5ffESa0A8mbpQBU4diU/O jEtRKd4epHxn41mOiRYaHTqpSDWcwv6ETHyqceJCAzmPi5GhHZ0aUYiz3CIV7bOvynVTC6iTkNvY Fjc16r6Y1AF4aON5OX0kVZO4WQCBVK/j9xz+kFdZtK0WUb96KOXdn8+99oQp/XiLXzlmFCTVa1hk YeOIbueyaNdKmfjdONFE0ucCtf7MOuHzR7+0E7n9J1cqzYbsW6LMHq0kqwSrE3z80zKDhaPL3ZST V89l/yh7jw5kkbSnMy0QJLDrU+9YWKdtI2UHS5hLThDdgcMhLv8XU0W81bhsd53nwoI/xPyUKmee lueOrrko18nZgmGewHoRSJErs+j48xiYcWr0OGSVq1E/EXQp/I0rnG26R6ZMDUS1UlC0M+yzSUKC KeNa0JnstdmEiAcc2NbqwAkyf6zikHbOmZu7fq0kHO92qH1uIsXGUtn1PPV//e6upK0jNPwS4JG6 W+fAmEd5Wz/lmsUiSgf9YXz44Z2i5CbWP2RuFFTBNbyD9LFni/ox6MuVOkBxtuFhmstwNT9gqMEd lDbiRGAzlHSBvDfYmvS6pt8YtlIsL4v2RdpKzxu9okBFcaL4dSPCNv9Nde8Cr8h7DgZ5ohreqfr9 r+hYLwBRTUd7nyROUSNYtamBNa8gFFkrWX4gEkuCTz4RW9i9sIVfKRQJ6QN6IticXRe5Ik1GzcO/ AC+Wv6GYuGFVlU5ymWRhL//1GQ0aspVTyq27DhWucO1AQmEH2Le4QTUJzg1zzS2qAIB0TN1lfzRV qz8RrNO37JkB0SfFFeqMRwoEpRkx6p41enKF7KhvYyLK439yo37yRaQtdIgoWEjrGq743/rj3eMa XfbwzE1IBPNONtBtmfAm8RhCZDJyGluA7z56GXCnPdm9fNReTlz7L4m2BfO8oaUUr1WevXuYAF/Q HrxDyxC6BKRD6JWGGNRN6x03NgBssWWLrfVqn4lX85iBN3A6pug+7r6Y5ZNkfKU8FVrbuOqsHlBI PAaZ0qYincGQoNZs604N10cwNrizRdHbbygRGdqZrrjOX0y788Fa7UrL9KR2mtaO4x+emY/LamW+ /GUGaVhUYUu4SP0mGdFvy9IBl7ORg9VWvzGPQArn2YJwA+a6byIv3fJkkn09rPQxk2EzeSJ7VdO0 2qT/qYJhZoOb0fBEESWBEAGYed+4pgpc/xPo6vdGPYRmxQOcevPZFCuS9f12/LBx976Lq5E4GdKE BnfH9oHmho57b4VcG6afOLk4VfiqgDpH0oe8+09JtJvIXfzbAHZuNc+OPKf1cgMv7jXQjMhMwkzW 8EA+ZRCMwXy7HedH0b7Lriy/zl5fVlMDRnzmi9cQbE6FPQ8KWLfYNK7tU4xsTaKOHOLDvmuGVpTH ePdwPKG+N3CqkoXNTM2mfLtow7XbNKflv8klPybOpGPRLXBNlQoXyz2oxIRPAPtIHp1EBciJSDaW nlm+7Ykx9BI4mAecCUSiyCUGdOhzIA+myCSX02+Q5R8U/4PSFhNgbZo0PVJSs7xBdgq23eVrYHPl EvhwBx9wyxbasow6R6plTcXdLVyxaVVNat98d77Yi67juUARbex2GWyi/VakJtF47wRT0izyf/fy B601vCy+lGibHhtljMWAm59ahjCseUxcXcY2mif00YPlwzzgR6mMzEBC97KyNB2bvknFAvEXENP3 1UqCTPvZFCzxiiO0TqRi2Vu7SPI7RKcJhzh2gZSXBbHjUBtKheRR7HKqdQBYG99XmSWwg+DOfq0B xPCoFTLUzkSuRQl3CWs1gSCw4WaDaN8INIFw5NX4CPiQtmu72WOpCEjqaZOLS+UFqQX5i2Z5lWMF KMBLc/2dQt5mw0aXUCDvBTgkpZJV7/hejuiGISy5l3doCfteWxAplUsqitu+ykMLdMjqIXuAyFLq ETohUWC+tHJ+VY0kNxhk/1uSSlzx12cvV/z9lic18VYylN6pzktvG+jRrhBVo73eIDgIIv14BPrw I+lptJAlOlGsafAJPMuYvP9Fw5WYky2Y1AqW1VQ7a/TfAHjn01q02r2Db/DtzJQ8DRnVEsNr1rnF boJhSaFcZbmi/Kx4/wlSQBpqA+AJWAS1SP3eDPdv9TA112Oa22AUIQvIalRfsM7LxvT8eCgi+jy6 XJ1azPffzo0+yjdl1ZT4r4RQ8TB4x2g+RAJNx05n1M5fXymF2Y/YR5X17uGfyQC9zuB7kXZACMFQ D+x6zkLjhZankOAqjdTeikgRRitfIf0urJf9MgP/anRKHIUiG045w6kykistBjUIeQ3XmRT6Xll8 KeE+lRMdmwh5fpGykkGVqdOG4syihTbZ48iNXfpv57sq3D7V0bWkIRAh/pi51PQXWQL06zUeO7r/ DnqH16ELZfkt9Y9+cxFiHNVASWV9LH+ytec/7jJilZovfl+OMm5syDPatNIjxS9KkAVITSJTo5lO J2usU4984wQ3QRmJW5QHCj1tl1P7E6aVVxBnNvUE7+LbULBIM8hwbcwsnYR2eGZrV+krufP78VXy b0YVkqUVqu6QPS6AlfPLtllcBMKY7o/ahkMR0mPLUqwUTOt54NFhkGz+qcX6B+d0Via9QyD74ira CU6sVmDJkm7Ce5UkQz8cYFZRQ/w2LrT2Ed4/zV0s44qhChpbDKHN/XLpG2k8PWf3IDInJpR0J/HR NCkInRjOI5skGW48TGGODnJpfi1vUawK8EZW4fpSlSQO2GYUaL1YmiyECRD7EfD/ag/pW5ecJHmt UNqo676wBpztAKd5JcFwFnNLA+WXgotD1W4EbO//gXt/rEJ1z0S/L0CDCtVyJK0E4qJ9CQE8NxJp wxgdNgL+Iw3C8MRK6ty/XYIeFSvudQ+BWxBp5ZVdnBYAGzEuTxES5650IFL17dwAGQ+aTywCXI6P adhoH8ADojBD9cN8qOaBoLI+xOhY7BFeCrsdRZELLmDYHNgSBR7P/iMoewh7mHqVkzdXGq0V18PM 8fR2kB8odtL1WYIzgeoJeo4lNfL30glLNQhgEQOa/eaOJnS8cZHacut338uG6+8Fs2FEjy+aFHJY ETIWZn+hnhvFaZLhTyqQM9URooPYhJ5Czpj/l2RvPed63LMNULVRalShMU9+jNbPxeYxYOTzQ/rB f9krblIuZE3TZYYPNhwldp4cj0ggSkjdf28lF3219361YkXf9J7ghLDCxBk/WzcTJlWHmRhp/np8 mWRyZsmsKoBzBdCamBk0p4QkIpJJRvIZpc5+Sso/OffOtwyXjjtr4hYCsIXWPRAz8EjxUTshP2QR aSoKIchtBRHpA02q1SEmWRSs7OMDm8uXxgN/VaXhaPa6wCqbKDL0fk8tZaP3xxSWKU4vuqLutX9h Dnm8xXrdk/o3Kvy61T8s3WFtVYxP0Q/o0vvlZ1Hnrobw7HxUxuneE/bN1QDXzGVTu0UrlGYd7Bpx qtkkAr//N5c4wlMGrzT8HYPzYKLG6fpv3sVxoRPZNmD3Bxc8I0+/f4F+Q87NIisF/zU0qALx957A LufULMilHM1kCVN4BY7Q+LB3Pdn3M/bZb+n3vzJ5dqI8PXZs1sm2Ryfm672gKiOKHTghStPmrMzY 5MLrmhRn7QFHYv6u1aQ/9ETQDgaLrF7RGwoyVk4x1cdlw+VvPLV7BXjUjPsI4e594MK22t2/QiVF tspBL8yFduk1taZhJ7PDwB+bm7xTWUWC417C50aOqQ5H5A/F2m7faSP7g8kRlqytknbkL5pRol06 MeBV1jyUz6DuDyf2plkgn/DDOIxUdOIw4/YyJv1VZ2emWnkTKlEh5lCkVXy9H5mYTKWilBQ9zBAo lUsNnDI8aD4S3z36IW7T5AuD+NQiPyg78T1QiwpUuq9hr/2ocrU4vhexSz+cP6diumwEQnzs97R5 p379+2H71G5pQQEM+KJiB3nvMG+d7EqTDH6U+iLtCpvbqYCscGkAvGQ2D/uwrK1I0xFQ/5HM7QPS zUTJibf5t/XIH4mvjKmGobAbqZkRmPxfCdTk76wwpy8tFca2/5yLehDfE773G1apqZXK6DuDySNo 4RzwtVJLKjuVl+wBts4y3dqY647qoKr1lWi0Nyl1KIH/Cn3Efv5/L1XjjGj0L9UxsXpxNcQbrZoS tbnc6s3M9h1YhYkLknJggmZ8y7elf5iKpzrBvqdeltXAZ5SD3xr21im5/RCxsOe+JA9ORkzw2C70 eAsPcBt5A0WqXqSQ2xbvPOXHrzgjrLlU+TXmAoCFM1i1El0Y4ylbdaLusiLdAM4uwsPuc5UCxoy0 ljVYY/RFA7wMbK/JaiKALb8gUpdmGTs1wfJgxKIwAM8yZNS1klu5fJ1HY7JFsqF62DJcivymTMnM nf3gCJ5vfg+LoAStQKYKCgP4Xv/jkPavOJ/SL/cEclAum2Ykz/HmFCBIC+bd8u7yT7W5SePoxJEw KEgCpNPn27kQTJyDgYWF4hHNLKf2E7L7AR5IHw2c49E00gwuW1WuISObl0c5aZgltrb60GsYxvEC knKA1oD8BAUfNFMGNa66ej7jRlrbbzMY2L9hdHMEA+p3VLEx8Au9b3I19PjOUzPa1FEeFY7b3tp4 wgDW8yOEqcLW1nmz/8mDKQUtm9MM9fAVi5DsVNfKoRhf6uL+5qK+u0/2mHJu6HMSoSBzfpWpZVNB i+otpbVNBOrkX3nKfwMPhmFjfkJ0nQ81rcFeO2QUUC8LGKal/1Wsyw9eIVanJt8d4u3rweSnd8/b eB4KYEaa6pIruitbg7RmnZOS8CSb79Ut8NMGoiOl7LT3kQnO7/4fgg5VNeVCHobiXVCEiXEQWrSb XfImRKyx8+zu5otLSggxzNiym9h2v8E9ivBQsbWTooJjX7+2poHqVzyVTn4HwbKcAksTBwWPcpJz GYEH1RIvBJZ+iqX4Z+9GsxKOs/J/FZMwFcaNZM/BvHGNfgQzN8grdFihcBaiiTZFf3CvN935mvSd wwOsoLgCFZsL75LDt1vmXHytDMPpPTQ0cDv2U6baB74MBU1aFp4auUJ1gg9INJZswLRqEPxjhxT7 pvqyXzxEugYYb08I9PIKRTa9WsC1ZU50HEcNzYH7YB5dMbYTVVlQlIi9R9AnN697NzQLc4nOImjK mUezr2B3YOd3qvT8SpVISiZb5PTFIrqUi/SCsQNuQwWZZa/TD8BjsLRxARC4twUHG1XrBIVR2gpW 8pFuVJZ4+5XJZcZqu7np+fxFzGx279Re+CRJ6OzDed6LvKJoz3QHpJsarYpUJN/ZREIuyLDpPsDO ju/nMmkkhGuBK2E/pLNJTnSrNIirAlWWU3pEyOTM+kv/3uR3mqrAPPXMkHHaWe33GKulRioUI+jW syslOFL77lyYEc8gULqjJkGD1kdEs+aXCjG/1D5RrxMQ+sRWLnyxWYKuCQdk/3emZ19XI0KDph/7 p23cMw1QHvd7vJYhcF041ZaoDhoeEaIJ8XmYgmNI9PUc2U3EiwV31U/uBwDCpoYGXGyojA19pwt8 ZNHUMPmI9pSVYYY2NvpsBuX6+koHR4SYS1YiXSGo/CLHKYWoKE/swVSeR9R2J3X5tDHa9e464wgT aUd8ArB5HWs6Mxgmi+eglAVeIwYmMODHD/0ERj9LHA5AOBeeenieACCywwu3YaHgqUVLirc0b3od QbpSiZdV72iCzUxKiJF/nnCPPeL4WmZ9dggPJuWSa4UiiRAkc22NHu9ZbuATZDJJK1xY/KLM44c0 19d8aqVLkyYr8XJ0VxCpfQtoEgyGL9BNW+E7Y6rJbzOSC2RPNW80IrIfSQ1Jxahd8mQDBGIjgz2B LSa/iitquayrmOMwY1NnmVve3zzW1f3WtuIWJFYIhGGnx345jyarn1vOS3Xj9p674sTITMaZiVpR 7pI3JJ9U/MWkbAjTv455xlDdsFMXDfNVs9VkRAwqaNx6KtT/VNytZqyUCaFRSDWsitwmQdr0kSif IbwcRmuAxF1cLZgKgAg7qBKCva29KuARigz5TcIv9TDuwnFZxgC9u65AxFtNVH3RkBvD0rPD77pf maxYisgU3WJOvCoYRg3xJ0BZ4nTGlrAS2gqqMLqWEKTNpaF3EHZHGOkADS0DXhXHqOOjz3S98dAo 6Dm9WcOvhv7d6l7JsqujYrVevdWtzFbSuJAYSaQIla/pOWRqAsr5Z+CutTwQX88MWNgT11jrOMkM sI1ZpRGpTtisritvFIxnR/2l+sZwlW94qoj4pgIfvW6DLQ4xMKU3TSvp9OWCrYu+YLULCZbDIwVE xIaI5OEcOAJG7r0SZtE6X12Yt74R+4hQcE1VJjRbrcQrs3v5gJ63KrDQnXGr0U/9fpm9mwxBzn9y 4U6iGmw68kCfqv94cG110M7TYvBVexdMiRYH3gE12bLE6aS6BWXq0uS/ThsucyScEGTXRQQicIAK 7IDvIbuQ69ErdJ8+JTZe8hKbfGACRHuuogoL8yxY8Qmmn3p8zSs/QxPfARNH6NRwP6xd5QTWRSU1 /6F2t+CPp6Jdge12ieWnJrYdQRPsieOL5QtMOsLTltHt/AUwRxdsG0NTvdY6sH4daZ1JrbPWQZ1e ba8fjhsgT2uMXjiai6sM9zvbXhYvc+ekq/6EnzOJ4SYZj139ygCvK+FsLxvihrWe9wp+rhUlNkai ZhAQ7AhJ0He2berfZrFTPCBWNpH6ey30tkTo6FzsvvCdXnqiBcUTaPc4dKyVr+WJ7S1ApSz6GKH9 MCgyAnSGAXw/J7dbl769zy+AUeTk5bjK54sD46dXM/2tRMT2UtLdA2KPHrkjq9lBh+39412Q+pyQ mOZrpp161lq7/lVVz0nsyAl48sif1RhhAV26x9/I5vIfQ2oF+WDuBIZoggVUF2cQ5NrdW47tTzD2 0cncagjmIgdzMTSGXsgnZRW8+NV0dN4wC7PWxgySUYaIEwmWJXDa+cbnfe1vUN4XMrDHvPY2Q94g ymEPVfCj1DPMhxsdKJteB4IvgCisPRUBAlOG5rZvhN9sV8AkokorL+2bsyq1RvyDMVAG52zGuYgs Yk0LeDPZt26Qp/lKQlwyd7S6k/Z6l2kGfkqBAyPUSNaDdyVUUJZuRk1B0XW4FsxAMfB9SJThPrq5 bguvqBKfceLelr+Dz/qlXIam1Z0ZeGXoh/grHfJy8Z3Grh46CXKlYFAECzSn3qBmFfgNDP7IHx+X DlAj29MklmzDJt49muk8qRTiRDBsQ6Ncre/EpqW+mgLvGWwyQS9uvaAkOSHewnijoVwQPhJUzG8g lrryRx8V+m6sBE0N7OEiUT2FJofYL62FpV5M8RAAUzbQ1Axnz+qoy9sKUQly2sbPrdb9Cdn7KAek p4De0gHdIeI1gfOcYC9m3IrJ+zOaarxywNN9nMptAgCmzM2MwVO+Jw+Tdd1OR/vbcIICIhIo2doV vwN4s+HbR7n68+v/jkG+JEBoxvpPiW6uDtd2pDR5tsJqwHrQWsZ6pvJZDSUwkj4XSrCZBhhwwurz O9A2K0VNCFfR/2YAP0GcnqKD7G0zqqfeexODeCifmWoKvryXu+BcBGnuRIpefnlhT+in8FVF1YN9 ZOYJY89AuhdE8DW3mtEFyPpyEdghzBmt0LhR5lUHj9JrY05fyD8TCV70Wg+u7W2Fe0dKLUV7Ki/+ kvPPb7V6EjWAFIk+MGOAv4o9A7SzzhWs8beqhYfAObTEmDEZqa1gKUGcPnJJo+y4qPYJplmqAbLQ 7+uxBNRjqoYYCYPhq6bdiKY+lqMWnOr8cCgdplkYZKxrbIyCFO3/8X0b4CzoumCs2fO5EsIceGQE ImryN3EjWshlFGDnocxKObgxpsKRPoGDPVJoIhfS+8u0bA3AC4TauUsKJypkyohhsEEU+Fcir/yM uamx3cY/LwNyOE1JqZg0fz5ZeyAxLADrLGeUtKS1IjzWTiNBXWeNeOx48kk2L8jThLBNqP+UlZYk J6MoCz3puRlkf6pC/v1dnvJvcLK0jeR2dt9EHdz+joD7/VoGXA8CW0WjRuE9JypFb97D17ZZi9iI 4z12ubW2sLjwei6XIetG/cGRoRCmGjp0KA16L8XrrlZclGYtIE65YHw15YVdwFZWLbMTKErOXkQa MyQbduPRSja1RMfVtN9tIg4HMXMcUZTC6+z7lKRjx922S7B0fHkAszrLZdVmhCKO8WzvTOXRG7an QbWoRzU0hVZqj3xVe2VPBePUFEfD2nHTBNUHjl68osL5YlQpgShYk/1eojJkxtYZuOMVAiDgYfdM l+LAphuHNK1EQjchqQRaZdV4m4M/DVakoH8f3JOi8lY6HQDeB3VPC6OMeGYTyNx/9JpvxNiY6Gd2 ck9XazVm5BRSauFViMRvGT2uy627TiKMM/JMtTKCPUkraQM9ZoNNePAVW41eze52GvjONGrXFkrk akjotj7v3x7qG3kUQc9Rd1S8qdq1T3Pbz4V9X/lEm6i1el/NrTcVrVQWr3RCxXIGzG1brM7BH8qp tpO4C7xfstbzSvgxVWtxSLFp9iP1QV1BP9uJ5KZ4yxtH/F8J28r5kDGgxwszNvtH4+FfS13SBKuA Uv64P3f10hddaZJIMf33Og2tBH8QE06xOhFKOZEaig0wnI8f4UieZKZRUqmQtNEuAiGo5kVQKBSB awFbyHqyje58KFujQxFYYOmv+5y/RcifbaDMo0rbI4cl5WYg8QQ6+mbSFfJRU/yVBjEgy4FZlRm4 0hLIJvDwRn76XySt6LRXBeDb0tCmPPZEkCSe7AnVsbG4R/UbFt2DKjKbl4URmSvqzQYeI1/fw9Yr xRpSdi8P8CQWgbKCt45eINwGzab4sr7cSOnhHVHwMdGARVF+FSmX089gP+U+cmQK+8bWgjeucltf 89ZwZNXNSru6dM1S/KwBkBh+04Vmyln5SF/DDM3PuSXhYBl5FPRv+BxEs0AnP2+dC3Z60ytddep1 iJFCERgqzsTG/73OBNeGZi2D+hJ+Hn70qKtnJy3jtNuq7jPGgWM0ifgj4DVL78hzOb3eUPQy1M1W vRUQruEyOmZf3FAwNpQJnKEm2Xf3BeW6ajE5VkIq0M9VDFEgtjC2wuRg7v9vc81EIIuIhQYtktCY 19Cn6E52ToW/pmHsGujHwgzVpaQsTvWiQlo9xdW/IBdKW5LlJE7KdxsCxZV46+TGokXVVuByXnab ky7XEeBEkFwtLPxHkEcVoE0u5oAbH7StocuhSuj/45c8+lppu2csOBRjeRhNU+WP4Ca4nmWPUCTj qQZYcYC+sXEsy5E7qFy9GvPqGtXAUx8fVsG0OCWEj+qERsXfS5gMM3HK16R6eQtKuOCeV09A3EkW +vM9y+eNQL8dG3Fi4SuKjdD5ZyiaZT7yRw75YSy7euLpbBu9JuVj53tl/wXNVLs3r7B5w2+8KPSy mWyVOI4FLGN9wWyy7E9bwaBw1VRmXECID8mllSc+e1W9DT4OYJE3gkfjPHeAe/eh3kb/tvb8m6zQ QDQPrN1yHJP4CoPX+dwr7Ott2AerFjgPgMCmPgXeXe4B3d3VNctfvYVPcChKZi3OgkIWJdLjiNNm h3TzngBkmOGbPwv100TVzJcl7gzVHi1B6DbV43IwICvL4Bv5ljKfTHch+57iXykuz9HNTUcpJEg9 l1gajgzcSNwU3jnROTUuD8KSfwUHMwQoglnunc9GQIDqQtxCqzLvGPuQf/WeHxgUHFY0OGw+/SYo FaFBA6vX3d0T/T0GvV3GCNWQQ0/1IZ62AWedi/l8CR/IG4ymQ4q9iMQ1kWh46NY8ujo+4c3vGG9Y rWj17IrnVuEdMvpfKBpvifAYOxTk4f90xGVgl0srnhWjFhWJCKODlxaFdvm+gSnpJAoecINNyM6X h4xtsNbzGa77eDLiWc+r2GcafI/l+F9aTTn40OdNJl8u7lz7MG6Hj4TBgAWGXyrboeMP+Hmonwyb wWMVRuqC2Fj/X95901o7T73hJJAOlUSWuor9ilpcIpy/bzR7Tf2KCnm/JS5X3Thd5m/KgcIzzxiP 3/gb9OHU2y0SlrGcqSDBkGTQvqVjEtav7WL0noGT3C54XiKGlIbbytZoKNLe5fbJY260WBI9EjJ+ AEkGnSzYXcsjjRv0TdedQUOCrhqFMtS4wXPQFx6M/VmBiMrsF2Uaa7nqfxaRRsyVj5ih7zAutcYc ehrvYTJous7+AxAotI97YRYRcoweGIwywE3seKuOia1iroengMLFyb9kYZOQkMQG3/QPL+qijt7b ipOPv2KK+aIn6XRCdgHmXOXTuP9uhPiAmYpLSyqsQsmnl5+kWGPgsig/lWB46DiJHyGlJ0/BdCwy +Pm6mwINdDIPWqAu763b2qhTbnYdu8UYW+5m4lSWf8l+iZbZidb5XeSPg3k7IqNDKJpH8/XacAgw G0yC6xiJe7IaoqahzZzsWswmrjLoTIhM9LbKFtQaza1Ntd8+BiAVuoYAbWbM/AnWLUXz6rqudqzq 03pICqagICTZS/0R1Z35Qpyl45SJUOh1SS6WizvdBWnTpvNUzeJt5vtCgiPxuevJNkcS3f1//UOU PKpOowqBZH6c/vjg9u2G+0lVQc6wwDGlI62yBdejy0uIDOr72Y7e56xe+IloQAMckshvrrtEOmA6 0mKiCNdRVsoOMKH4VB8iO/0ZRtU4x/cvp5r3FYviaG5/t76Silqzz17b8u3HHVXXrTQnnaCXmQGc qydebcQ2IcCuFInPWJmDKCVHYY2hpXgYohE6x6uN30Aoz4j+3sEpOlxq3T7OitRYUHi/KOXQQ+NN t6Nl3/E8t+YhU921JnOWSvOFPd+LfwOBXFcqQSTfEe2rO554H9m19jMUpBGrVuXH7vePL9ibIYQy Gy39BB05M9RCvhM1L37KTtkRfZv/M3DJ7VgyHAYW6TEFjtYA4Feut0m9fJgbyf2BhFhB/7Rs8cxB TgjXxacFR2xRLP1T6uFkGbvCZDfllnhqqIhy9dp1gNz0XKOBwv/rQhrSfP4p1wfvapouBg01O71h W/oCXDGmVKVFcnCxlWOdT4z03K8L8TKqnGZ2gDc2UDxfXbIFhNLM1+EUjedcf/wfyg+Iaoup9iUV Pb8f1C31P2+d8IOmtDFW/aKLcT63oF8xgMIQ5kDNDf1cXhOAsKqahR0JGmmjinJDgQZUh/8xJSMz 8ncCzHJmJAvJR2SQc5Smowi1caGTYSrDqIPmMHWMCUSSOkhDKFhMdxz0YEsC0qleBQtyICVWm2IM xDa6DZvDZQ4GBGuPNtBFXdTiFVKJrhpnf0heLBsAxkBuUbF0BhZLm/asrAX/emp9eFl5U/pliQQ/ be748yAL7TtinA5NoEY2gCsCPw/vpr6D1Tl8BTnUktJQfsJSseuH2gcvM+6d78Cfji/+meOLHL7m NQO+fBrdlvmZi/Jzt+whMwM5ZhxDGgPbllaNrEg9siYK3NZCZ9IeadHUg6USFU9oyWwHrLxrDpvO ufoh9QA94CDxoDpN9AOCBCRdbxHYvOkwIACNupqKuE7IPIM5hP1WLT2hUQIigveMYruSXIbz5cc2 lwbv5pguB9eznThFkBfoYWfpWHS6PDtf/yRqD/YsSikxSvm48M/IH1t36foasHtH8Av5maQeAWdv WUPt8J5EpE1vq7b9/mfXiX3kFPrse31lSKOQwkxg6YdajXLYjbxokNf/JBgUfbwoS4E4oDhrocTV SZ2BSCiYqtq9sr0eEQs4zvY5w1UR0zCp0fw6EMA/Gi+GkXyR72BjD/h9pcvElZg4VpebVZSDeDLF 0/sEiYko/lLI2J+82jyIwfdIy0wkwHUe0gsdrzlKf0Yz2NrtCMZkjjv5llJFgagcfSS5lD1mNxtS W4KY1qkjf8BdFe4q98WFg7sbnpybNL7bTeUlFgGRZFfFKRFYOfAKqFXvv51laNJlqC1hzuLDKVl6 ZPj9EuTAvaMmRNryR6bKHC4A6GtztdvgCvK88XEiI6irfRhG07wqakIehn5Nk92iRR0e0UdMYPWR qae9UPpViTtCyo6GYP902hPo7yvozwxtoKZvvRwNYP6fviOWHfyFvu61GJ1prsU/rmo2RAbNVWhi yrJxtbJZuHcRV3Z7Roj9AjFWPD/CcDIo7nKmxOEJStSBXtEvAJEgGnCVzEYFNX/+PkAHxON9hdxr smrCMa5VP+Kp7IraLz15Bl2lb29wYUo/9loS++BWMm5Z0d5kdzv4r3AOrhy7LZ26QhncntOL5kd1 CiwdMbsNkfnrwscqHi8g5s4ojWWTpskA/T4ekWj5TthdnbWy0t8KbaoWvgWBwqZr5o6v4HnPrW/J uoXEvNZ473ASwOPEqRNqQ+SlLeVEm/aSiyi4z4xhn1CNhCik9zc/XzJfs2pb53SkondFMWGpsR4m 84GgGc5wIFoVUjcwUDclfL2xByM6MXMwKR4z1sG+dnlMZYUGB+lkwupDW5xNqdlUEoxVcajmYlDv mrVtaeXhNAin0u6pOCPT5ofhFbyQVB9mAaAR7f/ZGIdWt43x7Pc27aX6Aa6P8c8V6lb3QJ396VNN 1u9HiN/ywU2SU2yV+7J19l2M3FW9B48g1bJgGLI6EsNXf6sLQWs94L+nZZ2yAu9f4M6MzPEF6+E+ DI9skMZfnbgz+1f0//1Bji4bVZtJWRX6Tpo7h9qFiYi3h1VMyNk3uKqGvyMvjzeW/vhVbre72xv/ umJrFxV5pAeQ5IXoLdWPl1MpvbO6+7B0aPFD3Yi8KlS+nWW/PW6RMY1IaMdhBU0g6FcpHiTEqwQH icS3CuqvOerSkdniXboBC8llqmQlpgymLB99445lQ7LXy+6T+rxqzGG76DjV8j72+Fv+lRReSUwy n9TX9mxrXyv0+T6eH4D3JIfKD83g2By1qAJIGo2+Z2ZlRVGBJic3HVwMbGq52wFIMM5i2UIzHgoN Ei/VHQFLKiTGBBhEyayJwDFeu9WezVibxW0gNZXOAYVbDgltbKjwbYmclogxPm6yJAk3wj4vjwfY aUwEx3S8sP0yySxtLwVrawhVkDi3nEB8gy8h6hRwts2W9+X9jImXQcp1kkcouPf4J2S8M8oJ31sg Ob+he6XOCj8bQYsvR9FLmhgLQGyIOFZdsyru1T6wMqF+Y0G0JfSzpFuipfRwBP8/oAbCiq8sC6T7 U9VsHFxHXh4c8+Ozd65JWq2h6IdMizWSc3S4Zh8tyqiDgoRq1y9feRb0Im15shQs8WhGdmHwWx6U UngO4UBkHYB6mYV/RAd7uI3/Ia78hxj5wqXMNW9rsOBisp19fk1YGuxLl9WRidJp5xs1bqv2+5ME COvyBScinwQ5sYOG3HsUCp8xvI7IxO7YoUYnn4xNng47eL5x07DfCvN8RgiXwede068/tBXvAMbu S+gTG5EJJnQ3/hu5NIokqwKcd41Nq+U+uEglWS/AJQ+S0TYofj9tDxZAcK/r2WZNAUVr5+6aXFz2 J/E221v964+iz1qcx/t57YTdYnxWLJeekToI/IZ7jinteFjAxadwilw2RZF/y6ZrzI9ujuOU3waA 5/ix7IfcC9rn+jtpfEw71qXrjzJvHsuAtQTAxMoAUQty5e5shU0hmRoOEYdLN9OWZmlAbh7wO3k4 FhBc6ZJiYiWjq0f1orgWRt+ilNyb/Fy4+uXe6XrvySx3mJJ5Wy8NJxgmKP/XWXAgsJfJUVYch6rD zBrxtANsDssp2lA8IrvzCvmty3iQz3Hv3xClBdW5hJHj2hWY50gaCzIgspntTRVRO3NEtA7+7nHN bJepMGUoRXoFq0/Cx/csKzXgIf/hddibsT3c9p3j8txs5i2y7PI9xllpXocnmVHYaSqeHJimEmeh U+vYrW3UYGuEXYkhU3AhJ/vE/ouboLHOhPWW0pI3x47r+kqMbg99VEDpUg9+jk9La4Pwa8wtDH9d Bt76gHiOxJgqHINu+91wqcahDkCALo4u89VudqE+8ddPLCUK8j+pqFlpHWskAiLY0vVPaJfaXWsh JPysgyqXWcnCNA5dosPnZWKvAeUPuFxehPN9oZZGAlLVJHuAk/Y53n3OC5451k+zsqUjN6Izn11a RRNDq17VRuWMDul8yh8ysoXtJGcNwStKmKnxki/dB+dsroBnIW1pST9UpqR97RKhbQi9EAcC7J+v hKS1+GPPVpYP21G0BWEPLSgFNNcDOPw0t6fvu6/2hwuVe3RVWFYARNR5p0voiVXFGs2HBrm0Pu4d ZSAu8wORtialobZun3MY9oWE94t2yCPRLCBQnjlDdms60alo1JYYB8RH4Aqleb/hl2B9mHf89mUC ovHA0m4SgMgLBTtQfpUun/Wg1pk19oL3wBptABgQTXJXkhxNS54RLxb78KleuLZzJhqWfPt0liDk nkwYzY61VXCWUtVTxmJT8Kyp6IANR5eOC3m6NKL6bioU+kFK/wss/jV42kdthYzrPUGnoSPhR64+ 1aldq+HCfJReK0kqHDqodXrdEFPnRuwUsIRcWOP9dhnitn/gYbZedWoU/1Vv6sp9/DiABPaZWs4R i7AmD9XTedIUW0y5Dqtwe4HQ2eoqtiD5uOiSd6iuJtMtBHE1JRY8RhkHiCj++zPGpKPh2Ftb6dKS 1PSvqnMLq04cqsTTdd7ABbhYbQOi72uwaIUtXinVfCdDnD5HBvK4FMiczAoYM8KZYTk4uk4EnFC6 4b0fG2n35x+9Gz+vWKXSvmVNaPpsJA3AlK39bDUxItaRNuHvKnUv9GjjHJyO09N+wcgK7dTDEjur rE1+Prw+oUaJUgYsKnOCdIVrm9WEZiIy+oQzj33r7FUb5yFpedWvFD/iWiQ6fMouJMa43JqR+8zd /7i/q8wR4rsi4qjQvkYOMX/o0HAx4VNboooRxzf9ACcjbgtOFzd7Fl/kMhprIS91hAAm0QakOo+k jBLNVN4NZeOw0iOVUl4iOj7422aigqUk0UeK03BwrV9+9Jg5twRVJW3zj6XaVX0TA2ZtvE7FRKI7 hLzBohap7EbqZCFcJa3HrMynH16mj/E7nsbwyLlapwM85rq84bjHkKOKaEL1b7j/s6jUEiduZgEU kLUwjrc+NcqETsCAk86V2QlJzO3b1OJK3XvVeonOiiAGKnCKFmOzuwLJxsAoqAQIGuodd9vtppdn NS/BsZCuPrqAchkCRGQ8wHDvYqBrT66TSAEktDN47QaH+WC3gCK4hlnC7uRZP0SgweiXhjkhbk4s J+cYRr4ChIWpc9iofjskI+y+dTmjKnKp4Ttdcdk/vgwafgBqWXjOb0TuU77P5kOAjs4kAJJqeRjw MsSHX8n3B03k/i3vI7oZZAg54dHJZNr5ObZswhL66ATMJSTod3l6dULK9rGp+PDRDXjrxzVqQutP +aCalU9rG9/fwtV+jqK/eaRQtzWTCZtW8zxbhjzC6xwyaoXz9T41gf+iG/Z49yRm/ZxrhyIC/pK5 HtFmYzX4KsPKhQs/1LKJQp7TJf2GXzJxbtKknSEe4clk+M33q2zSRVT8vN5qHMcVENgQenKW9hHK dba7l+SrAbIL3r2i/OPRZCCYe9M+kTZvHu2CTGNymu/Mm0ocwbE0kFt8Gr5ZZnPgjur3iLxe/rpx SZaolNHKGDo09pFuxER0a9s0Ey/dqzV9ShJuDKzxtT38q0Um+KwK2zqEidJSGu3FiIoYD8uh11Xp vn7/MwrGepHge9vM2fwIxke00DL1sZuHWJ9L93z/sSuDbotkRHL13ep7D6qGbxdCMYOrB0vXh5YI 2KGzRzIPVJErb2gF7jmO42Y8AtsNiB86lUmTEH6uBMrCQlKRrUeBkgJMc70qWmZFUus6bXJYuO2V M90Li8UCkinY6O9O9hrSGPziTPy6hksfNIp+L70MwaWiQxZql0uKjEW/bkeCpsoZFCa0efuOZO1/ Tf5+ykHiKHxyuvM0z2A0+sJpzdiUk92VEmo+0V/QL6XfPcNUxJItK5iooHx0WsSwRyjCYqccjhWo 7FWmQ2+UBQG++x8Sz9yrNOHZLWfAX09pVwfyhnF/OEgvUUe7wASxJI0DjYTbtMgixglat49aiCxp 5WiF4J2plpe96n8id01/o4+o3MweVdgzSbKnqt1aWO7yD0ZHfSmsEtiQoBoPnFNL/pOJ4oAYCObf u63eMZ8zkoikYbSI7R/5iy/Y38uHSYvjHUwCDeZh6Thq3HCafz6fOxF9HXYg/9MBTbp90JAviNIy QLnnPOgi5aCaMUbwDWjXMhkiN0FTklVjvT/2ILkavaR7nmeEyR5gbuxsk0MF0BPfessdk6WiExHY SZNR4nQWFNxvXuHWFmKuP0HYVm87WoAcnyURd00oSrJH550NZnv6be6Z/8ZzkI2fJoym9XKNcl8w JTN0Tf4m1+afImS/biLsqn6ZGlSGdcU1acQ6A6h36jmesM8Z8HFDJ1V3Pge8hz/+WKkLaW+2UEhM kNjGblptVGd/Qr8FU2EuHTqV5rm3GakYe3iZSbZRp2Ukc2hmsVOoB7yW64dT34KtR1NyxcAm88cx 54hnZ4BP9jTo5zrrLXsWKeEIA3YGFp2d4dy/PGX3G/IMJgNypWL/1qDFoCk1Gno0nhFFlVISn7pc OhkCWlBxOFyj7l/crIfJBmr0UnxP1HsXbfmk8WPbYvgiHNOTjvS1Sydkdt2oaqWwr943rkopufn5 5LR/bn9noscx5eDXLkPalAjEY1a3Rgxh/oG8aONhi4ILldP4SC/trUDNh+BrFpBOpAc9F8knNZ15 pE9+vsauP801fz9anjnnMy/ailfhtSO8dwUA22dbULLga20HIBY66l9Q4+LhZK0BSwyXCeCH1QM0 WD8Xv3SHvSW9PZuHvVFMxvtW1sqR208UcGbJ+EBtPP+sljvAEAlj9PxciO+a1hTTQbczyZFQePRL AlT+y5Iic5FZ25dvi/T7iwYTSoDXQP8LZzxquum7yzE/XxeyHXzzrqNlvC8aSqC4V9wki94+3dyp SNv8HdNiIsNtaKRzVVZvMgeuLNkj2IDuTMxZ1ndpit2SANlNRRvuEzRVLWdcpbYXEVKl8LlANMkv KUB13U+mUEPciyFG72DMDEVNpXwLY+AZNmmmKS0hCujH0lb8SjYNy6b79aVmXTY1D7YS48QJiz0B FOr5XjzWUQT4ADBLeM6KvW3VKPDynh+V5xyPbQ7bGSpPndkj0801bfTb7zTd2XZsmq63jTZhr3zV aSPYsnHE0KVofOX4haAaAyA3gSdaYk0kjO7zZc3E9PyHzfGS+ewhRrUh7+sentiuDB9h0gP2dCMr gsTfpK9rVGMIsTsVlAiS/8OK77JfINdt7/l19yinmEVxONDpOVfHi0zBjaf6VbiS/tDh0F2EizNc TryoJpofOOQIBhndUchFK4YRp1W9jU7ux3UlUnMBGaYhEOwOvzLXS4/o2QP/nNUuBwntYLYrY8sg 0fqMlbaivsPLkskyGQab0xsVMVtayALuTrCOO06CpKzioAUPc/UsFHcRzDN17HQ3j6Pb6k1tEIuv jhA5ExHgz0jk1tE58qzhn2WwUUzcmxLL/j61nKdXTt5keTfcps+Nfg5XkVyu0h7uQ8TE5aOMMQVi ZREwi+S1/b9K3vBqk7iMaSVBdYwzo1FgpRXpqxgywq1XDhbpzHl3FcxIahnZPcue9uTYssm/Y8W2 6yMPnrOSdA2AiVkfnGTivAsPbd6PbnCAll/lNP7vpZiMsEfTFR0ee+GppwhmtAVSjOY8oS9aO2xP 8IeubCAsMOtzgn5HeMoUi2jjY7211I+ocZxFQET0YLGtuqFPOtNJr7kZdlPGxL8CwzK8N87gf54C 11wra4TUqGJyg0Y+V7ju8t4Z0gaKkopOncDZgBrUasti1q/xGxoIRwpEdbwyAYv1FfSvjokT+kQf ToA+XU4I5Rlpz79RVX8iv3OkDfAcwBnxB8e1v228VT4AmuK9oqomllObsNzPJVGOexEFKMAjowk4 ITGY/PyzrVEtkKmyppLmdYzs0ITjbKhRgV7U66eOL/4AdwkqHrxQzZaia04Zy7EAojs9jfLmUbtE 5gIdSDXUon5idj0jtw6NFs2uiBV2+VXVgWp5vB9qYngt4/uv4nI8zSXPb3LKSEplQ2d7vEj8PZO9 JAY2/G66HByS8FwPVujFpYFqGNS5dEB8uOP7ms3CfcHKnJR3/2oKujsiPV4+XIed9XZN28aASgE6 7fyisT/3GDtXdJKnWnlLJEawUeoEoukwjPh/DQbUl+Z0M1chMw24wTZq5lz2tPZDRWlM8xHL6raQ TtsT/uVlXrqPbsfloPiuqvp3e40YL55A5UB5XE2mGf/SBFk4uqWsqq46BFo2P3WC7U112cSyUrFR TZuV67kuH8dL/0dTBQjnOHmX7yC2ty5nnjs1xcZ92u60UHn6I3HDNY6sgQxQpTrR+ISJONcuxsMu 6/xQqroaaOc0ZOx+55iJPUfw18QgdU25ay/vdSuH90hFgjqEQyuUsBTFkJImAb+MUZ8oxNnWGp8O 1ViKxkHag1FJgKUwfKJEyduSwyYez/aWQ36NVYywkQHTXTRDR0L7N3rn57nzaeqmsst/Noev/se7 2TTVQ4MJV3cAgAWT5Dq7Zumnf0m9k3Jk8MW0w/o+s3mbKlYLhrEbOHBxH2ozh54JHuEEFwHo0HEg Tycr+G1RlUlzFvNfLVs2pUe7NMKQQkKnCevDjdIAsi0ffRtWR0jYIZW9H+wAO1XRl+P90NGChKdH Bl3b9+gmvgREe+pqyakstahfkONGxGxNRIxOV0BXyRt3Izmw+zup5Lu0+hc3YwjQQKg1wykjqiLu 4pNcO7rs52jmQleIA7G//vFTKYxpVk/bJMWixmsnDGuRYDCVgfJFanvLAgHTNUSe1fuuIsot+3Lg V+qALuYrh5Jgz/8C1RCjbKSR2FZWB9S18syGFareYAL6dDOM+fr08lWsi00xxg9r522/EBpY3Yue vU/52s6GHe4vbbpmSh32FNZL5G8MlOWt61VWdcG0vjAplbsh6HvnFeEF45nwgnzHQUkXOxO74jbb mYkX4EI71u0/1UF+5UTwCCmvhdSO63dFPW5YtU2WvxY5cmBFsyoJ6mZ/iqaObMJvyuixnaIx6gFf aeSkD1cNImwVEVfWWi+ubzNscfLjo2/99x5IrRLCwXNP/ExoS9qWEZrJkExq4qJPMGoJVtPXFj7V Bqq7bufAWu98R2TOGw9vDu6NqKultKWjKY27t+gZ3tijKgwLsJzYhJrItBG1qrQ4TSzzHMXZKIlr 0NVKSD1WDGWgMt2kFmDmRT72j1GAdZ1frH9s+4dfNV4Kf3IoCFyrRJnE0GEzw/ykmEFu7/o/7KYS uWaSmb/qQ0zvOdV8b9+I0MiYXkOkrm2ZxieF3PTvo0GmjRYVUV847NSX2sC1LSjRDlH8nhf+kIWH RWKY4oxb6KXmNJpQNRaPdYbvUDuTy9JchpBseSkvPnrh+IOwFT/Zc9MO3WYytpRtc6szXYWkSKiW W9/Kqt6NI6qlVWSyvPQ0AcEGT59azpkixzpk5suHLIxcomxnVpUON3IXSg2diaNh93BJSv+ub8qc RpypAWa1kKqvWLXOt2FnT8gpTMSqxBB4qPF7+QG27Cpb9zM5wrLaBBImdUQ5MuibloXTA/hoLZSN Vp5LeRJSpYUTv9qxjQqcnwVt3PEXyUlAXCgLb+Ti/82GVqFbkVQA+d8KUtLcD7mNQC5+Z8VbgnI1 OQsIiUDDe/DMJ7JJ8NnRT964TLnteBQyiYwU0phA5fZNDfKJsEYQN7ZkmEcZOr9BE6SpJwVXqoZS PMXFUn6lMFQYRUwA5vXTrRZBPjIebW0vxA+orK3q/yFYDvGnYpV0a2edNiV3QLFUc2nTO2/IpZxB rH7FjB+uOTCWmFhCE4rqakY4ZSPIkEIKRMNkY+1DtbrK09vkS/FLUuoEC3IK6OytJVuzvWOqHxeW 8efbN03HEQuuFkh8yZE6Iot53inpEX5ONwi9mL8zd18IDU8Nb2FHJaRgfv6OMoxEP4drU1esT9Xz /+ozcTxEB7W//lx4W5QgxVsNWv0woSZY3mpgvVpDjMUS3tq8yeRDmyG6Gxi3cQwzumGs/p7NeZRb 3RLDw1d0vWawYakltUa3tcQSlk8xs/6zVr9luaLtrBwe6k7gKQLrs5dpPHVZBAL8rtJOw4c5NO4M eM2WSptEp9vaqhQ5w98+j2bFPUxKyQz2dTn1u6XZWe0Ts09nQKyeQW3ymI1mbaEcwDd8HWucirug As7ZMY2BjsnoGcILZquembUEf6I8z60LMExgpRrHTIA+kMdOjI8+lLim/oa+A2FN5r8KldwCAqhz ATsb5jI3k+/E29BeFfAa/lJ0wZcw716JxuZgLqUFy5Xe3vQUSEj/t/vSjV8DhGkcYVEoi/uBfnhQ eyOiil3arT5B1bx9J4xIyjHNBywD6MiDh+/34Op0mr/J78F3SKEcDdJaCM7w9x98TDKSMBTKHxoX BKCz3z9UN8OXYwciOsvmlEaY5Pg/v2UtLHzP8NHhjKFOqSv8NIfbAySBRzMKA3naBJxhUYwR2Nv/ jS7FOajSP1CcmZuaxigETBEOS34AinoJ9EosbtyDTVj+YqZo/w3v9LU7Jtv4RQLC9HaKk7MCUwVC XuDiEjD2WoUfs0hlOtKfOMTtaEnrc1v4QKSwGsDPbeNRXeDGuUbzvEXUor7Zv5ScfPQJTHI6FdbT r2Njr36r/aBPH9m2cj6/pJTEG8X/J+ALiVoXwLu/VFn/NADKhveLKRdY7rziWvdxTaAyWloQ0lsS JGIkqLOuHRKIH88LNlIgmBFtB7hHeU/PlrIghKLsA5/RK7IoGsarmPmQJTNtzaDDpb1dClIUN3Si IHy4fxqS5ayxXkMo9jg5T3aUb6DqozsZX9PA2nMmgBM+OYnLBh6zi1jctWVyon5cEYesqze1a0vT Az9P/yCslfcU7IeY9wKGM7npwmxDN2EjYQlLAZDKxfXg0OQJs58cpwoMDcDIJwicxtViL0NOFdYU zacnZMtFF6oCFUMNkmYnBjFAe5zoEUKbNBHFqeQmMiF3ySg44YzCY6PdGzBOcfpU7TbXHKIAjjfx 4iGSLtyrK0qsrCeYuiw5qxfzyib0THOpR0JareWvFpNhR02knNi8IxM/M3N9bDsubF4lmnoaz3K7 syNU51C3FB9boPG/S5pvUk9coc18NBQINRDUIhGv66YIy0ADrOChMagkvAwwXGy3ZUbPmIjt6kr2 kD4JBS0cDC3GqoT60emMpdhrFnA4cfjO7zAJtouXKq/fdk6n/b0Snp3n78oyC76p4a6dN7XuaohK otDhcAreQFuGogwzR8MlLaj235eRh1/UxIANiMPk5L5NRV0tZy5i8PYoQnvlDgIh7aOjLj46eGbl 2HDV4c00YfAaxjUHiH43wYlIk2AcD/1Aa1QadopBJu5NEVuzZbTa2wvns9v4afIipf/XCcALOlwz 1p7kvcR/Wj+cgIeZvVHGWo/6bVReYckXotW3WTQd8V8QBMzcn8MtTGIfXIxuSDfaCTLgJ9reoCEV qWNyJwhpptvBTk3pPQewRLsFpzyKsC3Nr4KTXNWqiWiEvHkmALK/Ee62lx9j+rJneTw4kzoF+4+p iBxVNHcs9X/lTL1KC8cNTEJLtoqjSjpvU6HryF1sTYF5O/XR7taqb0x5oPsF/s37hKDhPJsIfPlX Qg1hXpeIQPpOXSTXcZtIJuFlyNt0QXjCOds0SDQeWoJuu/U7zS9iJX+xNz+xhNUF0Y1DgyYejMRN UvNcXSswFEAnYOPP4EVWLT+14hCIm/S+4A1pPCuZAtfLbtyuqNik7ks2Bify49C6dg7ygrF5zbTG LD0lEt6hDiXGVSatg+ZtV516iAFPsMucPtA2c/P69vn00GluiH+WvKD+Lh87ebzLI7E5TFSDDGBx 37nHnJCvOj6zu0og/t+wlAcp4t9udZnXnriEzXWcvAM6av5TKKdZhvmYdDmQYmp1Z8erxd7L8STb R55qmdkqR99WC4a1J7h5ib6V2o1aGpPa9wXIBpJNtkIRRBkzNvr5oOBP5pjQNrclnSfRWggHIWV5 uTlT04rQEFX/QYDJzRlpnpYOhs6nVasWh/Jjp4OXcP0edFoMZZLjMA9tpotHwDx4N/n5mXEenq1M w9n0uBE8IPjEWmdn71m6s+HaQAk47qY6Pzv/82Wlha9xeFGaFehUqf6W99ejSM27rGW47Wi7xcJV P9BzQi/Q5hVLZogzznHgLWYxihaY4HX1TvhrXZaMV2kRZyivknsbis/Oqn5VKkqqG2+BgsGS/9MD EDFnNcLJ8taEIZG3p6hEnMzfaJLFoX2EVXfmCuCMOsKGj9FM81kDdmaLfLuzZfodJ4t5+NdvC8/W Tgnqbx9MHb/+Gviuj7w7WjyZLGFKBRMtCkTtTxzA/BxM88sC0PhUavwo1L6F48tI8PB96bhFAvUO u5crPyhYpsmAP31pxWM3LmY8mflmuEUl/X2XrOgn5lji3njnYqzQwm8+bH70mKuM5vha5urkTwwQ 6zcQvtQJak8U/QLVuZAkfiZHeLywfbFftr20/r8wfnvzmPeI+RAZ8G5nalKddAN/tlylLPwYEiDK NGBDSVvkBfWPmUJyxlB1NWKDISN8wXKbTRAD4JY5d5g68rLLBVln4Wnu0RZyIrgWfs5n8mlAFOmq e+WClNYeFVt0ZYQQ7PyHt5vyiNYKV6gbglx/tsPxhxF/yYFtGSF4frQPg1wbQulhkFd+pu6TRBku PYhnsWpfiNhKwES86XCAsVPEwZQoBdC7IiRjf111iCQFQvPfjUqBrNZl9MvzcA9cbGoZPH+cHz9D AmWPRxdFKbDCA7K/iBtiP0WYGsUQrLFwVGw9/52NGFOpYde4KUhSDcIZ5yYZPIniOrhvbCIWCxJD ids6ppAiUNd/i8vE4Fqfd6ZrD0f1RErevu4cWsN9rRu1jlGUNBO8BxRRudxgCHh2/qzl89Wg9zP3 E09bWqsjdZ2tHZDf/zLYgOmU29t8ZOVCHx2QHoydzNVvqaf3ZJrVSKJ0cmi73nctfuSp4XEMN2Fr lb6wxlGylV/WUEHoBoq29paVKJcVXCxc/sNq9++vxHF4R8jj4GSBLI2zDnACgCYxgFJaZMb8Ycv7 S742ELy9UpjAE4Y8aS5XTdk+B1ekQPs2GZtGLYJ31j1PIwLr36Kf6trFjBjPxtjuDmXyi4FW6mIK BSQF5j5z5WyTPhexpL2RjKZ/jHbLr30cd7y0JSuNvKTR7Jw9m0+Xkj67yBIISFb0tt2upnVyiIoV LOgqMezaQHte/7Z/6l0wPtAF6plYik0SI4VWRNysDVu/mdnaA18erS0sDUKSEsfzmbapbBJbEk1A ManysZ9hrJgzDTJlJLXTsCMUBTUqIuRTWjsA+M5QCgva8cvxa9rDWijhEfhmhCFsYVxHVv4UJ5G9 J0QmrupeBVV69fyEBRA/HV24qtE0ARMun00mZ1KXWgTCvCXKEpbG8KLqjm3vD1OatqBX5BqQr5Ve 640Gq4pWfYYV+orEikvP4ScBOgklYJxgneTuaLrNmPDeeNPlyNLBxZRMm7lqt/hBYpRiWa+FCTQk uBfLdofT6fPSjlaVEO7Rbaiyb8ymJykwX477xPFQjiwXBD4P5wfM/+beKSaxe2BsK3o8niKJu/I4 8elImV4s1drTGzgv/0dVMFnfb+7kwR2EnhPkTDmHebhoay0gukDuidQs4NsTtLuJJFD2CwFJvA4O 5XL0id4r3hkkNGw9FKiLN+WxYwkNORL0aCTePlOuC9pZ1HKZT8I9ejkBmQ13Q0zaoTdGU3zsnV5s 4tqGIpTAnZcCbF+CIS0VKKTEF7FMplYDblgMUC93H1uFax+cEIb+njDAV276nYuTVLkOwCxtZCyn N12y9fAmeFqamZ2g4t/LplOL2AvqfgONtGH3EqOT8oVbiue7DNAFdtdcwPV9xMFxPIwrUt6bmwvk xMNRMBn4/OrqejycRhEybd3Ywm+B/woBdiLr2Ktw3dOXc2iflDYttFf2ws9DqT3uadZmLmHf/pUo /kXoFtTUPHt6GNUgW8XSloUponHW9obMsYAWpS9qe5+G51DLSQVDlxLpT6jiLACfVnPZrvrS6dm/ MNwyzR5PrIJMrDLdKhBZJqIzEO9AAU8jiXY5m2Ka7UMRT5OD6WeukwdL1okJQt3v1CzVkHc2wT7+ g0TTwgiK0EoNZUSwV2TdttzH7709amBBgIOnu7vzyH/6SBfMykGu7Vl8H6GShvRlw+/xrN7L46Bc abIl6d+pq+exwqdFcvMf0EvswOw+MXWj/bU/7tJsdJor6V4OeyQU2EjGpedbYeiF2r/HpdZV42G0 jxtYYUOwUJAtPJheXTmqRA0AUMWQitVunA3PAedGBNs2KyyJVh+OtmDcixRS1PshFxW/pO1Bbfrf 1UxN4WqfdpwCrO5MVpa6/l6indAxqrzQXqNzPkaY7hQ1J1l9JePTV69r3v3W1zoMP7O9tRn6tEWW EsC6NoWDV/9FrVsBIkYL6ORrCFvU/RJBj455gPpHJ7WOduLhCFxOv2rj7wapzxxnpxLGND0pBW5h duPiaelmmv+x2ImrhbNv/F3uzBGcwGyj0qediEK0614CPOhijYxmvGcrMgjMAT5WQFC5qefe+qAQ Gtlt938yxRyb+21FLS/Q571ySk6BOIW6OL5f7iuK/g1LUhp9Y6rPQaq9mRmEqfwaK1T7+ErzIqEA ZghsUajqkU8SFUd5mZVYBWdCrzj6NCkT2DS+/ilOiqbNPjWOAB8xIKlTI+uTxg4iayhWLqMiHu1I 7QOIcbNf4aO6ey6wXPntUrAwTBQk1LphLtjErVLgLNU8MdSPobT1PUmdGr2MDfuAvc/TMm7KR29j XCDC02LiwmZcISn1Q5qiKK3SyTbEfhWk0w/2JVOwikO06mwFlFDpc/O3ALgOcGThkB+PDjnW8i3W 1UJ9lyrT7JMhmvFhNJFAIDg4WS3VXKv4kNiNDPlJPx15dT3/CgM43S8AW9PqylubaLdb3MJTNbAu PCVBWYTKesrSwOPlZbqVvEixA6ep7lVh8y4/nV5vjR6BELXnC5qaaXH9V21l/4bO/qhHh9Cl/8tV eLYvjhuNlgc/dX6RRAEghKLeT+53soVTPwob2rAiknUpaR2do4faxSQ2HWE9hTyJOjH9yakByfua WYqCY3X5TaQtV+PCEilMBQ8OqSvLWRf5jP2m0yPUy2Kkae+1XOg6D9fPbsziVvjcwyZUuUgeCLEM Xuuve+jyghEdtLECcyJK62CfadbntXuKg54KQ25PYg6f9H1gaouP+HtR17KoKxbgLYqe9eDkbMPy rD2hIcUOZtX3kcnF5IdX0rv0wWhOruHqnqZ9ME+cTI8X1EC1YIunJUN+gFuT00tIKXDNstNKw6su BycG9B/+hB/au795mTAjoCM65dzYMd56dG6cGLiJZFRecpdcGfIF06y0tZa7Oyotv7+fY+xokXWM v7lmxMeG2oOtXER1NzwASIzLTdfxLGr3r/Dy8xYADtN4MfcgOChBLN+ilmPNm4vN84vfbwUiQmNa GwCIIm3Uk0UEsnb/YvNOCX+W9ZTU6V9DDFvDrUS0kpVZA1uRjzg8dGRa08oMeM9Uq/jE3qhB5lE6 4oPKboavpRv+UvPr/+VE8dxM6QjPGPO00UUv1r7OePBP9z2dj+NaQEvhFJ+Yr6eEVdUnQNjtOuwX lutMH7CHBcNBO15ZzYMOIKYR+H82Ik8thKplf4Sj5bj0KPCjKDIbdlbnWbsRs6JQjE1Sxb1ASD1V 55XcTNqVGCtjytL9P2Igs4d/I7o0kHNHYSM3qTSfqT0n/2af44wxMS0tMkTZ/yBXO4phoohkBPgU 2Ry5d+IjKz3b615ovPgLuMxjNkvxNdwzxyGaJ5X34erQbGceijCNoUm3T+kKnv9kAes82GK9j0wD ZyhPQgadKNzyhHqmUkhgxy1s4/dOzuqG+Qo79OPMP2SsS4YN6btVfYltRBCmMwh7PpV/+cO3UA7y /a1NrMCEtnowCKcwTe3AykvN7HCXTy4UnTcZCweezj5obmuu8BMO5+45mtwkx6W5YT7akrFisVNX PXhtoNSIOqxMyxA89ETyVlbI3X/zSgP746i5QJdJvNM23YuWQYqSBnnnABa9m7SVuY0fVXlg4qX/ CcC1sfUxhImH98IwWMm8fMaIllfQKwH241xNMXiRLytWlRUmr5OvHsW0i8j/GPGDHoH232Ra3aND e0hUJoLP9ZXkkS10knD8uDS/aYiYzR7epJmoSTG3s4jcDdfV7Qn8qJ7SnvAopX+8hWRUTUwmZRRr 05pqH/yePxZ+o5zUH7U81pMG+HsUqAIMfmKXrNQ7a9bLIYyE29bnnFhEVV6XLIAO7Lzui14xiYy3 g1/fU4Vkl6qmHchC0IyPZDbCbJOz7fKq8rssv1jMajLElN0EJ6T39wlyw7zesFyEqLctPU1vS1mH 0JFNOxW1EotSwd1Da6OzXB1hUBgZmr+GVgfrJsohmQP2RnPu6mZ1kQYHLpAVRpBgqSL/RZ52c5a5 wp0MFvXYmIpE8PtIefjH0rBtsCL6ErOgXPMcXjDDIKIgFc7DgkEdhIK/mmVfNvAhytA2Ey/KnyR8 AVwpUVyaIvJjVCzCSCRaULbd9zbHNtVes4Lbm0gXvtnN2lr1Sza/Hrlu0M48O32UmBgQ2p+xRqK9 A6aj1kSObrADfUXkGLm7dS6qhgtxzMrLnEi8g2q39TI4gF0KpGBefEydA6JVwoXRa8gAYANL7eBF 2NHy2t4VEbFGZFK/LpLWzuGmQZI5cJo4gTBg8zvomqdk7pD/AK+c+4z6SszxPcy0cR+ACx4hh0xG 8A9tPzscgcGlePtc9b0Fu4O0SLWeQyB2PM65tAZxx7wzyYgui2XV5GAGlCd9g/XWAhfRrJ7eWAO9 i9wUYtEVN4yFjW+scVzob86FPHScMMZmFF+SAU+abK7G/QhrTMgden8RtGS4R02xAQeivML5VI6i RckU49wZGGf5xhz/soopFFLZ7AcBOE3p0P5x34TdXAoAv368r+I079Gi7lKsDPfmBiIi6yHIAFkq cAbZx8jJ8BRiRV5ZeF2nBK3HhN/APY67i43TeN+fKmH3RAx2R4GN/QPn9QNgkjNKMrTvygWOnEnR QcRfrnundGIXj9+v5tEYaMni0MlxQNEQJyWB96qf+aoGVJMpBXGwHKHQy2oyPsaptJ41HfD1XDds wvVIo8rrnkwZ15uKLf42D12MnUpqskHgaHVYrp5GTr9Ws5+fpz6gYocBTWGqc7dp/AARIET358C6 fPkmNPtCyQhSFUEbfuR3iqIV7p6ke/Hgc/SruFGRktq3UVtg4z3DoFsqVWI0qZ5H1Gc1w0728Chy rq+rftj9cUsBv9DcnHc4YgzbprxJKJ48yf8QUL+DeZBxCaQvTVOIQ00CgBXTfGyQX4oBE+inwOuy 6vTiJDuvEDd2MGjEDJyutinU/DrH1GvVcAKAtqTps6FobhCxMXH/gL0vBOjdRPWdouEEpqVl4393 kQ9htDEzO09lyyncAK+ePkUBWKw3l2fIPuT6wx01rjqGE963Irodp9mqUenGr9QHtsJyciinCDqz cFlPVVN90AWRkzn9saGtUuXoRq7+B4WxDmcS/JKvw79At5bULnrK685eU6yTMDt5L2st667zkOZx FJyXU21eJiu913FKK2R0PepblyToKQvUhivCWt3ye3TcotMprOh6xE7WkPes/UA/WFS2Xqtk4064 HvsCAMeH0nVQZmzbueZ5JurbJquQQZriyO/RHRBQWM++62RNGHKMwAD7Axg3kIrG9kqu/SUvPY3e j8BKWQm1uDasV7r426Wdcj5tYRkhgSLPaD+Y2Tp08oN4+FVzeoxHkMOTFG5JvD0Lb1AVBT/UHDSr odIFrf4hOzlMU00EJdXWHRIN8wwCHEAGxgUcjtfew9WEElK6E+EgbTHQCOAiuK3yOcLZmRpXYQ0J tXpvJ4gNxPnU9pX411n8DnHNkwm1sjk37MGi3x4EjGyv4lIewJ3w+Sp5X8wyTesMXSlZzxsD5X19 ntvkpHe+VSeDtHrR/qAnS/Z3y0eYuuFbb3/DzKskRWNaQt0NGvVzgf0zcTTJnSelgyH55lupbXIY oiAIxpKrrYtxwF4z0F+5+nXBcIx+v2KE/z3rlEyWe0uk1cMg05IzNEKgmJvgqIOyCC0E7+u1MB85 bWJmUmNH2vafWtypvdINF4QqqebqmBjUEbPtHCZmVoJhA/rdapoo1EGS4G4+J66qtMNj9uoMnctK wGwijsQNKCPXjJDd/9FViY1/uKC9GlkO4vTGgvSW9DcPMLvGXfqRl4h0h1xAGf3KNmZxkrJC0sAm w/FrHvHG1yZweBpZ4chjsHFgP6kvE54eIlPX0jsln9n5ZnBUXoJT/KruAP1DOv9ba4nuMoZ0HP0z pupqquuKlO/exnFF3tyBczHhSHjg0gIR/vBVeIlOCGYZY5r+GbI0UNTIXNnD3u14fVV163OXHKxM cz/74k2ZCGMPS1SoyDVRfDWr+PFrTxC7761FS1zSyWzG6+rn6FJuCNhicpU2DVcWG9NqdZUKqu4N HgiozMOn6o6KNm17gB6cMuwmYYtEyc59f8IwvBExic/+aKpcNnPr5lYN5Xvc5q7fb7MFuJPMFYI6 9paPOR98ouaUJn2vWfCBoKo/VWJ6d9osaduaaxqoDG2dlAfHVxDO3DjyAcV0V3dJtJygroxaOaH8 CCIoVsj6pQtvIE/sdbzZwt/eiHN+swel0fF5dTDF7vUiN3CjZnOh9HpFTB9rFyKEyjuJH217Xsvr 5xcyl0DWL2mzeqXtIb27ZVP/bulHf/cIbtF33AkidKwXhWFVPkf8EM4YfkyTJuggIYr00n76J9l1 kR7Otss6h428b/iOJ5NHfuRxEYqVvvO9OTn+H2nitqs4Qx+wVnT9r0csYpmbCAc2fTF8WzqjR34q EpQgP6JmDxqAW06SWJJr+2jp1x1YQ5wAzcODROjaHuIFJngkWDYo4reog233QnJjiy0E8t5CPuOJ EtVMwG2P5MW3GhrejUw1WNBRKbrwjV/KuSpjGlzm9Hg2Pdqa/7Nf2WqeuG4c9jO5Tbsc1wdNzmhW jKc3pvU8lSlGZacx6JjcedP2oLIomqb4ZPSkrWkheVjQEs710wbTekvjmcnf9CL8pJMrbknYfkyo DYzTNUG4xRHa3CWcqmMKTA6EqFr13Qx3iACcHmBVYcsr+vx0DTtVRlN03Cl/Iw8CUuTGg1V3dI8h IhrelZOMjdgoWK0Fs9Ltk1hWGTpFYuyY0+nvaWg3XyaWpMtM6xJTPP8W+X8o3q455CcEzaP7PYZl +vCpl6gorY61d/3jRFKw+Kh5PFUIRLIJV+YU0CvD+AU13Ccvzxqff7x9j7+rsVtLpImo35HmWuZH LrOXSJUEcr507N5jgWSiYXPFTIkLjicElSwT9b1MccIDj7lF/gM6bq/z4ROPPuwljwrFh02f2Z7B kLmeCnmhO4dASSl9aLc8MWH7C/0Mnplq5NYKxeZl8kDoavG0spJrELRSN17q4GnUakmUy3vAxuPR cSRZPdRsvIBa1WtZIVMPxUD9LpC1zw6GCpUdJ0DN759Mdqs1lxcHHt8aukPrlODrA+yv43ENtYTf 7QqpLRSuQApl8Q0RJ3BHFYt2xRzLM4HgTNdoIVn4Rj16V+qbfmXxZPCV285MWqwz5+2Ccy4dS5LW KDhgkKriC6kbjCwDpDxhDJj7ADs0AVFHInYM41acNjfE5xc39oeFNpVd3hD9/bFZ7gDPXXK8OWl8 DIh8XfC0vkDfTklL6K6COI+jcZQZJ+TCFrNOSbp1bH1F1hwCV8i0miUeaUNyCLGfC+8sclONgmqR IiyyP6eDJXnOiGXaG2NxSNK1Hp9R04V3iruF9uBTc23Azg3bOmfKMXY6N7byUvdMWkLpPgLW5JF3 ggmE31zEx1YsYbD5dfXTXjQFcRK1IdH7tQZQmOalz/jppKy4NqfMxB2DWh/tayxREXZG4Ehxphjv FL/iIIC40edpLfiYpHKBK120M96DHFXn4g1nYj++hGOY7jvo1OS+TiqJ2XY1w3A3KtaKKCtBRIT9 9RYcnnLoSHV/wCL+xxIgoHIkx/gJOKK0OmftIfzzg/+UUbe+xKB8xg2Nex9juDEVdKMQuPR/JVAE CqIiDI10UPhZHx/fKaIj5DlW9OWs+s1a/hKhUTdCNM9f19ArVoNbKxTyi9QdkdbEZwIalC+9RIpx P8QWgAV+UGD9hyVHlety0xejX/VOVusvoIqtiUaX/LvI1Jln0oo2k43GRtOBGsWX3vGPngOJSgCP hHmetkbcNAmYQrd+XRiGD0ecUgyCPwNaZwOHuhccj0hxMmkMsIhpqqBpSf65xDPR/ddpZ5RSddOu MKgyiFwOUXZa+6lDuJeupeMTbXETCWf6seoTKKd2yyp4UHwLysVkVA22hSJPKsy7jWiWzHMtK932 tN51Twsl1K3NWHsGognKRpb+XakBjFhuD5Lt0AFVoFFvWhd5cdLUgMKfFiZwCVGP9WL22uDNlEH2 1Ek1c4S+YfIQ3WoVjKGrCUMhK6JSvd3T0l6SQZ7LE+DkgM5ohL1FZstuaSmmf0V4mJaV4QX1vCdK E+DmWh1uYRWu8WrtFyhN2K77XhlwfcCMQ/LpE2Ej4JXGsqCD5I8zWr9p0Zt8ljeXmdqdDQ5ebcxK 6DUEfJ+uPnwlYWDhmL47YNg/ArHvoaT2mStqNd/48mWzFOv9zC3aaPeedIJOzJnsCLlIMXDCH/X+ 7WXOhwmXkKlPRBdSEDBTEZljKy5d4nj3oAUOUzGyvVzw0BQTzTY5d4EYIu7JNj8AeX7A0uQ+zAF2 iAfWb6DxrjzWdCDCvjLU2amBR7lNxGBrA/QvAGgXJK55rEJ+F86vm5grc+576E3MR9CLlYHtDqzU khjZlMYuiyhkpIZsV67dSPh1fUQ3nD74ADzATffPT4UPNV9ZLRp+B3u2Zb1SbcB2SGnCVAsWnabL 3U+lUCygOh3WbS0k7QC6OzEKCnPqv3XxjajdjovOCM2Xo/6DqHgZ5J+tpIX2z8DspfzkDHbW9KEL p7swoE+8+mQvlifd3ieNZco9zVPwIi0T+x9Hllut4SoQi5qvAuq5FSQtkoQCLiGzb4X2iBSq9wxl jyuHLzb2fFfmaTQ3afsZtGr3Ud19TE6GaP9MYVHpWyImm2fkE0ItStlnTFTxoIALdqfribgETNp7 rv2PwNAFIk6wFiMg+Ikx0VgYz8tJmTNmF+nE+XmXpDKYRFEWvHeuOHtWfgh3UNwcg/0ySbjGHp0I YycB/g71RGJP1uufXjox6s9WjwrqfkAejHAxXXTjHyB75YUF1mQ8dbrzbcpNXuo/ILoyOMvLITnX ZU2ghMGAzTuDfGCyw43kzyaz7deLIKZt/x48d9oo4zpibODCK3w7cffiYCst9VqNlSY/gnqyBFXR wMR1pXtOZz8mJLDczxeNgqNUeZbcHEjNxkS3rudh7yVoXKgJkXhBVYdk20prq45ZBvSbJRLDSSkK PcC80XfhRukSSGP/FwR+UrDOpH1yqMyQkW2jEF8+Qkwh4aH3Zhbno5+QoymNQ8RDhRta+g0NsoAF YVGWef/NGuM8BiTiPA7zBf49qhphvfXDZ70Ip6urDkHluymW2UKcqzn5IeqwgP5Y7g/I1YSaPF2d fwXE45Ev4B1ATnaLk5npuJkerYr24ZTVX8ou6YQJKI/i+eu3aMM12Ze7Ldqtm78v5acjtkLnX/5H lluYy74RzJILe107n4B3Q0F4GnOFFPJgT6TkA6XPjfgMzcvFPx8G0HJJJLMb28ZFNkS9WGtWC4eQ k+NQoMfzoEVz+103+4kg4STS/+daiHtbn/eTLgWL06QlEhymZUT2f93MjxQH+ylP10TRIdFJSzWA Q/DhcptHVKj+k6ce51OgIzoJKIE8gXpbucbiJD40YjlQdC123vhNb/TXeyP8F4I3xDc8wQRpugli i10oQz5m73qFJlJdK1VfEa71VDXW6VwJcVW3qRbAhCWSeV3C4m9Lr00WqU4mduNmEH53I0wZKi0W Od2gLkBnO+Z/VMw1i+hAGaeVMDBJRxYBtzhssZArz0D4b7ZDOHWU1A5UE3LMaq6DUgYN4K+h7zAX S0Rl6Y8/ATsVd1h3yCVHCQ6Jherir1WxxhXTZ2b7V0egzWX/1Hntp/nl2AR/2jp7ctbkWgect3HZ wSA9YrPuLsWgRx53VxqQ8fGaJB0YdFtBWRsrwr8JnPHq2g/gi9g7pZdDm0i5eGPqV+z4klRtlOfr EJchIncBfY9xWREsXauOrEEVrX14JzdKEPzoO8piGN/vZhZCWXBh+eOVFNo1RpsGz87WLbr/24EC O+SR1A8ELIN/JzW/y+WbKoXHxEitycEPhKPlfdQ7kYo/3eBEwGsrUYlnwSkrWo3x8PDZcAdNoOlJ HfFuBwn4KEp8UWYqyd012KPIyuGnS/9PmwUYjiPZz5ORPcIaPL2R4Hf8WTorSOLqsnm8sIduUq4J xm8O9inkW1SlnTW3AYvpUiBGo1Vt2u7UKSprmuwQmAlVhFtOLIc9nf2ZZFm61Fzm8W69fs/Hn4Vk ix1gDvrQwKrKVlgraaG7px8GKcsrRgHTxDrlwsjAwHmtGgf7Rqmbkeuf3+JzSzkNaonBEqTdWKiX ESNl1X+YoSsdaqyhOsDdynBmdqyiB0hxO4pxd8BPPDWJYwuzXdwweWldYOcmsryqhP5g8zQeoBGo WjQTPr9JYUnc+QTT9PbLWR+p7+Fxa+97EpviP6VAAxnYLOkallfFRm9fSuS9HcnjyIw13DYSgHRg igGtUqGWaHuBuGlv0hTf8ity4I8EcuREjE6Gac8P4936sSH3uFE20slRZVFgzaziO1xK2apZ8RT/ LQkVf5Pd+Y3wmEdY+iUAuWgeeZe0XZeQLRwqAZc25gKEWKk7X1iI6p4RXtuwDKQPDwauo4fLS5xZ wm4190/QOMBnxkAan2xVnCLRX2rLzCbeNNioABs9qNFJG/aHEtnNFqbYa0/BeZRZxX9ZC83dTDxu JTgDi2pxKE8xIWBtcyyaNjAgO6YTmqhl5uvjcO3oRvg+LIg1SivFLZXN2OfTmFbPw003a83M+KuT eTlX2Yd3ju9bfNqb84MMGgA58fUn/t8LQdNKFjNczd8zAMEI+QFl3BeEtbfAtkEtSVubPWiBIQ+N Lv0S99GgYOi+V0FmB39XDQTcZOkz2yi4Hf9kCqAhr7fowfyQpCFmHSjFsq6qQXhJy7Bnn16qqwJ2 NcrloXZYxBbbcvb7weFDd0+0bkCskAGxOvoP0YKmDZoKjxspU7njulXc5iFkVLTq5XvAgUWsVasx 220ZCGe4qbR6akR+TT9mwxjO7wkKk6zOU6AlTcWtIlAXYhiqQ0vdjQgSqaYKbeMfO4SfPzxAeF1O 3XIEV9SiirXPXTFM12ZfSZgzxFezATUP0K0SpNK5uhTPEj7XyVnn+/3a2i6Ijh3XOQYoFgnGaW/P pvwbninyoVIDktGheg8EivLF86+JPNe9Deq4KN5zXolVW1A/Xa7tqKpEGTgJoIn5nG/B5uSH+Qa9 KvnZIfA5aIv+eOj0HFCJ6fEHye289t+YCHZ6VY5WOFkEOSjAFniC25Mu+SaCowS67uQwWkj1qXbs LO0C83nnNkN5Nc6qGRDqwAzGFe1bTW4o/QbJOtydiOpWi7IHNnmYt0LQPZ1lb6ufHG0zRvdrrE08 /GhsTksUSXLvENRJ288JyGDTfjH/8FL3SqZ1gS31VtNcGBB2Ls8uSZCGfSvXg5TUX/aDEAJxLAhM c3qiwR4gj6wFDjlWrNIK+6tmxtK3UKiaF2GJRvm/HI3xcaawy2Q8VfG0PFXbhuFl90ghosQpDg8t rxeuFmG0tsLdKeWML3SV29zeXi+iyyXpRplsIrzjvGSEw9KYgXByIfWulP+tFHw0iQtve6tbz2d8 FZaMWtLmD8Su0I8g0gD99l2zHzkfvTiPAy8gXuSA2EWyA6L7n4+bhaZ9Wt3KOqh44D+Cix8w4G8I lkuL3dAOz+MMOUIxA48LxWwzsLHg5oA2CPSDlhoz+LGQafS0DAY+sVKhyjchsuZxKOMYf9tauYRX GnkV1F6s3RGqlzDQPHjI2nwQrnfGVHrOkfZo6AtlfAwiiyi48l8SGMyd7leUKldxnrdBCD1fhons 18TDCkl3ysy6x1baXYTOaDoqTLTY4EVDTs+nVbTu2LzDB+3j4tjjxQLu/FyppjPcO4RqALlnBZ0D 9fU7UAckW/0ycyYA/B0V6cEJbo86zpZthMXxzQZloRoFp/3iIUgiDWbxNSYDLevwFI6sKS3wm1v7 MlZzFejQ6olrykPjPoFpT6WMpOdeR0AJyTrEshDwfe0RFN1iwbAYqQkAuR8SUrLj98dQXuFF07EF Yt0YD1cqx0Jj38ycQKdmMm3Mcu3oCqN/WyXyO8vgoyCV0jReh34jbG4oS7zkvZJRu2SPYvQr74aR W1GM5/v4rmGmqLhEKnNSQUwumJENNM7NgJO18bXx1Y18CF0r64ZsDayERq07BDog7yPoUTGpXkX+ IsmtYx9KP/rHNLSgXPVNbm3sYPbgGEJzlwKgXo6OrBzvqb+zej7CvXKWkStq7uqbsOLzlTxKsjYI qvLtzh+O4XmmPr+ka5eW4kZhh3mmk/Qb9xeb+jgMp36M661v/I2yPz6QbF9nSjGV4LyEnbxlKKx6 xDJw3iXK7AhJSbqIPtU6KxTPMgdfcekwQ4r9k2H1C3T/Jj9JHSt/icQQZzhY2rLbBbdc5E5YkCB8 4YYhRWm/si8h4QkK6UtQLi16fNoLwKbCEWEriaKBDfwyudstWczJxvk/Bk5VhvAPm9MEOrNeKG/i ucMOunfl2zwdWh60OlqUtRgp3QTzEPiRSO0NIntjwg5RA40Vi8VlcmLcpHdEW6+7E08lyyvM5YDU VBTKg7efweWx6cNd32BKMNQg4QIHjeUHYA+zPerxlw03RuQVSnEfTSOXQwRC9kJjCl0J4bY17w4L trFyBkcaXkbxDEAUx7GTEeFIGh/SLPwwDb8pwtlCqnDnfLWreFxYfrtQTA19LYKilWcWyWwdGXbn HDyeSP9bkMerEkOw4yMMmcmQNr+FbY3R5oda2gnvrmJhednMsN8rG5rh+/LZdX/nMywXdnWu3xRi axHLL2LOoO2awVaaK/GtmSpLBQgCZJTg3suIoOSiINCcF32s8L0l3aB+kNJVUEOCvXXzjcvGPi9I i4cYCUUe8T25pDV7NIfAQJyZ3zBeBtuzeaTEYJZ1tr7iuu+JeD4vG+eYhLOi7fnyogSIfmftd8HQ NM7btqMZZPFOmav9VmLyGHaHILNfCA+clxXrQRAqvGiFwKa40ZlDG1O3sxt0BH9Tw8MdqprmEMga Kqs+aOZkcrCTf3F5byI8oPK/Wh1wGHoPFvHGOgqXTALkw7jjxNhmxhY7sass0+v5vOqFpmAp8sXq wmbeeC8nP91G8d2gH4+WKm+WzJ1XvzXfbOvs1g/AuszVwAZUt5L9uyGZav/PW1+A5wfOjc7qj1jJ 2wFV6pF6uM1KOoi7jd/xoLb0YGrdhMO09MaWQbaYohG+wLePnP5OO8bVN9p+ISytVzm9AAyM0NRP Lmri/rwMl60E9vpIgzrYteh1Kdfn4Du0SfgOebaAsA4xAX60i0y6Uk1HuWgMji072wK2Ws2r7mN/ zbtaWPizAYvCyXW5kt8fRvEqXDvPj2T8bcGnMfsZnrpKGZas19gWPsl3pswMwg449B4cc2TiR4h2 eikMS9abDkgOd9/v9Sy3FWQOb0WISIBG0mcIP9Dh+I7FITX4na9W5SnmLUNmcxE9oZYGZXHR44sJ Nywu7tBr78jktNamLCLjuMeYPKoUEkpOtxipIspT98nDQ72Sau4ZCmEtV7BpDG/DmXd0NzOQ1MlJ YKwiF3N2vkYq0p+un249STq5N+FbcImCW6Xr5QYgoHAA33CE7Gus+jTQZpDl9+OmIMn+2l+SLF5A Vl+2mE1MEXT9SgM76qn+SccGRIgj01jqeSm6YEge03X6btjDu48J/1Pd0Li/Wn/89G30yFD4g/e0 qSwxPbwO/oeQer99PFovwC0FFqxnopzBoGBbVcXfL5L7sfwxHipHXgfa6PQNsV64+TBRXTB67CdZ 2FOr0v9ZIi1JqDSWmUBbwCgDpNSUfik7P/CMpjzU5hmAI2Bo2Ty5b2dXWewpCACARI1/WfOtCo80 QrRcoJ9Y0wltQgykfavoQCm3fViJ8htEBmeUG4Si4X+/2E8vzAMtXTQHtJp8D5bCnPn7LPWvT08Z Efw9zYIebaSx1gP18kpI7Neo0fHB2i3AUFtI55EVwDL8AK3XxxbklLOGv5zYxlVmFnLhj+a0cIwv s6NrjoHKzXDGpGU2Fw9kVZ8tSw40Ozz1vy8omLthVP2582iyrtQI/H4m+DcQ6D6MkYHnvZ9EVK+p 0Z2wpwqkW/HtO2uc1T2kfoT5meHZZdbFdDktKw/bpuDiH6xd4QUDjaGBxrvhbYjFnAU56OpkBY1s s/pQNMFEpbyjDMnKQDtqlz3Nc/23gyipg3hY5vxezcS+8jmcs7adkUryri3xNa66Yc2HFyXj/0bb 9SGSr6ILB6LGwhlavV3PUUSS20mTI0hM3Tr0yIY8xEAvAav1yMi4yPw8WyzCr87/5KGl94z/qW89 5+jn2UERedMvFzE3ImY97iWzToHSxrAurctmcUk7SUmRRWlfODtINpL43dJAtuZiGcGHluHwJTy2 2EmDUQy+MyNU9C57Y/zK0poIkTkpaXOrPyZveRTqtCNyT1+LXMaOFZGmbGOXjl7naPHqzOguhHAn tHrLvy7tzL4r9Oe+gC8yhZj8MX8GZQce+/4N3//cj5+ZRvAvuNtBqQimL9ZJ+bLwIOb/ZRc0/FoE owcVPXt/2qJpFVWdyhjqZ0sQwxRBiTey+6Xnf08B8SbBjLPBj8RXI77u2yEuadizrLnhWykVaLcP 933eGpEl/kP3TP5AtBUtzqNcqr18nZaq/Q9I/5vPhe/UbinkAGAatqR5k0OuRL71mI21g3b6AlxA 74Pzd7wNX6IIMNOdhUMKZBF/LzXiD8KgOzkpHk3cK/OJTbtTf8aL3KBG9zezq/YPS5Ayg1tVsIXg syW/EBG0ompYtIWSwglVmNefWw3brPChoEGkq/qvkWXsF7Ji89RdnmfKJWrLY9j62QlLbHMp26U8 zjlKLHASH3kCsXQsiX52fuix5WBu/u4Sv/cc3Z1iayR9Bolj+KrFYrEtCAGiX/3HGLNsLK6D7oLx b2Ep+X3HVMpWvap0VCgOJL49K9ENmT9JvNPkx7xgdTqtMTZofPvUvWk7/VWOyLqVUfpVL56VZ5OT TgG3VrXBjHIo0Mv6AyH0eCYCylFJu2dutb2cJUTUB5IZAFA+/X3/EvsoG/m/9TAi7w2yTudUePju opI8jF9+eJ24QF8jpFnwLFinN5aLUk0y5YKTEMT5atp0+EOrjxPTKXt1BirJkcGJdAIjjfS9D7MX d7Blxb+u1WmYO4JqlKlR7XCQe7y9/aGlSQiZpy1mqyvsmadktBY0ofbiPQpSzvwER6utZ+XB8FsD yhjdCxembGWggYoZKEtW5fQPVHJ55JuY/uE4ZwYMxuFdy+AD3rdBmqy/DF7k74xlOzHYAgJwVjML O14jsakRzlAoWLFeL3Nq61BZL551K7TF1vfEWqHZ1W6AvihkdrxZXyTomwMUPydU2EUvHHhFU+Tp x+LgaZcdxXwJAuCCBegktMeUKVVFiFTwfxEUMOF2/9eZmFzq3W0+a1gAeExVgqyc7C4sC40S5f5y HibJ5GXri1UnEHsUKHy+6/poZO96UAOcRP6ORc/b3uPjvJUYQx/kUsmZ0P+j0SzmDgmBJeSHS4ji oa+ffdDn9nhqnXM/MvxlBsYZRfWvuGpyc1cU7Wb54Pc1CDTCpM3eW3/xQdZsaX4BUohQu4+n7ijT Mz6lMnqhf2Q4kpDO4QrT1Ur77RUYMVDfdmJb80qhzcVqmR76KExX7ykYXIKl/zl9HqxbQ8rpD3G6 v0wsAGh5/YkWNno0TCXcwcYVW873shkAZUrBO7hPiiwlZKbw/1EGMs2zTvqRAOc9+2KjFHhF7s6m FasnXJuPYEvVDfXNW3EpnnnieLO1E+ozUvYuImC/0k6L8bYsWfrYtTBHeDYADKCvgqmP+PkppdpJ 5U3EitGQf1tKpaO4n5Mo6EwddWml/fe5HFo18wUf723Ei0i1bp8tHP23Hav5ghbQ+kCug/ysnr9Q joZZrPyksBNNQGTkOFvBLtUsbss6+7KStG0lBRbm6Y96wyq0mfJiPOEUn6nFeOu+AsVRN6MhFMjY zZcdUpJOEqhlKSh5uzj0a1mmTzl7dg9s/bh1xDDnNG1nUUocdm/IYT7r7dzb/NVf9UiU0m2mcc6A z/ia4nMTJhrGWsMuz1MSkoR/VDFhD4kOQukdMvjufLbA73LWHtcZ07AQnQe+KsoljAh4pm+DTcAH FJQLcJUzE9DHGjUHBdU00QRoRpF4xFEKVM0rMH4mx8LyYQZS6glbiwzJTLGTCJ4/qHJ9DWhSd0MX 7vIgZYUuUQM9FOV9FBZNFPwNEU/Csn7lMyIc9VTWrKKeL93XDhOMbwhBqaF3Pwavgb//o9xoP0e5 Lq5UcVs5ejRaPIViEEmyzBEJiAg9M+2RGVgRrMpKzoUhnrcSyw4BG+VEODdet0ARJ9q4SxNCcXgN UTEoPdBnU51TvqwCm0S6Kr/3+n8vDdaboUJ0er3OC3GNmYDUxwvhNhlXBH30JZsx2YNjSWqX6UCk NoIoj564qIg8VejW7Mz+arqBBbPGdhFy6dZcCSJzFeflPQ48/H4HkMjaCTc1UegGN1QR9osJiYO1 vAQ+Ois+fFFoAXfnHC+8Hepg6GicksHC+GU1R/wnYXoWcscVo0I18FL+X9RzykcsoC6kAuT0Tp/S Z2GDt342lDnenYogqGNcMGrE31UWWv8d07dpWYTz3y1BORFP7/zRYzPiu31xqGVbnwel9/NRdM2Z Pr6iHkhWw2BS4wKb7fxcnW7Q8lH+LIVkTotQBaOj/w+gWb8geHX0JaI8xEWPXVYo1cN5+F1Zx5Rd 9sRk9FOzyTBYyVtv4JFMgDshdzrnSr5zhlTm68OeLBTiCXLcyLzdh8SlMyaHWdqjifU50wNK1zCb WWtQyI0y/L0LNOSGwc4WWpm/5P1/KBCI038oO9JAcHWrjFZb0C4fFP1UNoRzULzKQMW751IJIq3z PCFjacsdC2BmXJgjF0sqfiAP9DaY/otd5/HURsXnRnXU3oOPI675p97mZSVg67cLCtu3cvyFYpwL hR0eFmMEoYSmijsHCuVsSN3BARHd9ShMpHaxnB8RGWJHOgJOT1Xt7ZPUeU9oOcH2QlK1ajGdFI5T vvRAlME0sa39Rqm1Efkgcecqe6bjL9QbjFoa9P2C1Hgbp4O6W1qctoUCdAp8qzH05cW3Fk9Ty/k0 s1BTbhgkgoOCIt3f+wWceIn5ylJAOT45jFeUS+1eON6ywwy75PytMkyfOaGh/QJTE+nsVRaviN1u gz61wl57YrRaTfvV0KthhL4aDr4qt7O2Dg09Du6XKdtQPSiSEfDKx8gRPPXxoVTeFqDUDKyml4+p lLPfHmrFXlMFcTVPZo06rY0tdexhr0SVmriNxJ9fmx2lZSTY1HuL/trsXB7k9oVFXJjxVwcrjuAH HmDolKQbQ5fcMutlE3utHcnpkilighsoqpLnk8l5aSKHt7DYmbpZP6eHp73VhkZ5gLuoBKzBQ4jS FBYNDxcS9evnq/KZlhYuGqCIGdfYbDpZsIltccYWI1gTlPb2x8OFQiHzFUoRZ4EX5MDM8/gsEHp5 E02vKn76cj+V2D5zO+dZi3plAgkYE0Hb7C7823eFY9wgmBhz25thJQIsduD6ZsL+JC6tAunp8a8H xm6SSwiglEIDzKx5TfhPMDJ5Ow6mvQ0NTD5olo4EZ10OAjOrSO84T0y8oQZsC6gXz2hF7NbDIRxl 1I1H45gB+Y3ULBrxRWKPlZa5sULVKJ9obTc2AQQOR9iwPcZoOcSAl9ej8H3MpjZAmZOHCgs3xeiK S/Uz3fNQdeBk06FeE2f4vJZXFqljFZ5yoNCYvDPOYtxMh/NDxANDNPpCyN5Lnd4VNzYEtlLD8QON iqOOde4e2QyNEaIkqb31GiC4che++Ka7VkeWmPr3ub3fRzpDy/zCKGEl7MbrGQbL4pSz/GlAbyyx FXY2HvO8VoXZdwwhxJA20/Gt+t6XNosy99A6d/7C/O7sfH5+nvT5t4luhF4LHdntFy4Xhp/omPnO EE1EpEs4Dc1S5M+O10OSzlKrqKzFdWhncYkjAAvtDLT3LLnYYvBJxvb8XACM/Qh7vPektdIa1Lre Apl/hFv76p//8pG9iTq4WTLT7CX0doHt/UYEysKLfYA+CJL/3z0Rerxar1nOizYKVSnXTs/cnQNO vBFRR7oGDQz8RGlt3s87UcvWPL0zf9pQEKFGIINRrZdOiU4xoLz2dXBxM9TyxbjLUbfWb0DJXM/3 LFuWSoJUwwFQD4CiqxfIKtRXtdhHAj5J/kzJPSb2+3adZzowsuof8KNfv63eZ1TuX26fiDH7IedB SqlYpPGnYqIc18CpLaXUbldFr4dLWB43UXHU5K+PvmT8fCSQfC9KdXqsuTnNGwBfMbvuUtYRfcAF pwAj0FUPTueRO+2Hh85/SVKbUVcw7o6TEUaAYpOrbvDKxQo2yTEcYSl1XOTVK2LNmtHjCSxGA/58 BEes/7B+1a1osSKyS5cEKfx28UWpK9LQY0pVW8MHPFrfWCNmhdsbRFgQtk1A6WmIX6ANJx5HE327 wFseJPX07m9RDRLBjhbcBY42uyDxX50VXkoYN8/5KgZbt4sRgnAJbnEGyS9wVMrGboCwbFA7zhH6 u7B/zRTuWtBiq3dC4JHchbXUi7Nv+82SkCOMY3Q4DNTm+ziSZdHIttfHv5xi/SmO4e8HSy+44bp4 ofqSxOOYPA4fiJc+ZkwohMbJihDwdioz+K5WEJFD2dnsx2CxULBCqL2Em6AvKvcD5sxC2sN9PjEn l0yz5UzFZMCWa1Wy0Br+U7N/h+rc1ScicVY3f+HnxmQ6HgxRYMVdR+0SWjtckeTApzqZAambAGUs 7/CfsvwaOk0Z+qMBJsMFVP1GVQirwKaviUKzmpdGS4hLqpB1MN45zOMS/fSFIoFRmuNZqmEXW0eL dqB6McE0p1aWyYFGAXjRZWOSazRdZWvWo6BaFgiqhD5hBujDwh6ftXkvpawSRoqnEjiiFo8iHyR6 TnLci6OeR2aRe1ZAiJCddIwOFEmeZXQJbYE6fQ1yn0OEJLPRX4gDuuHI5utM2vfqRY75/d4AO8I3 s8kHn6Isyf1YnrbQr5qNKjahUSm47QroTnuJIfwLp69aqut7slXUuJeaSlG+jdX3o48TVnwmHWDc 4c29Q+qw2SzzdVj+jWAcVxlvJyLynD/6CVk8uaLZvyyJQ/gUp6cVPC3kl3yjuF9dc8bKRC5NXz4S 7u1jzBFJeXVkvysUE3qJabG1D+fB5Ea0seir84n0WdOdCzvQFwg72fiowp7yIpDIOAA2q1B+G4/I HP3/HAWsApK9MZJQTNeirqsyuSRYADD3dPe43nH6Mol4JtKzKAVsiuZKxujv5kIWYPazO+ngVkK8 aUsFy+f9jRHk+bP8qyyKaHFcCg7f39VihoCOxEhrufS6oJ2xJNIp75rRPmG4uWHWlCr/zlCT8FQM R3w0QCyQpIb7hSzZdU0CMa+AQIUwe6VUzWSeeftmvWdgTQEVb+13oTN4BeQ6LtUkKidxxtTPdTDM 1quBR4kp2BM+F8ONwroVNmQ9Q0OOJMcddJnFB40UClVQzypPS6wGwAW07w6Rlq8pXcX5FsLlNRRH 1S3VNDv5Fu7hHYLA/nTCOI6sSr2LdidIa+vPpWRy01gJaG0mJg5AkTWfMofsOsEIAWSBwR/7ycL5 0mEXBV6IcGXOrPrE8fjPCkgPbbf6+0/XKktS0RUBfppbPBAboXzbSYcfhKidsj6VPqvbwQ26jR/m hZWQHqRAdo9I2PvSZ1ZHFY3hoevySU0p9CkEYfAIDep9Ql56pdsIYhRr07MP02wpXPBnOY//fdEx Pc4pu1Rgh8CL6pFjLvX2m0ieAa/2inprumTRuQEVq5h2ketyqyTxVxSZAWkIdUWVx4T8CmQE2qiv pXkyVPrcgyABLXW59T2LFwfQxDWxKZC0nLRK8rto/gAlUr45aK9BMuJkbQbxKmwsB/2m7Vw4UppB QpFDeEXr1BxUy6uc00L3gvL6zU2oZXaWIMUIHR6HRihOyr9M5ir7GqwAiXkJnA2zHzkY1rU9u/QN lKxZezUZFwRAlotukmkQQ6tTv7SXFN6NJMQ27yhNFaifVV1/lpdjKLNluAnjrmDJxwEcygJtN/Rt 1bJ90rNP3/n6R9nMvCZYsmyT/zU7qxnWnE2RAh5b2zEvkqkz/I3Y0YReZRsZI3c4ATdAduzyu5rN 4TH2iSddiF+r5CIkjXZOmZ4AG1q5CKyQbTnDO/7LzC6eaXLipyAhy1Sg1oNnJctEMaxPiQ4vK5TD Xy/IeksOflwI4boMSH6xcMeyHTz0bN5ctlqkHEjDhPNm+QxD1UHex77dXo0cdqlQIQTUFFHC59U9 lxd3RYteF8xaqPJvO3LOT1bwQU+4CCG/DkzwdPa8dywHV92hkn+aX3i3IZU0cgNw2B0veQDfxz2P Hxhh3mMDhbtOH5xozu/K9r26nTTyliL6MEcBZK/9YfqgRtDvv25wby9ucfQZNPDgUcuagMBkYEr0 ofMfnXGe/K4p4sOtCQA8538w2Qy6LgDAPg+dJj4ZzeQmEEpOFh+uxx1NAHYlHvMG9NpyalH49ntO 8MClgFW56KxGH4R+DLXY1ciZq8y2PZus1qc1NlCHnV6dBAR2xV++6sE8kmx6BZv9OKNZ72og6S51 xFOkAd3+WgLechTDpzBj219CbfIKvvL1//ZE51Th2uDWZRMHH2sMsZdwPgbsZtN+Gv97QyHW8HF3 SgYqJLvCMczAkAzSX8vRxgT6u0qgrUKKPcDDIHvTgsd6MpVnHGGm9ocTcAcXvqiYUvl8ls0ChwAX 2QWLP4NuK4NRykQ/hdIHAFfZ1gK4sWr21HxGBZAgSxIzlMtpOmCsdI/PWXI0EY/rAwv6nKjtjeS1 DZqdywBDcyXz8EvA65WVTO326/NitSEFiIXONx9ErPkuUSozHJc/S3MaHIqKl3Dng0Fs5L5/wqiF 0QtOGqpFYz/vueX+L4Esq+BdDLG7qzoUTbh2s7rLcPhRT2Mrw19sx0MmOSk1YwgPaw318I9hRIzW KpX2q1gv61I7bHOwvVat2JM2I9EamMwLbRRldHB0eBlemUUtRT/pRCNVsWtloeYAGGUD1N+YNy49 H7WiBt8BU+dzR7Tn7NuO+s9NkzGNB6DkswwO4ky6RMsSQj0Rh2c0qHkdgf7C75Tco5/8a+MyYy8F wshWV3H82GFvGVwkZI19Oa2m6yPWAx53JC1TcvUyCfATkbaxzQ+IRq9+A+6cKD8HwfzKoqoBtde6 oDdGWCs25dPvf9c1W/I3wCNwIscBpelFMgEu9uDlc89ze9h96TYCVZXdpBazP8U9uQvN254Q9M/w FOOomAW9RWTEV6h67m7CMTkd8BKughYlDNDqbMQ+luDfNNkpdyGhgMKlIaFG21JD3fpiOnfFM0Qu D0WTDx1G81r0yY7/WKVFrnCZZXPyv1mAhjQch71Bo8y4eFRY9rzrgISeJJslqHzNvjNQW7980mxx 5ViQAmcmH+EEVhMKDFp5rHB8E2Bhnt+25yczcukO6RIHvS+LB0hceLgh20o+MT/GYuTduwtFZ0H5 wlk0t/t6dFbQCVf3/WhIygdaapdF4uuhneVc/AHUXEzS8aFSxZ4Oi+8++6Hqu067yPNu+mKQs3mY 0e1rD88FvSjS+sRRgOtbT33LHm4jiB5ZYWX1RTcOwYXTXnCw2s9/uYF/QV1HVMH269ZIjyLvWWK+ Q12YpXE+auPrL9F29XXoGL+RDIrUT1waUUjruBaHkbxTR1UQxuvrIxdBAIA4oZvhFF3YJ2wtcz+m 7hyAHZxG0F3+54Os6g4MQ+9m8bHZWLiHnhpNhsrUJeCB66Wylx82g7stIN6L6OXMo8VhNeY84BMu NayLxgyL8aPkzluUDJb535P6q6quaiEFezt/rXrLkFj/BdfK/LDPTYpJMPCsvjmG9Ho9TEBS20Zh 463xx9zLcDizsQlUtrh62kJ83Tex9NlQ+meaQ3rkq8Hym2ZgxZwh9C27Dil/8xJCr52uUKx5lSVn ryTrRdTt2SObsfaHGHoNZJXzeFZh4W2UpYCr8wkYTV+CnevGQTw9V0hNSs7Yls4fx5Qh2jkNjD4X c87k2WRilCkU/2fr8+z8kMhrBdLfJUItCb6CuvbjpGsqB52mZ04J7Hg6rb70o3cQFewjbPsOkp/T ue6Lpmw0Nvfn3PnO8r0j+XzTRgV5uj+lUSoHI7GkCZ9hi7BRvSrzfv2SAZ3H24eeyB2NJ8plq3p2 gNhxLMqF22yfifwAkDfBuoSwMIHqD9PJwHAX2XZn0RH2XdThhtP399XQ6E5Nl8+i23ZRkHuW0O4Q cvp1HOsZvwA1vDTL8gjEYzIj9X4jYjuZ3aXy2rLw81SWKjSAuma42BmrxeqkUgYxgug8voHusaDI Vdvu/579wO5tgPcrJaWvvtXGQ+uts1hWFkP6qsFuGORKBDY9kNAR1Ay/qhW9LVap1DNiz7HWe2FC JT7GDf/B+JuAEp+QM0rX+o9bW0JYzTeQZNbDp+V0XzE8hDu178TTF0ub7iWBwq9/peJefPreQK28 O76g9DdUQ5fnaELd+ln2g/l7rq/hnyBQbWc2yw6Erw34+9uXvX7Wa8Kb8tEC/b5VTrE1xFyvXr0U BtMS3wZIneycyEkQLgjtlnZ289fj1gBbg8vwbzlpn27Od7h0BJnq5+NOayjoC4F7zSG3aow04CQu cW/tpSq8q709ZqEIlGCnR/FZJKLvTyKeimyxOgujo7GDJMmjkTQVhbn8SPj3dJqDIpR1H303W1oc JTXF5Az+uMZjREOYp3bXsM3U73CeoUt9ZJiY1GsYJLuLgeztOTtG1+r7R7WPriszEk6M6avKUQlp N95YcpUBTTPTNNNSUjUsz2CuYZSCesUNrel3zwwre6rXJtoEAc6tkJJxUnjAVCT/tSklaRHPvFYz 442GzDsVpIsCs9cNT6T6NA0wejygO0UeV9sjbNcX5NDpLfxSSPqgclgUqb6EfR3BTpoxfW+ENjDp LD81JWgTIooRjVt7dXawsTpG1Y+Jk88rf823M7AsRW3go7DPI+4cMBwZrnZK7VpUiSKV9qRjU7tl t4AOAdbEBgF/eykfHkoyxdh3BWKsx5VVcFDMHcY8TMqUUJZr82bhDfF9xxHAbO9GS2+fUfLoDPNT 68uXYvS6Es6PkDuAN2GVydk9r1iiUlA7W22MEexGc5T53AVgmUdtHDpXk/GjHHRoCtftYH+qn+3F tI34kkZiVFbeHOKMQEy/6DDaLX7NV66yBJZf5s4gxCY/qn9COOywvWnQ02ZNqsqNywLx6TtbO5Gn RJL/5JkRq1kD8ylSiD1VyQ5Fx7Y9hc/e9hEFkJGe24Il4rTQgCKb/r43qoiSA4q3/B/OuWhyeceX 7HbDj+Zsv+DWS0FVDxaPFcr9h5od1zukwI9w2qETcakq6LI23AeHLdiw0vB1EjPwO4+TNsS0D3bC gjZHWTsRqHfuvio5v72+TnHV3HPYGvIPeu7xeDSFm9yiSRUEejmHIaG4pUSvGa17D/CaVQ/DmpKE lXzpKMqzj3pWbBYWYp9hSoVD4Wsnkw1HMhyfBSzaFGByXzFv3np1yO645NA7GU/77Y7jvOHPsCQj /gcwUFbqDcYlUA1rxJKpDmTQu3RiIaxI/obNIPJZ7hQKSoRYAVJLchoXWLFO46r6SyL5iVsVfBnX wf0LmCU5LgMR1s3gs4rJyTsDnhlWXVoJkRaEQw8eD70h8ppa1cirM4aGcJiQRFX39h/5bvMtsEYk ixJStE4AoTBK59EQfi5m1M+gFOVZ/vQRfGHMI0MQ6xVBoGTKdy432El4BR0JnagOkThbROQfQeQX b97F4cwiPjI6G66awm1Rv7Ebc7OdeN9guJ1oUwRvVZBcfdxLV8oWQeCjYlq65HtgIj/oT7izngQH RftDGj4gCR3OVjjKeWebVi36vYmseBnZAZzgn82keFilAujllNsnjrOtzEJlYL1wZayFkiPSiUIR Y/x73KIuhaljPdIAQ/0xUXerotqH+GvV4H9efxnr/v4qOnO4QnHPCo/PTwz/zh0JhsrwqH3a8R7G c0zWkYsELO1daIOjDNZ2+YdHcWVuhEB6isQo1aWy2Q+HI9m8ir0kF2+Dr36uWuiqnJVZwJcSHwtY 7SGHHtE91tGVbdM36zSaenQT2xPQnP6OmyXo3tewcmn1nQu+d5KmLQ5PYddrMFfejVEdfszeI5wX GoVGEBKuy2LEocZYM7gaOwpn5Uvbgl/eSNOrup3OZC6B05lAAtxKK/WS7ui1qMGVPt22reS7VfVz zBlzYEkVPW8Hii5uH32zPiOcntupE/DQCkleRsFF6ZcQygfF6m/s2dQKLTPnxWVXL0WBu6RUfrIP xn5c8sEZpKg9vaiaZNW86IOXCBDNiJ0jkLIaUrTgC18doL6c6efIdPj3xTk9hRg/O7WN5bn8ma7Z FCV3CkMcGGa9ziduBnZ3tY/WSutLDaVWDcdsK+il3svkvu0BwoBkQHfGSL88XYjZCRWIO75PR9RE ebhcxwS8v9QARNJ6Jnqir7d5zXMLhFkqba5cholsgKgGeSdUaKJVmFUrsTfnmsMJnLuDK9txXGWd mFQ71Ae6iLwY1k0Gylhu1BBrXNvvvfV3TnFTC00CF8s0HQb9bJzCHiLQg5nkFFEiJZTE5o5b1sKW NjEvyHb+LiSSC2HMZQL/UA98IMvFeWdnxXkOsManQ5aOkV4ddp/Qp8qvgREQXxPShi/2xRIRV21a ajdjvKxyzZQGf0TFjW2/6EQ3uKGCurpwixf6cYayTUhnYmPg1OAClp9lQRbE97qyfVBgmZ4+VpE0 LqcdYby05FaK0djpzk/P523sQ1g9jdTCL8pjT1EpfbI+GOOBT0XXpo74h+lJy4DijYi3l0ZDqNSX yeUq1S9l8u+qdv1DTTvBy1HWfyVz27MM1hCYqnaGBKJwO60md9VtvKjogCjv8MF8zTciKRKqX/Pg Js1euJiif1HcpCz8yhDklgEMeaJMUkVDRUQdmv0Citu4RvGXiF4HXlLw10bpZu5tqctxcPxxeHr7 hN4+B0ysrhlw52gu/ZD1rsgBtQvm8eJ/tlPyMP9ftIyjNqqSaH5jeAp1d7qzyBgay97PleLvDzgH LH7VDeX3rp3k9t+AutsX0/z0o7OLe3WCDt0Xws2jB4+AYAiNvAY4k1wrtf4Lp2/XN4miS+YRXtb1 36ixpGO7uZB0z8k3RHHmXdRsNmtmp10NRhP7mjV2DwWjPT/hyrOlwK5svcU2TEtpL19+k756SNnk BLR4A9/jV2LzD/P0nrxTT5VMhUfCxoJGsw3n0kokn33uIO9OuHH294wDJ4No/WQzCPJVJ9ea7bcJ uSf7oC09rzeoeXigauvIDNXlEAnEKHNX1XuPKqP3ExytCkrBA2b4DluNhKoFDuH6Axygs1fB5ezN XAINtXIuHjqmSnj0KbqBFHjVTgPv31c0zbXDz/vrBAL3dLS3aXOmDf+SpZzeM3vwMDo4bE2cBhZe dBLMpqU2JXGTL34nDcXC8FOZMEvA++RStcEQsP+XupigK1SN53eNq9earYQ0uDawWmCBT78E84IS EsVLWrfxz7cZ2noqRc0DGb/Fok/OVZgzRfbuTz/rsQDD5wskIgv/jOywP3JsM4Ww0qoBkq1oEz57 X+Z6Km0CDONgFQAIRM+niVFQMeBvXVWCcoLo0bB27JiOEySz7Z9CSrCohAkx3l/IdDgaknyy4iFW TAb57iyTGBZI87oKKdqH5lV0K2DHhn3+wIKL4ej/X62l9DrdpyCM1lI/Of9ciZ6WaSYnrRVrc+HX r3ZKptmWeviqoqpaR5igIiGSTZmXuCSw2bhSZwypQCkJ5MJZonwT42CmL+ZZPHfbCcVvt9i0UIK+ 5gn4ZldCirv0QJTFB1lABazTSH8vX6ga0TyfEOLb4+YaffqT2IEdTGPhwPzKcG4/7OWie+jHfVGW BpEN3B5OW3g3j12fu+3fzUwc9h/ozTknvbeFEoKwfXct7Zz4pSECLMcSYf4NOJ7dHa+/TN3iurcN FvPQojozHXRT5axSheUxPvGiW/8xqmXgDoFeoGr3IJTqM6xX4VDOrpi63bxnB+zXI3vXu26JydVF O4WinZ+ZohAomQuqF/wD+ZCiU4iK5bjQHDPEvIe/pLeXKJs5QzJg2xN0Ou9g9YHujBBY2WeFQz+U XXvT15EOs3Lj3NGQuBUS1WMCHGeUs2EMt7ilgSz9lD4wjimiS6UD/HOJZesW+gywvaS7hiKxeZ3O Qg9LtskAR/x5CWAaT9Il7jHC0e3OrH71oGugkOEkBU8dSaqqbddjczbU0Y0T+677aOl5C9xzO2im P5t+5+eOc4Ob+33LSwG8KOESrGgQUC0vb1wmI7Plk+yGbeel21+TsBCLch7VZqp4V062CF23Fi7s 8PL/c1hfWm2WUWSfX+y4U0KvH3SKlXJ+s2kH8AFVg8RrKHiSkzfBUJULIdSsbAiJi0VIrNFe/mom 13MSNJ+tHLX0a7t9dVeFBAgVSqF3br82xf6fkeV+9TmNxCHUyXpCWMoj8jghoC0toSt3/ucWyzCW JvLQm6OR0Dpnn4/osSLPoGtBK9o5CRXx5EgPQ8INB/+rtK0xXdYVSwL7lANv3/2wZEzw8s2e9kdq LHvcEGWs9qijtqlrNHaoQYwA24ndb9TFjwP/tZeXQYLIWJZJC1OFJQ7dgfTKBvTpZ7DYVCUyeDaP EN0ixM/HLBfiBImEhPC3H/SOHNwOAmvcvJYMZocQSFr8Ph/wi/JcpJthBgOmZa6ay6/fN6aF0AQS RPsvcYkA6uC+x42orQNwTdh7ncZpexrPDTeCwek8DvOQYAzY7egtwqtGmjfUnVxv/ZBe2Oj+jnv2 Pi5vpxcR1YnhENCfLu62lJwPAIMUqjrf31Of6LbuPh5ncivVZ11/J8MAnjV9lZZFQSg59ToNd6Da BUthyVjSb+irW6olZP9z3qlfkr8EoXzSJw+BCAahdO2pxQkYMetyyBM+LYDXX4xn0YcD5I7hg2t9 5QAgPOqY1dfmE/R9x09uzXlXF1aeXH+G4/Fc6qXkrRWjXDakSYsF20T1CcfZ5XSVsZuJ/c9enV5W Hnt6vdyQYDwTwpakkMUVh598WBvEpX4rSI1tNK9gAcVXdUsXI2aJQaq+Q7YhlbWXablT7UypxQxU M32MorDxQ0jjPFsqRgPg3t6YVdgiq8LmhYLPbKOO7mxOBk0kU2Z4PfkKro9GuYd3ttVzD10vo8f8 p4obbxd95E19Mq54iIrm5r5ze3gThH4yvvmZy7699m4El41qxm92zowdCab/c0z8ifTOuwJGw5my CIyy6ogOWwFYIwN6v7SCayvGS9OTqGuLSlpsjdy2SHH0gh31UxepsOsivhhHy3ipNymQ0xpXSJWv Jx/hz36YAdrcum71jCHw5Axf5AC6arSFQ8ifXjagf4/tgTMfBxfBaSi4LZ9IAx7gQ3oFDnuU628Q oMloT5KbskXWcbmgIKjMTA1rpByvhOpUOG7h6pv4iLkUsrdrV1GyojnwMlT3OH5sbGPARoTCYMqt qVKRpLMdowKixUSgprWwrVcY6IxMBhSc+1wpFslUIXPlWNcTsvb80qjPJbOWQKgelsyCVYlWvbK1 Kx9+6GwAV/2KrPhyhQS3+LppIuFSIC02kvD63FGFF+8FZ5NdO2iER9vMvq+SJYlA4I7jUb0tKEwz ZZF09Oomn504oZ+zSN1jucg9h67Sfh1XcD1jxHBjXJBb71HGcA3cc+HWCum8WC4EFvsWEK4JFojc DGKGZJofbg/mhPAKwQxKuzJ3MqM7A7fDeyCfyXvFEMbwWzcn9lcIUdoODlWZOmNjXycrUrUNAmH1 F4WHbRSxi/6fn6yJO6Lvay4lQEkx8LT2ykmKO1m8CgqIL/sTzqVzbabu23bnA2yUnT+J4bkR/18N dR3zwK0y1rYoV4pLoLJNkte8k0RKMjKLhvZMDpxBrnZC+JlP2AdyNQI56EweOUJNimj2teskTwC7 uil7RiTPkFBhepCWYmQPSmqpLqlWoSOro3hf0tcpFcgBikBDZ9pX8H5D6J7s/XZ8WxpKwa7kKz64 qgi2HE5cG+jXRIt4lPrK+ShWeQKcBmMYjTnj3p6Hvkl2ayiEWZCSY30JMuiyUIr1TlrL4VdE7Hux /d8oMRRUNIOrDs+TQSLXcELaGe7qtYRlkpdnYrmlsjuF+Aam0YR6yeShFxn/AEn1DaoOLS0uXWbx QY2ppeadhzmSEowQ2PBl85zhjNsUkuML7BC1G4RSXxaHcF1DR9gTXdF5ntyJS+GF/pYkm2FQnk5h mvbkKZ8uf7WG2lM0QX5wm9gtVkxXWZ4LwJ3T5x+I6/fxL6VQ76VOweb/dO/L/KYWk6i1jXKPv6Ff wlUG2f3s+tkI8YM/Q09+FJVKnC2YqQ0C7MiqJJWQIAjbCZ4bUVfrKUQPYNiNlnQe5m5Ox8uLt1Wu 8UM78mZvH8OLTUs9IwkFuJjLYgdNhVx6074rrbH1C+rYdw1xv/4avEr654KtpDE/XlmOoCQFb9g1 6a2Ih5M36TimpF4IvcQ5wVAKprJbdfjNhp6ISyNrSqU5rLwAzXv+eypRFMK2yIrdMtYzfhQIzazh fruLpVnUASGW9TWcGLlK0oFAHRjAq/T9KR3Fh2T2fo+LrX7de+i6Q800d9gtkndcrb+i8Fxk0fCs kb/13H9OdKVQYARWOoT7CYBCKGHMc/d6VTcnTDgcFXZd+S4TPKvtTWENA+B76+Pfc1UTjhqArWab EIy9NBHn4PQzH1kAhNEADG+FafDgZb0iUcqhqJ1ZgMZssBrbHsJTzBsWSX23lV6pyY5KDHsnI7+C 3ojVactNevU6H6le04ZFe1k5be21s2rPYsngJUBrV87UL5bQALxY59gYN5uqp3ZMoVjzVIaUn1iK OHXaQ8vKeQfWvI5G9ncFuXonyla6K3MddPVGhLyVQ5hFB7kY3sfcQMneHo2GpWGB0kfGCGcwZrex ZnGerLk3HZpWIT8qQhIiwbCigrB2MFpCjoQXl2AZgYMrafu1sq39+db52WbLfbd9fskL92zIG++a 5OSC9jSqHgzifHaKf6fAWL764PeT0Yf2XdDR+XXPobdS494mILS1YAXgrLCHwPNEQsQHMbllzw10 OcX9qiszTjUOtxkZSPG2Q1ps6OYiXHy61aekw8eXLOx1xHoDQBDeEW3A0Pc8XMOkjhWMN8lfz4Dj 2j9AK4Ybr40HDys+cVXSYR5tdW7gPabErvs8oO5bBwx2duq/rRxs8YaRg0sy6cbQSKepiTBu1y3/ 0v1XgX1DNxOwnoKYJixLsU1Ym3TdNtqZJPzkVsh9Wxhpp0cXx6D95FfZgJJZOYv79kVSs9Xog3kf IEOav2ebcHrgU9lcP1AiqRYg3+qdIF0TpYS7ay0KKHBLSwriNh7hy7OuLHHfhpN2sJED3jTPz9j/ vEKD9Pm8FlOozUdZfhE0qt9qA88X0Uq23owvREqB1JA+D+6W/D0OAmRKX1xqqzwqxdoj9EasxUN+ s/VNa8dFg8PTyxs8rpwzcc7R4CJ3gHBQ2Ua4CN6tAk9GDZ/YXekSGtJy6WYBy76ay38njky/NXHq pzc7QlHSeWtwfH4TPPd8H1pf0Y5KqveGW+MlLrrzK1u0E5i54UatunIUqaTubgNW9GCpGf5eZB0y lPPiH94/Y/3AEDGukMxGTF6sFr56Mju/0pw04/ul8PsN8DQZdUq3Wmx2JhjRotg30PPqp2IceV2u Lqw35qx3OElp3t2SixGcfvM7h8pN0362GfUZnnMqZSYquo4LLvet2dAjiCx9q0eZFg7hvH26T+Fw VXFY8b0fDAPOJVYzkYGEbbnwYVejX5BCajmYLqTwUvEELINozu9DmPv4Vj4oC2PI2a6lKW2JCtT3 6ytr7zvEuVpY7geyBjQFvMpQ6UO4jkIkp82FKqLXOOKIZKovgeEthR6sjaz6DikurOgnzxFrPTju 5lcjS26BP2W+zAKGf+PQkWhjgkKX3l/hvKOjVL/fq5ybUWyTTYgyiHx0Fx8B0KK1P+KmyTfQEjgT 43OiwZpEsCgrdlysg3wa1ms7RL60tKTeARAKWgQk4i6Gpjqs1RpCDG3XxWbPP+9kF0JEbnqNL5x4 PaL9wnQmFLZGoWLrX6uDQCA9cv05WhhOdkXydNSY0VAr8zr8EZQhwwMh+EgqEdqiyfTh3fWX3OXD leWwpcDJ0roLU8EeUkoW9MPd5i3KvSARXLxXdiJZMcHDFsj7NQ7o4CbrVUT43S1L3gbyIgaCatQ6 CtrhA3iHEm9isqGZIT7b8VnAUI36nP2J5Dv8dh7EG06azh9m8Nrzbv1s8Jh+MsPahaBSaou/xMw9 p0YPi5gX/1iqqdgoqekY1E/TIovnIYHKwKTnNb7j5V8NKJ9UKEhqE9ne9Jhd6Iyz0ZxXJnB2RQ/2 nShnsgEDR9xJ8+OfzvAV6AaLOrEaeCGc+PRiOHO+F4uOg0VXNoKkEUi0peggrmthcs4teQUvCdKl CtNs9xc3PDavbHgUHQBN+qwYjwn5gAQk2bTs78NG+h7HyGKenk0Muo3ixQ9yA8uzS6MFvrA58i5W cDe64M+eD3tDRTH58UdSUYYUWW5IEUX+/sNvfkF8P6srCBq3eWrWAGfLi7Gnr20MUOzMjYXiHIXQ t/vecvxuKG55ktQWM4EZut9XF8ibyD32PLYMRI4UcHH2xuAaZDdjGtR+JXf8VZfTCkEwr1Skm08e mll1yk8ykyR/QSchWw3P4UPDL+dyyntaxf/aB6eqAEkT4KqdGK5LCT/szsbhe3nDJ9Muhg+whH9x Z7q1fPlCDlMKvWqmWiTpgim7I2W7PNuIzWKjt61XkieW1LnuJmSWYfsLBK3L3QdfTaDTJ3xFgtu6 IIBLLs6egMbT0jbds5DOUVeg1a7emKSzSTYjx3KOzeyPXnFdFV8rLzT68MUFZOAvuP0xVcjVucaS 47ion9yLa05LwFyXv1Zv2pvaBcBlZVx1iPgMovOQnw1D7n/8iLCKEEJXMa5MkYslWZ2xRnDyjf7M E+JUrOD1uu9K/JjeXUI1QfSKmftXbz7gkzCqyDRH32nqqGh3nfLWkU29/H+5gU3GeilfhmunfeTP I4/FJR3ITlz+oFU9mWuAjVPHekDkvZgHyL5LfQakkwWU/IlS57p1yzbNx7X935lAXaTvztaGvcfv yF105bFxE9Wz094EB1FeVU+hAp6u2dlbIHwEUBWXPrWhU3WQ7TZ+l03olTJ/gNEKonuC5YC8PnSi kuhlxHKvyS8FtnvVXUmPKsFOYUTdl6BaGWbd5zeKS7ysOsZpd6eX6/bEP+pC20j4bUEhDUHTCjEJ 8HCFe4O9yAsTPGtOJNcj8mIv925AXGaJMSqLLRDVyHht3HKdgfhE/2IAd5Gn6gTplGT57DaJhdq6 2diyDmzZzbNVp+4ICtITyhsUVm7bUy5IWmQfw5C4Visqeva8GJVZ9pWs41K2rY2AX7LxdN8NPaR+ TIYm/hk9qcMza9F85bZG53snKW3HJL7IcqaVVgexXvKh3Sq3d8GByixBfSL7aIDESlu8et9TKr0I 1n9AFo4DZsQLWIvwyNVVnFQS0gROYLwI7GZTceP34dukxl0RxGCPjONp9FBRvAjPqqkgz7VDUVdX uaXM711VA2H1ylG2PN4sDdQvE1vJb1ghvhdVOGd9LxahGor18+14XWfAyeh1FKkqBecbdn5hpMhz lMZ42NE13JzOPHwJeudYsuSvOICWB9xjJPlcTkB5C4ujndeGnsmost0H6VD6Wjg2KU83i6kQXEHl lJas6WF3hRVDVFnZKwUoaJ7e7aNQ0nYdVh/6Z8mIjXUD0Y8ar9VHayfTmIb9YGA5WdLWJRhRe4GU 4CYeJzjv6JfvqsTgAICY1h/N69C3xXBFX3/mBzlBl7co5zB8TTY9u8OQgEtIof/UvaRXFJXx/TfP 7uRHErGPLGfDYzUCzS95YoOujORyBL2v2xMAALt5RRTKvy/yDJ/tGhwP6E9hPpxaDldIl/AMnw1L caeMp0vNIgNDuZdIDqdzBujJw6XiaHC8xc1EBWwmO00qLsugM3Y6EZZUTMPdenB1ISeS7Ce8+oYg P4QVkiZUEtMmKEPqYvlFzwQh8OMMctGPr+qpM3ipmgDeiLAtuCWQz1Ti3mQMVypEWWcnVG4u/ZEn z9P40eT1mylU3u7Im5jceSso8uvbUdv5TC6pe6sWsCAWimerhvKKaoTxhJN5QrD8Rf4tbLPIna53 LRqeTd8351CtkHHMgmUkV7lmKgShtgDHHZeMyxQpKf1z91OOd0VF54rtUQqUDD4HfPpQe+oiva4u Of+GBJiiXL14aO1qERb+y1J5TZHGuTBV7q6QL7hjDMdfv5baWeBUGEcI6GZnXPLZcXUr55SmWSS4 PoUxxP9AAn8O0cmGOe58iONeKHv5cVNh9SXGpuTcUZf6GNcl4fGdMg10c5SIgNZl9ZV5I0Mp7GHV viiE+FGS+jQVgsnDbEL6qRyfVgMrFwVH3xa5/Yfzo0SRfFcw/4pSO+97EtogwPzeK923LJ1BPPhZ rPLftm8pFXD4ibW8iUI7VAzOAy0QTjkrK7KA0XcaUo6WGp9At/4Xm3XQ07tF3U1FKf5iNIuM3wc0 zjlAuqlaKkT9awEJsM7DZreZFWDjVctmFSWlIO3RAzAEt+KtGk/EXOyy/7FlH0Vy1He0UtiuQ0Fd U/wQEVyJimcLJemexlD3eokvGiLwXjzrwQ6HmNKBgaDpRojs/32ZMn+yqyBmcBglyerqiJuEoMh6 CuaX5sWOopHriiYZpeM4ckpisYmwcS5+u5If1OXXLfYdOJ4dxrOdlt5h2+nrny+KoRZedB9ViKBL TysKMHl1DERORuAfe2AXyeB08DrfnXSFUwO0xUXeGhBJm4m9brd8JdoNgRFY71O3SZ44WFoVl9XR svOoFtSBqHimcWdopybuDHE+08LVV6qtWG76IzmjNrCQbYV6xGzMn/iL1S/rPFTltHADz2doaCkO b4QPuttNZhGYxuLI4CqUC7p4NRXkIht8fxcJAkf2l6SG5jnT4VDeAb0OEaUmrrv3HE6M0qFdW2QH HNgNWQkO72mObUfDYou3O9QIhedP/4V+gzhxs6v7PYgJGI6HDEBaT4xp+Mczls8e+zx37HZx8nIR 0CVtPCRVPJm773hJ8TK4252dneew4xNgiVWqOt282QvxVrAxB7VYdNMK5Q8BmMIwX9vt4XM7dq9f BNAb9M4rZozVttUK6J+pDSQlmX/OaU/HaoQLcYDryFq1QgBN2R/xJox7X5DkO+IGDxgKkxiUBI52 PrHBFLDAdtM3hbs7+CDczXmx2DHtKxVCGG2qb6h0XR52CESwkvjScP4LmMea/W/F90yDM6I7tDFR FR2SN9OrEPAbMUPLuVkjoUJKj17vbLwYS3/u1FyziQTMiACkZvQpWyMORpRtSmuv23Hj6wF/sRKk XA+bJGFIs1xO8HUaWfRUkWR2qhzyHyGnITTsfTaSHsoJHeL8GDqoHrxyIpKHbat/idRYfG6ahYBP uuEZ1Eb1B/0WhlQrFam8jZkhshg61hyiHdcONpIHrAMXOYvZQ8Yd67Wr0fBAZYQi6ICpmX+vB4cd nGwmOJJ8LscIUlFCPcsmmgfD3VvvEL5bpj5zqxtF3QegUzTXUf6iWIC97mvQadVO7zHYclEosd7p 0ESrfT8yW8POSvPtWRgQ1wxTPwdpk+4Kjr13kppWwyvk0dgawAVLFBkGBMxCZ4TBabR+1Trrffdx cv39qio39/NexKsOnmENzDUwDZSyDFX1eupwnEUdGDKFozQooLyNyCNeEkMVdwz3MxQL8dXlVxzP TcBIzkYX9f9r/rDuZp7Sn2l/dZRCfkb4zDMQL+Bt9zpWK9TYPeAMRuTc6FVbkK5Sv+Ry5u0H6cnG 9KvSymICqvmtWGZK5+ghF0+xaKVKqkt0D9gnZ5G9/vEjXdg1MaF/wIomJjBfnLUg3h/3AjxnYMxq gXNkePdDkxenPAoeBW9xdLUqhJgdRsTNyJiYykg7RnOo26naQ9XyLsPZ+XDuGBnxSi8OB2+baqwL oHwWxCdtFQjdxNGapq541Y5N/osAiz41Yj1enxY/HzRPcgQTVSU3pFFXLh1Pk8bzVeMr4PLN1DYO JxDCIoFinhh6pLtil+AgvqU6ewMkkelRu7eXEX+j3MfJFhEeenb/v8Vs6rTv17FXhSeRTB65xoIv w7coEumoxrHvv6Fr/8rTJLMr4NM2UC/rPiEjjoDAaTIkVszglCChoqQcDxaszCmD1ICnsjnC0662 +jmJX54iBcoYOnQXfjvgtOxa8jV+YnnCT/0qKGkw2d0oPLY63JSYKyFDiLhHxMTiEBx23fTXkk0B qGa1GMJJhshnAMxWgC+CCqCIfZ3k9nTxiHOS3DSablSDx9kaUWnxSxa8H5ic044JA6InFQ6rOSUD m7uxBJxs47U/c9h4mnhKs7K2y8YVPy7Xt4o3FxRcj15e21Z5ZDH7KmvxQjpmg/kNelAQf6VVNmbt meg8hah/ZxrnPPdoMMc2oXeRvU4BlJnMDx1Q84KdCv8hetoZL+J/wLrU6d+0PnW2j88pQaKuaqrm AiKCAu0U2NK2qIGIex7Z4puzkruoqv25kBksiz8hS8YiFnrq96WxGLj+LO/aOE6ozgwlYNbCXLlg dxVXcNIwaEG49YvfHTu+MHUlcXKj4c7K6vz8TnC/03La7EfcZFlnGUzFAubnV7DW0NVutm3bf5H7 asRaGz8fM5f4nEkFvzyIuCo9FgCmtICoIcUqGggZ+slfJMap9gP2vNbn47CWPKRb4fvQU+NFIDaG 7qS2ATZ7h9BepRD9OsAmC7JOxPlvMFZVl4kmTAlVgQHinFJGby6cx50qlWfzZeiEgNDHz1JaWJyi jOuX+LRjO/FdjpUnnTOhQmDnf3lfHZ40dWgc1fnC4xG+9i1n4+9Axxgs8JrbVRGssHVA1eJQCl21 qx8USmhdsmtdNUL+tQKs+/YSDBxn1rMzN4KTiraW5ZPIc9SIun7Aa+XQGx0Pkgk6RRCPgTJGvZ+d tfKkTDJwirValli26rMaL5aLXLkgbzcz//FP1mjWE2TW53d0NJMGCKZWw6BdVCYfW3DHOhZjCdh9 hOlLBDvh459MkHMYw8nuAjZpB7re3i73/QXYFA1SoJ2JlhF7oTfv1+XHTt/iziFmjgeq9Mxs7EQZ j4Ue0oWPXd6cguoTjAdcC2pqWhMVixnOdoz0KTyeaIOeX1LxmjpOhW6bP5DI6VKcTQPZJ11JF4f1 tAGMMrW2zDKI/iqbH5CNeAzS5OGVpLIaJvgtlj0Sty0b9yUGd+Le1taSixxWU4zTLtjbzvSYaY6t qGGOre1GttadWk3iE4hlzLBw29GJLQZ2ru68Bf4FnT0faAMzmipTKBe1R1SCW/hwmtWMRAG4Dr/f ScOABTku9VhUC0ij3AIxhz62DjKVrsDXQPI3+7M1hFSPHOfIq9niz8BEgAE7TJE/i033LgDjt+mT QBkIMtfuEOkTXXDu+77rYakxC1qx/DtsnqKwOHAAcXV5LzWJ19NNVSNT15ovRJcotaXU9Ddaa/Tz YU7ylF6Q3diAvywrIgon6NMVccz7IOCd26R0AtdczifyiqJwBxG8MS5CrKkkMes7JpWt7UK7oIeC eLF9rZAQFK8T7Mim+ry7T6EIvWOQaCsICI7UaoPbLOuogzzQMVEztn0duhVRHIcEnWnHe/OWDrFS 5BVfBorWISmTd/6VR2CWAQuGeSMQ7Iav5uwtUwLb4830jtqtenZO2f6HrB9k6IESwo9+6FF3Tqh0 TvbkBa+9JLofHICPJlGywit9cjwlUm0/DDgll71Nfkx+t8lAVAl8F90GIkktQYmBA4CRIZH7XyQT vQ9p12q4YQj+/2u03X5KsVP1dShJSBbt/OcS306e0uxOvreaieGGjvP8ctc6QDK3Pa22JxHfttQa r1jroQraOtNENsxDDQZXdIsZYGNiliTEl49lmA5oroNbW3+GA7YPf0WbmKQbg+xWe2D7dO/9d2te PzUSgDhL71WYh9O1X2Zm3XgpTHQ7sFzHA9jfnCXc1ydd1YKtGFJlal9hbGLZr0yazrf2KDhIqjz0 FaD+6eGMmAlsM3q6636jkS6DqyFEcFXD+f9JyRiThqRnBISRsDC0VMTmVPBEjOkUybPtZGvd2y9G dIeUg2ovaAcCieFBM42HQgREZxTsIFMhdilNV0vRwMRxYJty3cKuUzcuJTGgIQXnbrFcu4Ny+VYU JVe8rfpaZL0ILkChA29wZEZkjS94269i9Sh41YG7ZHU+KRbG2FEyEpaa0P3zZx+ZxpHrGSRowH+h QzQd70B2YqKP3fM7Inroz3aJ4ohrJZWf9Kwi9y6ll1qxpH4KIbi/wbwdVKcz4rTm7+SDzKoCjv9s glKvC7hTbt9Wl0LG2VYbqV38tanvGSByLxnl24nykTg4VRVemKaXdeUsG5PyK7YR724rbXjZaRgc 3uddMvAFqHddnmUYfbeeACvyAZ4p29sPgStyTMD7MGWe2UTqDBRvnhMsI/tGGMDQxHLx2J6WT/Q4 yfpuSxbrTFF1UgUGGds071GCQXBV5kLrnjM+0prZFCpUJejuH2+Ac5rh1Md9jTr9TSYI33vXn7lC kcrgIoOX26zo190a+0oaJK0ImO+DcSpmlsn2uqEpUh8xGYWQWVeSP+WGiCPC2ZcxqyMBucZ5kTFm 2h/A4DOz+T3UC++NJQUWUXhlkK+Xc9n55U7eQMr/54bAo92xmMjIlRBxOceC8aDdz1D4YGLwxzuJ hHtFFI/yY8BwlqhCWIb0An2E51Q9cm1W0JfhlaGnrmIuyoMIK0vjcZG3hWWwOiWGL4jJfetgX+tx uf4Yup2VH6bkpOuW9jAOebjGn2mm9mDxmMkXinnKkVfNCOlxCMc7xyrJ4a63p90RrdAR+WgHpdvu jfAe5+elkbTuL7XtJQiJF1JjBlqq3ZKgD6JAY1XS59Pkaumz6RpPl7Rn+ansfz9JCJBE+e4Tfa9v PIqEnRnYgbwB7MuKqW1rHq6hLk1ebhFXQIYc/dOca11UMtiy7nc0tAwF7DTxVF57ZuqWvBOoSOBl QxEZhmSdoRyzsdXIle3VblvZYaVRNz1xvMVNhqxIZmMTN0x52Qc1eZVkcMVlyXDXIBwi97vZdnjf PxZQvt6U5sUGbtquSIbvm6qTtmhNtiVJf785RRQUtrmA0kOz+Sp2/1yksd+SI+ZMgQgTwUtiLf4P NwZdT6KPBofQoA94WSshgWk/OSJhGXC5v36ZpnTaVJsCndu1u/apLjyJaTRqOyO0PsMFrxt4/hmh REPz4mB3xZlcwf23enemQzvUYGQYHqp1p1SD9LasBqU6aBoRuei8mAuWpmeY/phNPTg+w+HKnWTf 2YsTpJ2jSBs0Desf04Dv9X5VhjZiqubcRRGHrngEQgk2lJzTY9+9dCv6VrW+MwS5CfSHZ+FxnKsk 4skSVz9uzH8AkgtVZbpYF54St0mM3EnL3m6w6VL0p/V0NWDUgCXc0UB/Q8OvLM1ulsmDFAlaFB5k bQCpe6fcT8WBXNrXqwb51Nmx4cFiYvw97O10dwMgg/8kGOBcQI6PzJBM77npaOy8fHNppnrnhdRU RrAm4ywoIOXLwX6rAqELvuq3TmlxdUdUD0FOL/v7/t8ukAETPxPeufpXKG/Xblh8m6GKhPq12Nix mh19qzJ9CWIkvDDmdeDZpPxiBVJwqVeBRi6fwac7HsBfahtOqeozYNBlbQhVHVNTwC8hZx275/jN EcelVFZDQ99muBHkPGSLrojq9YuYjqKfSPGJSdvXMeujQfG95OeEnyfTBkfE8+iVRU7MEQv6XBXW zO6iPxmGPURneoyEd74bOSi4AqDkob8n9MdjJC7qb/qfyw5qT9Bk2h5cYVGHvyfxuFAw9dejYhqa vTf0Q05b90Od8KC9Vax3F1g8xw2vZIby8MXp6C24agehdSn7poR7ZGmaLGLxbwtxs62XsSAsM1/Q HaDwNrSYNKkjYnXuif7Npo6swcs8nMFcpKsSvRYksOA65Wqiw/I+cXjPADDXCdHB25vhW1NJuDU/ F422a+5d/6kw+cieHtJzjKlW9HZm34NCEx7KxoOXaGi1hVlMGgwss+o/BQETkc9BJ4XNxaCThbUg +BdvMh/aaMWF07cBMrHJLEj1nOeI33TjKmmSt0zSvUk7k1u+1zj0OoZNl9vDBK5gukb3P13kDXVQ DS8dd1VSoZLY8WPIxzTR/TEPoQjTQcmr3K3fg3GEWYNTPjMyv11osqECfNwAqdg+XlMQvjwesdFW WBwyJFt1c5fWEH4LIWQQKpXdo+ci1x/QsIixFScVICsphhLqmia0mR/zDIv1VtKJNRIBJV+M0vIM c/VghBZkMwntgGyq3lg9EysaOv2/UYoW77OiznDHNB4iODF0PolRbnDaUdx3i3UP3MAe4Bj/kvxs d6mbClcidRPcnJbUsPjzP30JqwEmOJVAzTHgo8bHADM2n+ZvV5SYyZvTnkmRrSN7jbY1pf0VEFwf 7/rUb1XC7W/dwZCQifVvVjmgNZX6l5mNHvQZFgSQ5W/mPYQQdcK57TWh+RblrlaW7Vjv9FXty9M6 +tbkT1E6jyyEFY2vra2dLVRkShEq70f14MKsinFCh+HDaL/cz1jWyYidt69ZuUpAjHPgR2V3uOJg 5WaaVqssETdfLok60Fro/KU3FFIaUBGA+BzwU5mjXX/MSkvmNakbzG4u+zpieKI3/aagug8sr+GV kvBSSmYuH4Gh3PeAo8rZxvABo+JmsjRwWHS1Hr5J+j3fO7UJFLcbWvok0H5gX4aFf+MOJfsrtomE 75V3Pt908j1XkUe5kznFkMHL/fhxKVkJAbDaDOkEpthdoofvUNnmxZO+Tk0v49nfZO5SJRXff2yz 3rEOM9/13GQUC+qjqkkO6RxzMsN5KEv/jaxuyNU3pdKoDxhidWNYRRxRKrsc0/XPyOzbgkUheN6F YJChK23Cuxbf8TVCX0YAJhcz6Hv9EkzJDh2fAXjZOT+CwCfKn7HtwOKsjCPv+CnP5tjwjmExCM9k JmG9y7TJL2p7xG+9C0XB6XX9Xhz+JRL2QSlNMc7PmuoXiZFXHbht41uI9024wUkcbwLg9KWWzyZX 9n8z1cU+i6bkd4mEIzPriYJLA0d/hwxFkpZYI05ClbeN5v8GMYhiKwb221mvAkenNgxsvpInzZtl 3FaSTEaiQoJ0YcHxL3cClUm71pE0AKOQQhkWB2glb+8nAfxcb7MYYC4n5tMbviRqjhCXXGLcDGeK ralBjbLrQNHu/VQYRDISVdwBmVAcCgbZlk1HA1Ljau280IlHs0T51R9Na+lAZt18l3ewhU2lHC2Y MkVGUkEo82rRD1igb82OiUzFNPEXnFHlLlZRDUfmswmu7ixrSDGu1Zuj9iWTTsTPqK4blQlBo/+s v+RCc1Fi6cIJKXbZdzPtKpVAYPGm7aJKpaYV7TQ4cKtXAkoonwck0kzfS7i3W53OTBjCrWgdCpSq jKMW4jDq1gdu7vwACpnSWOHuG0fe1LyyT7V6l/bdg17yWTsNxZ3IOLehuviLvB3DAYUSacoJamaS LFKlKD7ObNwXIPbLVcWvplpy76dMith/4aO4dokS6/hEjfUjEgHeXLNAgzvhjmIiKn1dC4v3H95W bWq4on1R+jjRtjaSsC4AiFlaWj9jmfMOlrYFmw71uaqXe18ZS/K1Z9p6VCiA0lyViVp8OxjTqsIq HsO8vmDxXJ20/ROXgXG3K18gMvbBhooPtnS13ijhKguNKrw8yryuhroyiZVJZIu7CuO7oyO75UmW DICJin1EZi7wxrZM88+eFyL4wyKi9st2HYJap60WzPM0MvhlaTUT9+6cThLLu1OQgM3TzO7CwXJ2 NzoHYLEdXbB0/oMmArPcOP78QQk1TCafcpUbmzEXcIWM7EoucqfMX8OB9C3piexkI8odlqkXNLPm r96IXLvc2k0TqE7DGZxMAbtgGYtbHtJsI1wrGn0lFpFe0sqcaCwMV3nfzoTBgQjqlr1apY1X2xFz Xfyxh/mBdAK68eLFgG5WC+mgUvBo0KlodQT/9wpVsN/MDyDZMHbT9YtpT4i2CgnIqGSVJNH1VKer c2feMAlV6K6owW04Qoml7XaaywjC9D5fYt6Z1fledV6B036hwLiOyxDqPW8vh4qPtBd3mic9bWlW 7wgrrVTSF2aHtILvojTtcxFIrQdRZQp2seCRWbG2BkrTv3/1bKZYnGQeaPoJ8cwmNqnnaVolla6b lUsQOEWia9hB2dZeuE8cuwBqhHcgVoVvvr6bYfCUvY8Q3No6t8prA5eH0SBMStRt5cEdzz/pOLdI 5R6hEOMw6JtbUfYBLPyrTmxSPjZTJPWdRQDzvIi3z0+Pyv5oIFxbSjvT9Vgz5+YJuJFTh0rVfg+l 5DDQsr0aEqpBoajvIUfxU734qOF+R2c3uBoWMNtJUdYn57ygEU3MeH/2MTutznAyClgNDWTWjybg 0tTvEeyV2mNZaQC+nGCAcMqPX4fmU9yuasTmHcuo/tLiXZxDE2heILAzPogw2fCaA8Mbcj7q7qQW Ut8KSZSNTPiLK6lxSnInN/WYWGikumoBf/w1bkSRgmjhvtLYnKwYnuBrtZLbQ3q3gMrK9Om3J3x5 FoORawc0pin4AzVIQQdWn0Wd0E87+lpqBzjh0tBv69gzK+jfpHDlXnlZFqrDh0zfFqm8nojOe9yY qiscPhyp8ezAlgS8tQFR7pTF/ysS5udL3GVEEWHCfc2ylNpo/vJodv04tWLe0iW7rRCDcbSUbx09 NMukphcqf38Th+uE8TjBENAj+DbwgXf1/M9lp4dh7+BnSB51fsvRIeoXaEtAAOYMaljNjUE+o8Qi 6GZHX8IeT0o30xHl8ST/hJ5c5z9g8Hm5n5GAlhXn7WXyNrtu4qREdeADPOIAQi9/aN5Fiol75Eam fYc7aVJwu0SeJdWr0bU4xhTmNKbDmakaUP9SIaeR0ehoitOTkizOLpeHdgoRg/64c9SLaQPsCe3I ajfoHR8NUe6wmEVSHVco2STg4EPYgqlGx8kXUquWilIgKhdY3MUgn7NNPOKR4IpnIVyy1cv61tqj x4Pp4Bz0SaBcEsOhuPJNJc2cVR2kQoHtrdhZbcEalbzknYH6DE8VOom2xW+2AY5Ub3vyQCbzbvJk plWdfFaFqQUjcaLHXEulCNE6D2FMhyV/8PmPPuXh7i+vDiDv6pUngNfrWXgP9SkTKhnK4KSyZt+e EBU1QO+nGhCUJcbzi60wYvswafRk5BTw1k/6fDffzT+o5Dbt2Fm0yxJshVrqMvwBBrebEpWeL3gf R1BqbOihhyZvklkwzLChYb6yL1CaB+4LAekiJhhZDRLNP6Ek6PZHoNOW0/sjC/A7pPreTPT97yw5 Ut9Y7FWKji3w4nLPRn+Byy+TuVpjwGZ+/PPWouMentg8vOtNtY8FgvaqzBYc6QclXCpzwlNKGnux V7tMV5qOrk4K2fdXApTFebb1GZhdGUMGwdSGMq9GyMRIvcNgNo8gzV4w91KRInuPS4Mvl+THKVZ3 SSotRtj+iKGjEodWYJlfA8Sxdgggncagc9jP1Kl6Tx03LBPwdOthrhgsv6ufLS2A4VjYzJ/kzJ/H 3Z6f7I54dGK9cziOyjLGya7EJYcOPzBzfQvEoBtRcoOU3gmIX7APf2IUaFWfC7+IPHxkKBDmwnKN QCt5LTIgj7DYUTg2c4hAh9qTQwh3XhlzYrhTaxY3zmJzJm27YtaTPwTw9ldCjutK5NaICodvM+0w pbIzS6ZzGkmQHHfq4sejqsx4uOgRfIhq8pnNm+hcGoQIJzQ8HQTnEOwNSF0SrKt9Fm8yDgvm9Qs3 dONOhdkJFKVcRgtKIf88Xc6eqXpRsgKgY3zZytgoiViuD7JK/cRh2wpSWVT76BCLWC2Qcj4XOag3 1Q+unlrh1HKJ6uhSUZrsuV6UO3s9qH2qr2T9fPPkFhsN/ey0ybR0QaOaBR4+7j/2YNM65CCnlo5t ZTKfkn+plwTZ1Ks8N2AGOQ+fp7aT0pXOaz8CsZycI7/trB8kbDD1adHIxskNDECBRYjJDKVaecD+ lZj4NmnpqTMimMS/ZcNtOsYNcx2nEu+EJDR3vFc3quPtdVzBmckq6yYC0O20ECe3YLGaKhLIXvMC X8BLzfskMNaJXNrM9FSV472T1deF8YyB57ZHHwDoTqKFzZPoVNluAk+DZtFGb5lpp1j9J3/8F/nt 6tlkF34T8zLeCIzi2aYAo4Gc7/RIPJxo0FWdPDmwiw73YWTbZjQxQaGs+WbgGT7ntAjf6w2at1/0 ZMsaL9gPS4ToF0st7+MnALnohj3drJ5eKw9GYq7RNt/f2ajsEWacBef/ms3UMzU9cQ9LOidiOTqe gJ6AsKAQLF4rubIuTVfNSepahE80jU2121xtAuw9WTUex+I3gQ1xYDNBNiIlVaFrrRnVO3Ie1viw SnJsnntvFxr1PqXLeSXLmDnfdpxD2kF4MOLTK7l4HSa0TQaJucPGBY1Yd63Tie7FYOzFIPkRdG1X O+olnYxE74o8+yRy+1GmmWGO5f54JREM1MuJUzUU4HLN926nSekVE62AbCS1TLu9El65PiPanD2O p7UDDjnd93dh0Olynh3OWdUP3jfc00NIZK6NQq/gwJCbmhmFSU/H2AEpXjlWBnNhFmS/TEFS7N/g 8A2LzSW9NclZ5UH+3IbjiukUBhdkm1yrVUz6sl6vW2MBs/IKMXLFyWx6ko/oyBipHDHNgqFkw59A sG5zX0qzzaCmFJssU2WyCdgVhmHo+7lDnNUO4EyuiV5iJL5fjcpRdmuNsYKJ2Zles7wk9CoDsonC tHcOeHe8JxgoS3H0jVjB5tIkvtv2SuNhNiD+wbdYX75C8iTFqLqZwks0DYp4ZDeQkLiNWy5am7G2 jG4bvtJxFuiq4l0xnugPkEp51PlkIAwKcT3Fb8jOLG3x1N4e8laXimPKGwvAhyH32BGSADBwl4eH zSuSMkcm0vx8MZxYgx1AAA74iaHcDdh7sqUpy6wbo/zI6+I/0n3a97U0XB8LuPXlbPSZyoPlzCJE 40/rS89rSHtRKIta/QyiIHEE4tqOa1v9sm5Y7CnFEvkOxcYWbstILv9nRjV9zujaMsUBJASlKI8M bNkSMQwL2MjEOjtr/H3g378+wTkhwCTBsOJFjbLJ+qByEuVhpaNKpSjPpmnH+94xJHFyqPRs1kWs 4MxBKvTv8kQ3Eir82t2r5dyX0zknU6ZL305y0oZ2yVfhK3yN2xsKjPS+itoPgCFNkqkhLbfG4PE3 TC+5unStJdO0/yiL56FcnuerhOTr5zYS6F2hB1SLUNlMQsl1VMR+UlqTXQr02bobT6PlbKtlOMg/ R9DOROOQpkjjkVMPNdUFJU7s5xhoe39uJ+W885D1/6N91sgg9P4NH5UKJb5UKYGNT5ACYJ+WeN4m hUWxU3c3OCsZp2CqiWrLMKtgPmCEzCHzUHACnEmc/mA17yGzUAtHXS/0lZmc5lonuDuQHTsnZXhm MD8243MFed664GMIhCQ/clcsBwnaXCapV8IhoKfPNhIorialVLv+boBc5WVcs/WGk1iCajozJORx 7lA+dG4AltS9k2Ge9WD2iGGixCXOPC8VDMSa0o8r0is8qGCKoZtD+Oujp+ZC4XGkS7hhjTqsIlAv ++LH0nWmsMkNSzxzbxMAmNX3B4SfQnlrugHtdb2vj5CLNwhkCqx4mP0HD5Iut4mAKvPRxP8nwOKM UzLu5MRGpEwZMGFeGrsJrzv8n23Ja+gAuqF9g14BPNxSJKJIsKdwkBJoVAcio/pvYeeVzgV/4kon 10tCymIlvNLfX+LzBaqe4yoINSL7N/mvRUnkPFhvLyEk30BZfNvWyuzF/7dU1RrGXRERMg1m3BDK 23XKt7pL/fyrKY97g2OPmnzVSLtaLomgLHAGKRlp+ZlggW5NniK7DtyZDcHNvZxHeSqlvpo5qgZM EgcqTZKphDPI5NhtFCqD8GjJKd+WPgkPQJtaHe5HhbgrbH8vEzju4Vbt3fzCv2S9e3eNPHXYaEg4 15LeGAkCtEVosWO/1dozVGOORUc0U1WkMy+B1Vr28ivrprjLJ7dkUmIKH9eVSLHOiyyoE0vvTwM/ D+WHswrw1tMnL5YJ90qsyLzMmpRzc0upQDDgAAV0JIdOiH86ANnxIKvsqJCfY3lL4P/fsaxu5fge sR5uDYpR3FT+3N+8zv021EdUIsbz3oiHdGE/hTkg72jHqi5xNLVv59IK71a9VDSxqH8NsO699C6R iPC4aSXayg10r5K627IwAHs0LVglCF1Iw4mH2WqTKlfnnAh2r65AQe5IHOAuLG8mQCDEUbwArEoI HeeNTtB20aVmsPVdZBPD4uGFj2N2qkchCkcgGeZMPXyaHyrOpkexBeU0OfbQ2Ww5w9cHmkLPw1hl cJFbh9mk9gClfpZOrD04iXNViVkXzoa+vqAmpTJ4nz0HxdSjW+6px5B3MMUG7hQs7+pIBGyTVofZ /PVfJuSNdbuZdPZR3IU02eeastc764i+lT482wQ/WADKpjax0F3yn+i7BIYG80p4nvbqEcJ22NHX tGA4rC/TPv8gWFULr++TGX3eNNjovlGAYD3qtn5SEwKQjfzMAiB6mwHaCO8OG0WwfiZOitP9kBY/ 7sS9VKi1oDefj2r4+TZDsrMS8/+R8hKU7L/Bh/ZmtwPik7nPDe5c1pftGVaj/PVY3/vC/uX+QaJf XRx0R+TQ3zeChjDIm0vwuIy6BUPl08JaOCOSoD0DC3f65KRQgIK21iiSKVqt8ERiPQWL651s48oC Qxz6RphQFU7aaGLZ54LZxcWpEhCutR5mTpaeN7anbdI0k4URgw0esgrhzfdmxcGNPODKT+/Nq9ux QHQE0E6+nNoAHi27JUZednXllXRoXRXORFUS9v7BAw0OBP/wgsuwRrdmYAhGYMhx/Wckiudiamae vADcBib0JxaNUGnxqYIX0cpRTyJxuNoCOEek79VNBttYwxkvBFL1+rD3sMHTWjbcR6zkZfgFiOHj KoWikxX+99t5mwHZ3NVB592rOgllSdU0NzrgKhpYgvjBmY7wJaKUBATd7qpL2cgrqMwt+cOqetU5 n8/dxiABLZxPxEeZdjinU4cHKBswkkkhpHgslYC7UpGtThyU60rf2mdvx50nWKfL0RO9qoKJeH8L WhKnhUyZ0H+ywXD64rGDt8yDdFMLzvnax9h/lJd61uQYLMdOCMAvmUY6A2bLChe+DOsnU526VfDj QXDzsY9HFT4ssiuvVy/9KfOrwqYAFnUOSrQS2xppt6dhsIoVAxjOl4YsjnPaxMVEVyMHZyaG5kPf TyCWmZAg5dX41gxeQ8T8XJvPVHgGm44Q49+ZAuvS8uFlyFpXNUgKNRRIUyxC5jaM7t6+nz9J3jPW Ji+CVHc+hMnZHGe0JNIxuHF6RRr07YAJ4gmGrdtKJoRwxWkE4xEnQqotiAwC8+aEFJZHTJk+oWCP sMohJd3cl93x6hmcjtv2b0wcCyKYYnnE1HjPbP8gXFxPn6zeFL4rpsSAjCdvmPgzBDxFo1pB0HBR EnHOBQAwXTdhXrRuy/s9xyfAnFTK2oV5330UzqiMYinSRGYs5o+gIk+B8ZASk52Aq2IehCaD/b2e uKX0/AHiyCwZyYng/b4NIPE62yWcQruNl2oQUKglwveZH3k/tCQZW9ekoXF0sLHPVLsisidkbB6M pFVmkc/x0RZlwf6enpxuJtVZy6Ud9oji/GkBg1JutRsfFG131cT1L6bk9aaFBihw9RJOoGQcyM4y CPWSrnbF7zwTEXjoax0fgspMr4JvunDuu+CRm5cU48t1lyLl+v+uEWOU++NdPjxxML6YMriGpefm NKt01j1ekgJcLxdCtH3Gyc2m5B6Jq9X6Qn9saon8jXEVwQ17425oITHQ3rY/gpUC/MjwetmF090Y yBdwDuzB/CgZqfgajquEmLrafICyyxv4c2IPht2gzj8jB8k7FGQfKsbROKTZ+AhSVrLvMSZaXjSK whEkLTIphoUUtho9Sg+XzGe6ZeDe06aRBwTd/gDodntK8O63taufoD71nmZYPIGfmZ4MnAfjVwkP wvgkAJVyhOHZD+iZpPHHoQXi58viQ8YMrLq9DUVUPpnqGO+eD5iZFIYAuFC3b8IySlD6jlLeTSuX Un3dObXeIOsNAohnX4SzvTzuID5U2a8U0WQgZsF7I1eQFW8jQ2GHtgdiqeOZvo4KTR6K7/cJq1Sx aKpdqlAQNWAjzfFy18O2TPL94puULAszOVHU88IBkqN97nk+pdGddgp7aWDomchT3zFxVJWtSoGz UcOYVEXKluLUek2RH2KS0hFpHxCs0Pypcq2OXus74VEZpE23qNTpfoMfK2yhK+6hluniXgkYfls8 edE4X3lOrnDJf+ewrRMebvLGYcxwSfep8il6NzeO93DHH0Orr0mOwiVLs1ajXZvjmEBlLmIhlrLE orAYN03QC2nAa5uyXV4In0kTXxrz6y2ymU/okkMMOLLp/p5rXcVPWJaSjMdW3reZujP3/7u7mqZS iw9jAx6heCFgI50fNKDZT5FA1cb+pWCCRMpuxJ7KL3H3t+33ph+NBiLJMM/xAyF/YJgl90mFHmVS F2ySS7WKTxwKnCgQsd0BGfIWckd2tSqsIJrvRxY1HB0DtCiImC5I3YYRQoxMMXQFC2sFfIelOY8d DMM6P7Obs76wTZ3MycG005D1sAo2huDeoHywdIWd8uMek/TPUcCbSw+ZBQhvjhNZC2KWk/U8fREb fqfh83kBtbKfC7X2+pUmzjU77QjYyM4TXE76I7DIm7qWQ+cUpK9OyyZ77GJbA1a7cQrU/YJBNRMe aAP9Osgel1k3TJ6tJTzoR9UF2ylMH2NraeBsC2xda0jx1H1erNUGQyp76bnuTMiSfG7RFHs6667C XNqVyxG4TxlAoihMko0o3R/qpuS6w47gijGN8m4HabHnlwDK6ysSM2fwZmRD5NbpZIy7qsMN2gqE L6HkdLI+/JpQqLsxumsshhqL5rEaZ9SqI2Pxb9EYYWn/Mvhs/+EvdDL0CEQEsJMcK2NYyaHq3YuK Vnebrq2SJpSjVhfnsVyc9Izy9kMNKKyoNJNV4sQ7+vRRvcwPN+G17GYhbr/ISeqsvCadbITNDcIv aDL8vZoDI6woO3bQ4l9bPw76mjLrHJbjBjnX3OL5zCLcVEtFVH1c+MVZnqrVzLMVzG2c6XIIDMJ0 h2uwUOJvyBfVf4+IPsCaBp6zPz8gf7Fdle1/l52Qr56EdPdmEXe3Gg05HMSGSAkpnjjw+Z2+Dent e5qFVdMdLE8uSRc8JxZqUjbRBXpUxRBbskvIRe661HqqPufk1OZ4kb76pQwYUXJASgsCEe3aOVlm 9N9ICaL5jUOJedzSEoJmGTOcOZBckB+C22jt9W57bLbGO1RffVQJdMbhVgxCBklKmzAZ5Jdw1TbJ 80FxWhk3cPmaeMKxjSbOMH59FTbGgJw3Q4foE//W4LjV4kLmrUj6eQu9dcFde/aBgJFEMuuLvidi +2sdG6x+NT7rBHggz9Vw5S0xEF8aQL39PoupTaypkCJGkouDxAGnaHgUzohTqa6c5rnM4BwHCZ1O +75hgxyjOhwK26+D6XJHV5SMGBBkhSFLD02vumnzekjXL+0961TcEQRuUftjbbPwRufzGwfGFINe aOX2jjqXEep1pENciMWfiwijNn0SOdURwB3w+717xdzm/lI7hvnJfMZW3/U/RKR6mtoXDV+ijoyx qoH0NPCmhgW/EyWSKmSgvIQXG0sQ5VLypZLrRIBLU4c6aX75H86z64ovVTocoxnxhkw9EZNdkkw0 9RSXKg8KIwwC8HQBo3Jlv83LCxGSsRuw6MmHCTfJSpnTWCLJfRlLCi6GH6lt4/a1/TBfDLlLW7UN AhVzcMRCalDOScyHF+rQR13wrkJe0bjwGL8NLWx0Yit0ES/sN0fco7YJu6KjHFM0ViKvQUAuGeKx +EfgTGMkZJnzRV4B0WSDO2lmSfYkdl17EI/OxtXUyTpsu9TBR4XDyoCZJUaleWNaylpoMtIikfyp VCq+jANnG0Rzec6Mpk8c8Un1lSXBQPwJnZSEGPxnRG0dW/l3z24YxeYUIhzL0MvIVl+KltdQiB9V kbjZt1xoA7k0jy6GbN4+Izt79u3AcfGhnhJiaaNaiaQC50FkPT3uKDf5iRFZBxKEAWuoEL3Sl6fT I9yKXyYiD0w/kdZeqT+8Nmtix293rSnprterokk8DvrBzv3hWv89kved68N0iwvGLIp8rUtmCfJm fdHX4KMiXtHCNfOCTyF01K+JyGN+STeLLgr/AJpj7TociRxSXFqEY4z4Du2agOeT0LUUtuMSwlCg CimQlk8BCzIB3IRtc+YO6OpfnMNlBX8zGYhDA2qkrp0UsAIMafLWffTrRc1soPX+AJglxrXMjJVd c4ihyRZmp/aTOV4o0WET0MtXM2jh9f3Kfwsw9jwFtlptX9popMj8YMwOqammy4k78GdzGZFDNiO4 acSIflOA9t3CxLXmoKhHuVZ3c0g7tG9UjtNmB3LtFgfj1GEK9C3FCBCWhIxwsQIsWDgy7wR04qoM SKb2GYNsMmokkXRQP9+7YZaHp+0XrFlKyfcKJ4q3uW4HV9xL7Abl4glTNKM6csQpLkv03VqFZVQD QckLCzY31fNh//Vb7KftZPunp+Mpg60LUla+e+LIV/xf+VR0Ff6Dhu7YD/WO541ApBUK1s14XnaH BCkAKOSyCx6IQFnRzn2FjJEStpvloVpqWWJuGOrelvSsctoh9tWkJq3KQv43Mmv+lz/nQ1dtiFia Ak4eS/iBeHstcgUJfS9v3fKTl2dkSml6Kx8o2bUhoSFTU7h9r5HUoUIUBURGBJdbe+V/5aHUaaoC Q5A9sJBcGZu0swsS4zyWFPC6NEEPsAGlEBtIwpgieIslBQ6uU1ywSGB5A8wgrht9vt0zUf9nqwkj C1eatsez3G3h2tSMfoyj8799E3MjvSAPxsA/hzWtKF3505zN7Fxr1cmDpYgf+pOSSACBrvjFFQkC KXA8tlKC2Wu0cS7cCNknMUqs45l4Zg35F7nKNPcCchKCLE2kzxvEuU3976wVlTIttPV4+EcRjSil glcN+yqCeHO1CD4QaDWMAOIbkWretVW2Ul/iq6XDEkSuUuEAIwrYpCkcqURgO/X2nYVwd69tPTsn yXmkq4aKhhs1PfXw7g/BO0wCCe/uHbt7sLSQuc8/eJ/hhOekQbPB0xofiU24v8QqfbhuqjC3K3F5 hd5/n/ky8zk94NWNDzODnKtSF7Khy/lkLvQFE2tSesou4lTaLxp3PgKpPb7X+INZuI++P4ygNNO1 z43PhcdJJaVFDByXCu6YZXzKPclePEBhP+uP6R+IDO/iB6kY6TAm2BSTAw06xWEtmfhAtUO7G4Au cJIBPD0AeJ+MzxAup+RxcydOt88nfkBOVARCugQt9dSYKuVIZMCO2RiY0PXv9Fk5HsrCAmY0ZoPb CjLb1yiprP5+4t7dTgP75rhPPMd0OL+/8XmaJbGWI8p533imkQaRnDlTBI/34Gb4kAeIzsE3MfMX taPXdyr+oAMBOzCuVE5+UX+PsnjfVuy00Aejr0Jn01Lv0+PfNNltC9itVB+dYVPCFnqLp8xKnugO JXGMDAkwCAC1MbgaSQ7wvL0/88JXRdgy0+mGS/LbJquaIFIhPqO8/64yFx9NcLwxwnX5vSGGce6I xRba6k+SwQh0CFWBYx6YuUouPrwSMOAhPzK5P9SB3WM7d4LWPXsV11BMFKTyFIiBPJKWB7HaMqh5 EKaR/TNsz3AMGLX0t3ipCt2txRxWnGGlaMKwIWWk5hunJnxNpjBCCrkCwnKzuGy4BcfewKTbvCOS eOe6Jvw43Ds+2haAGePMinAt3X2rWFkDYI6WOQ43ntRfIbSeMXXWVVX/cXXW/TQOV2IWHOMexZgN Oy9jf6Xus8JF+bOOgD1qnPhD1YOp0rdMtnpY7rvP47uBkLzYSUiXb9KYlvm9jEZHOUgMsLsyrDn/ pZXehSAWGPewAhqxQ8Sd9cEhfZCmvylLc4crbDQXa2P9FclcCsvpEjaAcCoh8Rh0HhHUBKKLaDhL WHFGFVvbxBCq2sUjJYOX7S6OG7OkmsUPt8fzfNFS7DEzhMkTTklW4RnR5EccFakKdgp4C1+UPtkp rysaIcOVaNg33rxfysNHC+OByJCdfDmCzoPMmRuoh/wvHU1MJJJ7/1bSK7z41cfbG7HcClas/pEF KRlU9aCyt5JkcYU6sor5Vu6I3d6zRQE3dmQHnuiSys5ysbnQomnrekdvpMgQZU0lc0dVtqRfdu3P zE1VCpLmhYyatdz0h0UxCHjF6FjZYbTNCRWtIM/o4wMreU46OaD6HjizI7YYYzasx9w8zctdR8Ee 2pvYozDzwRKpfONtKbYpPp3MJji8rIR3cRDcSsMLpsPTKvlQTi9Kw7dwMFT6ScC4QblbFMr/XIp9 tCmN/7HJhjg5nRdX0evXISxfb3UezgVB7UCtd10X4USmwDZyej2Zwu/XQNV3KvbobeV6f7dk12p4 bmcJQQPi6NxaCJo7vFsTZ1omM2Y/T842JIh+Maw7H3v8vg8fYV/LJUwPvIMtwD7Mo6eKC05qVE/J 8NGesoyF7kc+0QdTrGJNzpa3rrTEWQu0xcbb6gwzclUqtNFmtA1vPsOWGohjwARJg42TMPX0OLFN PlIqKxmLI7WBDXSiifQac2utwZKa89s3TU6ALf04o+5VBHwwhL4ibqvF/3SGBV+j2ZDcaVNt8n5e UMX4FedHfh2LmFw5ro3avGU9jRGKOaimppMx5CNbIPdqd80lEcJvdFBRDvBi62TYcNehziSKP4uF swrBa8flp3cKDzFu9Kv7EyToPPv+YCfSM4U780S697VQ4FTx5jLHGsxCKn6scZ73gNwqxGgEN78U 26KVbGT4h427lnLUXN1XGu7rl9EdvoKF6Rb1a81CLeTpjfGEzlTLmBLumWx/8jPeR890EcfyCrBN UXIsJEdw9+Rh47hGzGTWQF8UEVIS7BQ2TQzCPMIfgC58BQ7V/u4Fv6yGA7bX3Z90nS2wKYwEjdrY 0ValpsKC/9BihAEcvDw3kNzVo74O9cXrWdNucexO0BYCblOINhMQqfHCa6nWZcMxuWO0R0VVkGEp VCEWLhWYJwKp2A6V4D7qM9rsswC9bkx8koGNr80vSMElxyyWFCjjBK6y70Nkb3PuCbhJwfVCLYK/ Li6gcMLYTf6y0PfIdJL05XHEAdNOplD7FaAv9GoT3HazeFdpBMCeJx1OQoJOSJbKttbsv/CkKPop UlpAyqEFrAoUTff8Pt2mx3JWRcajh/yUiPz0KenDn6ZeZs4xMSJugeac43qX/m6u9RZ6w6oeBLwr oXc1iClGd+3P1WVUPmkr4mmEodJtayc852BXGI0R9tcIEeb0q6jsGsn5y2g86GqTC5p4dvvbnhOa WvyMaq7Mo/0Z0oOcNsJt6A5owhYnAFoKWGQH5utsS64RebYDJnPdRBjQl34NcpSJC3YTcIP0IBlh cSHnTTUjiUmpk1Kb1AyPV6gsh62es7NwJxW2xedLuvfs5BGVqrpvhwQ/3qYv29D9zvMbEQRPk75x f5RNaQoGGAEY3GVCWwORWKozb18x5IyI5kWTQZp35JAIHGWMkUSnUUNAsB/UtRsWfy6/kSA5VoW9 bz4SE9ysxi+jc86lz84yU+Gt0uL0FSLVV4BaOGOyS1vLIlImtJHFXnaIAkre312kYki2awYZNCMa O7jsrp5eKNdRwlhuvGzrmn8o0ibppRXqXyJ9wpxAarKhWx4CbJrAAde14xvvlk5S1lI403K+glhx 5gyeNTuE/zedaOekbClJmuCb1BbkuDMHSFrDj8/6kaM67Zxnld8NS+RDdBvrhxqD8MFBizampZe6 86rNvhmHlPUMNbq0E4Hqr/3TQNjjY7+dRsrtTwzDjaHvjHPZyo53tVxnUqtAL4XuCZ5zN0aG4mQH 9brsEwDMUCBlOSTt5NGowseB93gC063tvKJm6f+dZyZ8KdbeczrWhQOKd0qeaKzcXJFE6Pio7Gao QMVJ5PYYXKCxSzELSV6Yfw1D64nr8MlqoaySLfXqB4pbeqk/jPE+bLPCsTGvcE/UA5RsZ1X2+SNa M6ba2xkt7MnGdn1c1J35nF3DUSp7g8QOjXGnZS5FqnX178tocs98lGJVJlN9ZUVYqylqm06dkgCA OghuC5vaTeWc9mKKQ3KY4U0bNEUAOD4RO4qOOEmnAbtCNjnjNux3khpS9OlQPQZPIGkY0s1Obd0n x0x5ymF3NJZOhutxiznyjYB+DwaQb7sExQUeamra/eXLjo9id2DkWc/x/YAqAlOxzCOdQ3hz4GNd 6P0b4ytPfXHpNvOhTAthKdi6f2QAm1q5I3Vj5fdSEGgsv5/RTiD/8xnxR+veX+IX1WDwBhKcVzpE YKPAaOvfhDul7t6pw81rCE8W59Pv3zVSXkVZnNYfOXROUBmmqpVb3WS1jxgnJSjxZkzlbDIxkG3B HrmQAFsGRIaaCyFNLAj/Tyoxix33eNk993inYagKzMnvbCKQRcCnjC+BmP8SnRbjyaygBV1anLW7 +zh3SHPmTvft1u8RTB17z+mCsIN+r7ZihT3wlEO/MoDfS/MqAeAk2qCsnOZ6HyUxz34W20uDRbGM mDRTuPqdDBEfXzcJAhFujZXtKdcV04kQga/sSqjqewsiAS+vckqjHqUOF/MgmuG96tT3OxLNXLV7 LhUS4+NZWsKbBiMdWc8OmiToPgMKlbY3bjUawARXMI0l2mAcAiorIvh69SBeN+ryOMq/N2cs7t+h CQsspEJ3Jv72/FY9mNinj6R/ormTmIvY1fpHFrYsWQO6Wxh6kEMNgE5Z2PgEAM9N5vxCEjgWRYrm NRnxZNKg1x7LB4clETjoMn4l7FeIQ9gcuUzh7F+pa+4Uw/e0zxuiw5H4hlOGnGm9MTCuaJOHh+PV IDObKFFWBe3JBd7WULEmLfHhhOgp4bPbkLmIZkNTfPUyB/StgutCotRT8mnNN45dKpZM24VvL3Gg nqyh+/yXOh+NMnw0TeqwLbmawaVjHU15rbJwAcLjBLA0yMvdcYlEIpsbqXwM4Uw1v8zKTaG/oyMM RYnC+hUxY29/TzY9HFJKY1PKB7F9A3pVRjIBba4d8Ca2KsbnKVZqy/HMYbqFtVws1uRVfB+6Mwi2 y84UZRltgaHIXU17dA+gaW18KBVHgx3k4LsLQu9nFz11Ak5dkdaEbWYZ8XqhjbHQIpWtLmp29yAd +g5Ez2oq4PUoy4M+9SHgAWYFu1HeZoj+3Or3FlNUFC63+FtTppcW2TL64uyNYehfBOTA6EMfWtjo o7CsBOv1kZguCm0UcvHs7eMtDb7ppyrYU2osSxE5+Yf8NArPBuhGk6nRD9lrcuwHCpOGl+1E+d87 XkForkIqDT1MphRc/FP1yLO+uDLpZRsVNvKNYJrnVmzO7FjVcNwxYOPUXt3DrWt0yslLoXUwjqH7 j+0o338J5SShaRn0MhWoj3kXwNTe2Ml7TTDbhKRyUomck+LX/0psqYhK1CAdPx79QNZxu9o8lhWj wL2xTNUjkj15pPgdpo5L0aibL7ne7D4RsoZfQXnqud7d/fh+ipncWKl7CuzSjOzt3FzcH8XZ7+ek kc4HCeZt7/h2RDSaYrqFCDNs/DiSS5LWmLbIZGvE33C4nE3DMFpksbp3ta6TTH2qmPoeMPu8SxDi PVG9bYEe1u3aBV4wzAvH7y5MjFpjIRfRRJVaTqWnK+jmEUVoZQWSMRXSvLHiAmaDAO1j4MQ02TLu Y2YbHyvzijizKVQLzRDXN3MNLGBH50+GyJyU+btH93OMRMeFLv0JPQ/kDVaeU/+kD1IolPJQFy+X AjOrge+nvVJvvWqMIOb8wT/el+6QQ7ERzpswB5dOctESdEERFTwl/DtJ0Lh+S1WGZY2roJ2f9bcF 9qUS19GMxNu6PmlKHpLKeu8dWJNxYTx8i5/9JNH/YeF8fbSjg+iPts5bCs7ZAYGtSX7lBxc0yTZY X5I5D2JO2AHErrUO30RJ7e32B9UKm01t4RBvRkMYJQkVLGjoozSoKtnACC1D27KxgoOnyGo15Amj uHBKyRnGb6ZAKZLZmnNv80yR/binSsc5+O8MUWL2MXmk2MnOBLFcLhcT5hq20WSZIDr/0arKHp+9 5zYIGCYZpQHwbaqbaQ/qg4CsgH5gH7+Y0ziEOfQ+8YTkFCWdYrtJsi5cP5010B1/0RZb3JPVC1rJ NaytL+Nx5wE6HuszU9OhS4lMQAO2P8McIpdsXWMQT9qEbcao4rgJAEUb79ZN/o0nuIasD0uQoXqm Jhsol7fxQUugHs3VOzhLmnIYdGljs6wwbCw1AiQtUAjZa8NGOp+IiCHaD9VbfSPl9xDkYx4vdJf8 oIhkd2/2WjEVRWU1qsVdtEpwa+zp+D8NaXiB5iJhAgvXEfdemv1d/igigKgyphGZcMlsyOgDrqIU wcJ9uFNtooYjDaMljuGuQCuLpGjb2ightuk+Qv8QV6ufs1SDJR2UNRdzqDyjGwL62FpK9fCNi/bA vw3JXQMMbg7EIv2MGBhyqlW8EBDUEYkG6p1JB9+ZjaemjSVID0IyJ26vkdSjffEUFkn3qWcemTfh cgHk6DUFQmiFkomG4ozWIqxK1GZIss/F7UQaYuJGXlNpNrCbJdPmHy2VisZsnIGDWwn9go9xkl+o AeJqPWFvbBBKcjTW5ZZfiVSJkzBZIc4GrCOJ+KdjP+0FneQop1Z/NJRpZw0SoMLEd92Ss9hhs/bs IYx/iVqaWEsLtcBnYlqBTHu0p22cPp6DcNL8zqmFNegXoh5zhVXVkr5atnKABU+IMriXCP6l4qfO xINykOD/H6oT1e8MEV5dzSn/iN/Ux05xX0DI4eNBpiqIyFFDJLWyGy1HdFzrSxmZiZIRxy7Ry21A RUD+YmXyZPOqfy6e2e2BqBve28frMLaNDeEw3VHDhMsl0au5qdR2mVk38Tj6aNil1Izlbd0HPVw+ UksrwLgNBOc5L+bzl/M9HwLOLBIPIDvGdRBTJFS69XioAFRelfKb1GXSa3o6aZ0hejfigUJ1+Ggd WFGsz1Gq0qrY/Mv7w8+/JbwLRVudGRSYkt592wm2qq5zDFFRhXZczrcqYpsnkuIvHEWU4Wjjopwo 0o/jxo9oyM0kipaIgdsCqLI17T8JlAfJK3C67vBLw0Cka1lIon2ndlsLTvhvuUwkRfo0iLPiC1ao RL+sieu2+DEgdlkwdW1Z0lKbBGg0K5QKy7np9l5s3VmlexU5ZDj/Y2O/A7HfqP4Cp3WkokOjSTsn ozRhdOdqIHW3xA6MQqGyBAeqsPEjyu4H1pLwNLVucAGUexbTc/Z+wnrkTMDL5b+QqgQhjj/CrW0e azUd+gtbrFH1q6h6MzKxSU0ynaPJfWLNGShz/h1zu+GRtj2Ty1OPeyY2mea1Xj9i5opy/9Kk/RYd /AgH7yH+cyNJOJvGBnsQ2+64K8z3q9JoW3CxZhRFUBxMVsd8jVnhPap3ZLL9weu03E6YryX9vrlB p7nIetGXoQOxBEr/nn33WRc9jQ/jnKMsK1wPnXrXXFk3dUTiiPdIFFt9LPO4s/w7LWpwzxubNWYX TRYcAZHLK8C1Ho8BMFUdPHXOXoKtmY/nnPKt8pHJcHO7WBb4MIPL6j6CZFuSiieOuK/9ZYZ54Pec xMmRWJNCsLICImadEOpU8X60EqqTeoQSE9Y6JcgdLl5c9FaAAoDyz9S+atK5lxeNbVZU2qMl+7sj XklnA2vYZKyYfdI7vWGoDzY5stVOxOPMaKJUTEa9qsJqPUJjr31GfuodK6Nsy9Oazfy2WwVqgib3 QOzy+dmoRt6/wu+i9X4ZArccPkUJkaEYBxHH5dduEd0tD/mjMU+Nhq7V5WcY2j0Y0Mz6simPqCQ1 uXLCXnI0s7UCUUymWvIQPSOtR8CRi2UQ8EHU8UXBA82RnY+NFqWutEXBZThBnvEbKPKNya/quAzN 2VYe4ekHWXqen72M4eY4Nzn3uzK3EYk9jJO036J3GHMHEPjy/424D0npyy7xHunNXFFJ+x0UmBSP QKR1k29YQI9i3YVDHSyDHZBFdjWIQK/unsjVF31gAkNW77hSJ2kVm/ownxZjv9Cz28WzN1SRJlVj qLT12PFsyR3ZGbF/OC8egx+jxI1rYYkNRwWFkgBv6bLobftwmNolXHSrM/K0gkOqmcaqhY2NuDDu KXZNue2oc4b77NeAC19M9L4kYPX1P1fOOCBiyJvgoN+BweWdcOpVixANYrEBE/coO75cZQ1X6lnv eE5GHgxE2rlxiThkDOZx0fMXWNM4xecuhuQ/pFRHH9MojD3NKZBD/4evxbA7yjSvxDEHOhtUMQ9A mAxkKyj3DH0oqmAm1FGDki9lHJsxnoN0suib0idfXZ2zf0d0FM9r21yJEM37NpkjaGIQoi7+WVW1 80Ovkt7q3RWhLa8DC3SPHVb2q2uaqSNauUkt9dttdzDH9XnsI2mnzkkkWO/+acCxg9BgWp/nO74R yKyE9sZJX4Ey48UkiWMD6EaDGKOpt/NXIANq7kMSqxOr3V+gjyd4kVEcsg3D78wD0fHffzQnCE0r 3pbUEFfj+DCgD4PX+Na2e1rIcP8F/nuAZeTWqyF2Ik86TvV+KUok2LdSANeoX8HFFB1TStzpsb7L Gutjiw+y6Gtk98dsDRPhsWOqftMoKXcGmX2W6S/edkQCWSfQ3i3MvwrJo1tbjOPETjP2i8QEzFBU ixnyJ4eScq7ahaki8URwaBjMMMZNUipzyD5+Bh538ljk2JoYH86RB/zWomKscLutZkaakfA9TnOU I8/lQ/F46PNpnW2oXIUt7HmlGM6DA8rDDqaHwFV3C2euLQAmU2ow1MfhwcqH9dMnWeuNURtetYHo A7GHaWJ80484zftZPtPkWW/f7TYl2H3BtPy1FV0z1NJjR8hw3hHb2/u3DzaAwSus83iv/RTfdY/u 8JdlPbGNfQ7NIOwooX4CmnydI5L2EfrSqRtOP9Xoh6wtyFIs7DwjMAk/5uStGQgQoJ58gpmxCBcd 7DQ2ifNTFEzuCiDXCmEF6u1AVPHDKBqhTDB3qKaNv+iXsrOZl/LPCZQlvPy61k8ZqBtTuxuHU6EU l/TzDz5v1OlIZtDHDuaybSffLfcx0XSlxE1DMaNy7epTRh8Qk3r7wQE7WAGLoIA0Ylkdso0rpMId 7OEY7axt36ImGEozcYuLaImlQfCtLT38/95F7BEzWcdabPue9qWBnFtsdAG+m/F/LMsK4PWszb/g wxsMODIxbxFySQA4nCxT3kwA5yAVRV+sbXNvX58qmORfGxl3P0WTGtuCcW3Itbo5rv8aHA5WoTwQ 6lgqaEPKH6KY0GiTw4UB/8ccpbRfgYyGUUYnGkRKWUG9iSmMZhgwf/wGl8x/dIMi5vpsyw2JwZux KIvO1yaR2v8kXHa/AMoJ/naKGBwXh1kwO8pUqPegP82Li8MlJ16T4o1WjuZnNVdveHE8Yv7NvkpC 1alYHfdsdQUsSbYhY8fApGNfvpg7xHWVw/8AxnORDD57BMepPd6nElIeGTa0WljH2scKgkcIDGHl 23ALnlKw5TdBfHplQuJOch5DkZcRQFOgx2K+rTVUbKh5CNi9CPgep09digSBB50bfyaFmQmGzLG8 XirbWarxPOz85fLxrwhwgQqzg0m6Br72I9Gf2ST+7qeprCheeSAjGuhGWIWDqwyVZafTlXN57RYr jc7V6jzI8/8y5wqO99depsyzcVK8t9zWZAeHsF7ZoihaWw5/WIyJ/UYfHgZYZ8HrGyuqRkC7U1Zb 2GDfzVjc9iEkPFHn2DPe+F0vZ9Tr/AqxBUJMmZFNtZ1zXllHZWvzxYnEfYWackE5CjwxCdzG9lFK bAOg98strHi9yroo43Nb05e9X8FYfQmn9wFx+/Gn6w/Coa6h4b4i2cGtSbeHL76kZPSpwDduF3gl UsQkixW5ttkebGvXNcTmxnHbMQHtqqMGi3tGEv1bvHKBbWVWs90WHeLpaCQy/eMqL8Bv8ABs19oj wSMoXXvx8khQ2/jhXUhf3JgsVWUbFYA1mMY9c2UDUB2//tKn7KssoI+5OHBN43r7O7j0Z16bNE5o jCrfoOjl7ud/2JcM+p7PNHyNGy9k8ZlyE31vHaRAaQHvVqvd6R01FhHBZet8ATaVPnVgSnyRaA1l 2jGgmxR42fXWuqAz2n8I1/+kIFQR0u4cuEHx1/+K0YhXgnh/ha8eEU3rpYGIo/HvV4otOZ2Le6Yl H2LAf0F56gel56jIYSHysr8vPK4/CoX8bR9+HfTDN24sWRbcU6aq3IoPh4BOEErwqb19dW2DLw5F M0VICtW+o7lZG2dknJCjWSXZzuNZWsHl2fefnUeVB7MXV9qxlglCEeig5cPunkVU39hme3N94HXK CEftN8sr+SS6gHZM61WQhU/wniPWZykSjBfG8oLS7+bzGcjx3aICJwIUWHYxddVRu15V8Lco8NhF C7iOM3fCQ94pHHI3nGEnt5uEVxSOmC888yNialsglB5covJ6cyRQxsDCsrwSqBd+2JIoGYSxeEzK LhrqBvlYmo/Q5xRPaSlx8XA2s+eUNagPmou0Q2h2cj4okfGBua0gbTAV/IuQZaIqtRa/xQeUoVRm XLUzMEX9En+Lv4PMjUPz18ypVbRrkqmxKwWotKSnL08aJxYjPvl6uos29VWnFBgHnApK3QgiB0Y3 ayCLNR+hO9Piq3IRHeK3AL+7Rz3lVWcmTWq5o1DXaeIRd7vqjcMjHaxvC9LxKspXGDrBxO/o1xMk WDbNSGx7zhNKrL0QZ/HNMMXOIQMYChLeXQXCRVjFp+6mR/Aq9Hx6KgVrAwF3c9tHupdc7SUeF37v X1hKkNKfcWDDxjI4cpnZgk8CJGE9vty2UmETgzeZ5jKjOj7J+b55+WxNSydFMBMlALsJV4XDq6Cj qZLaoE7ueykZZ+yO5Q2B3FhakL3aMlELbhluO5RZGJtSj0/BdfCXO2oAeYw3oS8xI854b98nOVOw 5dDMbs1ztejqClMrAtbou+AhUdCvcipiRMbB0FEIslHDXcJmJcsF4RuQuONpTn6lsN0uuLaijJe8 tou1iIfXdy5irD9nI4syBoNiYb++GTRsmMH3TnEr0dQlvfV2FvUOvbDpgAZPTvgP9qiiQBV2P3E3 6xcAViIK8bqVoCfMaD04QFn2w+zCHd3WE2LD7dgGyDNys/SuSw5+2mOiCw9UPJWeY/OtKBMItorW tLt8wUZe/hxTVimDedE9cRSq5IPgdZdLkWfhHqUrXzmGuR7vUMOJyzVXe43l4mvPztRfI2NvUSwm BEszSzt3sJ802rJLTvJd/fpyDg4DinD9sh/pv43hZYE5ZJn/B+a5IdV42ZLocdAFdB0LNDWQ10K6 rDQ4nBVbqL7a7kzuYhFxvZ5ORn6WGS7SWPFXRPTSjG0OtjapwJSjSHX+ASuiYrR4m6xgHWKyegmR FgD7tPpnH2JKrEGBEzWefAtae/E6x5GFb4Zpa/WBVvZzJpxy84M6/h0FTMWyHZYEvckOCvQtFr8g wKhE4JCdXKYZVkIpEQYCssqnIT4YI8zjl7VeJpDxbrYtMWo1xU0sXbGxUrIpzRUsAP9f8DvkAqmv 0ORwlnALsfqG6TRL5PY9ZC5d7LOTIUnRMxZipcZoGCbcHwCeJehBIHUiXH0X9Dv7AE19Z7B+plF4 OGUYm07gQQSK4eutQAa+qXf4yJIvSbQ1h0unoq9e7ILmx1DnJXf4miDyVrUBea3Puya3mLjKuCJJ Zh+xuod00/5opLHI5xq15wxQ99jG9tYxamEViRuPYZSeR5tAj+UsLpmzyy49IFxaHVSEJ+drClL+ DqooVhHBvhDUrbESJBA3Cz/fWFMoOG6s5MTs8HdTFqmSVd73U7DUY7kcpOY9QYtokvHSojwXhAO2 +XsZ2ZnOeLComdfDuSftP+35Y6gSSwxxk8e1xTfMUxMZbGHrCY6vEYkA3tOA0nwilriOWbd7kova rGSwOgwWmqi9Q8VkYgCJHhqz18neQsCtQt5N4z8Saeywcut5/rwIdckh3Bl9R2dy4Qx3/x/uATCx OCMVlYkhxF6j+hF6weAMBsvOErGUXnVmYwF5Mlyrwv9ZoLIabEkwPy+dKNfbMwKNtf6D+You4NQa 8W+Egcv4x4/eEqA/YOO13hQHKy8Ta+qEdT8tWc+TGK8GCgLah184lfiETn7LcK4QK6nHTXeVkDOj 1Mz6kvPVW+xf2b42VCQ1F+UougWt/6fzZf69bvgL6/OFQcAIZSFrcBIjiHRt+eBJ7OUS7y8FrWIY OZ8gKP4u2wm7WrD05mDxY9zZQUpVb5jJcTGELLLNF5aLwmeuzlKmg7VAwlb8r8me+Bj+F4O1Rwqy MNphW+ruqqP45r67R/Gq+r/WSl1G20kNyamdPfBCmIoWQ9NLdudro4dSdxR1lgillOeqocenye47 3nZyUAC1FXOVzFa/rzrE9Ja6Z6UMiL8HS0uSGqYJ8EbA4vJAaKpxjpJB24V1bB3J7opSdc55u5pq ueRIbvHHTYKgDlmHKla0pktyXTmWGQmo8ljcZjQcSESXZu8FkSL/HaYWVve13dOxTa0mTppXwkCE E0cTEhxaIR4EIeejr80/nLtNCIzdzs8cbW8L+p28Q6KRm+dh8SpRzR27QZqgHSRJm1kPUD+WBsav ONBBA6dQzg5qSqoYP7rR61rJltAHX8xbFUX/fVAHj0wS64gOmS8C89PFTEWpkfkXVu1/0NUhxz76 BgWlvDQ+9d/vyCnBkJC24ZS8vDZJtDi8NcXj4by7+iOET7GvaFAuirRVy9pdNaFt1DiGcKAAADGi vzGM2F9bjcGcXkeffREsAkVvq/gNO7ShdY80E0TeehOjpvjQOgc8WjHk7grbbBCqkcid4gSHWKBG MFpdBhStLECAqbqN61yvFfKfUjM7JqvQeEC2ql7h885ERvmhyS8V/2+baFv5o19HEHFngZBYlkD1 YxVOKjWTUo8dryl+08nSHS5EsosSAcmSeG1ufEVpwG3igz/PXCbR08FlslgJPAV1vz9TQIRqnGgv S4QtAVE9NKTHOuFGeQTHwR5txOTgEbnmPSJt884wlSL9+Y1KcPWlr5TOBO3K/61gD5CnpyLzOMD/ J1sw/uC+ZxeJhIu/LQZlSMPIOmM3w0pNYZFN4eG03UlLEzgBhYBLsTWYsSAGomIYQLNtL7p0YNTd AqfuwT1HML63UJzBhwCazcHLbW+I7DJs1Oo1ZlXxgrjIFAy2+Yw4/8d91pqzwbfhQiuiCTbv0rjE 18TYisfxAeLmdF9NGdm2cAMapCy6iGnJfaTM0fEAs8+3ZdVMk98jdONR44kCAChvY5fiPIt/RfIg YD+ILn+JFBKAsM1s0UehGoOKFx4R+gfEPSUByF4t23mA5B9IZbi3x8595JcURtGlS0sfdO8Yxibj jQYjgNX2KX3B5D35JmMVxpfXrzjo1AMo77FRRslmAu+Wa7Ylyi/6HppTyrZ4wwRKRISdY4ZT4y3p nVZAXjdciDM+3xjFkbQFOIA/koHHzWlkz3jiSsA9WH4U4nSipeNSiu49VXn4yz32ZcphWP6n9s5h BcD24LTD2wRRwZt6e9i7QWgppkc+hjZWDQZQVsKeXupucen+UBB+kanGUUEnj1JCgNSN1Wv4mTLB a1r8jziD2nNKAkDC/KqkqkOJGqgkz1JU76wWc7jvc0Hj6pBl468cj5Ang9TKh5/eZ4wGMnHJpnpK Zk0tIteA1Tgyz+vhzoZgUMWHL/32tm7jSwETiPDg9hG0tPTahzS75wMw4Y+hWOApAarQ5FiTcosi VNEyvjpK9VdzNbrYWcHpIb0+UG4ue9MxF87Lkjgx0Cjg0SoDcghY5CvXBll659q56lTbRurlcITn FYT9kPm9rfHjW8dlyiZmchnPt7ygnXqwcHEGzdZTGwJuw1UliAyxtZVFQAdoqz3s7AGgkg6G1uHO nPl52YAyE8ggX3LndvQnHVB4RUowiQIPwcoNgt9r5nJcCRcgoICV0tts8AJaJmLj42LAxs8puHSy rzFeItRbmxcj3Klq0iC9WJuYluBxV7//ubdisOI7hlrHU0gEZB9V2DaYRrb2KpcK26YdMPuRqveQ 6nmOaeLqC6CdZ7EzVnc7Ba0at0/kcD9D169Fkp9sDJ3ICpUAkeQKKYHbhpPGIwoDljNdLxjKWQa9 7g174s7SEpgcE6pKs5VE1gGqS8ftrlaU1TWOW78TZSr2tclzPW9cecWcq0dzs09z+/Gh3MXnL9eG LwbeM9RHZHGop3Ps3BAwVxwC30us+7zLivjxODTvKsr3un9q7OAqYLfbVMKnig1dauIFz7+SphTu dwXy4XBpzJwuwFbPXwCaJ+9Jttlm6nHNruHP0QMqr2NK0SPZ4BLfHlyHIkVTs/isyFpbUe437y9M EMdoP+HCyqi6RXdRylj1cyrUPLRYtr8FyxSyOkt2YfvZc0cwsdhO5CO+nDbKLJUIuuRoAm+xRdVX hXjNeIdCH5ULIXxoPMZi2eK+aaqn121NFXtur2XAfcRPOZfDmihSZk3vFanfBo4TbAJ5BNes8UIf 6VoapfUi3DG0lkNRX2GUXgHs7vLAWxhTx3b5xBXr9I8f9rhnrfEHWwhhhfCEr3D3gWftdQTdYMFj WjbEEo0hLQ3XQtcDwpJpGyg9I14rcLJqJ6vnnUz5Mr0QTfX0QCXNSNRmzQsAOP8liX8C8/8TMPaU evVnu/quhjCUSM6Acwe3r/sW28PVCTXZSdzeBWnBs3/CDnJH+xCRbU52a2W9ckKQnmblXr0/AdQi O0cEnSwJitssuzLa8m0tNC7T5K6WJ8HwJuMhJlS+uHgtWDQvG7NazeIC8MbZbaca3iDdnlyqppPD UHuhevws/U145fP9/i5sxXhTZ3SmwQWeiHtQT8jy4SxpOeZR3Oea/0yRstY3hG9gDs09UjxdOty9 tWHjKSmp9aX7dGTygQrw5IEGKYtHUQtYFuYFyhzmrcwOygK5bOyDBGr1j1R3Clkd9hkIRoEf2xyQ EQKS4qE99m2N11eGYyxtGUi3znW/3tgyDJPUj4YuMDBFQdCL05qG//c++1Przm9xV1nGw2YvTnI8 /GM5S+39mFJKMxaVZrcRxC3b5j93nXerGKgKZHLBopGi/bgbySKo4tODFXE03T8u4jpr4STiJPRt WN8q8zmUYJVU8OgckNVkCg/IyaWm+ghIm0BZPycbtatjy76nVTOOON/YcbtJ6y1TvS+5ESkYRys4 K6wOn0PpZLIUL0ASjcz/CEqwD5YeDbjBWUbXc/d0R+AJ1gJvcIXD0zcpaqn2qXwP9bF2gha9oDYY GIBg/geKmvp0TMcVD5TPLcn4oKW6fpZb1/m93NQ2XYC7EIX16f+Qk/vK1rcWCbc8IkmYCHTQsvbF AuvO7QNEOwEUUaX4KeIJo4FiKjrsqjm7L3i/LY0qieiQwR48HY+CZwv5WptZHRvoIxrT5fdoKqBW qVJz7s8sfV02XnlLFY0q0LXQKIXggR5yS1NzMqgzen2jSCBIz2dKSSYegYCxayAxS82WX2vMMWDU 8FCBJ+MY0Ey7qDB/riIuf2pQxLbIqOp7kwGitAjAjdE4+dS2hyc+Jco8hcA/AtGRW1UCPr7GEp4A iXU2xe+DITh6nthXbbfI8HDA6khXGQAIyHNrVyOAj9My5ZNRC5PACjwWOWLrjtgleTWIZ1+bo3p8 ZRnLWN8JbJWWI8cbMPftNmWTlgawWmRQrbCS33HJ1kz1lulcbCymETkuQHyhOG+fnJbiO6ECrTZN UEWcFO+OfpHvs+5CCU9rAfK2fJYKcOvd/olE3IBVz16N1UuFr0b4YmILFwe0aTu7I/mtYKB3wKfC ZgLiYT3Hy+dC3TNR2bqur7WBqZdQta5mhF/+1dlUofwU+zVbxArhCImQgLijPkRQ63/EOAZ1NE0F lE08VgGPgSPOE1YZRwhdR/+uI0HpliffDnwtqjc/L4+3ckwi1EEscIcVjxcDFBki9oItaUNQJ0iQ ty+KxIb0Bf1nszHNG++vQ+E84kb0WrHVpU96iUpglpx9j7m6t+ai5CZWeWI0GnSa7Q2/1p/z+Ck8 8pHGA9zL2qPmMpopYGFr8BfkIhea61X/skGR3EGTU0+r0as853nUxw2dCmS6ZDa2gP6yEwpfPR5R 9tTXg4gVMFLCgGSf0a4JsZaWq3kwNe+o7JD41h0seEf672thWFsMXmhS4Zlvacf4NxY4yhxntCPm bZKTgd4RG5YjntuUSQTp+yVgh0TaVlo9KYbgXZmxbbLJ60n3crHjLXOP5pS82YsgKGXDCYrXMQBD NhEec5cM8RAB/RtrA5MWoV6/PtsCIszyNNaqgxCBIo/9BDxTarwAWWH0TMYOxcXwAbFGKYzOqNh/ daakI9nDpnOp+gjwwfoF3wafMyVGGn4+Al++5+iV+BDell/nwMH6MgnDK17SySGRbKrv/8FToH5I k0q7SpkFgE3Rx0I+Kk40Oo3vbJyjC0usgBY7myLAdKlhZ0i8JZobEHP/lbmTuGxdw5DEwAFa6h32 ScHh/XGHtx68gfWx6S/k+hfEBORaIYVm6XaaoIBJCZwfivWtt1G2mv+5jdw5c6b5L/vfOCr7HirV 4A4XTx9HbJ5ItkStCqNVKR8VszYFmskIaHYR3FaQYQeUepjy+Fp50GeOzbajv+CbALc9v2r3iSNY UWyNy5vVjCytgI17cdmYoD+tAlvMFUczXjDxrHNVp3ejvrGNjSRC9MgRbGpE66bwF2GSw3Ir/gBP mt/wGuDYlvDM8xwGkJD8lNVNxN8eaKF+ZpsEuBkGIc/JpqKPCnl2KzgNbAzk3llkMuJn20xA2YM7 mGf0jvOPKsYDBWJeTa9DR8alQExzG/twaGPHjyxMAwfEHbkk/CnrsllFiWWzSAQl3WAZ6kCPmRLM PY8cjw42zUvFAvLMvutxpOB8X2nbXIGXObq4NI5Vu0sgVF+NAMng2UTQz766ROIl12D66Wf9tM2N RBDYzqigUC5n7uADSfRPKlhmBTlSXae4hLY3cmgYHibZjGCAHFaJ15CkGDCTYMbcsa6soiuOhFAh +C77GckZlRLkcQ7IQKlHgphNx6kPfuDQ9bmB4UFMswyfNYlfAPi+6qPYLaDtBreSHnjMYkEYFCs/ HOgIeEzD70pUj6uhk2pM7XEX5pv4aVvB6jgNyUQWDNhWi0rxcuFlSfRNyaCmOSlxC+DMrXwLGS9B O/WqZM5FdDbiOaklqSWzGVLBvE1qTpH8ZznZqeL9XvlI2b9YQ17MtuKx8dFp/sUbSOXFgQxDnQ9v 1vsoq9gq5W2SofygzSZX9krdHnwe3yYTOPRSl40OVsTBAjFrUmEk0KL7QkMv9+aTeXiD/ThJe156 ttTkdmyMf+DTCKXc4r+9SwBvss/1oA6BzY2c4Gvx0Cb5JwObv5VTiax0qsAXTyOJLp0q6PvEXVZP mzgRbXuo7BFY3g9p3w1EinOuF6uejvhCBPrE0HhF98ab4By8WCDdhdSs2gm7kVrFdC72P2gWqz60 Rjh+XaVKTj99kfVj3CwnIsJAVL8sEo0/aGRNE4bxzRP+qPL7rPXigMFWohFvwzqljMWFhLt9jk9F i17GPOqmQJ8rrgGCunoHsemrGOWhZVK8+GefndukrCO76cAGhXy/VUz/qtl4CVpuYWNCJT2Z/fAt y8fRuRKLTSTHjyC5stGwYpoeYZhTxvjKNcPC31AUGEIBUe0hNXZuR8vYA5c0YKak7MyCGdpx0vbb b74xSYZby4l2MezgKI7SWF2UjI/V7nlaME6AsgzHE2O+ygQ+0fuXpyYl7wZHP3FtUrXmsA/NJQyO joSqhzgn5HTPP27yGQgCt7yKJFxqbI/zTSh8jM73NHL0lIeecNMRzwlAl64gEXO+z6LcPhQAqZ2J KC6Am4PuKl6FG++MMaF6gUL+mDU+4dhLc/KWvNgIsHptCDdTr8pmbaO0epj6kRI0mp0bcYSsduy+ 9X0RVHES1G4qOyVLHZucw5chIsb1QvwEgu5tNTjLJjZx92+LArAvwPbZz3yzEkT6Ig2J99uzVpX6 xJFFtE6iNV/+bY7K7K45cmdtZM3u6CrR2QRYvTnGSz15xQ/FIHavicWVEl+6H8ttsMHIG3jK5lZN D6PH3aFWJ9EcOpuXvEYFDNz00lKDeL2yNKY4hprcU1oJfUAGldPU1/lDFxgBSUCBAwFHCT5dcRts PH54dBY44HQ37HEBXe2ueaPk6hSBTkZIhaYJxBQWUe+kKBMT8nLMMFrbOX/wt1lYSyrrB4RBk/k7 np1ZQ7x07UP+vWA6R4JHmtql43xB7q5jS7sy9LLYvWfStB7pmLfUAvOs6fRgXp3du03uhBAVPt8n QQp5wlghNW+iYz/cRhKlgHrFHftoK6dMTZW5jsowkGzBLLFnCpy3QLetJlEeOp1pqTJPL4i8JPFi aMSa16AyMyjBJmylF2aMMg/e4CecbXrtDsuRP0FCARXL4JnBm67DRr4Rmu7IuQaC/YsWZ4wiPEpS +S92cXXWEt3eElADDTrUt0Nxe4K82ptn3zPUGcqnUDItLBh7pGg4vCWnwtKXa5MidpGZCtYLXnEM yi1vSz4AbfqOkHc+UDx7wEPx8UwjLvxLxG6EH7j9DenqV67J2rOHWDjMLbWz+VNxisfCDhrR1WlW G7ZmppSyMIJw1jB/zQ3TiSiFrmXuIF7Ev/ujJZrTAb1rz98Ftorg1TL7Y+cAXOkd2M0elrk0Aidl TPUJPP2QOUunivrDKQbwhJILdhp1kEogh9raA5CP5wpfwp1B1M40EBDI7zjAFLWpefzUikG3H3YC 2JXS+cRMAjONzbb0CyTGaoHNcg1zxu6YcL7HUXzAoU7NpV/BqqehfwjgBmwIAcMd2gEyNrfcIOI9 wqfxGxeSQPfbTcAnZTGSazGxEq5YLUi1dhegw2eiARhMSOHBcy8SphcnHUv+gQnO5Z0gaxy/TdSo XiuXRjCVJebgbveZA1xehH6EweqyMjOfHV/dO88oongjrvB5RsVxUonE9RwKFB6si/uYQKKZYHuq 5dCv/AIjqeYv9rRYuJo/CHZDzZkso7ixFsIJRjJ9sTlSQO5V2UDBsI0oyPlSjb4avUizHQqnV58c jEkuk9UIszV2grOnn+voJI3rXCjTWJ9K4YfOFGDew7IvbDENO2vHvaM7UFp/lQ64BeUKU0XqRV0I qKIlu8MHLdLO5lV6BL2lqfRzQDLcs4xrQ7oBgoi18ePXR+ZLRoW6YvXyQhK75/7G49tZyQJfew3y 7D7nge3E6iUKzgim9VLZAfA1Sk5cnCMMXmkdWKIjI/iRe+1uMuNXnCoLKcU/mS/r+lgjUU1DBt24 Pyw+OP2KhRs+M3eNiVCItp+mmwca5i8uUxMrs9fCOO3lzLUekBrKR9L16q7xFzOyyd9FHgpDkNlR +TLGd/Q2sidn4AswKqzZ5Mnxqy66xie2TgaDtRmhru3x9OrIn4xBcV5Sh9b1G6mMRtSU/QTG5UVg 5u74HTdJwFsiyd8jLdhLTAuq9XkdsjdY+uP8euFv2yGOGTe4/1MBCZFMEQhLd2LhsZcLWZHr/Uco cNl0utq9z9p8yLbZbpAgoKonLbp7zpvY0VFswZyS2I6+AJ8GKSHuqDXKswrAs7Bb2JZGCFbT6g+v +Mtoz6ROhELjdEMw8azcamO8jTDUtTJrELXIpGPqXPkNzCnYe0JMQxWA4mjp+cBsZekBQkKiwJ+L auCCehdrR4eoyTfFJ67V5zzfhO6rTmPlrVCcqNAa8V/3S/q9T8kSJQFBhxFS93vaOTXJdlWe5oYb bx7k2l1uXnygqc9h8+AeJMxBRros+TZipVGFhzlyOepuUxAXXkitD3WYKPqQu7+t9q54LPd7LaiL njpR615OQiYxqzfVBXrP+UqxtW+PbvFHiMcl/VPuXNsukXM6fvo88UGYEQiYO2rzWKPCEneakZxM WHAY3qCjUl4xLDlTfRIOAyLTSNC/krZv61pMFvWHBkWL3b5e2/RwCCHfV+thmLsEq2FkA01mKi8I oPQe76p24/zzpENYLDjdyRXr8LWLuvjyH+N2H/b5lm7vUSOIgNbij7sHOfuP4rqMw5F4JFr//MoZ /gcKklt4nPd3pU60/0bBBZgtnlIOLgsljE244CpbaiPX6RxHMX2ikP4ZQf2FrhDFwJwriP/kKd/d Quh9ZeOIyGU4NUdS7TR7iUKV9ZvJlhrpFLlJmqsBMhrRSzAvre0C2xKqro1CBpc5203l6eMurV5c GoN6y+5xsdHMpjU0JDheAChhKa8XsZT0eaA5vAXf45Kpw2XH63HpoKvf6lwU2y4TRf2lYPsii94B h5HVe9SVaob2WiVA9A7B5r8HJWaih2hP4enj7yLZWNrmz4/Vl2KgDciPypOm8UIq/2YdR9GT3CNb 2rzIfqsAQR+Mu06iMoGuBUL1iAor+ZQJ6hehngkEzmWyEualg2tJBXagOWo7AfrL6DLno1U4vcS+ EUHCWT+FNDZBq+72G6AT+m9zNMPSoKNrmBh+93rsnnvXjL+56XUY01fkpHNPQgxFdPxXDCgZpWBb jlhJOD/Yp2OjxHdnmq3+9pMVSv9hhxo8swfrL7ehslv5b06Rt9iD/Ly1AF39L1dUDbvdM++2bYZ2 UrJILc35HIMryXNdebctAXSUjrm0txZSIaiN27IWXJMu0/v+X3LSICkb8GeUwgiA+SGEnT3kPAZm 77LIBh+SEcgA3P/26UMXWWCFgPelTI0Z5d2rPEAheDLX8gD7Xty5v7pOFN9GhCPI4lxt16VsUySY ZbIs5ACH+gET0eyAR06VPhg+1XTYdBACoqCsBlTW69p7T3yaAXgGURgkKApi1yMaktW3p5q6lIc0 fIms5bIhijKcsW+uKUwgKHZWhWsoy4L/5Zw4rg6e570S33p8pLHzBVqyUYrwZlFYpVbwGgs8MO24 Sg6XKmszqDq9cEu29/rKwW+okYQHDY+uyR2yeKCCVgv1YFUXmZ/fJJbNl9FI7aXJFErp5LgyLIX0 9hnGWT4bzmlTDp/1RjJRqQUObSc7PodApCx/d42YdNsvEjkQHNJaNnY+VDjMylAtAUX+1uENzemG hxl9qgMnd9Yqt4E93887zVF3jcNoDG9i8nYwcoozAR5r/dndUxfLBcTMqubD5tjogc5zSmCO/CAH 36XbjAd9+tKVGi6ENeroLtsTJ+cp9tGT/KzQrOl7j9Pekiey0X0DBjVceOYejUPpp2AY4oCjrhew u2fH8r6Nwz2r0x0OTqOdlGcDXo7CdV60uOXHMo7A5cmRWh84FuLKjds7sAfNbGXplVvpsLv/Ui1A Z6SqI2vPBuaCmf6coIYtWUCg5hUmvMIw6tXoJrURt35lfSyoNYi9nKE8aEXIxtLRoub6MugZN6+b ESEyoptewHrDIyFtJ5v2yGZ1u5MTXH18g1utVR9YllSiqb97eYvPqq+r8hT0uHhqIXgeU7tFa9Ze mKBMHQaKwvuTyQgMOIJ9cceRw/sz5yT9RS+ZAxOQwQL0nzxPNOjr8b2hP8D22jc16gTROyJFpThu efh1uTt9f7yW0jhjDpA8RoSgae1TBSGP0IEP1SNlzzSIbiCcwwfu9+1Tfp6V6n6jS4bVjCV0pKI6 aI+oEZg1iSjRZgsFzAkkfat6ZrDoFLZZjlG0q3z4sZ+CYBproa5tAsF7jvPdCpVqI2HG4717OWHw sUFQwsh+WVIk8BzF1R2C7n19C6FSiAx44dH7bPlK+BOiAE6qGqtIfP7t7FikgE3txmnSvKBQ1lez PSBbSGcORE7QoTSmThCIYi+I8rrGj26j6HUyMFSIchAdfGVG+xAWb1HlLTrUIHE4bgWlX0mWHD0D rqF5WwT7UUjvHaK9uG0iardgKd8+CjmRmuoMcRTa2sO5RtXAewZ9PUkUqKU1ku/L5+P3IMOtZdvi s748CeGByuL9/5oioEVQz81jCgl+PWeaBNKvrtBBKPPIa5ldBe1024sx5Kn8g1HKX8Pe/EkYxqyY YsgEBHxh/WjZj+TCXGS59aL5UqXv8tsMFOobSjWEds5a1uCENAlxxRw3BVeGxUiTIHGBhq9z1STy rgWh6XHS4pzFtjMAZ+FvxbsjE/OMbbGcvvHe84+5lLEN9PQgNQLnpPuwfyCcgMxzfMxo/WSVW3NO 7xXNVIeZGBzeI/DDq2wtFv/H8rwseFXMU7s85Y4jCYGDwtGBAbhl9cg1HFSIFMBIYLGQ5FehAJKe N9vphVrmPYk89pSkIIrC52QBQGZ/QKYkYRUU2IGC8M3EWmrmwybUcTUcOCdp6hDDgr7whY5qlvJ1 TS+u+tJEDY5pG3Pgl8eQtYPiM8TubY7yAWrXRVWNkNN5GhdUepf7Yi+VUYfd0GOMSubgGWjT974F 1I05PvFNG++87akoSEUgrKnNt1PsO+MpbHo5hmleLUur1GlRyIkxlflQWizEcYL0MJ+JFj8yWfMo m9C00gY93aRxtYN8PiIF7O3B+XSxH9tma94TToUATEQx2YAtWvsEl11/LQXoVAfsxx54g/+T9vB4 JOWhi4FumdtLsXz3uHECb5XZ0cuzvCd3izbpCPuTEQDShKKJKFcD1U+WFH79NmjoJHCNm0KOwiMa mlm5QLua/gk3JVM/CsloPfEj/2CKP0aE0cxeu9y01v3sKpCQGQ09m1fCgR+jCnC8phoX44ewhSdV FtJD4+IWAvr1ccQRmlG74dR86dcY8W74Y1bgdAgyXHhATYvxrlRhOocNRQLQ2QGy0sgYiGFhFYJP 2zNPdvB8mYuM28tFo8lX8PLm60X/2gDAXI7UP5J1/6kGHkOQCDkefrSDBuiLmFBDCY7oHSGa3TXN /Ahr8f1dULQU7wdSY+3GGRGmQRaGo0T0RF8FwrmmvsZTZlOo9H0SLGmbjy+i0/TWqWcTBm6ooyc+ dhj0Z7+gKi4hBscEXYkjV0Jgg1tFXj7YmkleVKYsh8h6S4M2chsoMMQL9J4lL4W08qcOuhVriuG7 P6beQbHl2OdfEx9cydi+/CUJe79GBJMSM1XE1mzeQy39hibl+tQlzVUmWG6anXim2CZaAnLdFTQU o3MrZ661NpbdJXh8I7vgnuDcRd0+vz7YjtOrPAr8DtjmnA5vOclmyml3xXWfx+kz4RRvNvBlaw6P OcN/4ZmcYMx+yLu8jeQpGy4iGSWktgJZBfZXNPHPPGZIeOn7xD0n+Y5rmjZSQl1Tp5fxsPqMmJzJ O43FGn4W2APEj5i8djzHccMcGjO5VhpvksNFgd3yk4dy4VWhZaFYJZLxiibiL+tXNKdZqasVLhjO pj4YHBpL6xgEA8QE2/2QgAKGKERUhlc5P9l/cSMZk0AutfiaHoxQbO9PIu/O21Df4Z7F13r8FsjN q2LGA29MgrsZIAYwRpjANNWqkHdgdN9X5Xro9n/BrOgTwn5cuN1sdbgct44iRT+MFBRXDKe+MFqY DRni/e3soqhJQXhNtWqYE+0JPwRG9nSEkcrLHOc8TEz6v/CXzEjKFMMncU3Yyj+QkT35fDO77k/A QJQiiZ95UcfEp27UnQ6wFWUX2/iLskvxmy2EnQbiAscN3OdUKHFXjX03aWZN0yJSvV4z1GkaCOQh yt8J2pGWkPV4X3258qAvxhJDBcNVsu0dTvwhJoPJpBySUl8JYuZFSwmB+WszptX49S05PqUt/Cfh MrJSVNozt667LWNfSzPArVFHfLYwQtSJ3tol+EQSWh4uKeKaNBJsbMXnin4GhIjRZXgZrDmMcvYX Rq/r5J+qB8DJrkHxZSipxsXEADYgqH2rbWIXFBL523siPLdmaL83WGhVt23pVjNFG+AxdhXikA8S e1A5VGAyxxOhUmspL2xeeY0n9S25euRZ4ryCgycMc7a5qSS+Be/blI39I36QgfrAozJpO5yJk2ka ybYXJIJRI23QcPOG3A2WKjm+LwxDvrCG5LrqT98RA11VUABt8NJdJ4JDoSQtPP5017X+xa05tH4v sDiTlJSUIl26HPJXubuO0ULvSG4EspM8OlGNNnK274jVaB5q6o9OXoDQhPmMrilOPdmIuPq7dwEt nxKGucabu7vdZw== `protect end_protected

mit

APastorG/APG

real_const_mult/real_const_mult_pkg.vhd

1

27902

/*************************************************************************************************** / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Xilinx's Vivado / A 3 space tab is used throughout the document / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This package contains necessary types, constants, and functions for the parameterized / int_const_mult design. / **************************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.math_real.all; use ieee.numeric_std.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.fixed_generic_pkg.all; use work.fixed_float_types.all; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ package real_const_mult_pkg is /* function used to check the consistency and correctness of generics 1 */ /**************************************************************************************************/ function real_const_mult_CHECKS( data_high : integer; data_low : integer; unsigned_2comp_opt : boolean; round_to_bit_opt : integer_exc; max_error_pct : real_exc; constants : real_v) return integer; /* functions for corrected generics and internal/external port signals 2 */ /**************************************************************************************************/ --returns a vector with the high index of each of the partial outputs function calculate_high( mult_fundamental : positive; input_high : integer; is_signed : boolean) return integer; --returns the output signals' low index, which is the lowest of the low indexes of the partial output signals function real_const_mult_OL( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_low : integer; is_signed : boolean) return integer; --returns the output signals' high index, which is the highest of the high indexes of the partial output signals function real_const_mult_OH( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return integer; --applies the assigned parameters of round style, round to bit, and max error percentage to transform --the constants to the correct fixed point form. function fixed_from_real_constants( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return u_ufixed_v; /* functions to obtain the integer factors from the real multiplicands 3 */ /**************************************************************************************************/ --returns true if all the values in the boolean vector are true function all_positive( vector : boolean_v) return boolean; --returns a boolean vector which indicates whether the constants are positive function is_positive_vector_from_constants( constants : real_v) return boolean_v; --calculates the needed shift to convert the fixed point constants to an odd natural number function calculate_pre_vp_shift( mult_fixed : u_ufixed_v) return integer_v; --calculates the positive odd numbers from the vector of fixed point ones function calculate_mult_fundamental( mult_fixed : u_ufixed_v; pre_vp_shift : integer_v) return positive_v; /* function to generate file names 4 */ /**************************************************************************************************/ --generates a name from hashing the parameters of the module real_const_int to obtain different --names for each instantiation function generate_file_name( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : positive_v) return string; end package; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ package body real_const_mult_pkg is /********************************************************************************************** 1 */ function real_const_mult_CHECKS( data_high : integer; data_low : integer; unsigned_2comp_opt : boolean; round_to_bit_opt : integer_exc; max_error_pct : real_exc; constants : real_v) return integer is variable output_inter_w : positive; variable output_w : positive; begin /* --trying to multiply by 0 assert report " ILLEGAL PARAMETERS in entity const_multiplier: the absolute value of the " & "constants must be greater than 1" severity error; --using unsigned but multiplicating by negative constant assert not(constants<0 and unsigned_2comp_opt) report "ILLEGAL PARAMETERS in entity const_multiplier: the design is set to use unsigned" & " format but the constants is negative. Whenever this happens the parameter "& "unsigned_2comp_opt can only be false." severity error; output_inter_w := int_const_mult_OIW(data_width, unsigned_2comp_opt, constants); output_w := int_const_mult_OW(data_width, unsigned_2comp_opt, output_width_opt, constants); --selected output width is not enough for the result assert not(output_w < output_inter_w) report "ILLEGAL PARAMETERS in entity const_multiplier: The selected output width (" & image(output_w) & ") is not enough to represent all possible " & "results from the multiplication. At least " & image(output_inter_w) & " bits are needed." severity error; */ return 0; end function; /********************************************************************************************** 2 */ --used to calculate the output'high from each individual mult_fundamentals from the output'high --of the previous fundamentals function calculate_high( mult_fundamental : positive; input_high : integer; is_signed : boolean) return integer is variable result : integer; begin if is_signed then --(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below) --example: -2(1,0)*-3(2,0)=6(3,0) result := input_high + min_bits(mult_fundamental, is_signed) - 1; --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 10...0 we have a special case in signed: --the output will need 1 bit more than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = -4(100) . When the input is 100(-4), the result is 16, which in signed -- needs 6 bits (010000). Meanwhile, for a multiplicand = -3(101), the result (12) -- only needs 5 bits (01100) if is_signed and ("mod"(log2(real(mult_fundamental)), 1.0) = 0.0) then result := result + 1; end if; else --(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below) --example: 2(1,0)*3(1,0)=6(2,0) result := input_high + min_bits(mult_fundamental, is_signed) - 1; --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 11...1 we have a special case in unsigned: --the output will need 1 bit less than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = 4(100) . When the input is 111(7), the result is 28, which in unsigned -- needs 5 bits (11100). Meanwhile, for a multiplicand = 7(111), the result (49) -- needs 6 bits (110001) if find_rightmost(unsigned(sulv_from_int(mult_fundamental)), '0') = integer'high + 1 then result := result + 1; end if; end if; return result; end function; function output_low( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_low : integer; is_signed : boolean) return integer_v is variable result : integer_v(constants'range); variable u_sat : u_ufixed(75 downto -75); variable s_sat : u_sfixed(75 downto -75); begin if round_to_bit_opt = integer'low then for i in constants'range loop u_sat := resize(to_ufixed(abs(constants(i)), max_error_pct => ite(max_error_pct_opt=real'low, --max_error_pct_opt was not assigned a value 0.0, max_error_pct_opt), round_style => round_style_opt), u_sat); s_sat := resize(to_sfixed(constants(i), max_error_pct => ite(max_error_pct_opt=real'low, --max_error_pct_opt was not assigned a value 0.0, max_error_pct_opt), round_style => round_style_opt), s_sat); if is_signed then result(i) := sfixed_low(0, --irrelevant input_low, '*', 0, --irrelevant maximum(find_rightmost(u_sat, '1'), -FRACTIONAL_LIMIT) ); else result(i) := ufixed_low(0, --irrelevant input_low, '*', 0, --irrelevant maximum(find_rightmost(u_sat, '1'), FRACTIONAL_LIMIT) ); end if; end loop; else --result := (others => round_to_bit_opt); for i in constants'range loop u_sat := resize(to_ufixed(abs(constants(i)), max_error_pct => 0.0, round_style => round_style_opt), u_sat); u_sat := resize(to_ufixed(abs(constants(i)), u_sat'high, round_to_bit_opt, round_style => round_style_opt), u_sat); s_sat := resize(to_sfixed(constants(i), max_error_pct => 0.0, round_style => round_style_opt), s_sat); s_sat := resize(to_sfixed(constants(i), s_sat'high, round_to_bit_opt, round_style => round_style_opt), s_sat); if is_signed then result(i) := sfixed_low(0, --irrelevant input_low, '*', 0, --irrelevant find_rightmost(s_sat, '1') ); else result(i) := ufixed_low(0, --irrelevant input_low, '*', 0, --irrelevant find_rightmost(u_sat, '1') ); end if; end loop; end if; return result; end function; function real_const_mult_OL( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_low : integer; is_signed : boolean) return integer is variable aux : integer_v(constants'range) := output_low(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); variable result : integer := integer'high; begin for i in aux'range loop if aux(i) < result then result := aux(i); end if; end loop; return result; end function; function output_high( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return integer_v is variable result : integer_v(constants'range); variable out_consants_low : integer_v(constants'range) := output_low(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); variable u_sat : u_ufixed(75 downto -75); variable s_sat : u_sfixed(75 downto -75); begin for i in constants'range loop u_sat := resize(to_ufixed(abs(constants(i))), u_sat); --convert with ~0% error s_sat := resize(to_sfixed(constants(i)), s_sat); --convert with ~0% error if is_signed then --(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below) --example: -2(1,0)*-3(2,0)=6(3,0) result(i) := input_high + find_leftmost(s_sat, ite(constants(i) < 0.0, '0', '1')) + 1; --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 10...0 we have a special case in signed: --the output will need 1 bit more than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = -4(100) . When the input is 100(-4), the result is 16, which in signed -- needs 6 bits (010000). Meanwhile, for a multiplicand = -3(101), the result (12) -- only needs 5 bits (01100) if constants(i) < 0.0 and find_leftmost(u_sat, '1') = find_rightmost(u_sat, '1') then result(i) := result(i) + 1; end if; --when the multiplicand is the same special case as in unsigned: --example: -2(1,0)*2(2,0)=-4(2,0) if constants(i) > 0.0 and find_leftmost(u_sat, '1') = find_rightmost(u_sat, '1') then result(i) := result(i) - 1; end if; else --(a downto b)*(c downto d) = (a+c downto b+d), (with exception: see below) --example: 2(1,0)*3(1,0)=6(2,0) result(i) := input_high + find_leftmost(u_sat, '1'); --having one input(multiplicand) fixed and the other variable: --when the multiplicand is 11...1 we have a special case in unsigned: --the output will need 1 bit less than any other multiplicand which is representable in -- the same (and not fewer) number of bits --example: for an input of 3 bits: --multipicand = 4(100) . When the input is 111(7), the result is 28, which in unsigned -- needs 5 bits (11100). Meanwhile, for a multiplicand = 7(111), the result (49) -- needs 6 bits (110001) if find_rightmost(resize(u_sat, u_sat'high, out_consants_low(i), round_style => round_style_opt), '0') = integer'high + 1 then result(i) := result(i) + 1; end if; end if; end loop; return result; end function; function real_const_mult_OH( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return integer is variable aux : integer_v(constants'range) := output_high(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_high, input_low, is_signed); variable result : integer := integer'low; begin for i in aux'range loop if aux(i) > result then result := aux(i); end if; end loop; return result; end function; function fixed_from_real_constants( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : real_v; input_high : integer; input_low : integer; is_signed : boolean) return u_ufixed_v is constant max_error_pct : real := ite(max_error_pct_opt = real'low, 0.0, max_error_pct_opt); constant individual_highs : integer_v := output_high(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_high, input_low, is_signed); constant individual_lows : integer_v := output_low(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); constant result_high : integer := real_const_mult_OH(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_high, input_low, is_signed); constant result_low : integer := real_const_mult_OL(round_style_opt, round_to_bit_opt, max_error_pct_opt, constants, input_low, is_signed); variable result : u_ufixed_v(1 to constants'length)(result_high downto result_low); variable constant_high, constant_low : integer; begin for i in constants'range loop --the transformation to the desired size range constant_high := individual_highs(i) - input_high; constant_low := individual_lows(i) - input_low; --assert false -- report "constant_high: " & image(constant_high) -- severity warning; --assert false -- report "constant_low: " & image(constant_low) -- severity warning; result(i) := resize(to_ufixed(constants(i), constant_high, constant_low, round_style => round_style_opt), result_high, result_low); end loop; return result; end function; /********************************************************************************************** 3 */ function all_positive( vector : boolean_v) return boolean is begin for i in vector'range loop if not vector(i) then return false; end if; end loop; return true; end function; function is_positive_vector_from_constants( constants : real_v) return boolean_v is variable result : boolean_v(constants'range); begin for i in constants'range loop result(i) := constants(i) >= 0.0; end loop; return result; end function; function calculate_pre_vp_shift( mult_fixed : u_ufixed_v) return integer_v is variable result : integer_v(mult_fixed'range); begin for i in mult_fixed'range loop result(i) := -find_rightmost(mult_fixed(i), '1'); end loop; return result; end function; function calculate_mult_fundamental( mult_fixed : u_ufixed_v; pre_vp_shift : integer_v) return positive_v is variable result : positive_v(1 to mult_fixed'length); begin for i in mult_fixed'range loop result(i) := positive(to_real(scalb(mult_fixed(i), pre_vp_shift(i)))); end loop; return result; end function; /********************************************************************************************** 4 */ --string used as this function should be static to work when called in synthesis and thus cannot --contain line data types(which would more flexible as the size wouldn't need to be predefined) function generate_file_name( round_style_opt : T_round_style; round_to_bit_opt : integer_exc; max_error_pct_opt : real_exc; constants : positive_v) return string is constant high : integer := 60; constant low : integer := -10; variable size_for_numeric_part, actual_numeric_part_size : positive; variable accumulative : u_ufixed(high downto low) := to_ufixed(1, high, low); variable aux : u_ufixed(high downto low) := to_ufixed(1, high, low); variable result : string(1 to FILE_NAME_LENGTH); variable temporal : positive; variable counter : positive := 1; begin case round_style_opt is when fixed_round => result(counter to counter+1) := "r_"; when fixed_truncate => result(counter to counter+1) := "t_"; end case; counter := counter + 2; if round_to_bit_opt = integer'low then result(counter to counter+1) := "0_"; counter := counter + 2; elsif round_to_bit_opt > 0 then result(counter) := 'p'; --positive counter := counter + 1; temporal := integer(ceil(log10(real(round_to_bit_opt)+1))); result(counter to counter+temporal-1) := image(round_to_bit_opt); counter := counter + temporal; result(counter) := '_'; --positive counter := counter + 1; else result(counter) := 'n'; --negative counter := counter + 1; temporal := integer(ceil(log10(abs(real(round_to_bit_opt))+1))); result(counter to counter+temporal-1) := image(abs(round_to_bit_opt)); counter := counter + temporal; result(counter) := '_'; --positive counter := counter + 1; end if; size_for_numeric_part := FILE_NAME_LENGTH - counter - 4; --the total length minus the already existing part minus 4 from ".txt" for i in constants'range loop if abs(constants(i))<1 then accumulative := resize(accumulative * to_ufixed(1/abs(constants(i)), high, low), accumulative); else accumulative := resize(accumulative * to_ufixed(abs(constants(i)), high, low), accumulative); end if; end loop; if max_error_pct_opt /= real'low then accumulative := resize(accumulative + to_ufixed(1000*max_error_pct_opt, high, low), accumulative); end if; accumulative := resize(accumulative*2**10, accumulative); for i in 1 to size_for_numeric_part loop aux := resize(aux * 10.0, aux); end loop; accumulative := modulo(accumulative, aux); actual_numeric_part_size := integer(ceil(log10(to_real(accumulative)+1))); if actual_numeric_part_size < size_for_numeric_part then result(counter to counter + (size_for_numeric_part-actual_numeric_part_size) - 1) := (others => '0'); counter := counter + (size_for_numeric_part-actual_numeric_part_size); end if; result(counter to counter + actual_numeric_part_size - 1):= image(integer(to_real(accumulative))); counter := counter + actual_numeric_part_size; result(counter to counter + 3) := string'(".txt"); return result; end function; end package body;

mit

ComputerArchitectureGroupPWr/SimulationCore

src/thermometersLogic.vhd

1

6186

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity thermometersLogic is generic( termNumber : natural := 128 ); port( rsTxBusy : in std_logic; rst : in std_logic; clk50Mhz : in std_logic; clk3kHz : in std_logic; rsDataOut : out std_logic_vector(7 downto 0); rsTxStart : out std_logic; led : out std_logic_vector(7 downto 0) ); end thermometersLogic; architecture Behavioral of thermometersLogic is component DummyRO port( clk : IN std_logic; osc_out : OUT std_logic ); end component; COMPONENT toplevel PORT( clk : IN std_logic; Vccint : OUT std_logic_vector(15 downto 0); temint : OUT std_logic_vector(15 downto 0); busy : OUT std_logic; alarm : OUT std_logic ); END COMPONENT; constant THERM_NUMBER_SYSMON_Temp : integer := 2; constant THERM_NUMBER_SYSMON_Vcc : integer := 3; signal chosenTermometr : integer range 0 to termNumber; signal termometrCounter : integer range 0 to 2**16-1; type state_type is (Start, Numer, Czekaj1, Wartosc1, Czekaj2, Wartosc0); signal state, next_state : state_type; signal rsTxStart_i : std_logic; signal rsDataOut_i : std_logic_vector(7 downto 0); signal termometrRegister : std_logic_vector(15 downto 0); signal termometr : std_logic_vector(termNumber downto 0); signal termometrEnable : std_logic_vector(termNumber downto 0); signal selectedTermometr : std_logic; signal nextTerm : std_logic; signal clk3kHzD : std_logic; signal clk3kHzD2 : std_logic; signal sysmon_vcc : std_logic_vector(15 downto 0); signal sysmon_tem : std_logic_vector(15 downto 0); attribute keep : string; attribute keep of termometr : signal is "true"; attribute keep of termometrEnable : signal is "true"; attribute keep of nextTerm : signal is "true"; attribute keep of termometrRegister : signal is "true"; attribute keep of selectedTermometr : signal is "true"; attribute keep_hierarchy : string; attribute keep_hierarchy of DummyRO: component is "true"; attribute s: string; attribute s of termometr: signal is "yes"; attribute s of termometrEnable: signal is "yes"; begin Inst_toplevel: toplevel PORT MAP( clk => clk50Mhz, Vccint => sysmon_vcc, temint => sysmon_tem, busy => open, alarm => open ); led <= X"55"; Termometers: for I in 1 to termNumber generate Inst_DummyRO: DummyRO PORT MAP( osc_out => termometr(I), clk => clk50Mhz ); end generate; Termometr_Counter: process (selectedTermometr, nextTerm, clk50Mhz) begin if nextTerm = '1' and clk50Mhz = '0' then termometrCounter <= 0; elsif selectedTermometr'event and selectedTermometr = '1' then termometrCounter <= termometrCounter + 1; end if; end process; process (chosenTermometr, termometr) begin selectedTermometr <= termometr(chosenTermometr); end process; process (nextTerm, rst) begin if rst='1' then termometrRegister <= (others => '0'); elsif nextTerm'event and nextTerm = '1' then termometrRegister <= std_logic_vector(to_unsigned(termometrCounter,16)); end if; end process; Chosen_Termometr: process (clk3kHz, rst, chosenTermometr) begin if rst='1' or chosenTermometr = termNumber then chosenTermometr <= 0; termometrEnable <= (others => '0'); elsif clk3kHz='1' and clk3kHz'event then chosenTermometr <= chosenTermometr + 1; for I in 1 to termNumber loop if I = chosenTermometr+1 then termometrEnable(I) <= '1'; else termometrEnable(I) <= '0'; end if; end loop; end if; end process; Next_Term1: process (clk50Mhz) begin if clk50Mhz'event and clk50Mhz='1' then clk3kHzD <= clk3kHz; end if; end process; Next_Term2: process (clk50Mhz) begin if clk50Mhz'event and clk50Mhz='1' then clk3kHzD2 <= clk3kHzD; end if; end process; nextTerm <= (not clk3kHzD2) and clk3kHzD; Synchro: process (clk50Mhz, rst) begin if (rst = '1') then state <= Start; rsDataOut <= X"00"; rsTxStart <= '0'; else if (clk50Mhz'event and clk50Mhz = '1') then state <= next_state; rsDataOut <= rsDataOut_i; rsTxStart <= rsTxStart_i; end if; end if; end process; Output: process (state, rsTxBusy, termometrRegister, chosenTermometr) begin if (state = Numer and rsTxBusy = '0') then rsDataOut_i <= std_logic_vector(to_unsigned(chosenTermometr - 1,8)); rsTxStart_i <= '1'; elsif (state = Wartosc1 and rsTxBusy = '0') then if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then rsDataOut_i <= sysmon_tem(15 downto 8); elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then rsDataOut_i <= sysmon_vcc(15 downto 8); else rsDataOut_i <= termometrRegister(15 downto 8); end if; rsTxStart_i <= '1'; elsif (state = Wartosc0 and rsTxBusy = '0') then if (chosenTermometr = THERM_NUMBER_SYSMON_Temp) then rsDataOut_i <= sysmon_tem(7 downto 0); elsif (chosenTermometr = THERM_NUMBER_SYSMON_Vcc) then rsDataOut_i <= sysmon_vcc(7 downto 0); else rsDataOut_i <= termometrRegister(7 downto 0); end if; rsTxStart_i <= '1'; else rsDataOut_i <= X"00"; rsTxStart_i <= '0'; end if; end process; Next_stage: process (state, rsTxBusy, nextTerm) begin next_state <= state; case (state) is when Start => if nextTerm = '1' then next_state <= Numer; end if; when Numer => if rsTxBusy = '1' then next_state <= Czekaj1; end if; when Czekaj1 => if rsTxBusy = '0' then next_state <= Wartosc1; end if; when Wartosc1 => if rsTxBusy = '1' then next_state <= Czekaj2; end if; when Czekaj2 => if rsTxBusy = '0' then next_state <= Wartosc0; end if; when Wartosc0 => if rsTxBusy = '1' then next_state <= Start; end if; when others => next_state <= Start; end case; end process; end Behavioral;

mit

benjmarshall/hls_scratchpad

hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/sim_tb/vhdl/sin_taylor_series.autotb.vhd

2

39230

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; use IEEE.numeric_std.all; use ieee.std_logic_textio.all; use std.textio.all; entity apatb_sin_taylor_series_top is generic ( AUTOTB_CLOCK_PERIOD_DIV2 : TIME := 5.00 ns; AUTOTB_TVIN_x : STRING := "./c.sin_taylor_series.autotvin_x.dat"; AUTOTB_TVIN_x_out_wrapc : STRING := "./rtl.sin_taylor_series.autotvin_x.dat"; AUTOTB_TVOUT_ap_return : STRING := "./c.sin_taylor_series.autotvout_ap_return.dat"; AUTOTB_TVOUT_ap_return_out_wrapc : STRING := "./impl_rtl.sin_taylor_series.autotvout_ap_return.dat"; AUTOTB_LAT_RESULT_FILE : STRING := "sin_taylor_series.result.lat.rb"; AUTOTB_PER_RESULT_TRANS_FILE : STRING := "sin_taylor_series.performance.result.transaction.xml"; LENGTH_x : INTEGER := 1; LENGTH_ap_return : INTEGER := 1; AUTOTB_TRANSACTION_NUM : INTEGER := 19 ); end apatb_sin_taylor_series_top; architecture behav of apatb_sin_taylor_series_top is signal AESL_clock : STD_LOGIC := '0'; signal rst : STD_LOGIC; signal start : STD_LOGIC := '0'; signal ce : STD_LOGIC; signal continue : STD_LOGIC := '0'; signal AESL_reset : STD_LOGIC := '0'; signal AESL_start : STD_LOGIC := '0'; signal AESL_ce : STD_LOGIC := '0'; signal AESL_continue : STD_LOGIC := '0'; signal AESL_ready : STD_LOGIC := '0'; signal AESL_idle : STD_LOGIC := '0'; signal AESL_done : STD_LOGIC := '0'; signal AESL_done_delay : STD_LOGIC := '0'; signal AESL_done_delay2 : STD_LOGIC := '0'; signal AESL_ready_delay : STD_LOGIC := '0'; signal ready : STD_LOGIC := '0'; signal ready_wire : STD_LOGIC := '0'; signal x : STD_LOGIC_VECTOR (63 DOWNTO 0); signal ap_clk : STD_LOGIC; signal ap_rst : STD_LOGIC; signal ap_return : STD_LOGIC_VECTOR (63 DOWNTO 0); signal ap_done : STD_LOGIC; signal ap_start : STD_LOGIC; signal ap_ready : STD_LOGIC; signal ap_idle : STD_LOGIC; signal ready_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0); signal done_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0); signal ready_initial : STD_LOGIC; signal ready_initial_n : STD_LOGIC; signal ready_last_n : STD_LOGIC; signal ready_delay_last_n : STD_LOGIC; signal done_delay_last_n : STD_LOGIC; signal interface_done : STD_LOGIC := '0'; -- Subtype for random state number, to prevent confusing it with true integers -- Top of range should be (2**31)-1 but this literal calculation causes overflow on 32-bit machines subtype T_RANDINT is integer range 1 to integer'high; type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER; shared variable AESL_mLatCnterIn : latency_record; shared variable AESL_mLatCnterOut : latency_record; shared variable AESL_mLatCnterIn_addr : INTEGER; shared variable AESL_mLatCnterOut_addr : INTEGER; shared variable AESL_clk_counter : INTEGER; signal reported_stuck : STD_LOGIC := '0'; shared variable reported_stuck_cnt : INTEGER := 0; component sin_taylor_series is port ( x : IN STD_LOGIC_VECTOR (63 DOWNTO 0); ap_clk : IN STD_LOGIC; ap_rst : IN STD_LOGIC; ap_return : OUT STD_LOGIC_VECTOR (63 DOWNTO 0); ap_done : OUT STD_LOGIC; ap_start : IN STD_LOGIC; ap_ready : OUT STD_LOGIC; ap_idle : OUT STD_LOGIC); end component; -- The signal of port x shared variable AESL_REG_x : STD_LOGIC_VECTOR(63 downto 0) := (others => '0'); procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is variable whitespace : CHARACTER; variable i : INTEGER; variable ok: BOOLEAN; variable buff: STRING(1 to token'length); begin ok := false; i := 1; loop_main: while not endfile(textfile) loop if textline = null or textline'length = 0 then readline(textfile, textline); end if; loop_remove_whitespace: while textline'length > 0 loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then read(textline, whitespace); else exit loop_remove_whitespace; end if; end loop; loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop if textline(textline'left) = ' ' or textline(textline'left) = HT or textline(textline'left) = CR or textline(textline'left) = LF then exit loop_aesl_read_token; else read(textline, buff(i)); i := i + 1; end if; ok := true; end loop; if ok = true then exit loop_main; end if; end loop; buff(i) := ' '; token := buff; token_len:= i-1; end procedure esl_read_token; procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING) is variable i : INTEGER; begin esl_read_token (textfile, textline, token, i); end procedure esl_read_token; function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0); variable idx : integer := 3; begin ret := (others => '0'); if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then report "Error! The format of hex number is not initialed by 0x"; end if; while true loop if (data_width > 4) then case RHS(idx) is when '0' => ret := ret(data_width - 5 downto 0) & "0000"; when '1' => ret := ret(data_width - 5 downto 0) & "0001"; when '2' => ret := ret(data_width - 5 downto 0) & "0010"; when '3' => ret := ret(data_width - 5 downto 0) & "0011"; when '4' => ret := ret(data_width - 5 downto 0) & "0100"; when '5' => ret := ret(data_width - 5 downto 0) & "0101"; when '6' => ret := ret(data_width - 5 downto 0) & "0110"; when '7' => ret := ret(data_width - 5 downto 0) & "0111"; when '8' => ret := ret(data_width - 5 downto 0) & "1000"; when '9' => ret := ret(data_width - 5 downto 0) & "1001"; when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010"; when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011"; when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100"; when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101"; when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110"; when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111"; when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 4) then case RHS(idx) is when '0' => ret := "0000"; when '1' => ret := "0001"; when '2' => ret := "0010"; when '3' => ret := "0011"; when '4' => ret := "0100"; when '5' => ret := "0101"; when '6' => ret := "0110"; when '7' => ret := "0111"; when '8' => ret := "1000"; when '9' => ret := "1001"; when 'a' | 'A' => ret := "1010"; when 'b' | 'B' => ret := "1011"; when 'c' | 'C' => ret := "1100"; when 'd' | 'D' => ret := "1101"; when 'e' | 'E' => ret := "1110"; when 'f' | 'F' => ret := "1111"; when 'x' | 'X' => ret := "XXXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 3) then case RHS(idx) is when '0' => ret := "000"; when '1' => ret := "001"; when '2' => ret := "010"; when '3' => ret := "011"; when '4' => ret := "100"; when '5' => ret := "101"; when '6' => ret := "110"; when '7' => ret := "111"; when 'x' | 'X' => ret := "XXX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 2) then case RHS(idx) is when '0' => ret := "00"; when '1' => ret := "01"; when '2' => ret := "10"; when '3' => ret := "11"; when 'x' | 'X' => ret := "XX"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; elsif (data_width = 1) then case RHS(idx) is when '0' => ret := "0"; when '1' => ret := "1"; when 'x' | 'X' => ret := "X"; when ' ' => return ret; when others => report "Wrong hex char " & RHS(idx); return ret; end case; else report string'("Wrong data_width."); return ret; end if; idx := idx + 1; end loop; return ret; end function; function esl_str_dec2int (RHS : STRING) return INTEGER is variable ret : integer; variable idx : integer := 1; begin ret := 0; while true loop case RHS(idx) is when '0' => ret := ret * 10 + 0; when '1' => ret := ret * 10 + 1; when '2' => ret := ret * 10 + 2; when '3' => ret := ret * 10 + 3; when '4' => ret := ret * 10 + 4; when '5' => ret := ret * 10 + 5; when '6' => ret := ret * 10 + 6; when '7' => ret := ret * 10 + 7; when '8' => ret := ret * 10 + 8; when '9' => ret := ret * 10 + 9; when ' ' => return ret; when others => report "Wrong dec char " & RHS(idx); return ret; end case; idx := idx + 1; end loop; return ret; end esl_str_dec2int; function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is constant str_len : integer := (lv'length + 3)/4; variable ret : STRING (1 to str_len); variable i, tmp: INTEGER; variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0); variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0); begin normal_lv := lv; for i in 1 to str_len loop if(i = 1) then if((lv'length mod 4) = 3) then tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3); case tmp_lv(2 downto 0) is when "000" => ret(i) := '0'; when "001" => ret(i) := '1'; when "010" => ret(i) := '2'; when "011" => ret(i) := '3'; when "100" => ret(i) := '4'; when "101" => ret(i) := '5'; when "110" => ret(i) := '6'; when "111" => ret(i) := '7'; when others => ret(i) := 'X'; end case; elsif((lv'length mod 4) = 2) then tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2); case tmp_lv(1 downto 0) is when "00" => ret(i) := '0'; when "01" => ret(i) := '1'; when "10" => ret(i) := '2'; when "11" => ret(i) := '3'; when others => ret(i) := 'X'; end case; elsif((lv'length mod 4) = 1) then tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1); case tmp_lv(0 downto 0) is when "0" => ret(i) := '0'; when "1" => ret(i) := '1'; when others=> ret(i) := 'X'; end case; elsif((lv'length mod 4) = 0) then tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4); case tmp_lv(3 downto 0) is when "0000" => ret(i) := '0'; when "0001" => ret(i) := '1'; when "0010" => ret(i) := '2'; when "0011" => ret(i) := '3'; when "0100" => ret(i) := '4'; when "0101" => ret(i) := '5'; when "0110" => ret(i) := '6'; when "0111" => ret(i) := '7'; when "1000" => ret(i) := '8'; when "1001" => ret(i) := '9'; when "1010" => ret(i) := 'a'; when "1011" => ret(i) := 'b'; when "1100" => ret(i) := 'c'; when "1101" => ret(i) := 'd'; when "1110" => ret(i) := 'e'; when "1111" => ret(i) := 'f'; when others => ret(i) := 'X'; end case; end if; else tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4); case tmp_lv(3 downto 0) is when "0000" => ret(i) := '0'; when "0001" => ret(i) := '1'; when "0010" => ret(i) := '2'; when "0011" => ret(i) := '3'; when "0100" => ret(i) := '4'; when "0101" => ret(i) := '5'; when "0110" => ret(i) := '6'; when "0111" => ret(i) := '7'; when "1000" => ret(i) := '8'; when "1001" => ret(i) := '9'; when "1010" => ret(i) := 'a'; when "1011" => ret(i) := 'b'; when "1100" => ret(i) := 'c'; when "1101" => ret(i) := 'd'; when "1110" => ret(i) := 'e'; when "1111" => ret(i) := 'f'; when others => ret(i) := 'X'; end case; end if; end loop; return ret; end function; -- purpose: initialise the random state variable based on an integer seed function init_rand(seed : integer) return T_RANDINT is variable result : T_RANDINT; begin -- If the seed is smaller than the minimum value of the random state variable, use the minimum value if seed < T_RANDINT'low then result := T_RANDINT'low; -- If the seed is larger than the maximum value of the random state variable, use the maximum value elsif seed > T_RANDINT'high then result := T_RANDINT'high; -- If the seed is within the range of the random state variable, just use the seed else result := seed; end if; -- Return the result return result; end init_rand; -- purpose: generate a random integer between min and max limits procedure rand_int(variable rand : inout T_RANDINT; constant minval : in integer; constant maxval : in integer; variable result : out integer ) is variable k, q : integer; variable real_rand : real; variable res : integer; begin -- Create a new random integer in the range 1 to 2**31-1 and put it back into rand VARIABLE -- Based on an example from Numerical Recipes in C, 2nd Edition, page 279 k := rand/127773; q := 16807*(rand-k*127773)-2836*k; if q < 0 then q := q + 2147483647; end if; rand := init_rand(q); -- Convert this integer to a real number in the range 0 to 1 real_rand := (real(rand - T_RANDINT'low)) / real(T_RANDINT'high - T_RANDINT'low); -- Convert this real number to an integer in the range minval to maxval -- The +1 and -0.5 are to get equal probability of minval and maxval as other values res := integer((real_rand * real(maxval+1-minval)) - 0.5) + minval; -- VHDL real to integer conversion doesn't define what happens for x.5 so deal with this if res < minval then res := minval; elsif res > maxval then res := maxval; end if; -- assign output result := res; end rand_int; function esl_equal_std_lv (lv1 : STD_LOGIC_VECTOR; lv2 : STD_LOGIC_VECTOR) return BOOLEAN is variable len : INTEGER; variable i : INTEGER; begin if (lv1'length > lv2'length) then len := lv2'length; for i in lv1'length - 1 downto lv2'length loop if(lv1(i) = '1') then return false; end if; end loop; else len := lv1'length; for i in lv2'length - 1 downto lv1'length loop if(lv2(i) = '1') then return false; end if; end loop; end if; for i in len - 1 downto 0 loop if (lv1(i) = '1' and lv2(i) /= '1') or (lv1(i) = '0' and lv2(i) /= '0') then return false; end if; end loop; return true; end function; procedure post_check (file fp1 : TEXT; file fp2 : TEXT) is variable token_line1 : LINE; variable token_line2 : LINE; variable token1 : STRING(1 to 152); variable token2 : STRING(1 to 152); variable golden : STD_LOGIC_VECTOR(151 downto 0); variable result : STD_LOGIC_VECTOR(151 downto 0); variable l1 : INTEGER; variable l2 : INTEGER; begin esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); if(token1(1 to 13) /= "[[[runtime]]]" or token2(1 to 13) /= "[[[runtime]]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); while(token1(1 to 14) /= "[[[/runtime]]]" and token2(1 to 14) /= "[[[/runtime]]]") loop if(token1(1 to 15) /= "[[transaction]]" and token2(1 to 15) /= "[[transaction]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp1, token_line1, token1); -- Skip transaction number esl_read_token(fp2, token_line2, token2); -- Skip transaction number esl_read_token(fp1, token_line1, token1, l1); esl_read_token(fp2, token_line2, token2, l2); while(token1(1 to 16) /= "[[/transaction]]" and token2(1 to 16) /= "[[/transaction]]") loop golden := esl_str2lv_hex(token1, 152 ); result := esl_str2lv_hex(token2, 152 ); if(esl_equal_std_lv(golden, result) = false) then report token1(1 to l1) & " (expected) vs. " & token2(1 to l2) & " (actual) - mismatch"; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); end loop; esl_read_token(fp1, token_line1, token1); esl_read_token(fp2, token_line2, token2); end loop; end procedure post_check; begin AESL_inst_sin_taylor_series : sin_taylor_series port map ( x => x, ap_clk => ap_clk, ap_rst => ap_rst, ap_return => ap_return, ap_done => ap_done, ap_start => ap_start, ap_ready => ap_ready, ap_idle => ap_idle ); -- Assignment for control signal ap_clk <= AESL_clock; ap_rst <= AESL_reset; AESL_reset <= rst; AESL_done <= ap_done; ap_start <= AESL_start; AESL_start <= start; AESL_ready <= ap_ready; AESL_idle <= ap_idle; AESL_ce <= ce; AESL_continue <= continue; gen_check_strlSignal_AESL_done_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then NULL; else if ( AESL_done /= '1' and AESL_done /= '0' ) then assert false report "Control signal AESL_done is invalid!" severity failure; end if; end if; end if; end process; gen_check_strlSignal_AESL_ready_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then NULL; else if ( AESL_ready /= '1' and AESL_ready /= '0' ) then assert false report "Control signal AESL_ready is invalid!" severity failure; end if; end if; end if; end process; gen_assign_x_proc : process begin wait until (AESL_clock'event and AESL_clock = '1'); wait for 0.45 ns; x <= AESL_REG_x; end process; read_file_process_x : process file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 152); variable i : INTEGER; variable transaction_finish : INTEGER; variable transaction_idx : INTEGER:= 0; variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin wait until AESL_reset = '0'; file_open(fstatus, fp, AUTOTB_TVIN_x, READ_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVIN_x & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp, token_line, token); if(token(1 to 13) /= "[[[runtime]]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp, token_line, token); while(token(1 to 14) /= "[[[/runtime]]]") loop if(token(1 to 15) /= "[[transaction]]") then assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; esl_read_token(fp, token_line, token); -- Skip transaction number esl_read_token(fp, token_line, token); wait for 0.2 ns; while(ready_wire /= '1') loop wait until AESL_clock'event and AESL_clock = '1'; wait for 0.2 ns; end loop; if(token(1 to 16) /= "[[/transaction]]") then AESL_REG_x := esl_str2lv_hex(token, 64 ); esl_read_token(fp, token_line, token); end if; wait until AESL_clock'event and AESL_clock = '1'; esl_read_token(fp, token_line, token); end loop; file_close(fp); wait; end process; write_file_process_ap_return : process file fp : TEXT; file fp_size : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 152); variable str : STRING(1 to 40); variable transaction_idx : INTEGER; variable ap_return_count : INTEGER; variable hls_stream_size : INTEGER; variable i : INTEGER; variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin wait until AESL_reset = '0'; file_open(fstatus, fp, AUTOTB_TVOUT_ap_return_out_wrapc, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_TVOUT_ap_return_out_wrapc & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line, string'("[[[runtime]]]")); writeline(fp, token_line); transaction_idx := 0; while (transaction_idx /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; while(AESL_done /= '1') loop wait until AESL_clock'event and AESL_clock = '1'; end loop; write(token_line, string'("[[transaction]] ") & integer'image(transaction_idx)); writeline(fp, token_line); write(token_line, "0x" & esl_conv_string_hex(ap_return)); writeline(fp, token_line); transaction_idx := transaction_idx + 1; write(token_line, string'("[[/transaction]]")); writeline(fp, token_line); end loop; write(token_line, string'("[[[/runtime]]]")); writeline(fp, token_line); file_close(fp); wait; end process; generate_ready_cnt_proc : process(ready_initial, AESL_clock) begin if(AESL_clock'event and AESL_clock = '0') then if(ready_initial = '1') then ready_cnt <= conv_std_logic_vector(1, 32); end if; elsif(AESL_clock'event and AESL_clock = '1') then if(ready_cnt /= AUTOTB_TRANSACTION_NUM) then if(AESL_ready = '1') then ready_cnt <= ready_cnt + 1; end if; end if; end if; end process; generate_done_cnt_proc : process(AESL_reset, AESL_clock) begin if(AESL_reset = '1') then done_cnt <= (others => '0'); elsif(AESL_clock'event and AESL_clock = '1') then if(done_cnt /= AUTOTB_TRANSACTION_NUM) then if(AESL_done = '1') then done_cnt <= done_cnt + 1; end if; end if; end if; end process; generate_sim_done_proc : process file fp1 : TEXT; file fp2 : TEXT; variable fstatus1 : FILE_OPEN_STATUS; variable fstatus2 : FILE_OPEN_STATUS; begin while(done_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; end loop; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; wait until AESL_clock'event and AESL_clock = '1'; file_open(fstatus1, fp1, "./rtl.sin_taylor_series.autotvout_ap_return.dat", READ_MODE); file_open(fstatus2, fp2, "./impl_rtl.sin_taylor_series.autotvout_ap_return.dat", READ_MODE); if(fstatus1 /= OPEN_OK) then assert false report string'("Open file rtl.sin_taylor_series.autotvout_ap_return.dat failed!!!") severity note; elsif(fstatus2 /= OPEN_OK) then assert false report string'("Open file impl_rtl.sin_taylor_series.autotvout_ap_return.dat failed!!!") severity note; else report string'("Comparing rtl.sin_taylor_series.autotvout_ap_return.dat with impl_rtl.sin_taylor_series.autotvout_ap_return.dat"); post_check(fp1, fp2); end if; file_close(fp1); file_close(fp2); report "Simulation Passed."; assert false report "simulation done!" severity note; assert false report "NORMAL EXIT (note: failure is to force the simulator to stop)" severity failure; wait; end process; gen_clock_proc : process begin AESL_clock <= '0'; while(true) loop wait for AUTOTB_CLOCK_PERIOD_DIV2; AESL_clock <= not AESL_clock; end loop; wait; end process; gen_reset_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin rst <= '1'; wait for 100 ns; for i in 1 to 3 loop wait until AESL_clock'event and AESL_clock = '1'; end loop; rst <= '0'; wait; end process; gen_start_proc : process variable rand : T_RANDINT := init_rand(0); variable rint : INTEGER; begin start <= '0'; ce <= '1'; wait until AESL_reset = '0'; wait until (AESL_clock'event and AESL_clock = '1'); start <= '1'; while(ready_cnt /= AUTOTB_TRANSACTION_NUM + 1) loop wait until (AESL_clock'event and AESL_clock = '1'); if(AESL_ready = '1') then start <= '0'; start <= '1'; end if; end loop; start <= '0'; wait; end process; gen_continue_proc : process(AESL_done) begin continue <= AESL_done; end process; gen_AESL_ready_delay_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_ready_delay <= '0'; else AESL_ready_delay <= AESL_ready; end if; end if; end process; gen_ready_initial_proc : process begin ready_initial <= '0'; wait until AESL_start = '1'; ready_initial <= '1'; wait until AESL_clock'event and AESL_clock = '1'; ready_initial <= '0'; wait; end process; ready_last_n_proc : process begin ready_last_n <= '1'; while(ready_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until AESL_clock'event and AESL_clock = '1'; end loop; ready_last_n <= '0'; wait; end process; gen_ready_delay_n_last_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then ready_delay_last_n <= '0'; else ready_delay_last_n <= ready_last_n; end if; end if; end process; ready <= (ready_initial or AESL_ready_delay); ready_wire <= ready_initial or AESL_ready_delay; done_delay_last_n <= '0' when done_cnt = AUTOTB_TRANSACTION_NUM else '1'; gen_done_delay_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_done_delay <= '0'; AESL_done_delay2 <= '0'; else AESL_done_delay <= AESL_done and done_delay_last_n; AESL_done_delay2 <= AESL_done_delay; end if; end if; end process; gen_interface_done : process(ready, AESL_ready_delay, AESL_done_delay) begin if(ready_cnt > 0 and ready_cnt < AUTOTB_TRANSACTION_NUM) then interface_done <= AESL_ready_delay; elsif(ready_cnt = AUTOTB_TRANSACTION_NUM) then interface_done <= AESL_done_delay; else interface_done <= '0'; end if; end process; gen_clock_counter_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '0') then if(AESL_reset = '1') then AESL_clk_counter := 0; else AESL_clk_counter := AESL_clk_counter + 1; end if; end if; end process; gen_mLatcnterout_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_mLatCnterOut_addr := 0; AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter + 1 ; reported_stuck_cnt := 0; else if (AESL_done = '1' and AESL_mLatCnterOut_addr < AUTOTB_TRANSACTION_NUM + 1) then AESL_mLatCnterOut(AESL_mLatCnterOut_addr) := AESL_clk_counter; AESL_mLatCnterOut_addr := AESL_mLatCnterOut_addr + 1; reported_stuck <= '0'; elsif (reported_stuck = '0' and reported_stuck_cnt < 4) then if ( AESL_mLatCnterIn_addr > AESL_mLatCnterOut_addr ) then if ( AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10000 and AESL_clk_counter - AESL_mLatCnterIn(AESL_mLatCnterOut_addr) > 10 * 1156 ) then report "WARNING: The latency is much larger than expected. Simulation may stuck."; reported_stuck <= '1'; reported_stuck_cnt := reported_stuck_cnt + 1; end if; end if; end if; end if; end if; end process; gen_mLatcnterin_proc : process(AESL_clock) begin if (AESL_clock'event and AESL_clock = '1') then if(AESL_reset = '1') then AESL_mLatCnterIn_addr := 0; else if (AESL_start = '1' and AESL_mLatCnterIn_addr = 0) then AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter; AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1; elsif (AESL_ready = '1' and AESL_mLatCnterIn_addr < AUTOTB_TRANSACTION_NUM + 1 ) then AESL_mLatCnterIn(AESL_mLatCnterIn_addr) := AESL_clk_counter; AESL_mLatCnterIn_addr := AESL_mLatCnterIn_addr + 1; end if; end if; end if; end process; gen_performance_check_proc : process variable transaction_counter : INTEGER; variable i : INTEGER; file fp : TEXT; variable fstatus : FILE_OPEN_STATUS; variable token_line : LINE; variable token : STRING(1 to 1024); variable latthistime : INTEGER; variable lattotal : INTEGER; variable latmax : INTEGER; variable latmin : INTEGER; variable thrthistime : INTEGER; variable thrtotal : INTEGER; variable thrmax : INTEGER; variable thrmin : INTEGER; variable lataver : INTEGER; variable thraver : INTEGER; type latency_record is array(0 to AUTOTB_TRANSACTION_NUM + 1) of INTEGER; variable lat_array : latency_record; variable thr_array : latency_record; begin i := 0; lattotal := 0; latmax := 0; latmin := 16#7fffffff#; lataver := 0; thrtotal := 0; thrmax := 0; thrmin := 16#7fffffff#; thraver := 0; wait until (AESL_clock'event and AESL_clock = '1'); wait until (AESL_reset = '0'); while (done_cnt /= AUTOTB_TRANSACTION_NUM) loop wait until (AESL_clock'event and AESL_clock = '1'); end loop; wait for 0.001 ns; for i in 0 to AUTOTB_TRANSACTION_NUM - 1 loop latthistime := AESL_mLatCnterOut(i) - AESL_mLatCnterIn(i); lat_array(i) := latthistime; if (latthistime > latmax) then latmax := latthistime; end if; if (latthistime < latmin) then latmin := latthistime; end if; lattotal := lattotal + latthistime; if (AUTOTB_TRANSACTION_NUM = 1) then thrthistime := latthistime; else thrthistime := AESL_mLatCnterIn(i + 1) - AESL_mLatCnterIn(i); end if; thr_array(i) := thrthistime; if (thrthistime > thrmax) then thrmax := thrthistime; end if; if (thrthistime < thrmin) then thrmin := thrthistime; end if; thrtotal := thrtotal + thrthistime; end loop; lataver := lattotal / AUTOTB_TRANSACTION_NUM; thraver := thrtotal / AUTOTB_TRANSACTION_NUM; file_open(fstatus, fp, AUTOTB_LAT_RESULT_FILE, WRITE_MODE); if (fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_LAT_RESULT_FILE & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; if (AUTOTB_TRANSACTION_NUM = 1) then thrmax := 0; thrmin := 0; thraver := 0; write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"'); writeline(fp, token_line); write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"'); writeline(fp, token_line); else write(token_line, "$MAX_LATENCY = " & '"' & integer'image(latmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_LATENCY = " & '"' & integer'image(latmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_LATENCY = " & '"' & integer'image(lataver) & '"'); writeline(fp, token_line); write(token_line, "$MAX_THROUGHPUT = " & '"' & integer'image(thrmax) & '"'); writeline(fp, token_line); write(token_line, "$MIN_THROUGHPUT = " & '"' & integer'image(thrmin) & '"'); writeline(fp, token_line); write(token_line, "$AVER_THROUGHPUT = " & '"' & integer'image(thraver) & '"'); writeline(fp, token_line); end if; file_close(fp); file_open(fstatus, fp, AUTOTB_PER_RESULT_TRANS_FILE, WRITE_MODE); if(fstatus /= OPEN_OK) then assert false report "Open file " & AUTOTB_PER_RESULT_TRANS_FILE & " failed!!!" severity note; assert false report "ERROR: Simulation using HLS TB failed." severity failure; end if; write(token_line,string'(" latency interval")); writeline(fp, token_line); if (AUTOTB_TRANSACTION_NUM = 1) then i := 0; thr_array(i) := 0; write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) ); writeline(fp, token_line); else for i in 0 to AESL_mLatCnterOut_addr - 1 loop write(token_line,"transaction " & integer'image(i) & " " & integer'image(lat_array(i) ) & " " & integer'image(thr_array(i) ) ); writeline(fp, token_line); end loop; end if; file_close(fp); wait; end process; end behav;

mit

APastorG/APG

adder/adder_u.vhd

1

4647

/*************************************************************************************************** / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Vivado by Xilinx / A 3 space tab is used throughout the document / / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This is the interface between the instantiation of an adder an its core. It exists to make it / possible to use external std_ulogic_vector which contain the numeric values while having modules / which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed). / As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer / range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed / a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is / adopted where the integer indexes of the fixed point types are moved to the natural space with a / transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and / adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example, / fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector / Additionally, the generics' consistency and correctness are checked in here. / **************************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.adder_pkg.all; use work.fixed_generic_pkg.all; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ entity adder_u is generic( DATA_IMM_AFTER_START_opt : boolean := false; --default SPEED_opt : T_speed := t_min; --exception: value not set MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set S : positive --compulsory ); port( input : in u_ufixed_v; clk : in std_ulogic; start : in std_ulogic; valid_input : in std_ulogic; output : out u_ufixed; --unconstrained array valid_output : out std_ulogic ); end entity; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ architecture adder_u1 of adder_u is constant P : positive := input'length(1); constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt, S, P, input(1)'high, input(1)'low); /*================================================================================================*/ /*================================================================================================*/ begin adder_core_u_1: entity work.adder_core_u generic map( DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt, SPEED_opt => SPEED_opt, MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt, S => S, P => P, input_high => input(1)'high, input_low => input(1)'low ) port map( clk => clk, input => input, valid_input => valid_input, start => start, output => output, valid_output => valid_output ); end architecture;

mit

223323/lab2

HDL/source/coregen/dcm75MHz.vhd

1

6526

-- file: dcm75MHz.vhd -- -- (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved. -- -- This file contains confidential and proprietary information -- of Xilinx, Inc. and is protected under U.S. and -- international copyright and other intellectual property -- laws. -- -- DISCLAIMER -- This disclaimer is not a license and does not grant any -- rights to the materials distributed herewith. Except as -- otherwise provided in a valid license issued to you by -- Xilinx, and to the maximum extent permitted by applicable -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON- -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and -- (2) Xilinx shall not be liable (whether in contract or tort, -- including negligence, or under any other theory of -- liability) for any loss or damage of any kind or nature -- related to, arising under or in connection with these -- materials, including for any direct, or any indirect, -- special, incidental, or consequential loss or damage -- (including loss of data, profits, goodwill, or any type of -- loss or damage suffered as a result of any action brought -- by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the -- possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail- -- safe, or for use in any application requiring fail-safe -- performance, such as life-support or safety devices or -- systems, Class III medical devices, nuclear facilities, -- applications related to the deployment of airbags, or any -- other applications that could lead to death, personal -- injury, or severe property or environmental damage -- (individually and collectively, "Critical -- Applications"). Customer assumes the sole risk and -- liability of any use of Xilinx products in Critical -- Applications, subject only to applicable laws and -- regulations governing limitations on product liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS -- PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------ -- User entered comments ------------------------------------------------------------------------------ -- None -- ------------------------------------------------------------------------------ -- "Output Output Phase Duty Pk-to-Pk Phase" -- "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)" ------------------------------------------------------------------------------ -- CLK_OUT1____75.000______0.000______50.0______466.666____150.000 -- ------------------------------------------------------------------------------ -- "Input Clock Freq (MHz) Input Jitter (UI)" ------------------------------------------------------------------------------ -- __primary______________27____________0.010 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; library unisim; use unisim.vcomponents.all; entity dcm75MHz is port (-- Clock in ports CLK_IN1 : in std_logic; -- Clock out ports CLK_OUT1 : out std_logic; -- Status and control signals RESET : in std_logic; LOCKED : out std_logic ); end dcm75MHz; architecture xilinx of dcm75MHz is attribute CORE_GENERATION_INFO : string; attribute CORE_GENERATION_INFO of xilinx : architecture is "dcm75MHz,clk_wiz_v3_6,{component_name=dcm75MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=DCM_SP,num_out_clk=1,clkin1_period=37.037,clkin2_period=37.037,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=AUTO,manual_override=false}"; -- Input clock buffering / unused connectors signal clkin1 : std_logic; -- Output clock buffering signal clkfb : std_logic; signal clk0 : std_logic; signal clkfx : std_logic; signal clkfbout : std_logic; signal locked_internal : std_logic; signal status_internal : std_logic_vector(7 downto 0); begin -- Input buffering -------------------------------------- clkin1_buf : IBUFG port map (O => clkin1, I => CLK_IN1); -- Clocking primitive -------------------------------------- -- Instantiation of the DCM primitive -- * Unused inputs are tied off -- * Unused outputs are labeled unused dcm_sp_inst: DCM_SP generic map (CLKDV_DIVIDE => 2.000, CLKFX_DIVIDE => 9, CLKFX_MULTIPLY => 25, CLKIN_DIVIDE_BY_2 => FALSE, CLKIN_PERIOD => 37.037, CLKOUT_PHASE_SHIFT => "NONE", CLK_FEEDBACK => "1X", DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", PHASE_SHIFT => 0, STARTUP_WAIT => FALSE) port map -- Input clock (CLKIN => clkin1, CLKFB => clkfb, -- Output clocks CLK0 => clk0, CLK90 => open, CLK180 => open, CLK270 => open, CLK2X => open, CLK2X180 => open, CLKFX => clkfx, CLKFX180 => open, CLKDV => open, -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => open, -- Other control and status signals LOCKED => locked_internal, STATUS => status_internal, RST => RESET, -- Unused pin, tie low DSSEN => '0'); LOCKED <= locked_internal; -- Output buffering ------------------------------------- clkf_buf : BUFG port map (O => clkfb, I => clk0); clkout1_buf : BUFG port map (O => CLK_OUT1, I => clkfx); end xilinx;

mit

APastorG/APG

adder/adder.vhd

1

7644

/*************************************************************************************************** / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Vivado by Xilinx / A 3 space tab is used throughout the document / / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This is the interface between the instantiation of an adder an its core. It exists to make it / possible to use external std_ulogic_vector which contain the numeric values while having modules / which are able to manipulate this data as fixed point types (either u_ufixed or u_sfixed). / As std_ulogic_vector have a natural range and the u_ufixed and u_sfixed types have an integer / range ('high downto 0 is the integer part and -1 downto 'low is the fractional part) it is needed / a solution so as to represent the negative indexes in the std_ulogic_vector. A solution is / adopted where the integer indexes of the fixed point types are moved to the natural space with a / transformation. This consists in limiting the indexes of the fixed point data to +-2**30 and / adding 2**30 to obtain the std_ulogic_vector's indexes. [-2**30, 2**30]->[0, 2**31]. For example, / fixed point indexes (3 donwto -2) would become (1073741827, 1073741822) in a std_ulogic_vector / Additionally, the generics' consistency and correctness are checked in here. / **************************************************************************************************/ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.adder_pkg.all; use work.fixed_generic_pkg.all; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ entity adder is generic( UNSIGNED_2COMP_opt : boolean := false; --default DATA_IMM_AFTER_START_opt : boolean := false; --default SPEED_opt : T_speed := t_min; --exception: value not set MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set S : positive --compulsory ); port( input : in sulv_v; --unconstrained array clk : in std_ulogic; start : in std_ulogic; valid_input : in std_ulogic; output : out std_ulogic_vector; --unconstrained array valid_output : out std_ulogic ); end entity; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ architecture adder_1 of adder is constant P : positive := input'length(1); constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt, S, P, input(1)'high-SULV_NEW_ZERO, input(1)'low-SULV_NEW_ZERO); constant NORM_IN_HIGH : integer := input(1)'high-SULV_NEW_ZERO; constant NORM_IN_LOW : integer := input(1)'low-SULV_NEW_ZERO; constant NORM_OUT_HIGH : integer := adder_OH(MAX_POSSIBLE_BIT_opt, S, P, NORM_IN_HIGH); constant NORM_OUT_LOW : integer := adder_OL(TRUNCATE_TO_BIT_opt, NORM_IN_LOW); constant OUT_HIGH : natural := NORM_OUT_HIGH + SULV_NEW_ZERO; constant OUT_LOW : natural := NORM_OUT_LOW + SULV_NEW_ZERO; signal aux_input_s : u_sfixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW); signal aux_output_s : u_sfixed(NORM_OUT_HIGH downto NORM_OUT_LOW); signal aux_input_u : u_ufixed_v(1 to P)(NORM_IN_HIGH downto NORM_IN_LOW); signal aux_output_u : u_ufixed(NORM_OUT_HIGH downto NORM_OUT_LOW); /*================================================================================================*/ /*================================================================================================*/ begin msg_debug("adder_NORM_IN_HIGH: " & image(NORM_IN_HIGH)); msg_debug("adder_NORM_IN_LOW: " & image(NORM_IN_LOW)); msg_debug("adder_NORM_OUT_HIGH: " & image(NORM_OUT_HIGH)); msg_debug("adder_NORM_OUT_LOW: " & image(NORM_OUT_LOW)); msg_debug("adder_OUT_HIGH: " & image(OUT_HIGH)); msg_debug("adder_OUT_LOW: " & image(OUT_LOW)); msg_debug("adder_UNSIGNED_2COMP_opt: " & image(UNSIGNED_2COMP_opt)); adder_selection: if UNSIGNED_2COMP_opt generate begin generate_input: for i in 1 to P generate begin aux_input_u(i) <= to_ufixed(unsigned(input(i)), aux_input_u(i)); end; end generate; output(OUT_HIGH downto OUT_LOW) <= to_sulv(aux_output_u); adder_u_1: entity work.adder_u generic map( DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt, SPEED_opt => SPEED_opt, MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt, S => S ) port map( clk => clk, input => aux_input_u, valid_input => valid_input, start => start, output => aux_output_u, valid_output => valid_output ); end; else generate begin generate_input: for i in 1 to P generate begin aux_input_s(i) <= to_sfixed(signed(input(i)), aux_input_s(i)); end; end generate; output(OUT_HIGH downto OUT_LOW) <= to_sulv(aux_output_s); adder_s_1: entity work.adder_s generic map( DATA_IMM_AFTER_START_opt => DATA_IMM_AFTER_START_opt, SPEED_opt => SPEED_opt, MAX_POSSIBLE_BIT_opt => MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt => TRUNCATE_TO_BIT_opt, S => S ) port map( clk => clk, input => aux_input_s, valid_input => valid_input, start => start, output => aux_output_s, valid_output => valid_output ); end; end generate; end architecture;

mit

benjmarshall/hls_scratchpad

hls_cmd_line_testing/cmd_line_proj/hls_sin_proj/solution1/syn/vhdl/sin_taylor_seriescud.vhd

4

2551

-- ============================================================== -- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC -- Version: 2017.1 -- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved. -- -- ============================================================== Library ieee; use ieee.std_logic_1164.all; entity sin_taylor_seriescud is generic ( ID : integer := 5; NUM_STAGE : integer := 6; din0_WIDTH : integer := 32; dout_WIDTH : integer := 64 ); port ( clk : in std_logic; reset : in std_logic; ce : in std_logic; din0 : in std_logic_vector(din0_WIDTH-1 downto 0); dout : out std_logic_vector(dout_WIDTH-1 downto 0) ); end entity; architecture arch of sin_taylor_seriescud is --------------------- Component --------------------- component sin_taylor_series_ap_sitodp_4_no_dsp_32 is port ( aclk : in std_logic; aclken : in std_logic; s_axis_a_tvalid : in std_logic; s_axis_a_tdata : in std_logic_vector(31 downto 0); m_axis_result_tvalid : out std_logic; m_axis_result_tdata : out std_logic_vector(63 downto 0) ); end component; --------------------- Local signal ------------------ signal aclk : std_logic; signal aclken : std_logic; signal a_tvalid : std_logic; signal a_tdata : std_logic_vector(31 downto 0); signal r_tvalid : std_logic; signal r_tdata : std_logic_vector(63 downto 0); signal din0_buf1 : std_logic_vector(din0_WIDTH-1 downto 0); begin --------------------- Instantiation ----------------- sin_taylor_series_ap_sitodp_4_no_dsp_32_u : component sin_taylor_series_ap_sitodp_4_no_dsp_32 port map ( aclk => aclk, aclken => aclken, s_axis_a_tvalid => a_tvalid, s_axis_a_tdata => a_tdata, m_axis_result_tvalid => r_tvalid, m_axis_result_tdata => r_tdata ); --------------------- Assignment -------------------- aclk <= clk; aclken <= ce; a_tvalid <= '1'; a_tdata <= din0_buf1; dout <= r_tdata; --------------------- Input buffer ------------------ process (clk) begin if clk'event and clk = '1' then if ce = '1' then din0_buf1 <= din0; end if; end if; end process; end architecture;

mit

APastorG/APG

adder/adder_core_s.vhd

1

30691

/*************************************************************************************************** / / Author: Antonio Pastor González / ¯¯¯¯¯¯ / / Date: / ¯¯¯¯ / / Version: / ¯¯¯¯¯¯¯ / / Notes: / ¯¯¯¯¯ / This design makes use of some features from VHDL-2008, all of which have been implemented in / Vivado by Xilinx / A 3 space tab is used throughout the document / / / Description: / ¯¯¯¯¯¯¯¯¯¯¯ / This is a design of a parameterized adder which allows the addition of signed numbers / with high fexibility and control over the way data is introduced and the level of pipelining it / will be used / ┌ ┌───────┐ / │ │ i e a │ / input: P│ │ j f b │ _______ / │ │ k g c │ ----> | adder | ----> result / │ │ l h d │ ─────── / └ └───────┘ / └───────┘ / S / The clock cycles it takes to produce a result from the input can also be specified with the / SPEED_opt parameter. The higher this parameter, the shorter, in general, the delay path / between each register and thus, the higher the frequency the design is able to reach. / **************************************************************************************************/ library ieee; use ieee.numeric_std.all; use ieee.std_logic_1164.all; use ieee.math_real.all; library work; use work.common_data_types_pkg.all; use work.common_pkg.all; use work.adder_pkg.all; use work.counter_pkg.all; use work.fixed_generic_pkg.all; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ entity adder_core_s is generic( DATA_IMM_AFTER_START_opt : boolean := false; --default SPEED_opt : T_speed := t_min; --exception: value not set MAX_POSSIBLE_BIT_opt : integer_exc := integer'low; --exception: value not set TRUNCATE_TO_BIT_opt : integer_exc := integer'low; --exception: value not set S : positive; --compulsory P : positive; --compulsory input_high : integer; input_low : integer ); port( input : in u_sfixed_v(1 to P); --unconstrained array clk : in std_ulogic; start : in std_ulogic; valid_input : in std_ulogic; output : out u_sfixed(adder_OH(MAX_POSSIBLE_BIT_opt, S, P, input_high) downto adder_OL(TRUNCATE_TO_BIT_opt, input_low) ); valid_output : out std_ulogic ); end entity; /*================================================================================================*/ /*================================================================================================*/ /*================================================================================================*/ architecture adder_core_s_1 of adder_core_s is /* corrected generics and internal/external ports' sizes */ /**************************************************************************************************/ constant CHECKS : integer := adder_CHECKS(MAX_POSSIBLE_BIT_opt, TRUNCATE_TO_BIT_opt, S, P, input(1)'high, input(1)'low); constant DATA_WIDTH : positive := input(1)'length; constant DATA_HIGH : integer := input(1)'high; constant DATA_LOW : integer := input(1)'low; constant OUTPUT_HIGH : integer := adder_OH(MAX_POSSIBLE_BIT_opt, S, P, DATA_HIGH); constant OUTPUT_LOW : integer := adder_OL(TRUNCATE_TO_BIT_opt, DATA_LOW); constant DATA_IMM_AFTER_START : boolean := DATA_IMM_AFTER_START_opt; constant MAX_POSSIBLE_BIT : integer := ite(MAX_POSSIBLE_BIT_opt=integer'low, integer'high - SULV_NEW_ZERO, MAX_POSSIBLE_BIT_opt); constant ADD_LEVELS : positive := 1 + log2ceil(P); constant PIPELINE_POSITIONS : natural := ite(S = 1, ADD_LEVELS, ADD_LEVELS + 1); constant PIPELINES_2_INTRODUCE : natural := number_of_pipelines(PIPELINE_POSITIONS, SPEED_opt); constant CONDITION_EXC : boolean := (not DATA_IMM_AFTER_START) and ((S = 1 and PIPELINES_2_INTRODUCE=0) or PIPELINES_2_INTRODUCE < 2); function is_pipelines_exc( s : positive; pipeline_positions : natural) return boolean_v is variable result : boolean_v(1 to pipeline_positions) := (others => false); begin result(ite(s = 1, pipeline_positions, pipeline_positions-1)) := true; return result; end function; constant IS_PIPELINED_EXC : boolean_v := is_pipelines_exc(S, PIPELINE_POSITIONS); constant IS_PIPELINED : boolean_v := ite(CONDITION_EXC, IS_PIPELINED_EXC, generate_pipelines(PIPELINE_POSITIONS, SPEED_opt) ); constant OUTPUT_BUFFER : boolean := ite(S = 1, false, ite(CONDITION_EXC, false, IS_PIPELINED(PIPELINE_POSITIONS)) ); constant ACC_PIPELINES : natural := S - 1; constant ADD_PIPELINES : natural := ite(CONDITION_EXC, 1, PIPELINES_2_INTRODUCE - ite(OUTPUT_BUFFER, 1, 0) ); constant PIPELINES : natural := ADD_PIPELINES + ACC_PIPELINES + ite(OUTPUT_BUFFER, 1, 0); /* other constants */ /**************************************************************************************************/ constant INTER_HIGH : integer := minimum(DATA_HIGH + log2ceil(P), MAX_POSSIBLE_BIT); /* data signals */ /**************************************************************************************************/ signal input_resolved : sfixed_v(1 to P)(input(1)'range); --where the input is converted to resolved signal inter : u_sfixed(INTER_HIGH downto DATA_LOW); signal output_inter : u_sfixed(OUTPUT_HIGH downto DATA_LOW); signal start_sh : std_ulogic_vector(1 to ADD_PIPELINES); signal valid_input_sh : std_ulogic_vector(1 to ADD_PIPELINES); /* control signals */ /**************************************************************************************************/ signal start_delayed : std_ulogic; signal valid_input_delayed : std_ulogic; signal counter_out : std_ulogic; /* structures to store and manipulate data of the adder tree (ADD) */ /**************************************************************************************************/ function T_ADD_state_data_high( index : natural) return integer is begin if DATA_HIGH+index > MAX_POSSIBLE_BIT then return MAX_POSSIBLE_BIT; else return DATA_HIGH + index; end if; end function; type T_ADD_state is record level0 : sfixed_v(1 to signals_per_level(P, 0 ))(T_ADD_state_data_high(0) downto DATA_LOW); level1 : sfixed_v(1 to signals_per_level(P, 1 ))(T_ADD_state_data_high(1) downto DATA_LOW); level2 : sfixed_v(1 to signals_per_level(P, 2 ))(T_ADD_state_data_high(2) downto DATA_LOW); level3 : sfixed_v(1 to signals_per_level(P, 3 ))(T_ADD_state_data_high(3) downto DATA_LOW); level4 : sfixed_v(1 to signals_per_level(P, 4 ))(T_ADD_state_data_high(4) downto DATA_LOW); level5 : sfixed_v(1 to signals_per_level(P, 5 ))(T_ADD_state_data_high(5) downto DATA_LOW); level6 : sfixed_v(1 to signals_per_level(P, 6 ))(T_ADD_state_data_high(6) downto DATA_LOW); level7 : sfixed_v(1 to signals_per_level(P, 7 ))(T_ADD_state_data_high(7) downto DATA_LOW); level8 : sfixed_v(1 to signals_per_level(P, 8 ))(T_ADD_state_data_high(8) downto DATA_LOW); level9 : sfixed_v(1 to signals_per_level(P, 9 ))(T_ADD_state_data_high(9) downto DATA_LOW); level10 : sfixed_v(1 to signals_per_level(P, 10))(T_ADD_state_data_high(10)downto DATA_LOW); level11 : sfixed_v(1 to signals_per_level(P, 11))(T_ADD_state_data_high(11)downto DATA_LOW); end record; -- in Vivado and ModelSim -- this constant is used because even driving only one member of a structure implies driving the -- whole structure. So with resolved signals the analysis takes places without problems and the -- subsequent synthesis generates the desired structure. constant ADD_Z : T_ADD_state:=(level0 => (others=>(others=>'Z')), level1 => (others=>(others=>'Z')), level2 => (others=>(others=>'Z')), level3 => (others=>(others=>'Z')), level4 => (others=>(others=>'Z')), level5 => (others=>(others=>'Z')), level6 => (others=>(others=>'Z')), level7 => (others=>(others=>'Z')), level8 => (others=>(others=>'Z')), level9 => (others=>(others=>'Z')), level10 => (others=>(others=>'Z')), level11 => (others=>(others=>'Z'))); -- ADD_in stores the signals entering the levels of the adder tree -- ADD_out stores the signals leaving signal ADD_in : T_ADD_state := ADD_Z; signal ADD_out : T_ADD_state := ADD_Z; /* functions to read and procedures to write from/to T_ADD_state */ /**************************************************************************************************/ function T_ADD_state_read( state : T_ADD_state; level : natural) return sfixed_v is begin case level is when 0 => return state.level0; when 1 => return state.level1; when 2 => return state.level2; when 3 => return state.level3; when 4 => return state.level4; when 5 => return state.level5; when 6 => return state.level6; when 7 => return state.level7; when 8 => return state.level8; when 9 => return state.level9; when 10 => return state.level10; when others => return state.level11; end case; end function; function T_ADD_state_read( state : T_ADD_state; level : natural; signal_number : integer) return u_sfixed is begin case level is when 0 => return state.level0(signal_number); when 1 => return state.level1(signal_number); when 2 => return state.level2(signal_number); when 3 => return state.level3(signal_number); when 4 => return state.level4(signal_number); when 5 => return state.level5(signal_number); when 6 => return state.level6(signal_number); when 7 => return state.level7(signal_number); when 8 => return state.level8(signal_number); when 9 => return state.level9(signal_number); when 10 => return state.level10(signal_number); when others => return state.level11(signal_number); end case; end function; procedure T_ADD_state_write( signal state : inout T_ADD_state; constant level : in natural; constant new_value : in sfixed_v) is begin --for loop introduced because of obscure error in Active-HDL: --Error DAGGEN_0700: Fatal error : INTERNAL CODE GENERATOR ERROR for i in new_value'range loop case level is when 0 => state.level0(i) <= new_value(i); when 1 => state.level1(i) <= new_value(i); when 2 => state.level2(i) <= new_value(i); when 3 => state.level3(i) <= new_value(i); when 4 => state.level4(i) <= new_value(i); when 5 => state.level5(i) <= new_value(i); when 6 => state.level6(i) <= new_value(i); when 7 => state.level7(i) <= new_value(i); when 8 => state.level8(i) <= new_value(i); when 9 => state.level9(i) <= new_value(i); when 10 => state.level10(i) <= new_value(i); when others => state.level11(i) <= new_value(i); end case; end loop; end procedure; procedure T_ADD_state_write( signal state : inout T_ADD_state; constant level : in natural; constant signal_number : in integer; constant new_value : in sfixed) is begin case level is when 0 => state.level0(signal_number) <= new_value; when 1 => state.level1(signal_number) <= new_value; when 2 => state.level2(signal_number) <= new_value; when 3 => state.level3(signal_number) <= new_value; when 4 => state.level4(signal_number) <= new_value; when 5 => state.level5(signal_number) <= new_value; when 6 => state.level6(signal_number) <= new_value; when 7 => state.level7(signal_number) <= new_value; when 8 => state.level8(signal_number) <= new_value; when 9 => state.level9(signal_number) <= new_value; when 10 => state.level10(signal_number) <= new_value; when others => state.level11(signal_number) <= new_value; end case; end procedure; procedure T_ADD_state_copy( signal from_state : in T_ADD_state; signal to_state : inout T_ADD_state; constant level : in natural) is begin case level is when 0 => to_state.level0 <= from_state.level0; when 1 => to_state.level1 <= from_state.level1; when 2 => to_state.level2 <= from_state.level2; when 3 => to_state.level3 <= from_state.level3; when 4 => to_state.level4 <= from_state.level4; when 5 => to_state.level5 <= from_state.level5; when 6 => to_state.level6 <= from_state.level6; when 7 => to_state.level7 <= from_state.level7; when 8 => to_state.level8 <= from_state.level8; when 9 => to_state.level9 <= from_state.level9; when 10 => to_state.level10 <= from_state.level10; when others => to_state.level11 <= from_state.level11; end case; end procedure; /*================================================================================================*/ /*================================================================================================*/ begin msg_debug("adder_core_s : OUTPUT_HIGH: " & image(OUTPUT_HIGH)); msg_debug("adder_core_s : OUTPUT_LOW: " & image(OUTPUT_LOW)); msg_debug("adder_core_s : DATA_HIGH: " & image(DATA_HIGH)); msg_debug("adder_core_s : DATA_LOW: " & image(DATA_LOW)); msg_debug("adder_core_s : MAX_POSSIBLE_BIT_opt: " & image(MAX_POSSIBLE_BIT_opt)); msg_debug("adder_core_s : MAX_POSSIBLE_BIT: " & image(MAX_POSSIBLE_BIT)); /* Introduction of the input to the ADD structure, and extraction of the signal inter from it */ /**************************************************************************************************/ generate_input_resolved_signal: for i in 1 to P generate begin input_resolved(i) <= input(i); end; end generate; T_ADD_state_write(ADD_in, 0, input_resolved); inter <= T_ADD_state_read(ADD_out, ADD_LEVELS-1, 1); /* Generation and management of the control signals */ /**************************************************************************************************/ generate_start_control: if ADD_PIPELINES>0 generate begin start_delayed <= start_sh(ADD_PIPELINES); process (clk) is begin if rising_edge(clk) then start_sh(1) <= start; if ADD_PIPELINES>1 then start_sh(2 to ADD_PIPELINES) <= start_sh(1 to ADD_PIPELINES-1); end if; end if; end process; end; else generate begin start_delayed <= start; end; end generate; generate_valid_input_control: if DATA_IMM_AFTER_START=false generate begin when_ADD_PIPELINES_is_0: if ADD_PIPELINES=0 generate begin valid_input_delayed<= valid_input; end; else generate begin valid_input_delayed <= valid_input_sh(ADD_PIPELINES); process (clk) is begin if rising_edge(clk) then valid_input_sh(1) <= valid_input; if ADD_PIPELINES>1 then valid_input_sh(2 to ADD_PIPELINES) <= valid_input_sh(1 to ADD_PIPELINES-1); end if; end if; end process; end; end generate; end; end generate; when_ACC_PIPELINES_greater_than_0: if S>1 generate begin generate_counter: if DATA_IMM_AFTER_START generate signal aux : std_ulogic; signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt, 0, --COUNTER_WIDTH_dep, true, --TARGET_MODE, ACC_PIPELINES, --TARGET_dep, true, --TARGET_WITH_COUNT_opt = t_true, true, --USE_SET, 1) --SET_TO_dep) downto 1); begin aux <= unsigned(count) ?/= 0; counter: entity work.counter generic map( UNSIGNED_2COMP_opt => true, OVERFLOW_BEHAVIOR_opt => t_wrap, --COUNT_MODE_opt => t_up, --COUNTER_WIDTH_dep => , TARGET_MODE => true, TARGET_dep => ACC_PIPELINES, TARGET_WITH_COUNT_opt => t_true, TARGET_BLOCKING_opt => t_false, USE_SET => true, SET_TO_dep => 1, USE_RESET => true, SET_RESET_PRIORITY_opt => t_set, USE_LOAD => false ) port map( clk => clk, enable => aux, set => start_delayed, reset => counter_out, --load => , --count_mode_signal => , --value_to_load => , count => count, count_is_TARGET(1) => counter_out ); end; else generate signal count : std_ulogic_vector(counter_CW(true, --UNSIGNED_2COMP_opt, 0, --COUNTER_WIDTH_dep, true, --TARGET_MODE, ACC_PIPELINES, --TARGET_dep, false, --TARGET_WITH_COUNT_opt = t_true, true, --USE_SET, 1) --SET_TO_dep) downto 1); begin counter: entity work.counter generic map( UNSIGNED_2COMP_opt => true, OVERFLOW_BEHAVIOR_opt => t_saturate, --COUNT_MODE_opt => t_up, --COUNTER_WIDTH_dep => , TARGET_MODE => true, TARGET_dep => ACC_PIPELINES, TARGET_WITH_COUNT_opt => t_false, TARGET_BLOCKING_opt => t_true, USE_SET => true, SET_TO_dep => 1, USE_RESET => true, SET_RESET_PRIORITY_opt => t_set, USE_LOAD => false ) port map( clk => clk, enable => valid_input_delayed, set => start_delayed, reset => counter_out and valid_input_delayed, --load => , --count_mode_signal => , --value_to_load => , count => count, --not used count_is_TARGET(1) => counter_out ); end; end generate; end; elsif DATA_IMM_AFTER_START generate begin counter_out <= start_delayed; end; else generate begin counter_out <= valid_input_delayed; end; end generate; generate_valid_output: if OUTPUT_BUFFER generate begin process (clk) is begin if rising_edge(clk) then if DATA_IMM_AFTER_START then valid_output <= counter_out; else valid_output <= counter_out and valid_input_delayed; end if; end if; end process; end; elsif DATA_IMM_AFTER_START generate begin valid_output <= counter_out; end; else generate begin valid_output <= counter_out and valid_input_delayed; end; end generate; /* Generation of the adder tree */ /**************************************************************************************************/ generate_ADD_PIPELINES: for level in 0 to ADD_LEVELS-1 generate begin except_in_first_level: if level > 0 generate begin when_more_than_two_signals: if signals_per_level(P, level-1) > 1 generate begin add_pairs: for i in 1 to integer(floor(real(signals_per_level(P, level-1))/2.0)) generate begin T_ADD_state_write(ADD_in, level, i, resize(T_ADD_state_read(ADD_out, level-1, 2*i-1) + T_ADD_state_read(ADD_out, level-1, 2*i), minimum(DATA_HIGH+level, MAX_POSSIBLE_BIT), DATA_LOW)); end; end generate; end; end generate; transport_last_signal_when_odd_number_of_signals: if (signals_per_level(P, level-1) mod 2)=1 generate begin T_ADD_state_write(ADD_in, level, signals_per_level(P, level), resize(T_ADD_state_read(ADD_out, level-1, signals_per_level(P, level-1)), minimum(DATA_HIGH+level, MAX_POSSIBLE_BIT), DATA_LOW)); end; end generate; end; end generate; generate_pipelines_or_connect_cables: if IS_PIPELINED(level+1) generate begin process (clk) is begin if rising_edge(clk) then T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level); end if; end process; end; else generate begin T_ADD_state_copy(from_state=>ADD_in, to_state=>ADD_out, level=>level); end; end generate; end; end generate; /* Generation of the accumulator */ /**************************************************************************************************/ generate_accumulator: if S>1 generate signal previous_output_inter : u_sfixed(output_inter'range); signal inter_resized : u_sfixed(output_inter'range); signal addition : u_sfixed(output_inter'range); signal selector : std_ulogic; begin inter_resized <= resize(inter, output_inter); addition <= resize(previous_output_inter + inter_resized, addition); output_inter <= addition when selector='0' else inter_resized when selector='1' else (others => 'X'); selector <= start_delayed; process (clk) is begin if rising_edge(clk) then if DATA_IMM_AFTER_START=false then if valid_input_delayed = '1' then previous_output_inter <= output_inter; end if; else previous_output_inter <= output_inter; end if; end if; end process; end; else generate begin output_inter <= inter; end; end generate; /* Generation of the output pipeline */ /**************************************************************************************************/ generate_output_pipeline: if OUTPUT_BUFFER generate begin process (clk) begin if rising_edge(clk) then if OUTPUT_LOW<DATA_LOW then output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW); else output <= (OUTPUT_HIGH downto OUTPUT_LOW => output_inter(OUTPUT_HIGH downto OUTPUT_LOW)); end if; end if; end process; end; else generate begin generate_no_output_pipeline: if OUTPUT_LOW<DATA_LOW generate begin output <= resize(output_inter, OUTPUT_HIGH, OUTPUT_LOW); end; else generate begin output <= (OUTPUT_HIGH downto OUTPUT_LOW => output_inter(OUTPUT_HIGH downto OUTPUT_LOW)); end; end generate; end; end generate; end architecture;

mit

benjmarshall/hls_scratchpad

hls_cmd_line_testing/hls_gui_proj/hls_sin_proj/solution1/.autopilot/db/ip_tmp/prj.srcs/sources_1/ip/sin_taylor_series_ap_dmul_4_max_dsp_64/hdl/xbip_dsp48_multadd_v3_0_vh_rfs.vhd

20

80739

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2015" `protect key_keyowner = "Cadence Design Systems.", key_keyname = "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p8dF6db09p9oWm0lH/FzIYezvpS/HJnbKSgl5+PijtFHcZ7Ssq8w7noU0FlQ42fLxw1YKWGl+40U b42uF+Colw== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname = "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block TTND60uSynLMGVurFpzkveZnvcg5nZBFY3TbcBHmeE+r8DMn33HCUnnIe7IJks7stVugYn38C741 P/2wQXJ9s0eRV+wWoCEWHxYennRkRWPeKBtwG0Z9OUg29bJ6c1er+L7C3X9h1HRRSK+X/FLPcDbO 6eJHumUz7qK8eSg2jNo= `protect key_keyowner = "Synopsys", key_keyname = "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block X8R/sm43wYbLCDYYUKPd8XRkX59OfY9C9rTS23YKJxcdg062qV6rrCVyUv9Qxv7bIyRZ6WoxTxZ4 xZI8yRb7BdDKTYm4XNo1b++4p0iZml9EAbipYPxcAd40nyZQvimzFHBhKl+RQrQAWxXWg9hdftro Gfz9IymBoqAAtxNZZ0s= `protect key_keyowner = "Aldec", key_keyname = "ALDEC15_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Wrw4XASblZbeOsghf4pAdnIDxO1DD510wb85kH1G2wiwlLl/s+xAfFnhwf75adpT8+aa+L4z9d1x zncnlp2y8KRs5SGiDdiTLfcUqiVuaFKkgI82FjxUg4LPFO/Ph/iv4jgOzUp2q3joC2/mrV3M8tdY TcZvlK3OoPjlhEVGydHIFhyq5z7040wx0ky2KzEYHDGvokK31GtvT7SRScIpU/pcIPYdqGu36LNs 4dMqU/tvF1NI2rJ8V0nXBo1HZx0OmIEDJPIYs4PGtLLqUDmlgHbIeASBS4Bjbe47cF1BgwRahdnT 7BLUYfKKyc85XBVo39QEnfsR1jbiP15K2YaISw== `protect key_keyowner = "ATRENTA", key_keyname = "ATR-SG-2015-RSA-3", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block LlUwxwgrEnCHIxDi+H/Sv+Zihw3yFsl8/QAoOYEz68lrINnExF1txK0Xy9k5aBcRbCfGRkM2HY0A ybtS6HbV+quqzj7fj5xK5GCsvXFdmF17lzBoaDim8A5EQCHsx9jQNS6s2HurTctN1DvutOUtXNsC YQPAGRsh/vl/EBAf/CVlp8pQlAtc+NNIsmHdv3IlOmWtzj0j1BerJ1GiDGf1lI1wcXWusjXr5++q ralkJx9+6TQa92QDHYO+iLB/NE6P3Vg5aWQzlVlbV92oeQDfrhvSWtPj+b6H0U5RJaz0X0D4GS4i gLQ51uXmBDziJjJz8jDy7nB3s+tzXlCwmyhSwg== `protect key_keyowner = "Xilinx", key_keyname = "xilinx_2016_05", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block jSLJf6eKYoY2ZAgntmmz5FjSEJSLT3EsrDhA3xp7tCaFdq4nnT4/8ihvUzSKXb2prxWolk+ch+Nj ezCeldJp31FvLVz2gCyeV2aU5afhiA0ob1wQWQgkyXprEa48b83ZOZsVTGyPZRWr4ZCznsMlMu8o 5FhQe9+yOYmip2l1IdvoKaq3tzmcgKZ0R+4+Pu6P6r17FUkHVJ6htHcheLCoxXnTaMOiYmFT3fSa BzZSjbQgoS01lS28y1TQq+vgLK6i1C1dycLqGAG0d7NHSsmHR0VGdES/4JAu1k5RMJWlsKdIps+p ABCcf9qXJejOI0MwWmeygTJ3Xm3uzazjefeXSg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 57632) `protect data_block QCuLdQnOPKmgrfnyL3TzNGb9MmGOftaeWnZajruW4TIWVJZGVEgLgjSF5wLryqJ5txV4kNt11Y4N T9luiN6S0pJsXIWy/g2VK296Rfoj1ayr3yKXft4v1ZjlsJluD23Gb2S6V1ShQ8J/LaEsTVGhkky0 o2Xdjb4LQ+LH474rcEnHBQbmNAXCZ/+eNXbXEnVyUh2eCsmZjIiH7exgCiDVxzQSJ4nGdaDwuU+U 8hki04VxXXRlCsXSccZ3WHNP2J/z8ptWc7SD5wRJW1aWUWLitFpaX7aMDQPMHdjEdfmn+thQY9m3 bR2icjUJC3wV3SXRcv9eEY/11pVYqW967Hi+qv5q0LJLK99xwnveD7GLbHdmVKQGGl+CCC98F4y6 DEOL78vCIYE8TEcb66OUhCu/yscfhlG918dv2QyPkXsKYR5nMy60ZH58WCdTwEeb+fvAkTr247WW 8d2pPWBAQjMKt40XGNjL5ndFW9XYq3vnzeG9Z06CDKWaqouhUFwhPGsUHB4sEf+YuXfSCxJSVNlr 5jHYTyYlSGUtfkWaEdJLbSylPVQHho3u1+VLsR0lDadL51LfTHJSIOqvaH1+ZiVu87dxCQPT70eD jz33jbR98jlq3v7ZcMe1oP4bP36/GsrBoxcpy5cjFnxigzIAGkLKQZh3QChKHTErcBJqApage+CF m/3xWyKPMPDZUJTpQXu22ZZqKIXBiDGRId6QotUzjgMA+5BFttLK2/RIfZlGm+/x9x6tlOOBMW1x aMggi1wEBsAyvno2q9WP7FfwCePnaIKqcHUaQA/QW9yhkszaO9hm2J5GnQhWt8palmM0ggEoEAGh nQDpiBcDltI0cUm2nyc5I9xRtCBeoIUq1DExCrU4q7WFw6U0w31DGnwnJZRmgaoUC4En3CDRFW3p 1oE7BYvJobFZXHdbJ7cVGQTfWzuO5yBulZSAVBY6jbEvWTO+YpJaW6qfF/cPd+L+Gi+0AxZ68QlE U6/slXs8k5HGAb9yMqs6Uuex34l4paxkkxRz57/41gKgj3VAL1eliLWZkhkk1TkFgE6GO+ss8aRS uWwZ+SL01B2YMt3g8Fq+12zNG5Gx3f/m3Wc62x8o9yiS6kZ2rI6FwyNlyvVDMT7C7al2Sv6igUST 66Ot8NAL8bgb6LyAzb7PbjWXo1FwzxpmAgO8ctowDaIX/DVV5hC2SrcL0NdlflWjn28nRt7nGwZy NbBCm94U/FkX/IeRvrZwXqyhnm+sR3VI1DHqmd5fMV20MUjP3LK/zghF9M+3ZcbUdFlHfzjS+t7u WBWKzW3A9ifx7O5HqGG0FKlm11jvNl4WXyjoQhx3cbKxvocWQ3BUmh6V0XzCygyFEwaJFk+S8qoj DlNGHv2ctR6VaOceXZaboTjbc8n9Zm91WHamuUfx3aQK4G8mThjABQjpnDMlv5N6b37vyRU0ucOQ gH8BmlescyRaZsz+AOvr09daFTBxysHufsUlPlhrB2DuqviOEjBNYDR3BDh9ARbPnXhg/y4QpvjP U3e5LT/3EOZhdekKi2slwCvLl8NKbU8V0lqa26iyxFF9GDFhIAPrYUpWYGBk1a/sHL55IJDRi4md ZH3xaNDm0ADzTbFyIT7QSyH+PfR/9kzk8T3fNaiLxB6M+PPTA1h74bMz6YF4+Fn5t2qhMIFgZo4k xx/YE0/AdcrnlVh2yVEZEcp8lZ+9+cZ0Ylx4zniZiRnFixF2j9grh3AUbarGr/uEkIEeEte4bJ1Y 75bngb9j+cbSzPLy0xveS25L0yrcqzig3viI2M2jtT6EPmglY1dPM9zWKeBZNlj4xA5lveaghpNF Bd961Yw5C3LNJ/YgAj0ZM+U53bqeh7/WzehKdVFwnpvRXaKeL+7KXeAxvl5I9wwdTtfc9rGOOiVx SXSmawbhEp9TF2ov8k98VpnS5Mek1Fk3taacNR1cLVgDi6+e7TsT1DZT2IskZ6W03W5tW9Hx2MpE vM6bNt3wUpduKvMSHyBhbrK8ov6MCNsmKuDTEwGutno4JmWg0EbWhZn7a6EwfidvVpB+wHafceMK LKkhUmWSj/Gc1foDOaQFEJoCyMEXXHd1jiPtqN8JGUwcMo+CFmEz+xDS3YLf70DiYOY9X3lxfILo WZYGFpHYMOmaMaSBImsm8QcV4oYBmezWK2FizGt5f8CVsx7jup1yyeGOBVcuyBp2mFeu7X8NRvKs ZQNuG+GhukSiimjwen+q9GuEs1zSj7R1zKjBtqwv3AZPhXl9a3PrllXxJ5MFATeI4ixlSIbrPS/z ZPzrZIbxX5LsQ5NT8EXqZPyOkSXLPDmt3C2IstNt/LM2jNojO5sIHrdquV3GVWePscysl4Arey66 nCipX+5tLUTTWgnChcT+D0pwFX0yHVk1Mb7r4J5gT++elSQ1ypjfp9W4B/6ApL2XiXHzOHV/6Mfr taJa32zN3qUZRgq8G7U/QZ4nwjnarwwU6CwQ3bGcKpXajJCEwk34rM+D19UcLq+r7weIRU+4Kh4V xO5361lL1sZLu1CpkmYnNgf5c+CdODCDP6PZUad3LFPJalpY6NExU2KOGICqBYMDOCDu6wwnW5bv 7594EaT/YJfGQE1g9mlG0oargTipP/Oz3SY7qBSVRAowWUtD0JbHhJ0gNsSeY1nJ4qXGtZEPtexC b4cjO3DTFftzlgH/8WdmFzVbcTHf5BBipCIpOIXmG1oqI30MXUgQegL1ihceyABZSY2x9U/m5lbh I6hi0O+9l1uVPL44n86LQaFlW8RQO5C/pViIvQOU5+Uq9r4XMxtnZ3hgBXircUmbJkNEM4u1SFLZ faIhxy3shZejztHT71qWTYq+z12E3nAX4M/Y+2kmDotnsh7xjbTRN22f9ecARVGlenoK1SPaAHe3 pzzKliOwNoHz0CskWe+EflAoiEdR0jLvIX3thfvLFsGU3YXqyHi2qZglEhLbk3TytPC7ZPwU7lML CuMD9RCA0Wn3Gf18Hg/YuyB3OgTyyd8ZrPLVvZN6BblDq3PsZoJv8FzEMoi3xiUQ+Loa2vW0ba3O p90HjF/mNsYRgWgfcAhInfbZms7TOfGtVNGS+IAEcQRFQ2hn12p+VtQME5EX+QlIYgIT8Pe+wRg6 XZHzisskV2OHERI4QcgamenvILTAjSiwnQRLxXFr8OaHLV8lypUbCipVeGmw6twXj9u2geT3/WKM NoSqQMZO6V/aX1Ahf5bhd108NEHo3hc+VqhCAxbbT1nsr2Rb+HRNLW80wNF3XSMgbrU7TANyyvDv 6UX9Qm5/kVDxKa0+ZKTMcrqaxSkRCejdsZhtnwj20TaOzZRcticyCjdPuvVSFpJsclEd76BHZBbF s1Xzpw+o9vjCTQ9yFC1QZ4LtG7zGt9OejZHhZ9XqHDMtG71o9k7BHvUMgGXc5E1kLNIZuO1Vdc2e Hzyd6SbQZA9tkW/u2vnLB4FEGgopg5LBs5EJE5MeK6oJuUH9ApntbimhVa7m9VFLnS7MIYaaB+MJ brjIO/nHUyE/HwNagJzn0ym1eNb7Xa2obcgNl57QQXVfLSfpbpuQg8PyLus8UyrLnuX0DpRpmLeA 3abzxfFLWM6LvpAuY7U3KXgWjrCepxJ3H0aWxXbUgRyrOEpoNKD8b6+zaHbYQzPYvD4uiNJTWnFv 6f9AXmLROu+1AZLnK2YndtfFHpJTYCb3OtM4a/D/642j3WcYT03z4A5tgxwcuT0gIfJb7GSyvHco 6HUd+DROvv/MkACw0fGfUKt5lhWfQFOLqii+uXQFoO6o3GSdUyx6FCPjTF64e60wShUpu7+Hhdne zhkPYebGxVDlI73oQDlHr7Ba6AiZUmyfQ2TUdTgHRHU6gHmlQEXLSq1jg6CwHAEhCiW4J00H0sih XII3rDkKyWbrdEHmbHzFoFezVzb+YyyaBS2sVu3ktu3wXka/cLyOdTeCM/pWc7b7qKjEvL1HYNuv Hn9a0xjL2egeh42ZUKEAFltbVPFlEhE0yoX62GZdGJUequzEkxweKxJ2kKmmJlhihKLAiLApoAxH Zl+jeOFnGgPUq73mOORf5PApNo2f8Pyd8DD7flDdcyHR4KFn9McF3VabjJGvzF7tHTV9PYXAv7mF oTdGOJx4SEgCv2Mm9ZQN5oplTkO/6MNnTdYTTwiELwFmu8LpS6SwG7V1noVBVfpDZbgv18DThMnt 2wePKCXUBk7LHid7/9Iz2g3MBunpD/GSWNv80pbwbuysTwaW3RtV8tyj79klBHwwScrxFscXCEf3 HfDfEBr5PZ+2BY9eU28u227VKn+lIvBoJebvTE3P/hXKiqERKYAJj6qBAUFjItd9cXVZVdSaNdsg Q7eKEgBEUF7m2mv41fTZO90CAttvV2TA9WGjZtDfAiv8oeAnEDzaZLCKlfigMRIkbPkwbTHvwYY9 Cme7LCCNPmfi3uqPDq+8f3hl6FN+UAoPZDOCbvYd5qhUi+TcXAl/JtQjkb4dVXCBot0x0wi45P+G D+3LjcDSwH1eaW3IIzP018ILKzZfQgs9/R7LpwjyhUKH0/DpXh/qj1bOSPFhhCqx3OqvlJYtYk8m 4fYGJuaMLbuUvzKTS5V+Vnf8TNaRa9ywI/EYuNNo3iMbtsyM76ZX6g+wcpeiFbISN9xGB0QbhVDL OpJzxXbh/eeom3M2Z17jl2WS1mz/kfaPM0t1DPaX1AApTK8Z2i54e9noNA8Q3LW915/M8yPuRpbZ GNO9ah9yIkcRj8LgUpF+9TAhJRGAfjV24dRN+C1LKheLeMYSOUQtZTBEoTV0si5Z1R8o6Iy/wScA yiKhVOb5B8RDH4oDlxJ31v1n6UkOXYsScpOZuRE+uL6c8glZlzULnL60pZjzBXveCTbQDmR/EDVg KmzVLFrBX9S4sA4gDBpF3ldu0vId0n2Vu+PXBXYYwZMyW19mpjgjwAwt2g9WSdsspLB6F72ZK76E T67zxqHz1AE4bcHoYn5YaxjspTNjp5ZAHjv977WZ243wkAw1mKf1sKQTqE1WlI86BCYI0tOMo9XS kc3gZJC5z2C9aUuDfG7B7WSkh0b0Ql23aBZWCSWvIp3gXF5AxsnyM7OXuw0SLtpKIPnfUOIDuxRI EQ4Ji6CgxplGtYk/7s91lX9ywMoszY+CcDjeEs2InhwYzNQ9uLUQfZ5GCX2GuHFisL51ndzka/2l 6Bo+aEAIkPBBgNkQ2j+wnN29w2cwCID/dO2NCe2/6w3LF6H+7hQ9fdA0zrezBJnrCDVNH2CwdWY0 5M9F7ZnNpKu1a4kyOdMGV5C0NZ1XjAK8S5RhfAaeb/sJhIE/ILPOKlIn57QJ4WJcVLTzgqEcxtqb WrZqBak44Z0wzyNGXys8p7kC/++92Vo96GvlZCLfKfquDHMqY9sOSL98wvt/+T5jbRuExX76AlcE TEZmvX829FhTWBAw3VYmcHbc/Zwz2Ih52ZRg1Y6kK7HTE7QDSdZLLiXImH0CMAfAWjc63QnabWia 9q0sBSIATZGMl5lVfCgl/eyKcLexNcMzj1cNc1qK4NDDKMVw7Oe+wUTwvCgoZ17L09iqfnt/ay3K A3Vi9yVR/A23im8DNEFrR73dcL4orCA1yC5MN2Ma+RL7Xzbg9/9JWBpKzSWdTzgPIwawVSLWPhBa STf2xzAJu3MxEirc/F7O89dd5RYSnyRTlFtTnMFmKLryzh3CSuiEgmiIq8jna/WXweEzC+2hwPd/ ZfsPNzZk4AE9ydywDCkCrmVJzM9tB7MBtyrHmXykrW12HOM+Sw/XM9+bInUaEQgxDl/jXMlpDMnC dih0QjPRrPezl57FuJ43PzmYBv9ZF72xO8QsoJBZ27ACm6AxBNt+5CkIUCvQAhsQPcUb0BD2tU4O KVg7dpO9BblLyKpvtyL/JGZYMqq33VB/v4z8trSTKm7Rj0L5btDqOkmb8xLNslsFRC0imdvAG7qH am30mxwj0Cdx2zjSaWicPNfRYiEPAKxwVS2LDa0OdeinRH7FkNUiSPicCjiQ60FysDxuw+Q15xw4 VnmmWYCeYGgmrAa/O2frlkE04C6MIrA+6gDs0LKgrA4GBViTHHSXs8V1YIw0oaKI02bR7CvvnfsF O56K5VVwxQYo8vhLNBb4nWX2YH2B67QoEHN13lyShL5xYQm2MUZB4aEnac546LJqeeAi5b4TB06p ZigiTbmVo1B0ka0OJc+vUa1K0Tg3ZuL310ENIa+sOYprrlUTP5HJniCf5LBJryy18V9fBL6tKarg aLFbC6VstIruz6SregKwO9BqkXlHjyhPIMwXLqAAU+fPEe+TROsCwjtf2aqmlQagAxTASzuo8aq/ 3BelBLhUsH86999EMqUns/n8US+l7HRyGY5u3hsujI9BZyo3OWNQziJZLAci/PMoIwNnTnokoCuE jmU6xchw5hHLsKYjdBfd8pWSorFaHTFWqVGRhNPiRRE20YPQhw1Cc1fuZaKVUuY9dyNmMB+WpkFp aCSuPIOkkAbOlkqgx3aLD+SnJwv9lCWtgNxun4FITuYMG42riPMG2eoPdNbC9mno989zaQbXmbm4 VWI/3yzvQ7XGVyfJ2TL0/sw8eRb2Yrx5Lz9IrIFCWJnlISSin8NwtTvVKl0434EflWuas41xcTT7 zGV+d1lqXyoOVVA/4R3NyqzTr0kbkrIv4LHYXCbIwaLV4p86TOy6TvOPuuof06vQLySNf5t7TWRs tBOgcRWSjJLRoJZVZyOc6j2Z4Zsrwkdc9ouviLiPv61FEPLgaZ/ab9ITsotfXb6XzVSYqhbZ/05J bPg5LBthd2PhFl9gz8YKczL3LUmTLEyuuXjK2ORfE1/8wwkjj2pBnE62d0vNI8qunp+vwjq+6v1c gBvog+2G7ShyF2DHdodJDllfe3g8KOh2nnDTIX8g1T+PJUsLuW1hjUR16wI+Jvk1FuUFnuhR/8fC 8VsVTtCI1wRG0gh0ru2P2EBISvliJB5QKwFxRGEhO2BZKISt6WzYv4bArSl6+J6bLrF/oz8L1Wxw pQDbFIGqiRvjP4Z7jtgBZMjTaKoheqP4C8Q4wDq43QHoCwScctT0B7fNPpD1SxYiIiH9WwSbe3Um 4teEj1G1IOdyBO/6YWG+/Zdjs06zuDboMB0NhtzfgePPKDIVRvMHYo6m6LQXCjCKa3qG83alhAes Y2GJMPCCn5ztcKBBZLRcXxXrpNjaOxKNimuR14gNaGVoNuCIkeMJm0PRu0ST7lHN3IjUr30IMhBI 3vzIGNpinAzFIPQU/GscTVBfuoArwMlzlbsNnUWT2Lwx8VNNLAAAFty4+kKnNMmqOM0kJIPlD2SO F7CU4XPprTL8Z035uuW+9gfbZsrQcVh+Ae1GJQg6zhYYaL1DrsLxz/E0y2VyU8O6eTCagl8flf1r t6Evat4JhNomT2HofNsyfKpuAx+qgMlPaz0zu4201BBdr+R/lhUl3NGLRsVSaxpc16tlGe1iflHw roJtyga319XCquurkR7UYr2QwOKg+8Xp8brB4n4aAQajK6Je8c9VQUXBfpPaxCE9YuUI/ZmBUkDg 5t09neD8QCBwJUhj0nr6wmgg4KCz425pM/oHFj47aaY3eEYNSnK5cs7ipI3964ta8NkVvIjjNNuW bMkpGijKAAWNxii5P+gyltNSGrpPVQaEg/G5l2aPCGWMX4KouSiBwfJcDeaUZjgTYeTxWW3KYq0N gtkVPODFMmnk34474GP6HnIBowad4V21ogiRck0a30IoW9stLjmwI3UCXTFDQCQWxSaPb+c11hqU uiRSasuPbDLjYDM4d086jBMzvTgbgZRk9m9FKzJ2BmAHP5H00GB7EH3D1n6kU0WZ8PKrKltGZ0kG 6w85I/4Xf7vdoY+GoIa/Vi4f7oIZVdUDTaQFw3nuZC/HxBvDvTuvMJQRQxJvt+pelmdNF7E2hjwd jHrsQKeEEKMqdOzIhbY0o8KKqQXg6cs0gujnjVjREMDsLyAZvoRoVZmdYX3PhMu+56caxFStPkGI Pxx/WPfLQWj8ae/OLxU0UxLGDIxa90tQN0jLaYFvfopLiwI5LOBA7RO1EFy8afCZgje/wR6Afjsa cm2wbjwOrCY0nB2uRCwSkmLvGOG0bm3CL2Lbgjsv9ijbSELrCYJZEG7dFsHsHiQ8OWgyjdjHLKDI xGeaBqTS65wFbu1ciUiyxC3DGjavxin2R7hoHtDkyEH3t9JxhnmVEEFnG5PiRH1/tkhOoj07Fu9x zpMnx4heiYx/LkunVY2tGikK6TZcNeqTYVkaMLiFSJuHHZ5B2NQ1cz9J5J9rgIw0g2lzo24FdSl4 7QI1IHvGDdvZpvDbRZJlp2ZxHNs7JZQAg7TqdgyMchDSDRnR9+vWEgPoUFf7SgbrpnCbSV2uSD99 AskxJsAiDnpAsQ0zaiupgrhyKWaiDVFaiV30aRnf+vl0r9Te1e6oC4Z8X6+kOvx2KOQJrJl3w8eL FoMd3Pt9Rnfl5JeGV7JmDHnsYpWV2rTGPx81B1BvHXIEccsGRFYMxUPQ3slrTXA65dm4RpluQXKw 1/r0NzxHZmdPa/gg08JaFbx/XWCk2gkvb4U1UWFAZle3qoIF0FI4Mpwz0jRjY2Vy++mH+4/3Zp7V yZ0OvbDMIyXEeuJm1lRwLFlY3RMJH5ghUeRO4f25l45EbU8LIw1aaZKqjBfsuSnEZII5iUu4B4ik KwO7QvMRTThTx0v7BveDo6F8HUrgd/QCOGgcvgK/z8Vzcyx9/0zLjMERKY2pT3zELXyPznKAObVW Lokdz8JusI9v9SyZNW3pUsD4rC4weDb1tb7VNurxhLoL6NEUPGC3VcD5HFpW8NMKjgCfGnhS4S1j Ntyv+BZRLn8mXiqXCnhaNQTvll5ijqb8AITHWPjaJz25GB9mO6tKIQ8nKlwWhPRcET1J2Y4C9O8Z qObETucJgLG+KWFHXKd+XGLJDDdgeJgBiLjkXOK074gnPle3CSNUzBGQGCO9u3/RauopBng2lVvP 8/tmiytFhO4bjS/hslob+iLHObbUJg0U7xPoIP1YyNDep92So+pOpS1uXEsqRZ032qeQct9+fiPe +DwKpDV8tMtUUT1hIOKiv/JXCT3Ebjj6n+r9raDEE2nJlpbH8p0cLgWsXCvIgxizyb3q+sa7NbUE jddJzle7EDsx/upKD5zjVK0fJi3SbCObHpUGMCOktwOSgWEDFhEEaPOY/HUhbXZio7M2gO14q2q6 cUgQ/xcLrNdbZRKwwGsb77UsvRxqdUttmNeM3MPByAxCI65NsYWJmG/QMmkf4JcFRTYVaGMYgMGL vh5eoTwVAzsB6iNBQzCG0bQ0NeRcuZk0W2e/SpG6taq5dBtjBdeYQqhGOIoI0uMyUsiNpcupnu1t VayfwWC61ZZXGY88ng4F2Ng95Nxr12D7nZTewi6hYeDVTKr1iEhkfv70XRXgn37pKTptcRNJKYKq cR8BUrPiMesdD8tqYQpxMd0SZpZVzTsFh+YnMWU9KdECCP3Hd/XJy9Pt4VqQThQehh+Fs+pV2Drv ozZCiWIDc/pdwg+zda/+EyEtyzcEIskumaareIyfbz9LjZ0x+oA2aVJWEJQYqBobm74bqA4u/R++ B623RDq0vCioj9I7syS5brazVgOBH3GfkSVc7WZ7j8JP4ulMqtvAj+k0B2OdwJkBauDvp6trwyUJ pCFfGYmi0R9F/NOtuu+hY8RTqjM16rtO9xQfI0S2kN55v6rSkA2FLox/c1KnaXue6JSmQzyKzHLC H+0aZP1ErVZ5A8Fab7+n1XE0HfE2rhU+qM1EvFROrm3SZ+hiQphqEV56Vpb/l03HvqJB6mXIuBUK qu8/dF6i11GKQrzBjqR8V/V1FwMaDXkzDlrh0gIS/ADRi0ilhC9D4U6VJ9+4D8e/39vJqw2A9ez8 mhg4AH1NU8i8QKv2okcaBzYPVPmPKOi1WaUqD8UZt7SBSsxPpDfW4HRr3/0Xq5r1Pg3mfzMLjJ2H N2iFPVYI42jDuEQPtNUPTm+CwTlinKRoppLfSLKjYsQXG7PZSKAuHuJ6ISasSIqcKeWDgKb+b5ly jkqW8Kfvuxj2AroUK32JMh48aLXdMOyTqXvoChDk4eegI9Gg1FZJ8a5BTQut62DU8kC5LtbFDmsv Q2feZdBD251a9p2C2XNPFJL0eYu2SEsOGMEMh6Wg6wAdYlCN4ZK/YxaZgzcPlAya6H1VRWqF1NnJ 2av9DNN9LBD2BTpqXAXVxr9U72aSmxjUImJTezuDB5EzmHauOMwXX2QxFgQIaI20N7QCq7MctQbA EIx4NybXrrOj6ly3sHeerRLRqGOnkeU4q6GDDETUY/OQX+JUNBUljrahvI//Dclp0o+dhuqPCGm2 JSXMWCE+wmAuwDB5QCbVffVT4w1rqh1ANjxLCFlwNlVXj86hF2xilwHLE23nn/f8+PgHuMSqiz4I l25Q7SmZLF8fApLmu5keYRR14QsiSl0hWb4SMstkWaWJ4DcXHvJRb5T6PeSd/9uk43Xq9sLNH0PU c4euO7Op1XZk3Y7XGwE2qdxWivQS5Y7ulnnSvTirHUuVsbFxRs70CwEy6RBSJAYNcQ+CKZu7V7ws g4P5RsPSxK91weCLL2NEmGgTpci6RIK7HL5QattccBSGqh015pkCIiq5BUew28FWIO81F8fjSII9 hGZXocDj8pMYmCzgUPd8LLQUiSfxGMS+zecrLSxFR8/4eSZGhNZXZBcglCmfMRkMjySEqx3ODi59 Jb6kfc0RPUmvLBrKhTPSOtoojM4A8fiSM9VBdxtZYUZfR+Qj/M1Ep+z2SmhzQkHPzXtxsGUDTbxF B2du0Uhb3G+GYcMVZ99lBw7nZ9jA5cCjtQu1jRHb3VjffvgQAMyg84X2PhwQp3yS8sTD7Ju/jxfR JZKspgWtk95OeVWqXbLO2QlKyay/lqhf3+esCtv162wj3eh1S0hyAk8cVhDb8i+bKKS58o4Z96D6 TDO2nIeWXtvkhrDpWzb6QFvuMGZljafCgtbpu6ZIrJVOXSqsobj4Ii5lc7uSRUo86yvvSndEaU7h eB3KaDVJSyTKmN0KubKjCgPuNRmXbXFOjKr+VezLSFcmBgbcAGhx+UeVfLe3kCAN1Bgu5NnqNyjT rTIxRz15j/z80nCeMINSmtxWD4ETt55w4OiQ6cUNErdN588rDzbOKEttbP73wzjnbtwdLdCHZBYI lIKlr+r1Y/o2x5eHHhgrlLHu2IM8zxwPWksmPpXDNPbnQtB+4golQ9Rf3SpoCE3zPJe3ukwtrhM2 DFFZCROkL62Jc21G7/QcjFTJAOkccZ7lPRAWMSSG0qGo/kY1eQJ2Gh5i/SZTx/NMH9n4xv3V0f+q ppAIAunPtms3viyemVCxeDW4aoaPSm2thb4nMXmLO1Mb/ocYm/QngooR+DBf4+J2F9Oc70r4BWZE nSSuZO5k9yVYhfXniGkHefpU8cWdNM43m4AN+sRvdmIrTvxrV8tYOuqcMhY3cB26CAvr00PYzjje JWVQ+YuQEzwBfFdT91FvMzJXaV+rgs3KtEwav5cPlAxgyVQjKeB4ZN5ylbZJvxNLCJ9h9UhAtxnG 7c47nSwTgMaxhxvJQFqRMWgn/8eoEHUDFvu7UGZk32Lq49dJ0J32mcnyPnBzQVg5ISiYRz0R+c3G yDfehRU01U8Yfe6glm4b3E3VSOq/kOWvvvwJMJgJzp/5D+DBwS4pYGo/PIKoL+Wb91DEbsY5CL5J Im4Bxmg9kn3jzvFeoq+aofiK9Zx6GAjDmcsQsRhRjPKSEuDbOL29HKj1oqLXdmxN/TzRGcrF5FoB cOte2gTeLUAWF9GCEXygSLBFzAGEz73Qs43LAJfsXAQRT685wjTCuaGVkocw5W/lzRfg4wvGJ1Nm Y2NuA96p0yTEbRXfSjj1MndjKYwE8WOWnJy3P8iWEPH6xx56qIRFCfSCNhU/YXm9WDCJBg28Vns2 CAV95gwfsN6BmT0v8AYGXb++PhL3qd2JRypQ+16DGMiJ1ZH0VR0YKStm3uKvWmU8CG4lzkyQ1Oaj 5OwcvOAZLXxYHkR8ST70PH0cbYc0ZKql1BSuGMiQpOiuZoejL8qizYASjvKtxKzknj2+tm7GRqcy c2JYV/+J0HYCLTwS2PraMGJUw7ZbeRBV3IDRwiYcnFUFSshCamlrYbvQ/Ps7u8/oMAmJnlXadHVl HpIANm4PB4sb/mLJhoaOBx6TihfRqym/pIWbWw4U6M6s9ztvgcECHFsMKU3sq5qFWKZXC7c4D2Gv Prnj5hk0KGoDFHc0zsoGeLivv8f7JKW7CI97OK3K8LOfP5+b2g/EpbhCQsHixqsIufN2NbBw7QHh QvTfxcZ3XsMdXiKZJn7ZGOD4Fbp7IH+cktfDvSbuV+sZgTpTwYj97a6GiN2HBbyOYhAiSEBupsfK ahCFd7WUdwMBnLWgQfs7JGYCSjyocLHkWGpBYDZfkAxujwfByhKhEI0/FokCjjBUQt1fj6cCRiyP ql0zDUdsNuwkG3P2P+tB5eCPracgIa7LTo/2Gj+jIW815F8BhJjqHVqhWfM45BGtdJkSQHKvBsob UYtDHcFrN256LRkv2NPaxSF64WcjwwK9WffZTE9yDOT2933DjH35zx8RrXeD1Qa9+F8RNoO4jdyv YlDhreC8ninvafSPUw9TrgEUf6S5z1iePMtYlxGIehbOWB5n3DGXvZdJgJwVhb6n9J4/v0XNGOsm JN0IEBs2pc4PphVSJ8SITStyIoZF3WmzpHVs/Wt/I+hho3hfgWHtFUQ/NNrCjRhymBUyp4tbpxRH DSiv9a4EKuvSfNX1xbaiLEPJG7ZWKvtdXD9GQY7bTOsaogv/AHQ5M9TgGeWeWrZgLBB4TIuqGvgw qGp7C07+2Bsmg8lTQMVMk2Kc04jPMvAIbKwneOMUU5PFnAHb1owwR9m1P5tOsMum4iAiTtGK6MKg HrI4gyRCNIe4eURSFwNf0NVhOIdOjhiszEfD6NAH5h2426ouTXjRQx3s/8EWkT6GOrntco60H+IG a1e0q+sUCrZMXx4Pkbxw0e91vBqjkvcAljJSWiyQXkJ0Yxlwf97NGt01jrF+YuZXKdtVpIflfEyd G7vnVeBmZqInzL9kmWZTdBWwFiZ/BLGfn0UJEeKzSvk+V85JQQMDBzixqFhinNXkaB+buL5iGKnH /poQBLJmXATwhkvywjLBti277m/dJqMV7SxFhRlqPgkwWNFPOiktPr8BEwR9LNZRqh1OWvkF710X J4vJA0ZBtpH7f1Hne6JipSPVnl5yo1MfPgVGEno0jIxRlgPPJRSYH9QOs7S80GT28G70gIg/iG25 /fIigR3iWBD1rzwnAVd9UKSEG1Onvq+JDHd5c8mxhmvl+jXznWYcPW4yRz1g7inw1Qq9F1Z+ozNs iIT36H4thvASbDRypvpR/2Srs6J0erEwrrV6gzYX40WcVe3OiwajpcZifr5po8lJFuNoqC+u2KUX nsKE/tqPT3v6WoaZ17/F+p4gXjvKVJ4jrSRL/wMGfBlz3jEJg3gUEoR7MkaOuv2dlaK8tYjaaOPu vTG9aYhr0q8sOl1a9FMfisWjTsUrVZPFjQTrMv/u9OwrMt2g7C8ha91leSVfYtgOnaMC9hrUB16L wKfUxHMlh2aOjaVT5sSrD8eWHWhVHnG9oqPcIBkClAbgALM9e20gvKzBcJ21hVmmEty5MhAAJhf7 t2swM89QKzFaHTxt+o8n9NtphK9erWxg+nUL7mtoUQMOb1G7tpyrkFrQ0fL4mdDASiYYomf36PwL CPF/IzoMXVztvdCwBbd1+LTz4G6YDhUl7PtybTOlRM5vm+GFianPOJ/uJ9zv1IO3PY0Zlv9FMlWV fh+gCxsS+rHI2CVuGAwlnSQgZKwhGJxVkXqXbE4SgHpQXaSuwjJNYGs7FhbMvvc8XCHqpZaN+6qc /CpbbeNkHruio3OamgsR1W+elCAEZ4nYSMIS67wQc49xZsBj2Y2j3zRtgeAPclT8x34gYNS6lkjp F/jkDY4k51h7MGxYgxWRJYliBKGruHbTvntOwEPZ3HqyIMEugnoi2/1PTYjBFNHPYf0u5MbSIN8j SiNb2xKTHfnM3BSjA3KOUZ9rg2gh3NF2QyoEnCKkI6qp1oyez55RtLUQRr9cZ0a4KRd26nhV4fnV bQOTXcGE6cHbXJ/zM0kIY1ZoujYbymkVO2OM4hpA867ngruvvSbFAfaFxHlV8+C3zMKzmaC/9Fbh psAKZWWb1mg9WQb+3Fw7rVqPqDUQRK+2nDZnSnrDG1Rx5P3KHrab3AySY7dL5mLY6M3uazYNZfa5 FdEYzOxtqERvBRI6eG1HGcyOepfcRQ8gSLm8AFi9K3Ncnx7M3K+rZ+3heQLi7giF4fzuXn3PVD0f TGb0kAbqUb0Ewa/QVqzZq+h1WSRrNkmosVbrgljqjb1FBdXEU0thaMtngDfwhCeyB/F14ty6Dut8 GbnURKIDzGPxBWOwT/T3orn/6mgErzmWCvk+3dpI1OQb3OP8+HhWZswP+SRT6eIMhw6EFF2exiIZ 6sP/WXZNEJf/p9L4rMoy7kjESUuv2pRlulPv/NLY6IHYAUM8odhnfIWh3U4Ec/B+kr5Q9jrE7j04 KxYDZtYWUrO7j6TFGwUAsnbh47ERQrcCvw/1yXoBjWL7gQ4/QGmwQmR1k3U/7+uTL4zYXPJJ1A66 eJYH6nkCeCb1wNWlplPKsDEds4rLYSo9EaVePour/A6r3BDJSInahapC1/NQvZEsPj20Fabu/ap2 u2QABxAEuCF9H7FZL3hSJig+qsTerVkjdu3egrtNi1L3kQA2rpsJ/gd5KBcT7p3xASfR76gof3PZ A+RYVCrAUH4A4YTB/33Zin836D7e3jQzsc0lvc7hEl4Jj/YCOD8BpXrwFsoTjW8S7WzDE1JEBURc MSIj1axKdGJEtQ99telLbHMEdPKUqJZ4FPC0en865AIdiONeIEFPuOdmvDkAx+VTzj3m6Z81a8eK Jnrzm0djcfsNNO/e0GwNhdg/ANDkUN0m4sSMLhA+FoaWdTypzuQ6lu4v9m3cptAHLNdB0z/AOU+S TAS9MtooH6kpVwo4WXOW7WDViGiWAcR2TCzuTxXV8qHPpVxO38fVXAV9+eITmc9kUEq8y2F39Avq 45oei62AzhSnudej7CdGqq9JSGTbS7GLZP/r+eTL43GYle73eLNjlGMzVCJNQIIKwGp2oX09ZflT vImHUE1u2ncCIVLHbcNEnsOnCllMKexyyuz/YGgiihErUfYbci3YyUbQW5KeWF5chJRnSJVerfFF IQnoQGmQDcHWDZBYU3amqc2Miohtn2431JBCOpsgLM7Ufo7zjqcteK60QLR/EeeUwBDTTUaUOHvs a/YYbD6lAXMFcwH/GK2Fu+unvI5Qlk8SktI9U7NYMw/LqP1TORKvc9E9AC7h/7EuKx7BTG/Y8T+w HR6emobOVm2TMQ5SGrgPACqk7/4xLBnDXfU3KBiUJAv/w5/shZsTpzLnXPTwM6bCUwkdGFrcNWdO e1YGWHB4gMyXNgvAYbJpGF4A5Tj08zrqgf4WRsPNJyvp0tWln2NWmZxbyluW7bsSmXdTAePTjejT tRyUDihqW9M8NXd9qflljZKNG6JVlYMVaGfgERVN80+Z80rSotSJ4Qo17LaAuaAwWQ983wvly3Pa chRu9C+4CUFLdKATEgprZZqZs01vmq568atvTl8wqigZ74EFfGgt80mMMCQfaKVFM4bNxVw9BoMX 3PYpm2uc+eoCwGukTqZkx+BBwTU1BwaILD2GBrMqmcsyy+Jzb5wTdCz7yy6zoqjIznZcfxsv1EbK zKGiSHVhxhYywHSRAfCSgZbic3ZXHSCLKpEPLmJlfaJXLmG/9lFF0HVP1y+6R92l7B+RyHyg+iPy u5yNGS0ECCAEHf1KdVHoktGSYw4oa2t6WxFcqtTf1lOcB5t1FiPEuu531/u4BV8bQzBMbjIU1x5y +R1zZWHjT7uHpJvBW6YPjs9HzDeBNIu9M/NwAXUoVBFMHzV1F244r6EBsfC31CID+CmHyc/bk/oF KzuAh6TKAqvejmoZYCz4ZXPt2h8e3fQVuySizRFLTygJ8HkycWIxHQp3U0H/UrVmwBc8orSmJBX4 gq4up/3NKL/VThnfqsYziqRS1h3XR56bv4LLiOgyFs93kMTqJQ3nVunt1b/0JkRRv92YMebMydhD IaExvFUl0mGAJ2oXvB7frs8z1U/Kj3bHMssA5OLxHN4dk7nbfIwCnM0HPoK40yjaxfndgOKoTUnO hzv/RaZyNZWcdr6DdXJNWs9RrMk7kMQ/CFEqlE01tqCs3Fy6Z8eXaFhlGUJ8CoSrbo4HIO7ZFlzH 7JEEsSFJlN2Q6RDuVHQcy7Wp+YI+6yeP0z1ssajXvX5okz3Ynm3/U8rAtJRVESzNxN+KUxmROynn 3/vyJkBEU6G8Vxpzi0Knu+ZiRnwtl+aM1oPziipPBJ8MduCExjDMn5DKdWOYVzGGBz0njAOycKV+ al1ro6ZnTjmieEsukC1yNq4kZmjlOvB6SgBkomwViKmTICYsu8oDohuJm5mUTugsJduueNotsvdH FR3jQQYx6k9/aBX2Ha2DP0Aii/nsyMNnJ6x87GKVvVR8aXofJI8fvuQQeaAcR65gnvUWN7fJL0aM VE8+mIh3d9fguuo8cWpQ/Bl17a7QU8Woh9fVvfN8+arYBP0W7jdtp0InRfE1ms3t2FeJZipnzTOo EgaOmLCkx1POzH8Yb2ixlS3DoHSr/Y6d+TKNhOqhiXjOwvmPlbLlG0b7mATnLkefZZfz07zAOj6B 9D2iYb1k1kRNmgn4JFZOFfw0F5/hbfD7a/h5dbKDl72ld7rTeNVwBxELFsOCoD958dVDwwXUvvBq VENZHdOUDzzt8hU6CPu0WvV5m8Ilqnsx6PzBlWPMzawOHxmh8EyzMUjo8XmiEffDTJqzJuxQv34T 55PLy8cxCapj0hzjd4s6/ldiqF5uMVImY+BDKOGtPe0VWioFqsRjbMi+n25HGZufFtQJ8GlI7Qae 3WbMC/V639laV8w44LJ9e5PqTiNe792En2h+SFEkLOfTaF3u8kZLqlNq9cQJlRhxmOqEe3tGJ10g M1jelMxIdqNP8B0N5NrAEreI9pzWntSw2Gax4tqjSUBy126FcjmcDL9GoZELPTS15q2ehmz/a3U0 3bVAgE7/KZy1Cw/ln2FkTBS4h8muDnhxC804OcZXMjKt1XZrrjtprTdfhq/zcFNJ3pWe5GWimdTM I4cqZmMrX9HlejqDfKGcV88NDFYcYBWshCu1TdlpNyxVNi9TtQDNEvNbKeKNJcClRgSzRUFQF3CC LJRWKa0o8ZgNL8UVzvknIh62bT6LxXYvEr8/mGgG4Nb8sSh7PAzJFS6Hd00EcneeZzEe3f6VQlNz rZANhQSHzxw4BhfkkvsFL4Nm9KSSZ1n7QVnt0kj7QnqcdA7qkgMh/I6QQ2X3h4QZ4JN1HwK+Zrdm YN959DVhXJJ0FKZUe0n90SyE0Ob7TTGjfHj7g6fP5QIk85xHV0kUytilMgi8IT1NYLCl0I26laZD ebXvh0d3X11WcqJ1IVZJOdQot7Kop7RTjYXswcBqXjriE6BZasyR3guOBppA/U8axsKZNZL8GwgB yBtWeL+XP1x7Ma8tJLgIDq09WQBryejNYVrxkdCG/KlXHx7zT8Ia8KbVGZ2OwI7dWMgwujgmT0t3 QCk80947ZZyuBGi/SNYvzzRcQulFKNZZYXQV5QewV1IF/WHUOxVa34uhSXHq6h+kScgKXK7j3Qua PkR93mtMyKIxJ1iqRrsUTVQDNvoysHLYBZ1lJQ/TxDicj6pqNur73+zhFmSXTQPpCnKQY+Kpu6pY LOErM6Vbadp5RmvgU4xpIBpYxZ806AF06kc2ilXQ7biJ6QkcyVSY5tH1TGceZZ7+kkWMcvlI1E6W KnYraCNplDjo7EG9hGSOpD1U+vGFo902P18VfMOLZd4pfKDepKAq38sibX6/xihW6pUrGc3xqg+M xLeylfjRCQ7+W87A8+soO0LlJzqzPRra7UobFcC238eakAZBpumeXO01cJFfBlceunDFmrWKIBR8 1N5zPbqYFhtR0XLWeJNvibbjuNh8lAAWxNcuVL+ohpnWyAWE1Snho8iuXzoqkaKNXjGaj9uSct+Z 4GHS0Nb0tppbrYEaYFZOP219qRwlz6EEZf1Fkx0hOPBLWi68u1PuFKVl5kjScabkwhISKVBG/i2U x9wxi/bYekkxLYOFtkZwzHIbNBDYGDXRG4O+qk9RCeWi33PWxSt4Bn4RJ4SJfXK5uvjXscyTms9V kAA7hslyhJsLUiCH38RQD9eO14GMNdM/fAgfJVHRtHfxf5A7Nqz4fM55+axHwIItHRlhl6QTWEEC Z9UBhKuTmcqszKqCnMOubgdwfSggqHfWXzD1EWRVPmLoBV3tKFzYLlLVZGh8bCABit6DEoAp8g9A 4oMI5DzL3T6DwuJ7BmO6EyIsLnb80tnrE0v0FEac6FybTZ/y82gA6VlmQ8+FLs4qZ0NtpDnW+nKr RYWeO16RfzfJmd/6nbJY+lbOC79Um4WOuFLrJvKtQCxQclRGhQB5lZS5vb2Xt3p80ebkX3tcevix kk41hRhxY3a++1DBicEKH1gEpQ27g8wBjtlJ0Kxqqx9ezJHW2qD/SeuXnyvirBqTOuY1wMzAgAOj 1ZO87vx2EFh0JsiwmAoLEfQ0e1JP1O5og1B+ybIA0oP3qipeVWBtNpdHpNLDUtzn2icMFheP0sEQ qG4DFmQGmKNQhGfTRIX9BIsirZliU78ZcY2amplohkBLkehAOuDw3DgetnZrio9NnBgxcDcVy5Q6 9QmKXJGWUJlSmvFsb3F5MfnoE1+czUE+mmwhnE5h21vbd/uBPKhcW7K7k1NEX5WLAYWN4lyOrEqz fd9J9UcX/zVxvx4iq75uoBZosD0FcJpam/gZfXF78imbbtuEQsEFq/y/b7YGIUlcOx5p3wG/KTaM pXHeVGk93wobopa6p7zQS5RqGGAg+qS4qa6atDqIfDLhVMTzbtXHnFEmuPrT1bhkNzn0GYmTdajD k6Qyk5JK19qo/+Gf8shPX+v0i0b4e21FxgtKD0lkMMIdRLwAhsxQ98VtvEmzpfRjncGRzpMpY63z QtIKkn8atSYntA5z0gmbp0tx+BhKE+F2GKt3ALFctA0o8yBhFG3Kd3sUTWRKfy81J1CVgyOX96o9 lHOHq1mvxcZ+BWq20KBXS3ZEvQWSr31YkSWAcyS99x3GWr8NvYkp1F1g5RaRGfzxuAuxeTebQt5O pzCfTFFOsKUm6+p6RNw7bWqxOxs2AZIPIOaixoT+jVRI0x+skQnkmHnYV7tyFDgyvbLQgMCpCZeg nBs1ZCAs9MBKu2tTZUVhDIWPi3ylgz8bfYGdPJBOyU2k4MSbMUApH65ZnG6sQVpqEgq255MXi3em JInjcVqbaJnSYpcukDWM7oVneDTq7sLEIfXSaoo8zFWzbWdeFHR5+RoQbPlwO3T0HpiHYv9RjaGf tJuKJyUEpxwUAoJfi+F/H5xDKKw6vXJW6+PYHRlf6ERPSZy8SAxSA1y0RAdKuEfNoiqiZW4ynoAl vfPtcNDSwjdcRGsoymiPDjLesn9wrw0/wZA6Wq7a1vhobl9HNVt4//btn/l0PhVGQ2eXQ7LPMayc 9pJaO9KFSp4WmKfPTZltNQpp0ncohp5AGEFhvJ6jFWiDobM2mQZpjg18cUrrNMTR7kFrJeQZTSyj GdrV1dIIhE2iiqt4D6kk9l/V1Wl6THRYr0cdrjIKQZvIHljr/uY/RFYSe7NXGIe1eayL8Ux2UBNY oc8127FT4bLswj29DEWh09no8afS0dXUOtJPu6BthICOl7AeByDraIAzeBz5wCnguVGAwn+jDoPX 7vqaHtuG004KoOwPtF3ZjJuMUAX1PW+rNbQqAMoOPO8pYINY7VV2XZ71Ux/QibI16YkDNM+c3qHi 1uun+TO7bFF5Sv9tC1Lu68x8cWKbSGePHSBXIS6s/HC2ZAFqahpeIrhx2uCs86yrCAuPfcmqyxDU yi9lGG+OrAwxFqb1tAth0XJPm3nv9c/8XU8Dyfc4JdXiv6Reqg5YmBTnPSRjei+MAalvy9Lq8m21 fjKWp82UNvlkEJT5E59ZJz76DgAxCyEgKaNwrnm5ASpou0aTz2VBXBU9ETCvt9uS4/Qkr/Q4ycT2 sOjPg4I7AEyBaom4hKKJEcJSGlMVGSRh6XZoH0sn8MReP1S9fxVa66h4NVkhmhiCtUZ6+2N6YCVL gYH/8rk5JaGB0w6/qxs9z8THInm5x/pn9jHj9TyqBEGx+HxVZNyfEJT3kkP3danLeLGzWb53SYKY HMOTavqTppuMCaD6hqwRQEZZOB8gvKbKlAR+pc2D1HSOMrGQHO001enXbce9ciTYwH2buTIwTUfk byvO0z/9RAT1SbRyhZOg/PfDC5D3G9Ai5vcnvyeYZvoAMsmr0xi55LLBPjoJWLb924prxAgz96Ig uW8bEd5Vu4rEeSbcljjuprSs3TpVPh7tLEQR/eOvWYphti6VvdIxeinPQIN1IQSSGS9RB9gDkmYS DosTtUw4CiTI2ayV57uC7gQ2zi/bpFA4UBFqhwmz/DsxAA+I4Wo+y2B/4SLxkVhcOZdFSb9PMdFE BKUdYatHrtsL/J4Q7uub1/P9Z+S7FuXKExMwIAgrIyQDe2+rTZFUxJLJykasGMBtWDDJNF5S1Jac cyzkBsDlumVzAuYiKdlklVWmQjikWkqCNCyM6kUPlB2RmpWspza97/YPw0uWrK9QrlNxSnZyrKr/ t4fFvA6CriNiXKD9oSEqvXaMDtSSFloQAT5DBNQJsZRWY1GhAuBG6STdQj8r9q/e8G5/DWjQam7L edAQ9saClHKhLE8DwQp6daApCZjX1kFXmQGPse3SF0nhV85GSwqqS5xZ2I26QII9tOEhT0Gi6dSO DOATpfEwSw0QO0H29hrGjdnLOAM9aC1X4bOhuibkkBc2viMEA6zauwJ/SWMQzYRuonfFYDqDohQN PLZ95RaglYerQA9TzPitZRaqum07JFWgOBlJxq1R32duaD4uzXLPRMRyp4OqwxqglVp/0RmAyvz/ suPjhPds6Rdpbzh51PYjyzTeGhS2N6RDneqpGWdJjWZ/LAkt9usCd93Ecj9oo+RdlG6istdrm0QX CSxA9gdO9O++p3GZpHyQ8JtDneizfFf29QIrwBerW+RhImUJM4VpsQhqFHfi5CBk9o5/Z6VcJcHw uxZ+qcMaUuBW4jvK0hG6p+6cr2RKGENWWPXTOlOHb06b0l4JIL4JBXHai45rNWu8ar7uCMLF6gyo JNyyeamkkAvv2AGPM8yMFgOcjhO7hLZvG11x29BlASJQUA0BMKpSITuj2y4V1zlTdCh3FI9e34nH qs4TWKAa6QQ/26J+wxTTD2QQqdHUOMBXkIOpFvBfw0EJoIgg8qsEVplavIXR3SioVVNHOW6jlMvD Y7VYL9+/qnYTDhrZiAfotNgm3dUaIkH5xKBKRLIY6w4FIYmbr3azQqL89tcOum7sFA+oOL1X1Sh1 CE0ySfecJhYTL5mhUh3xrU9v3iCygXcD7yWxBr4HrbogRebcCkLALsLuaZ3upW1TB93Cwts9nFDg MXKxP7/Z0MGNux9guVH10OtXXeeIBHuQQ6QHt23LMdJ01HC6ubgbFYXBIfoo0QvSQ7AoI/SpcgZa DlejtyLRCUlFd+/NS3hkVx14futmDH+kqzHgGfHwEDY2oV24Gg8LWvWPgV2P9L0TltdP6prGcFSr c0OXuJDnaLw7DTpYgoXKeVvtfai+ELLSG6XHEbRO1SUmOLHIENudOHT7XVWWxMzYaHvyyWQdv1MM gfPg5ntZLvbhlUdaK4LswU2GzH6Atumthgr2LRnz09ug1vJTZvMj35uixdAiUHuXZxObOHgrheax gIQtNExrJ4LFWYrnZW4yfdYkGAmB1HIz1bxyu+LkB2cv4aWENk5IcHvmzS84Cu8rSCFAEdsJCbau 66p5E0gwWrA9yr1TQmo1lttT2d5AKcyMtT7ErCrUbQMpx0JBUd9opDnXAg6WHOzo75bdmuxohdPo 0pn/nxn5mFWjqJfO/bd70ZfFSRVvUPfIQfgHHiYKAnYAd2Bwu/UedPGhZguXGWbfYlYGT7YFy/+u n2u+6cCPofh0ujdUTdOCQxwDIWQMu+nLRwUEU4k0C0yfrZ/92K1i+livMoAatmMKwtaqOPwFVzCd qpi2fENqpg1yhozrbf7A0uRa84vb5E3QzUz2M/K+6Q4xPlfzrFQqncCWHJbkRgqJm+desVZSFyTi 04GSF9Bib+Q1A6GESZwDSpy0H8VulyY7AZruWKiMprc+YuK0gR7F3ivekcPYRCGQQi2LC/Qfa4qB f7R37uR+qUC1xP/BYOI3OGLRI/61xe4topGoaU2AJyb64JNKacCrFru4Q1/4+w8eaWY11SUkDnR2 kInnR37pdBcuBbYDeBdVx57kcuq8wgBa6kLxyqR6IEZh4n+1cqZvixFI+2xqeSerLctZWcBp82os X23OtjJ6QABRFh1/sUuF+2S5R7TR6tBP10gPmqxQWXJT46H0I6d7vutcuB2tgKmLneBXJgF78Q2c eypNDiIblm8ghxcrY8WATLq7k43xs/X70kKrTSFga8nIL4bKezngvIlLjM4jXSNPEXmnoyiK15Lp RDuEUL0w3p7gODTkhOuLLrIWDpFTxP8aMM9kdg2jGY3hzPHJJZ/uvJ8UgnrTKC80v02DmyscAHk1 rm4nETv6c1bSV3LRfcOPLguBRuwlElGooU6VqgwzAFTk7Kg9gW8MVfiVGuUX1U6RsUbBMkQPDX95 Sc04Q0uTv9jnKN4j9libJ0oaOxb+9fx0q3Fd9TvSth2BhqgsenBAygnuqUGCWrJSG16dG4m5btbh 19IGiw10p1B/m66501vjtCqfP+gCy/+3+Lt1xNt3Pmnrlxiz4CJFUsTqmPcfCtqYT0Xut690uxh9 T5bBIbF77lm6un6Q8XF9Fc7ljzlloahTDBZZEGrcdi9A+im2Thz8KyTEdxAS/TSWDsHP9E+Gtz/x B65OD374uG5nlH17N/p9nJaMwkWe3SUR+3v8CKBB9AhMzaM3wACrhER730WahE+BFXoIa/Vac7Tg 1D7lnRBoV0qe/9rJQpQGCuevlOwF2u7mMMUtdudZMwtSGdTPZAosWFzEm1zWdSis0ZxBHzd2lXqH wmcHvycYzAO9n8A0+FivqPq27nPr/g9AbYitmoN82aUDrxQKKFIORgbttSL5TagZjlVEs/yCd3/K OYV2PRnkH2kRCyVCwGQB6y3ixiHB5ig2zhA4N709Ygl9cNeiShKiYUL7a3vTDeD8jVxY/p0kj2GB /I4B0A8W9tsfQ5Zu6HgXRj8cxm4tUzZjHYX314FG2SPZK3eS65vPXDMExqAeWC9JUVFnZ4qK16Ze 1T6HS+P5jLMWw6tfD4GPvHqffj2BQaU3ks8GLbwSiHLJ0YJH29TR8Za+OP5dol6H11iH5gcIIUIy c2NiA5vLW9KBwftffY2uZKz8TSJ9O3T9SNQf8wE4ulDRLxWulZvnbzPkIIE2AFjfVY1R+kwG8XOV YaKZF2RVM54hQRh0f5tBlsDaFMCcoZnHt+ObpbvM4Rl1hlaCRkyG+Or00PT/7VXZUbl74kfgf2pQ RYAuTJvcLx9ROvZs2OCRgeC3I8bAo8j2PzhtocgeipLWdv3sr4JajzTUQ0oDt/H/HKjWGJtQUP1c ajxMurWo99UehKWdvUODLjBNqecrbghpJiYXpsqvAaGdjAJwknbvLthjpLd3yf+GDyxxAMMy3GS7 G/uEvBpCdGbQZU1vRx7k5sZe3foAqNoB0cLZM7f/fuj7fKhiZtMwxjl8vCXyoIezNXLVUE8OCw1p FCkWon6dOlgMRm6f/I3uh5DrBVYZqZW0gr92OrQKj6j8/r2xg81Y+WXEwq36Jm6b8XJTpZopGv/Y I0O3n3fTajLu3GqTVfJMGdR7Bn/O7tPJYxbBsB9uVjZYsCP845hVDFEvsDu6Qg8o4AYt7iafcNcD iRGH9sN/Yrp/CvwdD68B32uiVtzH2PmcpMQYRwArgjSJ0w3dzfni3+gnWa21F9sewdtJ4gFY5xCN 0hHsd8t73G48Np+g4wiIc17xubz7nFMfGpiCGrEDrhMGQwSacHc+aplz78brK2tDuWIGBJ7is7dl zHXkkV1KpOinz/WbzIZCMei8M0mIaunj3yz/sxAjabFSjza91vW7TfOLduKhyqRDsngcFhZYfnZd ZDFunJkI7BckPw1VbxrzXEvrDtMgRNoBBonIG8pZF8XQOvhDUdgVNuXi61AGw+DHVtO8Ii9IMfkd JwR1Li/C90qnVaqnnGLS4lOOrz9aLMZ3W0SliGCDD619Md16IfW+ThvvlheeTwNs6cmWw4Qq11j1 LXgbeN2jmNX6d2lk8jkAdJ8+YUllQdXD/4tFBBuN8R7+CNGaql2yIlOUAAOVKLU/uXDo4ryG1w7w RApCptrObhIdmmPw+kSvQXzRxFaFUyXzUUnRdpfcO12vq4NevAMVT/T64MS6jNcmArTWwoeUxBI8 rtPFgAhFkKy6lFXytqiH3g9dBj9ZdxElEt4d02zImDYuU0+J64L1B83RFypr1dtoVheaxKi3Rb+6 i8WHq2zRqZ/R7PBe3VilzzJTaQn1A1Y18mlMTD+VJi/gqGAaMcB3JDc50l4bYUvnVlmn+eYYVjDX WKJ6l3kLbAIE5jxjpIFO5+AK/0tzMVhL2+2SGUZBWeAO8aEC8iW2TSWvGOTG9F6I1U03DMgWEq3J G/yK1KO/SXrPygKYn0vhtUXLVOwbMECmZ4uYkUNQOmDIB/1ooqU9minQc7RldgFRYsx8e3izfojE Gw4YxkfdTye5WARpBP5PMtCspNh18Qpaka9Vqtp4rfvObcXdZAhGR81axJg9l9oBJx7Hwj2LK76U ZIIDcsAgZbMGLOzs3sReKm6KAGmwNrncCqYhMNbTOqWroNphHG5riWFE1elSqOTN8aDCYOLktMf/ 3vpjzXO4geEOWL4R0OtDYM+VEJd6g6EM7mfhr8RXDRfMnVtGrvfcYGdy0ZyZzyrqgyTD9Ud1AIRg PSDT7lqerSNdj2mpfSgZ8QXINWEoX2sTR/D5YLQx7DgtEGppkGzl5Dcuq1UGHtvpLWlda/BhbG5N XQpmvL8Lg/fRj8xWp3WUBNWQnTLyNRp5IXnEhq6OozjhIYuCCDTyPz2wTw2/oU+A8G/eggqHuNnH 2XcT8tOJsUxuJZ1GGUA36YLDvNXyiXQYBFt4c10VcppWzrv0G4ynstiKbUWiHOc8Tv/dZVLzR+gs 6/yCzWaFZO4uPBJ9ifNor3n208+j89tOVDK3Rf5mUm924Pr7kjvUftlNDr/b10rP5eEOkqhOo33d ryvJ5er9i5C2S//cn/fmMyPURg5MRVqDTExuBE8i2+g0nRsvD8mbmgLreryGoQKz6kHVQ+t0pcKd ozkI71vNn0p3IzvR2lCpElVL8ROCW1JI82SFhvcXb+IdgzvRGy3NdhOjMs3iCVM93EkpvG6PsWkE J9Ft6kG5o7QX56ElhlJOPm3Kace5cUKkEktkydUyeDOdSJKK9cbelimmJ1NAfSRvlwLmF9kH6Dsz DddQtDozGXuQkfMeA+sHCJ+p5oWfvSdo5I3bXskcSEas2YYq92bg3200CkGxgsW41Kffd6z01Vxb 1U/pgPlTpUQdpXdCf/dj6DzOt49KtBLLnkw19+45NkeW/WzZBE6yPFHzqGs/gyO3ZhWnsBwOWOrQ kHkQ7UtHNsFhlVMAG/r9hjnES7ec594/y5Ugyee7C2NCFwBbgj74cL2C8HZZmG4j8vCCvtLhwNb+ DQ71/ZbyoW3mBeJyaGnqQQHD+9Bv2OCOKll2RKv0S8V5HdAeLcjPcLAMEy3mCFkRuvNBicvMAKSi DHzLxARGvFPDebG+MQCp3hDVO+KT8aYNnGpfEh7cBH40i3x6vMnt4GGNJk32zxfX/J4rwHUKVMoJ 0WhFV8xTr/SkNeuGSnH1e3yZvlUlmKPnVLPgQ2dAI6PmD1oVpJYFbj7SaFkor3C+PPK3TQ9aObPo aLkI6E70sdH1kPja9Z7O7+ajXp30I2VlXSW04SOUwiNXl6HqTJaTOLPDpbBbcegMGH+zUb0w2tfB ataLMFP9yPwY6bBar7BiANY6b6PRoImvD6tLjjUkUPIj9vM7S/mLXBt8HRz7VIFpy3iRvDAtbqXO aQkBOIGmxCTXKX/nn4B2iON/LAvA5cuaC7UK3lF0Bgazkjh0dBUcuj+BeBGOFBG2Slwq1qQG3/+a 9lwqDsEM22Wud4dHlgE8gvYtjPtvWlg9wddDI0gcyR6ADyGrw/OWF88S6z4v2Z4eu6FFHYjJUSqH 6eUBj1slM9Nqr+8A5UhKg/eP1Ul3DUyBkkkdDttEMB8Y0YNJejrNtBm7pW3AdDzs+kKh/aPysdXc Xzk7gAXA92ut/finoIulQE3Rd9nAMXBEOVwx5/VTTYAp7DBj2vU9vkYh3oBWgQH3zL1AGSk58M0K sbAJjVka6vSH3s5i69i8ntE5nUISxt8AMnAfgayAziqZoQjVX6YP2hXYxb/7pY2pQ4nX2M5gSC8S U6hidsMH322O2Zaq/A5M/zdW8ScWOX1K0msNk9BBbZByrQjPYStwiwOnofcaBGY0vW+p1n/FbyX7 TW1Th3UkiInDhOSqXJpUGOpVCBzfXyS4au4baso2dnCiBtQo5LvyJTyx1QQjXL1xIUStLzN1A6kZ BYxeIW2SJRCh85QV4mJ9yL2LnPhUSPWNlye2VFM4I6fJfbygOOoBqhSxq6Tqd5f523MFF3jexEbv Yh0PExk1Fzw3zZZaVJVUDxBi/UzvgqJpG1XFeUHKl1J298weB+faPzSxqYayAv9xC98vR3VkbFPf HPpBtR8ku8krYSOXszM5NKAOnxsWKxA5mr9CAKY0b6nwGh3m9EOUg+nrvXKeYxJ9Z3MLOFuFR0V4 cWHzsxQeIy/CCxiPPmdVJS8AlaleZW1Dm5ke6S/Mf/5Xv/uwOq7wU4EDPyxEGrWMtQ4bqR6I8Nwd 292c03zzdAtgEzVYe0yTiNY1UdR3Fue/jSan6+LhCdF5lqRxD5msFBloULNqXpzTWU8rGYZWh2nS I54C0YS2l7PR+zJT1flyWBAiUwXzpx8FjRGb9MzynmHkKlHAkHTQmwrfW8Xg7bGRdAwbeUNS/xxR aCydOaiVuqaCLueu0dW68J5PBDxJEB9U7VMfphrgcaaKLs8t6o6Gvh9ptBw8F3xksA832ZFy9aoz X8u8H9lYtFseil6T2ZoPkDHWZC8q4o2oboWYAmy1mi/uXtR+AuJNF/y3cRj8JWwRX7ho/LLVWjHt NiddH3PCKTCg8wOk19Z/AqKhX9rqRCkIz7C0H0HJp6B9pv6cQ+tAjsu4ygce27JrmdmVx+LKbESs DgKnZm0VKP+h/J3QqGODt4xhgREd+7+ZBrePu/A2oazku/XI7Sw0TS4jhyfRW221xWxmFfA279rm jLAcxAS536lcYhBFiHHqo65drTsrnM3odYum2gDqwGpjNdtLCu4whIsT8mLukF+hRCvohpC8edrq AiYqC9an/Eo0LRo2JYvSmgn3Aa4mqin8DT3lBWjbLSUR24fkjHFDWQTI/hqZ5lwFjDqnCbmQpr9k roCegdDPwi9V48W7wB9ChD8hdk6/wNpS33MQubcOBbRpHS37s4lnQSPg4SNm7FbRreccRypYDG0X eAw1WFcdjG5Uele35qIusq2Hz1hjdsGRD/R6t5oSaMEZ/bpwjaLipFabDZY7hYBSoukoFApu1EAE evckJ8H2yG4Nxo+PS0bRuqXWXW8cwH3GOOyCMnW8vZdHoggCMHyO7SY6nmNm7+tFWCk53OC50h1z GIAsCw60ZJ3NPpvHXTogqq6/XDCIS43FE81i2vIFyRqNRPRKiE5piKbnd8r8Y/YBRzBhJOoWtgqx uPxQQ8ADcppfSpIv7fjv1gRi7UNkhFtYaQJWWN6aCvanta468XJFxbX6llcPjpo9dAdvAtCI7iX1 cw5pmzw1Z8klWnTFHsQwW8zBCFB8YzIiXg8rvd11pkp7i2TxKpLuf1KUBQq4IaIOiB1kX+KhVaYt xkunoeOMQELn+iXRMpeG4cxeLbk1jxs4A5WbVABSKGbZMjICd+L8vaukEqEfMl0xgCV6ptbVlJoY TBs4h4Y8Vxu7zjGWri4zXILg01eNPOKhIrrIkNXcaXtldsdGjmH59vg6WVOnK5fj9Utw1R9T3NGJ XqdVHIM4MIbW7acEVQ45p3QxaWT9Ip8oNUkI3EWzD6w53f0an5s3Dol4Kvv47MoRcPy6BBOv751e g9V8W43PWDklWEqihUZp+fsdDkszkUNLR2g6peJVSgVEwVpnPn5IJKo3DEpk4893zBqt260omycE QUp6PCikoknrS2CJvGjJ5FzMRo7HrImMYu6cojB4ZWsyERJaZuRAJaCbdfQDZwQQtrPUvlboQUnE sXGe+pz70aWeLpmsjl7HnQney1uUF1nN18zj6/D4tD5Feu12DGncAGkSeRMl0c4ohVtaVjTzlp+I LDdFlM05AreGKOuuAPkp+/vEWaOjOK8T8zTB73PP5tYsYzOAwC182EnpCoEGmlfK2khQ+9X1ORwX 0Im+rXS2H2q63Jw+9BpFHugkLo/KEAdPkF9nddaTpGVNmvgYrpBlqDhcCZjPNRJhfj/YX/p7gW0c YT/9UuNUSRPiJ4S4HLb0BiH4pZFqwmsHk1hQ+anBIoGYqy+jV1qahhc3B6p/Ixex98Y1VuGurFlI 8vQ0yEKUKRKNAEuVWdWGd3TtPJnYtIZTw1kHOti90Zwa77fAmDlKFvkwHneHJxN1pjzdOxelysL0 UZqVYX21FBqg29z6ZmLF31ERWdoq8odGZkcukaOVv2kBouC/mOF8UE1/g3IHScvV/zHnrPKXipkg Gh8HzfK+rooHWvnijB5CyOl7dWYA1dbkGZeTfMmTDb/WWjBKswvHwsg6tjfU5PrUsQAqjRS3mcAx fVY221rdec2WKU7EedOCpsmLCWnPLMbRc6umdaZNrwBZ10aL3azU1wCd73iVZW7iDHUcSnHmEBHW Z2zgejlXbU+aPXuhK/rQIiZU1jEu/G5/zGEcf5jSmulK0mfIgMGLsWHXKVDT6ctT8WDxMvtr/q9d g6lz4ofKUB/UuvIZf5Z5V21ehly0AtOYGyW0lZ9vWv0HqdKjvHFVqEicSMEJCgE7TYC6ds2rP2iB u4Z4fK0cfMzrJZV4mi3QdsZBdalbg2UxMu9dsRskcJn/WLRbaQuYvNWrgU6PpjUSX0kYBTJi4A8w 08etq0XovC82T2PBrMZQJtNxA/DD/ZSdcqIzmnNMWfwqzYjKGqqCxRJX0c4+nd5lySOONPk2aP88 PDXKSSdnjNoin4uhBSs3i3B0E2utBNJZdGWcsHaMz7pgpo4i+9lyiDg8Q+YM+2WrKCm7bOyrQgVP 5UOlz5RWmYSCh4gOkSAETmbyeJhOMm8vGBkWny+hW8nnesdd6/d6u8ND+jKXU3Am/SFhE6OKs5EY lO6ISdE1PFQZVkIplyeEBUDWT2DLPt9wgdUoFq71Tu/kcvhK+PkurXuf1uFJIo/hrCkxDCmdr6/U urQVWSinegidDFmo5NeqAkO6a/lF4M/8fuxxVT91fwM/tkyVkRhIBmee9/MZHkRaFm0T2SM7P79i 6T4s7tSqg95COuLoUj61BS4kYnYRYnWQMErj9QJS1jjDnoTewIVzSLZyMsOF1tqOMdKnj4s9Nhg7 muizVa4dPEPYvPr8SMNstjqz8dfgAmKOYglNaasE5PcntghIOlF6bfhfl+wWO21knH4h8GgvLOJX WFGMQE56o/wIrXUUMjXTTK3IcEXg2UAfcjkiYyP+kUVRQfz94kse8BV5G0GxXHPvV0aEwq8doyQ6 bJa+ejFWqxBKdgz3MJF5T2b4zFyGDhzfGkBsWgLLER7EJpD5wpzFDX9aCtapCXeBSAUFeQaXtDCw 8XE/1ZBSJ39kDl1EOTr4i4Z6KStBnDaZkJeHkR4TH0iu9F7GVG/jwHJgbwRz1flK+rB/LZY1rpYI oumUOPMiRGzYLrvuyH2HO1eWqZVFLnpOuWR2c7PFjY2WyBqJI5XwC7AMTOHA0ZBsYX6dLdlWco9O opUvk8zTWSHlP6Fz/98rw265tk1lhdOmRYptudlMvYHTaVxeVjQxr7w1LoQsiYth5F/m29hLHePt qyEh29evZHjXoiOZVKtmgulNgdg+TTQ25MFQ7XLKl1x592re5AZC2NSQVNe6qTD/KG6ghH01YJeZ 8XW3FemUJjE0lcrpH8XC7VhbYv1uMtFwfCqYgBMIYgPFJktqz4yHBv3u0Qf0PRbyRwgbow/K2lb6 5EeBBE1fYaVG1NdYEqWJgIUWDxCCR3IunQbfzSrl+qcwERKbaxOQLCVzub0alp5BiyM9YGNdjnD+ Ll3Tt6NwkW8SC4LLS4pcDa59/sq/7zyPr0abEbUYZypLTGfAOOOERWdCo9LQM1oStBsvXDHyTFTd afyxLOTIuye8try+Bo0BJB7GGoy6vTeCy6Tbw+faqVcaK1Zqijr2XHI6iR9gusWvLyWJ/9ZyoUo4 6tB74OUU/QXG5CxFFVlsfDoHMOtXN2icTrs/yQtCFw3ZK+a9uM/S+RBoHStWLZKuVtkqI5nNYqCn PFu5mrWdQnFWiCW8tWcn3Bu28IDUuMoJRmVAT2VA+ri5cHz6avNp87uzj6vlTCZjGd/8Yl4bSL9Q MJq0bBN9mn1ONlU+d/dKQC4urkOPix7ag07phycD/zhPZDa625ZMVfb0nz88fNhL514tFF2bkNmr fOwwoBzDVG4Tu+O/RLOCr0+kLGcfsTaTYGMPuBCeCDMc5mdL0cr/KPc6ttDooWb36N3FcAGo8Oit hOgZ91QUvE0pUBBgE9KIJxxE+qZPgrSdOv31ELno/DSB9JZoJ8//Z0sm25fUpX3yfNf0znWBLK2B g4BjTCwTDuQ5jUTf7d9MCg5BLtyWvfjoJjsOt4wwR8o//bJEvmw7o/eHHvaiqVzbHcO3zggbTqqJ eAQo1dkY+LCOnBYqwUR/3ClK8JhVkTfeBvclXu0RH+8apevWBm7aCDWUkRwKdn5zUdAiO/jv8s55 iNi9ZPL0XbvVB5kAbBQYCv7CamzjYdZME1Le+oTPIPv5pV4F0a+ayRhCXCS2SPM85wxs0gW2++yV Rv5I6KJ/xtfYM9TCQI9AIvbmUzX/RQfHpCRMIkVZVZ2pZyfEB9h22goknt/CQ65Z0o+16hPe6kSl rpEjUmyO6+tISyOjfXHXULPaPsp408v0DmwQ8py7bGKThZvU70UkqXyvGoMXy7XHQX3Qe8K2fikF xunrxV1d5a6fCJ6T5vLA0y5CnJpUUuk3iyGmbnQi5QQ90EwSiTVxMmSZPcpsstggz+Bmmw11XxFT hiR71gWo+sFhr4VOMeQsOA92MquzXXJSBca3c2xkOLZGGRD8HmpQbUg0JTaDreI9VY4cheUm/YDd N5QQhBuGyZ8FJqdS2rts0W3beHD9fC7Qaj6+Sr2m/cyGGkvVc7lWtXb+9QK12qifczGWyCVkOjPc D0/Yk8saASson9+juW1leOY2JX1E/K3z6hpxLfI3bvFL4Uako4YWK2xkjMjAS96WRD5SSzGOtCNL KbRsXP0Yt8JhgUFZrmRb4Tz1JQalPkau+Aqz1Yj+SbX2DvfIKEdKzMloYD1qGNEhJKs4aLT3xDwD PSSL6axCNcm7dae7eDphTXHzo0/v1xi6rLm/hlMAmhdwgH4u9e7hNu8bH5a8QhIUQlK/5LujQcBZ BJrfIYDCzUfqCFzADN9+pJFpiZQfDjLucNruqwzGRf2lHAJhFmyIKZ9tSWbHbniR+/ISVvoIzIZb ioG73Ds8Wnye3ke2Pf5zRgYj4N4GuNn4CM8YRpZLNPsUTydDmJvZ3yCAeJteQ6f/0KFNpN1KPCWd w+XZVCisPMRmVeNZ2szcJNPFuovIB28RJeAapFovChjdWQSHuaFKH6XeV3hm4WSMG4P1sCIcsjkE G1XubQ3PXXMboJHusWwMGUBQ/EAbEirNJiu8wXklQADxMuZOhBzVbz6w3fF3szU0lkVhmrJgyQIh rRwEzbdhMKfEOStUutXocc/ljAi4H8iUzrFgrdVMT1F20160JBgbkVTIwETFaYLWmI3/We10NDJK hZZGQwVQJ89UHfKwUojvjKONg9UPmtlnt4bQYB0KXCbwJsiFKY/8IY/8Brm0XrTrNgVJxc+S1O6U fY4k54sN8NxW0aGfQx3km3tc6fuE4bX6XmNiPnc29U4gv/a5VJSPdR5JtRutJofhL3F4/Utx1P7M jcftnqvVt9m67SmLKYGsXN/hWAd4OgBFmrpYDWbHfMohN1IzLwMt9psFRjz++XuAedLuXq9q/S/L pm9D6biOebKOzizMnoxl6wx8pBwrj5gyjff/IvRuwHgXuaetReU0h4WnRdiNFcDbZim/jppa1Rc2 Fm7YeDSJe3ybf0xUNoQ5Er/40qv4dASBS4YIr8JxtTqKzMH5X2y/Zbil+NyWxh0AiLSwCiahUgLw jR0bO9/ZuQhfoBtL8AlWsvm2pCWvwYYa11Vn4Vq+JOFwNsy+bpzRUHEmK8wyeowEyWLMt6q8hvB3 CIeG5QxlBvqEg9K0q/BB6Apt20XxmyIF3Yc8ZCVV4j9uBVKMxtSxbYFBksaGX0Gr5qJHw0c7ulSf FPiwCuGNv1Ftnjod5pOYCGmLXmdNplOMMtkV1AOIlopJrY+sg8N1Wz3MSAaxErhbM3+7t+DH193g lyFgeIbQsJ64QLpplSfbxxEbkZsL6cgWAjkSrSH5hgYsJ2QGT1CJ+ZRPWruBrTPQ13JzKuP19ii3 bK81ihgWMkuM3+o3OdHnMeLJbubHFquyZe654QkA5sk8eAKizxXLExf0PcFqBdFWQWpuLzTbZDk3 LQXCJPRspVyiRlx+QRhKUsjxZFh2h9kQ1uvQ0e65fFa/Rm1ZRuKGWpVIxYEElRcA2PmplMaXIVV+ CxPv3x44hcPdWKZaU4X3hOlL8gUIvO4eVzvNZjoy0D1CApEZsdxqg6350N9ojjxxL5qEkbRAQ4Zd zd0U+NfU7DIoCfo0xC1kyeULz9cfoiiJGlJomKFsXpHobE/pJ/HPHl8V7rebd1a/05IlDroESxs/ AZTbIpyInOGayzGYhrH3p6ye/mteSdx0WuqX8QvRaVQ0qFqcSphV1/VjW4LbtPQtCnQyJUujVgc5 fV6gLN4fFbwcLzLNbcl/tELautwoMGsngn44ydenfYllURtmFaKuj90hNBpFgkIVwBQdErrXg44e fITmCN20oPuorvWPijVvSw3d+6RgBy4xiKUVFj2hCdGihFK0VgYWN/Dm+mZFz0VCgQEo0Vl56+jc D1LzOY1JLSx5AmdluJ7oyEcPEAlNWlYbK4xtmadJ1ijdhYGZFJ+AxPXsnukUGL+bhfhZ2vvncnjn 1F0j/yPpZO350QRo/gxZe4C/m9+AE6p335BZn8xDqWmxKw9z/XFUhA875GiTkp83le8UH+puc7sk yDR/dXksr0aBTivz//4HMN+0/NtBwuLZqY/58QnaihYcn43UVnw4oZ+QB3xXvvr3XQMkQEMF1mwQ M1xwSgNQRs4J39/70K3CVC9AOrjDS844gllVFSwZwlb9btM4y2wh+BvBy2uc5nngELA4shxuXma5 N90FX7JF0UWloETSxPQsKoxppGeLG8Gb/XDAeBv7dqYGBZhXxpGYYXgLn1dcQ0jqxYCH0MBBDxWk JuYDQAoqq8VKmnOIbDWm9nh21ekh6+EMAke0wnQQXFS3wX5ISyVEpmuutJJOlpQ2uY4kayH/ZEe7 0BAEFy2qt6aIpIfLA53LG6T4Fn/Ghi9i6wzmbiD8eamQxI/sWxT0PSuGaOoohooJko75btGaJvJq S4ahiYqwnn8fvhBnXKb7+ENa0Jn5TTzob8WOf8uMhu7prEJ6GRd7vQu5KCHZf/R3IR1jBHqYrrRo iVodnwDnySpODczgEx94r/T6N5a47LfIaJD8nf9BBPPtojue3yK/q7tzYxjtVz+30EaA8qg90MQf Yb3SxRYVyo/hC6uJSF8bYXj0si7hyRHUjzEji/qLbpsOQEz0M/CcEBf3GlcS1rw3VdiGmluvCAIA jjXS3zJAditOP9JSdszuFhulRqgzensgtnP9jyrw0OnSDx6cfRW0bR3RVF0AbSiv+Mdq1rgJlbr2 U5KyaMSRkNWQ7AfPnOfzOLpFDsbDUXYVSSbs9qSJipGmBPFRkbD/ctEYYSeQJLcKnmSn/gMPALcN rh5oHhDUnyh89DZgWH5t80lWjBooxQ28guKIIlOezsWZvP0v5UOT6gFGmBpHx7Nrn1HyCa35GEDv NKU8SFJrtE51W9RW8VbQXlBn4NnPEU7OHO5fbxieWm3zlWKbmlNoLDLUa+YQB4LFP9jICzI96PBU z4Bdnl3enM20GIEJ2CwGeA0hPwJ6xrTMp0EhyOXhjt5t2BNbKWCgLbaqwxsia0RmRCdDfp9HI7lP 94v4AwEnNHPgqJ13Vzfq39XwBLYQmwMOhgS5dJi5TpdJki6aldmvnrCXWaRDGP5Igzn3034oPOsa Vck/6DU8pJNUlATD1Dt0o9u5y/CXHa0O7GGspe81CKK+vVxq3YmiRhtEOAm38U0MMSJAZyGUeniO WSVv3LJXd1ssCgpCo7mV7N4/GJP37gosWE2ekr7mwaZvsUVaI0rgjHXIcLXTnpOq4xhJghRpnwkj 8LwsfxbNplLv2GH7ZAO2Q4vzvlXK95rRQ/cOTOR7i+Y80zQtjOZzX36WRPcMur+NxJHCuYIU1olW NSyJrxTU7pz4gm4sxu/mKwKbEvuaOFd3Q9bPuagoREIkGRNoFKIayPEyFd+DcC6DI3/BLVAVmOGy fDJwTm7Jcm0favyj7GDxdYjyfPX8T9/2ZnQ9rR596vNmHJD/sDKbYFHWBmZKUWtCaEEzBxUP1RHo KfFCPweQGplbTNleA9vV8BSZw/b/0Gfhai7G+4xGkLPSRpolqEn/afTWTJRB49dQZBMSlq7Ugjoq c1+vsVeqtkYxv6J3CIRyZxVFCBIpxsv1qiQlEUVcazLoKH6o8npcmt6lZe7RscMSz8fEA46CnthV mldD59Y/FqnH+3bboj7qPR24wRCAtfJTMTPgPu4W8napNYOE2sMYIV+FjM8JDkJI7Q4n3cM2m+PG WKS081kglXEXO4SPLzw8PcZe+Snz9I2ynveK+Z2cHElcdMLxtGdFlRnobgJolQurqYS4kaKF7fT3 FjeL+tKETrYzN8Lq+CmUBEZHxTzLF3Ir2z6dQO8yQlnhCL045jfiI9q+wISIl4HO4ldbyomRgOVc SIVozP8mQTd3YkPujwaWMHaCMGlvnf1akjT/MPQe3ipjgg77F2fYR6+Ta0koR6Z5vWNj7mxfuMix u+Yuch61NaPZZ53sJisv++uWpNXDSZY2bHDP3GiwUp4vs7VbDhxTDRiK8Bj9MVZ42iSUETcr/U2o qb/gaKZeo20f4B8hSyoul4zu1rKpRQ+NM0eM9OQ7zrwvn8zK4kThLmp8H5XQBfcsCYxa9RdBmkpG hkjOQu138BUKCwyShpH6qfm1Xm9e5ZsLabyEbfSBC6cjHHV7jrLYu225U+qfJ7G1KvrpoC5PpS6R 4ToM4rCtsC1PMb78LcLtHH54SQWOT+u+PXQXTiWQUsliB8U6N0DbQj4oKiY0m0xkx6ybRPyhd7on Euc0W8TCWTVk87Tkl05rKeQjAl3dk3wg7BTuz8eENp6CTBv5vVXbSUOSzPUyIXCoHL299jBCP2Uz ewnXl7vvnG82DjDD6w26MNWJP6fQQRpyKJL8mvCx/rG2MKsQmF0QG/b9w4FDtP4GH2nX2MGfzOlk 64J6LU82FDQMailF1ssNFGXCaiOJNLlF60BHmsBSDBG4IIzkrz8Wzl0a86wTRlbltWVDnkx/gdTZ e0KI/VuJ8pBeo7lVgpziLsNFTJeulnI5Z0CeL9FW1CTUFbb6x4a0mWUwrARDxhB8ksCohUIp+b3p 3mNaY4A8IJasQ2G66TwictRnYEM3Wz6IFx7JPuWHj3d6q1xj+OltfeAeypGr3E7aJyGGf9V+V6Mp J/01jyfRo7VG2g14MdfMrE5wETSARTMVKjaxSZSBdDdPbgzGTtBMUZWLVSwWq1D12BaVLfs8wB/g tXldZAnSIb9R/0iK/bwdELe2GKvquj7nEPx4iE+qQJ7KSD1Ou/RUKWKplZkT6uuH+Yk6lNAKbKA5 z98FYi4Rm1M18lCWG5mfGc/Q2pDbCPuFXeXa93t1N/1/3d8KsbQSQEyHa7Sc2GPguT38hHpbKE10 +i4ptRcMSeebrsys+HAF3RliyGzJsj5Dju+lsqMudZTcw077DiV1ak20gTShb6KxkBmX4jQvflUE AJVyD55b/7qcak3wbTIh4IW1Gt/P3x+TLXKjV4rphf/sKz6BexBxAMfKJFU1mgHV7AhVUREN0oND qAzxhF1R0DTJSxQeO0YXiKyggqK98qWyYpfY/2df9J3o62tU7gnUPiVWDe1sC0r4M8XyePK+VeqS iCZlnxOca79TaITTBlaoYqxr/3iktxzJbavVw2p/4mH5Wb8y36O9+MmR0z4T+2e5yrl3pffJFuQW dH1A4ubpGHfrkiC5Qxbf+VRxuHGZ8HAA0KkqRbjZEoVs7NXJni8EjADBnN1Y3qJVCG32iAwggoar mrrc8BhfoZOo8GQ4wVEUzghpM9r6cEL2fnTcmLKQpQmbpir5s6vZBPVL2o3dLTisi9KzJBoM7tTE 1xSU3iwlHBVu4ZykxaZYEq7wCAM/Xjwld5PX3yLKa0yImawpquPFhnqLcXsMFKe9vZ1/n9ZmjRt8 ssW6N3QfYmbMhV4pzMllXDcr0CYEBSoOvpSobzZaxseR9DF9nb3YhCKijhMLoBPonWxXGMmz1m6v 5GdtOKr+eKIDbwF0lNUQbwHTB28vnN5RxHssNR8t442PtlbsdZENzDBwM4i4Y1+6uAdYT5XfYqEN Y/rSgzNCkCYmvGEUjV8BQapX9rJkBg1SsG5WyXlNL2GqmmrAmku/h3m0Fo0NfFQ50J8bQg40lM4K 2Jq8hFvKsq8gJdnGKPS8ovz03/a2C1iqGVQZVTo1A5DBhQP1Y3o7/GLc6mqowcLSdmE0noo8SVQ7 CzmcZcUMrhoFYw4/uXjM/dZr5EclAzJVTfaXnYQgsmEJHHdUh3HZXoAwC7ZHnDRSrxzPTexuxWmR lNbi4hmfOn/zhgom6ta3F2QRqjsYGrl70E9DXItPCAa4DyxVhyi+OrYTB79Mf9Q+2wiKAN/zJ0Qc lOdsBQwdsGbLmBmX9IaNe3tGX/C4Sx1unG05PyiWe1Kb8jCbkDEQN81um2kQcEmonURYNU5P6xLg BXwtJ5V6iJREIFIxty7E7TGK2fFeVoddsvZq86n/IB+FrWxZzgHao8neMCnVtOegTYpPyafPdkgQ XNgPsM97ogkDThHm6QbXt/CtS7cdRezNIzecMq2qTCFu1R8kYZlG0iQI+kKY11q0P4/Ho9HvCgiH o+vo1clL33jR7XmiDgRMhydyopbQe/9p3SBhHFSb6kukHgRYameMw0i5PawFOXG8JL0xgi/CFimp 46w3cA0Edp+xPC/0VQrx7scRtw0LAx93FKOJPCyATXQNC7z6YfFxbyzevGqVZC2Q7S9AEm5E5XeI IJfAY8PQCBt2VV2AZRQeKudGUcFnBKjUNMk8YakKo/F+WvQ5A0rP/410wjmzKugtEQUPhPNnwSWy VRjY23Botqft9D95UaoIIAX0RIgMddy4O/4b2NXBRqi+7NzyCyqrTA6MVYrjXi8Ukpl75q4DUdyr W9UtrfjVcQoMUKJLNrubGgS7X6ccOMpEJpGYHTDurn7UpgPUtYP2xxkEZEMe2tst4vr3yE4+vEdk A5vk41B4tKjhoxqDWxdDB3y8JaBUjRDywbTpLo1vcv6E4n4vtYRhrN6tjX21SlW22WW04n/Ip8PB fylt4JYvcL/sfFaN2855F6c5Y7enbCpBn8scNvYrYXaNawthLWtZOHJPqmqChfCgzqpGusSSq3+G qZEP5G1JFsMeVojWfOvUTg0xKXLM/lXaiO9aY+F1jPSnZ7WrqisAxNASk9JH9qmF6ENzofkmbeT9 zFOgB+ntPft9L96my0taSt01k+d+vNJI5r519n5rBEMFIbHXHBu/vmE8u8zdv3HOsU/060MCtd06 R7xg2DkbDsAgDKP7CzUPtS4qx0yphY6L13krJhh8+Ucjsr71bHpNPhyrGdBXoP4QgTZ+knazTgOV +2ulyD8Ku9jCBQjDRAaLgozBLoDB2AfjdWo2PvO6T54Ou8FtYymOeBBPJ4BQ5+wiLbgECuxS3q/+ OSFu3zYvEzA3rAJcsWPJF0h4mn9zGk5JDAx1obpvyPkN7vg6MBfYHtl65XFaHpOEh3aKpLYiwGIl oKitCKsYeKbmF54ca9rspB69Koms+EPDP5diaZnaFJau544lWu6MTann8kWtRsWr59TnIhx9RYNq eH07TItb7dY9EvKaoHQBU7JF10ZKf4D0n3lGTKbA9/IR+IrGbKYBsJ7ounZ31j1PHQKNA/YcRG0t BV/8hCgeJiMKRJKQlCy9wac4hMvazbxdvOWZxi/MiOTCOoRWMQKqFaQasFPHCmFYL1Oi9CXsZzik NXB004MmVbzqhwCkatd+z4jhUq0bKsdmpk0PA1YOyUJNXqnrbn8K2a+DAWZ20CHzWlq5c+bOrg9h YzG1HOvy1w2Hh5Q1w3f1VmGzsfjEcS7CtUO7dq1wZjjtbVUKl39khjdnN5f+2bYGU5i422YKBH0j m/HkVlfxDyi7QE9JwvwH0YLKze6b78jH1w2QOs4rIEk8ZpXtyAE2mg9vbCyfTifEe3Rveb0wOt8J vhp2M9o2inPLGCeMIJ9Mmrf1zI2cX1g4pJ42d9qhd8wJaxpp5tJhNfbjCcNYY39r8N8eSX+gnmFG KBvs7+vTtvHjmmYsNbLxWF5GvikZywaIGnUCOW5CzvVxfMLRJavWdYm1zFTE3liMdTm3swoVgQjA Uk8xq5f4Yy68624ABozM8yrbAD7ysnDTbHe/HgpSK137Y7bozZcMUYUnrUCuG+iwYqvsGEDLCW/C w0B1W5KHSbsAsu2ggKy02AV1HRVoMUy1KiLvtKeejdk9DrGN0oyjp4M/qikPQTFB9yiPEhi5TcbL 6Ri+11lEujsgp8hvA/Kv5Qvk2+YuieFFSyAKrZvpJv58xeVknQZUVG9KNGUktD/HMv71TsHVcF+C eJm1c+jPvbPeENhCsrOyhdGTv7eQTQ+2QtxKZzeFOPJ7S9eK3rqyPiXTQKHLvBgNYICwHSlPsLNj X0L3/l2vvgcNv8UTZsJCzH3beUlchB19d7NdJ0ZeKVGgV9SPA94pfMlHTztuqq/aDKF6WhOzAu2s lH/phn4FGYBj9veD4DgBid5CCGctYGbreQATM6Usx8mKVFhXQARhBZPOdZCx4+me5wgi/WtcmbYt A6AVTJX11exygkqZ18xXqun0UhLWyY46v1EGiRlwCPTjmmXex11/TXVmzN3ZtC1TBEo88x/x17Nc 5Pk93cFT5vwh7lN1tVTh4/QkZeT5WaSqIZ/4+mzse2lhR4Esi+06/GtmcJYplGqPuBCDOs7yox85 RDLihjF4LJIiSaLbi8g2lj7chvu8UdoqCwTWWyV9mgax8YK0p95I73qIbD81yXNRSiqvv4CRdqzd 3jaeQmeJMJ37oQgjaTCHp/XibaYR0CaAoBOPnMl5wHpD5xIVgU2Qdwz+ItcIPd+b8f+5nOhk4skL 8kePg+adTPFZ/thlboe3R581OmoCyOsb+zw6wbNcBO4cq0Nl1uLeLUITnAE5rQCsexCo6ZZIjJ5E x0N7MOWcCmTTmU7XVLh96D25Cidr43v/wogHXaSDs3Iq3nLcqEGuOl28JeVhO+HT/WARr+4AEl23 DIHPyuDhf54VxCj2aXy0VNcOe2UIdemmuykAKUYu1e737z5r1SlTgWYNQOnkOo1Uid53Dg5ghzD1 b6LA2qNrnq1+pH9WKyPLB+6JWrrWu+kopOcdxKX//KpWitbiWog0ZD4DwlWVL0SiSm6YspAxTSnD +lb3f0onOsU+ECERmc514f4e1A5afiCVEqRVTYhbhV9swc/hId9uEhSkswIs3CRStDYOigYxtned eK97JypOvR/d9xOdlML+QeEXu482Z5dACo+xaWIfvJ8SP7ITeejNGDgfPc5Fh+Y+cqoSWIjJvo/Y Kl0yIzxFNL7OPRpiXwvmO1qxI1vtkFE55XZc24YevpUNuybZV7o7yNykNOarkv0pK9R8FG+pI1yg 0oAzliWm61OV6CEPaD0PnM+TYsefjwGRB+sOS3POhHSZ1DfmKuUR3sI791vvxKFPFaOom77kutmJ a8hJL13Ba637ngk2Y9UXivNnYUIBvUJAj6ljuErHV8CzmVxD+RZoAN+jAD8mqYKr5FpTnsM0bnVr K21iz1uIyWVBIxJ8/rTSzQE5/TdSla5RYJVtkdpJOw4AQfX9f51UBkapE3trtmKRkxfWk4BZOmEY unjM+WlfYX4utxUtr5g90nlf8NEs755njPpIFyM5oSCw0zdqotunfgKa8myAq94KE3syEugm8vZE rP88dWX13jOq7Zitcaw20IAI61XIv9WHc3OMl2i6pFrl5DyPo/u1K9xaS5zlOEDWqdbAXV//+kAD IwUoQzyI49WU6jGMpy82G8hR8BOEVQhE5ZM/E/iX1eUxL6UBpVAXfscgsEreaJMKt0I73y0GyKWl STkxCOcM+szyn71a07Ot4+Y/7AYcQ1+DTBpqznFzaMpPdV4b+cmd0yJC3UQnSBxqEaFrSsudLX7V tagcDkehpZlgz4ZxxR7dM0GvYsstqtHEepKHrI2TsR1pmcZ8PxRsQCAQW7URcf1HJE/vz4z6JE/X canzcak7qihbZT8V2prZ66uvWiC7d1cjoXwuLac6aceYbUGsXOrlPl8Lm3ZuUp2ra7rSbtwiCi1E so1kjIQNaxSokcFePZ/5vOGVIp+cjggIMAmbH0JDH1yfdx2AtDGZ16ZvXokqUGFL6gPT5L7OHb4z doPGJIgzxwEe3Gh8ETcn6FjPxw4DgU7l/GQOmTPtyDLZRIs18RpTbspzrcSyz9V5oTV162M0cxcZ D/3DOvJtgx2gEKQ8C9q+DVnKhuYb36kJTQwbCU2+V2NuCWHX7/ds98CQ3MBNOGvBT9b+zkFr+hKh BcYh13Jj3aD3AsIomEJRdq0Cbz/C7jTJs9sEdFnmOEQQYT6s9HIYWgW6gKkqrAug96G935gWzTkK eefCS7e6zJQlybzPo3qt/HOXdDafgg+eXHg/AE4OzMNfEZ3EF6ejrtiNjU4nas12J+6NBA8DnuN9 zgFgqmuTAI8AsY7GH5yJRKtJhh9V8QHpQzUXhJiFiBOcBNBOoE1lIS/veX7ERp4LczB6z4f6M78T +d7mYOLQ+9hQm9nRL0TB2cHeoSGc7pjvB+UENrk0n4G4dGca6PMDNJqxCzbsPmbX3aQsFbqx87H8 Y/tdcLQ7O7FOh9R1K0RSCTCoExOqlTsSIyD29YaSTeUW3/GKUCtrDfKcxBAV46WILFnN1VMk65Ws wkC/SH5eRvM+dEPbBzuY/SeKMCAlkkNcMvukIaAJHNvqmXtbKnEQKFEyQkrKNtvtygBPlY6yEyBo 9uCmY7MoJR3uJjORT1y2BfhPXqTgDx46zniwjspO0Ox+yZ25SOjxO/ZH0RKatwMmVynlD6QIPeg2 ajg3ZE/bf68pYXDggyHzTezt2DnEcIUxBkO4ajtiUdnomQxNaVkvMR6SPrF+cM/TWUh2aGykKMWu nWyATzrdlktYmBUvldvW9oGAjWHF5FLAQBs2RpGronGG0TJVZbrE75t0FNm5OUOF1d1hd4TDkXpN ZrmBLGqZZ0qy7mlKfOV+flDEcQrWEVq6jGjvW9bL0TsG9lg2enSTE+UmZLIXdzzqf4OcF9p3DK53 4U43FZXqgpZUJGyfumdQtHzzlgyuCIFYwt44LXyFk6YCnGx0/jQtcJfJpBe2QxipFwh1ZHWr5H1c vDVqx9ZJ4edQkRDQl52am8qdqy+apJEVDpmqGmcys5vcGfz2rB6IjqQfHdyc1QiDdCKtLTOhKjPO PlLbHNkF7VUkiP8zY5+oUnibJ3YJH9RKB8BYWyjxKoXmFkjp9uHkEbedDLben8vFT6q6v/v7FSMX +SIdEvfQxSgeITaxkBjfMjWAXik/zDy9zihnRQ3Pwu022U6VmQy1vY5wB+ebhtFwMNcyXawZ9qBY SNihMMMT17r+lcbUGgLD6ZwyaRCe123eoy4XpaflKCSaUYRfONh+WQgQzwcqdKw2nRG31ptfr4hJ du95zQFNlHmOETCdtEVyiODswszjxJzibBHfDs/uLqToodgiQ8hb45SYHUy/XLbZ0vT/ShD/VNPk y1e5zkQ10mNQeF6oQVmE7QniAP3wAVYZWd+pNSFipu0diDsWMMMEjmm5cwWX9FHNiz/Pzj2rTIvP GY7SMVZYo5pQO4LwI0N/5D/MhCQS+ImmZJLRXqziHxf62VeLhPZz6uumylsOkh99yIPZc3YvqBjo JfNw9TqR0noKUUKfHTrdwdoVCFWaPfewmCfwpcwCGpXV/g/iVmf2mm5EGScsrYnbuxqigIfLKodX a8jRn6eLRaowz8WsbhjKBA7waARizMFiePTE/dRm1VuXSjobWeu3SrD6FtA/xgnzygSEmRWVHQUP 6TGChOeeUnVrYyeBtRCEaV1tzroqDmNIuQvc1jJ1xQLbDlVFQkw5vTES9AC9HDqsLeMKbPqn38rG EVOg/8q3yACMzZgxu+hAUqeHEw7iXJ62FJmjqi00X+vmG5L6NFwebHoAExI3bjqAT631BYIPRJca mF7KBINGy49ZwSllLsNyJnHkH6qWk4q7/1iK2HbG2pOPgueW7iYljjTIZJHrIXZXjld2WyyxdjmK duvww7YVW/SWTKWBp3ECCYyMDg0nDjUnS67ehxdinwnmNgWrSyz5sAXk4hXgfrPhi8xdQJQKH9ld 8HOI+TMA4iFFdnYbnCf/VZsz3D7f5sAVI/lWeKojBo6bkw10b1g+yFolzQ+S5SxYDV2rSQKHKlzF IGqRu+ssIhE8ZZcbwenSaCKI7x5o4GRHcz77gJ8GNjGebL5wrX7uBL8iYUE9PmyTTeJTwmh+L2gC rsfbT9OcEUi6uVMgJJkvCmuEMJeL+/czUvvV/BaqYMjYxgdYtSuJk/zxdrpkZ3VzntDlCvc2lH4b Z3ttdsJIRd0rkDWHVnnvjOFW0ZwvRUQZZ9oklAG9+LG9IuWyS20/bfqEXKLLBp9sDb3if9HRUeNS U5gzYrLFM+ZWGuFA8+zIjcOl8uyWGBVcJwvup3BsYXHdRi8a9iNq0zZKpBTG0DPTMrG0Mhrvy398 sZ/acV9Aqa0z7b0CrkGjIL/gjRxjDRWQQHB/MByjHdNEAugXkXi3KC9ul+MNfPhcz4d8mmJ6gTdw oD+nfllutfmuYdwH55/+YSSMzoI0ErfDqrMqqIo258oPKuvnlOs1J8oopC1NF80TYv0pV0QZSViV Yhhx/PLta1e/iWRxQDDhfw50j+cjGlbM22utJIYvKPUvWufd7O6wFrQHILzzb91QDMQWGA7oPZz8 lcVjiUmXftlEXIhlpbHbCBTUHtNzBAVyTxRzr6v2IRaZGG0puEWWN91ac6cpp9qEw+sODJmFw8e/ TskElUoXADqBGtdVTfCS7ubeW6FpTYwOVtC6aK7JrIEfv4BHU/UFPdfze0dJaiIpEc4ZqZc/A5up 16rM6LlznncoOCAuHX3m1k7ljf9YbQYStBaT6kRrIcLJIqVGy6Kf3Rzpyvfgv3ObiC8EHoLVmnU3 /nVKpkOuW5OovXK1tVgQTaq3b2LPl8U3WzTrFhRRxWyzHRLoTktPr0U/RhpwVl+RFPjk7XJFx2as fJ7YBgw9z7NRGvSIPLSsIOcNcXfUTdU+HEE47TeOzBtvmPlF5lTBroIDiyga8m93NPoRZ+p+o8T0 zIm+oBmrlvh/WYiicWoUMQW6Sl9swjmWjpAaPm3unaDO8rXE6gpzndoxBt5h03nS0ob0MiaBA0O8 bQhY2yoL4OgIN2UlipttQVOcqDQ/GLgDqQYY+2rlDwd3J1Ek+szwZYkFSLiOYCNX5fPoqsCyNFlk tlp09Qwr2784+XPwZBrMBPIf19i0JTXSKoFFSC2n6D50Y+Q1QON+lZoIsF7nWObvgzVJr+JPXC6I ROHTgqf2tTKxSaREAGZmzd+o/5lL2Hx4UlC16El2Ibr1u/hhTsZq9j5mShJb/w1o1MNgMrI+kOS2 SJhr/yZGvcKx1/rccClzO9TWW8/+Z2h52fBsADGaU4BcsiarE+hMMRdLSrQkH1F5dUXBey2aMR9z GPcKNDLXNTgOdpft5ZKYTJAxhgiBAhqAFwWvZRcK7kyCKap2g1O8UfWU7bnzk4nDRx89c5UYTQSi 6y7diyVq93Y320D35QcyhYKw4FlsCai6VH1jwpbd9OyvYlaDO7GBhOKCiHbsRIzH4UtrdvtRcBLP aDs/ABuIZzuAXV/XWuBiY/pTb6NWUTAuF4aBLGDLne5cj+hih8IQ4HlSjgYdN7O3lEUY3jDG0fk1 lJ441ZcYFuy9osOBc/+DGEepv+sYg0JmljOI1tjh8sRt6uuZ63iD4UJzT+8tEDvdQrTZTb3HGf9o qFoUCTEP0cvgmt9hulnKvs5ujxjw+o+BIQm/uU8wT/wP9V+P+CSxYhhKpVGYjzdU+Il6sRNvleUu NAOjdohJzuJC25wWxuR9QZfGpzA0j+WXmWfp0Thhx1sCjfxZI3vCXWgk4jbSIwIMn0rn7r0SGRRY SlXUQI8JJHDzjqjZ7owUyXm5jk/V+M81Hu2Effy4ZE3zF2+UEbm+1OqWVYLskpW5E3h43Tj+eR4x NbFdVJDiLaZoTdrflRaEJlv4nu9OP+cgvw7I8HYrko1gA7FaBa3+7vOGUTsVLg2mKSL0VNhN7f3L 6QqZaoVjqO6X8bMfgL9hvRYnH+rKcKyO1zk6UR7eLa5U2vIyM/uP7lX40jwJjgS25yjw4fbtyCvV CCOPrWu9Ne2Cb5ySLuOVqviR1JQAzFMWeY+Rig3ml8uIiPBtPN8+uXu8IuB/DMTO8ePss8xXaYhh n2I7xfcgyd3xzQgZfa4u04XZxUOWsWlsJV1t+R6WfqQuHt3Kt5kASXUDklVex5OGqHNe3NgcO1vr 448jKRaB4jeCL5unE3xMdauvEERPIh+inR34Ivqbi7TumG9eptgG0N9syRqk+0s5nglU18+XOnnE BneGg0/ONOUizTCqzA2u4chnfxaXxHAPDtYgvdDZenUpx+8/naXi0gRyHoe8rVAPXXkKDfKhPusQ 4cgHjK1RP37CMa3668ADtFRVYXOUPnQNK0lN26SztRQb3ScTcLpDsy6xUZH+FrOl65W0K7eR2vS3 4/WxZZENLhaWkQiiSo7TU1lHacdAhDpRUfwOpy1OuvATP1+JrmSg2np4JRODEKJdWMB/nyFJ2RtS d6FC6g4aAAm9m2s1dcwsDlgRYa7JOyiFXfz54ju61fqoavCvQcePaTVqekzfz7yo1OKXPDPrIvzT JQMoc1Lq4aXSeEL0m3bhA3rWbJD4lsFFhYlYqqZe2HHnrub8pMUOc9FKnOAYEl+nqUHve8TReV9d Q1ysxbPQarPcbheU6qRjyBvCsp2xWSIfiVZmAS2e/EsGzZKkBBi5xHo8yIWMaqPqvYHmJ/JIfA/I TLuQEwGsYAxP3ywfYMpwMA3p+mtDQiXZHF27VZPTz2cJNAeH1PbO/ib2tot2ctQJeW3IIezW+9mt oguAvDt3fLeD1/E0BQqG9mdxxP/NcxcrYQMoyR7u19Dfa/dYzdt+aIqe3CGmTBM+GdK+7BEyTZ/K GKDo4vGwZk2ZRIziOjjUZMPAdUrcs4bNFmvBPLUSRVQ3ffCxkWaHw/VWBIvyyXqi3AQG3HSzGgFv Mm7kwwO/+VEBVzFa6OcgbbxkFWjEyaFY99+D/K5wOM7LL4QaVn9DSy7apQLVK8SgBaeaUgUQ0Wh8 rZrcxRdajHV4Soe+o3nOoEGnDOhClitoWYgIMQi8t6GsJENDZ99BjEIziUwIxDIZ58SxK7W9W+z3 zexKUNjGYVYMnhLGMRM0cGjFKrrfN7SBRQSL1Gy2MNOelavDtWaNgA9fGVdGm9KoKu/u9jPoJIx/ 4CWzRAm5SwyQdRleoAKMjf/qSXhQkYGf0QVjyMk9i4/VOmbc0XKGUHLSY7j3fEWwphc6c6MHN0rY vlpaBoQa0//QOFJX6HDdp1OZ2e2Gwl20jVXWDfNB9rIcfmcYriftYQn/ZnB8+JOGwnpdgqJulsrB X16+CTvIXWrG/N/bTIVlP6lcWDxRpWCQbA6PHR9yduJUbyyERFIBVy+zrdhV/w5fgA6gIusfcRLj JMaKBPs5lELHtQ6AeO78FVQnFXfxehTPclthC8EiNKa9VRbhvea/EsDxRAoyEg0f/akQfvdVs8Gv +2Yb9fQkke9d5RtxbjWViP+100E+H61e6ns98GVRX4w7RVDkVDOchpI8hREhxEITOWVxsTm5/RLe jbfbO9yjHGA//wSPUvPRjoFplsaEngDdCWbhfwaGdEg4hbzOgGFmBz+o7MUFR1VkWxvf2f2N9tvT SN/5rKeDKovk59tx8TonyUq4sJAoPC+YVyFP9UHDi8wWr4jiQnT/v77O0WSk1t4FJvhyVkAjz799 wOwWYpEI+J07+GUrKCptO7Wlw6jDBX/+oP5z7AxLbuqA0+zHvaNjlstpxw58sJ1u654u9Mo1TGdv DLPy3xyhFqX/wZN/oSG87o3O08YR73IU0DOrKPJCTTKYwT5c/FphO2touQOE4hxVjNfh8wQoSQas dHC/BN9okQJTVOHnJSK8zl//D6fcOqCn6es0jvCzHgMeCklqlVWAusFzyrgmhmBXKKmYRQzOs0aP ds7PpKGDC1kz2nKC8iuhwGqywmRS0JqNy0KJT008szL2UvonGL6nShf0pShVpwQt9tg6YCDgG6wN FgXILjuDWq63M6+dVy0D7jXlmswWQqiBnfFIbVtoZFfR1MBdHu5zO6xSmEBpbgfeXLUE0xXk5YhX HDlj9SFb2kEa4vyx+mqepcglvj74N2rpbPKxTAyRyZ7ZH4JrClGhFhGAOHtR5AdjIq7o0MRUH3zl C/11sOtciSpCJY3OZC1lHDAK9ziae4JZFecL3iSWcmLAGF4Q3HyfRIRK6YnRflpKBCPdzqlM+dbW Ik3PFbB8lgMpSnP9GydyOpI3oQhhJTyjQWBlT7T1T91Pp5FO8gV0OzzBJ8KqgdygtqOFG9j8TTy6 dSAuYM9//QjYAclTiR6cvtkytxi+CZppMQAru9OfY4KFDydvA8/aIagdXsSf2Zf1YUOfPoxpo+bt ukwNR0E9Ip3ufoGM/3g0Mq34XJx4rUppfl+n7BEfZ+hFKsUu6RH9WVlljlM57Wx4VrCEUOxmI8cr 7NLlUZ2SnDR/yJlW2F2L09KOGdglj8MhJ83CmLPB737i/vc4EF5VrbjpHfa5l6JB2jkfBrIOZmgr S6RCJnsY+tUVSXa9dkuIuYN2/PHuAhNAAuX+DwhbEuq13dHF14ZxXD8qUJxgNdquVoNcsNgQ5QUQ YWUYReDD5Fj7TxM2aRHdZRKCNa5PAEwd8i5drAg7jwV+O6KNL/CJ3j6sl9Rn0s3QSsu1+rkNGcbi oNSa4zn+2QnKx5kyLC61eojWkjXYUSwjp6kXxoKo9SPzaToVnhs8RlstcDErLObznK5zb5yj8I41 g9Nc1+I/5CrGhLOpz1n2J47/i3ohpMugB8/52FtIF+x2DRmZ2cVn8slfVRLiqiTwvCBmaXMr2n1F OxnTeR2Qxi85yDhszx1lRO6KZxQy2AZYmXmxQ83py+0xy9tWCblBdxE2EPqX388FaTfsrZ8RCgn6 W698bYdqTfGeQOIMAtaKF1rfsVolxtfDAu2K2o8v2XKtnrJq3d7MBCs6VnH/82PzNTVYKQLtC2aS sPMA46WBLsAyIL4EMSfASDtX1xx8un+yg/bndvTov6+mwzB6XTklZjopYU5D81hVpPA5DgnRM+kD Om+BEp2WhzQnaQ20Z884jjon2u2MtneUfneLB6BgbVU+BNEtG4VsmJefJFrf8oRds80a/n0ANB4Q yCz7vzqXpXSwSZPqINfQeHRVZ3CTDCVFsYKvqrB0dXv3rUVBZOHQiF79F82vvheehNKlL1bipw+4 zv0BWsS+0DkB6AAxJ/8iTiZN7pd9kKfT4PsK9WkDK3ECwpYJtmjruZ93g4c0E5huhAhQqFfaYHIP WpGVvMq2r/EoTSKUd6m/4iNmuGr3bo03kZxbDpMLefuqxMJMYsmDTn/zDmI8F9oeHrSF8alOZJ/B JVJeW1hXXErmX/RCtutjuQDESUlIPRaL44WfdNsZiTDJf8wQB8QEjQC1lfQbpjZDoYk6epsHarNn S+G3g1ECiBwWWNyjt+rBGycV45TaIKE2nC/gv0a730QDidr+ltyWC8DAtpVD8aW9uyL4/ImP5HMD gIigDc4U7d7QHNLbWXpNrKOXGq7/hpiUv4jRmXwWbReWpE//DHjUY5Njr+cEAgfe5cQGy9cIR3IM 1jkY9lqK2Aht48gs29HClx/+3k44zt+bfe+FRe7sXR9Ac8wt1lxZBA8AZ8nAOUGQiJb5gNvBMTFD WHtaN4t9kMVfmmTt1heRcCubhmjTJgmO7lhWxbMQBjfs7tZZmdQMNYanE/5l51YcYh/E3k7Kx0pW oHmAJ93T7uytFFL3LqorUxUtqNbUkcfZaeRnqoOZ8cUHCixnginmg26PBESc4vu1KXmFulwZjbH0 q7QmBJ2kwXP2SuErVDbNL7hzEjXealOzBrhJUoxoR3B/PxyE227HLSV3U9f1gKyvTXkj8lj2sP+6 rxAWFwADsNxZ4CDV6ZX+bQiBbKvKcsK6N93ddWGjLo4D5NrKU1eOhQ7ESPqGw3kPF619LgHg13B9 E/FJpDQkFueeUsuEHRXgqFBMQIqZSpAW7I0ggdus43YUgiiByJnUT4Yd4+7L+EfMcgLuVsbZ/fGK M4dMjAU6C+58kYvyJdbAGNWT4hKrwvJGvAXJcflQi2NJw8fcC/Ol8tEC1l9mYn+/eweBUhn70Dmv ++HzAVCuVXmRC/3AxIF1MOOqKbf1eqSi34YTmpOyhnNoZAMc9S/WpqKUYwOct4NXhHGuGQx9nRCd s16V/dsQ2sEbf49xWKwgtdbEFAtzVz9vet52oWFf/RFtPmv8ZgcKdIMAG9jmRKqkTCcLEn0Hrbds dl1A/5d/STVShDYV0Torz2GakWj/qXqOPceY4qfyWREduLwWZkUFD2oxFXFCls5l+g4jVnpweSoR gl2N712FCju+gFEDCX+JmSzkJq7YhCXM2zRcFoTx2u77Rte6WIwn5RSm8shX9lWF6dwqi8KNKK+J +Onz1itVNAqaAmrDkPOG8i+CCfBcTJApqcm2966QnsXN+iV7X0ZBjzZg+nP/GPnpSHcjmF5Wwu2m CoPzyNhu4RF+VwGmA0u+AAC4GVFaWmiVetIpN83WDvZwxR/6spVKvgcUHcEv3Bl1sO75L1+dmpw4 YlrAToj7iHr9YvVKa9mrcIcApeKTzZKbqfqKJgQ5a1YfMZ+SgbaDgMOS8ojW9siXDTOjvkm8nYLe NDky8nVEnzxSCvNJqGRmYKq/IQWWZ+RxtoaeUJp1RcaGtvnmO9klWPAs8cj5eDh7ynZwgvdFjeDn OBlURgPuIBuokcw/kE4Qcy9C5kuTzP99t5lMjrVDHQwn5tcTQ6UAsdTxIFYUGzcSJnqo504jVGEA pCedxqjXhCuwUZnHVqY16qR9KGWPkLNwg5fNLqN59l67vJEtrKsBwzYLZeJueCHPA7HOIXlwAd8T +eNCChbRoDlwdFTPpvLOZZ5fkJXDZ+vkFxiFY6GIvcri99uYlZNR9G3JNwkupjVcEzVn1X1vU66I HUX7GIu0hCmr57x2scq3U48xdYQ4a4wJulVrxJ6IfjV2f+rTcdUxVAMqnAP39lXadahK629mVl/h IE+6vATQZGcl6dF1eQrI+RvxZZuYW4duCAiGd6UWBSH6SNLVCQ6cz8XW2rZUatHhvJQ1yDPbUtYO IpCOVh/vVh7eTGINf2J2GEVZwGKA1ELD3dYkYTHa3unN6exaghBXmg1YOVIYIt4+83kEPmVsrxE/ ClQzsYE+MWVHugZ2Fq3okta3ihjunY9NTyvlH7boIFMnUTz9+2vXxhFRDT1uThsmf5L5uC1plmGw 4jdZrB+BKtKwibYak88FY6gNhwDd9gpSLh/egzddpFvxMefAr9wwidYVY8T4q8cGfEKn23YjMFWj QeW5A/N1gGqK41a0xDuhgjMXACfw/NHAWXHwi5BIOTLFRtVNaGqP6F3HPFUhDLSX/s4sqMSjVyRv S6BXU71KfHh3YycDe/Eh6RTU7ZwshSZ+gaPSeEvy8dGZbRSxSK2ekWk+XC5dnpbxP+2KyNwSFj1Y xx/Ht6jNoYku83ReSFIPeOlK9JfeGjFqSUjllEVZew4pjpoKqLQcIJd1vAA0CAx6CAahasiisy3t uI+ZQFj0RiS/zzuD0yRWPGGULBHdoUJGwJ8fB8FQgymRUH8MGBGPUs63KOruGHvozV/ui5rCMDuv qGD0sNJfodjUVJzIJVspAafiTCaV3T8sAmAKHhlA/dZj/1RnwdMB5Y8uoC9aLhShpJAjKwSlAFck aFHxqTi+Ur2slY6+3NLNMctbhqamVDBTuAK2McBExEBcNoRi2pftppuPr9IVfXeeRq0tIa1KdCLZ PGgnb7NhqueTp/876SSOwgSHOTi5xdcYfrWrjGhX1q6NN35+6Rdp2NRz+EHiVZoDnMrlysNhQjg0 okB81i4plRNcbyJ+0pj7KTzYpvSA9k6bG97rxu80zF6C4CU5AaKkw1mtJbCJ5s8HAF33jSY/RNrt BvziVxdwGlcddE9Zene87IEc0Gb/sYbreHJHLFLVyKG70K5wcDV8mGu1FzXrheHCjU9kgfYXwG0U BNinMExl7vXXPAsGSXfEt+9YcZDsUjgC283F1xnnGwiQkd05k8Z6YBjiRa9OTzQi8HhOLGPE0/nq E5in9Qf8fFBPyaJzUi/EUGyNwsXe01+sWqk15VANGwRzDfRi4U0FV6O5kvqWb1QY/Jw21UgzMXF3 xMZDI/gBuAsncjp8+Oe70QVtiTk/rljhPUv0ElUEZOMvU3SfWUCs+gotbz5QcoAHYh72oo3DXWlP 41Tve7ZS1pYPShd+p4by83TNNmH/mal+Nq6U1vFaLeD4Zo3ScvXvdwWsumcams8tfocxgusAMx7y qva+SjLt2qAV8BwshNgYXvbPHSWS2+bceWrAcn2iv2vmtwMz5nPI+bFgiY9cK1NIvM2oIMkmkMm8 YAqzjpsjz8eoIuQwQZvohUY55Td7Rdxkw6wDR/ONi/1TPmpUtJVCwVKPU+gWpGdgamBXcuCuw65I lx+0arubOte8q6b2dNKhLpZm2/Sj1aKnvozMsqKQjCFWPIJfmSiLp722ruQp0iDMSk2oLfpEaomq JuS0MlZlsk93xn6HNnhRGhhRR4uvp0lKbyENe5iVXPeWa1pSdPzM9u66ZxtN/XCjJA+jcWBrtPPe HlXM1/FPARwVf0aXvNx6pRTgDIiFbR9CtmXfTYx+X5ZXcsCx9Z0js1I1jAlj3NcCGxylKF+kV1Dq 0HpVwCVOrWkt8G0ulQLX0mJAjvbGGItAT5mHfVSb8R59L6Zl3uNWDNvYkm17wUvo2vVcb3Su65Wm 6BX+DekcUYL515wkEUumjwv+uL0suG9wJV+WKJ0kZBaikSm60ohwPvz1Q3kScB8TvDI95kyJR2UN 53JrvWwvvGQc39vCAkVAngT5P0JNAP+k8pKwASotYxXrq0IfcEukFsyeNGVmpXPbD87ix+qwW2jR 3qZ2WqxeKekZceU+2noVabrIxmE1J55ysozWGEmqnAa/wLt59WU++mQFqR1pXT4UsZZqxPRHQVaF pnDgM4B2nhy5wxgDCYr1ZYFY2NFSCGERZeyTuoKPx/akCCdEwxGUINIfUYAelVO/YF7xupPqc0U1 pl3JX//yR1PZ4tvgE58614Nw/Vi+47nnyrt5vQgdR2gFMdpppEyzoIwNfdeS9J58sWG/qYwA/6Fx wFrc7TANPeXCvksSr0gVQVR9XFrbeAOPSO2h3PQz25vKT83rP+75L1pMgxSsIWs8cF0q310ch/4i OFwRhoWGlI+lnYe/y6Swy66J0er/ncxbFO5uBwpFsk+si4P4tFCRYRgEt2HXpOD6j8p7tZ79Nahe QUfZFIsK1GwJGzLEFV8MpfiddDReeQKl7euRMxPmI97526lIO/YXazopRg6aA0fS/D1lddtKNn9o Q3tg0/lS5uH3TU1JJSp8TyP6UE9VUVufDEcZPyYtH+V+MuwibzoTzqPSqJ53TwV3lLJ5t5titmTS T8nXhRw0ahW3mjzhSNezH5IeTHKyzn9NKiyJMwrxLEzaCfk5faTFbL2mY1Lj7KJnLJXgQ43yrehK DyCTVd+VhzNvFTUDuPMFpgj3vRXMmILwDGbNB0+XzO1eT9QyDSeLhHlUGTqIJEWHoYPehPhHfRwv taCPD0ob8loMyUE3Glxsg/DxlRqcJtARkovTkOPjaGFbqq6H9hPeIwMVhoNATE4VjUr/8/XSe7xl GzpzisL9Aek6x3hppjmuyIEw4o/uBGsIatLT846sHXsvSLMnYgojGvtzl/Fjfd5F11LnMYhjhfvb 0fILR5xVD/is6AUrG+piykeBoe4tzpGjcp4bPZ/C0d5huyYvqlz/FJSPtTcs3Z8GyfgeoHBoGh79 Y3rh0G/BfLkSYx9FowpmTVKxcDJh8Xytpo8AYbBYTjlDeeenD513UOqhIwl2AbuzhoAhOE9wV9K8 5EpuuMbChANCJlD/NpPWHL2/G3gjF6BWH908/PfB5laO+AhfitbC2/U3uj2TBvqdMa0nHt+IFqhz /vV8RuwOnu27IfGEVP0OpttfSmLxpys42Ucq6IJ7/hvVxIo8rBIxP6Gy3EftVpxY8lJ3a8plnB6M GhuTlvGgpBuKnUc7XOohIIAMWf4Sz/UU0hhEj53XuKiwGl4fBpO7Drwh2cVpJanHsauUMDgVgVkK qUi9p7JhhQfpKPtyP2iraikU/qyKs52G2qz0rIrzj7mZ5vBP9buey/39eBKDa7DvyHOMRchyK6qT U9Kt2zXCFreKbuOg9vhFHxa4PFC95wMsMXEwf+1/55CB96aED4a+n7Mj8nUVeGEezit24DTbjucl 65B1zKZ2+RswQwpoZunpyL7ydQIalOVSI5ilQzHR+EJPUqOJjBGkeHp4wSLtcLKXTIx0HJjBXJYR cOccS2cJc/+is4LRK59H474OmeoaXLarBzEuDuVXAsPXMco5Pobi3mmf6XDYJoFUKwoMBor8CrLp DrGxHO45ioUc82ac2cDaOgjnebT7bfKZ8ITV+ReyLxRSgtfhSmrtpbbZDU9EtvTa3QNWTwq+L1KA /Y6PQA9Qn+7dB4qBGR6jOUr3I5cu/y4HYkkT969h/cB5NBOWquctYa9DKj+QoVndORDjHexOHalB KvA5iBWXB2M+lq+RQoQvvAUKRSiAudwZw3e5QbdIE1i2Kz1ydX1VzH1/DT6KlUob7Ntyd5gNndXT njRlguYkkhn2QdQZz0oP9H1rMczpv05Qnjl8PePMReRV7OHrdclnoiCyCVQ/+rLyql8CppPWaCSl RCD8lswbq4KqNGp3dbSvwcoiP+lh1SM7UN4fepomPxL7R0w6Q9Mcbwj+TGCBCdSfR8bfux5ODFiS dUDqp7RRESdT++LxOmS9Bnswz7tej9PdkfLDsYBZ/PslaTsiMJ/6geJ60nrHav46bacpE2pL3e/U 160aCEGiU3eSEX4eqMi1vQvxwCF+IqujAxP33hKLxEiBHLHMyclQdpwuic8uSwdf/8fY94EhUPku Y5uI/frh7nDKMvOcjzrGihD00g0JOKdzB7SvQS/kWW2ChorO8WWqAblStbEpJ1WoecAvjb7VU4sI +lv/282FQL9KS1k+1OqfLOVe8M6x7S+Fo7FJskjM3QC1ydqTrz8Y9tK7vojzhkbf/4RpawZTW+o8 x0zi9yUquZQOiuT0UbkxQ3C9FzmFaho6dHuqN8AyVJU5QZgH8CVHAQFWHuDMPlgypyrBtd89grwP 9hCK+WC70m6iOO9hzneyRzbkHyeh7nTWlPaljaREPTZocLYUINxGoGfH1NsEz2ccrkIs5fQoPKt4 ljAUlKZVAAm5hIOlG0pkeRPY58hOLaLOFyM8hvYoKGtq+kf/N8dTg/ZJZ6WmDbOBX81ZMOGnSAK5 TBOeo5Y3eoVkd1BNGszt4pBMv3C4qRz/jmNLztJMLtQsnSnQZ3CHELNqhenWz792KDD1JEksavG0 sEyQWkLcDISyWfna/DMoh1v6UUJLEFxSj3WLu61pdB+f3d3WOX1qP4i1WaWDjqW6G6pG5gqGeMV5 WixURS7IQwOcH7WGYm/lg7pS8aK0U+E5cXXMBFl/EQeqvUvizJseNhFgspfKJz/4q38dRyMJGxKq qpJptW5+jBteeiWWt2os9Zmx23/Pz1Vg+5eGV71y6cDXb/Us2PwT++0xGi8qsYtX/yP33+5h8umL ljLlKB+M0XBYU3m7+duDCltj84w3Sdg3IIeYP0IxYQSyCpb1ungUBPPy3O0aYuA4VlnGRL9JFfId SKkSUrSK2ENs7jxEb7/tCYelnKNbFx6lD18L/n0iEaxPoID4m+DKPc2Pm2oy1mQARUqKft1zD3wr Bs2WMGcCxHoaIboy6suuoH++bVtjSpUayrN3Y6h863YhdV9XeBvSMP4vCeOdy4A6rpFdzvtOCsMA lSQo6YPKHWQCAH52wcgWyNQCweZgPzqO2xBAzCOozHEA/K1UWQNcPWQehBim6TxkMe+T9bx8OZv1 SdLSOzK4ogii7UZCfGOcpfbtBjkAg1Q4jKPdXvl0dbDLukI3qmDoJEoKtICfsVD64LRGS+s/of8h qKbaKHqVXGiUXfnrhJa6P0/UHFfQyK9u5mHt32K8A4/Q81qOyNKm849uR9VkM5+q2vuvWbS2qxK9 e5XNx2fQgqzDHYox5R7bdHp2mv/CACBMcGjBZ6yNk+dZXijVJvWpep0IJMfbCHT7XdYUiKsrFsDD Q6e33/+fY3CI/YwWsV/ZeoA0dyBEjh855bl5EGS7Xk49eeIFrlDZL2RWzkU+n1nE92wAeKA+dI9J Lkdwi+RfbYJAtJO+uFHvdkNOm5BlYWARnGs7SxZk6ibTfceNvzjtfdCWRasfQJMXOsW1L9jWTlXD SQOum8FO51cqui1KiaAnzzulORaYpjIA7+jPLsr46jhff/okgT06+BGt5WGfQ1Htg4K1XYqBwtdl ovyx9Iawy5vGfvCQhXgX2/0d7bWbVU7iCZKBhOEy7FMJjw2ojZLL3wzpiqZxzHQGMZSTjvFXsn/J ermO0zZD5C4yybIHGMB7/dGEbcc/pPd9ul1/YpFAt8ixHiFskOCHnFwNCe1HutxcHKAYPgJ7kA0D dHDUGEgEttr9SiqXA9uP1Fv/GnqJ9/fojM+DZzaG6mUTsl1Rgy8/RYW29P0SFs7hvitW+kCgg5mi VUuGB+i4WPdQ4eN3QGN2iINP4p66r7OWnshspOa7ZdYwmS/46pRw6L3r2wDgbNKWAHW632L05UeE dTjKjGuotUHDO/YAcr8+1/XK4HLZuCCGQQo+yp4kV2lZBss1kJVw5LIMkg428g2EnSa/rRX3MQ9x EgU3pQSZD2eMA6zgzLNRyb+lAPl3U/4Yz3bO+3blHV1I/CktFw1aRV4hHwCyiQYwpKg5klC5S86P k5QCl3CGxWtWaEoIkEpuJ7GbjYfdwUouLeKXpY3ot/MKqRaF3WMobStTwXorl6t8rjxH5CZfF2z5 kg4MxUBnbWCaXghgz+V+BdJoxgB7FImtpIj6WTRQ9lUdegJGR27Vm95CH3PbU9zxWTpYn9Bv/wWd SwM/DbfmzTv7DeddGt3p5LgYTfuxRRH3yLv6Y19nmGHmCRO687eOeZWy3Zpd6Mn7h6WJnwDIvlXn p0f7veFErSZRebT+8dCt4l53j0QHEFTb1B3LZ97ueesA1hrgs1FDZWPWm8YSP541yKkDmDkO5wRj 7geHsxw1HJBsro23qVKx9TTxqmDzKaLc+UvpkUwVo4XRXC03r7o5mZhkcEmDzzWarHou84mdvMme hwrm3SMgrhHneYn0GIWEyTIPzcpRW2jPxeye3pdMwn5oB73MuJLUOnbhUyOYDmM3viJXi2trGJSi AdnNbePIJF7wdwQVt1KHb3yI5L056tx6a1rXEd9x0EpLDH7AdJ0ghKHx5qO+4UcXdCV5iQHhZrVc oJemLYnGeIhafVFvouQgfRIQuinf7h3YA6Vw5dfxNep8bYNgmbofPpIpSmdXK8aDaSDGDzRm+T04 TF0n7//chKcGdlQB/yp1ZJxiqQpK81w9xPxb8r2tVLWZ8X39Ip1fpL+mSoc1ooft4lbglpTwk5zE mYwNpTh84JnhrvnOFnzWaPXk+XlToUP5tZ9Rfe3BN8nP1omCclY97Sye6ilRhBTyB8Vk9DgUh1Gs +6VYq9EwGt4pQ5TNGOExmrI0/Jf8yC3xv8z+VPjMdQvdP76OYQb58XarrMQq0gOcdbaWnwX8PF6+ 5e2E7ThvjkLexiuFaOO24CWc8uJQjEbCpEVhEN7UdB6912+o8jxrY27hKqQchsTQ6tobJQ/sJ9Nz sm5g+w48izeq5v/mkWZsC21If0sSzrhYu1Sy9ovlVJIB39ItxY6fkRsIeQFiStB/Qj0ZZ3RCqPup ouKupMFL6QwWsRnJgZp5z7C4eB9bhZ4Mw/38AQnEyPCNIzOFV7Q1546HFLIoRycfhDP8fpZKS6sw 0+oJaNNg3B4P2hOHSvNffznS2FqICdOpLyUm9Xl/xfJ3M1W6n66yq50x594hUUoMZtGuEUvYjQC0 /ZbqPaFEL6U2vsJAXlxw8mL1EtoaFJyq5fiGyZpWEBl+VSYgONMVj2D9tLm/kdj3i1X0WYTbYEL+ zb0mAuO9IpDBo3din0JmjiKp/6tmrm8qY4UynGZ0ytUadCLIrRgWFLinLgcpcpN0AMom39SG/v+E OVrqBvg3AfbO15xDSHDwC6BDmruyJEX9AaLJ9ZsD6bxgQEA0hhDYiZC43rNOyrcWeBJbcTUfzIeS ybEAHdMgau5ozwOURMv85lJXtguGDUISiG7qdoj9UXXQ57pigLVH42JBlJzHzDuqrF0JCYeGnYbX DZ7CjNYiB487WUCZVnKRdIchL10nauTVQ1PFeo1oHREG5ldymINv3u1dhYS6YnnUX13Qp9cM5r9o 39TyBX2VOgIaBQsf8cRYEIXS+H9go9GcBTXdnljs2vnCkch2V0sLjjqwiul73M2amiW+nAi91P3w 0tapcjgIZ+Y4UXbV0RFQJbSjAjcD1YRRc50w5BOiYS0JiDO7OHv8LKDe+1Idi3w++AMUnCTvkUsM vqVJ3GzeL5OrLrufw/Y4hrIpO5+j6z6O2stTQfVvQ4d6fvnXKRkhxzU1NFVfgBaKoaRbIO5ZrG1/ Tx1uNKYhgnRe9nPZ71OjRAAscEHsOkpNWS2HCVz9ZabIyL76EzO8BT/P4Zx4jqTGrfMXKUszEfPm ZEfiY4cwijeWlR8WwkGkWjEYQ8QBpfXeYS/lRrWo9sycZyLt5jurB7wCRQw0UaxbUJqUbLJBzF9R 4T7LYVrPnDTk3YEUfdhm00S4ulQpm7GhunoPxo7zYqty7W1ImacUmrKnf4bM3f/xPn5MK5tdiPPv cnEx6a90O9g9bvnGBeuk8aiBiagMn0odQBuD3NJ4I7JFbpuLSPc5otGViSaUusvw9phCjhr2EMp6 QjLm5X7EW+VClc7icfKe/B2siBwPMIH7RDZ6AxoyZnyaMMhT8+j9ezajaWAoQDv8CgN6UF20wZRh nBwZqsBFNtTAVhkrFP7WdwZ9jd5luE+oKA2RYQ/maog7ixGl5XmiSDzGpJDoUYtU0nui5+XglZzM r2pTLiyImjnV9y10PnFonHBBlhd/2n4ppcPiPGL1rU5ROcz0CZ4SBIMzZgz1xP8zPAOVl5C3BPiL drhWVEZQBnpguHE7kQIFTFvUfcnAHMg8vzoFPLvum6+8BUSKL8SQneeRyL7LXHGP0phNBsOsYaqR hfY5w+GdzFOztKw89duyAMsBmEE2qINHCRkYcAY1xBWZVHzRxjDofdSbBYCq3AFzlQy+HhcLMu37 9uiJIPhyncceACvOmZyuI/Xhh8Bu6fHDpkCsjeloDDsZPTlp5LzgrOmuAzNMTFCvvbNOQqzB+9+2 xjggGFzGTigG1JLfiSJqf5al1gLB1X0cXe5XlsWMOhP+ZX2CGYPYuc3eiClxF8vYrDgKeJ7MGMXH apfxSMRLpWXMyiZ5DIy9/vitRobbs5CyY0UVNfysUg+b4HPCk0nwq6yNQy/+9lOtsWjlhpuShfz9 YWvcfawgAL2yaEXLZxPFo94CQcd8NRJpFemkaw/QXrYUT3P7Vg5RHvN35BrQIEZTk3Xwjc5Iei8f Rbvsgjbcjl4sLVC/ANLt8A/Xc2xrp8p6yhYx3qMQDI1L9XLrqqxryz8e+TIxSUaKxjls2hswwEBo PEWnnxlVqVVXqKxzvtnir+dSXHylBbqPGQw5MftMeN0/Wpgqh8zWxxiXLbT9tYwfL1SKyyiXVLke c6Yr/GQE7NyVKOoMDmzdQMVcbmvWnDYjzemRBVY4o3CmSJC02C8sPAUEnSFpRRBn53gQTrRah+LM jkQvINuqu9VF3otlpqkI+UDD7n2vRtCCpDLN3qI2gNzBILj/0b7KFJKprWOTOv71V/yXZmU0pgDx 7QRbMW2ojdpFVAgkRMB3JvZZ/HrpVv/vQIx7KX7n5AUHOw1cfaYA+EZXaq9njRzITW80HN8dLmrH MZTaPY6yvQEiKB6e4ESMkPgO5VetAtkVgViHMlhCheI8W8+oA34KeCcWSJZ9S4cQVG50+/dlw1PX bUCSoCc7RBtizmbFelYIT2/YJ7JcaZf8ZdIh2Otgnx5A3vL1X5gfDQghk/9eWdjfIiMjEorTS0e/ Jfs0Zq3Sf/gLtaSVh7bD81JzXu5EBHYj92MdpWmE4sFIOPsE5qM/MLY1NGelZQMc+YjANy5pYJ8o knFYKnsn04CJtnIN6uRsnczq4zPz0YPpGH48/4HSJMycBJ3dNmLXaVs/kGhHSyqqoZkJEDv0qhRw 70MrhVuK2sXmZ7Y1eQkHbHk+LduBV4gFQ7CVVY9vrJAWVf1lAv2MKIW4VgsmtWE606UENbo7GR1e 1t2okRKWxrCuzzQte+2ju0xUGpCsu3/ADVpJkLiUeEBYoYSyI+9xUqxsPWAuUa+WRjfqGjxViTVQ S7uMzYvOlFVtprRR0iodiFux1R24pwpMG8FzoAKW+9vJOsjLiZWT/Bbu8saqnq3oBZG2Of8cglcn gahkkKIkkfjWAu+gs2CILt3iv7H7by9ZWB4Rf71hvEbXNp1JrWo30Ykf/ld8uz9ohgZ2FjFdDirS g90UEvkiZZLF/JBkUIXKmG+A2vwVLgxnA8XiH2mG/LtGrrNvggEeeNpqzB1rmhajDyDye9f1Gb7m SsNb5FwF3MGR0XiWvIw00MY0JPCtJylwXhZrmiSU0VYSVrx10BalokYiHO/BHralhVwy4m5zeBpU FAq1bQslQ2eeDqCDhUH4RjFnAk2XjHRugFApspq9HDJ4WgpFW44rpaHfmuZCGcAJKJ0P7n+MXJ/5 8tb7pEgwSPuPLqlWg/b+PXuWJjBNakZT/zKcsP3C2xqM/kIeghP+1cLgjFRfbOVx7lZsdJYHtgcn F062AYxXn+8MxqBXDXDcInPdO+DECfqA/K+8/KxAkmHSXPC5mv0bHTtU2OAg/unZ9fJIsFqs3A32 GEDTGzNIVeeT2P2IX6E+CrBD3GFQOQKglLCVqa2aha6jP4VJ2IWF0nC+mq9ETkmaw2azOZiHosRr wWtCsYgB3tL7/tJWUdxS58HfMlt2wqqNKh/HvUeeEcgSwGPL+66N7iwQkRp+uT4QQSUHQhzBw92D BlG4WMIOoK7w1+LCwYdnmMp83mr/PyKbNHoXMlgxKwuvmbItvBt1uKGUsbXwokc7r5DAs60rrKmI hsS4wF4OPdZBBOug7owWGBm7cFB4JPFy1jXBSOSUZMQS0i0/oNroSmkGC20/UtaeW75gxIgv05Ka 4f5CIhpxXeELXV6g6cAm0dsmXY1v4j7lrvj9P74JRVF1mKi01C63qQnFyG7Ye0qPdIe6RiPlCW+W GLoshdIAo4MCDQpC1dTbJjAm5X6y/h7Oq2Gjg2Lt6UWacEuS8wmQp2dnj2QAWU7hHXdpfVsDU/kV C5oK/eHqTVADlNzDU4MdTIIOjZy9k0OLpzOx2Rl/YS8uPjX6IBak3Q/sHrAdvm1KvfT/EhcbURMT YcZoAMl9K3aNtpwKRe3RnPSRh5Ps/brNyB6H2Mzmcn6DECWYfdqjsYOOyTbIr0wB3Z1eVwnpBs5Y C38GggQ4Zn0uUg3bouRJGGVxCb/ExlqRyRivA3ytZDX1477w8eThqPhBAZ+/8R1GHq+eA0oHPg4+ prYUTTe4UTZd5PMwKyLdbRAvjzQ23x/+LwsX1cgdHCV1ex538JL1swJUb0/wCeoFqZ8Xm02osI6E utlRMjND0864EKdgwac7MQPdDvOg+DHhG2M2+gdKz00wjpLx6oJwUFZ4mFNRxeGawLHH4Kj/EO5z rzA15bCcdp8497O0DU/Lw5Kgq2oWUdx/sdeW6lrpFXygMAvTXFD0VXure2EPfuMWNFCTIxWJETIN FpTArvDL1p7qudSwRGzhsvmwM6M6mz6XintBx553vuJWF2D4K+6SL+H1MaEjAIo0m4W8AnO/dJt4 dmNwt2VvTc5eIoPKPA2SpNVxaeHN7G1+WDAb9KLoVRWuNJNYANER77+d20IzrNvmz4qqoCatrvC0 m7RouNJvFy9WpJaauhQP6Vee3k8IRpJG8+RONwUHnnBXlZyz0B1Q8o9/ZMHvbxsjgDoim5VM0x1J I7iPQlmpvTXAP5nsKBLV4HOoClNhC8/TxpU9K4R/gWpBhi5kZUss7/lgcySjp+PEGBQnOpLPfUQK fQuDg50sxwVMvIq74nAnQNUlYxA2FR4xIFHvnl3yO6aM/DBRNjf47VvKuMv3XzNeyfN8XNkM+SMp lt95ZfBvG9io33OzrS0xkXUXO6RnKZBAGff8DZo/pD1rqPTZvah9Sjhry9c5O+XJmq6/x23qFQon /if+g99gK/P9A1l8ruTFruxLq5iIpZ4gmypK2YV39wDyW/oBcz9U1p3ipLjtr9ZTt/0RfZKRI76C ZsTZX2tSe+Zaborzu8XhJJNl33S45d71K52++1pMJA/Uk8rcGJub/n7sxh4WONXqQicwb71YL1gE CLT6MnyvX+XxlqAePvSpF+7l2oMrrExUbgE6bjnXcL0kHjUGbzZr8oHQQ5ERYBSRk++4M7qqrmtr INzf15j7173lG0DJGMZ8d+tMMk4RrtVn1XDfIE8x1gD9ox7onUqgGR47PK3b6GqO+9bhw4rBiPdV xe22lfu5t2k+WYM7Lt+zDh3QqnLTuiSPz/xpxjeWtbDz9hvNibgeGx2SJgOMs2n/ofKNzBll7cEN kjUzES7QvVWQJ5gAMPXjTMBXkMZxqY3kwD1ZY232V9S7VBXs5S31FBNy/RuRy0kgmKC5a3sKK2UM NIos0EAWZa3zpXXqiwa9G2LwrzHW3OIBsSSSQja0tJrJnaU5oV3Q2uVwVJckpCoU3jYK10jNnwYD YkS6GzRVIpRWHhMrkHEpJnIG/Bu4S3Bb4RW3kA9TsKbk2SSQybVO3KmzIbZ2KmkBmmFJcXt4aADD eBnKMaR8ZJ4XocKu4hvaNmf/Afg7aTFahF3jqXNKsjzMRttaSYCVEI1lmVs3abiRY2I/IKcmUIJc spxW364zWIBoecFOZC6+GTZQ6OjtDhjhMJG9nUqxfmKDk+Kl6ETrlF77oL1N/AMDAKL52zSDB8Mi PCp6K0z0CDJb3zXGRCnfOiBq4tDN5tJkbTwJULj7fsOa9L/JjQpRPRCfluIQ+jEGEXskg7K3/U2+ yhcgzv+l0GtmxfYpLLQZ4IqYhp3Zmg5NDkReoktP4+p4uF3dKlDmnZtU7k7/SAtCMsDRPX5BtYat OgzEpfq/c6wOOu7rp9n1wMO7trb4P2F4sjXWoILgCcNWe1YKjvFDs7ZKmwhu6acotYv9ExRRfgZD DOe/GQRzeBBzMM1urpCTJ5LHacrQcMuHm61QfuqMCi288ReL2JRDcUS2c5brFsHgckWExX+WGdNu 2AmDEoHV7LLaUBMM6KK34ZSnOm0dsr9A5L4z66c7YdWaN3LuDPOD4j/ik1nurDuLbnGeQdjIVRjn J508iMN1QwI1eq74npyDaApgTfUFtNOnlAkWkPruyr3PobelPZ4fiqugKk/IpfizKR8THT/zAAu2 Dn2SsJr3m2jvfcKC9uRe2qksw4RHKa1GyQK9HeXv+ktwVNK5LSL4f9h2bM/HgeFAjvwWn2YMGgEv npz9sp5YnXGo4L7NizWd0NIzkH3FP846JLlNWu0ot2O+Yijo1o2dfQji0lAprGJt3P+M+yg0pVhe 8z7Qtw+o387qwS0umzEM7PVfBRBnPENFBQbqpqzM+S/blfRzaYjelDwc+rwrOTgiEkkxoFtUBc4x 6lbDegjE0SsuTuCZGIrAYbmaqsYQOHNcTE/GfJk5o1CXLYgfwN9s+7gIrJ/pvNshtwD/oz5r5AMG t1+v+m5R26SacMg+tXEjk2qQbn0lQj6AKomSMzfCTfJChaUPp+mKeFrNSEPY8AgsZtpKC91P3LJe 8E8uAu9tyqDXb6Ir5iDWoL2QSqHCtrGizGN1JUTLMXddhUolsLvmVsSmiSObk3BA4iEHicrC5juo TD0SskassgYWRO+9rYeVh+ObDYaOnb2Gaz7/46LKe6oYb387fiAqTE3v9IzGwcPIvePfoFKbkD7m pC8vuEQhUjt+UZJ6byCPDceMfd/sYt6Ep5dOzIuPAf12rO/U43ybb56/wPkmLX+TBxJFXoletHV3 ENQgiAQm8TXnF8oCNJTDhHyIesMEVKuSs0or0Y9bRGsfAGOTSg+6WIDY96dYcpbqBac6Zz6kgebD 7ySJu/kk4swws5nWSOWthTCLYbz++bbP6SGJeMKCO6EEXWNt5TZ3ixcbJz42P/HfjMcZdDVnGonn Qtyj3/9B7jWjNr0G8aIWuys4N/kBNqv/ULypz+5a+SyakuFFWEoJI099OBK/nE/DVhste+nWP4mk u1cfvhL4K97eQeqrAJ840gcZ4rzCRFPtmreoe3tSV29jrOrtcgAuAt+zU0Bcx4PRnPxgoLJqfeUP lU3IJS/F6l8yvFWUAQGL5uWGE/5DTZlKOGEis7mF0REFy9P3kTbMv6uSMTcOJjooE7wGZKN6NZJj ZO/Gvauhn8fnnyqsWZd9RlHuX6MwkGd+UYF/IQ8022B9kPJtP/3DyIJcMD2wwaQJe3xXBL6XZUZb 9wfPM4NVnG5yTwV1ULnkRAVOugTxE2wjVwkdF5Mltwh4Cg61PYqxMcbI0sh1yMBskzUQzjQ/GISw CfGpLrkb+HY6vB7uHNvTE52JncUnblYs60PPgnARMS5Q7ZORhtWDDXhm/Go4fJ205xNkd8KbOByx 4e53wHXQIzpEj+X1JMuinQ1ejPStRJByTWe5yHQykBRkcov01WUUDs191oTxCSWXiaATR4Pfbzow 21kwk8JVXZONAaqxFQR+f4qmYdN6MsPNFpizy+gQe16KvXGGtXmw36wkUifeCDx7iOo2SBcFLziZ AcLkkZ3pDIM8Nvz8f08D6CxKzSwxyE/xX8N1xiQVs+/g9LayrN3lJI4P83OTRQikzcMl0Vjaf49P bnh9Ii/1APWs1v3ZwujMqiBDqre85ihFpC1ubXGfpqmSCOC//gb07NOPLjqI+a4F8BXzADHWnfar Plibb00tV4MulY/hmUCp2PlkeDicVYQA1X+a0dTDyMTPZHwF4VO98nvdwhk0WVhmdGdEeOrsoS+N YmpD0nJRZAaxtdCVaLGz45f79bWFUvDFhiIdyQQfy3e2wc8e9cIWSiW5xE/OQ3TfwF/MAP2qujoq zQZcmQYNSvxNfmxmeloxBydZdx4gN2Q81eAt+GF7bgNtCEqMUL5Ud+fYyhlvZlIcghv2P28SOGKf c4LQemJz2aL5demxvKWhnaOx+1BuSJiQ0wNbgKfP2qhVFHcJHbcB2U1laRDEHUH74EFpRhFbKnIy G09FDdQNvzXYxJilbmR0d+F/4GwKiCDI1XuVYnY0GXuPzPgpV8Q+omsqs/kI4wD+7xDGehGqzshf xRyg/oXwI8JkIoZpx6T0pYhNt3md/Q9aEV3x05/dScbDgpMPJVKtEIxsJ90a8WJp+IAQcJCGpHDi 9AhRzOYaASGCfprUgxtsr0mgnPaoOLDhUNyP418LmRUdfFv8l1xUWN3LO1upUKUx7OuqQMJXwleZ IoMha9G21h0zN19LkgSYQo0efE1OpIT4oDSMCVCq+Drsi+y6cPUiXVSjmmm8PS2bxdLVC5odcxVm gPAUEkiXDWxDPMDShH9U3FuxfVRfgkMJNy9FQJfmgfSO9iGFfbPWOw59NpIAahxRVlpIIuE7J1j+ Bci8JwNOuw5mo1YVDwlVXVuQZ+NoAV4I3nzs8fu59yMCSBdAWjRtWjqLCAq9oWRUHthvaeTF2p9f aSN+Pb+1zb01egZNAdNwyPdM44hQRpMz+0SuM0MM4VxbWrKzzTeCQnQBBja+EJ4AhEyy737JvnYS tVGitUmtM25dUNQ9sqh/dSsnrAxMPv4VEozm2A1af50tGGOBDt5KO3KBtqG5stzrhPfAJB6b0oZq o6x7lL9FNgvjcNI+bePZB69uHOtrmRpkngTUMybQTIaJ8UA1Cu8VcxcRu26yQtql4nJvKNeDB4q+ smtItJWJwzODcSj9PwVzsiQTeVAqzkyLsXE1NhMIMKuN6tnDDkw9w3Zv5ByTxodeJk3iVCz0GMlb le/J0qMKqFikwbpWVgt1Uyce93houvqIeiz0WEnKPsA0t1BXf+zzI7KTUeqgr5gUGjkidhAN5XAo yw05OCPpeQJiOw67iZ3QX0/awTHsktF0T4399jHfc+KkQhYMO6sWLNM8nDwzp2PKmzHNW2kXn3J/ 8ehMDEJM5PAGddM6gZMbNd255xzyhR6unBGLa7IPA5/BvfBsxACnEx9TR6Xlu+G7tUeATyDK9y8y uMNueD9qkXx0jqEssbg0a80UMDWU1P64vcNLX8qlH5qHV2cDjWbdl3Vf6IJAUNOCe3C3NYO3zCRn nW50AwlxO1MsRB6nPDAjBTTodbjIMr6TFZMhZQcyc6PmXKumJMzUipjlhW8rHRM5tTpsP4nSP7Qj oHiqr1+aX6GIVTanKXMoi9uxmegxh00itjwtaztnHCj5Q5GHK3//w3W2/jBidsJwXNr1dhlK1ihf 5xcdDIViCyUjVCOdHZ+rIwRYsTC8m6xLY99wlsGEyhnWiHJaBw+o6P/XqlPUefwK01014U+u3YKX QUQFW2s/la+6LJw9WEk6d8ZflX2iI2K8vcFrpKgj9D2N7W80xnUGJbw7v8xeeowOf14ZGUciKvWB eJi0ghvFk6KIuKTQIpIrssZmIAAJpPpf9tDnIv7DnZbSkM4kjM+6rR9A5Q3StIxdvpu3EY4GjLW/ DatX8umkDPlicrqNnawBg1+emJ0lkjt6ttB2DrS1rNF5DXHJGWv2kOQspy72X6FT3GLRpWzZFRdS 9CDfWve5Zap4EufZW4OhU5/7WgaF6YvrLYIHXLPk+j0L+QHDy20ak07pZB8MnbCj4fQpxzCVZi32 fceZ4frMqp9L5BnHl8R1drwG+/V3VYn9DPnFMurF0/VO//+DFRfs+dObkp1kxcLpwOs0RkI/j48A S88BJew6yHjLZC1u7Cv65qJ+0H0i21QTrBAats6Pn3Mbgbr0khREb9lO66Qonaskdmfv0vgfyKb1 nGLu9YavvANl2+biXTmUBLYwlah7pqQlz7tONg+KYdDRcRv7QwdEtCBNbxo8C2AEHhitoU1jeuKz yil3MKmaj3jlR++1X/cjFDTjj2lzgAbXRx9ZF9p/tiWepZUmLDeLq8yb23B2ZOHJ7ltTwIZzrjh/ WPDHedMTtj6ua0UMehtZOahUJDuXoTugUIlnLN4HastAO7EuFCkeh5XG/DNaKCGuGjC+ZTfYQcU6 hTAPHTmUat1CAM5Oq+4SqA8YMkfIYO3MtF9fvN1f0cvZsurysZxcC2Q0lTs8Fb0TF0WC5PWMhC47 X3N0w1KhCc/Nkw2UQvzqR9vgiOI00cHWpzL/RI9tQDPu+WOSJ5W8fKRS1PCiHnxhQYLxhmMlGd86 zGIO7oe2fE/V5/MTiBEjMCnjnwg/4okYx5Rbc9G4w28u8u7ijOJfZUAy+sUFoIVJkEZk/Kq/922a SbH4fIHoA6U/1hX6fY0nuBcc1w1zYfdFo7pQQXgo875S8vB2QQP4ggp7ayoFMT8Vq33idI1lTs/f hJu3ndBLZv5SiNJwXU41KW5Kv0HodCBobncGfHMbP3rjsORkMIw7K9jbfdGOMAiGcqBS71CuLvHZ hWcUwPILa7YOJnLQ3RePLZWyAcd+B6NbOGqhZtQ2l9Dt9bU0y53CmnCljxOpYgo+KqUFc+wTBCWT Ubp/Ue5eHxUQ0O8S82vU1FnJhGGvUazBjdyL2cKFiGflNMK65rAO0klE25fr9DiXMecbfTolVhDN yHW40jgRE6i3M2kVi+rIT/UTv6harMs83yt9pXAkIn8kqf4XqlVFokKuM6d1LL9uuFl6VSz4esSP WhdC/i0CA3EusWnZBwSme9f25CvnaMVeVI47GFlnZnNq71jzvFzyNV6chBJ16mqpkRONbVGNaWRG VYq7f7G3rS7myJmdYKxD0Q9LDkBD2hTXw476ACEaXJREl5uVxXj90OZIswI+upLM3mVTCmqRr2Bg 4bzVh5nuOvuZHh0RHpk6m3h1FYtUwYkMVjGPIoq4dVxJ8/VCZWg53BjVOhFAwMnaN3fVJjkarNqf XPlYFj5myhRrWS9KeRjXi/e1OmH3o22sCESkhaoOjosQJIzdfB4F+4ygbHlDr6fsplao1jOCMiiH soB8Zqy3qGX3pnoSCGFi7mFcdYXqo5biW+eHWdK10jkyKv/xj2N7P2O8giBVvLI0jmzRt0kEfA22 z4039QLKB25/JNvHAsHubb9ERLBAVL9MwXhquK/PeVwe1OBo5vFiIZ4uW+9a6UemrvfwlrEsfXJw Xr/XkqbM2uyXE51uPXHqdV5UgkSuIyrhMg8UF2ScWAwWUndaN4vFb5Sj+41eJ3+lE5JRY6oW7oIa rYUBXgAyR4YGEaIKUFZ8gU9N8hmuxGXOd5Zkt4ECAqBkmTysqFmXt+Wf/WNZXuRpxqHXZyTU99rz 7HJf01jkeEdufTjOp3zup+eloF7+r58yh6VrVfLCJChl/WxSHPg2ihu2VajNSwkO1JmdSA40LcWa CS1IWh5Q4ob7+jmRqfq9b1bGVnUmjdremFH8MjJJmmjjPd6uFTV28vMj8J1bRcMTsOpckVSqtj38 hKHoT914ao5DuKAywFyc1Txk+vhfE3uViZo2cnS+76UGJskr8Q9TrdprkA77Ydidf1JTHw82R7Tt zWaNPBAdbG7CuTASonUMXS3Uhats9E7XehmIaf7DHPX3sNPuHIDgXxs+iRmZETO2LFvWNC5N7ac3 +237AFfUN5TRwFP5iplpOaz6P/+Kh+qvJ9g+wqIGWMET/fcZGa8o57lmhnJqVxxose4UfeAKaOzE R6zxcQUMDZXxLrUt0mKALMw4xaacNzckRComPYd5JEcCKtktqaCIDoWNjYbWo0eDItcEk0Bg/u4M JZd7Ro4hF+Bpx8+vpZFIol6J7GjZM1cWXXhf8mt7jcI+7uqb1X78x9bZfDUHTdjKnSgKTH5iwKKI mDslDXH7WKAQ6gcbcAZH0rFEQgj5LVa5syIT53uo66S2Fpi7UxtxiioySwaGc+301uDG1yERkb/8 sXIcIs6S/Km0zjMHsBbKzKvoM8Nrxq1yC1wQTJ/oI4R5QVuDLiYptFQ/7xiY06iuJzIHW4nZPM/u 6txUB5ZMa/maW0lvwC18VzcJfpntk+2bq3N0BiY+BVMkU2ixiiSbYAPGEDcfuY9Bjkcj+GHNdzQM vBDF+Cw7KKeC8FtQict3XiBrhYcYOyo/tA1LGtC9e7AbWa3c1zFTR3I3DD7WSKxOPmYfZ+LTyVJu dENZYYv6P1m+tYliUt1d0Qp66Oiqao8CUDbD6ZszKgLtQ14T/Vxyes+Q7xSEoL6yiyTESmxuY6iq 5mPAwmYccgDAhiwrZPOAvdfXlFBNbw4HWYujdf+eUwxisRU6tptTqgub96QfFqDKGP0yDjsBaE2g Z66lPKP28WkHj5+FxHAEwAsmEdrAvUBe6HoE/aFiSjrTaqJS2fsLftQYyKaS/xHQlMCgAEwZKNBa gJjZtgdQyhSHA5sfohTD4IMs5P2wDZogE/7wi4v0UY7nNx0SW+5o05WG3UIme97CJRTMa+OCX/Ja B/Tt56fhGx/4yQhBfzUEBRbjNMPWq4WgL+MO2XNiporfJMaU8S74b9RdiKME8S4tX3UJvrN6+zup Wact2DP9vwkQDm5EJZBjPk+K84tbGXEDMLbwXYzb62uzL+A982lUmo8stwZFFkeVotv4SKs13W69 9d3wCuEmwR3J/c9+Fj3eAQXlmcD3MOTz0KG8No6r9otaKYV2rmOulQKaQzfJYhcBJgihC9jWGlwE naFdcCAcms53ZIY6reAAw1WhPlGSdYt9ftUwEcPj34dfqnddgSpE7hIuz5C1IjyjmVNNWx89DdZ4 MA0SNSirdte4W0JdnrQMZiNe+i3cocaTQbNnJt2Yqn9Mxzc+Myaw9jZ+dyYpIioBHDjzHJcVRrae BIH5W/kcL+l5WYInzfHFvo0yH8IL3n25Ss49TQxBNLf0+SdGDhRJZexUrK8Fap9WQv6KuQCCU/ZG kUWS5kNGp47vrZG19R8s1kl7AhGJqxftQf/pY+L900HZPOe8m/3tPWq0+be/0rg8fkxHDjjgnU/h 0JD5yefd2wcjGrpLziEi+E10yExlrtIq4HgNXbqWeH4DtRQBNYIHHhf+ZvkwFfVBmyu255B6ol+q ej5EBwR9yMwyvK/cquERQkgL8jfMRe2C8HTYU9Evr93yh33rPZtbmha3TllYIHEC2a+MF5zdgDAQ dLUyZNNxme6efqQT5fJQm/McFsPogHm0QpP5H0+RAZuWquNWS4aceqwd1OMG2faaUPX77DWQ7DXl HuTn2PD7Z+VP4FDIVI5b1WGawMEa3lrUXM7srytgVMpTCj9gRApM+cyXAWKvIWjeiI34CwlPaiRb WgVe9J8Rs3Vmg+Z4lLJvWx9ianblLEEAPLRCi1V89D6ZLDXJZNTSHF1l8wrV15z+K1+5u2Nz4oQn JmPeSFSCvfvn2XJ5CgpCXN9xciFwsXPIyYseNM3OYqVGAn84CnD/Haafw+MoX1nH6R0rSr9bpLzD /o2k07xfjtUYtjrrh5OSzRt/0FtwQg7mHjDrllfL1lUZD5bRGwuM9mdYVz+P7UP/clkHTigiCj5o PPrSHZyo8fN2O5z1vA2oXixPYZDAAOhlqNG8MwgAmLqlDFqm3tjFUKvyv5REsVLDW0u1qKca4pOB 9rOklFw+/pSp+2MmwKuqDDrYgkwKenSLMOJUYimnrC4BC6ZhDyG15/vEdXWbdE7shQonypmEigcf FRGdzoi7ZbIMe+O4UiAHoYUbWf+F6c0Ya81GbpG5lQ+eC31HPPn3acCpwZIptMiN/MUOiW3w8Gus 5sNH7/yre14xihFFkwMDh/BLKuupf/LsiGvBMbjMvjwE9dELdDtKc+1yfPjooA77RamgDvP2MelN /uJxFYW4MEwuck2rASo/RD782AeRZNN5ioKMzcLzcY/Chd+GwrJ54dC/krMbbyss9kSNSgZER5jj QhZss7K84ldKiviv79VT5DjH8C0h0+UaTtjM5yvo4IZO8MJdh82Lz+J6jmf1MMEY21hE9TODoI6T ZmnWVr236/gY/pvwwIvCPL1av/1FGt3fdBnzmJj93/oEqcvV5MfZiTpyUJSjTYn3qa7LwPVKf7z4 NcicSdlvpeTHMqnWWSTkZ1R/YjbWXU0WiMaEYFbj48U0EoT9fkp4aiQzkCxJsx+ma9MyEoHAFMXM OSWWUH0yr4SeCzW5oMgFFdu0/MIfmW8vX4eNWDcLRpJ9awK23ATk9p7P6yq+rAdviMO3zIBS5bm/ hX2LkApmV0qxFxaCFFJsatRZJhtw7JS8NAitFxWnTbMcKd9nBx3LMsRM97F+fCEz6Ez44bXE59yG OA7+TGBH2HSRTDp9BzFs624SVYB7T6i3JRsfLUQtb022lUAXf18+vC9GZo7pg6S15C/sfq1b2qCV sQagcJkDUjaH3rMGaCxODSbtr/uEIYdO46Tb6uRVbFX3pv9oneICqQI1cWRQhAA3TPU5rHUJJQWL b4eKRD3mJlGLs6JnOXmRDR6Y5uI1MPI0QG94KbIhfJDjtX4wK81C1qG5h4HIeR7HdH8lGoWGePKl Cc1mau1YahC/T8jhLpAkrlzFLYeq47NDdye1LECZ+bgQZivWf8LIV6wtdjJgk3og1tGQMCtrtS4J wOQEKwoMO4n8AqV4snOdNOcBKbAgnvV+zJlvuTK5oT28NBCA1mcFlHoTg64IOPHdfKHf5M5jvM9m lX11BnoPxmDyPZbH3BT9VqX6nZrRmDnf8rbhEJVXsxXpj18PvgMhawRYFXfaZ0h6y54E9Tgpmt4v 8H9KOrjaGuWyxJjMUvPtbvDKwUgwhH7nhHxhFUnc+jhHf4veHBnokVuXW4CpGd3HvDlr42+gBdi3 CNyA9j3jaArgqQtwZBG8yoFFWLJkY9A9s97DiXE4z+V42PAQFftdbNUn8awvhpAnidha/CpWYGhz XcNmjFxT+VmGLGX3bDhujLiEbLxZVTb96ImFzPd/d1/z5D2kigxXcAI2DCjzNgtJ0Z9LiAJN1lzA dJg+XCyb2nhreuHbEjLPsSB/2HPZqMzsLJbHviURZj3k9mOHFvH725w0BjsKxRdMc8Oqz8vqe+DF p/pMpEoZJKk3zy3NLfDE1TEJ+/DuZVUFS7QbjMyKNRCa4NIuB12QExH4RdO+Dm+/X2mytBWOe1dV 9B8O0ZPrLggl5LTXKDaVMbeRiVV7W7rQBjVSFHdDB0iDjCYltZopFsALjftZiCChDqsiBclayoIF cFkdb+y8d10wgO3OpJsmZdImiL921C40Mg4SFUOymbcn+1apYZToB31RulGAoIN9yuhyKcfe+Fj+ JbihoP681v59jvlskXg6imlQpNPPAB8ohpdOfvaFvLPWXFdh7zMIV5FP31hAqH/tQ8+NEj5yVR29 ap+/VbaFB3rwdlcUWo8fDYqu6AOl9oFQTjOhwEVMpI3T5Br2HTqURIl6h9ZVS/z8NQfKWfDSUFcy rBrQavNCyI1TI+nTcNfL/vfWAmSN0IagyxhXnMBTsxNhJg6r7bh/tshfJHxatv4aRoO4Wa1ayhu2 JVgepJyWfXJV4oApSV9tnNqOL0iwPSKRKuYbRMrVQ9Ia/5Ze5UcZ7ZEiZYIhX5jg+2F7TiOpxEMz Q1RGwd+ASr0dB0Lb8TyHZKfCr0iJ8oKbXrA/2Wpbl6T3rAHMEnSSIaMMXtfdCdD7p92ekJVrghJP WupEf16ABdPZgJDrhrZi5Urz8fyKWJODcj1SjcAdlYj3pIaVChpyMVbzXDxeFZMWoBSTSa1pKPp8 kBTiGPCfgkBuiP5/ME9Piwi4hajBwB3fGcdNgK3HNmlGfckzAneVOv524fI/z4Nz0tJlYCHOb4qn 9OBBYm+W59Ouxe8i1GCuadhROrEWzR/zIPkcpMREm75SfYUumFfCc8DvbptGcbfmOOIHY8aiNzmD 3BAMXlD46MjcXWqwT+2IPWFJ56bBaSLllT6OMt7hixFRC5ceunBQJAg5qSeT2aaDAmdKRK6vYc21 z//qKJpDa9vhhqXYG0ZFjxENfQPhYIVHcoeoWYQY8ZqNOPjSov+7vcPVfGQBzE5bSZvCbprStBx6 PwOjsDlPKhgpWklWEa4ThXXdioYsSj9rSaYSSz6NsEORAq1vblG3NNv2QAqLk4SFi6wUCtacjUXh BYDe0RPbDP8TzpQVoYZNMjAExNafE8Xq6ZV4/EjTzVC0ZZWAEmFXFIPimBmX0Xo3VUWIJVPEKc0F 4DoiR3QqQh5IwtMUZtKjVHS/i3Mru+YtQ89aXDBfo1WxhMs56QuVXyQUtOkHRMJVG7j5m+4aYdb4 Nj+9ph0taUF1erd2s0vDZYgDmrKOhPbuXC/GNRv64Aqc6CTkTtymOymfia4rOp8/IJm8sUlD9KKU rJRE/zFpoODOBcHE01I185hBhEm2gSQi++Sg2rpLnjehQ4Cd39eeQsKvZXuUyly1gw18TZ6YLVOA zPAgnSNgTFbLJZagVyO0F8qMASiEdzuJL4KepQP7/mH6NbFkMKvzaITNwnbQIOrB31C9eIF//cj8 o8VcfT0ell9LDCyvxR1lMfg8wTUrKiyvLGtAqxP4Zz3SqphBwW1J/kPNUmuMxiCbVZ4g1dt2pegL U3AQQuf4GYMiygfmg4SrWACuVSBVhSScF8GmrNezLvdnDk2yDXNPSjzPWf4IH0TsCRs9OVaHuUd0 F4ZCoS6+v8MwiAHFXKnM1SZp9wj32A3FUYhw09tjMn8fWUdG2tXULE7weCkdHVWkY5RaP5DUFnOz VMXtnT8VVlcscFPITa+v5iwz7O6gbzMKF3p2KXN6HEsN3QH3Y8Iw1hh6dfr11Xa+3ZaJBPXzbVlm mDIQHdlzpqaZ4y6s2onrjo8C9v6YuBH41Behc8GNENiFtk7mQSofCRYp3XIhWW+kQZvyBZwXeFBS XJw28SAAvtjZc+Z0YSNwkzn41AFsWT6Tmn7rmC83yHCf9sy9AKGtCXHbIoFJOkEH32G6B2gFBQKk 6LM6uaZRP6IE1oMZg7SWqmpxtj5lBTv2xab94pwZ2F8Uct8P6nOn7mQparb4k1kj1FBw5ztNU6uF FMlpAhSN6ZCVfI7JlADo5YIeDrr8pEmMs0aIjQMTFxfBxqeFCB/EVoSREYvyC4Q1/EU9orPmIQbB Q4nq7Utu5/deDUjcQ1moHngwZeSkYLETjJJp7r4gYFu8t9rYOPh1StoTTm6h4MnvyfWhlsb6hN4s 0JDHLmW89fT7sDp/h9JX0TgTkEf6J+pkB7TP5ilKAJKCd881NPXG1NmEFTXv2JjLwUksv1s63dQe P3MVVY6bL4R3fDSMst95HuGrw3BXQyXj0uwMnHbKR74f/xA2GLhxrt3XnJEo/8jNOBwVTXh05RCW AxJ9fbLNYE1rsQTvZ3B1ibXTiIpfI1WDV6N1B7qqktl8kD/QzozHJj8yyCh/Dc51DVQh1WGYamnV eiCMw/vFqXNylnlM7eeoQgK4z1x8K6c9PPz0BRCWyLgobG7KbrhfWgro/FlHhk6vm4XoYdThPRwB Q5jwJlN7D5QiWqNvoLDe5kXJl4HVVfL6jFrzXkoZxq8upwsaqStKX3KcW0oKaigkdwv+dthfyP9a ccI6KpfMDmcpCcDYU1/Nziy7j99D5TyeC7rBVN2VBO9clgEZk6fMTAqLD3vyk9Yst55R1EP0oOfm 5Sy02D+blsmwfcAyeFjGYTgoF+/rxaXbnmfQU1RRiV+Vr1w6uO7tmDC9VjwPqp05RBGdhwqqHjju 7a5K2ZxntzKlRcpiLiJyZb9vH+hkVQ/J2Gt7OS0ap88Dan9+OLEobN78/dJ/9U3pZcluC36HB0Q7 2B+Tql+om9UlqHnMYHHLCi6AM5+PzdRqcOihNX+kTpW1ETGScvVgBdrePr7HkI5wZCzRbTvQUnb+ Kr2QSCfSuJ1M7LMNPvlFrpGihDDmALzLTN+dOTZeOZjIR0uJBFwEUO26qnpm+pTv6mh44JpCmDNr Za+7607WQf8zUUIOk9Cel7ZHsxFvXG+ZW9vnRGT+Bn1ESSjHWnuz2HMnNIUVFbs8F5yqsw5YzVEM 96Ve3vcvxLVT/fozwEjoSGMw9jcah4GenIcVnY0HaoLRav87BNYvZQbApEsxfiAX5siZN2wntEOG MX5OexoeWlnbjjsqeaonDfKxKmXNERntojUN8pj3SMnBzNAlpc5B0HWShDJbIlmjlnnSz9CYjkKp ZqWLrYvh5kGSGAURbrse6FPkiPMlpT6EeeB+19dYDs//EH3cYDTPD0jQUULWPtv42+09/oI27Lgq IwHtS7hPb8KtN1Jt6eI1scKQR25T5Pess2wxwIfUQ73e6+w2Oe4fP+xorokYGcyF8GOVNneMKMg6 TmBn5WlrGiPz1pcfWx21ip+UnGajDjj2cpustk9JlaEvWYtDNfW+0JZJrm7L3Fuz4AtMOJ9uS5OD zcsMzCL4c0k/xBz86cMikuHxfCjM6AM9MUSO8ee/0daLRBAKv0lcQSyVA0S0utFLx3w/QAIJjOgL zZP0HtQG4w4tmWMKj8Dsr4qooDxVOq1AWauvRrhHilwHDDKKyHjMI7+tc9X5UocwKNNDF+l12G3e EpHyXcmFfKannIEjLArBA08ZVKDixlwcgTbdphNhEp/gtW5eqbvpZZejAwFjj6WedAxRqSgVWAIO cOWvYO9HHMnY7oCBjVAd+J96o5/Ouu8aCo032o62TmQdckDw7Bfgr/s0STygaPQ4jIBhb3KZMyP3 CLusSvUT/wkhdA4+RPeeo8ciCHOmGmOW0a156aHTVaqiRi9YHh3JGgvwLdxl08xp2HKkaHqYR+Fp umMRLSBux27U55tioA93XS6mllS/vnEhhdaGy74JdV7Ug4zo8+hxWp1gdogfOZom9D0tUe2T7Z6N jN6sjQ0sdkq246N0rdrZ7O03BTRzEaeaJ+ZGReuoXcPpfOLZElbCiexNhUGB61suabksLdg4t0kp Z1rIc1UH0lt8khsdlXh/iguVf7XYiwRJfjzwlsfuBHX3fw4arTDpBUoT2KVv3GpieMQI0EP+iKLG MfgXZVK2UVwaoEYHW0NXLZUUGs7qW7qn6cuTL1CLn69g64PwmNhlemQcmV5Lr1YS1PND3NkWO40Q M/jFwfS0EkByZgIGFBVonEfcEWs+ADVCtOLYliPkcWAj2Zr8DnLAamYEyfQQibsgU/vOkc3y8RiH +4a8oDA9gZiWqmtDBPudVjQ32c4SATc1YyWVXpkcL0E3DTtkoPQAqZf2eYfTzVcC86IwipmFj8zG DMJfIngJ+fAns9Upi8iDb6tnpGfP38g+66jEcvYGIhAmtsAAiv8WJ/AaUSqZjV/XoGSagnMHx1tO uWoWioEHFnzW6KVsXax70rnP/VNENmE9rqV3gM99Bz2o70p1WWVF0591n0Oyq6Ig4nK56IkSc2ht uNMQlU0sQoXMMNTEArUQhAamhkyNKeEfOptOzJTKWhhGSELHoee/f7gqK5rUWcALFOSXC06I5ra4 LwOwzvRAUrykQeP717B5aVGj/x6NyfUpAowppbpSmnoq9zai6LoeIcyKZMYpmUa9nHRVzhIccy4Y WvoWAGjAV/N2wX/Rv5WL4S2a05HQG3CHU0fTGuPQQYmXqNQiZVi9U1ywPR6WcnOLtcrkNvAmL/ss RcWfBrkj2gZjW3Meilm0jw0+o12PeAGNo1Ejq5Yy84o9wwFOzcyGC6gyOdLVSgzV447JKQJZAvVN /C8xgxIYPRxeq5XDTUALgVE9BDq1irMclrVCoATiCqZYdfpm6fk4NuGvSVvzJLLmUDUlVNjIyzfb LnHCQr+/Nv0+4WN4RAJoI3mTC1AOXKCG1ou+1wPWe8XeYXtLvVoxwpZIMZ259Ur2tDukuOl+8f7T EFcn2pMUHf3lvyUlkKOmLIhLvaaQ2ZKHU3NglMmk52+GUbpB/4U/bYNCITUfHQglpQHqZHFVM7rY H2AQ9tATyaauEOcRQGiZikKYf2NMP9KXeY9Vt4Gc4Zt3KC2ZUCZN64uj/fdRurEmUq8m4/xMK+4f nyD8mBbyyEqfxoi1Dw53o+pZWXq69OV6j7eFbr7m/E7r3pRMd9TIybHm72H4q3KWbSCYgpx17ORe pcwjCWyBuRBejNjK/x6UQ6Fa3T1fHazoGf7W4/JMR/sAMdJ6FAY51WHz8zBun9gXV69qfvJcRGjP Vhu1io2xOp0cgi3mD7cEof5DjguQPOaSWGVC9dzzRAWbVjxnffZj+QUKtGnxwBX4e2PCrLTpFUMI NazqXmCJt1XLoguOa+A1Qo1c/6PuzFXdtPVPim82qLUKbGjiqF3Mj1VFp1vjA4071HBkC9S/D7y6 VYEsBss= `protect end_protected

mit

lasalvavida/Zybo-Open-Source-Video-IP-Toolbox

video_ip/csi2_rx/csi2_rx.srcs/sources_1/imports/mipi-csi-rx/csi_rx_4_lane_link.vhd

1

5662

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; library UNISIM; use UNISIM.VComponents.all; --MIPI CSI-2 Rx 4 lane link layer --Copyright (C) 2016 David Shah --Licensed under the MIT License --This combines the clock and data PHYs; byte aligners and word aligner to --form the lower levels of the CSI Rx link layer entity csi_rx_4_lane_link is generic( fpga_series : string := "7SERIES"; dphy_term_en : boolean := true; d0_invert : boolean := false; d1_invert : boolean := false; d2_invert : boolean := false; d3_invert : boolean := false; d0_skew : natural := 0; d1_skew : natural := 0; d2_skew : natural := 0; d3_skew : natural := 0; generate_idelayctrl : boolean := false ); port( dphy_clk : in STD_LOGIC_VECTOR (1 downto 0); --clock lane (1 is P, 0 is N) dphy_d0 : in STD_LOGIC_VECTOR (1 downto 0); --data lanes (1 is P, 0 is N) dphy_d1 : in STD_LOGIC_VECTOR (1 downto 0); dphy_d2 : in STD_LOGIC_VECTOR (1 downto 0); dphy_d3 : in STD_LOGIC_VECTOR (1 downto 0); ref_clock : in STD_LOGIC; --reference clock for clock detection and IDELAYCTRLs (nominally ~200MHz) reset : in STD_LOGIC; --active high synchronous reset in enable : in STD_LOGIC; --active high enable out wait_for_sync : in STD_LOGIC; --sync wait signal from packet handler packet_done : in STD_LOGIC; --packet done signal from packet handler reset_out : out STD_LOGIC; --reset output based on clock detection word_clock : out STD_LOGIC; --divided word clock output word_data : out STD_LOGIC_VECTOR (31 downto 0); --aligned word data output word_valid : out STD_LOGIC --whether or not above data is synced and aligned ); end csi_rx_4_lane_link; architecture Behavioral of csi_rx_4_lane_link is signal ddr_bit_clock : std_logic; signal ddr_bit_clock_b : std_logic; signal word_clock_int : std_logic; signal serdes_reset : std_logic; signal deser_data : std_logic_vector(31 downto 0); signal deser_data_rev : std_logic_vector(31 downto 0); signal byte_align_data : std_logic_vector(31 downto 0); signal byte_valid : std_logic_vector(3 downto 0); signal word_align_data : std_logic_vector(31 downto 0); signal byte_packet_done : std_logic; begin clkphy : entity work.csi_rx_hs_clk_phy generic map( series => fpga_series, term_en => dphy_term_en) port map( dphy_clk => dphy_clk, reset => reset, ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int); clkdet : entity work.csi_rx_clock_det port map( ref_clock => ref_clock, ext_clock => word_clock_int, enable => enable, reset_in => reset, reset_out => serdes_reset); d0phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d0_invert, term_en => dphy_term_en, delay => d0_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d0, deser_out => deser_data(7 downto 0)); d1phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d1_invert, term_en => dphy_term_en, delay => d1_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d1, deser_out => deser_data(15 downto 8)); d2phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d2_invert, term_en => dphy_term_en, delay => d2_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d2, deser_out => deser_data(23 downto 16)); d3phy : entity work.csi_rx_hs_lane_phy generic map( series => fpga_series, invert => d3_invert, term_en => dphy_term_en, delay => d3_skew) port map ( ddr_bit_clock => ddr_bit_clock, ddr_bit_clock_b => ddr_bit_clock_b, byte_clock => word_clock_int, enable => enable, reset => serdes_reset, dphy_hs => dphy_d3, deser_out => deser_data(31 downto 24)); gen_bytealign : for i in 0 to 3 generate ba : entity work.csi_rx_byte_align port map ( clock => word_clock_int, reset => serdes_reset, enable => enable, deser_in => deser_data((8*i) + 7 downto 8 * i), wait_for_sync => wait_for_sync, packet_done => byte_packet_done, valid_data => byte_valid(i), data_out => byte_align_data((8*i) + 7 downto 8 * i)); end generate; wordalign : entity work.csi_rx_word_align port map ( word_clock => word_clock_int, reset => serdes_reset, enable => enable, packet_done => packet_done, wait_for_sync => wait_for_sync, packet_done_out => byte_packet_done, word_in => byte_align_data, valid_in => byte_valid, word_out => word_align_data, valid_out => word_valid); word_clock <= word_clock_int; word_data <= word_align_data; reset_out <= serdes_reset; gen_idctl : if generate_idelayctrl generate idctrl : entity work.csi_rx_idelayctrl_gen port map( ref_clock => ref_clock, reset => reset); end generate; end Behavioral;

mit

SoCdesign/inputboard

ZedBoard_Linux_Design/hw/xps_proj/pcores/axi_i2s_adi_v1_00_a/hdl/vhdl/axi_i2s_adi.vhd

3

18754

------------------------------------------------------------------------------ -- axi_i2s_adi.vhd - entity/architecture pair ------------------------------------------------------------------------------ -- IMPORTANT: -- DO NOT MODIFY THIS FILE EXCEPT IN THE DESIGNATED SECTIONS. -- -- SEARCH FOR --USER TO DETERMINE WHERE CHANGES ARE ALLOWED. -- -- TYPICALLY, THE ONLY ACCEPTABLE CHANGES INVOLVE ADDING NEW -- PORTS AND GENERICS THAT GET PASSED THROUGH TO THE INSTANTIATION -- OF THE USER_LOGIC ENTITY. ------------------------------------------------------------------------------ -- -- *************************************************************************** -- ** Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. ** -- ** ** -- ** Xilinx, Inc. ** -- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" ** -- ** AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND ** -- ** SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, ** -- ** OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, ** -- ** APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION ** -- ** THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, ** -- ** AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE ** -- ** FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY ** -- ** WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE ** -- ** IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR ** -- ** REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF ** -- ** INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ** -- ** FOR A PARTICULAR PURPOSE. ** -- ** ** -- *************************************************************************** -- ------------------------------------------------------------------------------ -- Filename: axi_i2s_adi.vhd -- Version: 1.00.a -- Description: Top level design, instantiates library components and user logic. -- Date: Thu Apr 26 17:49:16 2012 (by Create and Import Peripheral Wizard) -- VHDL Standard: VHDL'93 ------------------------------------------------------------------------------ -- Naming Conventions: -- active low signals: "*_n" -- clock signals: "clk", "clk_div#", "clk_#x" -- reset signals: "rst", "rst_n" -- generics: "C_*" -- user defined types: "*_TYPE" -- state machine next state: "*_ns" -- state machine current state: "*_cs" -- combinatorial signals: "*_com" -- pipelined or register delay signals: "*_d#" -- counter signals: "*cnt*" -- clock enable signals: "*_ce" -- internal version of output port: "*_i" -- device pins: "*_pin" -- ports: "- Names begin with Uppercase" -- processes: "*_PROCESS" -- component instantiations: "<ENTITY_>I_<#|FUNC>" ------------------------------------------------------------------------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; library proc_common_v3_00_a; use proc_common_v3_00_a.proc_common_pkg.all; use proc_common_v3_00_a.ipif_pkg.all; library axi_lite_ipif_v1_01_a; use axi_lite_ipif_v1_01_a.axi_lite_ipif; library axi_i2s_adi_v1_00_a; use axi_i2s_adi_v1_00_a.user_logic; Library UNISIM; use UNISIM.vcomponents.all; ------------------------------------------------------------------------------ -- Entity section ------------------------------------------------------------------------------ -- Definition of Generics: -- C_S_AXI_DATA_WIDTH -- -- C_S_AXI_ADDR_WIDTH -- -- C_S_AXI_MIN_SIZE -- -- C_USE_WSTRB -- -- C_DPHASE_TIMEOUT -- -- C_BASEADDR -- AXI4LITE slave: base address -- C_HIGHADDR -- AXI4LITE slave: high address -- C_FAMILY -- -- C_NUM_REG -- Number of software accessible registers -- C_NUM_MEM -- Number of address-ranges -- C_SLV_AWIDTH -- Slave interface address bus width -- C_SLV_DWIDTH -- Slave interface data bus width -- -- Definition of Ports: -- S_AXI_ACLK -- -- S_AXI_ARESETN -- -- S_AXI_AWADDR -- -- S_AXI_AWVALID -- -- S_AXI_WDATA -- -- S_AXI_WSTRB -- -- S_AXI_WVALID -- -- S_AXI_BREADY -- -- S_AXI_ARADDR -- -- S_AXI_ARVALID -- -- S_AXI_RREADY -- -- S_AXI_ARREADY -- -- S_AXI_RDATA -- -- S_AXI_RRESP -- -- S_AXI_RVALID -- -- S_AXI_WREADY -- -- S_AXI_BRESP -- -- S_AXI_BVALID -- -- S_AXI_AWREADY -- ------------------------------------------------------------------------------ entity axi_i2s_adi is generic ( -- ADD USER GENERICS BELOW THIS LINE --------------- C_DATA_WIDTH : integer := 24; C_MSB_POS : integer := 0; -- MSB Position in the LRCLK frame (0 - MSB first, 1 - LSB first) C_FRM_SYNC : integer := 0; -- Frame sync type (0 - 50% Duty Cycle, 1 - Pulse mode) C_LRCLK_POL : integer := 0; -- LRCLK Polarity (0 - Falling edge, 1 - Rising edge) C_BCLK_POL : integer := 0; -- BCLK Polarity (0 - Falling edge, 1 - Rising edge) -- ADD USER GENERICS ABOVE THIS LINE --------------- -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol parameters, do not add to or delete C_S_AXI_DATA_WIDTH : integer := 32; C_S_AXI_ADDR_WIDTH : integer := 32; C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF"; C_USE_WSTRB : integer := 0; C_DPHASE_TIMEOUT : integer := 8; C_BASEADDR : std_logic_vector := X"FFFFFFFF"; C_HIGHADDR : std_logic_vector := X"00000000"; C_FAMILY : string := "virtex6"; C_NUM_REG : integer := 1; C_NUM_MEM : integer := 1; C_SLV_AWIDTH : integer := 32; C_SLV_DWIDTH : integer := 32 -- DO NOT EDIT ABOVE THIS LINE --------------------- ); port ( -- ADD USER PORTS BELOW THIS LINE ------------------ BCLK_O : out std_logic; LRCLK_O : out std_logic; SDATA_I : in std_logic; SDATA_O : out std_logic; -- MEM_RD_O for debugging MEM_RD_O : out std_logic; -- ACLK : in std_logic; ARESETN : in std_logic; S_AXIS_TREADY : out std_logic; S_AXIS_TDATA : in std_logic_vector(31 downto 0); S_AXIS_TLAST : in std_logic; S_AXIS_TVALID : in std_logic; M_AXIS_ACLK : in std_logic; M_AXIS_TREADY : in std_logic; M_AXIS_TDATA : out std_logic_vector(31 downto 0); M_AXIS_TLAST : out std_logic; M_AXIS_TVALID : out std_logic; M_AXIS_TKEEP : out std_logic_vector(3 downto 0); -- DO NOT EDIT BELOW THIS LINE --------------------- -- Bus protocol ports, do not add to or delete S_AXI_ACLK : in std_logic; S_AXI_ARESETN : in std_logic; S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_AWVALID : in std_logic; S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0); S_AXI_WVALID : in std_logic; S_AXI_BREADY : in std_logic; S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); S_AXI_ARVALID : in std_logic; S_AXI_RREADY : in std_logic; S_AXI_ARREADY : out std_logic; S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0); S_AXI_RRESP : out std_logic_vector(1 downto 0); S_AXI_RVALID : out std_logic; S_AXI_WREADY : out std_logic; S_AXI_BRESP : out std_logic_vector(1 downto 0); S_AXI_BVALID : out std_logic; S_AXI_AWREADY : out std_logic -- DO NOT EDIT ABOVE THIS LINE --------------------- ); attribute MAX_FANOUT : string; attribute SIGIS : string; attribute SIGIS of ACLK : signal is "CLK"; attribute MAX_FANOUT of S_AXI_ACLK : signal is "10000"; attribute MAX_FANOUT of S_AXI_ARESETN : signal is "10000"; attribute SIGIS of S_AXI_ACLK : signal is "Clk"; attribute SIGIS of S_AXI_ARESETN : signal is "Rst"; end entity axi_i2s_adi; ------------------------------------------------------------------------------ -- Architecture section ------------------------------------------------------------------------------ architecture IMP of axi_i2s_adi is constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH; constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0'); constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR; constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR; constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE := ( ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address ); constant USER_SLV_NUM_REG : integer := 12; constant USER_NUM_REG : integer := USER_SLV_NUM_REG; constant TOTAL_IPIF_CE : integer := USER_NUM_REG; constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE := ( 0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space ); ------------------------------------------ -- Index for CS/CE ------------------------------------------ constant USER_SLV_CS_INDEX : integer := 0; constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX); constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX; ------------------------------------------ -- IP Interconnect (IPIC) signal declarations ------------------------------------------ signal ipif_Bus2IP_Clk : std_logic; signal ipif_Bus2IP_Resetn : std_logic; signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0); signal ipif_Bus2IP_RNW : std_logic; signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0); signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0); signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0); signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal ipif_IP2Bus_WrAck : std_logic; signal ipif_IP2Bus_RdAck : std_logic; signal ipif_IP2Bus_Error : std_logic; signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0); signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0); signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0); signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; -- bufg signal LRCLK_BUFG_I : std_logic; signal BCLK_BUFG_I : std_logic; begin ------------------------------------------ -- instantiate axi_lite_ipif ------------------------------------------ AXI_LITE_IPIF_I : entity axi_lite_ipif_v1_01_a.axi_lite_ipif generic map ( C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH, C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH, C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE, C_USE_WSTRB => C_USE_WSTRB, C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT, C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY, C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY, C_FAMILY => C_FAMILY ) port map ( S_AXI_ACLK => S_AXI_ACLK, S_AXI_ARESETN => S_AXI_ARESETN, S_AXI_AWADDR => S_AXI_AWADDR, S_AXI_AWVALID => S_AXI_AWVALID, S_AXI_WDATA => S_AXI_WDATA, S_AXI_WSTRB => S_AXI_WSTRB, S_AXI_WVALID => S_AXI_WVALID, S_AXI_BREADY => S_AXI_BREADY, S_AXI_ARADDR => S_AXI_ARADDR, S_AXI_ARVALID => S_AXI_ARVALID, S_AXI_RREADY => S_AXI_RREADY, S_AXI_ARREADY => S_AXI_ARREADY, S_AXI_RDATA => S_AXI_RDATA, S_AXI_RRESP => S_AXI_RRESP, S_AXI_RVALID => S_AXI_RVALID, S_AXI_WREADY => S_AXI_WREADY, S_AXI_BRESP => S_AXI_BRESP, S_AXI_BVALID => S_AXI_BVALID, S_AXI_AWREADY => S_AXI_AWREADY, Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Addr => ipif_Bus2IP_Addr, Bus2IP_RNW => ipif_Bus2IP_RNW, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_CS => ipif_Bus2IP_CS, Bus2IP_RdCE => ipif_Bus2IP_RdCE, Bus2IP_WrCE => ipif_Bus2IP_WrCE, Bus2IP_Data => ipif_Bus2IP_Data, IP2Bus_WrAck => ipif_IP2Bus_WrAck, IP2Bus_RdAck => ipif_IP2Bus_RdAck, IP2Bus_Error => ipif_IP2Bus_Error, IP2Bus_Data => ipif_IP2Bus_Data ); ------------------------------------------ -- instantiate User Logic ------------------------------------------ USER_LOGIC_I : entity axi_i2s_adi_v1_00_a.user_logic generic map ( C_MSB_POS => C_MSB_POS, C_FRM_SYNC => C_FRM_SYNC, C_LRCLK_POL => C_LRCLK_POL, C_BCLK_POL => C_BCLK_POL, -- MAP USER GENERICS ABOVE THIS LINE --------------- C_NUM_REG => USER_NUM_REG, C_SLV_DWIDTH => C_DATA_WIDTH ) port map ( -- MAP USER PORTS BELOW THIS LINE ------------------ BCLK_O => BCLK_BUFG_I, LRCLK_O => LRCLK_BUFG_I, SDATA_I => SDATA_I, SDATA_O => SDATA_O, -- debug only MEM_RD_O => MEM_RD_O, -- Bus2IP_Clk => ipif_Bus2IP_Clk, Bus2IP_Resetn => ipif_Bus2IP_Resetn, Bus2IP_Data => ipif_Bus2IP_Data, Bus2IP_BE => ipif_Bus2IP_BE, Bus2IP_RdCE => user_Bus2IP_RdCE, Bus2IP_WrCE => user_Bus2IP_WrCE, IP2Bus_Data => user_IP2Bus_Data, IP2Bus_RdAck => user_IP2Bus_RdAck, IP2Bus_WrAck => user_IP2Bus_WrAck, IP2Bus_Error => user_IP2Bus_Error, S_AXIS_ACLK => ACLK, S_AXIS_TREADY => S_AXIS_TREADY, S_AXIS_TDATA => S_AXIS_TDATA, S_AXIS_TLAST => S_AXIS_TLAST, S_AXIS_TVALID => S_AXIS_TVALID, M_AXIS_ACLK => M_AXIS_ACLK, M_AXIS_TREADY => M_AXIS_TREADY, M_AXIS_TDATA => M_AXIS_TDATA, M_AXIS_TLAST => M_AXIS_TLAST, M_AXIS_TVALID => M_AXIS_TVALID, M_AXIS_TKEEP => M_AXIS_TKEEP ); ----- bufg BUFG_inst_BCLK : BUFG port map ( O => LRCLK_O, -- 1-bit Clock buffer output I => LRCLK_BUFG_I -- 1-bit Clock buffer input ); BUFG_inst_LRCLK : BUFG port map ( O => BCLK_O, -- 1-bit Clock buffer output I => BCLK_BUFG_I -- 1-bit Clock buffer input ); ------------------------------------------ -- connect internal signals ------------------------------------------ ipif_IP2Bus_Data <= user_IP2Bus_Data; ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck; ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck; ipif_IP2Bus_Error <= user_IP2Bus_Error; user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0); user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0); end IMP;

mit

ObKo/USBCore

Test/usb_flasher_tb.vhdl

1

7582

-- -- USB Full-Speed/Hi-Speed Device Controller core - usb_flasher_tb.vhdl -- -- Copyright (c) 2015 Konstantin Oblaukhov -- -- Permission is hereby granted, free of charge, to any person obtaining a copy -- of this software and associated documentation files (the "Software"), to deal -- in the Software without restriction, including without limitation the rights -- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell -- copies of the Software, and to permit persons to whom the Software is -- furnished to do so, subject to the following conditions: -- -- The above copyright notice and this permission notice shall be included in -- all copies or substantial portions of the Software. -- -- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR -- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE -- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER -- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, -- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN -- THE SOFTWARE. -- library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_UNSIGNED.all; use IEEE.NUMERIC_STD.all; ENTITY usb_flasher_tb IS END usb_flasher_tb; architecture usb_flasher_tb of usb_flasher_tb is component usb_flasher port( clk : in std_logic; rst : in std_logic; ctl_xfer_endpoint : in std_logic_vector(3 downto 0); ctl_xfer_type : in std_logic_vector(7 downto 0); ctl_xfer_request : in std_logic_vector(7 downto 0); ctl_xfer_value : in std_logic_vector(15 downto 0); ctl_xfer_index : in std_logic_vector(15 downto 0); ctl_xfer_length : in std_logic_vector(15 downto 0); ctl_xfer_accept : out std_logic; ctl_xfer : in std_logic; ctl_xfer_done : out std_logic; ctl_xfer_data_out : in std_logic_vector(7 downto 0); ctl_xfer_data_out_valid : in std_logic; ctl_xfer_data_in : out std_logic_vector(7 downto 0); ctl_xfer_data_in_valid : out std_logic; ctl_xfer_data_in_last : out std_logic; ctl_xfer_data_in_ready : in std_logic; blk_xfer_endpoint : in std_logic_vector(3 downto 0); blk_in_xfer : in std_logic; blk_out_xfer : in std_logic; blk_xfer_in_has_data : out std_logic; blk_xfer_in_data : out std_logic_vector(7 downto 0); blk_xfer_in_data_valid : out std_logic; blk_xfer_in_data_ready : in std_logic; blk_xfer_in_data_last : out std_logic; blk_xfer_out_ready_read : out std_logic; blk_xfer_out_data : in std_logic_vector(7 downto 0); blk_xfer_out_data_valid : in std_logic; spi_cs : out std_logic; spi_sck : out std_logic; spi_mosi : out std_logic; spi_miso : in std_logic ); end component; --Inputs signal clk : std_logic := '0'; signal rst : std_logic := '0'; signal ctl_xfer_endpoint : std_logic_vector(3 downto 0) := (others => '0'); signal ctl_xfer_type : std_logic_vector(7 downto 0) := (others => '0'); signal ctl_xfer_request : std_logic_vector(7 downto 0) := (others => '0'); signal ctl_xfer_value : std_logic_vector(15 downto 0) := (others => '0'); signal ctl_xfer_index : std_logic_vector(15 downto 0) := (others => '0'); signal ctl_xfer_length : std_logic_vector(15 downto 0) := (others => '0'); signal ctl_xfer : std_logic := '0'; signal ctl_xfer_data_out : std_logic_vector(7 downto 0) := (others => '0'); signal ctl_xfer_data_out_valid : std_logic := '0'; signal ctl_xfer_data_in_ready : std_logic := '0'; signal blk_xfer_endpoint : std_logic_vector(3 downto 0) := (others => '0'); signal blk_in_xfer : std_logic := '0'; signal blk_out_xfer : std_logic := '0'; signal blk_xfer_in_data_ready : std_logic := '0'; signal blk_xfer_out_data : std_logic_vector(7 downto 0) := (others => '0'); signal blk_xfer_out_data_valid : std_logic := '0'; signal spi_miso : std_logic := '0'; --Outputs signal ctl_xfer_accept : std_logic; signal ctl_xfer_done : std_logic; signal ctl_xfer_data_in : std_logic_vector(7 downto 0); signal ctl_xfer_data_in_valid : std_logic; signal ctl_xfer_data_in_last : std_logic; signal blk_xfer_in_has_data : std_logic; signal blk_xfer_in_data : std_logic_vector(7 downto 0); signal blk_xfer_in_data_valid : std_logic; signal blk_xfer_in_data_last : std_logic; signal blk_xfer_out_ready_read : std_logic; signal spi_cs : std_logic; signal spi_sck : std_logic; signal spi_mosi : std_logic; constant clk_period : time := 10 ns; BEGIN FLASHER: usb_flasher port map ( clk => clk, rst => rst, ctl_xfer_endpoint => ctl_xfer_endpoint, ctl_xfer_type => ctl_xfer_type, ctl_xfer_request => ctl_xfer_request, ctl_xfer_value => ctl_xfer_value, ctl_xfer_index => ctl_xfer_index, ctl_xfer_length => ctl_xfer_length, ctl_xfer_accept => ctl_xfer_accept, ctl_xfer => ctl_xfer, ctl_xfer_done => ctl_xfer_done, ctl_xfer_data_out => ctl_xfer_data_out, ctl_xfer_data_out_valid => ctl_xfer_data_out_valid, ctl_xfer_data_in => ctl_xfer_data_in, ctl_xfer_data_in_valid => ctl_xfer_data_in_valid, ctl_xfer_data_in_last => ctl_xfer_data_in_last, ctl_xfer_data_in_ready => ctl_xfer_data_in_ready, blk_xfer_endpoint => blk_xfer_endpoint, blk_in_xfer => blk_in_xfer, blk_out_xfer => blk_out_xfer, blk_xfer_in_has_data => blk_xfer_in_has_data, blk_xfer_in_data => blk_xfer_in_data, blk_xfer_in_data_valid => blk_xfer_in_data_valid, blk_xfer_in_data_ready => blk_xfer_in_data_ready, blk_xfer_in_data_last => blk_xfer_in_data_last, blk_xfer_out_ready_read => blk_xfer_out_ready_read, blk_xfer_out_data => blk_xfer_out_data, blk_xfer_out_data_valid => blk_xfer_out_data_valid, spi_cs => spi_cs, spi_sck => spi_sck, spi_mosi => spi_mosi, spi_miso => spi_miso ); ctl_xfer_endpoint <= X"0"; ctl_xfer_type <= X"C0"; ctl_xfer_request <= X"04"; ctl_xfer_value <= X"0085"; ctl_xfer_index <= (others => '0'); ctl_xfer_length <= X"0001"; ctl_xfer_data_in_ready <= '0'; ctl_xfer_data_out <= X"A5"; CLK_GEN: process begin clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; STIM: process begin wait for 100 ns; rst <= '1'; wait for clk_period*10; rst <= '0'; wait for clk_period; -- blk_out_xfer <= '1'; -- blk_xfer_out_data_valid <= '1'; -- blk_xfer_out_data <= X"A5"; -- -- wait for clk_period; -- blk_xfer_out_data <= X"88"; -- -- wait for clk_period*255; -- blk_out_xfer <= '0'; -- blk_xfer_out_data_valid <= '0'; ctl_xfer <= '1'; ctl_xfer_data_out_valid <= '1'; wait for clk_period*100; ctl_xfer <= '0'; --blk_in_xfer <= '1'; --blk_xfer_in_data_ready <= '1'; --wait for clk_period*256; --blk_in_xfer <= '0'; --blk_xfer_in_data_ready <= '0'; wait; end process; end;

mit

ptracton/Picoblaze

Picoblaze/ROM_form_templates/ROM_form_JTAGLoader_3Mar11.vhd

1

96991

-- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- ROM_form.vhd Template for a KCPSM6 program memory. This template is primarily for use during code development including generic parameters for the convenient selection of device family, program memory size and the ability to include the JTAG Loader hardware for rapid software development. Kris Chaplin and Ken Chapman (Xilinx Ltd) 17th September 2010 - First Release 4th February 2011 - Correction to definition of 'we_b' in V6/1K/JTAG instance. 3rd March 2011 - Minor adjustments to comments only. This is a VHDL template file for the KCPSM6 assembler. This VHDL file is not valid as input directly into a synthesis or a simulation tool. The assembler will read this template and insert the information required to complete the definition of program ROM and write it out to a new '.vhd' file that is ready for synthesis and simulation. This template can be modified to define alternative memory definitions. However, you are responsible for ensuring the template is correct as the assembler does not perform any checking of the VHDL. The assembler identifies all text enclosed by {} characters, and replaces these character strings. All templates should include these {} character strings for the assembler to work correctly. The next line is used to determine where the template actually starts. {begin template} -- ------------------------------------------------------------------------------------------- -- Copyright © 2010-2011, Xilinx, Inc. -- This file contains confidential and proprietary information of Xilinx, Inc. and is -- protected under U.S. and international copyright and other intellectual property laws. ------------------------------------------------------------------------------------------- -- -- Disclaimer: -- This disclaimer is not a license and does not grant any rights to the materials -- distributed herewith. Except as otherwise provided in a valid license issued to -- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE -- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY -- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, -- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, -- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable -- (whether in contract or tort, including negligence, or under any other theory -- of liability) for any loss or damage of any kind or nature related to, arising -- under or in connection with these materials, including for any direct, or any -- indirect, special, incidental, or consequential loss or damage (including loss -- of data, profits, goodwill, or any type of loss or damage suffered as a result -- of any action brought by a third party) even if such damage or loss was -- reasonably foreseeable or Xilinx had been advised of the possibility of the same. -- -- CRITICAL APPLICATIONS -- Xilinx products are not designed or intended to be fail-safe, or for use in any -- application requiring fail-safe performance, such as life-support or safety -- devices or systems, Class III medical devices, nuclear facilities, applications -- related to the deployment of airbags, or any other applications that could lead -- to death, personal injury, or severe property or environmental damage -- (individually and collectively, "Critical Applications"). Customer assumes the -- sole risk and liability of any use of Xilinx products in Critical Applications, -- subject only to applicable laws and regulations governing limitations on product -- liability. -- -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES. -- ------------------------------------------------------------------------------------------- -- -- -- Definition of a program memory for KCPSM6 including generic parameters for the -- convenient selection of device family, program memory size and the ability to include -- the JTAG Loader hardware for rapid software development. -- -- This file is primarily for use during code development and it is recommended that the -- appropriate simplified program memory definition be used in a final production design. -- -- Generic Values Comments -- Parameter Supported -- -- C_FAMILY "S6" or "V6" Specify Spartan-6 or Virtex-6 device -- C_RAM_SIZE_KWORDS 1, 2 or 4 Size of program memory in K-instructions -- '4' is only supported with 'V6'. -- C_JTAG_LOADER_ENABLE 0 or 1 Set to '1' to include JTAG Loader -- -- Notes -- -- If your design contains MULTIPLE KCPSM6 instances then only one should have the -- JTAG Loader enabled at a time (i.e. make sure that C_JTAG_LOADER_ENABLE is only set to -- '1' on one instance of the program memory). Advanced users may be interested to know -- that it is possible to connect JTAG Loader to multiple memories and then to use the -- JTAG Loader utility to specify which memory contents are to be modified. However, -- this scheme does require some effort to set up and the additional connectivity of the -- multiple BRAMs can impact the placement, routing and performance of the complete -- design. Please contact the author at Xilinx for more detailed information. -- -- Regardless of the size of program memory specified by C_RAM_SIZE_KWORDS, the complete -- 12-bit address bus is connected to KCPSM6. This enables the generic to be modified -- without requiring changes to the fundamental hardware definition. However, when the -- program memory is 1K then only the lower 10-bits of the address are actually used and -- the valid address range is 000 to 3FF hex. Likewise, for a 2K program only the lower -- 11-bits of the address are actually used and the valid address range is 000 to 7FF hex. -- -- Programs are stored in Block Memory (BRAM) and the number of BRAM used depends on the -- size of the program and the device family. -- -- In a Spartan-6 device a BRAM is capable of holding 1K instructions. Hence a 2K program -- will require 2 BRAMs to be used. Whilst it is possible to implement a 4K program in a -- Spartan-6 device this is a less natural fit within the architecture and either requires -- 4 BRAMs and a small amount of logic resulting in a lower performance or 5 BRAMs when -- performance is a critical factor. Due to these additional considerations this file -- does not support the selection of 4K when using Spartan-6. It is also possible to -- divide a BRAM into 2 smaller memories and therefore support a program up to only 512 -- instructions. If one of these special cases is required then please contact the authors -- at Xilinx to discuss and request a specific 'ROM_form' template that will meet your -- requirements. -- -- In a Virtex-6 device a BRAM is capable of holding 2K instructions so obviously a 2K -- program requires only a single BRAM. Each BRAM can also be divided into 2 smaller -- memories supporting programs of 1K in half of a 36k-bit BRAM (generally reported -- as being an 18k-bit BRAM). For a program of 4K instructions 2 BRAMs are required. -- -- -- Program defined by '{psmname}.psm'. -- -- Generated by KCPSM6 Assembler: {timestamp}. -- -- Assembler used ROM_form template: 3rd March 2011 -- -- Standard IEEE libraries -- -- package jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer; end jtag_loader_pkg; -- package body jtag_loader_pkg is function addr_width_calc (size_in_k: integer) return integer is begin if (size_in_k = 1) then return 10; elsif (size_in_k = 2) then return 11; elsif (size_in_k = 4) then return 12; else report "Invalid BlockRAM size. Please set to 1, 2 or 4 K words." severity FAILURE; end if; return 0; end function addr_width_calc; end package body; -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use work.jtag_loader_pkg.ALL; -- -- The Unisim Library is used to define Xilinx primitives. It is also used during -- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd -- library unisim; use unisim.vcomponents.all; -- -- entity {name} is generic( C_FAMILY : string := "S6"; C_RAM_SIZE_KWORDS : integer := 1; C_JTAG_LOADER_ENABLE : integer := 0); Port ( address : in std_logic_vector(11 downto 0); instruction : out std_logic_vector(17 downto 0); enable : in std_logic; rdl : out std_logic; clk : in std_logic); end {name}; -- architecture low_level_definition of {name} is -- signal address_a : std_logic_vector(15 downto 0); signal data_in_a : std_logic_vector(35 downto 0); signal data_out_a : std_logic_vector(35 downto 0); signal data_out_a_l : std_logic_vector(35 downto 0); signal data_out_a_h : std_logic_vector(35 downto 0); signal address_b : std_logic_vector(15 downto 0); signal data_in_b : std_logic_vector(35 downto 0); signal data_in_b_l : std_logic_vector(35 downto 0); signal data_out_b : std_logic_vector(35 downto 0); signal data_out_b_l : std_logic_vector(35 downto 0); signal data_in_b_h : std_logic_vector(35 downto 0); signal data_out_b_h : std_logic_vector(35 downto 0); signal enable_b : std_logic; signal clk_b : std_logic; signal we_b : std_logic_vector(7 downto 0); -- signal jtag_addr : std_logic_vector(11 downto 0); signal jtag_we : std_logic; signal jtag_clk : std_logic; signal jtag_din : std_logic_vector(17 downto 0); signal jtag_dout : std_logic_vector(17 downto 0); signal jtag_dout_1 : std_logic_vector(17 downto 0); signal jtag_en : std_logic_vector(0 downto 0); -- signal picoblaze_reset : std_logic_vector(0 downto 0); signal rdl_bus : std_logic_vector(0 downto 0); -- constant BRAM_ADDRESS_WIDTH : integer := addr_width_calc(C_RAM_SIZE_KWORDS); -- -- component jtag_loader_6 generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_din : out STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_addr : out STD_LOGIC_VECTOR(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); jtag_clk : out std_logic; jtag_we : out std_logic; jtag_dout_0 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in STD_LOGIC_VECTOR(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end component; -- begin -- -- ram_1k_generate : if (C_RAM_SIZE_KWORDS = 1) generate s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "0000000000000000000000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB16BWER generic map ( DATA_WIDTH_A => 18, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 18, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a(31 downto 0), DOPA => data_out_a(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b(31 downto 0), DOPB => data_out_b(35 downto 32), DIB => data_in_b(31 downto 0), DIPB => data_in_b(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a(13 downto 0) <= address(9 downto 0) & "0000"; instruction <= data_out_a(17 downto 0); data_in_a(17 downto 0) <= "0000000000000000" & address(11 downto 10); jtag_dout <= data_out_b(17 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b(17 downto 0) <= data_out_b(17 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b(17 downto 0) <= jtag_din(17 downto 0); address_b(13 downto 0) <= jtag_addr(9 downto 0) & "0000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB18E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => "000000000000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}") port map( ADDRARDADDR => address_a(13 downto 0), ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(15 downto 0), DOPADOP => data_out_a(17 downto 16), DIADI => data_in_a(15 downto 0), DIPADIP => data_in_a(17 downto 16), WEA => "00", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b(13 downto 0), ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(15 downto 0), DOPBDOP => data_out_b(17 downto 16), DIBDI => data_in_b(15 downto 0), DIPBDIP => data_in_b(17 downto 16), WEBWE => we_b(3 downto 0), REGCEB => '0', RSTRAMB => '0', RSTREGB => '0'); -- end generate v6; -- end generate ram_1k_generate; -- -- -- ram_2k_generate : if (C_RAM_SIZE_KWORDS = 2) generate -- -- s6: if (C_FAMILY = "S6") generate -- address_a(13 downto 0) <= address(10 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b(13 downto 0) <= "00000000000000"; we_b(3 downto 0) <= "0000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b(13 downto 0) <= jtag_addr(10 downto 0) & "000"; we_b(3 downto 0) <= jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{[8:0]_INIT_00}", INIT_01 => X"{[8:0]_INIT_01}", INIT_02 => X"{[8:0]_INIT_02}", INIT_03 => X"{[8:0]_INIT_03}", INIT_04 => X"{[8:0]_INIT_04}", INIT_05 => X"{[8:0]_INIT_05}", INIT_06 => X"{[8:0]_INIT_06}", INIT_07 => X"{[8:0]_INIT_07}", INIT_08 => X"{[8:0]_INIT_08}", INIT_09 => X"{[8:0]_INIT_09}", INIT_0A => X"{[8:0]_INIT_0A}", INIT_0B => X"{[8:0]_INIT_0B}", INIT_0C => X"{[8:0]_INIT_0C}", INIT_0D => X"{[8:0]_INIT_0D}", INIT_0E => X"{[8:0]_INIT_0E}", INIT_0F => X"{[8:0]_INIT_0F}", INIT_10 => X"{[8:0]_INIT_10}", INIT_11 => X"{[8:0]_INIT_11}", INIT_12 => X"{[8:0]_INIT_12}", INIT_13 => X"{[8:0]_INIT_13}", INIT_14 => X"{[8:0]_INIT_14}", INIT_15 => X"{[8:0]_INIT_15}", INIT_16 => X"{[8:0]_INIT_16}", INIT_17 => X"{[8:0]_INIT_17}", INIT_18 => X"{[8:0]_INIT_18}", INIT_19 => X"{[8:0]_INIT_19}", INIT_1A => X"{[8:0]_INIT_1A}", INIT_1B => X"{[8:0]_INIT_1B}", INIT_1C => X"{[8:0]_INIT_1C}", INIT_1D => X"{[8:0]_INIT_1D}", INIT_1E => X"{[8:0]_INIT_1E}", INIT_1F => X"{[8:0]_INIT_1F}", INIT_20 => X"{[8:0]_INIT_20}", INIT_21 => X"{[8:0]_INIT_21}", INIT_22 => X"{[8:0]_INIT_22}", INIT_23 => X"{[8:0]_INIT_23}", INIT_24 => X"{[8:0]_INIT_24}", INIT_25 => X"{[8:0]_INIT_25}", INIT_26 => X"{[8:0]_INIT_26}", INIT_27 => X"{[8:0]_INIT_27}", INIT_28 => X"{[8:0]_INIT_28}", INIT_29 => X"{[8:0]_INIT_29}", INIT_2A => X"{[8:0]_INIT_2A}", INIT_2B => X"{[8:0]_INIT_2B}", INIT_2C => X"{[8:0]_INIT_2C}", INIT_2D => X"{[8:0]_INIT_2D}", INIT_2E => X"{[8:0]_INIT_2E}", INIT_2F => X"{[8:0]_INIT_2F}", INIT_30 => X"{[8:0]_INIT_30}", INIT_31 => X"{[8:0]_INIT_31}", INIT_32 => X"{[8:0]_INIT_32}", INIT_33 => X"{[8:0]_INIT_33}", INIT_34 => X"{[8:0]_INIT_34}", INIT_35 => X"{[8:0]_INIT_35}", INIT_36 => X"{[8:0]_INIT_36}", INIT_37 => X"{[8:0]_INIT_37}", INIT_38 => X"{[8:0]_INIT_38}", INIT_39 => X"{[8:0]_INIT_39}", INIT_3A => X"{[8:0]_INIT_3A}", INIT_3B => X"{[8:0]_INIT_3B}", INIT_3C => X"{[8:0]_INIT_3C}", INIT_3D => X"{[8:0]_INIT_3D}", INIT_3E => X"{[8:0]_INIT_3E}", INIT_3F => X"{[8:0]_INIT_3F}", INITP_00 => X"{[8:0]_INITP_00}", INITP_01 => X"{[8:0]_INITP_01}", INITP_02 => X"{[8:0]_INITP_02}", INITP_03 => X"{[8:0]_INITP_03}", INITP_04 => X"{[8:0]_INITP_04}", INITP_05 => X"{[8:0]_INITP_05}", INITP_06 => X"{[8:0]_INITP_06}", INITP_07 => X"{[8:0]_INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_l(31 downto 0), DOPA => data_out_a_l(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_l(31 downto 0), DOPB => data_out_b_l(35 downto 32), DIB => data_in_b_l(31 downto 0), DIPB => data_in_b_l(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- kcpsm6_rom_h: RAMB16BWER generic map ( DATA_WIDTH_A => 9, DOA_REG => 0, EN_RSTRAM_A => FALSE, INIT_A => X"000000000", RST_PRIORITY_A => "CE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", DATA_WIDTH_B => 9, DOB_REG => 0, EN_RSTRAM_B => FALSE, INIT_B => X"000000000", RST_PRIORITY_B => "CE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", RSTTYPE => "SYNC", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", SIM_DEVICE => "SPARTAN6", INIT_00 => X"{[17:9]_INIT_00}", INIT_01 => X"{[17:9]_INIT_01}", INIT_02 => X"{[17:9]_INIT_02}", INIT_03 => X"{[17:9]_INIT_03}", INIT_04 => X"{[17:9]_INIT_04}", INIT_05 => X"{[17:9]_INIT_05}", INIT_06 => X"{[17:9]_INIT_06}", INIT_07 => X"{[17:9]_INIT_07}", INIT_08 => X"{[17:9]_INIT_08}", INIT_09 => X"{[17:9]_INIT_09}", INIT_0A => X"{[17:9]_INIT_0A}", INIT_0B => X"{[17:9]_INIT_0B}", INIT_0C => X"{[17:9]_INIT_0C}", INIT_0D => X"{[17:9]_INIT_0D}", INIT_0E => X"{[17:9]_INIT_0E}", INIT_0F => X"{[17:9]_INIT_0F}", INIT_10 => X"{[17:9]_INIT_10}", INIT_11 => X"{[17:9]_INIT_11}", INIT_12 => X"{[17:9]_INIT_12}", INIT_13 => X"{[17:9]_INIT_13}", INIT_14 => X"{[17:9]_INIT_14}", INIT_15 => X"{[17:9]_INIT_15}", INIT_16 => X"{[17:9]_INIT_16}", INIT_17 => X"{[17:9]_INIT_17}", INIT_18 => X"{[17:9]_INIT_18}", INIT_19 => X"{[17:9]_INIT_19}", INIT_1A => X"{[17:9]_INIT_1A}", INIT_1B => X"{[17:9]_INIT_1B}", INIT_1C => X"{[17:9]_INIT_1C}", INIT_1D => X"{[17:9]_INIT_1D}", INIT_1E => X"{[17:9]_INIT_1E}", INIT_1F => X"{[17:9]_INIT_1F}", INIT_20 => X"{[17:9]_INIT_20}", INIT_21 => X"{[17:9]_INIT_21}", INIT_22 => X"{[17:9]_INIT_22}", INIT_23 => X"{[17:9]_INIT_23}", INIT_24 => X"{[17:9]_INIT_24}", INIT_25 => X"{[17:9]_INIT_25}", INIT_26 => X"{[17:9]_INIT_26}", INIT_27 => X"{[17:9]_INIT_27}", INIT_28 => X"{[17:9]_INIT_28}", INIT_29 => X"{[17:9]_INIT_29}", INIT_2A => X"{[17:9]_INIT_2A}", INIT_2B => X"{[17:9]_INIT_2B}", INIT_2C => X"{[17:9]_INIT_2C}", INIT_2D => X"{[17:9]_INIT_2D}", INIT_2E => X"{[17:9]_INIT_2E}", INIT_2F => X"{[17:9]_INIT_2F}", INIT_30 => X"{[17:9]_INIT_30}", INIT_31 => X"{[17:9]_INIT_31}", INIT_32 => X"{[17:9]_INIT_32}", INIT_33 => X"{[17:9]_INIT_33}", INIT_34 => X"{[17:9]_INIT_34}", INIT_35 => X"{[17:9]_INIT_35}", INIT_36 => X"{[17:9]_INIT_36}", INIT_37 => X"{[17:9]_INIT_37}", INIT_38 => X"{[17:9]_INIT_38}", INIT_39 => X"{[17:9]_INIT_39}", INIT_3A => X"{[17:9]_INIT_3A}", INIT_3B => X"{[17:9]_INIT_3B}", INIT_3C => X"{[17:9]_INIT_3C}", INIT_3D => X"{[17:9]_INIT_3D}", INIT_3E => X"{[17:9]_INIT_3E}", INIT_3F => X"{[17:9]_INIT_3F}", INITP_00 => X"{[17:9]_INITP_00}", INITP_01 => X"{[17:9]_INITP_01}", INITP_02 => X"{[17:9]_INITP_02}", INITP_03 => X"{[17:9]_INITP_03}", INITP_04 => X"{[17:9]_INITP_04}", INITP_05 => X"{[17:9]_INITP_05}", INITP_06 => X"{[17:9]_INITP_06}", INITP_07 => X"{[17:9]_INITP_07}") port map( ADDRA => address_a(13 downto 0), ENA => enable, CLKA => clk, DOA => data_out_a_h(31 downto 0), DOPA => data_out_a_h(35 downto 32), DIA => data_in_a(31 downto 0), DIPA => data_in_a(35 downto 32), WEA => "0000", REGCEA => '0', RSTA => '0', ADDRB => address_b(13 downto 0), ENB => enable_b, CLKB => clk_b, DOB => data_out_b_h(31 downto 0), DOPB => data_out_b_h(35 downto 32), DIB => data_in_b_h(31 downto 0), DIPB => data_in_b_h(35 downto 32), WEB => we_b(3 downto 0), REGCEB => '0', RSTB => '0'); -- end generate s6; -- -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(10 downto 0) & "0000"; instruction <= data_out_a(33 downto 32) & data_out_a(15 downto 0); data_in_a <= "00000000000000000000000000000000000" & address(11); jtag_dout <= data_out_b(33 downto 32) & data_out_b(15 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b <= "00" & data_out_b(33 downto 32) & "0000000000000000" & data_out_b(15 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b <= "00" & jtag_din(17 downto 16) & "0000000000000000" & jtag_din(15 downto 0); address_b <= '0' & jtag_addr(10 downto 0) & "0000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom: RAMB36E1 generic map ( READ_WIDTH_A => 18, WRITE_WIDTH_A => 18, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 18, WRITE_WIDTH_B => 18, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{INIT_00}", INIT_01 => X"{INIT_01}", INIT_02 => X"{INIT_02}", INIT_03 => X"{INIT_03}", INIT_04 => X"{INIT_04}", INIT_05 => X"{INIT_05}", INIT_06 => X"{INIT_06}", INIT_07 => X"{INIT_07}", INIT_08 => X"{INIT_08}", INIT_09 => X"{INIT_09}", INIT_0A => X"{INIT_0A}", INIT_0B => X"{INIT_0B}", INIT_0C => X"{INIT_0C}", INIT_0D => X"{INIT_0D}", INIT_0E => X"{INIT_0E}", INIT_0F => X"{INIT_0F}", INIT_10 => X"{INIT_10}", INIT_11 => X"{INIT_11}", INIT_12 => X"{INIT_12}", INIT_13 => X"{INIT_13}", INIT_14 => X"{INIT_14}", INIT_15 => X"{INIT_15}", INIT_16 => X"{INIT_16}", INIT_17 => X"{INIT_17}", INIT_18 => X"{INIT_18}", INIT_19 => X"{INIT_19}", INIT_1A => X"{INIT_1A}", INIT_1B => X"{INIT_1B}", INIT_1C => X"{INIT_1C}", INIT_1D => X"{INIT_1D}", INIT_1E => X"{INIT_1E}", INIT_1F => X"{INIT_1F}", INIT_20 => X"{INIT_20}", INIT_21 => X"{INIT_21}", INIT_22 => X"{INIT_22}", INIT_23 => X"{INIT_23}", INIT_24 => X"{INIT_24}", INIT_25 => X"{INIT_25}", INIT_26 => X"{INIT_26}", INIT_27 => X"{INIT_27}", INIT_28 => X"{INIT_28}", INIT_29 => X"{INIT_29}", INIT_2A => X"{INIT_2A}", INIT_2B => X"{INIT_2B}", INIT_2C => X"{INIT_2C}", INIT_2D => X"{INIT_2D}", INIT_2E => X"{INIT_2E}", INIT_2F => X"{INIT_2F}", INIT_30 => X"{INIT_30}", INIT_31 => X"{INIT_31}", INIT_32 => X"{INIT_32}", INIT_33 => X"{INIT_33}", INIT_34 => X"{INIT_34}", INIT_35 => X"{INIT_35}", INIT_36 => X"{INIT_36}", INIT_37 => X"{INIT_37}", INIT_38 => X"{INIT_38}", INIT_39 => X"{INIT_39}", INIT_3A => X"{INIT_3A}", INIT_3B => X"{INIT_3B}", INIT_3C => X"{INIT_3C}", INIT_3D => X"{INIT_3D}", INIT_3E => X"{INIT_3E}", INIT_3F => X"{INIT_3F}", INIT_40 => X"{INIT_40}", INIT_41 => X"{INIT_41}", INIT_42 => X"{INIT_42}", INIT_43 => X"{INIT_43}", INIT_44 => X"{INIT_44}", INIT_45 => X"{INIT_45}", INIT_46 => X"{INIT_46}", INIT_47 => X"{INIT_47}", INIT_48 => X"{INIT_48}", INIT_49 => X"{INIT_49}", INIT_4A => X"{INIT_4A}", INIT_4B => X"{INIT_4B}", INIT_4C => X"{INIT_4C}", INIT_4D => X"{INIT_4D}", INIT_4E => X"{INIT_4E}", INIT_4F => X"{INIT_4F}", INIT_50 => X"{INIT_50}", INIT_51 => X"{INIT_51}", INIT_52 => X"{INIT_52}", INIT_53 => X"{INIT_53}", INIT_54 => X"{INIT_54}", INIT_55 => X"{INIT_55}", INIT_56 => X"{INIT_56}", INIT_57 => X"{INIT_57}", INIT_58 => X"{INIT_58}", INIT_59 => X"{INIT_59}", INIT_5A => X"{INIT_5A}", INIT_5B => X"{INIT_5B}", INIT_5C => X"{INIT_5C}", INIT_5D => X"{INIT_5D}", INIT_5E => X"{INIT_5E}", INIT_5F => X"{INIT_5F}", INIT_60 => X"{INIT_60}", INIT_61 => X"{INIT_61}", INIT_62 => X"{INIT_62}", INIT_63 => X"{INIT_63}", INIT_64 => X"{INIT_64}", INIT_65 => X"{INIT_65}", INIT_66 => X"{INIT_66}", INIT_67 => X"{INIT_67}", INIT_68 => X"{INIT_68}", INIT_69 => X"{INIT_69}", INIT_6A => X"{INIT_6A}", INIT_6B => X"{INIT_6B}", INIT_6C => X"{INIT_6C}", INIT_6D => X"{INIT_6D}", INIT_6E => X"{INIT_6E}", INIT_6F => X"{INIT_6F}", INIT_70 => X"{INIT_70}", INIT_71 => X"{INIT_71}", INIT_72 => X"{INIT_72}", INIT_73 => X"{INIT_73}", INIT_74 => X"{INIT_74}", INIT_75 => X"{INIT_75}", INIT_76 => X"{INIT_76}", INIT_77 => X"{INIT_77}", INIT_78 => X"{INIT_78}", INIT_79 => X"{INIT_79}", INIT_7A => X"{INIT_7A}", INIT_7B => X"{INIT_7B}", INIT_7C => X"{INIT_7C}", INIT_7D => X"{INIT_7D}", INIT_7E => X"{INIT_7E}", INIT_7F => X"{INIT_7F}", INITP_00 => X"{INITP_00}", INITP_01 => X"{INITP_01}", INITP_02 => X"{INITP_02}", INITP_03 => X"{INITP_03}", INITP_04 => X"{INITP_04}", INITP_05 => X"{INITP_05}", INITP_06 => X"{INITP_06}", INITP_07 => X"{INITP_07}", INITP_08 => X"{INITP_08}", INITP_09 => X"{INITP_09}", INITP_0A => X"{INITP_0A}", INITP_0B => X"{INITP_0B}", INITP_0C => X"{INITP_0C}", INITP_0D => X"{INITP_0D}", INITP_0E => X"{INITP_0E}", INITP_0F => X"{INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a(31 downto 0), DOPADOP => data_out_a(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b(31 downto 0), DOPBDOP => data_out_b(35 downto 32), DIBDI => data_in_b(31 downto 0), DIPBDIP => data_in_b(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- end generate ram_2k_generate; -- -- ram_4k_generate : if (C_RAM_SIZE_KWORDS = 4) generate s6: if (C_FAMILY = "S6") generate assert(1=0) report "4K BRAM in Spartan-6 is a special case not supported by this template." severity FAILURE; end generate s6; -- v6 : if (C_FAMILY = "V6") generate -- address_a <= '0' & address(11 downto 0) & "000"; instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0); data_in_a <= "000000000000000000000000000000000000"; jtag_dout <= data_out_b_h(32) & data_out_b_h(7 downto 0) & data_out_b_l(32) & data_out_b_l(7 downto 0); -- no_loader : if (C_JTAG_LOADER_ENABLE = 0) generate data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0); data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0); address_b <= "0000000000000000"; we_b <= "00000000"; enable_b <= '0'; rdl <= '0'; clk_b <= '0'; end generate no_loader; -- loader : if (C_JTAG_LOADER_ENABLE = 1) generate data_in_b_h <= "000" & jtag_din(17) & "000000000000000000000000" & jtag_din(16 downto 9); data_in_b_l <= "000" & jtag_din(8) & "000000000000000000000000" & jtag_din(7 downto 0); address_b <= '0' & jtag_addr(11 downto 0) & "000"; we_b <= jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we & jtag_we; enable_b <= jtag_en(0); rdl <= rdl_bus(0); clk_b <= jtag_clk; end generate loader; -- kcpsm6_rom_l: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{[8:0]_INIT_00}", INIT_01 => X"{[8:0]_INIT_01}", INIT_02 => X"{[8:0]_INIT_02}", INIT_03 => X"{[8:0]_INIT_03}", INIT_04 => X"{[8:0]_INIT_04}", INIT_05 => X"{[8:0]_INIT_05}", INIT_06 => X"{[8:0]_INIT_06}", INIT_07 => X"{[8:0]_INIT_07}", INIT_08 => X"{[8:0]_INIT_08}", INIT_09 => X"{[8:0]_INIT_09}", INIT_0A => X"{[8:0]_INIT_0A}", INIT_0B => X"{[8:0]_INIT_0B}", INIT_0C => X"{[8:0]_INIT_0C}", INIT_0D => X"{[8:0]_INIT_0D}", INIT_0E => X"{[8:0]_INIT_0E}", INIT_0F => X"{[8:0]_INIT_0F}", INIT_10 => X"{[8:0]_INIT_10}", INIT_11 => X"{[8:0]_INIT_11}", INIT_12 => X"{[8:0]_INIT_12}", INIT_13 => X"{[8:0]_INIT_13}", INIT_14 => X"{[8:0]_INIT_14}", INIT_15 => X"{[8:0]_INIT_15}", INIT_16 => X"{[8:0]_INIT_16}", INIT_17 => X"{[8:0]_INIT_17}", INIT_18 => X"{[8:0]_INIT_18}", INIT_19 => X"{[8:0]_INIT_19}", INIT_1A => X"{[8:0]_INIT_1A}", INIT_1B => X"{[8:0]_INIT_1B}", INIT_1C => X"{[8:0]_INIT_1C}", INIT_1D => X"{[8:0]_INIT_1D}", INIT_1E => X"{[8:0]_INIT_1E}", INIT_1F => X"{[8:0]_INIT_1F}", INIT_20 => X"{[8:0]_INIT_20}", INIT_21 => X"{[8:0]_INIT_21}", INIT_22 => X"{[8:0]_INIT_22}", INIT_23 => X"{[8:0]_INIT_23}", INIT_24 => X"{[8:0]_INIT_24}", INIT_25 => X"{[8:0]_INIT_25}", INIT_26 => X"{[8:0]_INIT_26}", INIT_27 => X"{[8:0]_INIT_27}", INIT_28 => X"{[8:0]_INIT_28}", INIT_29 => X"{[8:0]_INIT_29}", INIT_2A => X"{[8:0]_INIT_2A}", INIT_2B => X"{[8:0]_INIT_2B}", INIT_2C => X"{[8:0]_INIT_2C}", INIT_2D => X"{[8:0]_INIT_2D}", INIT_2E => X"{[8:0]_INIT_2E}", INIT_2F => X"{[8:0]_INIT_2F}", INIT_30 => X"{[8:0]_INIT_30}", INIT_31 => X"{[8:0]_INIT_31}", INIT_32 => X"{[8:0]_INIT_32}", INIT_33 => X"{[8:0]_INIT_33}", INIT_34 => X"{[8:0]_INIT_34}", INIT_35 => X"{[8:0]_INIT_35}", INIT_36 => X"{[8:0]_INIT_36}", INIT_37 => X"{[8:0]_INIT_37}", INIT_38 => X"{[8:0]_INIT_38}", INIT_39 => X"{[8:0]_INIT_39}", INIT_3A => X"{[8:0]_INIT_3A}", INIT_3B => X"{[8:0]_INIT_3B}", INIT_3C => X"{[8:0]_INIT_3C}", INIT_3D => X"{[8:0]_INIT_3D}", INIT_3E => X"{[8:0]_INIT_3E}", INIT_3F => X"{[8:0]_INIT_3F}", INIT_40 => X"{[8:0]_INIT_40}", INIT_41 => X"{[8:0]_INIT_41}", INIT_42 => X"{[8:0]_INIT_42}", INIT_43 => X"{[8:0]_INIT_43}", INIT_44 => X"{[8:0]_INIT_44}", INIT_45 => X"{[8:0]_INIT_45}", INIT_46 => X"{[8:0]_INIT_46}", INIT_47 => X"{[8:0]_INIT_47}", INIT_48 => X"{[8:0]_INIT_48}", INIT_49 => X"{[8:0]_INIT_49}", INIT_4A => X"{[8:0]_INIT_4A}", INIT_4B => X"{[8:0]_INIT_4B}", INIT_4C => X"{[8:0]_INIT_4C}", INIT_4D => X"{[8:0]_INIT_4D}", INIT_4E => X"{[8:0]_INIT_4E}", INIT_4F => X"{[8:0]_INIT_4F}", INIT_50 => X"{[8:0]_INIT_50}", INIT_51 => X"{[8:0]_INIT_51}", INIT_52 => X"{[8:0]_INIT_52}", INIT_53 => X"{[8:0]_INIT_53}", INIT_54 => X"{[8:0]_INIT_54}", INIT_55 => X"{[8:0]_INIT_55}", INIT_56 => X"{[8:0]_INIT_56}", INIT_57 => X"{[8:0]_INIT_57}", INIT_58 => X"{[8:0]_INIT_58}", INIT_59 => X"{[8:0]_INIT_59}", INIT_5A => X"{[8:0]_INIT_5A}", INIT_5B => X"{[8:0]_INIT_5B}", INIT_5C => X"{[8:0]_INIT_5C}", INIT_5D => X"{[8:0]_INIT_5D}", INIT_5E => X"{[8:0]_INIT_5E}", INIT_5F => X"{[8:0]_INIT_5F}", INIT_60 => X"{[8:0]_INIT_60}", INIT_61 => X"{[8:0]_INIT_61}", INIT_62 => X"{[8:0]_INIT_62}", INIT_63 => X"{[8:0]_INIT_63}", INIT_64 => X"{[8:0]_INIT_64}", INIT_65 => X"{[8:0]_INIT_65}", INIT_66 => X"{[8:0]_INIT_66}", INIT_67 => X"{[8:0]_INIT_67}", INIT_68 => X"{[8:0]_INIT_68}", INIT_69 => X"{[8:0]_INIT_69}", INIT_6A => X"{[8:0]_INIT_6A}", INIT_6B => X"{[8:0]_INIT_6B}", INIT_6C => X"{[8:0]_INIT_6C}", INIT_6D => X"{[8:0]_INIT_6D}", INIT_6E => X"{[8:0]_INIT_6E}", INIT_6F => X"{[8:0]_INIT_6F}", INIT_70 => X"{[8:0]_INIT_70}", INIT_71 => X"{[8:0]_INIT_71}", INIT_72 => X"{[8:0]_INIT_72}", INIT_73 => X"{[8:0]_INIT_73}", INIT_74 => X"{[8:0]_INIT_74}", INIT_75 => X"{[8:0]_INIT_75}", INIT_76 => X"{[8:0]_INIT_76}", INIT_77 => X"{[8:0]_INIT_77}", INIT_78 => X"{[8:0]_INIT_78}", INIT_79 => X"{[8:0]_INIT_79}", INIT_7A => X"{[8:0]_INIT_7A}", INIT_7B => X"{[8:0]_INIT_7B}", INIT_7C => X"{[8:0]_INIT_7C}", INIT_7D => X"{[8:0]_INIT_7D}", INIT_7E => X"{[8:0]_INIT_7E}", INIT_7F => X"{[8:0]_INIT_7F}", INITP_00 => X"{[8:0]_INITP_00}", INITP_01 => X"{[8:0]_INITP_01}", INITP_02 => X"{[8:0]_INITP_02}", INITP_03 => X"{[8:0]_INITP_03}", INITP_04 => X"{[8:0]_INITP_04}", INITP_05 => X"{[8:0]_INITP_05}", INITP_06 => X"{[8:0]_INITP_06}", INITP_07 => X"{[8:0]_INITP_07}", INITP_08 => X"{[8:0]_INITP_08}", INITP_09 => X"{[8:0]_INITP_09}", INITP_0A => X"{[8:0]_INITP_0A}", INITP_0B => X"{[8:0]_INITP_0B}", INITP_0C => X"{[8:0]_INITP_0C}", INITP_0D => X"{[8:0]_INITP_0D}", INITP_0E => X"{[8:0]_INITP_0E}", INITP_0F => X"{[8:0]_INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_l(31 downto 0), DOPADOP => data_out_a_l(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_l(31 downto 0), DOPBDOP => data_out_b_l(35 downto 32), DIBDI => data_in_b_l(31 downto 0), DIPBDIP => data_in_b_l(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- kcpsm6_rom_h: RAMB36E1 generic map ( READ_WIDTH_A => 9, WRITE_WIDTH_A => 9, DOA_REG => 0, INIT_A => X"000000000", RSTREG_PRIORITY_A => "REGCE", SRVAL_A => X"000000000", WRITE_MODE_A => "WRITE_FIRST", READ_WIDTH_B => 9, WRITE_WIDTH_B => 9, DOB_REG => 0, INIT_B => X"000000000", RSTREG_PRIORITY_B => "REGCE", SRVAL_B => X"000000000", WRITE_MODE_B => "WRITE_FIRST", INIT_FILE => "NONE", SIM_COLLISION_CHECK => "ALL", RAM_MODE => "TDP", RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", EN_ECC_READ => FALSE, EN_ECC_WRITE => FALSE, RAM_EXTENSION_A => "NONE", RAM_EXTENSION_B => "NONE", INIT_00 => X"{[17:9]_INIT_00}", INIT_01 => X"{[17:9]_INIT_01}", INIT_02 => X"{[17:9]_INIT_02}", INIT_03 => X"{[17:9]_INIT_03}", INIT_04 => X"{[17:9]_INIT_04}", INIT_05 => X"{[17:9]_INIT_05}", INIT_06 => X"{[17:9]_INIT_06}", INIT_07 => X"{[17:9]_INIT_07}", INIT_08 => X"{[17:9]_INIT_08}", INIT_09 => X"{[17:9]_INIT_09}", INIT_0A => X"{[17:9]_INIT_0A}", INIT_0B => X"{[17:9]_INIT_0B}", INIT_0C => X"{[17:9]_INIT_0C}", INIT_0D => X"{[17:9]_INIT_0D}", INIT_0E => X"{[17:9]_INIT_0E}", INIT_0F => X"{[17:9]_INIT_0F}", INIT_10 => X"{[17:9]_INIT_10}", INIT_11 => X"{[17:9]_INIT_11}", INIT_12 => X"{[17:9]_INIT_12}", INIT_13 => X"{[17:9]_INIT_13}", INIT_14 => X"{[17:9]_INIT_14}", INIT_15 => X"{[17:9]_INIT_15}", INIT_16 => X"{[17:9]_INIT_16}", INIT_17 => X"{[17:9]_INIT_17}", INIT_18 => X"{[17:9]_INIT_18}", INIT_19 => X"{[17:9]_INIT_19}", INIT_1A => X"{[17:9]_INIT_1A}", INIT_1B => X"{[17:9]_INIT_1B}", INIT_1C => X"{[17:9]_INIT_1C}", INIT_1D => X"{[17:9]_INIT_1D}", INIT_1E => X"{[17:9]_INIT_1E}", INIT_1F => X"{[17:9]_INIT_1F}", INIT_20 => X"{[17:9]_INIT_20}", INIT_21 => X"{[17:9]_INIT_21}", INIT_22 => X"{[17:9]_INIT_22}", INIT_23 => X"{[17:9]_INIT_23}", INIT_24 => X"{[17:9]_INIT_24}", INIT_25 => X"{[17:9]_INIT_25}", INIT_26 => X"{[17:9]_INIT_26}", INIT_27 => X"{[17:9]_INIT_27}", INIT_28 => X"{[17:9]_INIT_28}", INIT_29 => X"{[17:9]_INIT_29}", INIT_2A => X"{[17:9]_INIT_2A}", INIT_2B => X"{[17:9]_INIT_2B}", INIT_2C => X"{[17:9]_INIT_2C}", INIT_2D => X"{[17:9]_INIT_2D}", INIT_2E => X"{[17:9]_INIT_2E}", INIT_2F => X"{[17:9]_INIT_2F}", INIT_30 => X"{[17:9]_INIT_30}", INIT_31 => X"{[17:9]_INIT_31}", INIT_32 => X"{[17:9]_INIT_32}", INIT_33 => X"{[17:9]_INIT_33}", INIT_34 => X"{[17:9]_INIT_34}", INIT_35 => X"{[17:9]_INIT_35}", INIT_36 => X"{[17:9]_INIT_36}", INIT_37 => X"{[17:9]_INIT_37}", INIT_38 => X"{[17:9]_INIT_38}", INIT_39 => X"{[17:9]_INIT_39}", INIT_3A => X"{[17:9]_INIT_3A}", INIT_3B => X"{[17:9]_INIT_3B}", INIT_3C => X"{[17:9]_INIT_3C}", INIT_3D => X"{[17:9]_INIT_3D}", INIT_3E => X"{[17:9]_INIT_3E}", INIT_3F => X"{[17:9]_INIT_3F}", INIT_40 => X"{[17:9]_INIT_40}", INIT_41 => X"{[17:9]_INIT_41}", INIT_42 => X"{[17:9]_INIT_42}", INIT_43 => X"{[17:9]_INIT_43}", INIT_44 => X"{[17:9]_INIT_44}", INIT_45 => X"{[17:9]_INIT_45}", INIT_46 => X"{[17:9]_INIT_46}", INIT_47 => X"{[17:9]_INIT_47}", INIT_48 => X"{[17:9]_INIT_48}", INIT_49 => X"{[17:9]_INIT_49}", INIT_4A => X"{[17:9]_INIT_4A}", INIT_4B => X"{[17:9]_INIT_4B}", INIT_4C => X"{[17:9]_INIT_4C}", INIT_4D => X"{[17:9]_INIT_4D}", INIT_4E => X"{[17:9]_INIT_4E}", INIT_4F => X"{[17:9]_INIT_4F}", INIT_50 => X"{[17:9]_INIT_50}", INIT_51 => X"{[17:9]_INIT_51}", INIT_52 => X"{[17:9]_INIT_52}", INIT_53 => X"{[17:9]_INIT_53}", INIT_54 => X"{[17:9]_INIT_54}", INIT_55 => X"{[17:9]_INIT_55}", INIT_56 => X"{[17:9]_INIT_56}", INIT_57 => X"{[17:9]_INIT_57}", INIT_58 => X"{[17:9]_INIT_58}", INIT_59 => X"{[17:9]_INIT_59}", INIT_5A => X"{[17:9]_INIT_5A}", INIT_5B => X"{[17:9]_INIT_5B}", INIT_5C => X"{[17:9]_INIT_5C}", INIT_5D => X"{[17:9]_INIT_5D}", INIT_5E => X"{[17:9]_INIT_5E}", INIT_5F => X"{[17:9]_INIT_5F}", INIT_60 => X"{[17:9]_INIT_60}", INIT_61 => X"{[17:9]_INIT_61}", INIT_62 => X"{[17:9]_INIT_62}", INIT_63 => X"{[17:9]_INIT_63}", INIT_64 => X"{[17:9]_INIT_64}", INIT_65 => X"{[17:9]_INIT_65}", INIT_66 => X"{[17:9]_INIT_66}", INIT_67 => X"{[17:9]_INIT_67}", INIT_68 => X"{[17:9]_INIT_68}", INIT_69 => X"{[17:9]_INIT_69}", INIT_6A => X"{[17:9]_INIT_6A}", INIT_6B => X"{[17:9]_INIT_6B}", INIT_6C => X"{[17:9]_INIT_6C}", INIT_6D => X"{[17:9]_INIT_6D}", INIT_6E => X"{[17:9]_INIT_6E}", INIT_6F => X"{[17:9]_INIT_6F}", INIT_70 => X"{[17:9]_INIT_70}", INIT_71 => X"{[17:9]_INIT_71}", INIT_72 => X"{[17:9]_INIT_72}", INIT_73 => X"{[17:9]_INIT_73}", INIT_74 => X"{[17:9]_INIT_74}", INIT_75 => X"{[17:9]_INIT_75}", INIT_76 => X"{[17:9]_INIT_76}", INIT_77 => X"{[17:9]_INIT_77}", INIT_78 => X"{[17:9]_INIT_78}", INIT_79 => X"{[17:9]_INIT_79}", INIT_7A => X"{[17:9]_INIT_7A}", INIT_7B => X"{[17:9]_INIT_7B}", INIT_7C => X"{[17:9]_INIT_7C}", INIT_7D => X"{[17:9]_INIT_7D}", INIT_7E => X"{[17:9]_INIT_7E}", INIT_7F => X"{[17:9]_INIT_7F}", INITP_00 => X"{[17:9]_INITP_00}", INITP_01 => X"{[17:9]_INITP_01}", INITP_02 => X"{[17:9]_INITP_02}", INITP_03 => X"{[17:9]_INITP_03}", INITP_04 => X"{[17:9]_INITP_04}", INITP_05 => X"{[17:9]_INITP_05}", INITP_06 => X"{[17:9]_INITP_06}", INITP_07 => X"{[17:9]_INITP_07}", INITP_08 => X"{[17:9]_INITP_08}", INITP_09 => X"{[17:9]_INITP_09}", INITP_0A => X"{[17:9]_INITP_0A}", INITP_0B => X"{[17:9]_INITP_0B}", INITP_0C => X"{[17:9]_INITP_0C}", INITP_0D => X"{[17:9]_INITP_0D}", INITP_0E => X"{[17:9]_INITP_0E}", INITP_0F => X"{[17:9]_INITP_0F}") port map( ADDRARDADDR => address_a, ENARDEN => enable, CLKARDCLK => clk, DOADO => data_out_a_h(31 downto 0), DOPADOP => data_out_a_h(35 downto 32), DIADI => data_in_a(31 downto 0), DIPADIP => data_in_a(35 downto 32), WEA => "0000", REGCEAREGCE => '0', RSTRAMARSTRAM => '0', RSTREGARSTREG => '0', ADDRBWRADDR => address_b, ENBWREN => enable_b, CLKBWRCLK => clk_b, DOBDO => data_out_b_h(31 downto 0), DOPBDOP => data_out_b_h(35 downto 32), DIBDI => data_in_b_h(31 downto 0), DIPBDIP => data_in_b_h(35 downto 32), WEBWE => we_b, REGCEB => '0', RSTRAMB => '0', RSTREGB => '0', CASCADEINA => '0', CASCADEINB => '0', INJECTDBITERR => '0', INJECTSBITERR => '0'); -- end generate v6; -- end generate ram_4k_generate; -- -- -- -- -- JTAG Loader -- instantiate_loader : if (C_JTAG_LOADER_ENABLE = 1) generate -- jtag_loader_6_inst : jtag_loader_6 generic map( C_FAMILY => C_FAMILY, C_NUM_PICOBLAZE => 1, C_JTAG_LOADER_ENABLE => C_JTAG_LOADER_ENABLE, C_BRAM_MAX_ADDR_WIDTH => BRAM_ADDRESS_WIDTH, C_ADDR_WIDTH_0 => BRAM_ADDRESS_WIDTH) port map( picoblaze_reset => rdl_bus, jtag_en => jtag_en, jtag_din => jtag_din, jtag_addr => jtag_addr(BRAM_ADDRESS_WIDTH-1 downto 0), jtag_clk => jtag_clk, jtag_we => jtag_we, jtag_dout_0 => jtag_dout, jtag_dout_1 => jtag_dout, -- ports 1-7 are not used jtag_dout_2 => jtag_dout, -- in a 1 device debug jtag_dout_3 => jtag_dout, -- session. However, Synplify jtag_dout_4 => jtag_dout, -- etc require all ports to jtag_dout_5 => jtag_dout, -- be connected jtag_dout_6 => jtag_dout, jtag_dout_7 => jtag_dout); -- end generate instantiate_loader; -- end low_level_definition; -- -- -- JTAG Loader 6 - Version 6.00 -- Kris Chaplin 4 February 2010 -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- library unisim; use unisim.vcomponents.all; -- entity jtag_loader_6 is generic( C_JTAG_LOADER_ENABLE : integer := 1; C_FAMILY : string := "V6"; C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_JTAG_CHAIN : integer := 2; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10); port( picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); jtag_en : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); jtag_din : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); jtag_addr : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0'); jtag_clk : out std_logic := '0'; jtag_we : out std_logic := '0'; jtag_dout_0 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_1 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_2 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_3 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_4 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_5 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_6 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); jtag_dout_7 : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0)); end jtag_loader_6; -- architecture Behavioral of jtag_loader_6 is -- component bscan_logic generic( C_JTAG_CHAIN : integer := 2; C_BUFFER_SHIFT_CLOCK : boolean := TRUE; C_FAMILY : string := "S6"); port( shift_dout : in std_logic; shift_clk : out std_logic; bram_en : out std_logic; shift_din : out std_logic; bram_strobe : out std_logic; capture : out std_logic; shift : out std_logic); end component; -- component jtag_shifter generic ( C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18); port( shift_clk : in std_logic; shift_din : in std_logic; shift : in std_logic; shift_dout : out std_logic; control_reg_ce : out std_logic; bram_ce : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); bram_a : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); din_load : in std_logic; din : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_d : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_we : out std_logic); end component; -- component control_registers generic ( C_NUM_PICOBLAZE : integer := 1; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10; C_BRAM_MAX_ADDR_WIDTH : integer := 10); port( en : in std_logic; ce : in std_logic; wnr : in std_logic; clk : in std_logic; a : in std_logic_vector(3 downto 0); din : in std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); dout : out std_logic_vector(7 downto 0); picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0)); end component; -- signal shift_clk : std_logic; signal shift_din : std_logic; signal shift_dout : std_logic; signal shift : std_logic; signal capture : std_logic; -- signal control_reg_ce : std_logic; signal bram_ce : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal bus_zero : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal jtag_en_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); signal jtag_en_expanded : std_logic_vector(7 downto 0) := (others => '0'); signal jtag_addr_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); signal jtag_din_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal control_din : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal control_dout : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0):= (others => '0'); signal bram_dout_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); signal jtag_we_int : std_logic; signal jtag_clk_int : std_logic; signal bram_ce_valid : std_logic; signal din_load : std_logic; -- signal jtag_dout_0_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_1_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_2_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_3_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_4_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_5_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_6_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal jtag_dout_7_masked : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); -- begin bus_zero <= (others => '0'); -- jtag_loader_gen: if (C_JTAG_LOADER_ENABLE = 1) generate -- Inst_bscan_logic: bscan_logic generic map ( C_JTAG_CHAIN => C_JTAG_CHAIN, C_BUFFER_SHIFT_CLOCK => TRUE, C_FAMILY => C_FAMILY ) port map( shift_dout => shift_dout, shift_clk => shift_clk, bram_en => bram_ce_valid, shift_din => shift_din, bram_strobe => jtag_clk_int, capture => capture, shift => shift ); -- Inst_jtag_shifter: jtag_shifter generic map( C_NUM_PICOBLAZE => C_NUM_PICOBLAZE, C_BRAM_MAX_ADDR_WIDTH => C_BRAM_MAX_ADDR_WIDTH, C_PICOBLAZE_INSTRUCTION_DATA_WIDTH => C_PICOBLAZE_INSTRUCTION_DATA_WIDTH ) port map( shift_clk => shift_clk, shift_din => shift_din, shift => shift, shift_dout => shift_dout, control_reg_ce => control_reg_ce, bram_ce => bram_ce, bram_a => jtag_addr_int, din_load => din_load, din => bram_dout_int, bram_d => jtag_din_int, bram_we => jtag_we_int ); -- process (bram_ce, din_load, capture, bus_zero, control_reg_ce) begin if ( bram_ce = bus_zero ) then din_load <= capture and control_reg_ce; else din_load <= capture; end if; end process; -- Inst_control_registers: control_registers generic map( C_NUM_PICOBLAZE => C_NUM_PICOBLAZE, C_PICOBLAZE_INSTRUCTION_DATA_WIDTH => C_PICOBLAZE_INSTRUCTION_DATA_WIDTH, C_ADDR_WIDTH_0 => C_ADDR_WIDTH_0, C_ADDR_WIDTH_1 => C_ADDR_WIDTH_1, C_ADDR_WIDTH_2 => C_ADDR_WIDTH_2, C_ADDR_WIDTH_3 => C_ADDR_WIDTH_3, C_ADDR_WIDTH_4 => C_ADDR_WIDTH_4, C_ADDR_WIDTH_5 => C_ADDR_WIDTH_5, C_ADDR_WIDTH_6 => C_ADDR_WIDTH_6, C_ADDR_WIDTH_7 => C_ADDR_WIDTH_7, C_BRAM_MAX_ADDR_WIDTH => C_BRAM_MAX_ADDR_WIDTH) port map( en => bram_ce_valid, ce => control_reg_ce, wnr => jtag_we_int, clk => jtag_clk_int, a => jtag_addr_int(3 downto 0), din => control_din(C_NUM_PICOBLAZE-1 downto 0), dout => control_dout(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-8), picoblaze_reset => picoblaze_reset_int); -- control_dout (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-9 downto 0) <= (others => '0') when (C_PICOBLAZE_INSTRUCTION_DATA_WIDTH > 8); -- -- Qualify the blockram CS signal with bscan select output jtag_en_int <= bram_ce when bram_ce_valid = '1' else (others => '0'); -- jtag_en_expanded(C_NUM_PICOBLAZE-1 downto 0) <= jtag_en_int; jtag_en_expanded(7 downto C_NUM_PICOBLAZE) <= (others => '0') when (C_NUM_PICOBLAZE < 8); -- bram_dout_int <= control_dout or jtag_dout_0_masked or jtag_dout_1_masked or jtag_dout_2_masked or jtag_dout_3_masked or jtag_dout_4_masked or jtag_dout_5_masked or jtag_dout_6_masked or jtag_dout_7_masked; -- control_din <= jtag_din_int; -- jtag_dout_0_masked <= jtag_dout_0 when jtag_en_expanded(0) = '1' else (others => '0'); jtag_dout_1_masked <= jtag_dout_1 when jtag_en_expanded(1) = '1' else (others => '0'); jtag_dout_2_masked <= jtag_dout_2 when jtag_en_expanded(2) = '1' else (others => '0'); jtag_dout_3_masked <= jtag_dout_3 when jtag_en_expanded(3) = '1' else (others => '0'); jtag_dout_4_masked <= jtag_dout_4 when jtag_en_expanded(4) = '1' else (others => '0'); jtag_dout_5_masked <= jtag_dout_5 when jtag_en_expanded(5) = '1' else (others => '0'); jtag_dout_6_masked <= jtag_dout_6 when jtag_en_expanded(6) = '1' else (others => '0'); jtag_dout_7_masked <= jtag_dout_7 when jtag_en_expanded(7) = '1' else (others => '0'); -- end generate jtag_loader_gen; -- -- jtag_en <= jtag_en_int; jtag_din <= jtag_din_int; jtag_addr <= jtag_addr_int; jtag_clk <= jtag_clk_int; jtag_we <= jtag_we_int; picoblaze_reset <= picoblaze_reset_int; -- end Behavioral; -- -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity control_registers is generic ( C_NUM_PICOBLAZE : integer := 1; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18; C_ADDR_WIDTH_0 : integer := 10; C_ADDR_WIDTH_1 : integer := 10; C_ADDR_WIDTH_2 : integer := 10; C_ADDR_WIDTH_3 : integer := 10; C_ADDR_WIDTH_4 : integer := 10; C_ADDR_WIDTH_5 : integer := 10; C_ADDR_WIDTH_6 : integer := 10; C_ADDR_WIDTH_7 : integer := 10; C_BRAM_MAX_ADDR_WIDTH : integer := 10 ); Port ( en : in std_logic; ce : in std_logic; wnr : in std_logic; clk : in std_logic; a : in std_logic_vector (3 downto 0); din : in std_logic_vector (C_NUM_PICOBLAZE-1 downto 0); dout : out std_logic_vector (7 downto 0); picoblaze_reset : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) ); end control_registers; -- architecture Behavioral of control_registers is -- signal version : std_logic_vector(7 downto 0) := "00000001"; signal picoblaze_reset_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal picoblaze_wait_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal dout_int : std_logic_vector(7 downto 0) := (others => '0'); signal num_picoblaze : std_logic_vector(2 downto 0); signal picoblaze_instruction_data_width : std_logic_vector(4 downto 0); -- begin -- num_picoblaze <= conv_std_logic_vector(C_NUM_PICOBLAZE-1,3); picoblaze_instruction_data_width <= conv_std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1,5); -- process(clk) begin if (clk'event and clk = '1') then if (en = '1') and (wnr = '0') and (ce = '1') then case (a) is when "0000" => -- 0 = version - returns (7 downto 4) illustrating number of PB -- and (3 downto 0) picoblaze instruction data width dout_int <= num_picoblaze & picoblaze_instruction_data_width; when "0001" => -- 1 = PicoBlaze 0 reset / status if (C_NUM_PICOBLAZE >= 1) then dout_int <= picoblaze_reset_int(0) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_0-1,5) ); else dout_int <= (others => '0'); end if; when "0010" => -- 2 = PicoBlaze 1 reset / status if (C_NUM_PICOBLAZE >= 2) then dout_int <= picoblaze_reset_int(1) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_1-1,5) ); else dout_int <= (others => '0'); end if; when "0011" => -- 3 = PicoBlaze 2 reset / status if (C_NUM_PICOBLAZE >= 3) then dout_int <= picoblaze_reset_int(2) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_2-1,5) ); else dout_int <= (others => '0'); end if; when "0100" => -- 4 = PicoBlaze 3 reset / status if (C_NUM_PICOBLAZE >= 4) then dout_int <= picoblaze_reset_int(3) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_3-1,5) ); else dout_int <= (others => '0'); end if; when "0101" => -- 5 = PicoBlaze 4 reset / status if (C_NUM_PICOBLAZE >= 5) then dout_int <= picoblaze_reset_int(4) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_4-1,5) ); else dout_int <= (others => '0'); end if; when "0110" => -- 6 = PicoBlaze 5 reset / status if (C_NUM_PICOBLAZE >= 6) then dout_int <= picoblaze_reset_int(5) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_5-1,5) ); else dout_int <= (others => '0'); end if; when "0111" => -- 7 = PicoBlaze 6 reset / status if (C_NUM_PICOBLAZE >= 7) then dout_int <= picoblaze_reset_int(6) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_6-1,5) ); else dout_int <= (others => '0'); end if; when "1000" => -- 8 = PicoBlaze 7 reset / status if (C_NUM_PICOBLAZE >= 8) then dout_int <= picoblaze_reset_int(7) & "00" & (conv_std_logic_vector(C_ADDR_WIDTH_7-1,5) ); else dout_int <= (others => '0'); end if; when "1111" => dout_int <= conv_std_logic_vector(C_BRAM_MAX_ADDR_WIDTH -1,8); when others => dout_int <= (others => '1'); end case; else dout_int <= (others => '0'); end if; end if; end process; -- dout <= dout_int; -- process(clk) begin if (clk'event and clk = '1') then if (en = '1') and (wnr = '1') and (ce = '1') then picoblaze_reset_int(C_NUM_PICOBLAZE-1 downto 0) <= din(C_NUM_PICOBLAZE-1 downto 0); end if; end if; end process; -- picoblaze_reset <= picoblaze_reset_int; -- end Behavioral; -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- entity jtag_shifter is generic ( C_NUM_PICOBLAZE : integer := 1; C_BRAM_MAX_ADDR_WIDTH : integer := 10; C_PICOBLAZE_INSTRUCTION_DATA_WIDTH : integer := 18); Port ( shift_clk : in std_logic; shift_din : in std_logic; shift : in std_logic; shift_dout : out std_logic; control_reg_ce : out std_logic; bram_ce : out std_logic_vector(C_NUM_PICOBLAZE-1 downto 0); bram_a : out std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0); din_load : in std_logic; din : in std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_d : out std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0); bram_we : out std_logic ); end jtag_shifter; -- architecture Behavioral of jtag_shifter is -- signal control_reg_ce_int : std_logic; signal bram_ce_int : std_logic_vector(C_NUM_PICOBLAZE-1 downto 0) := (others => '0'); signal bram_a_int : std_logic_vector(C_BRAM_MAX_ADDR_WIDTH-1 downto 0) := (others => '0'); signal bram_d_int : std_logic_vector(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1 downto 0) := (others => '0'); signal bram_we_int : std_logic := '0'; -- begin -- control_reg_ce_shift : process (shift_clk) begin if shift_clk'event and shift_clk = '1' then if (shift = '1') then control_reg_ce_int <= shift_din; end if; end if; end process; control_reg_ce <= control_reg_ce_int; -- bram_ce_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then if(C_NUM_PICOBLAZE > 1) then for i in 0 to C_NUM_PICOBLAZE-2 loop bram_ce_int(i+1) <= bram_ce_int(i); end loop; end if; bram_ce_int(0) <= control_reg_ce_int; end if; end if; end process; -- bram_we_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then bram_we_int <= bram_ce_int(C_NUM_PICOBLAZE-1); end if; end if; end process; -- bram_a_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (shift = '1') then for i in 0 to C_BRAM_MAX_ADDR_WIDTH-2 loop bram_a_int(i+1) <= bram_a_int(i); end loop; bram_a_int(0) <= bram_we_int; end if; end if; end process; -- bram_d_shift : process (shift_clk) begin if shift_clk'event and shift_clk='1' then if (din_load = '1') then bram_d_int <= din; elsif (shift = '1') then for i in 0 to C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-2 loop bram_d_int(i+1) <= bram_d_int(i); end loop; bram_d_int(0) <= bram_a_int(C_BRAM_MAX_ADDR_WIDTH-1); end if; end if; end process; -- bram_ce <= bram_ce_int; bram_we <= bram_we_int; bram_d <= bram_d_int; bram_a <= bram_a_int; shift_dout <= bram_d_int(C_PICOBLAZE_INSTRUCTION_DATA_WIDTH-1); -- end Behavioral; -- -- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; library unisim; use unisim.vcomponents.all; -- entity bscan_logic is generic( C_JTAG_CHAIN : integer :=2; C_BUFFER_SHIFT_CLOCK : boolean := TRUE; C_FAMILY : string := "S6" ); Port ( shift_dout : in std_logic; shift_clk : out std_logic; bram_en : out std_logic; shift_din : out std_logic; bram_strobe : out std_logic; capture : out std_logic; shift : out std_logic ); end bscan_logic; -- architecture low_level_definition of bscan_logic is -- signal drck : std_logic; -- begin -- BSCAN_SPARTAN6_gen: if (C_FAMILY="S6") generate begin BSCAN_BLOCK_inst : BSCAN_SPARTAN6 generic map ( JTAG_CHAIN => C_JTAG_CHAIN) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_en, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => bram_strobe, TDO => shift_dout); end generate BSCAN_SPARTAN6_gen; -- BSCAN_VIRTEX6_gen: if (C_FAMILY="V6") generate begin BSCAN_BLOCK_inst : BSCAN_VIRTEX6 generic map( JTAG_CHAIN => C_JTAG_CHAIN, DISABLE_JTAG => FALSE) port map( CAPTURE => capture, DRCK => drck, RESET => open, RUNTEST => open, SEL => bram_en, SHIFT => shift, TCK => open, TDI => shift_din, TMS => open, UPDATE => bram_strobe, TDO => shift_dout); end generate BSCAN_VIRTEX6_gen; -- BUFG_SHIFT_CLOCK_gen: if (C_BUFFER_SHIFT_CLOCK = TRUE) generate begin -- upload_clock: BUFG port map( I => drck, O => shift_clk); -- end generate BUFG_SHIFT_CLOCK_gen; -- NO_BUFG_SHIFT_CLOCK_gen: if (C_BUFFER_SHIFT_CLOCK = FALSE) generate begin shift_clk <= drck; end generate NO_BUFG_SHIFT_CLOCK_gen; -- end low_level_definition; -- -- ------------------------------------------------------------------------------------ -- -- END OF FILE {name}.vhd -- ------------------------------------------------------------------------------------

mit

viniCerutti/T1-Organizacao-e-Arquitetura-de-Computadores-II

MaterialDeAuxilo/serial/serialinterface.vhd

2

10731

--############################################################################# -- -- Controlador de interface serial com autobaud - versão sem CTS nem RTS! -- -- Descrição: -- Trata-se de uma implementação full-duplex de um controlador de -- interface serial que pode se adaptar à velocidade de transmissão -- do periférico. Ele interage com um processador via handshake assíncrono -- de comunicação, também chamado aqui hospedeiro ou host. A interface -- com o host é de 8 bits, também full-duplex. -- Operação: -- Após a inicialização do controlador (via reset), o periférico deve -- mandar o dado 0x55 (equivalente a 01010101 em binário) na sua velocidade. -- Este valor habilita a interface a ajustar sua velocidade àquela do -- periférico. A velocidade do host não é controlada mas tipicamente deve -- ser bem mais alta que esta, tal como 30MHz/50MHz/100MHz ou até mais alta. -- A interface opera com o relógio do host. -- Assume-se aqui que a velocidade do periférico será tipicamente entre -- 1.200 e 115.200 bits por segundo (ou qualquer velocidade entre estas, -- em múltiplos de 1.200 bps) a faixa de velocidades de uma interface serial -- típica. -- Observações: -- Nada é assumido sobre a necessidade de sincronizar o relógio do host -- e do periférico. -- -- Sinais da Interface -- clock -- clock -- reset -- reset (ativo em 1) -- -- rxd -- envia dados pela serial -- txd -- dados vindos da serial -- -- tx_data -- barramento que contem o byte que vem do pc -- tx_av -- indica que existe um dado disponivel no tx_data -- -- rx_data -- byte a ser transmitido para o pc -- rx_start -- indica byte disponivel no rx_data (ativo em 1) -- rx_busy -- fica em '1' enquando envia ao PC (do rx_start ao fim) -- -- +------------------+ -- | SERIAL |<---- clock -- | +--------+ |<---- reset -- TXD | | | | -- --------->| |=========> tx_data (8bits) -- | | SENDER | | -- | | |---------> tx_av -- | | | | -- Lado | +--------+ | Lado -- Periférico | | Hospedeiro -- | +--------+ | -- | | | | -- RXD | | |<========== rx_data (8bits) -- <---------|RECEIVER|<---------- rx_start -- | | |----------> rx_busy -- | | | | -- | +--------+ | -- +------------------+ -- -- Revisado por Fernando Moraes em 20/maio/2002 -- Alterado por Ney Calazans em Ago/2017 -- --############################################################################# --***************************************************************************** -- Módulo de interface com periférico serial --***************************************************************************** library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity serialinterface is port( clock: in std_logic; reset: in std_logic; rxd: out std_logic; txd: in std_logic; rx_data: in std_logic_vector (7 downto 0); rx_start: in std_logic; rx_busy: out std_logic; tx_data: out std_logic_vector (7 downto 0); tx_av: out std_logic ); end serialinterface; architecture serialinterface of serialinterface is -- sinais do circuito autobaud type Sreg_type is (S1, S2, S3, S4, S5); signal Sreg : Sreg_type; -- Esta é a saída do registrador de estado da MEF autobaud signal ctr0 : STD_LOGIC_VECTOR(16 downto 0); -- conta o número de clocks do -- hospedeiro durante os 4 primeiros tempos em que txd está em 0 durante a -- transmissão de um dado de aferição (0x55) pelo periférico signal PUpEdgeCt : STD_LOGIC_VECTOR (1 downto 0); -- conta o número de bordas de subida -- durante a transmissão de um dado de aferição (0x55) pelo periférico -- sinais de geracao do clock da serial signal host_cycles : STD_LOGIC_VECTOR(13 downto 0); signal counter : STD_LOGIC_VECTOR(13 downto 0); signal serial_clk: STD_LOGIC; -- sinais de recepção signal word, busy: STD_LOGIC_VECTOR (8 downto 0); signal go : STD_LOGIC; -- sinais de transmissão signal regin : STD_LOGIC_VECTOR(9 downto 0); -- 10 bits: start/byte/stop signal resync, r : STD_LOGIC; begin --***************************************************************************** -- MEF Autobaud: Inicialmente, o periférico deve enviar 55H (0101 0101) para -- esta MEF. Esta conta quantos pulsos de clock 'cabem' em cada '0'. -- Logo, conta-se 4 vezes. Para se obter o semi-período, divide-se a -- contagem obtida no estado S5 por 8 (oito). -- -- Atenção: Note-se que a ordem de envio dos bits é do bit menos significativo -- (bit 0 da palavra) para o mais significativo (bit 7). --***************************************************************************** Autobaud_FSM: process (reset, clock) begin if Reset = '1' then Sreg <= S1; -- Estado inicial da máquina de autobaud é S1 PUpEdgeCt <= "00"; -- Contador de bordas de subida em txd inicia com 0 host_cycles <= (OTHERS=>'0'); -- host_cycles é calculado pelo autobaud ctr0 <=(OTHERS=>'0'); -- é o contador de clocks que cabem em quatro -- tempos de 0 bit elsif clock'event and clock = '1' then case Sreg is when S1 => if txd = '0' then -- a primeira descida de txd é o start bit, Sreg <= S2; -- que dispara o cálculo da MEF autobaud ctr0 <= (OTHERS=>'0'); end if; when S2 => ctr0 <= ctr0 + 1; -- Incrementa o número de pulsos de clock -- do host que vem do periférico durante a transmissão -- do dado de aferição (0x55) if txd = '1' then Sreg <= S3; PUpEdgeCt <= PUpEdgeCt + '1'; end if; when S3 => if PUpEdgeCt /= "00" and txd = '0' then Sreg <= S2; elsif PUpEdgeCt = "00" and txd = '0' then Sreg <= S4; end if; when S4 => if txd = '1' then -- espera em S4 até aparecer o stop bit (txd='1') Sreg <= S5; -- Quando isto acontece MEF autobaud concluiu. end if; when S5 => Sreg <= S5; -- Em S5, armazena o número de ciclos contados host_cycles <= ctr0(16 downto 3); -- dividido por 8 end case; end if; end process; --***************************************************************************** -- SENDER --***************************************************************************** -- Processo de envio de dados do periférico ao hospedeiro. -- Sinais: txd (periférico) e tx_data e tx_av (hospedeiro) -- Registrador de deslocamento de 10 bits que lê o dado vindo da serial. process (resync, serial_clk) begin if resync = '1' then regin <= (others=>'1'); -- inicializa todos os bits do registrador com '1' elsif serial_clk'event and serial_clk='1' then regin <= txd & regin(9 downto 1); -- bit vindo do periférico -- entra pela esquerda do registrador de deslocamento end if; end process; -- O processo abaixo detecta o start bit, gerando o sinal de resincronismo -- resync. O sinal host_cycles em 0 funciona como um reset do processo. process (clock, host_cycles) begin if host_cycles=0 then r <= '0'; resync <= '1'; tx_data <= (others=>'0'); -- zera os 8 bits de tx_data tx_av <= '0'; elsif clock'event and clock='1' then if r='0' and txd='0' then --- start bit r <= '1'; resync <= '1'; tx_av <= '0'; elsif r='1' and regin(0)='0' then --- start bit chegou no último bit r <= '0'; tx_data <= regin(8 downto 1); -- tx_data recebe os bits de dados recebidos tx_av <= '1'; -- ativa o sinal de dado discponível else resync <= '0'; tx_av <= '0'; end if; end if; end process; --***************************************************************************** -- RECEIVER - Sinais rxd (periférico), rx_data, rx_start, rx_busy (hospedeiro) --***************************************************************************** -- Processo de geração do clock para a transmissão serial (serial_clk). -- De tempos em tempos este é resincronizado, para ajuste da recepção -- dos dados provenientes do hospedeiro. process(resync, clock) begin if resync='1' then counter <= (0=>'1', others=>'0'); -- escreve 1 em counter serial_clk <='0'; -- ressincroniza o clock da serial elsif clock'event and clock='0' then if counter = host_cycles then -- aguarda que se passem host_cycles serial_clk <= not serial_clk; -- gera borda sincronizada counter <= (0=>'1', others=>'0'); -- escreve 1 em counter else counter <= counter + 1; -- maior parte das vezes passa aqui end if; end if; end process; -- Registrador de deslocamento - fica colocando '1' na linha de dados. -- Quando o usuário requer dados (pulso em rx_start) coloca-se o start bit e o -- byte a ser transmitido process(rx_start, reset, serial_clk) begin if rx_start='1' or reset='1' then go <= rx_start ; rx_busy <= rx_start ; word <= (others=>'1'); -- todos os 9 bits em '1' inicialmente busy <= (others=>'0'); -- busy, inicialmente livre p/ receber 9 bits elsif serial_clk'event and serial_clk ='1' then go <= '0'; -- desce o go um ciclo depois if go='1' then word <= rx_data & '0'; -- armazena o byte que é enviado à serial busy <= (8=>'0', others=>'1'); else word <= '1' & word(8 downto 1); -- desloca para a esquerda word busy <= '0' & busy(8 downto 1); -- e busy rx_busy <= busy(0); -- rx_busy fica ocupado enquanto enviando start e bits -- de dados end if; end if; end process; rxd <= word(0); -- bit de saída, que vai para o periférico. Pode mudar a cada -- borda de serial_clk end serialinterface;

mit

Main-Project-MEC/Systolic-Processor-On-FPGA

Misc/Opencores/c16_latest.tar/c16/tags/V10/vhdl/input_output.vhd

1

5838

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.cpu_pack.ALL; entity input_output is PORT ( CLK_I : in std_logic; T2 : in std_logic; SWITCH : in STD_LOGIC_VECTOR (9 downto 0); HALT : in STD_LOGIC; SER_IN : in STD_LOGIC; SER_OUT : out STD_LOGIC; -- temperature TEMP_SPO : in STD_LOGIC; TEMP_SPI : out STD_LOGIC; TEMP_CE : out STD_LOGIC; TEMP_SCLK : out STD_LOGIC; LED : out STD_LOGIC_VECTOR (7 downto 0); CLR : out STD_LOGIC; -- input/output IO_RD : in std_logic; IO_WR : in std_logic; IO_ADR : in std_logic_vector( 7 downto 0); IO_RDAT : out std_logic_vector( 7 downto 0); IO_WDAT : in std_logic_vector( 7 downto 0); INT : out STD_LOGIC ); end input_output; architecture Behavioral of input_output is COMPONENT temperature PORT( CLK_I : IN std_logic; T2 : IN std_logic; CLR : IN std_logic; TEMP_SPO : IN std_logic; DATA_OUT : OUT std_logic_vector(7 downto 0); TEMP_SPI : OUT std_logic; TEMP_CE : OUT std_logic; TEMP_SCLK : OUT std_logic ); END COMPONENT; COMPONENT uart_baudgen PORT( CLK_I : IN std_logic; T2 : IN std_logic; CLR : IN std_logic; RD : IN std_logic; WR : IN std_logic; TX_DATA : IN std_logic_vector(7 downto 0); RX_SERIN : IN std_logic; TX_SEROUT : OUT std_logic; RX_DATA : OUT std_logic_vector(7 downto 0); RX_READY : OUT std_logic; TX_BUSY : OUT std_logic ); END COMPONENT; signal L_IO_ADR : std_logic_vector(7 downto 0); signal IO_RD_SERIAL : std_logic; signal IO_WR_SERIAL : std_logic; signal RX_READY : std_logic; signal TX_BUSY : std_logic; signal RX_DATA : std_logic_vector(7 downto 0); signal TEMP_DO : std_logic_vector(7 downto 0); signal FLAG : std_logic; signal LCLR : std_logic; signal C1_N, C2_N : std_logic; -- switch debounce, active low signal RX_INT_ENABLED : std_logic; signal TX_INT_ENABLED : std_logic; signal TIM_INT_ENABLED : std_logic; signal TIMER_INT : std_logic; signal TIMER : std_logic_vector(14 downto 0); signal CLK_COUNT : std_logic_vector(15 downto 0); signal CLK_COUNT_EN : std_logic; signal CLK_HALT_MSK : std_logic; signal CLK_HALT_VAL : std_logic; begin tempr: temperature PORT MAP( CLK_I => CLK_I, T2 => T2, CLR => LCLR, DATA_OUT => TEMP_DO, TEMP_SPI => TEMP_SPI, TEMP_SPO => TEMP_SPO, TEMP_CE => TEMP_CE, TEMP_SCLK => TEMP_SCLK ); uart: uart_baudgen PORT MAP( CLK_I => CLK_I, T2 => T2, CLR => LCLR, RD => IO_RD_SERIAL, WR => IO_WR_SERIAL, TX_DATA => IO_WDAT, TX_SEROUT => SER_OUT, RX_SERIN => SER_IN, RX_DATA => RX_DATA, RX_READY => RX_READY, TX_BUSY => TX_BUSY ); CLR <= LCLR; INT <= (RX_INT_ENABLED and RX_READY) or (TX_INT_ENABLED and not TX_BUSY) or (TIM_INT_ENABLED and TIMER_INT); -- IO read process -- process(L_IO_ADR, IO_RD, IO_WR, RX_DATA, TEMP_DO, SWITCH, TIM_INT_ENABLED, TIMER_INT, TX_INT_ENABLED, TX_BUSY, RX_INT_ENABLED, RX_READY) begin IO_RD_SERIAL <= '0'; IO_WR_SERIAL <= '0'; case L_IO_ADR is when X"00" => IO_RDAT <= RX_DATA; IO_RD_SERIAL <= IO_RD; IO_WR_SERIAL <= IO_WR; when X"01" => IO_RDAT <= '0' & (TIM_INT_ENABLED and TIMER_INT) & (TX_INT_ENABLED and not TX_BUSY) & (RX_INT_ENABLED and RX_READY) & '0' & TIMER_INT & TX_BUSY & RX_READY; when X"02" => IO_RDAT <= TEMP_DO; when X"03" => IO_RDAT <= SWITCH(7 downto 0); when X"05" => IO_RDAT <= CLK_COUNT(7 downto 0); when others => IO_RDAT <= CLK_COUNT(15 downto 8); end case; end process; -- IO write and timer process -- process(CLK_I) begin if (rising_edge(CLK_I)) then if (T2 = '1') then L_IO_ADR <= IO_ADR; if (LCLR = '1') then LED <= X"00"; RX_INT_ENABLED <= '0'; TX_INT_ENABLED <= '0'; TIM_INT_ENABLED <= '0'; TIMER_INT <= '0'; TIMER <= "000" & X"000"; else if (IO_WR = '1') then case L_IO_ADR is when X"00" => -- handled by uart when X"01" => -- handled by uart when X"02" => LED <= IO_WDAT; when X"03" => RX_INT_ENABLED <= IO_WDAT(0); TX_INT_ENABLED <= IO_WDAT(1); TIM_INT_ENABLED <= IO_WDAT(2); when X"04" => TIMER_INT <= '0'; when X"05" => CLK_COUNT_EN <= '1'; CLK_COUNT <= X"0000"; CLK_HALT_VAL <= IO_WDAT(0); CLK_HALT_MSK <= IO_WDAT(1); when X"06" => CLK_COUNT_EN <= '0'; when others => end case; end if; TIMER <= TIMER + 1; if (TIMER = 19999) then -- 1 ms TIMER_INT <= '1'; TIMER <= "000" & X"000"; end if; if (CLK_COUNT_EN = '1' and (HALT and CLK_HALT_MSK ) = CLK_HALT_VAL) then CLK_COUNT <= CLK_COUNT + 1; end if; end if; end if; end if; end process; -- reset debounce process -- process(CLK_I) begin if (rising_edge(CLK_I)) then if (T2 = '1') then -- switch debounce if (SWITCH(8) = '1' or SWITCH(9) = '1') then LCLR <= '1'; C2_N <= '0'; C1_N <= '0'; else LCLR <= not C2_N; C2_N <= C1_N; C1_N <= '1'; end if; end if; end if; end process; end Behavioral;

mit

scarter93/RSA-Encryption

montgomery_multiplier.vhd

1

2891

-- Entity name: montgomery_multiplier -- Author: Stephen Carter -- Contact: [email protected] -- Date: March 10th, 2016 -- Description: Performs modular multiplication. See paper for more information. Designed for use with RSA Encryption. library ieee; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity montgomery_multiplier is Generic(WIDTH_IN : integer := 8 ); Port( A : in unsigned(WIDTH_IN-1 downto 0); B : in unsigned(WIDTH_IN-1 downto 0); N : in unsigned(WIDTH_IN-1 downto 0); latch : in std_logic; clk : in std_logic; reset : in std_logic; data_ready : out std_logic; M : out unsigned(WIDTH_IN-1 downto 0) ); end entity; architecture behavioral of montgomery_multiplier is -- Signals Signal M_temp : unsigned(WIDTH_IN+1 downto 0) := (others => '0'); Signal state : integer := 0; Signal count : integer := 0; Signal B_reg : unsigned(WIDTH_IN-1 downto 0) := (others => '0'); Signal A_reg : unsigned(WIDTH_IN-1 downto 0) := (others => '0'); Signal B_zeros : unsigned(WIDTH_IN-1 downto 0) := (others => '0'); Signal N_temp : unsigned(WIDTH_IN-1 downto 0); Begin -- Process to perform mod mult operation compute_M : Process(clk,latch,reset) Begin if reset = '0' and rising_edge(clk) then case state is when 0 => -- latch data when latch high if latch = '1' then data_ready <= '0'; M_temp <= (others => '0'); count <= 0; B_reg <= B; A_reg <= A; N_temp <= N; state <= 1; end if; when 1 => -- perform appropriate add and shift -- check to see if we add B or not if A_reg(0) = '1' then -- check to see if we add N and B if (M_temp(0) xor B_reg(0)) = '1' then M_temp <= unsigned(shift_right(unsigned(M_temp + B_reg + N), integer(1))); else M_temp <= unsigned(shift_right(unsigned(M_temp + B_reg), integer(1))); end if; else --check to see if we need to add modulus if M_temp(0) = '1' then M_temp <= unsigned(shift_right(unsigned(M_temp + N), integer(1))); else M_temp <= unsigned(shift_right(unsigned(M_temp), integer(1))); end if; end if; -- check to see if multiply is complete if N_temp = to_unsigned(integer(1), WIDTH_IN) then state <= 2; else state <= 1; end if; -- Update the A and N value used to update values N_temp <= unsigned(shift_right(unsigned(N_temp), integer(1))); A_reg <= unsigned(shift_right(unsigned(A_reg), integer(1))); when 2 => --update output values and return to default state if( M_temp > N) then M <= M_temp(WIDTH_IN-1 downto 0) - N; else M <= M_temp(WIDTH_IN-1 downto 0); end if; data_ready <= '1'; state <= 0; when others => state <= 0; end case; end if; end Process; end architecture;

mit

timtian090/Playground

UVM/UVMExamples/mod11_functional_coverage/class_examples/alu_tb/std_ovl/vhdl93/ovl_never_rtl.vhd

1

4229

-- Accellera Standard V2.3 Open Verification Library (OVL). -- Accellera Copyright (c) 2008. All rights reserved. library ieee; use ieee.std_logic_1164.all; use work.std_ovl.all; use work.std_ovl_procs.all; architecture rtl of ovl_never is constant assert_name : string := "OVL_NEVER"; constant path : string := rtl'path_name; signal reset_n : std_logic; signal clk : std_logic; signal fatal_sig : std_logic; signal test_expr_x01 : std_logic; shared variable error_count : natural; begin test_expr_x01 <= to_x01(test_expr); ------------------------------------------------------------------------------ -- Gating logic -- ------------------------------------------------------------------------------ reset_gating : entity work.std_ovl_reset_gating generic map (reset_polarity => reset_polarity, gating_type => gating_type, controls => controls) port map (reset => reset, enable => enable, reset_n => reset_n); clock_gating : entity work.std_ovl_clock_gating generic map (clock_edge => clock_edge, gating_type => gating_type, controls => controls) port map (clock => clock, enable => enable, clk => clk); ------------------------------------------------------------------------------ -- Initialization message -- ------------------------------------------------------------------------------ ovl_init_msg_gen : if (controls.init_msg_ctrl = OVL_ON) generate ovl_init_msg_proc(severity_level, property_type, assert_name, msg, path, controls); end generate ovl_init_msg_gen; ------------------------------------------------------------------------------ -- Assertion - 2-STATE -- ------------------------------------------------------------------------------ ovl_assert_on_gen : if (ovl_2state_is_on(controls, property_type)) generate ovl_assert_p : process (clk) begin if (rising_edge(clk)) then fatal_sig <= 'Z'; if (reset_n = '0') then fire(0) <= '0'; elsif (to_x01(test_expr_x01) = '1') then fire(0) <= '1'; ovl_error_proc("Test expression is not FALSE", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(0) <= '0'; end if; end if; end process ovl_assert_p; ovl_finish_proc(assert_name, path, controls.runtime_after_fatal, fatal_sig); end generate ovl_assert_on_gen; ovl_assert_off_gen : if (not ovl_2state_is_on(controls, property_type)) generate fire(0) <= '0'; end generate ovl_assert_off_gen; ------------------------------------------------------------------------------ -- Assertion - X-CHECK -- ------------------------------------------------------------------------------ ovl_xcheck_on_gen : if (ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate ovl_xcheck_p : process (clk) begin if (rising_edge(clk)) then fatal_sig <= 'Z'; if (reset_n = '0') then fire(1) <= '0'; elsif (ovl_is_x(test_expr_x01)) then fire(1) <= '1'; ovl_error_proc("test_expr contains X, Z, U, W or -", severity_level, property_type, assert_name, msg, path, controls, fatal_sig, error_count); else fire(1) <= '0'; end if; end if; end process ovl_xcheck_p; end generate ovl_xcheck_on_gen; ovl_xcheck_off_gen : if (not ovl_xcheck_is_on(controls, property_type, OVL_IMPLICIT_XCHECK)) generate fire(1) <= '0'; end generate ovl_xcheck_off_gen; ------------------------------------------------------------------------------ -- Coverage -- ------------------------------------------------------------------------------ -- No coverage for this checker. fire(2) <= '0'; end architecture rtl;

mit

Main-Project-MEC/Systolic-Processor-On-FPGA

Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/uart.vhd

3

1641

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; entity uart is PORT( CLK_I : in std_logic; RST_I : in std_logic; CE_16 : in std_logic; TX_DATA : in std_logic_vector(7 downto 0); TX_FLAG : in std_logic; TX_SEROUT : out std_logic; TX_FLAGQ : out std_logic; RX_SERIN : in std_logic; RX_DATA : out std_logic_vector(7 downto 0); RX_FLAG : out std_logic ); end uart; architecture Behavioral of uart is COMPONENT uart_tx PORT( CLK_I : IN std_logic; RST_I : IN std_logic; CE_16 : IN std_logic; DATA : IN std_logic_vector(7 downto 0); DATA_FLAG : IN std_logic; SER_OUT : OUT std_logic; DATA_FLAGQ : OUT std_logic ); END COMPONENT; COMPONENT uart_rx PORT( CLK_I : IN std_logic; RST_I : IN std_logic; CE_16 : IN std_logic; SER_IN : IN std_logic; DATA : OUT std_logic_vector(7 downto 0); DATA_FLAG : OUT std_logic ); END COMPONENT; begin tx: uart_tx PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16, DATA => TX_DATA, DATA_FLAG => TX_FLAG, SER_OUT => TX_SEROUT, DATA_FLAGQ => TX_FLAGQ ); rx: uart_rx PORT MAP( CLK_I => CLK_I, RST_I => RST_I, CE_16 => CE_16, DATA => RX_DATA, SER_IN => RX_SERIN, DATA_FLAG => RX_FLAG ); end Behavioral;

mit

Main-Project-MEC/Systolic-Processor-On-FPGA

ISE Design Files/HAM/HAM.vhd

1

441

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity HAM is Port ( X : in STD_LOGIC; Y : in STD_LOGIC; B : in STD_LOGIC; Sout : out STD_LOGIC; Cout : out STD_LOGIC); end HAM; architecture HA_arch of HAM is component HA port(A,B: in STD_LOGIC;Sout,Cout: out STD_LOGIC); end component; signal A: STD_LOGIC; begin A <= X AND Y; H1: HA port map(A,B,Sout,Cout); end HA_arch;

mit

timtian090/Playground

UVM/UVMExamples/mod01_sv_for_vhdlers/SystemVerilog_for_VHDL_Engineers_Primer/primer_examples/processes/vhdl_adder.vhd

2

949

LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.STD_LOGIC_UNSIGNED.all; ENTITY adder IS PORT( A : IN std_logic_vector ( 7 DOWNTO 0 ); B : IN std_logic_vector ( 7 DOWNTO 0 ); clk : IN std_logic; rst_n : IN std_logic; carry : OUT std_logic; sum : OUT std_logic_vector ( 7 DOWNTO 0 ) ); END adder ; ARCHITECTURE rtl OF adder IS signal sum_int : std_logic_vector (8 downto 0); signal A8 : std_logic_vector (8 downto 0); signal B8 : std_logic_vector (8 downto 0); BEGIN A8 <= "0" & A; B8 <= "0" & B; sum_int <= A8 + B8; adder: process (clk, rst_n) begin if rst_n = '0' then carry <= '0'; sum <= "00000000"; elsif clk'event and clk = '1' then carry <= sum_int(8); sum <= sum_int(7 downto 0); end if; end process adder; END ARCHITECTURE rtl;

mit

Main-Project-MEC/Systolic-Processor-On-FPGA

ISE Design Files/DPU_array_matrix_multiplication_3/DPU_array_matrix_multiplication_3.vhd

1

2268

library ieee; use ieee.std_logic_1164.all; entity DPU_array_matrix_multiplication_3 is port ( A0 : in STD_LOGIC_VECTOR (3 downto 0); A1 : in STD_LOGIC_VECTOR (3 downto 0); A2 : in STD_LOGIC_VECTOR (3 downto 0); B0 : in STD_LOGIC_VECTOR (3 downto 0); B1 : in STD_LOGIC_VECTOR (3 downto 0); B2 : in STD_LOGIC_VECTOR (3 downto 0); CLK: in STD_LOGIC; clear: in STD_LOGIC; -- preset: in STD_LOGIC_VECTOR; O0 : out STD_LOGIC_VECTOR (9 downto 0); O1 : out STD_LOGIC_VECTOR (9 downto 0); O2 : out STD_LOGIC_VECTOR (9 downto 0); O3 : out STD_LOGIC_VECTOR (9 downto 0); O4 : out STD_LOGIC_VECTOR (9 downto 0); O5 : out STD_LOGIC_VECTOR (9 downto 0); O6 : out STD_LOGIC_VECTOR (9 downto 0); O7 : out STD_LOGIC_VECTOR (9 downto 0); O8 : out STD_LOGIC_VECTOR (9 downto 0)); end DPU_array_matrix_multiplication_3; architecture DPU_array_matrix_multiplication_3_arch of DPU_array_matrix_multiplication_3 is component DPU_matrix_multiplication port ( Ain : in STD_LOGIC_VECTOR (3 downto 0); Bin : in STD_LOGIC_VECTOR (3 downto 0); CLK : in STD_LOGIC; clear: in STD_LOGIC; Aout : out STD_LOGIC_VECTOR (3 downto 0); Bout : out STD_LOGIC_VECTOR (3 downto 0); Result : out STD_LOGIC_VECTOR (9 downto 0)); end component; signal S01,S12,S03,S14,S25,S34,S45,S36,S47,S58,S67,S78 : STD_LOGIC_VECTOR (3 downto 0); begin DPU0: DPU_matrix_multiplication port map(A0,B0,CLK,clear,S03,S01,O0); DPU1: DPU_matrix_multiplication port map(A1,S01,CLK,clear,S14,S12,O1); DPU2: DPU_matrix_multiplication port map(A2,S12,CLK,clear,S25,open,O2); DPU3: DPU_matrix_multiplication port map(S03,B1,CLK,clear,S36,S34,O3); DPU4: DPU_matrix_multiplication port map(S14,S34,CLK,clear,S47,S45,O4); DPU5: DPU_matrix_multiplication port map(S25,S45,CLK,clear,S58,open,O5); DPU6: DPU_matrix_multiplication port map(S36,B2,CLK,clear,open,S67,O6); DPU7: DPU_matrix_multiplication port map(S47,S67,CLK,clear,open,S78,O7); DPU8: DPU_matrix_multiplication port map(S58,S78,CLK,clear,open,open,O8); end DPU_array_matrix_multiplication_3_arch;

mit

Main-Project-MEC/Systolic-Processor-On-FPGA

ISE Design Files/FA/FA_tb.vhd

1

1780

library ieee; use ieee.std_logic_1164.all; entity FA_tb is end FA_tb; architecture tb of FA_tb is component FA is port( A, B, Cin : in std_logic; Sout, Cout : out std_logic); end component; signal A, B, Cin, Sout, Cout : std_logic; begin mapping: FA port map(A, B, Cin, Sout, Cout); --concurrent processes process begin Cin <= '0'; wait for 5 ns; Cin <= '1'; wait for 5 ns; end process; process variable errCnt : integer := 0; begin --TEST 1 A <= '0'; B <= '1'; wait for 10 ns; assert(Sout = '0') report "Sout error 1" severity error; assert(Cout = '1') report "Cout error 1" severity error; if(Sout /= '1' or Cout /= '0') then errCnt := errCnt + 1; end if; --TEST 2 A <= '1'; B <= '1'; wait for 10 ns; assert(Sout = '1') report "Sout error 2" severity error; assert(Cout = '1') report "Cout error 2" severity error; if(Sout /= '0' or Cout /= '1') then errCnt := errCnt + 1; end if; --TEST 3 A <= '1'; B <= '0'; wait for 10 ns; assert(Sout = '0') report "Sout error 3" severity error; assert(Cout = '1') report "Cout error 3" severity error; if(Sout /= '1' or Cout /= '0') then errCnt := errCnt + 1; end if; ---- SoutMARY ---- if(errCnt = 0) then assert false report "Success!" severity note; else assert false report "Faillure!" severity note; end if; end process; end tb; ------------------------------------------------------------- configuration cfg_tb of FA_tb is for tb end for; end cfg_tb; ----------------------------------------------------------END ----------------------------------------------------------END

mit

Main-Project-MEC/Systolic-Processor-On-FPGA

Misc/Opencores/c16_latest.tar/c16/trunk/vhdl/select_yy.vhd

3

2763

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.cpu_pack.ALL; entity select_yy is Port( SY : in std_logic_vector( 3 downto 0); IMM : in std_logic_vector(15 downto 0); QUICK : in std_logic_vector( 3 downto 0); RDAT : in std_logic_vector( 7 downto 0); RR : in std_logic_vector(15 downto 0); YY : out std_logic_vector(15 downto 0) ); end select_yy; architecture Behavioral of select_yy is function b4(A : std_logic) return std_logic_vector is begin return A & A & A & A; end; function b8(A : std_logic) return std_logic_vector is begin return b4(A) & b4(A); end; begin -- bits 1..0 -- s_1_0: process(SY, IMM(1 downto 0), QUICK(1 downto 0), RDAT(1 downto 0), RR(1 downto 0)) begin case SY is when SY_I16 | SY_SI8 | SY_UI8 => YY(1 downto 0) <= IMM (1 downto 0); when SY_RR => YY(1 downto 0) <= RR (1 downto 0); when SY_SQ | SY_UQ => YY(1 downto 0) <= QUICK(1 downto 0); when SY_SM | SY_UM => YY(1 downto 0) <= RDAT (1 downto 0); when others => YY(1 downto 0) <= SY (1 downto 0); end case; end process; -- bits 3..2 -- s_3_2: process(SY, IMM(3 downto 2), QUICK(3 downto 2), RDAT(3 downto 2), RR(3 downto 2)) begin case SY is when SY_I16 | SY_SI8 | SY_UI8 => YY(3 downto 2) <= IMM (3 downto 2); when SY_RR => YY(3 downto 2) <= RR (3 downto 2); when SY_SQ | SY_UQ => YY(3 downto 2) <= QUICK(3 downto 2); when SY_SM | SY_UM => YY(3 downto 2) <= RDAT (3 downto 2); when others => YY(3 downto 2) <= "00"; end case; end process; -- bits 7..4 -- s_7_4: process(SY, IMM(7 downto 4), QUICK(3), RDAT(7 downto 4), RR(7 downto 4)) begin case SY is when SY_I16 | SY_SI8 | SY_UI8 => YY(7 downto 4) <= IMM (7 downto 4); when SY_RR => YY(7 downto 4) <= RR (7 downto 4); when SY_SQ => YY(7 downto 4) <= b4(QUICK(3)); when SY_SM | SY_UM => YY(7 downto 4) <= RDAT (7 downto 4); when others => YY(7 downto 4) <= "0000"; end case; end process; -- bits 15..8 -- s_15_8: process(SY, IMM(15 downto 7), QUICK(3), RDAT(7), RR(15 downto 8)) begin case SY is when SY_I16 => YY(15 downto 8) <= IMM (15 downto 8); when SY_SI8 => YY(15 downto 8) <= b8(IMM(7)); when SY_RR => YY(15 downto 8) <= RR(15 downto 8); when SY_SQ => YY(15 downto 8) <= b8(QUICK(3)); when SY_SM => YY(15 downto 8) <= b8(RDAT(7)); when others => YY(15 downto 8) <= "00000000"; end case; end process; end Behavioral;

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd

11

136312

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd

11

136312

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd

11

136312

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_0/blk_mem_gen_v8_2/hdl/blk_mem_gen_generic_cstr.vhd

11

136312

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block VZz3gA1OEAo0GderLFN1vAy9VjW6GHfNIvzuIsiYL4pObhfFuD92v4JXddeUi8Mb9uiE9mWeniAP 6axurY4i4Q== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block V/FHqGcuHkuQA/mXo5Z6hby0fYqv5HdbLwzSf6RRkitLROmzZ7kuem6lbOkkdKPEq7el37wV7LLB lS7Z0SpN6+NFFxvpJwmAXsxAlmNILJUkYM2qy3RGTd18wZzOLOD3LW/CxHw6U/8KDCIE0QPR7gPZ MonMc1sdRumiZxCH6p8= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block MhNvJyoQvuBNKA9BY4qs8iuN6gsubuCwSLP9+9HALR7b3OaTr2NNpcJWL5Z2I5y4M70GpNsDLMPN 9x6xxl6dDjiJRZECV9SwEWPnMOiCoaB+AsXeT7vUUtbJNztLP+IJM8m4GxoaXa82G7GmovIGBV/w 4I8s3WETrKiD+AzsZGw7+K2Rv9qW0odg0raG3Nf3cg0Jj3QVcFHpKgJBjvYUZ5EulGHRyU9ez7w6 y6RJfN1K1RY6s4t66rCqdUJUgL6zuBnooS8J3bfZMDJBU02FgqcqfaGv3VkgxhqebXTwUHH6dt05 XvK5nC5Fa8ivOVaKTCai6uvlheV1U35wjc4UaA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block rQ7j2Mp14x4heUZNN1sxi590D3svKV0yVp+Er26zbuDVzZY2es4L4i8KGLZDZgWNlJ8KygSbSSmu AMrgF/9J6L45adeffFOhMlUSE3dKMc9uVglmHX8+NJzpjX5dYFIRPf6r2tIEsYL669q5VkCA/E1w OYrkIhxgyBWc5KA4bdA= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block XSzu0gCO60UCezzrasTnl1P56lBSmB5WoyDnA9GcGthkxKlRJzbd5G8JQBmzgeQ/X31AQOI/hSSR 0KBXcFTa4p7F8sfh56g8EO9ICdlNGlmK5lwucB30KgGIDn+D16gBT1WrdmuBInOK9hVfZpKxtH1C vNGY4AZdGokYQo2eE7iEU2Odq01QNto1qz8mklUCahoHRhjnyHMerh56TbVU4kjgnoVqlDhf67S9 1gulUL5I72iVvZt4D9d+OrnhSSYIHIsZQNCxGgLPpQh16jelRUvUb8ApjVQqxWWD45oYQxzToKeP cjW5Qj2B5xwGT/QE3ivcnwGi9iOvHlavt386EQ== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 99168) `protect data_block +SfTMUYhoEZEGaPCN6exMh8+5eINx+9h8XenvZKnYT7lUL+SKIud5B7JP92jml/r022nFvj8ljEq tNdfF9RCQGGTHNZFMjYkXDv3AR66TL+QZKuZLZWXeNcUYnnD9SKG2ktEPEeV+OTH+i17D0dQ4dc8 bTXU52lZhc8JkWmQWsu8ynkKhqD6BWq3HkGOlzar6pn+tCzd5YncrCeF+VThPMaAk5jH3m3g/w2q shWfF6W50/ZK6pWfVJaEKW7U7W0hPjwY7YHIv6wk/4Jcp8Pwd541tlwVviXKwQjgLbi/+ya/aw5Q vYOzlQORcZtlqJ/CeO1zAkrkbAcuC9SpMsBws6kEA4yPxooi1EGUbBxQmv2usaJqoZPrUC4AM3s7 XVmpRjfyfU+u6hiNSKCJAtNK8Pf/ZVdOKrTF0UJegfeiZipCFWYlhEa6Vw0cve18V7/celtgL6Qi 02dFMt1MnlCIdiKBeINSQhseONklNm1inHBg2lrRZ5XuOdwt6AR8DLy5LFbzz/XotZjUj9vBDLZ2 8k58WFKvW/AWi0Ljwb27U+NmazCXYCgQH8iPRWybUx6am7q/HFbgCTWVa86R3uAGU8Kz7w/SiIGA ClEqs+5bCxCY9YpO3yTjQn7JNsxMI9G7lnyf0fwoAYJYILxPy3de4EuZX4H4j/F1DKCkUZvShPC3 ng9lu/LnCGNXEdDmP+kqccxCtS/ya/YdcnB0JXG2jEDT/XhPYof02HdktePZVeGgc/+4TxPYBBOS YkYFkpf2HK4bAOWcjQ0/YMGV1WSGkuheG0ZOAxxJ6QnZ/2u0i7FYir6C8ndwT/WNLifbO8aZentK 2R/AcYVghfUw5wkqdhl1payu2drwWUDm0YaYwdQOT+E9YK0srOSEVIU2Wb3/33y+ERafmZ2VMT+9 Vp8XPrDUnJbmDnK3TfxLCXjyh5gUpgnPk0dSInFh0h9gT4dXxO1nRA5535HNxGNq+JOxZJlgrrFm Tac2CUXoyV7aP0Xe14PldjKnkWjCTIYLtrPgf/QCpSatYDczQQxPhoopicnFvRoIe+HazUC21kVL EsQ2TL6enQduIEXH+eKlEG2Yj/9m3X2d0GaRre5K/fYk26T18/HQ5cYn947zFNAZVa72+QEm9fwg qFuCAfWCy5UFtyUTLsRnSceaWF4fQa4hyE9sJNbj3RCLR1MO1OU+NyP8LCX2SVST+Hh9dIzXWfjR LtI09v52T55kfbdxy+5YPssCOJwB9+KoUhRmBbVb2oHvE7FnYkW15aa8Uw6F6uBpSBL07NwsYwZR bbuccv80jiutzHh0KsRxI+JHSj24nUfZ0ofM17xOeacEqnEsACqKoKty2SkeTb34Dng4ApYlG/rH upureRjAqyOtsFzYq1SxsowaOOcXj1+Iw66GWrs7Bb+dwR+uYhvStKhJjrqigEFeCDZcx687OEkw SLnCBUM1Jw2POetGI8/b3N1Gz0viUR1dgCOMo09NLXUm6aQkYgW9B3jjqS6HRjG4VV9DS3kohLuS HP3TlD4vytI3+uaMPHfLi14oWOeYfem79e2HuqoUbR6FoUWetnbGJGZe2iWCWg2SINTGFxm00Onc xLtWRCGasWYBw7j+ZkrHQWiX0k3XIneS+9jUPuq/TegyrbMwzCzwJmvEO/XdXsyuawoTLet7rqhv /S9YDuQgDFQ1A17sWax1RHLy5o1ssg9RBw58LVCBgqGDJLzq+jrakMiPc25EngaDubDWZhU+6Dks HRYt2tfBq+3rqdiyd6RSllBQWMo+ErHVfNpHe6/rf90TNWE8zSSGOvzHn3ssl5SEbdvknDMaWszR 9xJ/EhqWDbBRaW9OnSNBnUHHeXCWCr0Q7tbGAW3DFJO9/pM7rw46r+HuxDXQ83YPI/6jRkJWklvg cOt9/PfrplkSXryD4Mk0mz7XD6ZkRd3UR3gkGBV6TbMrQJjaokzGJidNzBtozgcKBUv2ZyO2UYvY r1Z3KwyfTVjRo8yC7EtVi5bR2pVuQnxpawgCUqsdXHJEXSNUTyIBJuidg8A9rmRZmbPFCbBvflrp vR06UPQuzhkPM0MP6OMUdb4bWtCl0CoF+7gCfST89acZ4J8l/jyxZgqmozk2/rY8eMyQZoxmuZI9 EKfARwISgTIblcj2A9a35MlCnCuE6EGHGYxj7g+2qiVm43pDl4LUhie/uY0haizTya7qhEWCMpbM DHKKeYgAzo5eHPSz/3E35PBqKqhsDxF+2jQvD8TOQudka5xIsbFyYiKIGuEVKPDfwvFr4Wb6geuZ vh6sK/gef736VMq+NMwhttBZWWblU++N59/kn9QhHjqtXemIPmNjFLTY1551+K2Vp/ReLf/ItugD 2yyELVibvL48exJDhzxlGQSEUL4OrEUzZhZNVijIh2POY841oo4oDbdTpTeO9rqnaPuBNwG0SGjY aG+x/OVSuvkoMOP7ltEJ8L6frcxhcIFBaCb1mstlTxHxJGV7EuUW6EHMgHs8WUdUCqTygpZ5HETx XmRM2w8Hp1RJoNUvVoCU8BlmCLxwxgPQyLusCTMf9QU2vQrehhr168+TWKAFvBbOfeWJsXTmKmPd KoTb3eMQdOAHIKtMXDB+lcQ5/gtr1KrVw2GEaSX1azNWcm15lKlGXwwGK0xpNXwuUwr3B+RXuHB9 khcHu6t89MuCv12y8ScdMdVjcGIP2wGYBpU7ZWZPZN4HL4vOA0Arly72YngI6ncA8pK2i9F6Hddi LQaYzWJXVq0pCd8Vxi2UtRE3/2cp9IftpROGb3tOkkBSyQlZhMEiHYro8Uhr9Xq3FiseLszdQQMx 2HttMaRSo6X2Xw5Byh/obUeCOHvOFjvd77tWi2ZjxWxO3lIfrd5uHJRkQeeayCbkDt3niDXDmfBn 9wZsGelQgnYjd8TgHTqeqt+18C//bJ+C2ZNzhSgmDKCHbQU5r7j8QkW4bJqTcLidcfmejGwYX6TG sHT1PdUQtV44faSaQYQBlYYpnWgB18nla+F7L5wt/HLXp7dfNXSTnKK70S7wYKbOuK71BJXnVV6R tBNKmwBh/wS5EMWfkK8kcfkK0twlzP9xmf0UHVAhJ//gTDmzuk71xXD/7xTl+ds8DHw+f7Y9+kiv OwoN1kfP1FF8kwNujzwRj7ZFYf7TUTTZLq43tPN49qCNr9OxzwqjmS/4mapkprrsJbq+eoYz2vuK NlWb/WJdKAsGcI/+BxCWDPxrCu6eiSWQ4eu6/k9rAGnOBWqVn8vBt/UyHtHh+dyKzAGsG3QvqMY4 2gd4ie9rgzN7oJRIs1XVMBJh95UPMozuPPPN0XS91t69HvIzFHpP5LPK+T+qS6awiHi7PZFmOPmT r1nrrX8rIeDquQEJg/K8iO4dpJCK7X1uGpKQAG+iSKuJH2hAEZr7aZlNvLEvqu7Pe9RCwJ5PGSs+ +Ldp1BHxGiyVGAaeMiiaTERsKaevqvg1XtjUQEJ07q86FoXcaMjRoSEUv1fUBd31llzZkaXN2/7A +p8s4dCyQ4mwmcW9I53d2fsouI8Q1RvkO9o/HShVUI5h4sulFO1TxLgXTqe66YnjBF0I8H2JmYif /N76hJvjvGMn+cDElOAFvcc1fLbEaggQiuZS6oyypmCvg2yhE7CpnBEJhtQTYnxnOCaQQSZGh71f CUTVQRtWcLgR3jlrIDzSn/CdMP16P2mezdKg+lp3/vMMKF9yUh2s4uoqA5IAREnqFWlwrI2JTvzS VHpXZThIuSAMzypQZbeG3p5aHq15TRkIggF+Nvy4YK5RLmDTbWobuN6WgwbW4ytxgah2+/MP7Jty pI25N0+99wprjGu7Nzh3uZJBhEYp9f7jipEtcKcxLFIPbHOYufDc0u6p1OBO8stdPDn7UUGwnJfc wHL/+gnyGp514f8SrKYJyouXmd2CtKYb56ZudV+J5JqHkDY/+CijaVbmv9gN/NjKJ4t3BxddUigf WqQ9bKf06UIRucEnFBlNEfFn3kRUapB3g86RcQlvdXCrN4tNDMejKm95iXokAoO4g271B9rFA3+q IYJ2cnizKxWi2G8uQ3TDGDVUDgM9MrVnF6cT/O/dpLWjFr0cUT7aKXAfI5uC+lgUowLo359tcU0V KM3Gh3dpRUQJB5b92zJtGDqClPKZcUu2uernXtRtUmNIOeX3+h/kvKjgpA6wbtwvOmoeUzcqCxs8 FVx7vgSYbvEY68IBQqau0V2eKhHscAuzqwUFc8iGVXA7vzOEcdBXCfPrw53XniGVkL1Lh6VKpRvR yzlYGlDA0ndpqw2McDDAuK1xdbowGLb5RQ4+XNhZ0SkgHzti+H6wMsE256lsCXoA8nBP0Bc22ZjS fNKrL5pe5pYJsKZdTk/3ujRwb10y2uEt3tv5batUtTXVfaG8fX0Sjc7eXzU57VrikRYFqX3CXP2p zBRqqskl/YqJYD27C8MSPyPSSiQYvRkDbD4tU38VQBBQTfx+nB1ouonn3DQg5jTh4RweKZ9OEX1u E5J4jh5+8cRbPJ8DwKyS2WkNrAqVcmdQ5QYqiEakTSvQxDzjoI3Y9a5C3bFzLDjjhH7ycWb2VySI 9MLZdMYWZSfPhiTXOoyrhv0eRXJC4NHAmr2mIKsoTPX8+f7GcvxjgPJUv3Y5QmgSpsXNKAd9zEGg ZCuVhVChqRvv18/jgKUHQs0hAJyE/Lg70Bh5O5A1UHYA+ITLPzFZKcu1wK+gR6GRDcFDjgaEClL2 lIAMUzPe2gbdSLhFkPMj7wYHDpso7dPLRUt64Qb3YT7VzRkWE4Y+Wv9i5JNtYACI32MaNa0yXTlv NlQuk4e9zz6sIjdZIY46jNQe3/R1FU1XmtcvaDdUt0tphLpV96QNS3htw57DFiiIgg735LnAtRod nNkRfjjSrcTTlRdnGE8xNv7qDnI6ZdA3CW5PMmsVko3EVqpfSbRHqCJsyXjXFQynMeItm73A2Y/Y fmBl1p7k5Pb1kaGTZkGyLDqQGW4kfsDpL2mXaEqnBdIQnxk6GvX5BUPe7CVRQGDzaFKnNc0iNEra 6by6yKqqlRBZqHJfcmZY41k8iRu7/9W1+5LdbopU6m7NaGRsnezmZL3YTfdGlmvGLNWC/0/XApnn OuUDFX4KhVIlun2a7R501pK9EE5mrpxe2Q7OHv+tOVEuQQ887/EL1r9wVOmbZEHR12zZ07gj4r/v eFmv215yxNd01mNILTPN6nBP/sNcAWqFRO8JTiwp+sj/j/tPY05YOgQbqMZdf1pPLLiLpXpfLUQ1 73HhbhYKzduzZQQne2AYwldUj5U+oHVUbXuzKDr29FP2X5htlcaRm3IEIXL9jIdi/MbeCajX/VPP +4K1FuKdaVQdj2Y6PcteSibd5+k6bCUKHVIm0ga+XhspuTi2f0/qCnLmDpzfwoaFYBPl2mUTniWK ILDX6xcgrNMqjbCWF2qS9aMwIxIRo1Pi8TPLBxQEgM4gvXxTuvHvwluRksS4ddrZWHvRYWT7o4wF TN3dAHhOBaG5rRdYKVQfGsGx3sr5ZG8S0+fzRv+lbf1i9L1yE6fs3vjkIllRwgicIMr/Re+7D+uD FA10ipj2SuLYGNI9QrOsoROZnYTXdUathKj0wpei7Gj6I5VO4Nzm3Gx0KVeXTIGM+Kb4o327txo4 g2wRANNCj94bBdBdS+JaPuAxieq7gXbMBcGO5FJ4/waUt3Ln4LwGH4M1sM8INl+fvXegoryAIGI1 fdtzL+PdaxNrKA16ERfQ/udFQu9gAnxA5eWNJQRgAnVPJqRetxex1SC68lsNkzw8o5ihh4+07BTi mad3siJogE9rZmlpUZ61cNHUBq9TJ3dX0IRcsHY1lCr6dEnWvIAYmBOH3PU4hPTZsA0rBJRDslc2 NS3LK5cTeQ5cY70mnZoqbiooWIQfkSxbkUVz8X5GSnhkbcggF8oeYZn5e8qhxDFsgubhg08hID4F XtwO7TgGFjUIByVg8WDhOY9tk82WHZTORexsnDru/hUnSFh9/KYLS/RjT5n4noJkOX+Q9wVORzYN /1rQ5lMHUCiUqNSS514hLGyaRMCuVEKqd7QfuGuiXXWrbgEdg09sI7WHKf5jQ1Ei1NFE2ALzdQjW 1+AGnHIkzviFMltb+IpCYTPNtxgO6RXwDht2UOVSFgoy4e64qRYvo4cBOtceHkLn0v2av8svQwVK Bb3FZbdWQeEvaOmoKMcIp+fDiHkTKyxMMI2CZRMLaaQytHiOGlY3hfQwXjaEk7x7gF2jKeYxiUrA Ul924JabF5zfdtH1qQSuyL4If1X2RJ1FHK1SkWMQWHfGJZfiOr1cAXZchBua1Kn4KjbmI7BlJ5UR cRyU4q7gikDw693gskJ93s5DDfo+Tq6zqXtFHZWaPTTsdKJW2APoajp34C+D1ZBlhI8XfIQhVyj7 NR9eowDvgpiPKPWNvPo4c3xCKLiXRIJQI2DN82whv/QzwVUD9woQdio43jMa+Sv1wA8Hz79iH7lv 29ccEzFuieyekQ/nMBSH2+bXhxTm4tbgculG1nNxz8rGg+Nd4fDQsRqt1+b/SQhPXnmQqwdYwO/Y AbK9zCUSJVnoKOIgxI2DJqvBmUQAHRTK8muMvvgIAfuWRmol9YGRuHZbyl/9Cy+CgF646eD6ln/f 43TLV/kunqWljkgfTvL3Ud0F4p2s0PNoX76EXfQ/dl9Uc3T4+jDyqSHNQofgKgvO60YTnlf5Ggf1 OKfuh7jOSz4Krr5nSYIZYvAmxzA20qCJ/9H2k/MJenIsoRC5STXb2sk1Hn6pN6Xjz5URPa5V911q lh9njqsDzMQh/anNR7tA2zG+AucPwAo5qd7DKM2CIwQGTB3f7T5ZbxkL6NQcLIl1H4NsEGZhjhUv jqzhNVDIDWDyNXr0ukyX0nNKDn9JutrdybRKqtEDvVbQDj20/Lbpuh0nF3y5KReCzOdG+HVB3msm /tgOB4Jk/DvrMCFkkYG+PEfhZgOrYkQvvcRl6uBuM+MVA8mDwd73cq85R4VepT4ds8R18EKdeXnX 8QcoKNnzJjiflWfUZqu+I8ykhrQ/DPq9Mc/WG+NDqx5Ui6z3MooW6+BOce/t4QEpM+fH6NPYRg6Z NIHeHSddoV6QlfoB8dA7m6QLzE1oI+/Rf/69mUNmUQIyA2sbGJJ1/foQGczdJt8V2bgkNjfcr6Cs F8rbMeJB+HzI3fTqpwqUhwTm/WDn5pFVaoa2IeX5/U/J9TIHVDVPngW30bO8387rwBkwxBN3D7sR wX+016uKcwRFwHpTpe//fG4RDrG44FgqH/QELydCv+EN2TNUHWOjk9tqZIIt8tB0w0t1Lw3ZePhI Ue9IqarulW0A6hKKSraVXOZ0iYlA/bhnbooE/kQaY4Dul67QWfbMhQlavsxOds7uRvVp8I7LUD4i ShAWIoFKQVBDYR/adyNIfrHvFv3zdJCWwaJNfpsdfwaOrnlekyf6JA9DyaOrsYCK4xIYLPmRdTP5 BcR6EX8fi99PHlOMtOgMJ76knKrzK7nEDkvMg/duI0UsoUXcTk9MvBWpo9jQUBoi0+uVuHauWWad Gpq1CvpMxYB2esJSxl6wJb41ewuYdtR4YvkC8FbJK6pTJYgG8+/SzjcpMFoJr1dewSQVuRA5EnO6 wwdlVTVLeJGSdARyGHsN0G7sikRzCqul6Fp2s044HRoyNKY4eL15r2AQTx+iyiiqBSvTwoDNVME5 iMNQJBqkxfcGZb5ecoKPVnm3rfe36t4DMX9oZLoJtdMbariM+cNyXlkw0EX/vy9xY4AB0tE5i7kC WK3crQwur4Cp8xIzJwzDJEKU6O3Lm5ROVYdSRDWy1ZByW/TB8GsXYIXcRcRPBsJxA9uncV0FwlNI VooB7rctavoEGqC6/EwVSyPB1jz3NBZIAp6eBtpPXRkML2nYVHA0/fUqgg8a4xmYD636ZI9rHtBI UOfqUztlPvGEsKbMXSyrYZFjlvgxbdfLL8kTEdATE3EsH27Uy5Ua3V54epUxSV3kFqCRjLIxY/7r Ds9MEs6tMyvnk9hrid7jFmsvOg5BpHKAYDNrb3gnC7SJLQINXaEBo88RTmULBBNwTV5rc1TQmIMi 5/7NadTE7Mv5U+pK8id+t2o/BDchQPTBtHp8XljVw5k6I3mfhUxrZGQEuYAMBEv0R6OSfUSVmLzo yLUsaIwxgBCKyqUhdH6s+gXrwMgPd6vE5gVMl71N//I7wuT+XSMSdwRtXED8+HxCTdGygAjXa7rQ tJOJvJNZ//oLAgRaZb1DUg2nqcmaigz7nA5hqplF8AlJeRaQkPdm1ZZrPUFyVzBvfMNs9qhIzAsj 7/7nLsbq6buFZmG4yye6i8L83V8i9jWtbczWFdnriz2yOpRlmbOzWc/+b5UKNWsWqWNUwhETz73G YVARytV4JIphmtE9D6Gn1lCW6jqKaZ31T00IOOhRtp1z6N+jZ6Gr3787WV3n/YL6ZzuPjfB+XXs3 0rEuXppcHUG1itQTqKBveI1r42udPmGLY4Gx2zz5uZhvT7EHpQDL8iEUKyWRvvzQmeU6WA/uoftA VsYTq2xeDNJjA9eqJQSU5oMiAfsRaotuEdQXgmAprTIQTtCkLvpTbkFnysQIisZ4+Curd/tkrqr0 eVtGMUA4DUNpixZVnfzrqdM+s1ANo+jAEbtkaaQkvl2O8xR8chwRrxx90DThXOEDZLz1pgH1RC4m ymyLawgqxyNgeLXy/wlSd6NcwmEJdcYH7T8MrsEvnmPLzYeT4/a+NQ2c9DodDC7VsbrNnYFsPKKA nEWt454H/VqxOwCb3yhXqL6vRJKkzj/SLVI9Dh+FSBTIcAd2WH1VWSksk/542EjMHcU1MpXqK0ex mGTsfi3PRizcvCNmQTmFyWrrfVtDr/JGRVupbZerrFiT4hXyzcsA+yyNf5xrhAcFMQtnQV19S/8H XoOstvDMoz+F+iD7bUwunXptsc7x0MZfiWtahNR88QsEW2MVU5RUiGa4/u9eRacPACSc+Pj+FvSO 9o4q57PhE0T5WtSP9F3M/LzHTN2QB3UsfumR1I/U00tkZTBqbXNrVxpWush0LJJ7MX6CBsafPxw3 0mj7+DL9IrS0OGDzUoQLM8N4OQWX/9guPrmRIBEoiiuxIoUr0B0sOWbeIM2GUK0uythRMbcC8Lqi JCqsA91Enoh83GLyviRVIDfehmx8ZMyfANnAvJPCBRE2O5H16pkHMA04JSXQsG5+6hrBNR3pW/zF ALrDM0PsSFeVekGE+FVyOfjtA+Pq5jThuOWBJOOSLWew07UTUIsFFbT6ZqAYogQumuHzryVCl7vZ /mjrCFM91Zd2/kp7IrwJMWnRUfyF7bXdzSIRIy4CMaR9IuR1dLnSfvlDuLoMoBkgyZXdJTrz2o2q dfTmSVBbYZZKhLG2u5J5kyCYckc2Q2FhO7zpvn8UjO9WcjQQ2X3Bnylp0yGmg67QfqvYifMsW3au q0NqrBkfwPCq1VtloU8lzTrkI6owbbwpNqpJjADfZ/NFvvtEDWSQUeF6tSe8r2/6kXpC6UX5Pxmd vyakYoc4uQXOXN9rJpLYijethYwN9q/x9D+IztrUrQtTsg7vYYK1TpEIKVQKsyPt5fCHliJI3lls aRLTHcYc2gkiIqIICxs7VUPgoogf+OegwJPYgiBUXWjo62+ub3d84rvEbrieUNjGK6TkmFSy5ctU IkDv7WozXPVmR70HIJ65kA2tdmuaaf8XIDH+PeT4C63aZcU3ksnQFDPclP64gBnEkI1NJRMjlbE2 FNZZq4tSQQMYEhIqmrac5R5f9W4pf/MQb2qd7s+YYSEGm7xNtCA8azTn218y9mWkvylnfH07VRlL 3DfrXpLhyA6oQt7UHqJRav+wAXi2tFpRTrUsjohgICxf7xVaIhSYsDz2lzEXgNDlaujFZFT8eA9J wwqWGin8TItJMXhzSQBl71et2GuoWiKcGieKBxKPGuAwZuJHAhsvw04nUWiNajUGoant9n/fTGMN BSj4YURU1FfG+FN/TFC+c2PIh9xNIbCmYS1wyE3w//1XePrCcOUH5YtLy03RtZwjde+bBcwc495D DXxgY9z9ydoS/0IFmWi576cpUgK5CyVCi5ala8crnn4thGB44xU9EfludbiCu4KU5pubYuakxggd TreK0+e1BrNeJBWrSMpJ4PBz7BTRxN/O4so98b5+Zm3gx4X6iEVV0EB0qOIyJOcpnL0rGKDRp2c7 oAZjXKrIoSv1csopCplY+jwgTgCQ9lGyRPmZMgFch4PhtAJdX4nfmUnsmE6xzmEmx283N5zJm6jc 4Ov96DWp+R8y06wiw54USBXRnGF8tZWJ9vHvU16vYs2ih7kdY3TFBSMFYKtUFqmb8v4u0NKklF6q 1zOw748DDISz3RTs2iTbjQbD75cC31WqelRDG7jpJygJvf+vd78tk7dPxfewYsjNYE4uSMM4g/JB iYHDTUwY3eMktBrHJsMdbs2/bgMslwhhWhGkk2Sok1NhxFLiRJuQB0QWTGM7IumSlmtV91ACVBPA 4b9DJSHSkGBj64l1JGbLmsTeXnvW84RTssRXilNuL4dCDw7A6K1+gQK4xiZ1u1lbOqrj90BF1tmI Nvf6ar4oTdDduyOoIXrslGvW0IAyZUgrC9EFAHOXXlW0ag2u1O62cIZIEqyvr3yKs48oLqB85UbO WxwKNKX2uLbwinaVnoDSh21nKzMhrODL6VcenNOQLUy5LxTsN2R/UVZU/sxWG+FGuvPdmKCAOU83 DG6GQ7q1omOmRgoKvLjXWkuZW6p+lvZiF6vGVYjZQS4TZDH2RsEU/SoaVeB8hsNMJ0L0IxDmOuzf o4JovKjpJ25o2G3cvFnuqzk9BRcE/UhYcGaBOrU2S3ew+mb2gL5m2jGq1oFhUwsJXMKZWLo1KcM4 CjGlseUQmcsP2oE1haL+41ig8gNsw0lrWm133OD8k/EzV4AcgfUbyAcX4S8qWYGeg6PobBEx0Nrk xxRm2fV6S8gb0UXYemB1nEzbTbMKYkstgu03kBDZxk2z4WUVYy4baMp8+09tzj6BlD+Ob0Twdeo8 5JYYRS7cxOrupdqeQCPpiYu3IMrVW1KsUX49tNvCOSjG6WmkSE3lzOLYA7qPi9cVgeEH3d7MiCiH 66VdtAViA3NLTVygmpMIZl+qtgCs6TTPhPVLRmLCED/N+nMOTDJXiM0oUxD9c4sKfmHK1peuIkur sqcxGlpYytRFugwDBsy5jvltvV7fWuA+J74yGJk4vjVfgdDb7ktwCwDY9A6jCiTC/FEjEccZ48T+ nvTSQ9x4YYzav7wcrsuIRk75bo0Sh0SiUNdvsev5uJn7X7vCmtPSpTe9i0GoK6BgZNx6XTAS+yQr ayccGX4K6+900Ux3ID+leXQ/VJsdF5E4DOYZDf4DSZrLKsDpqkvQCAd/Ks69tB3KJ8W2SdfapI3n LFfckG1DpqlVsR78cwMNdv9BDcFwkVC0mpMcavuExPVPB+NpPJgkFnNWemfxd29Ue16pef/TL06K zVH4k9F2ay0XNAmcCzIIrgiPW9qZSmFu6f8eZaDHIQlf/08MbIL9F5kT+juNgOCvRbk/7l886hLv CHogYxuEy94yzWAJs3Oz+qdqj2VWRtq1yqJu3+v88OqG1C/u3xYfhP/cH3aXA5E7Voy2QBxixe// p8KHq0PWXr8UNcize1yirxhr9Tr/5eL9dZYU9Kz1kv5c12ySsdsGx1Dz/PSqoNr1sN3MgcMdFQ/T M+fssi2+DDhaObEzsstZlNzCAUrTuztUdC0tjSu+14IewBjozbTqvETVQi8DMiaK65qxbXrPGrE7 OFPveT8DT+rmYoxzGX/IMrfP96YJutQyi3NCrxwKiXWgQ1dBU8gCJ/gF5+ldJalHzKx/gkK9MuXw 9hg4ObEOFynQ4k1G02W5zJR3HcAlij0nLzt+mieMU05RWfSn6gDagVD1VHd6YfmhSWX9brWlgL9S IHydcbuTGp1Mk1+TUl13GO/tozr4W7hfE+QRd5V2yZFKpZTxYbNWIrFmzIu76SYtg2vuHSYjl17B CwEARSDmmVkuiAA2h2zxQ/TWMj+cfqbCxoadN1XA9CwI2whI0MueW0jQDu+V/nz7bp+hhNmsNQyC 8jetgpMgDQDUqm/OwmUp/iqgKJWjNFo9Bte7ML4YQGbyl4E2uxQM7rEhuxH4ftr5oYko2afW436J 2foFRQZiJtRSfjT6ASfhK1+bnPXfGZJtRCOL2zy/y+lhjRM2m+N7WN08E2yCM+yNahdqvBUh5Fuj D1O8LwVdV6B1QNJhqrrpS+9LVgKtmifQAn9fSoWhoXXdSWOQSTmtQOg/b+5GubJLaHUsrME2Dh6R zI8V3GCAACho/MqGY//bilVG1a2aI1qIxr0WFg3XydOIQwg4WPfCaF5cWv6Y4lMH3TVYrORABO2k oJsg3W18MFrDS9yzt1o6RiddEBszhGLeliPko0mJPyijiCg9cU8yZU7/ddBtW8WzH0oYsMmSWpbM i/TkZfAAiDCYbVZ+hmRqV2R7SYJ2VFxLkFnQ38GM9KutbfrbbJf8dge25NAvw/sW6lGxjT5RT615 ftiyYzDG7p/XcYgHV7QQaqHVNYTdzgceExskkh3cKUUYjOmAqXIOj7H8DxxvqiGzd+lB0AXedIBN jxy4CHy1lR11gh4YK5Qnt2/GPaWcspK1JYYA7eP7vcX4VeOG0qLrn9MRENvoLClAcr+9KXGGAXc9 OEipNUmFajlRL9+WdDMm/L5IdJ2/ozTmUtjcaDs8CqYFw4RHVk+dUVq3RC/kCSad55qdvsQpv/QU VTyJgSfzFeDUAIoDSntt+X2ZzMJEoU2Lzqsk5+ey6h7C/pqyoLRrHwHirvPdIH9+HLUa3wgU/8Oo IbskvNIYVFTDF47MU0m8kh253QW4OvTYk5WSqZplaKORHHaikFRgHb7uEODxGNwfH+JH4cWI+rhJ WiiF0Y6idFKGG0+QusdlcQB30BU0xSZZISIaI7MDjv87nnDkuQCjMX/0+nteG9Yg8N0BojqSxnZc UQN8tMsQ7hNY5P9UNGCcgRnDt3tgaPaONQIira2/mTl7HFqD6grzOz1lKhr8qu+wFO+7QMkkiNiX EES/TANNhodvgMvt/hm9FWax1Mw14i10Sxh9x8fYKebHXVIeeVrtqYoOXaDnvrE1VFVZt8kyAeo0 DUoCK7kdxIo9UHkTAJWuhEFTN6XCmsOXiWerHDcaQFJI8sgv+i/m8aQDgX1xAAthuunapvM8JpGM jUDJy9Es/lLcna6BquQ2u6EOar61+fVKiEn2ixBIspSzCz5zIdNDBms7YkpLzw/QZ7H2Fx3Eg9Sl 6PWjmmzxyfA7hhcFe39wjOKqQxJdsL5kKGNeSUkmlmAZ3DOM03ZNF/OSytW8sBFYvrx7MlG61DMf DZNnWIQdtj7qK8hNkkDW2T++afFP6Jmikq+Y7CO3lx+CmwA6UXOGwvOHbFE8itWteXqO8cItFXQC h4GR6NlQNWsrnQH5Eb7Z8BRlqaeiBkotNzLW1AJspZdU7M7qH/FsmfiPncKuIxVOaMuOiKTdy0Jb 2H/2BvRJ82Yz2D3DfWy4FVr4NE5rNVR4lL+dp1SBlBW4JtZA4WOML8putvakPG0e3Jh5OCpUJPEZ itWRR8geAMrce5GVrtYBbTF9KtwOmkNeLmwyrqFAjl/OymQa3gT0Z5+a1q90YELKJ59SLrhJe6+L l9HYZx+g8Yy10fdwSHZkfLuGV1niqCUrv+z1gWr4lkdkru3gf9XZLhZioOCSb7ySrtoLz60HAdkv P6j6CLjgqWQmZer1Ov9U+iSBrOxZgb//rQkpZDDyTbnY9cv0qIBgtmKqE1a+q9x2pei5KKrKuIno y4ARYXw2jLD75DZ1qXieHT5Bx0HcXFhfnlQggDWDOGau5jzpt4qj4L9UB0VaZsWLk2iQkJ5huNKN czoaAHaN1QeOYaPVqlyHmnZ6tU948sCBYMOSMbQZt94yvtJXdYjGLZTkQnIGYDnRhwGXMhi1WIJr Otap66+BzQf9N6mw/UeRbZ8lGGOBiRKStUTPJ/jsYErawnF05XGLVx1BPMKw2qLCl3TFq7MgtMlI YqTT1u3iUCVd9vct12mTrDuA+yNCzTN+dkBSVeoceWaTKEa5kLAJHiLX4oKG7jgJ3DhAx2AYO9FR NS7odjQZ0zxQittc75XO5pflC/hgk7o1D0XhXpB3nFvhhgkxPR9zoj3dw1x/iih45rsNEGhl3Ejr WMJ/OXZ1hdQcwPsBKOlKiB9kE0iMiBiDk0WYay4UjpQH1ziXtlV8GelKKHD5B9i31hUkogsFczLn KInbpJZPVwiy/B8jO+9YKJDABaXN8KWiAQe2uSpzvEO+9WOx60mOj7ucVdRuaAdto9p9hqppjgkZ oOkFDr5g557KyB/86Zt/nsHsLuY6F67VoNL5Xzpyw4uT9NjfimXC7YlGilDIfqQkYrBgo0+EsVO3 DtwV5r0UpWStzS6cCMb8INGb+HWrQdHJRgfJ2EUd45Cg/KeZtaU1MFYFBd5U1PWlh/6KOGN5mPkP ou1VPx8fKLIvFr7dACTT+A5JYMO00PiespXqokx/JhDMbrSu0lHsnzwIL2cA6dAbgT2sJHNpCHOp oSfDDA/mB+A1pWI51kVw1gOfytdW4aRSs94/wlHIlIgKyFpm2G5O/P/FE1fOH7TGYwyX7Fhxr3/O hDLCMpn4PUuxv9zbD/r1SFb0eIel0RSJGjF8k7yL5I1+0MqCO4cTmhwJzA4n1nLTRiE3tzCUZSWB thM2agQSRJTUjVrGsmtePJ3k/QEE27b+QFAkz43YuXu+NsWecSNx8GKrMtyaF1iXLhoyZdGechrp Nsx8LOfprQhDK9buSl2oLs7P0c9J+d/hpxJrI8azi+TPzGZi1vbFAH8xYvKQT9gD5zLkD+svWeFW Xsljwwus+rloOjwJvcOMKTnlGnXm9rVJoH7962bAwPC3A5HsIr/KEYric6d6wjiDzZmMMTJmCUcM v1H7eRWKEGyT1fFtm1RrgL7MiX6EPGpMqXnqVIgL/TXUY/aVvkrmlYAgOUYVFzsvHlYEOODYHyTk k4OHkU9shJ9LXqNzgerkUN+CI+QoLv1lZg95rWSzfWoao8Wgal4uviuH51KqWAQaM5Of5NmXjETm dBN4ai7ZvAWmv8A0aofCtYgaKaM8YYc9cRpqp8BuJXi5uQDM1gSTakqBd1JpGBseKBLO/54nqDNG b7sOFkN/o+Js4FwArJ22IN+NPkXcN2qOigFapL2pU+UkuKewvtJJTpKdpbRiVRolmfG4EunMO/hW RZIlgEDCZMkk/jtZi5VoJN0kFaasL8YWAYhRUZVgz6KwA3Gg+5pAV/HeEmUWxIzEkQ45RjpdaHGb YttXVi7VKUyD9dfxsnxXILBRlq/lsh4yDQG32eAHy9I7p8vEhGZUxaNlxiHOHf2jY76kKKRHQ/0p aogJgVhXn0Z5+9DpazQlarrnMROV1K3fCM8dizr4wNMd7oImHk5aO8jbTeKXw3ufGHLQ23RbtnzU AbQdILdh3D+X7/hAAP9tDjyLl2I4FkqQVOt0c+zqlx3Yfq3T0ySYEP0jKP88SX1bY+euWrgzltiy zA913hWsMoA/F63k6BZ7esASEKJ3/8F938MIJgZrjKezhzTkfKzahbV80oxOXbqSw/TycEPmdLpD f9biSu4BqLXrerjIYjWyRMpr2LehhR5OZ4JGivhyBuk/IyawHCpnNbogv6hos0+oi987F614qeuw 3V9zmL89txwLs/ac3cpjWFLcVptAhbFq2VYaFrnh2lNkTUFP4IaL4pY713GtEzB0BJjRG3JUJ5A7 8Pp7Xw1MvQisH700mNN9hq/kZTCa68v2ENRqkbO8ruz3bR3P7xTahirP2PHdTYNLH5RyIsPSxxso ilZCZW0UJXRD2aNVsmuc52/myo0n93SM9kOr2Ehe7zWcb6gNmaU/manV69kzuaTbQDfk6mAq7Ad+ mWeWbZEt9AOdLCqcSuj3V7x8RlohPgIHOGNLhSSJYQPEUEyOTq6dfCZ1Vz4QVQ+Ugwvk+qYU59IN C8Z3bB6Ya1kwuPeimh89UEerLAzmwzmRkmoS+BO3DxVoN6XUyVWB/6kJ0M7WIEbw6V7xAU0fhz/m v0ALCwT9xnpoL+pbPy4GrnW+81Rmq10vsD035b93o8oSsEfpanmNuOrKU0RDoAAi493p2KpTy1Jg EIEc+YoeEH3HEY0CrLJ59YtBejDXg7mkaQqW1KDmUdQ7HICMnnuLmdwB6Xn2u59dEM++FIl8w2zL bzanOyOV9PsQqxrYLiyvcQg3WX0vxX3lSyAqFnNAStEUDP7Cx0+g1dRMJYDEx7VGDHmWUrgl3uDU duZyprbnlwn5+ENzd0TR2btOZlJ70JA+uMJh0eueU1kimAp2jMzTVu90RqM786HVyY4ZhNrWgYfA vxkjPsV7skVjOEE4c4/ZtCMQXb4TpRKDTEuIEfpAeUSzXEDO1Tq22/90BNQY5YpPrP5fFd8vgDIC LbQvXTUcW/w35CVqGSzhXIbxCIQAAub565CwqLQUZ/4/QSZ8g47ypH7sC8rVKP5aRoWV2I64flQC p6hGReVzj9x4oA5XEGC+Gv2/tW4+wfd87rmvf+DEwXjDFg4YXn2zBpjacHlcRQ75QlTsmAAN344A v0dWVEjJDs8FfsmDCVd8+lUTPbS5BKnPaHTCH0sUv5gUNiYys3jY8DPGPIpAEywM8AcL2ojtKrwg 1EGU2SvcRqJZi14l6xPwd5auJFrPHBRZhP13mJMEUj4TjIn6oVhpUIVepyyCXCsumi2sWr+tNYf9 a5umfJoTWpAxeGgv4e517jiZcUixh98qYK+xTM8XCB9vNcWKD5olhsMiY17EPtlgd/7VJYq4qFsl qsyKrl4ciGXgFj3PekDp3/RjpfGwA1rrmzNkVqp3FuLty1g4sXAsCkJRqRK+vS0VVpp4/TVR1dh7 3qIHkI9GQEAhe1ztGxerCXajygi09ktzjG/TIOfLlIgPHDZ3Zh0HGuaztfBMjlnf0FOdALVMg26+ Lg5OVcfczFQU1sCFKxGcpX+Y4XSERZuMTNVgtR3KPqfV445baKATG5fG9LnV/1mK+OZb2ldc2PbA vQ0MmNdPFS/bKhdB6yEcZsxMe0S9qkDGZ/4M0G8p5KX3vWnOum4NSVhuX7RwdlRbXnsxjvjgfsMw jzuZZ3t2NFacrxgkn8TS3xq6BDOVZj6ZpP7D6w488Qc0xCf3/43exr+vs5LAd7j6hzzgCA22NyY8 eENVIe4dzYWA8SBsNJx4Sc2Ae77O8QbzJMVBUfKRijyvFkJEeZlzGtWy+CWsgx9vs59TbXe7Omay dS/7IQ6w+BBBs3x/cp2ZAQMoPJkrryJn5JorUGZFA31fxOmXB5tDKe7y4ZZUsx4CkjF8MWaL0+K8 kDZT1GMBsTA2pIPh/ELaB/mEZxOk2TwGdLfR7ZAws4lE6dzNuTX6S2l8isFCGRFrR70JQwGfMLd8 b+rq3dG1yGqFnu1AufOZvHws/+XFJFyHc5Z9ZRF062ajpVVOgbb7Al4YidRc7805TqsmN2NI0YKb Piq7uXR/d94MNHpLQioTs3h/NOg8lfooMzuyuc5MVoMgvyaxETBRAyZ9QJJpJkZWUMqlBr+i5kBb JpTvxcKCDIeDo/nUTbmpFiOtCNE+DQOO71l4dc9A2UVLlgWSLm6qDlC5zecpLiqh2j8o8m4eeNpi uNa6Cjk0ISWrWVEQ5IZPZwBADLRGKmae3Fv8tjSGrb2lFFTEZXhyelhtxBonkdvU4vkpTu7iDll8 eLgsnm++FsM2Q+I1oBqyJ4uaoxvP/YFUQ3YbJjlxODKIGz/SwSm98JRJKS4857W9LdMP6/r3brpY rngV3eR0Yxx56SPoYFgLNH1CLeLyoSmFMPRl7xch2jvFbXX2LwkQTMLhKRB/7TA/Ef57N1ls2mZf l4SloNmtuX6RH9IItMvKEYtqB7E2MAEYhVc2XdC7iZjf6V+ydloTlDHyhcOXhY7WVFjzHCri23iB HJvuAwBAGqhG+/Dnq7n1kjEON7V38cAOJzTtQrlOCEHBIulKBsZJr8i9dOB8yZmZLWW0K8lCkfrl 5CGy67dQUAsrcvzrYuYX2To9cKhaynesumlERnoLPPQCUSQ6qzK2vUaeEDOSIMaztJB7OfRdgsYT P22OiLK5QZcgcWuzzwiLz7/8HI+Ywn9Q+tquiAQgDbZ2TbgrJ0kpusdq0N1mVgiyM/HSobBLUkuI VAZIe8vSGV1VUGWc3PykNXrtgl5p2xoeGWPa0s8CcHu7Swnj+Ai1b13mqKTIXEmT26xP39ifSydW wZennhy48GJoWWq/gXTCDkTL8GajUUp9KhL/byUldo/IDE9DoBdzswCxRaBf90X9hqLFSy3QD9AQ BMERKQIdN7JofkdKAOtkcAdExiWMG1LunHpO4IigGtKk9vbJ6rCWc9riXQ6pP8YSPo4cNynFYv9+ qaLiwiMKozhYyM1YbWXHsWbLYKwskW8OSiYO6nNbf+RccXFwGFPaBtvVCFM6S74fK5QNmjayQ10j D1PWOo4PDu6h35YkNpCeGiC23pXWgln3v1IMOej4ojKplQ1zQSv2Uzh9+RtTFPlW4g/piikyjzAW 6Lb8Ys4ntJA+H0tlibf0C5JzhJYv4d9M1Vr6bB+aiXYgaszhQPAp/ImC4tCIGVxWc/6SKscg6tY8 p9HMZe20jju4dplCrsO5Ul4xX455sx5six+sliF49J1kO+qfZyUgzgpWwuK3Is6vfQa7tSz8vasb mgj2qeMOABcP8QWniJgijs7w6nb2k/NI5XXHdYO1jsVQxBe0Esd1czIrUAcWhk0l2SeITRcJuNmA DdXSu7t/I01j+Yg6N2sSo5OAXxCVg727N0gxfP1dInivA9Gw32KASiph2XEJlA6q8w0ZT7a1fAd4 OJVgty9szrGY2xvhc7An60QoL9rQrNt1YEz/fbwgFZJR2oSSNAljv5fRVY9/JCoKb7NQKBnn7VFK VWVJ5Lqr8f2aufomhesTAbaVfg/G7PIW52LcCAtha73nUXq8gX0NN7pQgMxGg/HqZUtZRrToud40 cBzfpyt/IYzuCppvP/wNnRn07H79+jp6KOqczr6OLu5p+ikP3xoN9jF8hkCWNN9RH6bXytpARCqS UxlqpkvavNq5zjNxvqbXZjxjv43CYyINWvcyBIQTJZKB83TZP5keEn1tvRuTpwnqWXMcKRQ6eGmO pHwByxVSXThUISQqTnbHaD74C/5F7r1ldx7s5xLwR1JCueO7qQtEk8hT4x41BmFSdC6JFl3+ArFt yI5l+7yKMO7d7Blry07TdtMLWnhIV8CnT5vtWdJK1OEihKUMP78MUdBzhW9gWeD1yOGXhopv86a9 tRn51VIu7RjdfI0t0k53WT9le9cBiqRNDBuWy/+P2g5TF/CYRG1oywtfGKWA529lK3mbgGBmAUdo lYKwtVSGK/tz9Om4rwRtjae7X0spUqaKX/wAUht0oWhgOmLYHfALlwlctHVjbkPyVenESZiNjvW6 34h66pTMlcRGJsGDQu3m8yn5GgnvdjWo2qEAEATWvyzXgIqmR7hiMCs1qmdcSvF/M623LcezPcq1 cYZzxF+I3A8czuLirLrVBpNYR4lX0C/e2ECUc6WEoo2XaYsN1By0ph0ll6YEGWNaHm15CKWnUF2X xN06vbi8FsxnZDO0bQXB+qKD40o867+nRYEQ2tuCIZM6fZi7rLL06IDphjFtMeSugdZuI+w/eREL UbTbYngl2VUF1Lbxdn4CFFrhoUoO49u1d1Mwo7uo1UZCDfxlJCvZ7M3OwUd5HJeewPuPnXoIkDKB ENjBNzG6SkcymKtPQURqbmNcidOMK83lWr9zCBi3qW6cAnTpRBTlmPs69tJuwneb6KGdUBkeSSMh mBWoLpjSAfZDmVbEcaQxxjkkyEHJmb13wWSLoRmyM6vBkB4kE90vWGe1AKKDigI3310YO1E537ig w0DiFYXCxN/0cQc7qXYFf6Phel/dbSf3flTIgK61DPjirVUgDPIIyJB3SCgI2mAA6HsMnCyMLJTf PUDi9g4OAMd/3urvNoSaVLWnq2St4HWOTY8BGygavyvB7Y8BsyWpiOFnQjMQmkm9UwtnRTQ+cEQg 7j+iDyb9BndQzgexViyx37tiNBdMu/TLi0NMeQMomPTqc981zz7R/mlfsXEdMu0noLZoZtjvWz4i q3RZaX9ONzNUVkIFDWsl7M2gwJqvieBR/8j5gjdYGeLXKiWjDBN/ACUuRxy/4tDKsxQEsSlVNziM Awc6GKk8Cr+FMDmDDqZ/GN/YmHj6ckffpvoh6BMGfAqGwZKxS2/oGUeKqNMHaOeQARmHPcSGXS1p wvAZWWppNPid6xOLDrvDAPvDip4OsmY64+epyNH52O55lxfmGQRf7MC9fj2gDIpQtzvZaSvHBYh9 DjC1F6SUPYpgMYSaAZYTkRgAg5XzatohXYCsKCQPOgJ68ikOagHlo/wTM5qMOemEC2v4DpEpeunn HCGExC+STP4bGKkGf9zw5UujOj20w3hfpkBbETVMF1NQ9m1dEAlmX91CmTAbS8CH08rEM1teeZqE 24CRmIpVJPfe9r9rTVJaQKC29EEutYrsGSsIUEx9ms8VXP8+RAptUyCd5ZxIiCEfRvL9s47haq6F FYCQerx/uwzJi5+yKNADK8HLY/2AT5UqZ9qo5dkgF+55bZyk1XbiWYXFgpgwdmLqv/e7wWBzHcE1 k5gRBGX/RmFx8cuDrcXyIfLDYmn0axWURLa49BsRuZHjJ3ozmvTSQYwRCURJCHKVgjU7pzNmTtWk rPrm3Jq6BOrMA3L1/1Ji3X9/lHRiV8uTwS9xHvGXETlg24q95zs8oWbFQcKFNuVpZcw6sjsWxmWZ yu1OQmgxMAzQ0VAK3bQUIuhOfGrTkgUKZgT2vUkMs+1NdCiuBTfsXfAZwh6DTCF3jPcah3tchJt/ g5hfIcYXyb/gIk9rOt4PerKMsoEajXewrGlAktWsFrSu3p45lVhhrCYSqJpv/HBtcpOj6KekOBId Z7upubQGUG/3r3/q1S3ruWwrIk4APCofYA3siIwV8IlzqpCK602tF4VB9chIvtNLuNRuW/vSt5lJ uM433QvoB8PRhkjdOCQq5QJxH5CIajXLc9+BgHpwMUmvVAXFKbFNKPP6Wv9erKyGiqSH74kUAvHl /tfxgcyE4aTEB7bq9WjUJlptebUF55iqCB5wU8Yfwy73/FLWXTN1H4Z4wu2tZ2EzMohedFR4KgUA uFiB/ZhFaK1hxu48Fr/AzHe5temy1f8EKhRelN+N6C886kYyTygnRzBaqNyc1/TVTwXvECsYgCjj co3Qx3VFa+xR4XgLXIrth2BdqxQ4V0OxXY2UYXIBOELjFofStAV3X2MkF5mVwb3dCEUQhQ5OTvDu clUllaEMUex14gJzZjYIAratNmYvEeKwSYirmcYPLZ9sqco+2dbm9M8iKJaMYPjfhmbax03GnUeT yuV7jCQUaYJVyvGz6Hc87rphmFnwSO0xN3wiUALulIkSGxIQJm3OFwTHOQgFUqY8e1YXxL8AI804 sGhgUcLmfrFofmoSb0Hd0Dgq3u/lk6LUSMIDs0Gh3hVd0Y9xix+MgWFBQrsLqtBbkYGLRCFBLfw+ MFKloYd0Pm6YKIsv69bjjBN93zR5A5DEvYMxkKYlqNjEzcoBh9tHti3zYGuOEANPQBMbbJzN5cCv IzpII1TqGNMxOHhblaivw8uTrJXV8sQlVej9sK/X/onCvAEJp74edTxZN6C3muumEMfAG0/JASUh /dTq0QIUYao2EJ8w93NCpHacifUw1qnnXqQSI96EwwEw4oc01V9j2gfGyUYYuLvjQI+vatNW79cB MxdF/TFDCPb5xSskrX1Zl3SYHYy4xlfZYpH70gRwRje9BAJWZJyAo9vtY+r1fDXE2uByIW8m1icz XHILK+CU5omzplR3bcmUxOSyY4Q4pJ2rAZR0lt4bC/AD1lnFq5fnpMDs+kqtbZtXcIiusne1B1PU n3PPypQaVNS2vN7N9/qVaIjH4K90ZVzUWSlsJ1/rHcv2fiJgrwEmpaWBRxAqOm1AbjkNRlBdFtuG i4okcxU8BFBW9QNGVM+ijkXb/Lvy2QiTepdKuX/bheiOMwdF2A9tV7H7PWTOFRaxgfolELWzxr8Q RNHFWjN4HUCKBvaLFfR5na+LDtcZHCxsYBW0u83yRROm2nWfFAKbNbUFUhE8ZDHr+/HJECLurRmK 55wZwcVy86aFDcyJoM24J5DtDddMkhSnnriWUQWUDTjhap6Yio+wNjnU8/uhusborrkELYRsHREZ qGNL1TIGrhYWF1zZCWg8l7uOnypW5B+TQjVLtPnSmoXM1CKas42KtyZNKbPOSaU4+oLX+6UglRVX KP1VNRDYFjFZNSopXsZ6VDLn3/4DFGS9SvM+DAAs7MNq8xrGfc0mClvAEJUi+/qQ25Ndb52b2wLM 4R0WUKpHJ5TLutxMmTOPOWxgj9BN9QbGbnSqDKTFLQYxdNVg2e1iOewe/ErFaFobdVQl8ktGDOnq qwv2+KTjRBETgsnES7HWcliyLJd9XalZk+XpPvDWiczxRgEbXyxx1CVLrQp6kXl2QRXAdzV3NgW7 wJ1lP/eyymHDDtO44g0zYcFYtlKnWeRIh10wgXJ4C48STZydBijfbfAzTQ3yva5TOROSRYLKaCEC mCqAEOsQ0pt8757s28lc3LYZVIek2givKNuO/TuWlqjykJcAvgRcZaWFdiuUbkr0lHkOPqMr/5dV XAhjUdxH9l3IZ4LLgkiY0XH5rQ4mBXyjqIY97Ifbeo7Msbq47PahFl+xCSMGmYZUOXgZ8SLaaPgj T0SAxxyhj+4zh8/NH1te++/3txD6UpulwTyPLu9k8GbxonyqXHwFZm0tWtF5wqbgOPuztpw/fCZV HHVeOLROMiSfzjdmQA5A/8LfwnQo+c4s8mAbLvj8bnXayv9lgXaVFVs39AABZNWphAVVTi1Ssxtv tzyXRKY2a6wFqk5Gq8bqithhw6bh8RcSbUEiFIxIwjVAEEoWVO+7IN4qXtENvnREUyKp5hK2IgJT SbOe7kpErBHsmEzb0R2Jfpd2RfBDqg/YuTERHrLVClQhHMUhX/catIg9OrJVPXhN9S9TjrnUTcWL OK/9sNsByd+kBCyK3y3J0YC+8f5vaPmUK3uPXrsHJZA816NLQUgSjmEqfU0lmtcB1p+sZ2xzRLu5 0MzqULTe1HVtH77FyHhGIeQIQPOca+0bYftc1k+0dj4fMC4mLdTV0rBoY3is4dgVvo+N1YihNjgI UiRif7e5ASXsingMPGhPSJoaLvetZ2i0BPQ4d4pRA9ArL/XmTi9E0Zhll35YOAYKbc6JEpUDDvQJ G/EEg8IYZfNmMTPborojspILJQEajTMSIipK02y58TBPv0vU4ww9gZvcccZ7nbhprTrjJ39JrZ/K WOZNaA7qhpNsQtWgJOgQcS7xF7rhUcApBcm2bWStcOpkrrbTeU9y1QXp7JU//bGPV0OV2SQaPz4v 5NyIEMymFe4S9VM0yGLZXgmLz2/hIJu9gC1jjBsOP/EKuuXhjyEVXzqPKxG/2y6C64kC1ib3DUxq zFWR4U4Av5Qpn/uHoroyMHHQLYbNBQZ530aHvQnevHriSwPThIb+f3p0X4J6X4zR+1Ii3U//ag7x +L26RLg1CKYzm3V/Q1SMlar9ZCBOw6+9UDik3mL+jtLMLj6nxNWI5jBLrvALCVhkExdDYvuzvbyc MuMejZl1xU0cRw6uvqY/dUS75AW/pU1uaQX+K35z1qf9iq/SXLqMmy+ObOyTS+9zW3ry5u17ekRq bYpTWUZiVA2J0NPRJ9P27/qpSdUnZl4Ubn3fW2wg510x5QVJWjK+aNsl+uVg8id+4E1HtFzbumqV xGFqlVSoJ4WiYqPcpulp+aMGJkzcxNPXKbMiqw5+TKrgO9O3/FC1ToLN95ztwHHrOQ7xaQJOotdk Mg0eXdXPpymFBN5fSPrvAE+DmNbjnSDuttdOcxDcLTYUeX/ICqE8Ze+uRbrs7+ElHYdoAsgDgCXH nmrhoz74bAc29AMsuN1ExUFzuddc88ePGgyNe9N4bXT8Ao2/0lKP2hWjwnS22kcPS+WEJheFpbMG MnkMlwdozd47DSA7oEhWCcI/Ju/qBkfHOyYvzSiswl0ImWxwVs762UT7HSsjOvInsMGMfaKJ4x5d v12jVkdFPjdQ94D8JkY58cQOh0JbSlH1uxJ61oI3aEVbld1lCMnfSPsVnqUSBRja9GXezX3q7v33 MO79D5e3neeyoq3XhgpkDohUCem5/b3H7IHUWruhAHSbein98Lv2RZG7BmcEnjVyXaZ8Zz+a7fl8 3PwIDzD+26XYToBhEIwvcJPyq+WUafx1O6WE4AA9HeCa5TVaBt6ytt4ojcBTnZDmx5VpC9CNCQa3 0PJi27HQpJ8NnDMEV5LTy9RUYVUCMT1dvxGqFkHd2cXtJ27hPeKtlGiPA2fFbJXCES7oKPNIUOw8 kp/0xWOEw++MHpsBxQX/KtEPzHFKUyee4G9HoFQJZlc/WGv/6ZPntGba7qEADwggmpogk7+193bM nqg7rBdWOTEfC7TADPf65GJUfgVX/omVtiTZbFtWYv8AhgNjM/U0iLdE2786vrkU0vKHe9STjPun xOwsTHtbnBbPOMSp/anho1eUVz1aKRL81gLLyd7sFMirbDcS2G1hhmuIgVazueWkQHjy+/r0c4Op Qz2nP3aBXTMzZvklf3Oa7YUKvZeYzyInfucxWsUGNk/egnlJEIes3lze4fSGmCOPGcNFiJ8h/K8a 3dmmgzmjSvFB98zbrH+X5RsQ27HCVn1AvFxM39pOJu7bkeZcgvtKoj4iRs+qSGO+Fj+k5K++Kycn Wk69T1SWqT9O55SfQT9TIjZINa6HNW/+6WW2FALfYI849I5ywdP9WsFuwSmS6q17XKUgOTIhybAn Jjw3uOIkOrnjvbQoWMBAwIak64wUJk+SqiuZzOIjWSwU470uIG4wssnOuMUmM1WdqKNfxWVMgPjM ytznqX5xvXrM7aoaWnFuwpAMfmxY3KsJqX5k2UoUyF7yrTpUEsOOd83/cZvb0ErKzBD5d3UeqCdn evKLaiL3VME8V9RHONTELzwPm87oI64gFSggQPPjBwTlR+0sWaTK8DrUeJm21kAC4DMjw/hkeJmz vQw6j1eyFiBBMTigWY8V9zAkQp/nUzpToJGE456v2yBdT8t+Afpm6h3/sQjELf6o3Rwn5Sd2ms7w 0g21Lt6QTRWkebQuP9Y8kO4DH3yjY70sJefIIATKPabCkL1KSTMQdxvEax/J/Ft5aYyNWg34DuUK N9RMdfOI8e1iayTzpqasHQ3MYMouaRIsotWzL0oVb1bd7foxSAUu0QrdQ8lJJ9FJdoR+bNxvThvo foVoLmB1w5s5lEBGD2MihmHUKIpjEBN8qsxeAo6ZMEwTZeV+7+oiT3qyiMeTaWz0sL247V9KaPzu ld32gyCeGEhuY4ilL8o4ScTo39/kbc+SJJG63D1P+lUW//t6x8HurSKTIOzepk3pI86C8mPf8P0p /LQlWtlVbm0Kp1tLfNlYAfywIjOdVvakwaUX6y/rSwxgB8qnMp6bQMIzDkRvYLZy+cCFdMVap5B3 vJ82kmFe+3f/3x4a3BH+Qf9SlyfhNtS1xMM0DStzRgO2MmZ5l0XVYl/7VEPy7slGUFFeqSV90755 PjMroodFTnE2zgBZDeut2ODguQXs+vcyi2xVtA3m0uwqGuSNfg1oHgW1p61peOXsc3AF3YRkDhf6 WDtguJ66ykQ60SAm5LLDAM7bsauDiSaGsLHPhBcmLv21bcvymrekCSfY71NI6/OWQWaFgQ1S4H3h +3r7U6EyuGXC3OqYUmvTQjGSA/aNIk2uyksKmPlEWvpuf6ey8wbU7X4M37/mVvwwr1XyIeLNLX1o jy6uzZaR1kxZ2vcMAp6q01wtFHrk9QS9dsA1X9IUT9Po5f+L0a6OFSgODgXO15dkNkqdHDfmbuIn 26r38jJuzxzN4LWHqG1UEzNNDOAKmLXPJQcTlp0k9ol6XhGcdpCIIT199HPJ1Ydt+VP8oZdvM3iZ d5EpBqMLj4VGcu/wZQOM788/s7Ve5zxWQl3tCoiwsUfIupuvS7xHj7AZKQ2PZ0doZjl39sHQLAdw auFzMoG+cbkgYAr97RlOl3oWL9E7TndnJWnWp6SsM4gQvzCtg+sGDyfl3JUPdAFRVUgunu6A/1pA 19iwxpgS4UB9F8UWCLt99P7p11La6kkCuStymhN/kZLJLwhGrePWghaGhCqzQmjUtDyt4qTU/Lcj aakRx2Cwr4A3lVcqhXFwroquiWa1ifGlvkrRB2A2v+iDylxBMUE9OELUEBP1/Q0EsbW3Sl5nqgW5 HdNlUxNHSY/xYCfXrILv3NgMwphqPIHxLOqSylg8fzcHGP9j0Y0otnGyC0EPFhyjHztODa5iwupc 13aqfTttfxN7ogTLClmO32SkcdmdqFi5Xgf9kA8w6yZex+27Q4bmR1z/5ZCqvq4YcHwRqr3aSrJu n1JZmNv4zr6vSEk+vaI69fJfFfCweRdmaV7FLvNke29e4GNYmoem2Uefu1Fr8otwRELYFNm0+gRZ A758p5JlCQKnv9o8u1z/05WfiHw4G7IsTSqM7ojKuGRBt9/xS4eaeeSfOOQBGS2UK8eZD9L0sPHX JegLqLnTlL0NifQdiHf1gS1hWYIGAwPiduIST5TYaSRwGAkgrq7sDj0T5jhvejHh4NdSikLm0O6U X5MH4rQMQxBPVyQxLhreEFPq4zE3cvQ0zyYOLKzuPjJWPiSnt29YGRwM9yXtMu3A/Wgi/xgDRuNT wTTtloLcZVa54l4YfrYaY77YgcnZKaTrjffBt6G1S+q1RyB+/n6S5ef/ZYQ+ylH3HRPwt8XG65Ih Gv/vZvtJqzBZs4Sg/+Fh3yR33J+jyshZIsRvVjPPGa9+/1QTPX6+/5Ncxniod5B6yd+4hPw56L05 hrmCv6LiCcx8frOwdswcHvYOh/65OvDNhQl1aS1WO35yTDNg7ImnWLwQn9fJ7k7eSyvVgcnZme5f QppFyEHsyKj6lfzSgPsGthItAt2WEAZxjOoubDehAHhcaL+j90u4aVcxVdWt/V2ErQSZTeprxNF0 AWe/lgI6PqQ9SxGqhmerNSx7T1uWUfKVj2tbWkPgr0gRAwugGacR7WkHpSYZARmjhRc1JFA5v6Mf GHidl7tQzPjlkJHW79TaVD47bkAvVO9Sften7Bt01hpR0XyonDg1ZSgtTawOzwKUHqUFZDZsznsh cBcrTwWbyqGzYPQuvf24o2KuE+dQ+scmvlLieUXMyxskasINifTCm7SuCpIaGbb6IoZR0zxe2Ald 6ehn5Z9axToVUAXidOFBCQuAM6PIoR/Hr/8i0dIfJyUGBJRsyOelHUKj9zScYRDo298aTQQBcqmX dvYSvVG1R33CenZsRL5VNl5VgLny6EOscBVbs2bsMATioox7ab/+UsrrQzk6Bq302G/ug0guZB4Z KYVlhX0DjHuswbgC30lyT3NS9U38nPlJzFqXX5PsewN2GCn/G8ud5roMzBISnuiJ3+p8gtoIMFtn m2MJWZL94VbceQ5oXgIvMa6AyQArsq9WKCaA//3nqXyxSqWtFE/XHuZzsZaHAIS4zu9kvUl65Gri 1mHdGPyYS9tCHd1AbrIv3tTyg7S/gX6Wjl07bi4KP71YrR0czmyDolI0MUQgIb1zwgDIOFx/6VJr 6taMoY0J+LDFzLi3Al9ZlbGiNNSft3nUrVbOu6MOXtdD0/Ms+GN0Yh4peP6/E/nPnFgo2QPGLZTk qD7Stso7dUNWEJQJy5E3VLDTAYhpLrG+8vPm6d0pFi9zJ6IieNifsQ1ZmRlEy9Inil2oHv+XoEOZ MjZwjIQns4HDqxMynQx3Tlm/N9JKAIqMN0+K+oJqUtpRGYIgbAEcdLnYTl5d1RW2hSDVJ/9KXbHQ oC5IdYKZtuwrAKO+Fg4D+uTaGcxx2bk6i+do4GAAR7pV6+sQU0NDvwZkQApp256iNf0QDLOfGw53 g7LqEqBUcPjvC7h2GFZ9canZr46mdJa205VRuDaWsLxSmlSPGHYSJFpqwV4zm7YbVhe5qiSDSpnr uMliprNSmrJ8Zl/IxIp+FKABdNpMrUKnWOhXwOTFrujmPoPzgf+Xlo6Dsku8iRRRllOG1y/rGl8i cua38rSWDCPQ5PGBTOFjpXmq/HN+yGFGKjoMzElptpC2LOyuXO5rYNeI8i4e2Ev28RbJZYPH55Uh b/gOzDZgezGfcpuPgPVwevAIO+RacZ2wXmwI4AcRfedreA8ElzYFadvTIwGiafKH8pXkDyrAIMpC MW4x7gLnxD2WoOsDPv1ifEHLKErMMl0IqU3sZVhPHyoVsB8nOnL035W312SoyGvLwCAcG3ZtRs+b BlWnznQjKrTJNka61cWl2KITXZI1bXVGYnJ6Ehe0lkc6UqI9tULwr05mmsLo4snwnXaz4TJbltsE wo+sSfNcMRTU8CIrcpoYP/p2i9AikzOoUCWUgXBgOr8lSprybI6Br7/XaDmaf6wFfuYNaNiruTHn MO1Z7XrrsWGPMu22Ega4leMKdq+/15HbhPb170v0lXxdMO0bReq6ENabMkul+JAphpgsxizZCdX9 OYzHvgcyvCFMqMWWr8lxRIfBem9rNH/XRiIR5wBXePdXPyCxe7rTIyK7Esanb7kgbzy4tznsGpFW DPaWU8XCD/I5qyKFREEO/xgjyFYcciWuSa01MvuuNtAQmLnuJwHqJ4KSp2Tmkb1ip2WpDjc3RqFW mCxjaLGHrgf4BJ8jURsZT4cTlRgwbV9Og+URKnHlDUT6oYC+88PCSvx6DoL8qpEEXQ4uRCYFFC1R Hoo1kjQXfv/sF7olEDr27VxVVp0Xm6vau6awLdiNBlCeCBOb6RgTS/EHnUGm6Z0QPrBtgdpq6BMv iS1Ok2lFPO2cy21v504nXSruWMJWP9o6ee5cSeCr5UWgFAXcok5MDmomf5xGFNbySdAAMPW9Xi5d bI4i5a+ZNuYei8OA5VVKT7RN8n+yvQELCKfaKsdMoe/VetBw+Vc4tal6MIn52s/+cIY+BrFjpvg4 UgZe+6/m6JgvX+w0/zfbaHfrFIVfk5wE2RJngk2y+bPq9Qcx9m1K3GNi1q8YyTGx1b8deNti18ra WeThQJJslik88D5p7YTtprPvg+jZUnU50Q8nLcFj52GNhUzVNWjNZ4RAwaePiGgFmp+T7v2KW75y e8mhw9rB3qAAyEcL1rTEIgrj4t0bym9JQHOeZEdWl/yCMD00Xe2Dr3kOO56/8YNWf604JKqEhwug qIptUqKqjZC/jFImNouIpC1qV4N5yfSwgB3zs9QtTM1EfZrduA0WjED/n8r9/QQ8lOUADlk3d7lO lQsi9FTkQ8QjyOVacm3Yf+AgayndXjB5ntPevsbfpJYDnJZc49/Bc0zXgezimy/b4xezEHjf0iWn Vub5e9/u1lMjy+HB+Ex4Re9RPj2I+smkrv5L9dqlrOUJt1IXkocraEFMtXcdtRbEbkwKuywNHwEa bIpQ07Zb0Rb6t2Bu8cGd5jVwX+j+/noRlHbGVc8QHTv8fODQZB3eqOL7TqYs5vAQSseInO7yML3M XagRn1JHUUjfftUHSyE612MPtmWjF/g3m8L9QwPpKJw3wMLw3nPwjU8XkOw4bRv3/JCEBRszx7BK BfdslgqegdtRsAeMRzwxsoxg8VGdvUn5vQ+cLITkc3uKePC1NxtwArhzd4Hc8bvO9vFiWj3/gMcX lYeVnd107MqIdWkBoKW+3R4TPxjWJm1oXsxE7hhxV9utkW93MJbXwIzIJl1Db5sElaHG6uJRVhmV 2riXDvHxsI4drsvWelR4zTsmwlmp5rxwe4uDjuYXN8vb6BBX4shqzzdRtDVJg0gjjEl4ntGpFyvy TYWFk4RnYgaS5WPXxzQK7vN1aYKpwrGt8Mk8QH9FhkSBWJRkVkKlEeP8ylpNEi8QF5MwYrc9kpLh TLrdFTvmi850PBFizIjCzIe8JTiQSFev2g35zXIhaOCc6J3pDJpcqkVgHbqgwS9GLCCaR5r42kD0 F0eRcT/8hX5HDzWMfF0029sD07HpNXCiW6xf6q4ymOSpvzmaHeKgdWLILhwWw9qot/v/DLw5B5Fg pEcvlxFCVQU0BAWF77ngo7E6eqQJ/heIWwxFCtNv1XotMp0oEwRc8nWALsJT/NBtGuecBalDZqvd U5jvxJZoJ0PSXFNUR1smkRiP+LDCuvpMspJRrOIIMy+vWdggxjSKTpRxNy0pzklIginNr4XKfVeQ 04pOl6W93AO7688nO77Ohce3B9v4XH+VgBs6cW2ef0hB9M0qFnkBrfZO3hkn1qf+iX8xN3IwFbDx MP1OhK0as+cANbXV/W6gVgH5KpFZFtk0FH9Aknvtxe/HHFVi6a5jnr4kxCJRAsxecW5QyWRR1BjY LzFWYXa+h7ZznyxaMjsiYtpiJy0T/xwOqgjDmnAOsM+vV22YetC+gEfu2ywQ5ra/zYWCB2vF39Q2 sLKW7IPbgf1vXe+dMB0aLgFUcqFVef6B/KOmC9VxyElX8i9+Wgz06cN1CI8Omvy2tXokKl7A6Aub 9OJ/6ZIPUwj4mNWYwNTzZEvhjc2a1Yz988iZf5Ev9orRLd9IIc4hZOFikRowu32Z5U/i9b7KtlVj wyQ1UxZKVwSAPdu1DipdSzhmBNjXgu3s4MQ43jqXRuOSD31d069K4hcvFDAyQbP89asFG1WeM+cf ZDOGDkDfGwPgaQ1zJzpy+g+U8ESATs4df+aEY5OEpVkVu4OKnbeJ2BL3q/W+Pohs5TRZc91v7sTu fb6L+yXXvOOkxOeqSdPwAROZOVGc2c6A/sfDSfwxzky+vAJFtv7BtTLTULLOUz4sn8DKCl/i7wZZ JaUuJAbN3pLzQctPeeNibGeQNslSJbvwRx/uSOAqtrC3HUyDQHOywjyDbCoUlxJ69aEqvrX3DVuO w5dk8XtAEOkVAwZWv3njTWeFNS3+8ZTHacBD8I3p6CkFLT7E4/yhZGwdS3mtonXUqS0ItPh3BgdJ sNE7KTfKLVCAM0Tagda35FMyTy3eGdlSWl8Q7uH1/RG2RwVgicVA1lh5A2sdE5LH8w2QnAmt5NIz BvnJT8aW1ek7gXQlJxZJg6SYaTJBvMacVXsyLwKJP4frqhAdslxOt70I6qsjY0ngKWQrHbf3/Csm Js1W72EzCOrsA/jejAqIYnxXIwYXQZnMv9e1OF0HnOdzvKuwM6H8a2SimJsz5+sYmC10vRGAKxI+ /PSGrue+aB0NJqUrC9c4ZzMIjUoFeZhCi3kH0aU5sshgPsDW66UtCJIy/J7DnjL0CdFMaaBsKrqL 5qXmBXp3Do1qcsD3BFwsV/fWH21yVUsdIxAFfRWuov7DF69I0tC9prx3RmsC6mnSX4PDKC09uwjx zbQjE0gKbLClLVhOIAyhUOMveWFNPdoAglhYvsqNz5b7kVMYDzIHX/0D1yIEjwYiGdo9EZZWbBiv P9IgfcuvBRxOdq51f6Ig16L99BPzjobIdc38KLJ9PA8dFHoY1WSfqWy3usCdXpGJ2OIgA1YeboFs I/BuuesTuk9vs3VKzIO0kyrUQLKqpQ9cAj34zyeMrC0stnIjgfgSkizwbRLnPhj2rGJCcF9DQZd3 Dnbw7SGFDbotctj8nSVFnDOnMRHmy+R3m/txvGzJB//zokCIq4giUxIFWoiCDXE11Eg1q62T3KQz N7W1Cyd136c864oiKtrACpQB+n6M6YGFlCSshhy3GmubemR5I5sGyf5dSmFyGmEQinLmsZFGg1zE FNfDoyO+sK3tERV1XBeza6z/cqc+5VRqZ8BjfcMK+n9TXyi3ZMvESkmpyFo3+n6R6IM+iZKeAbNn ZhRhlZin994YVJQHp5G+sC9sCZUxhOmj6K6BM21JzUzArDxmdDHuiUBAkVN0fdU2Ir/Y1ODyAGAq rciJ3pb0DK1MW/xmuKRqpwCmjE486MSG05MWRmpDvDpa+yF9HZHQKOjk6xmAO3fhnBBDlgjlan+X n+G/xTbYCiBILyLYtngPkMrR2dH3CHgBWySgk/Ue1hR5OHDU5ALVxtKacy6TEklldj3KAdQrCQk0 JwFwlMeze3OdmlmVt087rs//JtVDL5RxP0jQdndJzUenHACa8znx9EVsiNb76TbMc3GS/am+tayy UiXpbTO56r1mz6tRJLjUSTuQHctlkksIJ8832ajvykiZ1Nxi+x7JFB/mDVJqlv3QpaYndAcpBGJ1 QrEXorjKlYnNYy2Eg95y+XhGcWn/r7aNEr7E5URStPvYoXeeHnLZszJ4wTb4+TGtMYg3nvXaDPPs yBML5gKgIZZNuzjCErjEqDPGBTOW/kwoYroDd0ep+iUxbKdlbK/nDNGtEoYX4IvkSR7DVes2dKq1 7/zhTGW0DA7f1mZEQx7C4DgQOwqliDtJsbc6AQV+AxYqAfO5YTsZ1+UaR/V45KwUZ1iju7YG82bU i4ex8rqFUrEVWoofVZm66LRkousde9wtTyqJEvKz69RYKdFyxn0aJ49H9aekfUQ6dtscZ5ZAJgJw F2EhfSnJUmHba4MND1A1S1mxzG1S+1XX9GGlfri4fmGp4PubwTWNe5bAqfz2hr8meKmVROBbn5Q8 KkIibBkIOhgQWsabHl9v9lm763pz+v1tnfvoC2pdkLD8AhqYx7Dd45ZrtpHRzQQLxVUQ6ytbzjSB 0OiiO0tCN7aXpZJngek0SGWqMsbqRz2c8ya2LGooPw+Rk8RqSSsHuEsA5gMZdFGtEYbYrx/8QwVW v51A9LPu9u3+JqfEFybZcKiKGf4FDo2R9MA+MCr1Kpnlo1nhCjh9A/LWDxeoLHHzA96fV+h7uFBe FGboBbSa8O0IriXmi8seAOW+UqlRusMmJLwCfyhWyXP63XbuFqXJTgpX5da1VjWO1960eFF9rypQ srIF/u/d/zNGXQWS9LrAcNlVROT8wwxLKXUTtR3oi5kXGasT576H8Kwi8+8wnkRm2CFjFdvd9p6R cXMUHZlC7UXUtk9RBnkFVJeluP9OzRmOl4MtpTvomQjuhc8FE9EtEcAVtF0HtDicQDrwuR21W5nu lDFLNKv5eH3MEllaVYGBM6udQ6zytMwGhhp5YRn24NHBBOAUaeKpCLvXOsyymQxUu0w8N7JXL8/6 fbJ4+fGy9Hse6tOA7PfuBizapn2MUcgmDaMKwnAuWP4mPpRpuaDxiJ19xhDghM5Xm26p0bXZFgg9 fKxK3mLg83RUE5PKYGgBPjELVsWSBAdMmNSOfycGROAnZO4cqGoo8Dhtiev5M1x+8vdd4xkpeLjF 4fp01gsTwlsJgLQLFdinH1R9FYSzsjVBJywNzqfY3ocodMexKvJFEUIRv5rW1RENvC/Bwt73l6Zd vTdedyscP8xoTV6GLWb15h6Vpu9wWSir1bsMQpJyLTRCSUgplmZeKANcR598WCPcxGBQnHmS2zwQ cg6A9DWUYnEF8m1NkPERbMUBNPAh88b+F1eA1ZSrWsEKVvVb6CPCbeGadCw4PI3fUbNmRolAjQl8 3Bmj9IuVBQKmty0Ylm/BeZK3v6O5A3MmTZPo7NbnsyPXxHUgRO7F2lxyWfkz8/WTQFHgDxq4nUKu XG2BjxyX+JY+MOP0I3PqVM5G6hxapIo2xWJ9+ql1VOHMQJLEpBdx934McdtUy/eTB/6DqZOgzN3h 9KXTVWKEpALDbykGki85FKfsGFng4AO8nlu1sEvMqBxnl/z/5zh5w5TZnN+/sdcIcYPFaG3MRH2x 3cYYqZNczDovPUB6aZNDnmA3yNG8jzkCDLqNqAVtd8fpFEa2WnuVpcCiGW3LULtOw4ogDryda5la YIwokkwLE/hGxe3uaJRPuDh6aT6pJbLiGiNkOf3Y9YnUY3zKfF9777y/9VSoNu5rurYf5oxVtEiF hx2CqaJJCoyyTdgX/j04t5Ij22XGUwSAP6VATUAEJ7ZuQKi7xpMh3oOigKm72QDTX5GvxIRRc6Ju P5LM4xmEmPTiPeC9w6wY12BhZwUAglWG5P/DxiL9ZyLVA/F2s/k7AuG0VDG1Zq+zQsUbGUSI3FmM Q7YF+rpelSQ0ors8PM4dsa0YCuC8jun5YGEGo0eAS/dZzC1CCvMLAtOmSKnh0I230cA/zj7v7W8p PE/HioXKb43sFq+3wXUDjtKdiNysHv5V7sI6b5uB0pIc0tr7B7ZPcLabsbRQTGzKdpSnfYaU9acW fzsbt37tycvQ/WvHjFHryoL8C8XcexPvE0Fv4JLEt6Nlw71bO6/f2Udwhl2KVhZ69e7+2uOuGVZg 7aX6+5+PNMO6G4ctO/SwndxSvzJfm5b9b++ofhYrokN+BXvPeSyV6AFylbivmaqzZ0L7SlTovnkP Qi0NTBtzV7OWSI4m23Lid9egHtqEp8Y7B7vGKG+xeIgVDOecPdqxH2AmgKNqhKi2buTOsdWNqqwR RClBAM134mzc/YO9s278csqp/hkFp7Jr37xt8SFn86NB9LH/pehoTqkIBgEW+DCd9gkOSiQrA+Nf i4DorQzpXGBMPJ7rJ8fjRC+47Ym4//kiH1a/i6TxEAO85I2VNCSbMr107x1W7GBvABt3hfpR4o4a /FkMtpggLRPz4jydmUoP6Kuvs/BdTUwgGbS4erPhJR1WKjKJzZa7PrBf2rcnQCunrrZostk3N0bj kOAXmmE4p37ZE2r2wpZsrl+kG0D/4/9aSbSwq2WbnKVbpnC5sS5pO0skeEhBzJ5hGMke6YkvWtRb 6OO0AioPZsv8t1gFWnyccFJpgyw+meUFoLz6IcY64h3wUVxX4LwQ10DSRbsoZN0OeZw+7o1Gi75I gfK0hFzgEfHxt+tNUSO+9Eh9vuRbtFmnhJs5dlcY9FY5FNY0SlrKq08VI77JfzqCbEK6kin2ui2W i8IuUBqPAY1ZwDYt/o39NIIP1sYjYk5LCpH5APPQzTobzoXBcvyRWDhanYXlJ6i5vRMXJUOqMDh/ DPgNpVJEtxYAvV+plfK7BWNMhY1M1zFsSoEBVkSpaVj6EpmWimaZqaIe7TxCDvB0Fdtsx635ZS/p rWflsVtuAgtouJYB43MhzzGEZW9ce/ZW0xD57zqtNKvhB2aIo1pDgQZGKwmqwn8YHDtOD7WeZXXW qC9YjVCPqumCFQxFN8NPVYzX5MvLnFuaY3rAD+vXz1VsjkwbWARJ6sQCZzIlQEYRtRbGAuCAMHFq Fs078pNzn7JwfgGGqGUECNp8HzxE5zDkLg6UK7hOCOYhMlZm6EPurLmNr8tOOMGiQgvQHU0oe6Hn end5w0IDB//GrGmz4yMECeoSRmwUUtCRXTe2fbnC5cqI4ZQBl7VXs/CiuKpaKf0Pc7Bf+BpJ8WVw 6CC2PTYylGSfVbjMzd45GO7TkTNJXZzXCh1LQEjcFZ/zAPDmxa4EsoK8lmh6URelseis13+5QWRy mgCcaebcXtbND/5K1kdI7IZwWmA/27pb2xNugPLZVSl1EE+G+aaTuhEyxv9+P6e4HWZcm1VhufBp ogLghFd5lFrBL0xNplwLVrus4uQiJe8AJBwNLpJLly3HN3yctZ8cPa5djwykNzR/B8B/2686eVbK dwd2WoTRprHz083oFV/AqZstLN+QoOSA8WRRNSEMfcXTjqHNbbsquUhMkveP1KDafSWAOeUPx2HA XHz/lntVjoHXw8ddXJMXXsKLaclH1rZkydqElwwrlKIwKAZSupJIBod2ngX6jGU583v6a8JPOCy6 8YXfaGosRbjCl+pfMfVjQJ3GJC6+L1dXVTkUFch7017GRC3V9UAmO1wyslowUaN82T4etJNjhFsb NwLN+1jmuJjZxx5zDaeRVhBSkkyxtHcQyy8JMKysig/Q75HkGs1AnI8ktRE1K/lNzTYpaH7HlNkD l94PlVWZCrUHOXO+rsu7vZgbmBsjmFeDaWBsrpLP6aPKQ3NK1z2fALBLbYx3vkQBjuFdyO7CbP0n 6zDi8zCBpJSyM3mD3Xg2kSSKHVuM4hqiSzRawl/vxR8kzOyvafizYjCM8r3iWCgFk7e17bjn38kw wSiZP1nyH6mz3NEOi5dt9RYzz1cngciNfb51gfD2YAnr62cbH2nZ5yOsYQl4wAx34sxw2wSVjxW2 I9SueaM8yMtZtnJJwGs0nks68p8jF7navfnBfp4iHeq3GQk/HH7TyX9PfIYjvcsEnQPnNdInd4uN zzV/XUY4QFNI5hyau/4xmHktOBZo4fd1B4f/7GgytQizdB0buE/NtACJU6bM31Yb7Wqip3E6WHOp GUI3MaDq9WDryLX1f1nzd5uubnEx1Auu5iPk9lLXOhGs9xyqyBfgQND9uy/SYJ/jzcR7nEFPyeYU BP/hiWiiJ/9nQBQOwR/lbaSKc8QhFCA5t/aowEqfZQW3DOSIPNJn7RxggXE9EXmeU+9F2HDD/1Sw bEtKT7McQLfnV7HtarhPFzYCbffNjFevfkQg12MZkb2d/7MxuAi2ZMSvzjr53WFDRfwxMknqCaKm 0HCYzlsWg4xY0hcVNBfu3N47rlzJnv6zbioBTAkJ9XuJ3MajaOaKN41hpSPSvesbq7lO4JdsOMhb xmSCAi4RIbHGoeqIhArbtGRjq5oZ0OTj0qqV3QdBIflnQyjWPFrAsX/fLR13RKGnHc2ocPsK92S7 FUoiK7wkx+8k+Y/epb2pqat3hHIu5jYBIXJNpg2NczxFFzSDLvf1FjVWg+MADYTK3Dv/2AAqvkjk bn/uwNSAVsNTUBSJ3PZOTZgytfdg3CMzXFT6wXBfF31U5+TpD7kRGZWMFDMCcPc8usGenyAEUW1u CWvpPOzQGU9KHXRDY8gX8+PCvoLVyq+LpPhfSiVsRQptvPG07v+mSbUTBgNUHihOzHjVatxF3USx BC2ezOzqfGX/FLXN+qeHwu/q9oZSaoxoLg/7LUdIJ53xXpgA/SM83aQ8csG3+lVaaELHJRty5gGj kBQenQKJfmOPT22YMj+PWshh8/Q6KpaQbOytFQnjK+/iAXzvW+NHD44u6Rzw4H4rhtoNuW++u5kH amNoesZb+L6GNaLNGIl+cD7bC4kLO4xzgjIOBDlwIHNjq3NLzV1mz5QfBpiJI+jC8Ac02PO89fTK RrwoJ/XhxNI8NM7YiN9PPTW7AjekKoTMm5B99EUdNEe1mBey+c25h0GnxPRdlXrlU/lJPQMra+pY EWT1E2J7vBg46vRHL6aJ+94c7C6U1/sONx0ya26Nu12TJmkhW98m7twplHnlfJIgytgr5mrK1L+m Ki9ffCNRyvR2MvBd6wnTtW7R/eJXgqjsXaESn+oSZn9sbsEBtuDPMNVgZzXYZWymD2/Sp/BQ2n51 VpDn0fW0/p4flOra+x3wX9QuXEsoJWQfh6hmcwK1pEkeqX1qAiwyDO8lbrvEJwLoazYyY+7TnMs0 gvtO+37vwjH1MBLUFHLNu/GzHS7Dom44rVhUm7NNmpi3g3AS5UVdmIc67X4bVn11xP1WxGXKhRR2 /D10LSUR6DnV6efOKofOXmwq0j9vDweoaM7C/xJCfDT8ZMlrAp1FGTSEezmfGPQuhMGcfSZp59ij gQN/dN+gDLAv+M3DVtcOY9bEbIsfIhwBJV6++hlqPzI4F9xJPWHVqmXzLvlqrrXQ2ggP6aMz44f7 HfzHFFmWTErilXUVRYiCcIUh99k2YfemsTNXJ/YtUOFfJffiXBjDcM/1SJm2GrsZVV0px371hh7W gwpqealq7Secqwce6rB5I+hQXY/Y8sVxG9OvhOk50/rjUR145VLNgVckBh702DW3rtbVDcVMrZNc t/WkLU80Is+df0FpXvlP+ZlDOqkF46+ZcZ0WbObje2no0eLhsdwR6CTGRyBjR/uR28zE5JOVTQFA Ghwa7/O8dy6ac4Q71vyjU0FgMLCqkYMJJeu9aEsjsgIoDqMi/7lM2aV1qO4Wm5NIEJjzq6iaLqRk jHlHmva0y8GjkWrwnwDEeGps/eREjI8Qklu364A/g6cne3zGeQr176x/hXXu5keqx4YJ/N8O5YgC o4zhZWfH2A0XHlmzgLL0LKGIKLV72sv/ptxnGIKs2GRLMPBF6imN8EPpv0NhaS7wXUoiYmL8iYXw ii0zTikLrhVKZTLx+hAA7IfbrHEo+YuRQNKjLEp685CIMMYuIHHtX2boiW56Bx1HAaTWS2+75Oem lO3tJYO1tDR8aVCXLS3lcWK2Zkn4EOa38BQpkiAGdGfcWZnFb1Ck7kz8QC3m6gRIQIw8aTDnmhay 7R5wgYFr+2wNhtFj/d7kUZ9d264TJ4SW8CJDRjv4PsviYFjZa63N8k0QBnIRvTjdy4IKtlshob5n KL4T0nbwq2qmjHauQ0QOY90W2y6RUdWYDsLqLFAEfZPcVzz23RQcOaLkQP5awb1asiUOWdDYOLm+ Ssw5ICaUoJlLi0KLkX4y+/h8z4dFu7PDtOVQunZjyQLPnR2wPlhOVLV++G8TfxPFeAnRlgXZnHBG haeXUuDy6yPzxiQq+Ufdds+RmaZvh6z7HvNS8S33qQQ6ageXS98UwRyswl8RbYZ+HZ6LkcCL0Omv QbggxLU8VkyDYzOPadGoTqelj9EvIz89DufzlMcMjp7nM8hJRb0CcsUpu+p3ZNP6ex7mS8FRdPmB 46gjDvZD6EBVmJcp9yl56GwrwwAsgoDwwgjdByoguIj3g8ovUbIkKnGzWMUNBssFJg/3oTbOvpxS mqS2QiKd3qsIKN6iJJxNTQcQp1QXrdSExQtrohplVBfPT3dKot8Pl276ypFT9lauAYm+O1Cdqvp0 +QdQCmmyVFZ2ni4/gG5NEqNKwdf7+TJi0ujDgSqusxFLlDXDoOEAdLOlzNIIU2Hmw44i62sNxpET eE17zVPGoy/pBgEZOK7/hNciWZ5oC1DQAph+yvdzED8r/qiBhsIbjXSZR/VFGyAE84nqeA+WfMzO W90ApPxNuWLZTGRdLNa/yfJi1VNh4r2w3oilw7kj2Q5Oa28L4Cdz4w/UxAdKqHI+HiYBLLi9inXO PBemM+XcxM61jpqIlZdn4WXchMjAKhik4oFEU1IAD6Ds4aB/WZTZEtA6nKmr61RJO87ou2HR010f 0+T753IKrfSzU4zz4mN1PGfl6pTAgxJhqvnARONLCTwwyagDQ/DQ3n3iGDqlZtp7eJirYKupK8II Mg6hVBMvA2OwK15wXd9llFfszX1zupBxxfPjUJXKFaPiip7rvineK1bgMZIt0OduXv19tmplnp3S 7fZe6axK/YP4SIimlic8+W4oGyW66h7E9HwAxApP+mSgbo5d6/Hhje/omi6h78pm7bbgpN11/Qao y/klEtWXEJUyKCB3E/OqcrNqGBKEU57pQdrTMJaTKx/eU0ayrnXDuhIpkcW4VfQzd4kDoYXs6ymh 1hn3A5nSUG2YklVX3p59UNiPT+Ligs16RDeZV1doQKeWkV+7rU29ycAaTEBAUl4Dl0U+MVQ5+e7n NvUiC4LKt5rry1DhLywAhRWRWxyy6h3AfK0ov0KMiq+PzIn1caWD1LwGJxTN/5T7aBDEftqfcQy2 KVhfXJDSGnTUwCl8XpYHpZOajruMSfoSOJjs0BDye/tZxzRmHz9h+c9/2U2YLcXZrTFNBzD03xRw HSnBrVtPzcK/aQJuZ7T8gcKHmo565sua7OvEmG6Am/a2RkhFBLuD0cEj2y05OBsKAVBxfa280eqO v8WNuGgRECUYprB7DfZwQzysSrpaVkzzPSqG4NjuFRBaQpwWkq7YhzkKp467Y1J11ExX/kefzk9C qcdv2v8yfMbVsnqgVT6DAuh/xch5MgQHVx86hGC465QS91+o22w5hLdC5By8gZizclaW3S1xKxRb eH8nwPpsaXo6l2Zl5owCQk81FKEm01KnJyIMHbfCxjHubX/8MOyEhqA7RB3+7ONCgET6P4UJsJqN QjSuFgOSqwPuJr85DBK21mE7IBFs8BiPqw7xGrpf2m7GCVvBvjr1WMLyaCCHfiR5qtz0xSPvwmJK FEXN5pDkXhIT504nN8c2bJpJ4wcUIBrFh0VNgeSp3MPYsSA1T6fPDscdDWIOJyGglJ7cE3GMis76 Pva7lvRQV38+cyUhDv4yGASTvywEF/1gm43o5aXSpyLtSa/j0CdJOzdUckfaPTv2zGQKrP6nQw4P CHb4uPy4SygML8CsYVEl3RaGiKNGxXixv5FIdf1w6tv6KYjNe3vZpqCXROQ63SqNCJw0FeCsx/vY n9fBH87BJJN/OdAxGIUOEMiu+s7PnGSCR14/kqN4uqXffoo6OBA1J6kDWs++gu6jnNca8geYmOiK HbEZq2Su3rfPa5s3EQpAFypVMnAmOlIAHFaqOTCo/zCjm7jHSX/A9YZ7JMha4sPGN/xVmv4WzyIc arX1ntDE1nYDbRqjeiwx4kXLHnPbzdKSINrRD5ilKk0FQnxiKBttCFvgq7DtCBCYm6QWQI4WW2oq OfTyKsTtgYrAGJd/wqcRQshNIRp1UVClcfOkiY91gEIM1eBKBLuxPSm5mCYXfKdAxPz6icTzW7Hs fqqhRBGksoJqHfUAuv73qIvtx+tqKByz6ZeKDJjlVQbnI18BLt5QQFz4Jw9bPRg6GlMO+m4hW15m uRFxdLeWyBvhGccC5lIu9/3PKxLvahI8bYrihwVxw64sQgSfQBd1E5SMlsZjkNa3RwuzUh34G8NV ZM35qjwz9siBNg9P2R7mLKj58VRIbBkOwIDDK7jClX9EqMT+OV86z3Nk5xB2dU5rmM/wgF+MmDnn uKWKPERSlEY0c0jasJDD7Qzn4hT7KsyhXs3P5AlQXIc2FtIT586rILiQV7wpllJUtOeHC7Rz0aGN VsjWpB5bgUZcC6S8TI0HwglhjBhb4p9aq1wngn12MhnTv/5iJnDNJluEdAWk7gv/gLDqe1oOSDHL he/GrXlFdCa1NamkdhNYkHrk+j89HgfGO1W0SFNjleksQEBZStYMpFDTzpJSGLg9xNaIPWZt9Pm5 TvoaU2BsGmxK6KEN0ci3wBVc8Z8xdLz04lTqzaHLBIkMUB3Yl7UMQUIfeiHVjTqhbFFZJ4YoMF55 jk2lT30WIQ0jMIPerLbJHkME9SmuepfSboqN/sxajUjw4P4633PCsnIGMgJg6QqwpoedZ+GPakv6 jASqZ7NCKjzCvpXmul+jAoWsgtg90/61KJMy8c+ZP0R3hRcYKbJ8Xp5SM78eDMRB81WFGFnFsuNQ mtr+cU3YUSrp5lyZvINP3ufYVtSmaNo74fS1RNT0GyM8rjmojt1MKUNKnH7yPynxrrX/gQK6O8Dl UurWZErXuNVupGtZSlm3ihdkaWR2atFHvHEKSvfLoWPtX72bcCybefD0ESeZ5N7SHCuHDSaETjJ6 VY47xjnuOYb5YPVVq21suzsV7JrV1UuBtcXdHuHAmYDO91PAGYKcDWNNI3RsCE5F7VSOZCjRbjRH 38DrD5Prn0dpID8mM73T8mRDvpkEv3fxi39Q46stUSNQYikxFcg5EeCWS/rL7ckgrD3UxjEFYcxn 8YLN13+prH1Hj8bXUw0wmCyYvpwfr2JGQaJtHP0EC8vNMuazICWKuCU+q6DrVsrUh6oOe3RRBgqw uZUgcxTfErFSdDzoT0yEQxGkNupGpKAda7nXozpBlc5Nm4ZI7wqpepaninP6b1V0scwwBbEZ5aQZ dHV6XYSnK+VOvnYw+ALaJPfIiQn3W2/bDYWpoTVWq8bVc2ctmE7yjPmVVcWhYYdmTC6YY4DIiBIF sT2BVlTEApVEA3BxHfhaTNzxccFPWEFEDxUrhbDomXrB68vzyDiWNIOos5dH1JWSyOi9cgYOBRIQ /K/LITVZjVErBp88adyYYt+wqsYXC9HA7voXUrsMmM3fLIEOLCcnF7RV5TWi79jcORy5OfV4nkEM IR5QcLiNGbY/YTUXV5JZ7IhHknsPB2eg0w3xXTgXXT5dnol0ZTQLoFXKrl0DjNd27f7qeq4afZuU R+5HLBdesUf4TlDc9ayaK3eapZiqkXCqe6Etd8zJM2zeTLBQCK8ED5Nj2Xjc6nVUgTqmgnDYVWoQ Uhh3M8217vWdjis2a7Oh+A1x+YwUcQHDM3tpcfaGEZTW9weigsld7DdKgVD8ZCTE/+5lqH9LDsUj BMwGka1Zt/sJtOdQiUr7F76ycY5eMQDG5l8PARZQkWWc09HTYAxU8wW458SivQImPRo2VbldDywM ufRcnLlsuX/kY+JmgRrEU/kRjMzHaT7R26kU28JcG0fA+J8s4sjnt0FEdfmP2rNoOILMFfcNXZ7q l+RxGrtdL/3hZs9Nv3HwxFaegQfVk8xT9CNx8KsCQQ016Y0Jv9NpK1PzN9J3T3kStXweHu/rv+tt jarHBQdY1Y3uSul+YY6VqxirHW93jCL2yDGafsgY51+KXJCkUYj2GHBxd3CaTYXTPZcW91lerQRw GcVtg0ZbpmlQ+6xUzjFikJYKVh0eeLSHP/T3RWiLeMK9ZSsbfal7AY1/UFi31ni6Hytf2Hr5ucdP iwMRlGZML9AE4VmrrbIkkkyF/fbyoqvpgJl8XJ6lOuq9ZQBqJvtK33/QBM6t+2JzAhXBp7hXPoK5 sieR/G4HkEzp3MmiBOYQyWd+mOO+Di4/Vtx1lEZzqdfD60utPNZ5ngmB+cdLt0CkELn16zcta3ds 791UuIlknQkI8Ia+7lgHE73xbP30ft+jcFTBwehNeYb5+JeEoet6+yrqxGQIcMxmrqXW3sMEVVxk xZu/oDlQzf9+wgQnJcf8RB9SzLxiPrmGEe/EdTNiYlW9Yn/v3I/fH7ABHltSrW5OBl+aI1jOFasu XXQdYfD1bck1sAnPsmN/UzbSDjtGjS0vdtQe5xSzq3FO5KuThtIrz7cfE6TzswwnDsK1+R+/yId7 0Wts+jRrKsvq6LTD6KxkWMTOOdz4U4gYQ7LZo8HF5UvZADkG5l2UJFsG9qeTHm1pfD67+gU+VIJ9 y1OKbNCbcnfSfJQZ6aW0e7RnwqCH1K8S5RVhq07rlNFpOcEsC7IFtjnchZvZqfOw99w9zxsJIcOY IVSRd+0Y+nfz8cnuprsDjwslkvzKMbrLV4/srx5taAP31RdpUno/kJuIwEqqeuhTpAQcp7G0q6TZ olalWpR156lfZ//GMpTLeMkut8bCD+CnDn5nCHenhXTjARlF5RXROoYrpY3lNSTGxo7OemTk99OR lbBGL+AZDTreHRuImpYoZvDoUVJ4HGWlnxUWtzIo2k27+mwaokPX+crBCiDILEo9eAd52AvfNpkh tSRChINfcpGW3mP2oYKUX1FTpcwWEdkYbbaV8TMEFahb9k02LAFAjM3J4FG4VsyzdWrOF7ZnSz7e DnXZx2vBM0Xhe9/6HVa8mp5dcQ/qik9dgtJD67i+bKOUk+q/mzA8Bk1NfAD1I67/Y/GgcfSoS3no /m8glCaM9WsolIoC5ib+clAXq3ookPDzZDprkRsrK0JhnjuIKvB4zJhlze0AdTF3On+Uq8OCEWCg yeEtqMxEd0ffMntMhxzBckGVR+nnENnQPHkzNTNG3SZCWtgqg6Q7V/gLCkefgO3VLu575tgLvyGw 6Q/4HYdxqGONtWUcaUxI1EDACQzlLXnQoxnheAOPL0uxQ0HSdGloYceaRvGjtNQ3ZMid8BWgG6BV jwbWcakULmoSMDiEL9LpPg6qhygFgPTAK18HpAud1kwgck4ROBNXWA66kE5GiKU5ZZejXG/LBoVD eItZJKb6CPYmCnHntFV8FXYH8vpKLjdaum3iwp+Ix6hTrpENcKvnhzS8xxEWtjygo36Iy1NN9Uiw XWJsugZy/JdVwQJwz8rrVuBe9k7jQtrYXwJzVx9v0a3PjmtoVARStLVHn6SGyPZ0teA5+mdKuRaO Oz4KboOKwuWocr5A/IlCMdQAW4/PGEhXoGErpD/jNZrmo9p7fbZLTJ3IAw4JE0b0yuAkoDBLTDbr AlEkWmau2bilfHbKZi1bKBujLGOa2KPeD8n0vEzyLfTfISYGZYIsnarzzy8WXFpxFY0y0nwKjZgm oX2E6MJ/dmFlhBmK9sUF1D4NgodtO7Juwj1q1IIZ5TrRUlZYjm44XKW+vCKwHS5cv9gZ3WdunxI0 k49wkU9vRbNBSjrM27Z3Ecu73NLmLU4xR0FMODbOoPsLPH+vj+q0OpaO43I+oSwCmfsbVWDODf5W GxL4d8UdCRhc7k4DveBAlEUKasRQc64hAfvZAB5IqqwixF6C0bq4sSje6O06lwnODDuwwlOfWY2T 9Tr+pS3TTRjNoO6FiRxmPWXGGFeyuiatiTgG4pvvuxL1N8ADw4UrS59I9/bOUrkPoJrkwtvnGb8P N4VrAayvmUberZulYYMVfPbQ8ZH/7sLRg9jhuEVdzm0suAEBHIiCTKZxiHI92hxBTCDIm77HsueM zhMnxJWhlSMx0WYa4yr2Q8e8n2rdKQucXDQb4Lp2jcpB2fQADvaSEYUsMnQIaWZ++lCfPCTjjhBz vkkPLGymsN8+n8yzrZNdv3KR0bfHGKzoF/OtemS2PMtkdJhqIE/6Np8j5ylq7diRKi1BlDQa5N0h cPWDxSZX4Dl+g2Ly07xEP7FEALgV/JZcXYQvkmobX6obNjCL1CdLioVpJTipTp/F4aZMTmBS6WXP PCp8SpoGIh58t1KR8IFAHD28QbUsJnw3LtYyqK/zI9C7Lni0cMk0fntislxD58cH4ZcFVh38MNVs 0UOWMSO9mhRssMevgHWWNdQsYlYfquvvB3nKpD0iitjM39r4eyqhKL1ySENrK2wgUADRY16DW8Cj Lv0B0vstAEb7GoDRcTL7/LoO4BDFBFVyzkM8ELezsphsXGyfGNh52C2f5O4Mgi5pjuu7XvL1fpGW a1S15PzXX07ZAH0OIY4eXMAo+h5zIqudIAmTMtKF92co9mwxmM3i3QdASU+SqaotGSbZSmv3iv8J YvcPU0lpKNYJsCFisrYQAkJojWYScpjx9JWKUSV9N5VaIsn26adqQ3dsDd4+2AB+RID7kANp28op OUv4AWuEAlZzvnZa/IpfXY4nFgh4UCgSD9U3FHOfG5cmBlM1buksadr77F/dxF0hGxZiD2AwOeih u2t4sm//x5qrHa6MQhGzizvXqVyG/hFyqfb4SE2Kv+lhDFTaEjxyeLBKCIiDpN/H/rOFqjpMqVN3 kGG0sTDpOEyN7zf876oB2JpCunJVfOw9A8VrVgwTd5G5YU46fN5AzzyFUmt7GaDlNOwUUSnx2ige Oq73QzvfMPJFbUVKG9rJybNNwm+1m6ZKsAj7nCu9VHozL7Ew13VaEeAZUo8dRhk9rpJAQbui0zMm npjbLQhmtDTqdKhxThWdNN9HmIy5En1VxSu3u5D/drMiFAHwBjoAF/l8sTCuV1C6HQ9Aipo13VKv ZaIQ1QSMM9JddIg9fcZK/y7iRRQ9WpZ1Me2M3rLjbODbWvcY2uWT8Hjf5lbJKEKBTX2awIvdmWvz 4Tkv8m+1KYz/0vmF+0XtdTKL7Hg21H2CaXOGK+OcdF7KPCRpYtSaJJHb6PhbBFspJTozcVF6sRJ2 JBl308DD483iC04+74U+nCGn+bdXziBhVv3dQO/ilh2SxDF3xWYGZs1hPsWqYE8yYWWTr/8XQbQa b1L8S8mCF6SgOW6mzKIH4FkrowoJ9vH2UaPZRGSZXXDjGftDz/7dtSn38DjEUl4t7/O2hMFYhCDf QHKwFQd71CmWbC2Yi5wAOouixxQ61znLDPpQv2tLE75wSJexozm6Zf7056tW372tEn4fNb/gaSsu h2xQUtVuI5rqUWV3NoFsj4SCEETBAunrKWz5urlPxhcVT5qD8CrxarUKAXQbeWm0pfpMtFEPp4Ft D6Dhc3ILlxyxZg47j1ZskVljHnczCXgSKbmPKFgNKLDrUDy5fHLF8lQ2axBI3U5XN1fWEQX5k35y ROkaVI4tOMByl+Y1XRpDN2KhqeIQe3KTlpM9pPlrUBQI3mnOz8KBGSwQ9vVnjs+d8a4IWqSDjZpQ Iq7I7diVAv8nzoHAJXp0Dwd5ozS/FK4ahr/E9LJUv5Q+6L+xeUUBSsJEeCD7PxaEckLj2xC6Lmp/ 2j3WYy8XoQFxNTw9kMotsT8fv2VIsZzTzyAqmDZPwxu23QaG26zs7qwUzHYcGrJIlUzrFKkR9hL3 0d3sHx67RbTWlQzAGd5uF7ynFKgbJKecv8ZKv0S/x2OWz+2TFzZww65VljbPtTVeREu5J5NQDVTO mNEgZc8XumfR45HfJmVGjmCaavUJoq1tO77sPAu5JhHrxDHZFntysPt6mDpHacwld9yzOVt1MRoW c7oWbwx8mxkEILOq7elneIixc2msXVfJeVAKMje6a7vm7skroaQBB3z0/Zyglc0ecw09eUNAAL1u Yp2h/Asd4WOwJ6i7TrKpBuBEorEAi91ngGvaF0nV1GWua3F0PQe5pjPEgyS58mPpTY799LgNj7bk UJG6a2de58NphE0AKRHzxWwHjC4rco0YxrwLuzDz/Xc7iVPJzf+ftp/ZeHMTj90oZJdYrymcSdH5 0wCHCsm6YP4k1s5xS2TZKsrwMD0Ibu0tD5g8mGYWGi5QtbfDkTJ1h2WsUYbJ1wkzKUs2tRBrrBu7 SdECPIW1ZABnFBDcMvFQwrgw5/4v3L/9Uwtd4zus8lfBHopfR0aItO1K94rFtCDJKS94AkXXzPVr JBQ+yrukT704kl/tBO/bAPatgIjAIbs5+/+tXXDoE0hRj0xFX9NvnGeNY99AB/6T8ZImMORyw4qm YtoIMwFNP1itJevqvAvh3Xn9R5h25SUZm0H9JHdQQH3TYvTlLbwLQ7mGGM/I1AD3WuW9jJOXEJD+ xaeaWZkpA7e32DtLAtjB0KKGxI1S6nhp5DbLHi07KDqjgPpa0vdOCehK10gEng4uA2k7FESWhlh4 tUp8Dv2QZvN6yMt2DdgctM2cFUgOUMr8tYPWPxCfYdXf8VExmQnS1T9RyLRJwEpX1Nus+epe2yqR +Jqwvlj4m2cDZJqpXa3vGyCcbvD6mqe9dx0Sk+ZxTDqIs9CsR8GPqi+JwuCGusiebuOnm0nI38v0 Q3y/EIwSibNrwYrC6Cc2EIJ87RzU0NERM+ah7hOhdix/i/uKrMIkxMzJgYDx6kcCZKg3i68cWL3+ 2o6okmdQQ5DFwhgKf4siRnhe5I/utflnrYat2rfIZXTq7+nSQgIfghc53h4s9MjvBa0TqKdE0Vbi tMw7n8FPT1V/y1k6zlIVCk1pay8fRrLegxbwXAvqlYMD/5DRj5vCeTNtQGCV4+Wz17GOOBUJTzbb qUJD5WCwvk/bs4IFX15/pWNfVnE671laTqgZRsnQYI99LyHNwM2o9DgFAdmRdCqctRjtk88NnnGm 7bzrNuMm1lRqNkYronU6hMx4NryKQ69roK6Vv28mnXPYDGbG2SgmN9Coog0k0vaekQ7DBnp5XxDS AQE21DScPWwW8optGvEjspPArubOup/6lP0lHoB40HegSkk0Ylg0YJVfYeyyuQC87mafdOCOgQgg VBfnkaExYo0zU03/r26vA78aZMFHkawoRmlywDrGVXFxBo8ETZ87rxMDCRwnEP4dUAxlvxRTS2W/ i7yVBicF/HDrsFoEhZnzuCdUWjC60lBNgato5Rpafc7WJdr6NJtX3KhMgA7saAEu70AHOxxCnYgE TT+Ohrm1Td21/L2focjBgqdyoZBECITxoT61c//oKubx/XhdLR/JNA5CpJSd0Gyew6K8Z1P8aa0p 1S+fnsIKwxJlVaovxz7vQP2u7GBUs9EL0WOMRgjTNU6dx4j7j467AJmBupeWdjVW/LxzMb8iN/sw c+4femc4gJMSoPwmlNHhFbCOosT0tlLBAhyZj8BsHmMmhqYPivU9bIh7/CjFuJrApteh9bFtX+U+ w4bC+VLnd93Tduizpy7iEMWnS2mGeZy9TM8cCM7sQHmU9yQdd+FhkR01Xe/GDdBfZLhcH21ifEQK RqVvmxhun7qLvRf2KpBN6dCL53kueno07auIAwdOExCsSGrpG4RylqYQ3/WTnIiI4lftcI9BYNW3 csaZIiIp/1fbjwDgtOM6vpsRJr1NVCdrfgB+x5dsI1n2NZmUSHo9HnsqmrNI2nm5QmDw/dPwGXge 3UAiqEzQCENv1H+4YDt+tD4snio3boPncnfP2/w/bwoRScRK5KvKPf9F0OvfDyFJiAjmb/swKG4z zg7bHxUXuy1vcFsvzGSTqxOZOzdeLUFBWr0SKHDlfA4YWbt05Th+ZInB966aVHHLd4Zax5ahwsyT L4WbLqzVs1OZOpbsZ6iyg8TaCCxOND8DGDYM8M22voxASRI0C8PuZVDq2gPsTt51nXBdcS9XGP9C LbCQiQjQT6o9krYXz9MGtFOS/HePtrGDL/IReMSxlKICSDi6JFZM5+Srwlnu0BbBmfirGun6Plp0 6KkqMDYta0DBX/m4QbEbyfseBvaKILrOd1ClqBBpB+HOESsNsFE/giroc16HmatvAHoe56QoBy7D n7yH9tOGeJ7oQMrIMCQ0wZrgJegijQ/J4t5wHXGl1RMmjXJ0vEigNgZaKm+zp+Qd5+XmFEkl1u/4 34+kuMKlxitUkpKcGmtF9fdp4pwOwNx+80qPyP2q7cXcFgCRneTDsInFUry5rSkky+9z7qYlszk1 CdULeXLelS2WiSS/Bh4sEFINkTArHN+aTD0BIq9fr+NwTZ4FlH5sZ3X6o67+NxkgZPo87PrInjxj tZO1pYs/dFtyZ168sflcuzmWFH5hyPMCuHk1PZqfwluvDe/fgU8ohvhQKU+GK7rLAMLxbSNdNcBj IvrZI2MS8Q0tDNo985Vp1P4RPnVlce5yBEEt1SXBZfDXPmWxTZilFl94jMVxsRNUbJjcbpGasEmX Hr7ZchZdq3bsbyG3NyWhyrMDQavlKN5fyhUW7NqXk3pZHq6G2YFxUajD8KEHrcgS+YxvxeqW6vgu Vpp7qa9ZM9DBgAJWPc5EzSZd9/kbZ/JRxaQWAoG5TPjPqxM5Z2MVlfVprbxjN3BsKYhEszayTm51 qKp6CSIu0QCvhMN384+zzJ6ZcDzXmPXch9Pi+zaomfNXDafmUdUxlkXCGxkYaR5BdVMcahRdAp7i MS04DYG3bgwn1iz4dJAFIuIicfuKI6jIHuh+o+jwyH03u8VDGMiICNpoD1hNAkZGf/n+L8DyDCqd y5Qw+hL+T1Il/0gWqOhjogEXflVAfLc/O2J4oW3KuCO+oBjjV4rV7V16ezAFgkMZQRGGXcPQJVUJ ub73T5kc9DTARpSH2PTIGJIhhZvQQhfpWJSVMf3U/bVpnamkx02bCKQ+e5acMjshEwVMQgY0DGqH iRnCs28GA3IpeXrobbzuUYyThsj3QPNq9YimeDEZallk7fSM8gsv1PvRZ4kSYZ8DcOWHzBM/rzaE fsjPMgBtlWzrs8JbGK+2QFEq24WhDUKLUXBtfekeeXPXbJsGlplKOZt3ZLXxJzflotSG+fx9yZ+q 6mXH3X71G5fhg9C3uWJvkaaJUiBAsdXZPh66Zfnr07mdpAkMAKeNc1KvK4kMwbPQwYwzPg1xvNUf Cd5vvFZwI5d/y5ED25ayMJ3CuBdQ87cykgkk0a6FAJj38ATvJh9snrMGC8eE0njiamd/elLYV+BR wT6webujvfKui7raoT0cj4JrOtLvyLDkaAuSwr+SgBxVSfJZHvBHI/yGxLg0lA/euCEmsibTwip0 Ty8HtrTpUKlRqCcKkocCn9/OfC+gNwXJ8DlLis2g3WvWu+fQYCLMqFDqhiY76DiOxtbb31u0QgET 2mUKQT58ToGsxW9FQB9MpM5p2uZeILKkNqZR/XtQkPUREM9Zsx7j26Hj1CIsvCK4Shu7aWL65kHR 12naGWaBTe0ZC1svSyJKcqsXB46zPU8RBueHtwHYkvWAlkB+hqCbQ7kdIOCitR2UQOvSv07oDoUn t3iiNq3JD9YhJgrJfqLVvAr1Ib3zC4K2qq5nUyfVqwYVTe0aMngMwj4yuyX88SfsIpF3EGoiXVR1 PBsezaL9yjlrJhHt7zxr+EyLBZ6bm8DAqDoCkovShB5ZeaZ4kfygL/dCGbVmhM5aixVitFAKGv/L 0lDXSSU1H1Iv/DGNys4dHXppic4KEH8biMhbt7AGK45f+CYPBfxhJ0Whxj4nXh3zcshBXIXyt4NG bp8qAMXBFHipcSpOHFf2wq5SSj3aOZQ0Ful7UUpUjf83B/Gt1elLqtdB9+tpAcS6CCOjklKxSni/ D2yw1SYOOa9xSFfma5QHq5e7G0DZ7vnLl0PWr9cE/SYSDhkDH4sT3QJ0dqj7DeRZgSE0t/c5kvE5 h5O6/S9Sd7Pfd0JiF7dFEy9fI60RYmVwQthWz9LO1t04cY2slb5fb0acSJYdIuXQ7NBz9XinGn3+ JQJokaO2EPtpodJiZiciho20RpSjEb1NfiOt2ZNHS5oBuN6T0CPNvr/uweZ9tjsQaUf51AvatUld 1Y+HFH3d8+IQ2Qun6h9bpvNWCre1svNiToMWjMSAqVPNU1x+CxFK0BFNBIwwzq1KnYzzA51YB7rP uNeYW4xo1ESWooxi03mwD03yYyEIvYNm5mOnI/8uBe7yiPzG6sXWiNApJLhCKANeb+I2RNejunyb iYw7wqHpON/RrqX2dUV0uQLfIaVUykqjA2x0CMR7Ty0qGbwilV774kkzjIRTq4nl2wq61r5QrNzX A7LvZDAwuahfiGggR+ziKm2yiY/NDAcSZYbGABf0YbbIj5FiiDneADawO0yrXEPtLA6v2IvluFUx sybHEGwp/eGItjVVemsNLKq9yG9ylsCanaVZWPjRvzd7pn+zVTBCSftcurtvhlcTDI8yOEqNc2i2 xNO3fyRI7D7J38ak7e+JpEZSOWckL3r2+01hjH02F7oD98Qr5DsfvN2H/r09epeLHVSdALyQo8dz Yi2mxjoZE8ZdIayTmyI975zWu6lNuIQM/bYSeFGJ34Bk3Hfy8sblWXQGNgt5IPQbjFrz5Orod0Rn cGEhlnFEnjbSgymQn7apO63t58u7FjjVH9lC/mJ62wIMeSJgevxCPNXZ5jfzVNQIJAONjSV/I05Z lPGMaFcIqx+26sFK5Zdek+8XLb+pdJ/Wbqq/qtHtn+qogJ0+RHzIbQUjHUOQO/Bu1pGyRt58qSq8 s0Ej9fsPYERoJ2B7fPyDRichT6vdcYpI6yyU4N/Bll6QDgmxyvxeujluH6pth8chO6r51oX4Tw/S m61cLGy+KBkTNu+x/UBin3yEuPp9kHALExmJj4Dc6rX6dii1QPk8OOW2LEFeEowGnG3rnsKkH0Jc dYaTo4AkCczkA9o+o+IyT8Tj9HZuletnKVdllQXctTeXfV8POVBqa6iQEq41atFULztAMlHq50ST u7dj9CwfYeHoPAEJJiAu9zoYSJ9ppCUzEE3X+OAUdh2vvt8EKoIzAQr1poi6ETn7K6pODEatWmcz LVI2tQt3Q1ktZXUFQTcMR1CX2xQTfejsAHup02zOXUAYPaFHGUJW/fhE0GL/hhkCrVqecQ2UztaA LEo6oGii6kPtSL2cq342MhV5SRVU1pBgT7jZcfSwJ4EM829nxiMA+mX4BnGwr4cAEk1wwykzdaS1 6LekpYROl3r84tlV1I4sQw3Gw+9vZMpfuh6008nglbAJkOtMCJvhbAmklQGW9k/5MfwYyZhGmYen WYastCZoIM04F9oTFxCt+y4JosjpOLl3RTWyu/AygTa126CID74Y5pWzFKqviN2S8OsYM6r/Znqx RuOk6nLIIkNY1QqdoA5cxaQzRoo28FlHKwT0i48K1JOm+SEkEFF7bsmB/qD+J/il6zp7Gc0fmltP AUcAMW9MqR1hFaaaEVTee/7ec9ZsHkv+5H4edq8sy+nNr2LSfxeQn3vIRtv1A+scbLV2z0+tIh4e oLFYG2+a7lwCHK1eiE9XRB3aaNgbOTiVQhIH3o/DZlASBR6EK4y5daeWyi8EH46e8dN908LJJWwZ YgH7d97/KKkpe4mUvnq7AggN2p02ZBBiOatDuUMGyHN/jWe9GnPkHSNLqy3HlQnQ5RdK6XrBFe10 LdRdsyTMxnZ7e9MzCp+jeT395eDTBeyNMwnfRHmai2A1tZm29KTgrtY8y/U4y+t3cNsV4px5PHLd uJsl/r/ylCRupYYP+zKYpaysImZdUS+92Fg2aNO55SYc5Ov1VzEcW9juW6SLaOctkCkFKcfwm8f2 uS8qvDWWfrnC2a8S7p4Ce3w8XcN6J2LfQOlecfQ6NQ3eo9vHic7AZ4KfzNYvriMBro+zGXvsRPYA 73HAtyr7x7uvavWT+XK/GTrtIXFxeEZT0HBpAzpA0d7dJyfBJ7WHavkythFVHBZcP9buHpYF6f01 80PDyAFoWzYO7YvKqibUOu7qVSyd9uOejd4E+pVIDjZrUrup2vFPGfDBjEarBilEz8yfKAx7R2+i psmThh8vbRbGQmPsYqnHcZR1LhVW54QAAkSR5iVMZsPU4E2gkCMmZEeWU3gMbByOtP2Mv+0qxRMc MoJwxSVL/Jqxha4YY/QrVMCXEMhh/9OjoYF1E1s4YVUAaafJWV1P0LVAXjz6NucVzR0k3SW+BgED 7fc18AMl+rBGD6pROVERABkEmaXO/umiQ0l0amNSYFww8yqT2k287kPBDzR0B7JL5TPaeOee/pf3 xYqjb2YUNGcZSU9pCX9r1VYEKR1qdU1iZCNd9Ct+7BkpxiRGo4bPSmfNDpFw6T/JQc8h9EOO+Dps BqG4izeY1/rAV4DBYMMGDTYQg0n9Pe3WY/JZaJYitP1XfWnCZjzFrXl7QJxbuBKd864bXrhOhCPo yyTKQtiox9KioPZ+GVQ9kQ4ajZbY/p4RJeB9SqIBOMEx2KP6cf0UEqdSM6jUyT/BvJObXaqpFpcH Pi2GLokEaSX7XkXv/KPVo6mWcSBHdZ+YU+ykRgKI6szeRL8gm86TG8V281t3iq55R+yCHR7qNOyw Z1iYJa49nThTs5/p/nFoSiqbmljKEiv1/sVu8GcEuhNaHxxJsNRYuS45mfnzdU6IHUARfwee67+e 4+gjK2zakd+L1GbjRtO7ttmGruQwfwcA5kh2sODugqIzWX/O1Nfp7Slp7ClMGOja21+mda6hkOC/ 80k5WCd8RFsiZG7JOk0RlXoZJk7dtdr7EuRJZ0wc3sfs8BFGQtrZ0oN1Z45kzZsK7Cu8n9uePjt2 /SwlVA6swz9M1oBMMgylTgsCMTF8ZKplJ5vNQxQyDR1LBILAkV5ge8lSQ6jLLZr6s3+BFfnKbiyw +c+llZkWjgXqTCRL8DTs/F34UP8fqAB4lzk9B5eUfmYjcUbPpQ7gt0QAqRr0Hcz6vHx/BZfr/66d Shy3QEvlueBrdof5hxsSl9mwLROQLxPX2dE87UkIVjuGOILDO09BuW6ZiEIb4oW9JKHuO7JpG0NQ Q3QDb4PpndInv2LlE6gNgnJM3BDfdFK9Ql6n9lHiM1uMHxXc1SQoI0H9v5uTUKzqBMrBuJKEXOMo zc8WqD1bG5G4DQ2hY2JstEy5Qo5/hhzhPqFTXlPzJBEF7GJBu7goIr/1vhSBXCdQTNutH3sIhmnQ mZ4z7iFhqSX7N/nltIH4vEKS7ElI5KHXUX7oZVYkrIcaiYesgPHkOfDGX8JsydlhD+lj81Txr9wy CLhBn44QGNOoqJFG3GtccQU1sqkEvZWzTzl1D+mCQNeAp8ILbfOzzUl27LFPVAdJRsf2AqYQNGf7 hJGwNRVTs0dsPaNW8dudy5x1dI5/0GLN0jNHpJfTYKh/Y0AyMkAdCMt/WHrjH9tJA3ISwwASwyti nOEE0FldlhZL7MuqqtpjpPiVZmWhJfKmtnLCqanYdmmQlOT5siu3wAxPIZbz5nYwknxUBOCrHjEd YaNyISPag6f9Bdmz/lespuHIQHdIsPq/EVZyzC8issL3KUYDq30omU/ZH1H1zZUcHQM/TlqVlvoc rI/9xhfxpR5JA5QlqMjVLuexhS+raLhjsPWeQvtbvIKbb3nzUsEezb/CssCcIXI8ALxvvF37AoYc rasdWMmhMMKNc7lLagt3CONprfV2fmgREsXWCkXikfONR3ZW9sl2kmgPD4+Q8QQ0D6j2n5rn1Y7m 6McKli13Ys1otVvzD/ZyqjwKez+7q7FrcB9mQKnaop4As8Oz0A8NsXI0WtTjPOKUBJFCw6H7Lebz GxDJYPYEFzHi+v5x8RRq1scdyAlS8pgB/6VAtTHwcYXulmV26WgbHO0+pOMyQZ1O81+0oxtMMe5w +3dUuWhVdO5E6waGbaSTS+/Dte8ejid7DcSwB+dllohhmDlg8eoHWQenWlUPCQNohsLg7yLaCzaz 4+r2SMoL0NH4nq8EvebNiLcj8HcLZQ+ta0/CL2sokpxQfQzLWQR+EBt2rZRnb2YDupCtCRUy6EuP KMIpuABGH5+Oigp3auQC5ImLkMAlXhyluDqVrRXc7jBHDXZCS25Ro3poTw9J4bzUirylmBg5ge/V Esqv1mk7ux1Oraecvd92my/yvAnNtynMCIpkzf//fxOfngW5LPShLEoUNuE9Db4quPSFBhl4uGax wVwuXnRcRvi9nyhtsgR5sFxmx1h34rkeZYFOCg1asioqyIbJdYfTtA7RFd4qVImdE2HG6sMvGhB/ U9QYXws41d36dN5FLOZfNbLsDJDameop9Jc3jJ8OpzXYlI0VlR6NeAYf0SO7Omy4Xk7jNG692xKu 9eTzGnozfq9SjzQlUgYH6jFzGv5cp8IOw8jJXG5k8oXejyi01+rKJ/fr5TBdIpoiOCIeMDLwzOFQ oyxWlnoAub9yy1aJI4Hd8HvZvMO7axTq03e3SfWk55PyjluUS/p6vufxdpEXih6ubH93YGUMs+dc GqkS7w7FAGjBZlIL2uyeurLq089JKGaRhHbmGmUwLc2pjFilkQrrnLP5ojnnI2U2e79QT6a77L1x Uuy58k0CkiVtrfLSxgSogKXHRVWkrOmtHe4W8v20WgVo8IICWPuNAV+i/uPa9wzXAVwfGSzxxV9T Upn9a/eZFrh967h8pkjkqVahd6imRBs8lmee2u4Tpslslut8rjC+XKKYMrLScUuUPcYREn5iaUPN aN5X2/vIFwaYQx5qoEI1wBnnQH2qolg62/8xZfzouzx5N9cjFrh4UVUFaXtALNaOhc7rT1Sd6uhI 7j7Wi1zb/RZzIjYocS9da90ZKFx5A5mr3/7N0999c6Ac9DWIJy+ws9otUx46BAq+O1O6c6mExMkL iDLgyCEtZN/Enlxdft+MjwCl4RGhnMgE5lOy0gBVuxVQapTrX4w+6Z6VSmQYVpXMy8+wSlzBAoPH 3AwuU2robSzQ/Fvw5QbNTuugFOCbXCQNtEPaxFSQYMJdgvyLX/ioE9DAmuX/75ioUOYniUoPTJUy 9f675OIYicuWrx/axTLysS8E6gpispWwbf3kacRtf3pk1E7PV8MvQq3OBFv6tkP/FK9DRbJc9glI ufx6R39r1S5x2hwv+JzdhnP2UKS7li5qSSFfpg4S0Ao6ggrVYpVY+CNCmTqLZ74c/kqFUN4ck8f5 GLbcQBNyuoslAAByvoesstP0orgRiYnXjMM3PGWsDaBKGMlLePK92G5l/T5KOdwJFCEsME+txOn2 8oLM/TdUI+cBTQIR65DSHphHUYYYP+2G+s4uuThbzoZo01ZsYG/+wSemU8ooRrPBLoR7KZvx5s0Q O9hf9NsDqzNuygL3mT2JSLiuOqUMKSXJBKRn2gcW1bkU1ENg7uFbDFPW92oayjzXXhNrfNWwbI5G YNtFaXf9y5YdmuyzW4zlfpYHXcIV8NTHEojjlZ/L42/vF1XtMdj4heOQHq06LIHBssu14wwRwHuK Pt8u1MOD0F5OHmhVqDBm6r1llBn63J88zI6O3dJiVa25aH8l+vINc/CURksT6K84fA7qdlupTsPc YPkcEsbuovYC7qwCHUKiU0egGcJ9IZru7Ic9bA2XtM2j0wvB3Z5jkCgI0RYpsUhKNzi93Sc3wZAZ St9IbGoV0pXR9CBLRlcYzTHd9dKoKo4wLs0FPyjR5trdo+lcCuAZdF0fFaHhsGApCkEfy787Wo7J un3fjJ/vqCj/yNIyfzxjZILC6ihVGmbMzzkOQnWtNAopAxKTlKIMrBAsMvGOJMH4lD/Qk1Wi8XPB 9v7dfSfrJlgRt7unZg98YsYXEjj1P4GsmMDgdGqXVmts/jDWKtg8fYswfacFIC1+ZCH9fia1iJc1 I9q26LUCG1l8aw369E6+bft1drRVozkU8FcIT4O30yfnUoY72b+IbilJLBpl0xtJBxAxUcyQHLAb WsIP+vsUq1Z7aenFEvYOLMk8DsCcIpD8EU5rYmzO80OnA3BRR3t9p1b34my5aYZYhYzNTlSgkhgr 6ekc4ic8IStB5MvNqkHgDY1qe9c/HskkVdltl+s7Xz3kak1YUmbyl8ukLLlVrPeQnNehy1Fhs8LM f7Jxj+9v0IkU5b+OJSAMGqRZoTUFAX/MIUwxuOeFgYdWp1NeSwua8w8qgH2laU9LoHV7UGcD83ZF X4+CQZhyQAhp6VgSLcHIYkfhh940I3pfSzgj7Obar8YGu8GFMMQucUm5zw0plJFdSHcs0RN1WCod 8DZu6oKA6MkW5E4ks03rjUSNFHKpBCutHW4wYMcIhLPt3BHKn0zn8E8+L94c8z/snA/xWKQZQjJ3 VTY7H07NUWMc38zqEv2HSfHo/GaHSUzPYBMGiKIBWsjmniTvak1nMLji908DghqD8x0ccIo6TA8R b79EbmvwE7rqlGcHHG38KCpsprbboOXbThSBnGjoxw9NdEJ0r/jzmIAPCjC+iH1zfbZa3zCgdXNi AKGiWrDXoNz27RWdwBr8HsSH1S5ZLGZBTS9UE6ZcrucelKibp6U/vKqADNHKUIAlTgzmXdJrkW9J O+Y8OkIKScI0LujiGrty23qqp9LqTKjQdFf7bodr7BETsr3J31DYVrj/cIXLyVhmdKqsXS5kow6G qa/b/XRJy26FhaJ4eR+W5tfCV58Oz3zsrgKkvwhB3AwGYk7xujCY2ceQlmwAT86+dT2+az8LmqxJ BrVa3Chl/i7BTh/GXFKMeK6CUXSbEbhKtdcYRrbuLlnbKFSfnqt/DfiBSxN6t0mpCzs/RS0+mjd5 GYh73mwdIIbn2AKSprJI6EN1WZiDBVxmcZBEHYJ/JAAZvwZg5hYQbDbfBJ+MeuYWj18v903Y9/zR pueRSanxHlQwVQzXNLfOfLMb7m/nYU8Eyke4ishr5MUyVXptYRdTwssiUrQImUiSAQiB3mcQDdX8 cTpo+FCSlAhKmjGKI3Km9XIX7XJFpNL/gtLwLx24QX14EnVVrX4PlR74kEJK4g01Wa7ECXLB6Bov dxSJy6nCl/Cq7qejdGLTcVEi/ZTRickfVx8ng5IQ/f31axzfwL/qetaBiFosqfCBc8kdNPrNXRT7 Y3GVfW8X7ArUx6VnBynH/BRxrDMpBDZljVwR9eMJAjpbtuaWD5X3FxPUBKudTo3H74na/nOaeUYd c6sWpxtbqrg93hQmPEiUI4g/caTnp+ssElldf+BNThlf+KJaNEw82W+dxD+aLW1bDiSRffhGFzWw n1JfDJuLlXg6XQu71fCgYgPfLcJ/n4hcWRDsaZcBKT3ccGjMhSeBhAI7B38pbmUBzIv2eQxoNeQX 1ntuthW3AFLFYUWvjSdet4zByWtdpH/NltyWqddWd91j8Cr3BIS3UiM9p9h57/aGOshTBkcW8tAY aKrSI4U8L9PQnVRTT/B23LVw5NO/nJ3l4x9LKFp1IUz004R9wS3G/PqbLJ+p5JKbzbZl5DBK0RmY o2+38WJC135tRAZvCxWS1DyrhUz9Do89EqzOC7TctnKa9tQ+bkDR9OONJuiYH//vQ2lij2a7T1xq qo18gj3adOpXL+cliamI5TjAHcrw7XzPfZSZlXi6WRNT5a7XREx7RjoTKD7W/gVJDqZRPA/wE9/6 nDHuLxcEqyFc96plM7Nx3j2jLDePWLxao5lUo8Fx3LfX3uKglKkx4lNfsamdChCQjfNY+zf5rt/Y WgToUc0ZClCz6HNXkT7QrZtdj1AMhAG6bXxQp8hWfFcazvPdJB6IXUzpjKdt/ByvsS43R+nmb46L Tci3sT3MOfkCBmbV+Tm3KeRnnfWWxaZ5WYd0W/vRivsIFTDwgsLIS5V+aFSwh2EZD6KzXtxW3EZK 3kYtCOF0k2m0fjNzPO+s0kEHm6ZslA//bwx2N4JvZvtAh0akrRqK2Sq/r/BGilqXr3pCJeECB/kQ TxnHX6V3tapPqMyaiS/FioQrZ9+tsgVvJLNSfQKBvQGnPrp7oS7c5L0cmeUYWQBeTlPvSzISkcBE SlTpuRDAwJR3JgAjHExFzYNuMsT6L4Ys7IuZgTCF50kK3LIkLTwfGybY7y+WU9pwhO/hg/vEA8hk xHas7Leu4fO7Rddohgt8UDF2qi2CXsCLCp/QiobKNVrWa/5DN1dGVYL3EEvEkfrZA4Ipv22duzHC zWH7w02m6lcnHRUtIC4CH4fhD8JH6CEjHIN42YxtPrvMkv5aurpT5U016vCOlt+k8PIIN52cNaCL D8o16JoBK8XmZzPXanOqEJEoGx4N22ybUf3PZy6bT+JfdR8yaNMD+5KLCb0diPqevgXfWpVvhylv Vomvvc0k8Y12btjZH83uxecsvloX0aGrHICEh/HfD6yHbbBaXoWmakz6I962HgtLAMlr3oIKOQeB Ust03vRfIPgH86uPewWKUD2s/+fQ0ZNbuuKtUzQEGQMe+ukmWy1H5PLcl3A2MBWyjDpQwJjIuo3j QaXscS0zAYtqn3gU9Jm+CALitKK5FZ3VOAy7xMKFeAjPLEgJrD/Yv4vSkJF1iz6nCXvSBYsi0R/F za+LAldj6mrEQU47br6hMcO06pruhhzsYXw/TmxUBkjZWIZ2qyoeZtgDVaiY+g4ultW70LwGx2i5 R0Ow6FFeno/aJlYyQ3Gh2l0ELwrxs2X748pPxM6xwsqHfaeOlewrA3Y52RcmGVohLHObTOlesZWv 7kHwjYLvKDYHwF7NEdIwRraxbKEQBqffGj3eeAYWzkoCJ1PWTlJ3OnGMDGZR92RrXDd8Rk5VJ5GF /qNfc3IslGZlfoVP7NXO5Z8p1EgcFhBuBG+0NSWuxsV4oORck75MRnvNWhH/S9C2n5cRh3TIulQi JtZDbd/1n56RkASwINKLUSOPt0xFUhgLImc0G0UCpHNhVr0khzjIY0TUcd9Mb2yblsMbIZrgzoo/ wt1RJzyDRvldNHUKYD8yklT62aV+w0prYfeyU0Xn6ZvHKbyxQGIZ4YoXNZzLS7bo5Um4PnJAth/+ 5GkdqznoED+PGuP26ffcjs69p8PzbcU7fEllAwRKfJfYi9o3GMBpGYhJ8SSTVmSjOtH/QdpPgIKA YgLAMggqEIZV376FLjSdytxuRyYRzHKKiFoBizKysiS946PzuLw1+G3t32J8643A10IbrNpR21yM //8HNbYMkU+tfggMHz2oGQALL1iywtKizjQxqsNMrSNjUeu3gtWGmPTY/sByGLt/+7TQu++/Sc6B Gk7B4/nOECeswC/YN8oaLLKIuasv4gBT2uBHXED/ocffW6n0bjBjBo5zy6eEiPIKMxpOA6S/m1zA UinI2zpE/EEluPPqf7qyzR9xFEcMRp+MN/C7T4GnV8+ii/MDz1BVutKzJS3PiNIrhzFJ3J4BczSe XGcT5ykecqnji7iDkMN0rqVuYlGP/vbMAddioe280b30i+/beXGazS/XGQtk6iVJx/3dmqV5d+Ns tjdbU5Sy3KpkBJ5laxyU+cY2zXu21ir86QKmNIzBOiF2IqSTQWmhGsI6j+TJ2gVCT+syjy23IN7a o79j6I/C2l2mRj/X1I91QdaYdhPvM+fdXN6zPprUm0Z8ISFKWl3pell20tKWqTabgGBge9nqeDga c16IzmclIWBY1SMKtzBB+l5XMprJ2KBX8lKd/aJzVZiLP01vUEvlpxNQyG6I9qAe/aYJ/DZyKKeV G89Hb8XVjdadGhPwmuD6bEXvp777NRJ3JHaX9o40/nLNY8pCFIhFg8CWgWQJRnpViqGUU8IE+dt9 0CzkV3zStnHMefbI1ZiMddUfjwRJI7tVruZ1uy+Vyt4rVb0XT+7iASr8eIdj4abqHTsDCc7bglNE rq44H2VKBXa1TQ0jFQlIH9dGloZSUDv2ABjWz3U+6m3mPg6wc3lR3RQC0TN/QjFvur/NXYwypg5y +2pmDAvBRDLvoeSro7SPK2kbq6mDtExgMSPCrp0II1Qr5Oqf0CormD74mQWHLWSaHQJd6PwAwk10 h5r5sTIN0FMerM9PB8/NN4bgh19hK+N/OZ6EdiBGIJW6XutpM9+Bv5md7o7zssnYssjH4Xavooke oA1+AZTnYNBALEbjx1JgZgfrJvFNM9noCMzdyGkfm9Oc5PSxwqx2ylwAluHKFn3zx/ERU7JaHpTG LRKAiT+jxPl28fzD//hYwgmIrpQDwcLTCGP2Vh4sX1bwaj4nCB7rar/pnVZv/TD7V7SxjwPfkyM9 E5tq6ZVbR+Oj8GiYjs0KiBn5gUw9jnNPA7b4lUiOc99xivj3NqWw/Iv3/rtIo11BWGlBRbMlbM5o /p402YatcVHwDVC/JBJnZcTzhkEeq20OdhG57T48rx7hhonCNsAlqG/zPSxtkrWqfUyJlPzlFHkS oqJirPd72Ho3AenN6hYxpIp401YKqFrfTQefMWtZEVa+eAtR2HM11gJKa2V7jihV9jE3BZzgIThR cP5jyGR+NLRBBJZnDSQ9vh9M81Q9xrDjea8y4Fb0vcovcE04oAlLCEu1mZYBzfENJEjtLT9Oyk3V Af5xAmst4tsvNAfHSoEGIRmuaCgL7UPqozNhng+B14A8L0XwYd0a2wn3fwjMFzfiw6b4Z2UAhklh IPBOtBoKnU9zheIbvYHXfyyqS9IWRPJ7tcYaM2yJCTdOCCARlSBZSDAMLOqOYrMOzJfrI6QfQM0d gXK1HUn5LSptq1o80KBgG6VLOqaNyIFWTZ6MCR00XYG4P4iIltDofzWF5i3nntJOUfsyYtsOQAmp cRbuwILRqTPLxtxXDnSyBwyMwv+YVGjMiEff2PcSg5zhAAAsCVmCNMSAdMHITNs/vtWYKVBBotDv WO8vwM7741RHqu5Yux9k1CURPIuJoPxv1wY+i7gVBIifGN+8LQNN0rZxBaiRuWhxTu5Xsi7yveWZ N/ngxFasIdiJgpQ22hINZqWD6PPpi7H8IhfGmEPclpfbBr+iex7a2+ATTeZi0anAgg3rHxATbQJF 1iq+oCPnIS4ZQXAOW6xPEc4ECxU9m2jQZ4fkRi18EV7JkchQ04YHmPL59mSEZF+rXT6eE/vkpSG/ hleIjtSzjM25hLVi7Meil9W7X8E+atN07c2DTc6079p/LP3tzTxkZZRiieQmXsk6KtnqEIS3VFCs buC+XExg+rjZjlOu9Cg2LmLy8p6LH8BkFBUnqx06alsuz8LZfsA21bhUOCIVqRgAW8hQB21DAHCO 0yg9kPwZlNcigwZfmYp0LVVfpjfqNLDNjYrjz16skHskC3gtmiG3rePY+zQ763q1SZF/ZC6uYHLR cYCirkNjXBXPv/5wO4p0vnFuIn55CsMYWMv9SGHNQ7IRu0GQnOEYII2xd9skBrNCmWExC5kC9K6w ymhWo5/0okmqqep8zi/+R2HivgjiuaLRhTsEzUE0q4nrthYivROXgC1Jd915DmkUQrC4+lsmbUU+ qEWUK0tVOBQVnpSTmL7KCPXqmOJZ9aw/AXBLVnLBYJkjNmuUMpadMW4FmvG9A6rBuIPlI0M9G6BI xE/eUqUG/kNM7p3eN7U6WocSY05pHdPk1cBX8PWzSX7F0Qzyr42hyQjqUtxtIsz8UWF6vdB50mJl Oksaqf+mbdHLUNCBpTDYa6aM1kVq+wyvNKO5TmeBd8kNJYrAToEI0S6Cp1VI4nkZFIxV17wqGcFo Zs+/dUk340QgpjFBGngmJls9pM0m8y4jgoTTcpyrFZTOjro5QnqrhUptLaK3VgRcSKxrMayGLWbz iDd8rTiJ0OCZBgwG+nw7cHEFNj/jo/oVTuJIyvmNgTQU2WMx8U4X//iWCv+GoP0mVAV/IDV0NCw9 gb54Iy5wWmdJFROEHMWGBClPbEdBnNZp9b5ll2Oys/66bakHk7lufs2I2JZymABP0tMq+YOhjfR/ O0lzZUBN2g6lIGgwvmZISxQchkvErzUUm1Al0+ir7pnxwmoZx7pKXYW7sx/uuNFZ2a+QaPR7clf+ XK8wY/0nfoO9iinNEw5LbJu/IjDMt7oMJ7gYM3QC0LVPqGzzQWO9rvCuTJmULaLwz05J9iGHYxeX 9V+asnmcoyXhtJnJBKg8A2d3opfr4fbF5m+yGMi6XCDhBIaUM2AAfeMgWIM+pAYUNFrTwtXeQJ7S dqhOdbxBVth/AloTWLMA5103UjIkichaVG8T/lAsrXYpn/vk1GDbTq2x8Q1KKiUtDedVEchqU2MX tI3qF/XzhPVT1VO9qR9DDHMTg+GQL1lswdGB5ay2X6o8UCQCq4ZG+CVy7DowkbdVoy/yOG3Kf1iY /U/ORyaxt4kWQB01XiEICJX8eUSba+8pHVoUOvS1BzuBHXARJImZ1CVnNAheNrESwOCh9XpT5QHw pqgjAkVsLYsDaPsED3gCp2OkQaG999nKXdcj1k+FqJJMMZhxtiDgXegC7iV13YFC82hV/ZqPYG+A Mrw9E76/3+GduzXMlQTDUfrlArzwl0O9xdseQFk5tVNQ2PY+EkjARp9stGC8p8+HIFJlG/8nNkLS lRAg8eRewnJX4kxU16x77nsHpbYAaSS3YuzaTVxl2XVTRX/ocxCiUf5v0b5aPkrcJfSSherhopGw /fQiCNai1L6iGCtQ5SG7Vbx4vny1dfQdGZSLoqXayPElelBmrRa5qJY7+OlSyqtxYNwBex2d1PXB 8fh6XU/IzE0w5/yahcLDPcrSDWrQnwcgaPA0DjRIgJI7rTehR/7QWNdDRDb01rnzgIO1mwoVVElQ rPMTs28Vs9lplIYeM+9E7WuRmi00x8Uc223HeobfdksrNPt8W+QZ8jy+D2oX1M3SUOpOg3tn2JEo 3Tp+jtcWY4PMN5V9mpLdM7YDQC/cRaIgVHuVgpXWUiGck03jRl5PpchmJXPtkrdRNUCWK2jmQ3LK BpxCJVx3mCCIddo/w/o1YPV/Nt15rpUu9R4HubLBsRN/SRUXsOQcvlNSgb6cjIJRwVXXQxta0ZHM sOw2q+xFddYEgYssX915/fV2ZHdh9or3shhKQMMgf8V699GPja335bA3CHaObRd47TrC4xG4zuVt mGhBTmtA9M+lsAXsAQGPnGNR/N8I2QjHVhouc0WT4T2koIbOtzDC7ARPEbkLZBIuPa9mBonKO8zq 5V30rTpIQtv0kAMrq4fGilx0BPS0KdZKxKGePlFsJK7N9L94q/4h1yaiJMhtkxsZWGXCoRPPi8d5 9U8zxCVZiOyMBAorPizAv/UFZU8+eHsRwBNL6jR9tLA2nUxfuephRJnIjtroei81CHongNXOk7CS 2VQiwHJ1S2RlgoDYETkXfe2B9soTem6ZmcIz9KBzcGr3KHU6eLCPPmx47kkBdhe7VJQ701Ppiii/ PB8prwPMaoAgpaZ7f3siIiCkdyHU7+oPpqP2BmZjakLwvSmoQP461sMW+wmLofCSVxOny4dcOZla MW41ksSueAi6cWQs31+OzFc77oBshVPaqbygJCYTevsN/1WAifYKxf1S7c6fOzuO/zYVvt1DXObq 8Th0E+7fI27Y0wJEbdkf7Y0K0oY2ikhuK2AaC2lLhLSr9tiz+uDhH8lKM4b7ZKGrAh3JVDJ/eAL4 WB18J84sLUK7UxTVipoyXiwhyhEMbkp92zMMc7vZecY2V4Qmsmy2WMZ6rNmCfGzeizha56F6GQUP 1GecG8gK0J4SjJGc5RMWdAhicWeNJGwAAcNbHoqhUrahjunFawL4MCb2B5WKjnvzXXEFAAdanZ71 C1Mg/w/nMMoJ5H90aSg0S3c3TDvVOhdg2cCq1/78oThxdl6wGIzu5fqInXH7sTvMiQhL3rdZnbmM 2s3VxZWpVh1LZ/y2rIFC2diCbykdTf3c5z7OigVne39qnMeVxQJIYQqEYJpn2Hg/BIIVJfEIPSPg zfSvVxwhsYS5DLZzgZCd4piMGUEhhTWLp2oqMbVGuX97Y0S4OarWmlyIzPpxUG3wsE3GcRXk5DAB OJf9Lvp3kOGvBZ5Tu/8/psBImFgocxgPaItGXUlmkJ1wiJdVBLzmm9MexkA4QeteUUdDxSsh752e eMUJXPtjI37bE+3MZ/qZm5jqlxJl9QWLWM4jicQj96MCZu6QygJXB2HHWiucIrUGfPqXVdsY8ZiN oA+n8yuTwZ78fMRTZ3cUjQhKHlNHa784SH6NnIBr87/YUk7Prllq7uCd8oQOXrAOrPHH18+9kjp7 dcSmGUTtPiuGWQhmkF20/qa4BmI2Gv1JO1d1+l+6pxaBvianz17ZR2owjK4jXSVM/D3cdJucTAFF 6f+XCPF8RniROPZbsrVkEs3BtYRP6bv0IOf4gzMae2zs4fKpQh1C2du4zQNb54JoW4SEsa56P/IL rYMoy46EkOhqQthhjQZpYVylSTDrU4mI1EFLz8KEsYqPoRqmXxqYjqYLkbVn67uJ/BqIbgG17i+j 9DxPABVyy0yPKklnH5K91jlmFIw0gyOXQHDMLHbAOf2Z6ggOzeRqSzJXxOsUlLRlOnRGW4FaESSL 8tZSTYx2eOaSMkjyKmOXCsou3D3dBUhul4SmO7YB5Dpp9tcBnFsQMcL3RhbnTUHnvudtoO1iKEW+ AvcD7h/TOidFRhget1RwQH60uOvAFxrBOf0Uk9+liOl2UltKqevxPsW9Tz6JmmtUMqxOajDNEoED MLgOzS5W8XIrBZXh4CtD2Kkm9LRAWiVHUSwbdTlWM2j/zaobE/nhUCh5a5nflHNKbAcxJV1RnsRw dRbYA2ICGiLisDnwgr8gA75JPodHO3s0fouKgpeaQolaW3fkz5yXzPaLUW+nuThJW9SxC+1Tnfz9 lWwGLN6U5AfpYtkLzQhhEehGmWtbaaTl/0B1WXGGTY9ALe3LJarZUsurRBnffetiagJaMR1t5m67 cbm9Adh+JfXEaLy2Kp8OeERW0tRy3whNbgH3SmlgYOJKKqQ+8zYoSxHdGLAvnmxhNlgPtXrBh4b8 TnvbZWVlEdiBNHahoIDXk1qztrdXb0t8TipMOCNQR7FOjyHq8ekgUyCFFoSi42dKFKp7CkN6c/cw cAoJu55Te/0j83c4vc1dimdQ7vIqWMDnmg8gg/+br2OY7+7z7eBZNtPqZ+j4kmGYewN0MaMacpiH ow3tbhzNvllnCwgdLAWr2VPHtBePrlXJlHSZqlsw4BVAZ2mZloTle+8rdwutrFDQUIOzZ0SI7xTD sgvg+BjIw9HqfPDvvxbD17kAMY3trv7f12w5NBzApzaWac9aGbm5aYVKeIsUSedEq5PA9sDqaNxF +qv6CGVOhNX3zHvDZsYCsvn9zoa1eZs7hykstckXJynwo7xoMpiUq31xCjNA+7YM6OJBebjSEr4H 1HG1yLPHi1vTNqpFNRqlywx7l69yZ5PLqgpSGNvmU9BVOVlORXcqpJYExuGY8znzPxBJtThd1G53 hucDbDRgxvEuaMEQ/GrtV+LXXeN6fdHY685kFYfoyrR3hXxr5pE3m7RRY3FigXOavC22Zxj81GSf tlCjZ02pBoxnXOhsjkuq5kCARLKDknkI7MRjv7Iwy9gbZrT4lp4X5hk0IBFGRihE+GDGJNLdH+XU F3Yr/hVdAC2vUDpteMEQk1z7ETVYQ77fjV8oZe7TNseqD/MESvGPCL6gyjis1byGhYVp8kCNJPxV 33Xv2p3ydCDBC70Cr0bIlT1lzvscGjfoEQZJ0PTA1ucgj05wyW7891Ve7ppnS5nPTPlQlusVY7Uq 6S0kr54hudmD007GSMki4xZH0zvshGFU3zqVZiKrNC9HYNkG4ZE+7QUcGfvDaVq4gbkjltFZwu5n 9d2uQRBlBPn6y9k8OXPcM2JCK/7ejT/61ZzAhc9806IE9U4y7AAE8hRHYmEbBCC/GWZWhZlFplsW OxZOl0fdJIN/zTtHx17l3QRi6K12zqfTyjfUZ8FHbdrhaPSg/PkTaqrszHkqTD237nBTo6xCIZV7 LeISJdwlOBPfhOZJ/QLZ5d5Zw6uPIQv0mjch4miQNIath0JuWHs6m50UQYys0Vxjx6Dsvcka9jL8 WvfQuGozlF4R8vkVn1jz6I8ph2Qin7srsUXOUCRNUlD0TbGNL4pdUv5n58Fs/459ktr6cpbREyE3 otdZ/LKfkbUlpuxN6d3pGnf1Ol6iIq292TrDkX/tUeZHd7GLN5afKcDBciYfryWD9FNXRtZQ+NjG s4qNMt1LoM/VvGI/yR4/gnanbqkAt2jkKxp6AJCe0g2LOTSJd7QT75kpPMJjaAdlYnYALKsqRktf Ae6xdBMJLJUME0s/psBTcNsrV0p6ozYHllS3gkw4LKGQiNolUrdzGwicoP91k099seevVcfpyIIC R2c8kkD8XpOKwCiwFdwVwBdvtv6sm7APYQBhZ6xzM7s1+IRZOgper2ho4KrJENf/trjOURCcjSBD HqsPYikGsndTd3GCxiblcjCabnVVatsxsSqEwk38bCe7i3lmGzZK+pdjNVsdn+Bc/RqZtNBCNxkI qjqd6gB1Mz0UHrVdoBA1hqBKOogtLmjSmG5s3ctgQAPPL1AhNKb0CIPgOLSllqTTOZ7LQv1u6DSW +nhSCPO6clgAdwrlpf3h1KAP7nG0OTKifb9yXDJ1YnGl0CCTC/kd+UQ4hA2LWTSwFAuKa5+EZjHV 21ERBv8Up1tq5ScElF3NQfqbMjV+LeSIkloTcrNvTpumZYp6q/fsu1KFmuwV3LXqf6UpQjpuCMur yKSpkYmSyBbCLS/0ouVhFSRdSsLyySsBEUx8y809l3OAIi7jocY/iuyKQme5rZsLhGT0903AfyKh mGwmK8R2324S7yEBDC4GrAHXMwquQP05LkyuQq3QtSI6VhiJd2WRb7EpIdvDoz6rYn5/A9jEQpP8 9fhWW57tFEd/nvnbdOxIoCLZMZyzPupI6BsTy8HQDLgC9azs3QhHRudhS+4IKAToLuhsdB2a297W f6uDa5EI6Ke7NUFcq5tMQ0Jl84KiiNQj2fI9tycvdxl/9mcgw+khoeCoML1+xdm32DKfQQeGLLF/ P32KWHvXvXPk2wA6ICvv3Yy/Oj6pNO+71VppiGr+hnzRoqY4XMhbb+vQdqosUkjRLPYQljqDEuis UJnM0H9IPCnO3nr7i45Ux7aZhyk3idGorUC2kwMmWTrUKvEFTT3amx8DzkKk/JzG/Lhwjb8cDjsa WrLsOLzrUyiRLd2Dny14ujsZUvS/OOnezbiYaJKd3Z7/WCr/hOThUl5D14lczvzWjlurP7HYNXOw gM5TzJ1ilwpXkSrSFMiWaXNXZ1v0xwJzGNlO9wM7lxakTH2pbSELHC4ICngsmUx8h44wv92dZhfs 9BjZf+G3InvvaCXkSa9mLxHEApOaSf68PlD5QEpxzMC2wcOF+hyOpgNtBGuZZ2r3C2GErbPBfuIZ 1YjfwNEnKM3yLq6At4MiORc8mZsq7hga+5Rqm8hck1RTJ/ilIRhwhR+EuEhlLNHqffo8GP82vnDJ GfgjI7eDlofere3tHoOHWnmoATcXhFGt3D+M6uB4iQ3R0Nne2Rf3+w2Cu8Em5SE7YkTd+ArlqDBv vu8iN6dRJpfAjsjASzhekRImps8G398k58MhSIcnTN+igxQ9VXxYLgep/6rn+xejimjUwLW+YUSg Ewfal+u4FSFmd8XD492lXbf3wN2c2TruTK32Xv1WiJAnWEf3PlZbx1Uf6wwd1YYjtnxexlWZjmWQ y0vWG4CRmGYrW3+wPzDCiyNOlCcKkXGQmoHaZUFMsMvky09NxKhU185JceJ2ABiIlK17fmZM6gfa jsUyOESNjMaqkUEfCkgHEe+Lti+2mJZhAebxR9CHDIRp0sQ1H3l5IXzBXkcYqPg6Gj6YSCn4r+bM a+/fvr1DgPX9kHf50RU0A5/TbApp2RkXFQU26L/uUhXTnfvxK3prokwDOegCDXtXc+UTBwcT8LeM ijRc6qeEOpdgnqxGG7HZM0Muih50XM6RZ4b7tRh7trRjozD0xsI+k9WgFddkEeRNIFtAYglP15DZ uxL0lmjDI9LqQm9TfqlGnbHxubkAHq6lzUkx9QuKZ+PLiaB1u4ek0PDg9Kv0nQUjmoa2k5T+oHnn 6o7rrZvCAXIPaEqA6AkuQL7aOw2mtxS+kAayD4DsSBbU4A3y3dvPDvUOQuwAdWqZTj+x4zl4L1Tg zyMavE1mV1p+eQ6/1OOKTKbHlypJ9nfrJrhHqlyyG+z/P6ZqkGkctRNJrgJcy9skhI2QZsH3P9RY D7Bvarz9ph59DDoJB8/7k2fXKVHpeTt8OXKCFPkFc+A9jsdVMJzcYzJkvmA59leLb/pkt1OkLmn7 0M+gkwHn4PmpSL8+gLxuQepk4SUe4v4gFJWQXST0aRRrdZm0COAyRwHVBpCAXqQZ7wk31mdaBli3 MERkf/vdjh4NQ7/3cN7u1m4yZn/vaEwIIpap8JSI9PmN4KKDT586qlAR2R5tLFiUaMRZGNMhrAo7 7ktOXFH/crlx4NPSrKI7w+3Q3W/t9DGawrpGdHaXgrE/IsGH76TgDPtmYOCSVireF63oCZfOfAYo XlssUDCaYXXmc7eQPYCBcAtZcPrie13vQe9ohDvmTyqVZwcHNmDqZcIbBxtQyEj9TKxKM6CGGgBt eSVsUtLDQxsZqddjqcjGARq8wdS2fhLoYpFkp2/Fv5X4AWVL+lkjn1W9qqRz0hiMCCYYJe6It+6W eRT4Rr/zfpfvyNqQa/3F1gjEPIgOcZOvMeW4dXhd6/IkNeFrVRlURCjJ32WhiAhtCVrC61ZJGBF6 aYmNqZ6hMc0x818mQV4BJLkPRFQOL8gzIUPpiD7QQaCnb1dPft1/h9OH9DGD+tQ2iNUIjzccZ87w KL1tamTUbuLAhHyLbjsS6ilV0xw8YpQVQf3b3v/HIhREhOw/6hYUa8AACRM4FyQ09JyftDVJ+rHW 48pATvl6GY3Xq2JhlR/pu+eSnIc1cqcLU6fMUgy37wUREwiNsANIHyCl/9c8juw+6khD15+m3FoQ JdErY8Av+RZ1jqGujdMGqOw5gyKdGlx+iXxbx9lpHHOMh9agqBAUzolMGARqIWmODmTcqcgztV1Q 5f4oGjN6a2a+C4WOZgDDiATe13JpmmTXHWLW9UsvICT0Ub6H03GoqBsx4DPMuHdg5yjPJCfRpwyY J2IEppeEvllZAg35RNF/ztNVylbl+bC114WDCtxPskr1/oCnYVZIvqzZ0lpk/3Il3eB47GAs3RJI 4uUGV5Ayo2DghY+1+Cay3HePGq1BXlmMv9Saz3z653eJdFo0/aehNEzlJl1QSqiiM3zoQKyMAB88 99iguh4/MRQvIXzcATb3lDmda8kpZ2L3/hXB/uKTfwGj7UKNAa+Tw8NZBwYFo5ceLXccl/3u5YOo qPdbx7Y2EXHCFQJRSBd+UgZ0xnzCYyd80dA6Z5cpf5fJpIJUAKHwxpN8I5/RvEdcOi8kSHV9RZwR wX5EvSSow8odOxB84kK7cXMOYwxc9tq/TJ2iQrWAQgx5uxc4pN5uhqf4aY3fyh4KMaFE/nnugROk AimWkr6ipZFDgZ1/pq6A8PFLOUnib2zoSkLTUu363IcEBXMV0MQhBNEGF90Ue89gc2kBc2rNj9P3 lDEvKqg+G4inph5M7T3H5xApfe4tVmmE/3D970XR+xfKtq3F09sA8wtuUajSHBSF6rM1c+Nl/zKE l9g82S9dEH+cyYXvY0jmzMogsXXZuwKzx2EM4Zc6RSWjiIQ3hiNXxAtwf/pv+SWcCwKui4dEGk9h ZxKtZ8HBL/PK2kzNLF6PLQNqev3Q5ZBPhdGapwsVmsIXBioAAEUROpYHrFogt7AlfpzZBFzXWccu eTAZVp1iO7XyMkaoTgBPjZlyGdGwnz6uA9PhHBirfAf/L6VMTaSBSAqQniR2JRg2KMHaJTqB4Imu J4DhqgssbVfhLmMaRthV9bgt+rdH4qG/ZxKJWkLsUbNP6Fo3gHlbOQ7hsFsARpCkQIzaouWKCJlN U/49lh0eC0BafCZMdcoXhj7ARAjmRRJHQCFfN23DeMN2QQkwA3fT3ZBLYVm/iO2IZus8UYPg8V6F /I3mvG61WtBvFGbuo4HKSV7ZPOlTd++FS7U6KWq8v/phLdLBAEpoUEoxCC2F8qJ3yzs/yfGt9d9t ZpEjCwPdrCbd/E2vNWCDUrOKB42zubTnXjGRf/ns+44lohpmSAOI94YD47ozmusrPT5b0QhzK1zO wFTBR65I7WKx+ddsMpgIrUH/KEVGwDNCFXz0cl3+mGyUjGUOx9F1WeqiDtT0MGVzk4BmRWf6WB14 w5HUqx7bURYQc1NUHzkrPOjLMXhQsAPiygdIJZVg2Us92U8g3hBpIR01kNkWc8CQgUaDnFjWlXqW Y5FjgQa0OfMAAT6T2jIFhBmsY2qDgvv7+U9QlmGkQhbaCWo6FDC3H/fcEA0Axjck6CYx1E+jrO0O KPe8Q8JhpDn7LFftpuB+Up531whbpWFmsk+vGEmg0wUFMY6z1GvH1YOLFVtqWDjzkYZTD6ciH+Kh JzI3tzZL66JiamXz9flaHevHrJtq4WCgwYNkOj57vrR6dH8AJh+p37CaJU2KWmA/0D6oCnhkKczO 87asLuVU6TIp0xJRZqmHlRPqJ7lCvkHI1mJuhaoYSZDq3185ZAJzPzjcA/3v/c6mXklK4eysjtF9 7zIqFcdn9x8byBYjMGoOf7bZ6Ia0QwnQpdmLwLcXbCy0XrDzyRyAQ9+gAuxUYntJyvlKLcxD/rqa +7PKkwQNjNlmQHrPEBy2ZLzklyYl0DA5C3c2izttTJazt6KrB4g9N3oxwC4q9GobgaCwdTUFLTM5 o83Oio4CHf9tl5CQj+SVyIL5Vh3TnVAMdjBnQ+1mJmbjFYpCm6esvwQQkXpH1JabmraC5D+aCYcP s2EYxCImnB/WVLQ64fDvF1VBrpICBz6cAxHmwjDngZs0/h+AfRmQeuW1o/JKYS7dVCW0estSr3GY m8IpGUNC8KnVIxZe07fK/TlEHJv8c1U2jGa0B4PsR3sf2lhpd9z4QB9r/GIvIARUU0syYFxtyX6q tQ7JcMwbvMEjIm8ySIw4LfIHsU7ey9+bCh+gKnvlfVUHGgvUh/E5oJ3k07qos/5u3AAoSXsg9s2e gRBy/j5/S5WpQW9FKcVMfUYj20ewcFndeFkDE0stcZvkJR1MgZJaFOz6u/HOk4tNEI5WlXCm8VyQ ZS8CnfIC2J4TK5RZtspYSTiNItvIOpyPPhTIgtW+4JXjEBRWXxsrPgOEXeEmhVdhZnhIqetZ44ut US1des+4lntkmp2Q7vLVI6mBL02D9V2k9XiA9/w5lJyanaNypf21Abu5JkV3BYeDyHNdLMI0HEx3 s4SEMvHgtHYBzfIeNqjO5Gl5rbv3SHofHd1vRTZlDA0mqHV/KDxSnzuVh+8xm534+CGtrLNz1luf HYShRplg3zVo5MHsitN25UDmHmDctZHTnq/8elq9FYfv0Cao0nejcFkVHW4qoVMAX2ZPV/3MlVyo ookBRMuKO5915qvLp2ycMgxzaGWok1eN+oduzRMXxEODLctFVrSTrwLXHZ2zP+g1QkGq2pGwE9Db 6WsvQFyzZUZgh1cVbThVRNyET96aGbgbGi7ybFsIY+7FqYDpHZbFbc5dE/o0y4fCtjxqgISqPtrw nuFD9Fbe//Q11w4d40LoxQsDelSlijzUGk+m6hh7DzK9+wZuM+yZUlUpWZnpzGMYqbWXjJX0wSRx AdYv6J/19s3bLgFXBaVMcV1DGA5hUmWulEuejRPgspXuGhOPOF/Y6pOQF10f1s+NLGhzJb6ENPv7 /aitP5Mo56wluQqW7FD4wcf3b4NzRkJ+DxEeLBrIPVEYuyTtK7lIMqd9Bna0sFdCvx3T66+H8bpT 3f83JkyqpU1DZ96cPx3PIZDMkNa2F6hC9c1S+mG07OURm2Vn+Wx1SxuTHLi4DnzVAhSfdis4CiBA zZi8WBfCGpYZt/MlRicKvn2r13EdctQi7OSXI4yypOrKYFUWlu4wFOYLEn9osjNkaZRYJxjOs1Jl tk8N2OA9VrQ9pXAFgfYBLVfTUNOF/hjDFE2LyzJAsdxDBSQGJIR0pdpPgGaTdmp/hnADdXjrlUgq 4Eeevp8hNZ8QHhzhg2j+pKK4WXxddIapqQalepwx7RjcfQNWlNT56wlQDgsnOgWDMGJVV1DsyOEM JiKLEArzI+oCvoKiDzVDDAgnVkLwuF+oEJNd1rhjdr2GzkoYb9S+pqqRI44nbV1l3OPa0jsEQYrv arl94evNmok8J7H5ZxOyi+PB9UAsqdmggD5mHEjCDh8MtSJYFx5iuuXLGixvXUk+a9ExI4UgmBdL CnMCVeTY62Wm5WNcLEEDwtT+BW3VCdVaOAKTBoZuu1/fD+U0zFRg6/7Nd8VQ2lZU7xITkQKmoMA6 xyeoQiJ8JNO/s4tyxu8dWKEBYdtRhwWp2kdnZlTIIARjnWkP/Cc0iptNY/cjhTg+aX06gDEooObA YdZ+1Nfoq3uOWvRFkaPQ6qbtNq/824zqkVwB+gQYvttm+X+TuWyaVtGCy3m3P+zUGplvQi8RiM7m Vs+MNZejeGO97/ft9WaiVgSJCOiw0gYXSerm76Q1uoxBM5LGYvCbO3bVbkhm5rRQB9HjMRkoulGO 1dGf0YvwUdZAl3ZbRz4LZ3eIqqRVe6R7nobRFQt7pUzXmwhUzLfjcMMHnqHURcd4upDAktscftW3 EFjzWltIfQMtr0JhDQcCs3rQcBA6H57mwnCgbW82jwC62gRm6IIA9FIFx80ggFPmirJ+fyE4uppp St7vNvdqcxqP5fFynFG1Cjk63roI1nJpeArJkPytpK02HtpPsJRIaPZIUwe5KO9RnIC6Kf3wG+U3 Tr7nq0i31ibv7jpvKiXy52MA+ZO15GCFxT3lcmpOtySGwRRQ/vDyqm8gXUhEZgdkvCTrtgl4QIjw jmfKNIMXYMhLpNrFSHmVEZPs10Zy+kdqvtgxyhx/eP6r00yMfsgVXDoaOdcC2aaIo0Ee/pLfsp9R qUSjRmPnsKM0ggFZ86FIkX0rCd0SfzA/JWqBSVem1VVW1hC62E3XIZB8kC5Ry1IWDgHh9j/gFmHd vzBQb85bRyoq5TVWv2rt1pz45rt0OK2+z2OIg2eZilKDfSu8//ons8RjFU1fztcEZ3A8P3SSAmnf WdxqYrbD1HoiIBYX3+izwCrMfRG1ipsPcjyIHTlkGboKibyHuaOSQVddak4Idsl3yjW4LHWJpm9y 0KPNJq5XrNVf9JY+Xzbb8nQtWMCgXaXE/eqfowzDWVE/Tqg7x/qRaPekPcV5jzz45y6kJE6De++w FIWitUB4hO9CWeOy61rFHymjRmeeFRWwNu0H9puAO+vnqi+wBkw9pInizn4X+kxvnTQlgp/mSbkR 6ZItVdxaFHjDeYWoTJDrlzq5zEfUEgZEw7T0BUgFs1d+US85XyWVk3XYDwbUDM6kRmFl9tCKGWhN cLTQKLQ6Bs2rxTxoRgyulzqLE5He2RDVLa+FmuVdrAxyCZRt3YZpjkmd/SHMSjjjj85yGIZjGv75 yyC8/0xwiKrcPvndunz65bdxJ4a+fE3TIeFcUDvJEGL6MKEL2RnyWuSr0INMvDULnLNb02+Mp3tg nC8ffkZslXoXE7Ab3JWlYSS+jCdV2K+ph4/M0iHH/wmpj2W0RzVuuJNXtRKe++IhSzs++21xa54W cLoLp9BM/WFlFPWwyEKNDMw7UMj1/jTyz38bGfbs5r1CXfvqjI6HZF91ahDINOFYWxNzDx+odoQ2 Jq9RmgCRlttr5F1pQozgNboRjpu3UX/navvgsdrsk59BfiRhiDwe1ahuA4xR4HVhT1hmfSILyYED eqBy7XwdtSbZuV3wyBMK/xXNQ9kHh+MMcfqiwUn19g69AesFJD1rM2jdrrREXdWse2/tWqIlcnm2 zYFpsNS5N7tBG0e5to31Ae8Tma9qZmkM+cVYpsDrb5WVPWHUZ0R4NABOSX5XuGBF0GO4Sndu3ffz jXYueMg+yijCthJKlofLaktPR9jhTsbC72F7B2YyqowDr6f5vSeyVR4b9RRkcUs4fMJzAPUbwTO5 viepHivvRh8cYVAWmJcRGVsLSMfvI716oRx2YD0J8Hm9HPZspOyKszYB7+3UDVAKD4OMvgHVQAj+ MRylyglqntxHvhsLVfyV7OIa8YLAcavbA8BZnWiCRn7rlxccE4hFWWtRQC9EV0wE5//bZfEnzQM9 hBeRy52kT0FklEUY1tYolBE4/TnR7hh078vm1Y3IdW5+HsBy4x3osfZAD4C4RWwyYc8V82qjKBBu OlVuRu6g0s35FNQFNiXjcMqlxqZVHgKJp7otGi9tEWn9la+1U/NiVcMzGSC1Oe2BbUS6BWUAa25k o+ubxgobx4WY7zAi53wyRGY6+yH5h0ClSrHcjrDjCbD24Nczt0oh/wun8zRqiMhrz9L5JmvtSKAr Bz/BwUslFqudPJ2LWP3qoBujv0TiLKTloQRZV97bT+bQxNmr4/DLs7gLx82WIkdzZlVakwjf6f35 vgzrR92hVrXcif602FYiC6cqldvBC5bTGo4d+pKcGZxJ/SRG1YVNele8zMVLj+H1Pjy9oJpVZ80i 0qnEPmzGF7i9vAvrcjrRK5Nvxpt9Vc2Mc2Mu6wPFHyWhZLch6RRbkWolpUXh9754QZMuKrGpYBfe e1huOzD62QokRI+lyqOV9zKZuQqblwlxB0/U1zaE42eUSfrDn+meRX0cHgHHw6zHo+y6/0Peyd5Q wTPgrwic6IgnyC3h42X0s0z6V2qSnvd3pWkdcEhBOQIBgpF9XcD7cXDfmm+F4UqcXVcd9Jw0dzMy iKBCjID0RU3YtiAmIM+dzN13vSjSUI5sNWKqtKOEHrnd3B7EPIFCbTyI7eWmIzR+d0OqJq3YmMJL tIP+ieRtAVQpyQCVgkcr4t/MypX1rtGVx9p7cICjTGWk5Ie+G1ihaeS7pr7kNAMdR+Hd0aMxpczT nt6vl3zJI+TcjDukl+E68O6O065rjfayr47VJYQ891AzWr15XaiJDgvIAmAwNiBwIzcYzgwVc8Nc ZhAtTo7ATuEkrsWAp1pSEe0IhcKz7ABwyLqRBzsfxRKumdnKgYeoVEIWwg2S0lWS9mDnCemisG4O EtdCmAt7ztK7nvK/sFvXbkeSi/RnSMCVdAaF+60ppISV1S91xIa7PGE3E8PmATqUt/5jXCvNoxcO 3yRkm58+jS5RMKYXuiyAdHqWVupEEVGybj3IPL8qriBIqbkxF002eFWQz8LHeSqIzwbhKvY0o7Ak TA/W12AfmFEHiAOnG/8AxJLed1oYMKoMIOVxIw2svp5pesQROLNFXG3oAiKF+iW8LHkUMVqagDcb 4TM2vsbvgT2fxnIAQS1c+q7hRW0wYoTDz4rTyqanxAxJw84jrSFwRZB2+sgIyF0arWDNix1Gnoho 91DTYbxu8BpywMATCpEGt+AEZ5CAEtxtHj2oHG8l0NbFlfHwAg6s2q3lmcQNs1UrihrWMaNxPedL 3A8qd7Fpxiyh18JZ3QI82kFZ0/V4W6GeGfsdmkZyWTkV5EW7+FPU/oAn4gDSj9jRFYJUMJaUAfWa jh/6upAGb4OM8jAfmH8eCfQndvZ5CjRchQG16DGd5XOnQR2M6pvkDXQSMFyW6iHzJ24LAYkvFOzR TgpXIcNWouVGIgJMMtaBwnT4KcSCl4NCdRuPiwjSygpBWIb1FmTlkLVZV2GCWaR3GLJ2JXZaKYoZ ow1gCLDLhWubAA3132e/Kg4eKVqf1uboDMhdsnOA1VlpfSPfbf4IHh7WP4OuX2xmkjqHNYvx08x1 eFYrlVfbFRnRPAFq7riqfKx3lD6BsARVlpUcxPYcksyZ+LyXTNtDQgYtwPdP9433L4YeyKFrNnwK JuzCy08HstbRTl1qYTr6VezT+iiFFaxPtDb2BzBMOifkdpmJVttbEad+DiSk65SB3TYK8z2+GeEI ZokKNHjbwMXA+/r0kITCdk4ZM6eDnQ+M0L1sKVIMXdq03DgCrthyXgMCnnq0Tr3D6tJmSfKCnIwR gH2OPhbyuK/AgAKoJ4uaymUchGU7Rk0Fc6lHGVbpcMHsra/guKmf/yWPIksl3H798WeTsQJjHuOX mwzWlLz1zuO5k3an3yE0dOyiXOZWZObdpnINWcPzaE5sX2iX8VpEcb4JLyMBwm07EMGHiXMmBsza WRw9HkPY6aG4hL6F98rmrKoDEZOfSrcnfPGTdUBFJHkJy9kNmcJuvCKHJ5+O+usoPvSwqAPyvM5v wJmduvhd4sA7WGLGIqAlkUmfvHDBzIMs45sOZovY7EoVci1DAX/qdqfzc8kJh7MZQVBSB5zSbekD vFI8d3DLWHW4vd0FWmVnkETSDFd2UKk7Xk2aeJA0FiQKPSpAY/6kQEjE38xkvL9ikVRKWYxh+N/B x/pRA38k2eFIkHW3+TRpnNVWBuHjEKqkT8x7jHYuVbSCrz3HeA/9uyL6riEX8iQfn8QbW49b/dn+ 6BM3GyVddt0Fypt9GltvHCxHblQ429d9/FiBhF+cRXF461UXeLfuBX5icgG25SFvC7jHMaq0xWxr PBF1RNEcHggS719dWQkrw7HZgMXsgSpQDBp0VMSPJON6eBtaIq9f7j4FKSxAP/N3uZ3XATDStrvK gL/pcD7iUDi50wWiILgZ1rIyNvSlManHh/mpCmMPAFaoUgBpCiZ7lNKy5jmA8I14R+ylr8CsiG1H a7qHfdDeNm58qPUHODe09U2FPVxmPNpBZQoKGpac5UuL7fjWYAnEt5c8dc6cXK2vOHTEyCQCs/Py 4G3oMghEvgb+fg+n4QMwrJ1el6NS/Lf4s+vyswaQQes8HZzYmNbRYyHtM3m2npwSoa+8zJWdB246 6jHx1Yq6rTm9bTtfyp/6iU8VI844rCCD5j89/iOIQen73QM5uawSiwZwF7974Ae/rJXjxiXQCeqw XCSxnb+8SGmmnNM5IY5aVVY4Zn8/8s7XpakJfaWZ5JIU/sqoV03mQbKryGn9ZNNCVGeyOKT2UO0j x6RDQAXvPRWUYhO7wFzzQekdRXJJAnvlvEeQTDUCYjatqx00hHreNVs4zPdGuChxxqa8s14M/gQz rrBmbr5AQLdAXyKXj98y5aHYS1wVTos+EQD2vARq0TwMAYh2mAG/ht0llAJv824KQFTHceTbaEVY MBvjEp+yM1cQ6HVBDa1H63VLAkRHHl27i7mn+uUqN3TGwed0K6YK0kRw+wJJfQ3FgIwU69QuE8Wg eK+7NwfwZ0oqtRbTqqaw8Eret2eYJWIDvI54iHIhkSTcXanqlLJopB/9Nztl7oXq5MvEiWBpDdA6 wIAXjrie9dWoQC0pFAaUb0UMb21G2YTuxnNH446DHIoYHC2X7KiJm8J3bRsuDjNrBEiEb1c3JL6G 3rwyUseK8Sb1GSMmc+88U+BZiBY/fP5bOMbfZFAnriUyi/nL7CQNN8iC7bMskXheGPrDVrLfxgRD 3BSub1UwUBe8QlXqYCNeaG6TS0T35EpWEHctluRF+hhS1P0UVmTMhBqbOWwO5a3k8bzW842LiTxF TBoKDJHIvkkAi2ULhjhqLiYJ1Pe9TAMkvGTpK4CEwCs4kL/hLvVMuAh5t1z5WkmxbSPvSOtZEMr8 k/qrysIfrRHLdCPt5Rt4rknS9+FteQec6JeOdhOgbbRWXgOZp9x+k3GZFudG568UIHtwRhf+aYxB NjWQyDI/T2+Z3X6TPvwCbgwdqFdbnd9bq4tMIWwYzpjYbdbJ7jEbsIGr23roLvHG0L5hLzDzFTp1 NN1ClV6PTFbq1hkhYqw7/KQia+R0P0ByAQRrAEMlTYsx0I4CGPRHIEJZW1frVbs5YkPScjgWSQJx mKDUDSU71CeIBa6m1e2VmjYOdoddGus9yxvt3Y/OE1VuLvtabin917BWp/4/cF47mCU0oBcr4RHC Siin6D1hYmyWoEi+iyFmJBX4XtcJgjovyq6eWOff1+3qvlV9HTSTee7zHE58TvoKx5YUfKrtzdMN sydWrgNaZrknV0T+ibj9LGK/HU8Wh2CfeDlR4dbw/bU9oy4FITUSA32ePUBUV0GZ+dSMQKr0rzy/ OryEkmVbzgV5qJhZFa/pkCWVs1qpLj/5fLjNk74kGMW8OClPgmaSgNie1DrSItLN2+pb6oeCiWir ebaa82XsgsiVaCtxyw+nXoTBScoaVwdJuvvMn3XP3AMrZWioToeBcqgA1gvgUsvac6UXy9P9yXz8 AJKbvDhn6eYI391vK16H06N5NBMC/lj00sjpfLEcP9tr12O4WswrLcWgAeuX22INwo+dUQL44fYR v2MPBgWzW7xOsGAtb6Emi58iprbJoVLPNIue3d0kdS4tHOjlTJ6Lk5VN2yTWhvEQI6hgR9vseVml Irb1elKzps5rJKrz7c47eLCTdns73AdrwqssRzkhwP4knr1ewPdp1RhLB1o6KpJEPyTQgvdPrhAD swRWZigqzz+QvmOFy1CfYEEif9B1f5UR4aui5b5uKMy4e1qREJrVlmtQKRCCgw3zQ3984eY1PtJL y7Bj6zB08zD/R0OeXBToGO2seHoH51Wwr8sWHhfM+g03VpPGqD4oLd5PBIuW2VNFEiNWaBPWXp9k G6Oa7MPJtsWbJ7jH8kplrrxPukkfy/Wl6OIvbhmtOpfLisU+m0Y7pxZg85VYHnVs2+7D2PFO1D7O 7OvmPKthJKfuAmaWhH/26PFykjVIGE3CRCyJ8QauM+Rtqg24y5vBHvKGOvKMdXtktyn8/UdWsPFn 4DrMVVhbLChaIjAToLJXKnquLBtIN4ISOUEPbwgcnqcLHymwO2aDDTkJeFkf+0YJGGYeEB6dwH2s Y+F61QJKKQx3hfNmXvC07JEX/Sph9mg7IC0lO/KFZEzmIdmyXjDJhTd7uCDHYEABuLbn/79hCCoX cQFQ4rCg/osqf4qPvUs4JSbqBULqkljadjl9/EpL/VWeH9k6O3STHu4FQWDvPx/w2mU09Q5NWZ28 nSuDIbB1gUJjbppDDXWa17sTZFBZIz4L71KNVw/Lseqx+BbaiC8rPpR+c+3wtByCRpxdBPTkYB2v WcueLySmytKPialzQ15qB+9nKxFhiAs+IQP0BkcE5yGm27X5WyGa76Ia5ZuYpRtTtJVApvOpQcmd RoiYjtlEnmZmlJpjhKdjZmBxhTQwI8k9diul7NqgUehE0IHzIMHEH1BfOdzmsxpMNczKpqLrX3w7 29m1TWUi17ligXVv8RcFM80h9nd3aNvJ1E/I/a81wnFRFcajg+DAOvOe3IFZN5I7bFZzNWk6YgdH 4AU325sM1bIj6Agnf0dhsg0DZmTeG+KcwD5iWsrZaUhUQB4C7V2MJFm8i7C5O02/U4dTCh/Obb+Q 4s/d2nummpNx3sMaBEhHNACjjgBzND9VLy9EKtfBSZxfgI1m+X6ZaDGzJIR8OMvnCK3AerNNPbOd d1X6LvsF5gmxD7l1A7lmcaMDYgOS8d19xzEptiVGycMBZI/InJTQ9RTkss5iJ2NrZLHSFdYeeAAd FDaIE4X11Ryaw8GNYAdKcaobQFEeYITtVaLJq0fDiUmf0h4eTnvKljPnWWpamVUG4msUHPthEAwO loiZ31/VTgubl/nKAmWC9ajY+yqaP5oHObvx0u3qiYYzriU1YsDPVJJs7VBVK52NpxblSJiSXr9U qLOW0tKgv5QvhiX9nhP7KIsBQKSL4xXcqSnuq/kx701jIVD1DUsc73AFf6W3V3hYHy8a0XK25i2w DY6lBPeUWbfNK6l+DJRkkHUv5piORnKcpv4itXvAGgvRWOumdzK3mVL9/dex0VO1vfEuogNt+vOO FwPNKOjuVmDJn6P9gqc7frtHPGcJl0TMi7QAZOfYm3VjshJMOAG8RrYfYS2eqq6GV3I15c/uqH0Y GlIK730+A88rreNWvOUTNlDn/0TVRkUn5Ip96Fx3oFcJiU2/eCK+m4LkNfb4aum6Wv7FdXSOCBO8 WfhgWwRXAqhAPV0IiRTgi2MwM+wYDohlr2odc63KWZU5id2VOGXcLapGMS0suw4tfVwlRdXpiGEN usTavrs3cNbIj/Xq9buua2OaWH4gdMGUiLK00k7wKO2qfQMPz2QNJLYHgfxwMcsFv2bwWc57fygG vxjeuRCfOmF+TER2hkgUCEH8C9m+ix+Tbg20m8E3B35PnioBc6hA1FZItOvcPTRaISQRKSfm71co BdzfjFVJxc6FomvtNLmVaiIgKiWNt+Eh4SIQtzGZf8h0KGqizzqJlzlfUtJ7DirBSyZ5NX0286Oe OmQaq/KCWk8Lr1UPlAhkT0p9KoFgG96rsGc5UAhn76H4SgNcnYoX2o7QWnnZn1us3F0HCQD1dOve 2WRqFGmya4KTqcfipcXrc2BBvtieYwKgZMOKaBXYhpZByVcQobhJa0Iv3OKbD2TBSyQ+o2EF645+ ubnVNuYxP3uD9FdX57xUGI4ShxW2PvttySyYtdCwOdQsGjUpcnq3nnGh6VuP3b2chOt5XaW8pNZU quxacPM6K4uj3PgEvUG6X+RIKrx6wEsJFQTmEgHDU/tZ+9/0kjnKAZx1O9T/6YinLGrb1Apo80Om vpUHvCgW39k/ThkH9UKrcBCG99OjF1GDqHKnsOyl4OHz6dEN6b/5dJa043hftXMJSe/1zufZNDyB qeohaTCoYBiCEHS7W86SxK1TfFlM719AKqLuStQqwEApgY6F6r0zJvntNX/KJ0WiD3OupIgFmUZX xPAF6Lnb66+GOPxxAToHXAX4kzEi/BceM/7WBKDGYgVgMLUTeGqrieZm34dwPyx8fJGQ+oE+8wkH 2Y1pgkOuZNl469voPtDjFGH4QPVuDCdKeicfsw2VcoRNgHAjvbViWiJqcL173JU8zjZ+drOywwrL VOAEqUIpHFM7KeETfVJA8QD0zqCCEj0P+XVByTdS0QQFKUyvePG1/MutFStJu6oh0Wo0rOIw8HQP nJogZA95xTqqAFE6J3OP05F8VVC6B47JH5o2g2fdKanRVF+IZXU6oytjdCPZEOS9wDQB2YjiBd6S RAwW42Ac7H8WmCTgywAEiQHGQMnZqjNFoYMLY9XYqj7HHuz2Vc80LgZADlyzBM0z5lrKUI/oL1bq 7llYHzUaEU5uj0g7luL4Zj//WA+T3/DiuSygIb28XHD1bL1UtiXctRqLGbaRqVO3d4yKFaZEAZhH GUEM+/jk2Cw8OcPZHttMhwskWptLaMQIFmXwdWsCUGE4w6UVSCFpP4bblWzK2eRO05eH4oxCtimQ l5clynU9LIfc65OKYJj2Y4fNS4PNwPpmQ5eNuR9NyuLTm5I67PobMvsjbOvOLCzZiXrEUTMinYKH QUjA7LJuq2stU77msP+TmDRcu8Wosm591Ysmr1DKqJQ9Hn/e3vptvtBvA5c3ES/eBYHoVKTFRX4a s71MakPQvEUjW4szoKFFMEvZ/csB7x5Ty5OhYFI07PkTLTU9GB4L/HCy0JACXUyj8p8ibwCUNEQq 9DBYoZFp/DD/UViITcfRoGn+xsXCGzn3vCHoSRJ7rTCRrRW/x8cC73BnOlwNmEf0P5EwwcbZ2k2w Ugkk/XdAzJyd1r13OeF8gCdV6ZO0x1KipgSja2Zbtt+7geaFEydRgJOcvrxdP2IhQMpbvlviGjl+ REvOV0MzoPEdrv44eBApAVVUWmMamAOyKd/HRChf1bMayFtgfcgzuss3kktFDbqR41VbK4C9TFFv xroeN9wWNWxl5vSgm4Yn0tXhCzE/zltHPqpECivHdHhU956RQfeaZG/tDOcQI4lPPAFlQhWZxnRu jHBvJLTt+Ygko/cFhu9cLpyuF48ie2k7ZtgTyaP0Nz0oi0wEAvUe1A1xeXazvDgarGPu2duPt5ud 79DswDcz8oE0EbIDNnaRa94KBNGCTrGV5PVc9Iq+Ub1A+RC2jEld2RzsWnQAhD0jkW4jfsICierh Eq851lO5EnMcTsQV4sDFqdYGooeMMsFZgqzSEoLSrd/2ZUvAmSkbZ200aTIVEg23ft7Zy43Yrcnc 1QxRFL5NdITBEJwxjW2+NFLGDkRvAHrNzKp2+QswBw4NTX5xp7guk+ZbFo164XMyo796+bRyaTyW LG00hLM7EJKRYk9h3WairfIQfIpEPo1Cx1hlDEyJBxiKY5lJOpHWWhODsY4UN4cXiUuqCqdbvnRf Aoq4RmU2KLKo+2+qokO6xij1rQ4xldUGPLY+C9O0KT0OYyHXkJmqV4vomq1ZUAZG025wiZ02irpQ WqiT3nagM6geoE2Cv44HgDk8fFYm6MSRP/4S3NY3V3rM1DJXG4/Vj/1Ixgv4jwXsSGO14YsKLm5u i7VZbmfN9/rwqO9QPuxgNlx4Rz7aiXo/h7UJ4IAKkYNQwYaBE3NFw6KRtr4nWd3es+GFZLGMq7Z1 dhNX7AAhSMlqg8swKNH3s5MOgh12muNqLUT5L792oy9mETTMCsNHavSZVVLcItx2yYqmlJfc7ABW WbdtQNKozVwhDThkQJYWPbajbEApLQvkOP2vjr5o7hFspfEtyaz8rk+VEsULDbiBUZ7wgqI2BjTE eesq2mgVa18CRvBick72UL5BhptnePndo2h0ManxRw6AUX4gAVx+505KNQ8R/D1LYQFNZr5hWdMU gEGTlieG4jjnyoBF3mWFjj66QdRzfwRn3zu/Ul7eVLQhX/xG+3Gr9mAardcE5G/kDPl9oOFNL7BN LdwKEk2sAfnNGJHqIA8yp96kz8XFc+UD5nKep4i3Z08oyqFo63QXC5wkEfTlgUJEERgiUeMVyH7P /yo/gFBPYg/HkowItJWPODGJUshbLwvkknt/nk6ziu5SaXTGetJrHOsxYtwyjd5biQoZdNuwAOKh Y6KXGRovKV+vZ1bZQh6Tq/8iWl3tUu+NkWmHbzT2q32aJOX98pgC3V5z9BxCmjREv1S25IE6E15U DdTtygLlM50yTeoJBrp/lrROVkh5O5sCb4eja+e/V5tXwcWiAwn5cHKdPaTn/dzPYS/df9i/ADXw LU12K4Bk5vC6hHDI35NI47Dte+DXxN8Wksw+aaPcaHOBJ5tKfKhv7xp7zmtzraUng52R879zUj/z DtyVgLI8EsTVYDAaALLTrIJBG5RVfC8ZXi7Sp/Xf32p5YlnZ3grnBomSwI3wSQ2gUtVM6Qhrl6yM aHghNoNjQFcz6G6o1I+RWCqjt6Xp1hDAj4Uvu1AHa/8tXDec2dZhpitpQsMYmArV4xWKkQ8INZuG XY9kqF5zl6nmqsZpeB8DLfoPLrqWZlpbcpmh+7kdobFjR1WRqreVOquPB5WOyMVzfa/zm1MXuj0e 9i8mXiltDHP3LEOjIvK72PUs2k4eAZS+TZDgFRxOaFXO9Vq+oxOT+qNr2Ke2uQQ9432NS9WF7Pn0 1LtmIqNVChoWMzPQtG8cFjGGDaJXgt1oxWeMqPKF89iWhO+Q1oaknZ5fVYRiZINZ2ksTbOBsfJmh ufNGxBYSiNmacduCnpzx6/2leubB/1Z5vONhG4GpllqEgx4PaZY3TPd5psQROfb0cyFxx8AUH1wr lN56I9j/qzYiHrvNoRMrkCtBKhB4pxGsdS4/Z4tPMg2+xFUIIxSXZodD+HxRGU5OWuxya8pNy/G0 geGsXxk7pnWVEnxnDxRt4WGrkI2bf1ccDDW0RQkAJW1Sp4U3yh6Ki1zUKqzlgQY2jobT4KJDvy48 32zcu6S/8NvLV5fXp+8UGWKE7gzpeWo6CyAH8hYXdy3PFtEwv2GOVQhYxwAiso+3kxwReiYpCgjI NLl0F2CFKmGvoaK2uGFod/HLm1Vv3cT7Pp57F39mRUOxzdKSwoF9COgFdpWzKi26dWQL4wf/hk9t eEaVrYWBbthO6AoRWqQIUmrBcNPxG8LDILkY6dQKu4p6kITDXV+Ug0QEzXY8totdh0WZnm4ocw1X YORDHMK8up0rStTgj5gaLAtzh2LZuYmhnwXhJau7TpbcHBQUMncxPgQoXiEtTLN6P2r8uET0kTHc fRII1XkfC1xzAgo5X8Z/CU41MGaXo567i1LzAxlE9v6OuhyN95+RPjHztUXPkDe5oFL3psLGiWfM 8zVpBDzak2B4uk7u2lGSBpbVXS+L4favlqCP+K+jDIbT+tXzMO4JKIFuH51aq8y9srwubZYAeOSa nASBrNQDyc5kXCcVwAwpkY3rOPIekIWwA0rPvIDhkCFb7CjbCTz9TO7iBwWRdYYatHWfY98EhPez RBiNL9u/lcJtW4s2RLwTAjywwF8k6JRL+qa8g8K8Din22twfVHitboGQRiSEff1oFzljg/rZUuT+ tpwbz8CHr3jnftAGy9Uabzi0YfBjsJo/fkf/k8N4DI0M4A6rhJodJTa1VrUcRp+fPaW+Sg1s32kl G9mG+KZ9EgXEz6H1vrB7Db4tLU0mCgM+8gV5XDSHKHFgAzUcAnbnPwWLEnfV0MCqZKTsaE+vWn/n WFTJvgGQ40BrwDK58s2QvHbyPj4txG/LrpU/ySnnTsobpQissGr7E3T5+8yyOgw6ylvRtL4ldpiw nBcRDtRzcSciY/aGbV2Tt0Hmf8OYKJRQhm8YH3N/mtLDSKkJPwsVHYhz10kSVl8kwKFpnKgaCw+2 Hffm5/xJV77XExP2zEkp0ChC3ILPNuLeD86XbrIf0YAMaL+SxflrOQTzGskZpA2B2Sm+QVnvA4Vq zQfYQdcKOJEsaqW0/wX1FX0uCSKzyPgHR40xXqu6twQCEUiSd99IymBCU+eB83H6Q3CBmswqFCvL A3JHAdD9qNpLzTVqIpG105gtz/Ch0dw6ixp1loq62oMC36oXOUcU2OOr12abdHq45+9B0DIf8BSH yjvQbbyLyrCKeUQKweD4lVjNtYj/DswuZkv+6J6/tcC+N+BWNWCQlxmZgp2J3uj0kPK2wwHQXHQs q/2dohbnK5Vdb4KUaCibiGFekBateJXGUbngqiPqTeqH+CWoq/+2MkzdvxqY2jf/nTB/059d/0hG JhoZwrlu/2at065LcrY6HPLemV9Gsfq+xlc1MujaxgFtdFV44GHkGvp+tHs2dBYiWIk9Le2NGIF/ Ut6UPsg3Ydz5TXtq7amEW8qcNTjVLy8CqFRzbGzdPU2JTDzFTbkdheQ37kil077CQIoI8Vk3pyRr 3V40NTDoFFwJif57m82WQS6rhpfrHvq1VJz343wMnnmJPKKbHxs+lWS0G+st0wTm+u/GC44GZfjz hdt7LF0zKLpnDgS6SdtRSRP6u7qid8QVnUM/7HNrKpwXATRQJKRMMRX2q8YY0cP5k7qe/aBMzWLL PVjgTCXuBRHOaRWK2Lpapdx1t1dWiQc3wLXYJ6YU1WUH0XqDgQXXldl5Si4wR84rfGe+s9HZhQ3c XEdfmDuz6rSgn/4xcQFoLHPB7xT5aOTVXboyHoiKqkr/VpD/ZrMXcFjB/Me/9eLtN+maVsy+XFTY pe6Wnqno9CmrdXpGFhK+5G7sBEoSBUA6b0DyTTiMDGWOhhV8rki9gByADFYyX1X4iz+XtXt3+Eb9 AGplTO3LFa58kbmUP5Owr6p8fXfKhBABxqouUgJ3Ub7J75tHC9XBflp1DkwbVg4omhFQwtEy7/+e uw3r6e3GvWqfHqfg5bYHtstMc8uAGVIairHYVvRw/Cf3KD20yB7b7LkJoI9JzquFKn14xAAqPjOq QzsVmMApetnpWcvCC2NqBnBvLgpa2RvG9RTo04eKP86sXmQPwqwa9rcmBFZLiUpPM8qo+gdvZZgt eWHNhr5U5mFmg8lD0iH2UwVM4KHHOGVkdmCX7a2u1rEUs74VFnKgbHieVH0zpbwb/ECbCw+uSupX YrLeiKJM0XGpxM5hv/tWj7rV5t/wWZfnAmPbtFry5vdPxWwK2Ij91kfBwWgw7wxDZaj0Iz+zN6oe bRs9qCQru2RLN2LEyb5+XdfmB6epwzW53EqqTe6b1RrvnUIDdE+c8NPpJq6suMLo5H6ogEV7oXkq p6uUO/jhSuqy5Rgz47xReu3U4+yDgSRhvF4tP6p3WjMpE9dysMMSEhiOYWlRbymxuCT1LnO5fr0Y 5KaWGAxZnBDUm861Asd7FvcGcnlZZNsmGkKMTZUBaWKjX3qSL+PhPhUAPodDBDlSCNinHBDGJSsq 0us73gW8MTcrQGaxkfTrFXr9YDmDWCaQ1MOENDvgbApla3gXGzeehpApE4i4SC/skMjFBJRj50p7 cDYvgeYfhXn0WgY1FeSQAWCSAiajyfPWngNKPiXdi/qEzeO4I/KhPWCvph3SyclCZXUZqGRzyArp WW3GomBwgU8oywj8UBZjENLolF1FKaPyBi6wVFuehQCn36QhpWVCBGMAj/9LoUY+rkOhB/tu739T Su05RqhzXtbUx11BhjFQ8BN7nO/0zoL6JwbNNe9uuIp4G5RJp3J9vFljr6YM9dyvKpEBJeNOp4jh cS39GpCnCfjt133jCMrqOqhBiBDuBuwYkjCSzPmjdiJPknV4fuqhSNBr5UwAYyEyk39QUjLnl/MC hnKRhZADx56PIFxhhnVDT2UjxrA02xYwDKf4sxcWXsa70BXhHlpu7JzgYvZmMxq1ckL1VmCAwSHe /f5xzuZdvrMWki/ZlTP9DURuGBHwZxMdhqGjCKI0q0VARqm7n7N47xfkkETW+97ZVZQYr9cYUlza QYhbbsHzQmPXUA5lGycM8l7SIuF1Q4zRggkT5of0ipwKjlqXDiJ839HRR6kUuptxiCuNaHHLU92s ijqgyH196qJJlU6Go3yhLk+tcr1HqUdUMqKazutWXodttv4GDOYFpjY9tqJw+TMv1v8puQ8pZNbq ssmSBt6FA9dTGB0aweI1I9gdp8qoCDQ8GmQTKANyVwtJkBHWeDD/3xYpgixtyd4Bq/3s9aMZZKlg TVlRYfKMnlDXX9U3EozjBrp/IxBZhDOnlXiRNDLzItgfbNbAxsu9ghbOSDiWfGSEN0aYfoZMzj5g yja6mxdWo4YnmdiFV9pPrDUDMnCTGbBFO2rNTnwG0K70BaIEsGDh/YkxQZlISPkVh0JLFYCFd0A9 UBheCE9xbgR4HYN4IFyjhvnh1JeNNyC3YM7MN4+OI19Cy6CeSetQxAAWL0cl17r6+lcWe4hPLrFz tizTSg0Vs8Y44HvZnTrCn8WM5JziEPjhz9JOBEi/bHoPpbB9mn3b0S9hs5+0BmhHk5Cos0U6FlrA GjrSnIVMVd7cFOeVgPZdjWxyK+c7vuLEoJWg3hm+MJY3+MFEdGEEnQggVxLh8GaeWb6E37uvqqoN 4KrrF+q3b2AX52fMzvqOoCfmofyUXpiRSoiE9+cNLfQfaXm+g2loC2LB0UfRbkq/dQVko5I6Rr/t gWIvXYtRQ1bERR9CMzG4Sw6ikOjeeNUESfucZJjEIj91amEH9CUSy1z/HuZpMtafvXuPtWhBkRMy 1+UD+nV5apZb+y3U21LZqLfi8Bh+B1EQM0yNyjlxAvVptItmsNcp01CoUuoVUNyrmciR4cjfAENq Qr8uUPCSDP++SQuL3Z0N6bbtnhRNvWQjDm11c+IvpTbdw73714WwNGSnQ5H1G+em3tg1OxZOR0eo RZW5aKarKFmD1hD/NhXnZop0Bpe2djyn3IW894J7MByIcWz+/+4WxFtoyT7SQD0JIEfV/k+tfSpE fQv8wnhsJB1tm2WljbszDALJm59mZq3vHu+/lqGTMv1VCl5AtEAeOuJa78drfI71tm+9azHGPefN mLicwj/GXD+x3hCN2DRXSn7o+/u+AvvKyJjttWm2gZvbkg2Gt/RsXjvXoWP64luP5HB7KmACP/li i5loJ20hUm9d/ppUkrS0DcJVw2PVVXZL/5XXssRinKPlmJMhDpqnK0WPVs8FvndLpnCIf4cv1rN4 zBi2rL2jZC3m4917GqsoIu/RPfe8b6hmUjTxjP4o4fyiXVxLo1NnaFpe9yhvb6dPRRctehK3uo/1 tKDsoQckAkFJQcxqLmAUm+aOfsXQc6sFrFLF0E7c+THtMNP9owjTB6TmpsJJYk7ytuaNLYl50P4p bRmFDmtGDCNkqRphrrExIGhA+1QuPHT3SETccsxb5h8UhQDZ9mW9VJlc+n9vKOoyxOwMwO+bTstV Kp6q1aPkd2xvqoGYWcY9O81ILDyB7ryLkCwQhkiUoQShb0CzVkMuVb42+M3qtgLfTU9wU3Y7bpBb Mfiss8A2gyRTHOd+Cdjg6mQwvs93kS+AhvNiSb7RmzmFSKakO5/GG+1URqxiJCs/U1F4wY2S/8gv yLEU3u/SzbYCn+AGa/t+CEijivHErr4STdzyU/onFZ/G+T7CxrO0eoOdvYYmk1jkegExk/DhA+Z1 rf+zvGkN/JT+9Z3jyQwS84WXaqGOpYfEs8gTJHu/31SNOyGIkg5JOuRP2CyGy1euzJyW+SvfM1YT JGJS3dK9f962DBSxhdl1roibG8ESF5upoRgT487MBo1Rn5ZPYjwD0irlZRzVMNawftFFn4HtYcME 6axeZFtJ5MmQb8WBMGFcfOI2znoWYydAcdahiUmgVlXhPalr/xx9p44yQd+KBqRKf74iPyDBom+P vUnI3/JNVTTnD8/CaNnC7T91Q3K/TiqaKGalUZ62rNUMD1qoxDgJOj74MoLQSCAax+z1tXMbWt2R PX8l9ZR8CYaYYPkukFJmGzp/C/YDQU/O+qIXVedgFy3pFKdf5kYpo166f1yMuiZNuR+ACWKr3/qX KvovPmLJP29mtqD94UFpfYy6w1i1GZ4VRiBTlqCwQrKHpbgMHXWRT0+q8XnI6eemCr3l0OalDu4r 8BWQOjvnoIV7Ab0gNNnjo1IFeAJQTOPTcfDWhM2p8oHpWIFUzQqzhkkNfteaWkPxL2FsbomcpwND /xphPEWcKroVw3oLxdQ3jr5luyGqBByPbB3XjalPz9yGh5ehIu59Do9Pw3MJa+tSXUHjK59lyuKP ZgaXA2J2+JZ4xxu90c2qIow9/jJidHc6gz2/ie7rY+TzSKQ8bvUZTsFZm9sNJFVQoB7pvkds4Z2Z lOqlN85MfDhJYo2Qh3QDRp0MgDstFtSWRD/zfEkbuCNLALeQXRVQ/4OwJjhIPw0qNXlsjlqj35Ao Wr7dwZlwoX315Hdzb5ZVPaeHw13GkiseB3J4WnfyFCWQVDVv//yZzwDJfMfOpt0/8m7AxwQnyJUk r2VD0pn3LvhG0PsXSHDhT2rdMxaBzfF7sAKImxpBDEhHSwyRx5j8n+fVM11Z3hwQLOzMFmcd+xDe 20Aa30D3se9JFSAivLn15731o5umkA39hM2Glhk+P23cb3AiY/ncbOJm+LfsrZis4818oysiHPTy Qo0T2r4Is4ux97URDnJ8rB2Tf4k9OKqG4bJOFrPv8KSpxwd1/r1PZSaWtn2gc8x1KLIbQh3ZJKRx pgTXXzeIcu73k5siaL4uySmTmn0qN9cQYpIEsI0x4iPSW8mP+erRooY800NOIKu8VgZiZXDS3xdR WZb9FeaTuSr4JiHThzI4YL1Y7OIDmjiqw2LbCnJw/9MhoxrDqYzyx+qqlEY1sKHm+aT/8r/JyvS8 JS2Tiq/F2xfNLEhdMXJjvrB6QQ5Bq+ew9ge/OO6WGdGtZNSJcvUCVF/NEJKfQtj3kfCg/ZXNykfy cnghyIgOspCNLJeaH6Wpt8ZsQeD9JQNS0faKT0JDlMEiRMkH5cGRkDNQdiiGviZRX/2tGoaB1wvT zh/8ih1aJlbevZwuxSxefvwpUWqS069jODfA/1sGepii8okd61wp5hzpZB35dK3kS2Wm0jLLzt5n 9K5Ty73ZWS2U4m6d7+c20U1j8BP7crV6RZOSvw6SGKSMvJmJ2w38lBVZ6PRFZzwVpP443vmyQ/qW kW/Id5MivdaoTNoDlNI793hkGJ34h03wjsSrR5Z726KZoF5wmW5kbXFeoc0qplp7DwLoEJTraMos Df8gF7udmBgyQ0D7GoygR5rJFELl3dLkMPPPD1936Ad5Eqpx8Hly5Xc/q2FSnkI4IUSjNKodjhgY TrF869W6njkbCcgRvxCcZSGMS5v93GgTQVGZT2sPXfhOFluXqg1NaIU4/Jr6aF77U800rjpCfDPe Fep3WyDtwFRw5ZymOqdDmRxaxPgSvulP9Os3CcIWCHJhTGdIeygTLWlYWVpsM4oc0jek5h+S0bUU EKtuKYbIavLCSPzGBuuWw7esbDAFLuuGa5neBAj4RlyUCB3hfO0+FY5ludYnKxVTadCmyNub0mL+ 06ctBXERjjug9gAtTIAN5izs5UHXYgZ4PPkzQsejabj+LmwwoOfpjA5gAGUNMX+PSxinOTdfNgTW G8MKRkQc/soW7ELA3DOLGidwDMsIikFgTY+1ttDttMUy3Qph/ZHMHe4VseHZSxcOAsWRPvPBlXbV +/cOFXZDeFPUFUYuOl40hmt8fDjGIw2PjuU0wLD6P4UnyJt7FkT3+VmXWxa6jGmOKIT7c8ARE7vE rAdDxcMS0pCNdEIxlEoul3hVpAFddzVwl+sYEz6sZweLhI8jIvCCjLbdnoBnZvTsZbyNGHKPEQwA KNPn6tu1/96RssIPM7XXl9TM8qH44LT7ErxUROtmk9hyhcGKUha4oVCZa6Eql24X3pZuhVgIQyuj aHGticmr3cW9H6SOvt1GYYbTqPis2WQhpVej4bWjRrINbKbrUMbECL419mRzSHQ7YKyl2MIEdt4M MgoJvxVBUcQUuM7zwbahoFPLsT+JxA/3N/mwPBYaWKXFhT8VysPdyw0YmoagXVPex6tdU2KoCv9c WWhT7Jqit2pVul3eLro3ESnQUUdxoso8nYwPz6v5WFnCcfWMZ3Bs6/3EWHFQr5u9/VhMtLGUuFQe vFMWEgFlfuVYd2cpKNo5HhzF7Apq11wwh4bXCHoOahMGZa3MIshM6gb6HaVLLAXNRsaFEE+upbEm d05+FUbE8+uZXNuQMrVBrNoIzyhtQOmQs26ht2lsc8PkA8sx/gTAxVeFvB6PkR6O2cgg6iA01/Sp RRwZimncMjI5/uJUg+HM3Wr9+3eTRsJT8G1Qs+LCUfeEtw4fINriwUYnNsvropwtnk2SSsdbHKY9 iJvHHvrLqDYa0l0uY4Hg/cNtOO3oQGzCBUh5+6PfidA/1FFqk/8g+3Agv2SJB3lvgcAJvYtJDnX5 x934PrhaAKxKWuU2p976/eA/jpIlwLZqFGG2SNko/m0mStcRXpljkASgDI0KD2hWR4k5CJkeija0 3ZnKtQY3ZTCehZZWePjpQJN4MHKrO8iKZuuOT7ZMkY6Sw3BI/2Gi1R3L5hsCjtwdOHDTDKvmfuOW v41ZDEIirtrAA9/Sm5e8o+6uoFjwMpUW2Ssl5tCbzx7iQcsUqQwOQpzP3FqmKfcxunY1sjkQXlx8 SRQlOQEnmcCT3wQ3NtfwZOS1W67ZFwuv71hIsyN+ubhYqT81f7bSxaSwRSeoZUEC3/m/ZFgdh8kG SknnQ+l4xYxGWRzp4hWKXBhb4em0gsP7mrHGz3sSKKscvaihjLRVmmv14WuJxoHwUZGQJoTD55zN 9G0nzmwz2mq5W4HGwWSBOSd2ZMxpu/9WLcrjuIB+WcotAZgU7gFcH+FyveRuVP2pHiPJIcg1l5JY cAxMycir3cIiBaueClNwEg336uvj2nMhTqBoEU68TERdhMOuVEYqteGKQPyBVkYgqBBBhFw37ttS IWl+oA5ntjoNjD/UcDmBkz5FzCL0vSbDKdVv4+Sn+I8FRtf7X59TFXa9E1Z5QBQKHXJTBUbhoeTK rgalQj7whj741WEstF6FlQX09TkhN46ObucGiFe1b9XKlcQqnewIvV9doepmX/9BO2LYrkHF73sG gYxyJr/KmVVLwWq9ITXHjvjp/e/8ZBS/SmOML2UnYPzOdnajtgCYqKV6Pp0ZV3T+yT3ejExJ9BiR MeEyCKXqIwPK6WGdiHz8JaNjxi42tYSAcm7tKk0mrEvbD3YOuyVDrBU1gdR/gGDzEM6l4+s8MdiN dgOTmTD02HCvcbiFENsNcSmvJmPFflh+XCH57vXM97Ta3okKCCzXZWwlzRPgbMBi01pUiFGd1UDf HmbiGWbhT5vzKI07BstMv1ip3U7q+ESArQlyN6DZTwCF3nPn7n+exukXUspx6S968TA0gxyFnJUc dP7ySsPz+0crsDZIDnve0t3xCYFJS7lN0AReaQPWSFP5LX0fjHL9dRx7MklF6ZRVfhX17EaX1JD8 nF88cWdZM1N5wU28puavXXI6qdOCb+p/wX7Iy4OVawcuHtR9c1GniWee8mwMPLHc9O6yPMm0yg// /pSszjs/BQ5Q4hdnqeBly+8TfWq51ski/DdjiRZ6qoCGPWuGfecie5YCOdWvzXDV/TWcJvmLf/tP UP+bX7vAz3x5IQZBfFxhhq/xlKfOo0ig8Xz7xvRrcA7gN5Qcn00l1LqrFSBe1lL8Uuqp+AvLfD/b +52/mSK3JJ33sQ/pEpilJy8c6d0OGUOmz0w347jrWLJ8eyL8qcFZCCpJZMSE93Ca7NPLHdwB5Prt d5CqghcoU66oyBncNEiNJQ4AYZNHrHrT8dRF2xNVOkzoj1Rb35EllL83r42Cy9G5eAql92Ic02zP GFIIsHSrFjIVfd6DVzoOvnw6AjS5L0uuDhOm5at+jNTd9C7BYxMOZB/fG4LtXFMHxpHGx/psyqd9 yvZSmMlQDXKtiqMiwwvqRu6UPp02OHETh6nED4vY7/vBpWr0kREva4MVXXbOtLkCkAbQZChLZaiG kZHRWtQYsXN9/iErx5olRHSBjgNbNhwUH9HmhSFOCfWpiGgLmlRLQiIkuo2AHOeSeZzhxh2Gfe3c agL+Tismj0hRMkWVcSz6iGPoujCmPHJjsJQcKbrPbTBHPSbWxiJ+H1JqMO8Vc/87ElT1DvM98aUG e0tkUx6lI1dHk7wNtWKcmqapXkl+RiGZMYnGqWTCaSPgOqLen1FNbGaJZXRHiJyrzk+iH4VTsUoQ Vc0ebCk9drLd7k0Lg8LKsIIx1Mh7+der19CE5Hhzbrq7m4/eaE0A4oE9KUUtwURk3lXPhJEVD9JD AIUUHPHqU4nhYQdiAi7HnT2qJf3MGl3dxPzROKjKPZmP66adyLCpGdtPBfK4xNH9u3iMvveJSzpy KtrswLhTaNtDuqPOv4mz0KclgheY3x7NkBLFopwFOPmB8xr24C41kpuCYeoXhp0ylysd94RcNz01 h2kwb1SKvr/Oum1xZUbKz6B2ju4/eE1dsixjvfKtj1O+KX4j662GMyDHIpV7bCGzXR5DkAHhS+kw OYW6AhtCdmnJdL0oQ6MP4LFUdH+JJ9IBeWsm5PUPdXzc7qDZ7Yek4+HmUqQ83nS+pftdhlWOdwzG ozkdyX2YknckQgyJZE3ysXebePB7seHxyhv96uAdGUSP9wx7dOYCWwQrib+xyqC8zxpZr7ms1GXQ C/NKONFYvLen5li1dj/WyuWptzEY+DQl2jJptsUimWOx365vcVg9dnvf1Qs+vhE/sk3WY7rpGRt7 a6X26O+14vPDwUQGkUPQVfyvIefcYWQnguQtEW/ksoqpf2jkpNiBeLxR687uNZJUBZKEDDgy4GH1 RQaMEwN1tWekk+u/PlUEmbSEJfZ0BrzaiuaYvJU5A92cnw5vL+8Sxmwk0Zea0Iu+7pH3iKcrdh+/ WQmS7KjlkRfXqH/wuFH6IOA6Ln6+TZeM8HHnAgZ5LW0PGmAni/jY/e+Y2TqAq1Jk6awUZmSvjyO3 ORpVfzLrer7MWk6l71LQbJvTlVNcFoN9AIp071jwlZGGwllJMEK1xjVMmdOQvgc7+IZvkzCT34At 3R4+GxMcy0NWRY+dPynOKL2ofGxhab2yhzZG/qq/mqjcKiJK8C5k0gxK8aJT9tzpyCnBLkrZVost hwKYn+vbM7R+J1in6MvOPrJqiUkbCqV19odl2DW3rXBTFGakxrshphPud63Uy0X9gq8ne7ccVo2e M8375sZrhrYf1mRUQFi+UAoCFHTx9N2uzK2RbIzH4HV4EJ2Mp8I9b5KB6XNTtDUPEqRJu2DAjOoP NtegLdBEEXOEi3klKWkD8xQW5s3yhtHLSSAEZsQBReDuJTxG4QHbvXEHRDO2z9hwZ3mFXqvLivyi unT/cH9UeazAoUs9ELfOC+H+xc91597vyo8bWegvrLaGvdeGA4XKm/cCJ3BCg9nZJnuUyy8D0UgX /Rl5wkKCBvNGWdYzaAL8n2kXo/BoPqqScLFUouxOM0QNUMaisbLQXAm3vT7zke0466k8sJF9/x7D LB48yY/HOSpFVQ3vdXXuUIzufBaciSNh0l7FF5xiRjRgNkMIBXd9XJgJlq5FhOz9WA3rVwoGHve7 zCgMuo02PCfYTY+7zXY4L9Rgs2QKM2hhw3ZfNtneYdQ/JnGvwc4LHLeoPMr7GdjskbEY8afA/4xC graB0gsxu2J/8wOU99vGAHMlMtfGz1pI3CA7UUGJ1mF+s/BcO4z8D7p8Ym7w3gUM9rUNtvnSjahL yAbgrsJBqeLLQZfFHU4wkD+PkWCc+CpkeWgbYXsug27F81P3Dt7EIahjSLODV60firxKmQbfXWy5 RUSdACUVtl9DZxkxw1udshksdH5S4P35xSIRKf/mhJwaIcea/ayLk4hh0iaUjkK9sMitiC+E5BBY rNF2x0oX9ltryixvqrcs7IqVFzhe6bjcd+Bu8RfObxqEXCUGYBZUjAFandK0uvqaQbHWV7rhQvba kfKzYmypS9oUpTGAvCMBcC990qEHe4nLYYJlRyke59NTre1kG2hmqodBbDC7eOnTTZpsVPxgGctv Tw88DoneGzwHirNVFyY2edeZAi+xnIA0MzfxlGHbXi8FwujSzslq9GZd725mUOIgChq/v6LfOtSe BY3eUftTOCgipGmRxruVN86BU1zwXmxAHmo7Jo3CdoaR9BwAYNm8o01xInIcvHSMNJWVNXLaQrxa bdFT1RrA4u1cEpFcm7Tjkmb/bbls4ge8M+Nks6SWxRdEMaVjMQdEmij+4FZkkzOsFeT3Qg0vT8Vh 7RfdWe6gzwVAnfHHlZKxWGiTO8C1kgMf6r6G9JtsTtU4cTxI+6r84xKDcNq5H6LGi3LbRAgwKuzl 5/tQCsdtCD0KzRlkduSKBU5yWr56QerpX08Dw/Zvwki+wD/ZNJa7rYr54KXFKt3P5tvzSpzfR5yT diCQeoO0YkCAneKfcqgVHflMvaRxDzoi0wVsnk1SUeRml12B2pnqY/p9AVEsRxH0KXbyXD15oxRy gC9NAAyFaahFFX2KMjX2rpr3qO5N44kTrSnJewAA1E9egQRac8KeN6csiYMXM2ZiBEl1LPmzH8XK 0FxHuijf9TVACcpxzKmL+pyXQtbnsUvz0W3OdXPT6992pGtamIBhszlkVSTnLwAHnUCPavevq8TZ H/ASc2odO+89Yk69fvPBYkunq2I/LgL4rP+ITpD2MT6puBHvy3p+79J6itx9YcTAy1c1tMIBh4VM fIvO9HgDUZPJQ0ilMyl4EhH/xqMKcz2Pqrp22Vy88qPqrPNfs3BPQHukWsAs/hi0IyBXKA/0uXkZ V0av6aOQwcKVzCnvXe4IjY1noVzduMbeLawR/AlbvsdJfb/zZfnEp4Kzenwl+dNBnKyJfeNKeLIH 5cakPlYOABb6TMfGzUpziZy96ry0VzRt+Lb+A45TDL8Wj/7nl1Bn9khV9itPEXdX70g9cTbbzedS rGxoBTqs5cAxWzMvmwSHqr+QgsCiLObMgytxygpxdf4zKJXu+gznaTI7pmbJ4hu3cpAgnvRMHNpT fSBTtXDjKET06/JF1INHBCX/Ml28vCCXoyqpMwWp1606E+gaFtkB/IV1kFsILj0HEYrtBHZr8h87 EfwhN9uTiSdW/tbJLJaE04Dc7igbtCv2/9kDPvRYfGIOKxjzAnDLJrg1JPFnz+rnY7yo4VTnumku kXdQVbmyWEB9vQv/7hq3TxfJ0BnYkmOvO3YWuZHZ68yVWJVXMeqI/06eFAEsVzxFCIIgyOh8qEfW zI/ySjPUMYeSMtL+MdtAbpHvJHI95KfX2eVqREZYYE4r0QcKIk0jbq+MsFAodUotgZPX7eHwsFT7 do1A8zLfdKy6jvf+r1K0BwjJL5nLPNAAThEj+M5qUUvH/PYL+hHJB9BBHxCXCmqmuT4RZtntKwaY hUIMQKY8Sj/WjrzqDm01D/muZWu6EfRv2BUEhcy9+s+1jxN5YfIZXk5lGp3OUKZ82R23LOUGOIwL +0mDa95ckF+7QTXhgwVrjuwiaWV8TyEtv86rt3jciSa35oLR8kI3DFnLVAfDz33rh6UGQYVqFlFo lOGEc410s1Zt/furtb6CF2COyd+roEXUhRK6cVEjW8zAhs1yjsJWYoofpwIdeMWCmkp2N1mSb802 K26JxaxK23oTSRR3RmtwQb7eiAOPwoF4sn2KFe8s9mqUHO0wXNkBd88z+wEY2G1pNIpp6v4EOUjG oET183Xc4JjSK3xZtK32BXlDnOcYqV5nO2dY1TXPmnyUz/fzjd9oRMmve8DLCj0tcOskzb5y1D53 ZiTcu81bCd6E3vfNxpVtVh2nmxlyCDK6V90BtxXa4vm/g1F/S544ALTgaqJwfrZ80CpAW+Dosu2z 7foY/DgZPcfbUadUbXnyHzddKPPsmL2/rPWqYKIEV5WXCKK9m8vMKBZPzHqDwF9L7pmCMf2aJkN3 GqRt5jDgSnQmgVfmZbwrYeccs0MgkdHiI+X/qSV0RBPS1IUO8mjWLWFck3FRbFSuy07I/midhjwT d+sljbmMaF+VY5T8iNgXTxAwoJxpfNxgqzZA6PVvCJNPtGLitY7GIosUnXoYeypGMcyqSoNHyQY+ EAoSnAHk9t7kFO9R+C0/KKeUhpUF5DSfYan4kLva32FlXtsw31+RmLZr9iL5Kbw51zhmn1b7LN6P tEp/oDBLg8BnPfnUxIIfDUOmdAHZLGPGP2NHowWv2Uqur4AZaS7SL28bRc1rGCFCEXlMYLuNZAEF RsoCvb6LP6ivZnjSqOVjuqLOn84gBWXJX8h1svUXowR3W1LCjSdch9BR18RcdqyT6s4TrROz5po5 jfDBIaSlpKMQIlo6ehAEsqDRe/q8vTvUC16eNCJgYzH8kFmKlj7d8P4Chnmu2O7IY5LIHvxRuL0b 3z+hxUCmNWVpfcdMIkzQOBPAvpG2mW0J/0DSZg6pOJ78KvlZ/Duf8X3Xkxsk8rvSGIdfa7wXHRCi cimcDflzIjLTJrcCLowLEGYELRiZ9gvPCkf3w5ETif2MGVlDN21wmPUdWigDI07Wbbrm4ZnA7axs Dtp8SSZZfXejdp/HvQL7QV4OaWhkttMoE/TdNy9Za0U7kmH/8lAyLOx43M/TXqQsPkaEvo9dYVv/ TJHKR8g3D72PfA+c4DOwGSqm6x9WAoNOCpCqDJAjXGaK5UnuS7Iks7hB1w1R/HrLDAuPu2wIAvuO Rzj6jqOAvD0TDlNWyXsZbHyL70/PgqAXpP5f/MwBYyr64QZ9U0Nh0h6g5+rMDXnS6IETDtBwFa9b I9rtMgbo5PYpADBn6lrBGHQiE4UqMhCH/oXfFHmyl3N3ooeBbFi3idDT9VbsnPmtN9I9VRbr78Oj t3wLXkap8znS4GkPRCuDjtBty360M2vuVLWIj8iq7cxvWhRqYsY2LThJoL22wg0pLSmFOpxSMoCi NR0V8rx1EHPVOJ3/CYEPcCzJfvoM3WKMeHPCobEMeMyO3gc5F+1SrOeeRhqzaxBcD+AVJnjQridO dfhJ0yVntSi1Ly0J6Ad8ayzQscpcZLQnepFMtPKanlyGtT5DP0vhfPqwPqdzJ2DjZSN5MUh1T6r4 cF2aQFB0fERVbeqkTf8Pz+SrtR/VbiIc9spaZ4XN1v7I8pyvG6jvSrau+Ko2yD06+3kwyo580HM9 P5n5zcdlxUd0fv6eYPUajBqhtIY81i5FL+M1CEDus3tZ43X2tiBABdLPzZJOci+ri9iqxFW7xKj1 5IoczDMIgE9qSDrdb+0o0e/XwURIic/OHPuIEk9EGcCO7CsCkoGNfDLTl/ojw5Ftxuo7HvM03WfG +A4HDVrVBxYnzXbg+84dw7vJuUm/QkBhLX+yg405pDPOndwHTiDMdct93oE5R8q9UpZS8CP+1Al4 zEfRNaWKZ924Fn55etru/wZlioGoClYD/bm3SbjTTEzxGqNqTuQ8TvpCjd/0ISfzIyWDWzJnt07i zD+5wN45ekmDqwif7e1vXyIWIrxR8md+8B3bBH2of3QB5ApwgU3xAgkgCoqaGYw3VeR5958ztqZG crGGDKrpdyBj2Yqy/XAHuMgI+NhMjOn6gSsZrr9EEAxWQhCRe3rRC4kuIisxA8J2BLJcSOIuoAGW Z53WsFh232pvecxe1XyKwmCrnL0DQY97GXIAoTPIa6tMBE2AGsaOoMieSBCz3syKIAUo2Bm6mPSS /UX8IMZ/BssTOLyDvAkMEyDE2tg59F5gchG9fTTXyK99Z7XqwAVoECylsjVXVGCugOEv/ckvvvQX uFQdDell6VMCB7BW5Pomy6C6BzzSCgcMFWPzOAbKufG3zRjGuz59iQTjbZQaTROTrccS9VHa5/jY gk5n+IEC77k6h7KxdTfDh7cXBiKKNUYRdM10PwL1M1ETtvBkGw96793ovwM2jK3yNYdpcvpcKMpS Gfgm8hsPhASeG2gLucxj169f5hA0wfo/+nqVEztd9SDpIwo+TzSFPrItgjoMIDv8th9okDI/597D zhvc8qbXaIZ1vpogowUeWPuNnmtyGETxP/Afbiu7c4mZGJiCDrOZEoOkfTdcHW3miO2Wp9XKNBs+ MmvMDHz9JgrdOdOLDgnvEY0DwOV9G1/Ma8TmcDCcpZXSeO/0tgQOvPfCaIAMiwoOTorotFLynxnq aHP1yt84Fp7uNoAFLHZNf9e5h5DXFL+acAVRY3wV3nZudLySJp9MFxyaO+VnPyZuqJIRTGG+UMAy SLlN10rQDWrrqyGlZzWmcVnCRv9/BwhX3V60cYgWfy4MeOeSYNLoJ+7HhIyIFAJuupSbxTNU29dG yPslAZzs9Ykfkg90CXM+/87tmdsE+66UJ4/JKQTjdYJZWF8FWV+hPm0Esj+kPAsXL6bYv//bun5v KbG76QtrBvVqO02HmAPzTIkC/UcMxYvnSjerosm51hxrzio1hQU8mOormyybRAjycj9NSSRgDC4g Xyi6j5UsaywUcvLvxSem3rXC+ImCb+UVqQebfItPRnbJ+O6uEqH1yC+8hCCGXuBL3CdU1Wotkste bJ3ZypCqhj5hZGpCnsHEeQusjivHMMs9XkZGxTA80QA+okvx0ki9II53z3H50/SaH53B6s4hsOtS AbVJF5uYvUIFNA5+tB46QlYkcWwahfbq3hQJPz3/w/roUwjBfI+xhg48ko8yti7y18vbFf6fv+gf o7NPJiLj+C/gWdZe6jPCmfkWdIE8Qckc6XgMSF4Co/mhkpG1h1FMYZfHCeI4Ac3Y5g+XP2CeyO4J ypDOyjhuDvWHnNEnUGF0XJ9VAXTLrb/ZvQKQ6do2dKIANmAk+sG8SOtn+9ani3omsGKsLLwBHrPC lQ+DuMxOhR3ecLi+9YSNdS+LrJX2VTFZvhqhk3KTGE0+R4xnYrGgBOM2kP7aC8ZAwBt0pMN4NLgM AiKLJndSnDywNtpyhBT5O68kw8ps0YcPzXqzirumhkvs7bUvuiiG9aIYotfFxTplePkm0ooPxJYv V9goU9PDFwSNxjQYh90Ml/FWxjS/j+EqnatA1nTnSPGx9OyevIGMOO+scFhTRzEqYl5FeO0hNFvG JiJVCWGJMKY+lOZf4fMInxodaToNsI2oFprXnrBK0eiufvzQjfYAUPfsHkODBZYrdWmRMQOW2CAL Xm+pICju2pSVm8z/A6vgKD3AOtYfN463MUjVaZuarXpK752i+QfyTIMDXUFVfOOc3Y9S181MqUXS +og5PN1PCKGhst5STXLYnnbpPuYDLt8I5bEwKqpDK8M30pCohiP++8qPMy5XsCp4Dp+bfPPrPssl rhVkbLAOQQ7pNmMQ+//L9ZLiIhjXCS0DxX/cx4VgtmF1Ge/cmTLiI3VbCXG9sb1EeYYRkbjgDi/N AcQooHD6Jkj+xUglUcAiAkW+fbNpbPp1xyv9U6jijvhroKkuI9YmugSvr1I+UD4AVrerFh9zL+KF t4WeDmjwWrpFtYrCZG1Eu9UOzqJW5opyeb3rV82yKrHLVvgdJ8/he8gsyyeR1Vv/yPKQNOTBLtrS 3Y0qdowfCLuTllz8Q45XUchSKU9SujPhKSRWEHrD/84q/3Nl/IbCnuT0NrqxCqbSL0YohS0X4EWy 4ohZUd1X3BfXjYesr/1h/hl7nmITMUqSu0eWi5bahlMdFbQfd5kT61ToGDOooT0Ie1y5TUhn6R8T zg8j1ZaAcwqlUxw1ppHJxdyYdc+LyCA6tiXeptklj2E+KAQM1L4eRZNI3DZZ8/7b6BPYKgBktAiq SGnIzOPBocUbifmVuAZr7lEwffN4d3on1hsyWMoQ8YwA+6YAUKzkVioXdPHTCb/s61uX44fgO2ez pIJq5bruRlMgRtZcVuB8FFDCQxpN41jODXZKBAnK06TEdOZgEf1b7CCE1Jjq7VizaBlMJqLyw0gb SmwmY3S/4eSqpCNka0UUb1VZEu25Q7V37dqcfcbUMEvp5mGyxODJR2o8Hyh7voEdqI+BnxDY/SA6 E0A8vuNUxobZxlX2zApdrphoguPHX+DLxKhGex3OblsDh3JnRsOS2L2MOfbnSHc5rSooTtYWg6bw 2JDPC/1Kng0lun50FAUTUXChMlSBqGgErhaXpgO6YGj38qNMm/1SnK3N+KfTpZ8Jqsr6AGq1r9kB iY93AXAoiq/hwidz1AgU9NMWn2XQMHknsDOXGvvNumydaOvzi0psoW8aLZXNVlqN26vau82U0xwV k9zUYetc9Jz78YD1KNHDeAzw9G0n8gCh9ON9c5sdA3fS4/NqJVY0hpBMt9Rz7xWXEA/Uia1xZJsT fp3zukBD6KzRKMkxBRQZN82sn7I07nlOHKe6UT3rD0bDX/desBFdfigXzFL0R1FritpWHkf19Q9w a1I+CIgZELyUyq1wfCsgRHi0d7BMMW19uZX/IvLKjRWQlNTan9RfzOZU8Qpl9PCix5W5mRHVQGrt RVZc3n0RfXE2bipN1tmis10KTnjlkRSCTpr2TqPCMb+7CnIPZOZ6akzgAMIe47aZfboS6UZWIR+c c8gU2dBxG5OwXH57YduKDro7iWV+/6VIrN2mtrEqOycfr2z7DrNH2Jpy5/EM7IY8MgWqAm0EkLgf 3r7abz7NXEgMSxyarY5qjNQ3WlKpoPkvgY1aC7oXRuV8KxH9X9cMvAr+okHm1fLLQVD+ckRAO/Ag jFcuD89pasaiip+pWIHAQtnMon0jX/FKfS3sFGr5wFEgq0OpAIcEKRcUdtdjkEXg1Vp19Wfsvpqj 1db1Ao9u97DjnUUmuFdDBe2/7iSvI42kqTiS7qZhS13POiL5FW+GcMmF2SZp1tf+TNgo030EPpBa vkx13Z+DOXv6uN6upGWJOq+ewPkShCeOZwOfpHC2p2kHJHEMIMdpuJ07lPrXsLOVgc35h/drWyoI 69Y4I3ZeyHPNxcnqez1Q/N6mS3B7aVPlBreEbgSdI1X3lR3zZmuYT/53NhNDLOA1s+AMk6GSkqEY 5BqT+GpPsVCPCswvn58g+eefsvviQGewf9okIlh3Pnpk6+DyJB8BefEKpPaLYnzQpQvAuCX5OaeP 60lclvh4R5hTiAt012JC8Y4Y40QgTk61siFFWQJyPda3FCO83+QMoD09yx027nKTl16Rh8SjPok4 rJDCTZwjZzbw8MpWPKqikbIiz8G/qlCn5T59GEeibMZHvpgVU783m+Tpy06OQaLXqMnXBLXslRm7 D1jBNDgz4Tl6mkF3sdsG3psQyDIXeVEM9I3GFDVjVZhs071c1IgNqzrs5i/7CjO547tkC458wjnt t0fZV/URgdohPwSZqZsYgNR3ieJ7n0XHNLbdy4zW+hhzFG0sXR5pmh7wmcA9nZ23tALCsDhAMeaS XHQ9h6IfihoUMIVblxqooG0VfLXh5/oNxj0R8Dk8dSWCgZE2vwmp+mq410RsDrRgwRNenKfZ82sh iZxzkf8bVWJCVjB0pDLRpOnSWSzGsffjbvwRoSSykSCMuLuqfLzM3PC64Oe6BrqMRPABTbiK0ey+ vd8t8l6KWwJr28D425383/kuCGFMKX40i/31yGqwnn1floL3pllFbaCCVVyzzkUuFjWZ7JEqPeT+ +v6vBnSS7TQO97RUqw7IRPkozRz9DlD7j8xEnrd73ZXcLI3pOW8aTqfW6RmW3WdXHbjmkdU+0ifs VbwqdNsh9A8eDpDI5S65ME4h+b7gqC2xZS/ti+rCo8jbJlIc8XO6zhTgI2Znud6v4/O0hB1xCFWD zKJHMxfmnsVDwp//sTK8FPiAcdkEnAikxec1Edojt/9XVDMni1aBM9W4LZO9CqX2iIbtHS8eZHYY 72iN1N11aS/7TDwx0aKXadZU+TdLvT1I7mir82csDccgmm634AKyiDxqCecsnVxQf1CtR9NlBSzs cxKFly+P0xtrfTmFoO3S0n8ZzPhh/G3+xieVmAOuQFaIbAwxbpCIEhUW4n7jP9Q0dkiie/0jQWLP h0H/Cabk7SjTXmNxfWtgDYOZP4Jp3Rbqpzm92S7uSEyiTvEnxIs4gNqQOUtFda9RJVHxlPPWOdTS iVaGOFWGtyvJMunIQ7AvY34Z24QrEYJWP+L6wz3jNOjDjmx1AQX0zv4DjdGPVh1VUp1pdBC86l1k ZxCrLrkYGLU75gwnYfJgX36M7bBVbaNsZlT75dxlLEs+RK8RLScbLQK2Sv7YUCdT4PioUOb7RGQE Lc9bsJBA9EkhTwdoRIh1JvKgAkDj9Fdq7ckvgGU0nU17wlIMy4OeOINri70/5tQfbrTeViXHtpu7 HTqn0zPbP0CUaZYVr4oyX95Tm2nY2m68ft/WR20BoS57y502iSQq/Y31fgFs889SZV54UcIRKRSp igAmpnDjzMk94IuvR4b//2eKVMMt37cBHZCi6ZRKr2QzzW4NIRrEZUGYwokXLIynsbVweakZSTnp hDYDQPaSOFVVGDcwX5cox6MV+Mi0s0RWXpnXR5kSSonFmbdTqZ4wNOCKwFcWbxmirVaSekDv9BXu RRv/GqaXHVQRLrjIYvbRL8qurkIxwPl4igZJxfUlVxcHhtC9dRUL2rPwysswClFne3aowYEWrs6o IBDREQJM1L782PP+yb9FD4kM2ChY6X39kDVguS5rxJqo5CYBNN6KyWEYBUcHnumDeVBPmKIF/MQh hU+WPBalhYML5QDMaJDBEa6ol0AfqD9NOe1tWJJkL9r2h/bab2Qizq6fqAIzGJVjDP8jbNqVhkja x+fJ6QuyESlyHKZGsW9UuNdcvIs6VGsQ2FBNpTmTyad257NbNpe/ed1NnCtitKsu5tzO0gSLv8l/ lMQ7KzmefpnOssBSm/1Z+/59EvdYhLWgaVMKkJ5P+10+0WaETEc2reSj14jI/EIoqSGU/yuRrxtK 1uhTcvZWPtao2w3W9Pk3vOv61kcwMgXOAGk/Vk1e8dL5baK9NeqHLo9s7byGyzY5VIjhPlRJPG4B zr4kwLynoCliNNriRSUXVZQJ3fUA5+J2XqnZA5qvP9XoLnRqjypIdltwPJkqMoAYdeTC75xpSKCd uOAlZd6G7LsLZxqeEWB1XsOqxYdsosz6sq0s5RkH9MkPQ9np2V1+ADnPUcV/HmSRK+oDYIa0UR2l usRY756gGMbBFgGG/4+ME0B+K7++nw+UunrNwSh3VyAxvuMKHVV6wViu2tef6iYcj/E3BTvdXaOh G4UpwiTXgMSPEur+RLOTDc3+mzJgGl5CZTghdHuweGjPflX7qI6Bj7A7Joe15LuF2I60fj4rpX3r vSMRhF/pxK4FXeUIitBQboKsYrBd550JsSFmU/JolTshSbpLEz6PacoYIiBHRBMEJluA++CCKt/c +m4C8WgThowEjeT4K5MLl5MJA7tnyIuVxema+OIY5Gd8bOl6A3NSTUcpgwMt2VHwFlErJObcXqsv vql133u6GWOQcXlfYElOLZBohc9w2w4WpgcchH9mbE+DH7Vp7q9yqoInyqyULmvMB8ISOnMTu4lf 39rMdps0Rma8t8/2S4kD7jcGYj7uBLNAKiNbxWqf3K87a+LWyhDNzGx91iWEfCdRjKbntOhcS30R mjaQFTYkI92M/vWcItvY3qvc+Efw2BK1CYlfGRbakXeRWa8uJ6GuySz5+SUFPbx+cRYZvXqugowt D98w2DlhTjEUXkD/GpqtgyqZ1zEgS24tAC0ls/95YQQ8iW1LW50TRi7exTX1iD4wysvqdkTH9Gs0 VyhXM08senbNgf5VQZHwhTjDqS0PXd/YezKiKLncSAQCjZhrl30sBFvT1vy1NODX+pKwbvuc0Sqw DZTcysdO5DhOUxC9injppXcYlQn0Iq45kC6HoETlVrcMNnqBGJ8je63kmhXc/iwF2qP9QCdS2qSt q8fw3iwq34uRB1PUcsKW5sAFBJ1tQZVSfmqwNnUjVRWU5ss4dA0u0l+2c+K+xS8zwNMl79VBWYzU HoKdX9cpeR3AcyAqKjmywoAWYBmKhY34H55wXE1E5ZQt6F4FW6xwmo3o1U5eH3jT7Rc5OESxP0NB YCq0epRmF1W7IClA9PgBewiPWCRIKQN1+AM/9ee4WhiL9NUdiM754mWoii5smW0L5rMYzZWWcX5E 9mlB6uAkicFtFUuiu9azxM0qqJc9k+MPNEt9tpliGZioUiWFEnfOP2fj4dNrBjfYXm/iS3F+4zHT ERSkMn9upU9039obzf1j2L93ADXjJVOVmNr1k9sMuuMs1MbVC3CmcSC551lrAlYnpvoW/KOxVHjk bah6b21PEkZnEaN4G1hJAk4Ej2HC5h6WTvngnZWJMNJi2KKKvP76lCsY/Pqcy/z3Qed6Tf/V7//w WhTc9IHqce19V8elK/sb8HpVRnuXKiXaM53B4fkTak76U0cevFwE9p05UBNjMremVON/3DYGF14m b6eT+YWSoIs3BAwMqb9fB9A6iTqSiECqkZ5Qe8/f7O51O2ZdtcX73oXJWCOxMEMst0+4D5tihkhs L4OZLCmmHTjD4Bbca9QK9yESM9nFGoOguc3zF+TkRrl7JuJqSC5OlALcGKTB+uoZwHlHoCa9T542 XCjSeYzmgb2nqqalePadc7BGpJhLKzDqihRg66QG+VtwKlcAGHMsh1OpxEvCtjHibo37mwc8tu2x w3cpMBaTcexqdU4ysuyEf69JjlX+WcNZ/qBseMd2x58cjM15MQSmzzNiWT5ZSCLx925hzptzvQ42 EaIWQCJ7vaZm/w/Z65CjJvtyMLa0hgM12EfnGzRqWHP0GY3uE9xhrxd+o1Td3qWvF2bo0VjuTP0O H2JNyzaYDDLnjLCXlcm/vKg436KYkVdpru/HSCS5xf+ldEjnfCut320oEt1X2qjmJ0fJKsc9uCo0 FsIKo7zrNRlUX2OjLN7T49R6GUugZ3cDwukxJ7EQFT9Pbbo1IWekamQkJUptGA29dud3S0GRgfZf I7J1WqK9bT91cEinS/W8Xz5ITG3LVbwKHHl0/bOv4s62XbZUXWBiDSumzrT2EhXL6uCQ7YsiSTxt jlWWSPcFKZymVDdIXwz7gNgTkGmcBPPBv/ZVAHnJp5fYG7tJ58y/djG18Q/mODX1yLPC+OOw9TLq evmo5bEGuP6/49dpfhtDI+qbCpGopn1D1uFaZsYqxjITU6Zf1W9uGngZTeKxnk9w7zb+0fzI2dLy 7phRji0IRHoacML3m2DZbYp4q3hJxvY432zZrJ65Fh5zCFTb7mZM5S1ItumalianAsvnXvofilHo Glo26FOhj6JwdfmyRAnXx3LvSgXFJB29jZLnMf/sFFZIDNeU7hynjgroicwEL1UQhsUtAru/g4Jb xZ+SE0UhmeRxtu5DiLAcmdHAlJZgFcOrDjuiM/gzKFkNc1w0ZzIiJq0KW5GKZOk/roDrWkoqnoVu vWbvFsPOdwESaZ0lf/qiUnufTgdfNRvqbiAJrvetOGZT3+bXbCSeN9BG0AgJ3gp1HjKtTdE5tM8M OV0tFzIU8nCwYJBJwSQRBbBfhMe2L2cSAtKh0NnDwYd6qbP4vKr/dyyfe8eRK3Y8RMKza7iHvBmb +7Ol/tmdRGZKFEHe/WXUM78IPjB1zrUjNPLSkXdufoWuzhHReiCmuXHK4K+3cLVhMKaFW4JHlKj9 L76JCKE1N/s4yyxa6gSzYmgPaQnZgGGmvQ6g14zZY86oQszg3Yyrf0byDv9qaMTpeONKcIKnF1Ie F0TeJzuGYqRcW7aXqmdWA2pbJyo3QqLYdKFNSoS+uzZDq7PLzAjVRAGLcj88UKJiNUVRe1S2XgHM 7a1r/ATOI2C98VSMmwkONQmIL5TKwMXb8uWMEutieRiJBh5oTwK/U9hrtrovOrYSGld8JKXndxfX ZRFD6mpoaB+qOXmTagpUGVAX9NaRUpSvoX8FY+9f0fAKDxwLUwIaetjxAyITn4tgWFmCKeIyFZVW q30PHILQnXQU2rLiWgzwzIjDbxavp+WZCPYalgYm98iWuo7Gyi9wanm9ezTI2vJ6rV9JGxAPFgFG ZljZ7YonDTVZ/vWVQP0dCCxmcQYlqMmu53Kr/Tw4SqPZeL8+1g8kGbXyplRrOPESL2oT6sdDoLH3 DGvAY0vmnAP7T4KagH7+ewc5DWuWoF4jMkD9zMELrCi+DZl0Se5y6v3UHgs78AwnyquO9n4A4Tgj M8XAv1SbcIh8LIKjEySTADi/OiGGkX1Cl/JcMs5pymvyr7d0mBNHjsZR+AqoNlvOJdW7AL2C7eUW rTMsE/WJHoH+MKcKn9CxvogBELA5ZCcuFdRhFp1iaAY2qJI7SSKfCj6b8RPMGRlAqEmRZQSRFKRE BxUf2OPtky75ReIpqbMAyD+Wmb8cgppxUN9ItEDS/yeHMnnBM+XMwPnT2MwgZEMRuDqW+hCxcnqU DRmwZq9aAMUbTHl++xBW6/CCCIj4EgRFo6BDyMxc3hdprx4S0/uRcnRKelVG9m6W2ZXx1kE/SEHS P2M3tOfM9IHd0C0IdDgvoeuY2pHQEJZtylmXRqxFxMXeolHPqcLawlgU7Bawy+BhIR8iqB+Vbu7E +J6jTR9ABOV1+eUEli3QHjn5psYvDu7vHtBeQ6hl6+M6j4UmvgnRFfXT2Z5P0qREI/jv4EKKjiLL tDLtC2sIHavYIgtW/nwdudNY2C5XYzBwx65DfKpkwa8rxbKkqX7g4An/7xQxk95gROoMWtzBXgrd me/hETBiO8cXzZ0htMSI+n8ZZHQbhsFsIaE/rCKvXxnyvqAUBiK2/jexSHrTwOl8w0CdD74as+bO qhTD3g5ytyDLRYF1LGjn4mES2gPDTYhvHW2xDcvQ8MwW+jbvQgbg5p+ebk4NO8LsiS8H1cfYyL3N QiIu/WS9ctJPWO8MFnWE8JOCh56CIBLSBg7vN4IjqFWulXWV3E0UEFh8WTU7DoaxboLPToky+GGB 1J5lhWNgu6Ciot3fsGQEA4kXXNmLbQ222ZvR0m+JoxcEQr4O9RdWaf4XdDBP0PMlF4l8cwYvnEjG zezsK+nV8CeRnlZiOCvEak6zuoDVmMOpNUOyiWyrsVGG/q2K7M/P11NEW1isTfi7naq00yZrq3cy pStfrKsgy0TIYljhX63n79wBfV+1w//bqOFGu6tAknbT+3SNsKD61hCgX8hsGk8HDsQzbeCtQYWF /XqqEjVVmrrRjB/PBRdJ0tmxEh8jnPsKJ1H7Wg7B4GIiqvegrRVuadACI07sAV6E6riIPvgCXBEt hxEPizfIMLLdWU9ZSn7J656op9yCCjgmrYqWHxr6ejluC+wMby5R5WiBEcgyTKSTxhg5l1vbqI9Q HBIW80nm/pxQXE2oLGosUFrHXAvf+MbgCxWN4WP2KOEmv7PATZvLgl9ouiNDzqkSnIu+jX/mSVy7 pppJV8D/kqKMwIpQ71+CoLaaWztLv1jO7zXo/P+ayvVSwmT62jw2/FDo7XK6ydnlFRb8g+hmIht0 oszbTb5KTbscQkyoFGhWFlH9FfBtJxbLhzVsY6jcndPSz7fOS82vE/pgKf6pn1lzvoJa85G4ubbE DAa6ubowyg3UDl85hDaWV6p4yOALARtxT9BTkDNnqVfTTssbcFcpWtD+rG9LEFbH3fea5JArOxsr ziW2UTMXhz48s6wih9TNvC6Qtimg2J93X/Vyi6UYg6JJoBDN4bQEa9VjJ/QrbcQG6yNSbQMFJPK9 qxG4peGrk6TRNkZ4VEidSUVIEd1fOkUhZ9Ah4v5lTeWXa8lELFqI6xD+u5qgyRa2w6HzdWag6EB9 iwJVyZfe+zwaVINfiYikkrMYaymTgnhodihzXfimlRhvqYvs2i1Mx9Yl7vegSRlPa32OeGwQz72N t92gFkVYAK1sc7GIkIVhJ76+WcHUCPLPwS3oWlGT0rLz0tBK/PV77m7VrAyOnMCYbDYfkEjyNr4j Kzv8uQ7R46t87Ch6uwB8uxTyNWtVscrfvS5vXh56oOYjboG3T5zh9KqEanfFn52nUIfXnJL0Q0X4 Txls8l5CDho0hMbCKMBntGZZj3KJOV30O5HithbZ3Ska8msugjX/3sqWvAOPWSBVa+kCH8Pd4Y/9 GU4RgDt5l6dWrp96DekCqbpqft7G4jA9X/AyDCV130O/ZMDRUEONUIoTjLok9JNYI12v0Lqof/Tt ItE22OX6wULYYJ+J07UJboGGZ5lGsP6BAa4r+l8a9K3ZlwOPZqbdDwt16SNQGphnf6wpYGOxpXa0 YLMFnzgvhYfeTOTcOAJX5vTM7pfiCSTVaQX03YDhprqsuqGrjoXjrNdDcKs6R9XAqR5y77aGeGoe kdYivjt7TAadgrhh/8XF12k42zBJAOp2wtU49xuOlN04mi94acuD+OOyU6hCmfwS5QXfZAH7JVOe K4jfNAkaC2wKadgR6N2yvYhPDhUAvTux7TlR/02UaENp9fH0jsw+RGoUXonWd4+V1Vasq5pTin2r xzEpHbH+kSPVEcFBqqI0UYJbJ+OjtXOhkTFsk0ScaQUgrvcRjKWq6PdrtZZADdsvaq7ioit/iE42 WrDx78O8cZWJPrEDOQMiVtTmNWXY6m579Hq+H662n07rgNT6yL6c/gtDV6o2EEYdlvuuMFclsz2E e11x0vVkJhHQrs/nCSM73vOtlv1uUWH+PleioxyOQVe9l/pNMFmCrDgl2DKb7aca2WXXKlMkC2DJ gxWLIFUloEsIobDq38/8mCqnuuIg+aVYhBwdmppPZT/BNh9b+bOYLE3HWdu0J8Sr3aSICkk86p1m ngOsFq8oix6tEL12jDxCbpERi9ckijIUBecFblFIT7BXGz1C/sfTH0K24VxCngIMR52RZaqWZCAv 4wfh9b1LsEAeEXobL0kX6ejPBLXRNYs5LALKY+OYU1fUoIEBAApugc8B+zD2RkS5HQnAj8dkyDT2 YDvxtmqKDeqtZN5f29yapNI6oGPLA60IZgR+HNg5tHY6wqaDtreK3ywmf4x1424BSDDtCeGt20F5 07OqdGmf3PwRw3ZeanoqzQENrCKv1Fez4hUjx0j2wVpE714RDhbqxfFzL6xn8rp4Zc4Hah7Qeszn mlEWRwK/rW80MIRC678Ewh4Yz/3VVbXaaaDP2rCkHnR75xlyJPpLA34LA5dkQEX+R2y7fgHf8k8b dlCHhbgbZIGUBRKib03K1mZeGtmyfPotSW5c+Pfqx19pp9Fx8dHtNpzdfJmlIQTzgZYUk+pKM449 6PDlcj38bcB1GVl+6Jk0eQ+gs9+bI/sXo2FmovO781ihjEGA/8B8vzVVY4IhzEGYJTcSlELwL7uu XZdgGWE1hhDAjb8JO1YgrRKbxf2EboMXEmnUv5TgEdNrSH8f44hx/JoKPxaxJ17l6tFiGAqLo5PN MxJboQTOUekIpxmiIJYot/m77aje/tjSB0L1Dq581+M+vDuAx2BQYI8JlWkUWWOsE52WM3LXRX94 VjjGn+j6FT7Df5WPdvDmiKWnjgoTSQR85mtE7gOcp90JPDoGBWO+VIcMahBw6DQd33C3wMxMqUzj mAGFF6j3UZ1TcvNLjyFghHgEyw8bJRyLI0ml++1o54zJoKHR9/WCoV+a4jJe6GyfsmCDVySSkqCH zPalOmGaT/x+06t/6pvllhUd64jo1FUwYrb+uKjH9vs2GszSbVeJKRpgR1z7XO2A9CCG2YNeD4AV FLPoJiRzmLby8KZsX9pakpvasxZny25dz0ajruHBKYnLg9Ss4PVdho6NXyFN7PIN2xePdRSUeaG/ 2PAvsBq+fGk5xWwxyUViWgEqcnI4Tz3hXEKKkghzqlBay2EdtXS5AcqOIJZ9zX4z2MEfKINvdsrX VQKBINlZ2OnU3zGsuEADZ+0P0avIpuVS2Z4XJDcB8egL0FSqcJx3fxsDwEXRPeLzT8LSFvtSvT4X 5c+yrw8LhwqRCKR3xsivyfcPyDEIpEvU60cx68xe476P+ue84J896PaxtYtaBs8fx7YTMy2zM3Mn yEkWf6fgXplv0hnT2zO0dlHeJJqg3JTPagdMQ1OHT0bzdtWSmQEsi46+n6PhwXBzbbQQ8BReQwX3 n28Axhw9QGzzRTGy/SznAI3RuWhi4sQVAvkwZWI+oV0o1JNgozpvHYxgv1o3KryHWtekxlbgkIRP fdkjGzIXDFpxHRcu0aYfYP48vW8+or5Gw2lFQiU1+x7BZmYQEk5S4ZjRWFbRphZTuOM6csB3RT72 HJAzS1vaDi5W/r/nRnLwNJA97USbWjEQOUl9RQRUk5L8yc708MRAEqvJ3Hmp9nQSfixB0YmxPcTR ztss42cafNbSc5bAoggLtFKhn0WIb0cYvOa9XyrElg7dTI6bzgcWwDcx0VWsWgeGpXEC9tjzZgoX qE0spoetbfwD5afeIIzsH+DmLWtyAdS3jKVkKiS5KttRX6DolzvVm0QYecNdwM9wBrF29d4rtHge i1sYnY2iZnWr6vjh1FDTmG4Wv5Mm0t6I+ej+GxDpW/F0rPVcGNLzYdg7zcMy5G2zD1In9u17/FqU cNSD7YQzhEL3pPpBUwOPuBWBYIJ65Tz3SqW+VzO7AZiTAFhi/ppdN3Qk57y7heZ/UjTzYoAQWDqY CQDqM8hXp9A2/kzBi/XUiWVBY9v3c8J6e5YmMmrSAN7Hf40w0dWgeKqvjefTQ94hKPJ6lTmvsO0z ATXk+DUVjk9/joW8YqAf9+sj1OR5YHB45gqMOP3RflXbONRKiu6eO4S/cRXOpo2P7AmBDn5kspib 7vJl8GKs336ahYlXV2+tHULqQ8D+GV1dTpr2xhvziJa26cif15h9IhQC4GeXnzfMP0h7x3gCgID/ CBBd9PucOHtV9l3b3QabaESgeKB6t8ZyytuePNU+0H4Rv5AMVltIP04dlYnL2jk/1Zg3UCwtsTfK iSEEbwhwFiHgn/QAvSmHf3kSNVUkH0F7FSiY6hu/3/2uv06nxIadR4mTF5gx0PiUh4Ni/I0N8Z9t XlyhBs0Cke09dl0yFXytyj5e3z/z2xJR1RPcvHv8JNV5jV1phPPoQOqQyKGBdP2iw4pdbmccRfVB wDJsqBZzT650QDopPBxUmG2zbSC/eMEK7F+nD9ZH2DYJIHbziR2/pxYmrypODg3mj/xPE5g8zfUL 21/Kju60fj3vrmX3s5R0oJIDyp7aA01z8XjJssl7wPLtmeK8tmO3hdk6kWIiYHTB8Sw/bVzEJbne Xp/71mrBbBfDCD5M4SfIoAcjbaoBPhHgo+5hrH/f0ROZ/ua/X3kqFjoOFdYPhfPmIn4oGTMF2wzT c3WieLVIpf2h65SSFCfHvGyCO5BPnDSasc1gdb4oz8M0GmmFjvB1hpZ/F6pe3Q9WBvqsp4mO5RYz GH/QPGRTE3Botd66A8WlRm6+HJIw1c7qulWj+smc6fFPuOqT/DfLM4sCTS07K/E/L9O2osN6YHL+ qdgk/nM/+ZqbruWxGnV/+jivvbeJpcb8Fn/QGzmkuE69wsQAGjXSRRAmZjC/nR3F0cun/pXTiCX5 Nqg5MykQ7Wf6KvJpZ4kZjsStKRjF+s9tcIxClzSO81Ff0XVHVyTMKhZAKRVE6xgu+Lb3TyxpPLYz OPqgjJ4/ujT7bUZI2OoEm0rMY3+3W/UXSkGm9wVFwAbB1HkkkRTND8QswiD2vgLcon4ned87FTyF bCV33dqYG8WndcvqJjGq0foliBUMTw4jIPRPRonEZehibb3/Zfq7iTv21Adn5y07g7Gvue29sfG5 5DmqI3vEyRhSPxqhwUBnCOcZPodZ2QLaEknrsz0GQaPsqjrR68zPNBfCNt+Y0sL48YAJE7hLgYXX ArnZV1K8Qz81rIO2SXa9Mr7oADduVCLsOUKCCKSpnqqKJAV6veg7nKKQaHcZBNLt9xSltFzF6wfm fsFJnq2DEB/aqv65ekBcO3n+32Ofy3lAxK1eQO4kr7GB5vB3jxr9/DpRZxuIQ9O4o1jbDnyITj2f Hmykiv3kX/EdMJDYGJ8reDcTAGE+/7/JD+wk3ss1zQcNAxeWLqIpeqO5LlaRMHUKRkVigujK9Uan fF9lfO2uJ6YYGgFRsiFNx11Oz+hD0rUdp0B5Ztucdi7xxLIVH6qOQ+LMwR0lSJt1Dzhv/Mnx+SbZ 89+Xj/lIGmw4YyF+UOO63dxI727fT6hOToWsG3+xpKJqELOywNsw5kN24+NQ9HtaIbTl3xjJWXqq Z/scwg/0ZMriApsmeENHuDWUIOfMsJGzXZH/gAYHqUNkc9OS/teJ8y5etDQtqaG+BQKw/RzP71CL RiKpMs1+udmQrwBiNKSQ9J3OjFcoe52j8y3dtQtTKg6hd21Shr0QSA3WrYlqTLZleIBp0KK+e9y5 G5tGDasHArPE6+2/CODF+Kh2SyJNbWiV70vO5kgbb7BN8i4yJ35eNXZu2NUww+rqTf+r0pHuRalY 9VPESJYcsG7OmtjQzIuq5VWGhhBCmtuS5A6k5GMGB06AbInKVho9Q/dSKapBZVfAfwPicc/L0RnC i2tylb1rbPj4IIWGmXRhgV19ojXZ3npg1hLqJ0WtQGG1L+QWeNprB17bssUT9rLFUkvLfB4arZ9K FcIow6DLujfNDkvuRjA40FliPCazQMdZ8edwoYbIg7svQSXj+WNSyBSUufESUtHq6i6Lji/thQ9b pLcJxzLjrto9G45D3/suUFdN3OQpWKce9nx8/vxNSRy6H3tNsZB5w1DPWpMEtRzcq3nKTYufmqU0 qYoJ4oJg7dpDNq7HzOFe2OWynMH9kz5htyzVVlqkV0BGfTs6RpF3/KzF74FV2tBseQmsmWYp+OpU abSDjYOlHFfxG40KI68Hjm1azjp1eZCbw4jv8A3Ff+YdzhDEcGoMCpo1wFwP5UmlfzlT24NlKtVv Db9saZOtkMf1C8ZYwyKnm78Q5oigldGoq6xr0mkeH6xuAKFGlUMnVObZYze5FQvhs0+9GQ7miSNs P6dYIYBlyVHb9I/xy9lBBV7smSBeCK/erOh6fbggAhuMEsJusx73SZCQ5sbMNZHfFuuxb3/P7l+Z Ce+0qBpMxMRLIBn0edNxyU7P9H13Be7rtVLx8PkIEYdWPeGq4yhnqpLncYjYwwcAzaiYW3qgraI6 rbK+N9/ZIIx4dYSEwv5TOt/21FefQr4N1o9cgiIOQBXzxJPgqz+KMAPERsb9Df6rHYuE3G/R8N8l AX4A18URtUOXg3ZGEoI05HCsWWvUN5Jp6FQSDWqb7bgxfEZY/DGSgiQN/Q/HpwtfEWIAWKqtqxzW gq3eWR2KgQnzFxrH05mrrrV+qcwTyxfGFAh3zoFvZxsFlMQNgP47hb4cx8mGkXeKz9t5VP3P3saF IRYQ7u8Vo2HtUxxvxHdWxlbYSrmAWEY8gBQeg/S18YoXWh/xhxxsWOzKBg9j9OJTzEZGHfIEIhxr JxjEe724mkQl046B1sJlUbfIAfdbLxv8RHVIIophRWvd0HxUL1v14J4yFKdP6KNWp5mUaKRQKkwu DepzkjekHS8Sv9pyucZVMxc3UkGEhvLU4e7MqEGwrX4LTdfGUR+oGJcAR3GwEhY+7c6efG2n+VIe lAHUKcsrNMZyPBbcfJHQSMeU7eaKmTbAmbmMJc3yWvQ0Wma3qt/RFwas2Gs6lnrEupRfERt3C8qD 3aX5Dzgb3SproyUi/uNXh8TO3wJJ+qMCFaikvo0P8mWY4NdJoQZ5KdZpsdn6mO09dQkVRUHl1xaJ cha++7WOiu5xX05jFu5HGyg3xo5Hv96lJxNttBv5z8/rM43KAiqKpchGQs1rZL7iufIdCazM36bJ 319XaGmnzJa1MvbaUVUjCfKM8vcFr10HamWmmKdnnmUOv2QM4MF14HeMeRldbYV/F/qdBbkw8Ufx CMtyuFHi0/piCWLb1DqJQE7G84dP1GU23G57b8laqr8QVZGPycg0lnpGV2PZzLxu7cG6DNnFEMOo Nr+74ItuAuSv64oXgRRWyCTbu0cJ+IH7CDC99KvxYFojA8XJdAGm6OVFuIfjibvg7YV3711UZWdL 418iFlIl8C3jCcw93YikAYK4R5CG8B9Nu8aK0bZ/oH3vcLYmicLYeZsok0ljJAkYoGQgnD0UELmm t9VINb7LVDU/3cqlYxIm5r6HuqfqvQI6O0fK4ChA0LFu+zUKuQIJQLwzMbi4ceXHOgsFoWz3Csg0 F/ynTC20qklZPK7eiyFBq6pFFO0LWURwtTs0KVxwtGkKlZjmhuMzgUg77eqKNB7seuqij8RJoGNf Xe+MsrFQjwxAel5DbikwsLLR8aWR/EKiqXFFPzu/RIYPTQ2cnJCmqyzL5909HguLcBvX/RJCTiTx UFVNYsHkAbHnWicJkR+z1uZmb1H31rStkj/QG7nFKf3/uK6QarhUZP135W3KgcP2tui4pUY+2XTZ dFEAd+3YXk3i7FVb3eSDWEHuohWX4233nJ2z5zxY2FLiwavMbbrutYxEArRDv8DxIJqR+61k9+wp AhjShNH2U3riwwyRocRKBunLUsw/eYK4ZOYeratwDmM+bvq1LMR2pHhcV4Cu5QR0rLgudzmhTJEC hpJZxBxWxvKpiM+4smK7Evk3YmdZqF6mxsiMXR4WWqsE7Q5+uLDWYQDy48+0gpnJZcyg9fh+qfCx Ox0q2iBHz7JhCgov0RM9vsY7z/Ou5D7PrPm1q2sctALYEJnqnMa4aAA2C1ZFjlLDVsNujfIecBMN JnMXmP47GFRopb3dD4gCcJkuVqZ61GKKTB+fG4At5ul0Sv9Y+CyEpa5+JqV7O5wOr1B3etSJrTfC 5s5rrcFbQ2xQKC/701MPj1fAQ0zVzd3YCPPo4He5penMrhcn88qBIVSMorVYdJkyC1aYchuV45QQ CoUi9F5AaFa5/MvxLnbyq/fs0QkWHtH17ePmYUiWLhbKHBdFKLBZfbUYQkNWNLSuqunVcLMR/snc P8yAMcpBzaveD20gfeqwVuu6XpRnZHemm8RJyTNoa9hkh2fDUtv1m09joOTuH9470IxeqaWa9GtP P0GupJORmudoSDojoh01j/LCGuSelmEgU6LuGO9TREKhrjaHFmujIuRT1vFi96h8ibF39Emnc5cc OpzhonL3bgd1j7xBxYgZQTb1Y+Pa1txoNfe66a70uzyGOHzdSeYBIQsXu651lMbq0RTvFH2Bg4Kl b5eQ6qogNe9aeBTnSPKlXnBHPw+xO5i4bGX7mn8iHm1IY1QAZfwMSv3zic3xFkcYh8HCGgOJhjHx OPo1/IqAUPoO6EbRCZdB7l8oz1OTih/FpNqQ4vl2dYD8sd6pRA5R1615qomOIlXV66VCGm5gEHGH Lwe9w1sgBqdPh8HFg9ZLwHRzXwFWrjiVwdB/FJDkXtEIvXkhggvzHWJ0zTehPaQv6NUB/Ix/WIgZ lSPPoSXxpPX//pI2Ajuv3Guwf6+xWRvRBgE4tKLm0cp6/I+Yk2uuZVfIuPirC0It+wovUS0KotgO +E0ZFoCgsjTxO7rTqFn69RZy5J19D+wfd/F0po5WhIL3i1Ith1Hr47I+tjCbv/ktaWk7h12BkXrm jP0VSGy3njKOnXiYA38yRWwYkzZ1kBZC8iCiKKVoQCqD3hCnHP72YmAQI0pH6bGlvvVi09GdCZ6w l99zfUICO8E1zzpSp/nAaUCWvlKmiU+gIKTLB89EsSKgBf/iA9EnaxRUSbZPWUSx+9veQBW8cE71 bqw5RDtzuzmkfEx3GqYvkNGiyOEYvhQZgoY9ujO2W0c3LyNJvanQAr1LSe/+z4Mf4tteDlVQ3FJl B8g8NNlukEQKv+s1v6HJzX4srmbQKN9WrEse724itiF4Esx8vtWtSYf5MGX/tjn3hUWpQZKku9V7 qWE3+CL/yk09tkhIkFFlUaFyHrcKFtiBZaEIS5GT7GY4eQbrZ08mY9t/l3B0923AU4vgxiV+bqKL 2eB5caKml9TF/5UluknwBrNvS4UKNoo2Q7DcQ40EVQr+sXsSr3MOEcpuZn3CW1Eq2sT/zztalvmw SY03SJuof21P52REV0y0CVPMpwWhMulH6D4VOqYV5mIf1j+PyMrMHuxhHhukxMK7VaaIRdwJDRoc 5yHlHZJQdxTAd1C9WqSSYMd/CvPGaZdwx5q9LrD4dq8huyKiK0J2yEa62tH4XRhNoLHiewXKT3Uf RBATT+fAjWZE2sy26xnaW7bKOp0QdE8/8nbZo67JM+QSGwFbYUNHqFavqdWsto0XCEEWxou3NDHf 14y6kPz+bW8Iko3FZNQs/5PtP5SiFfz7Xlbq1mkJSfVQfr5mQu0LmhRPueiXJWPzt6h8hQq0X4Mw dJipKbSleaJGkXyczZF8vd269DGQkcf8hzdKEnFv54ArbEnE61493Og2GWJZRbjK6zXU9fZKtCG6 77opF02zAlGyQyxe5dARTaPo9ROJxcs5g+dfZgHWqX4fkWwa/WNdrRslutvXxxB0xfxotsM0zr1V J6GpXLiQLRNXBUTaes4/Fm0kHPNpY4r8t/38rQ7tJ3F76ccGUAhE8/HypNRmPzYI/1oBMJiGwHQX NnWiOnzmtEo98hvWfVG4iXgpZssBuT5hPwcyXgpWAeFbMWtdzG9eMpA6z6tZs9GV4NYKLbnN2emw quWL8vrzLbTH9Glo3MYUBI7j/vOezPG4M/rSatEEUY4tW+7w1tPsT8Pz3eAAXmXDG2rmW9yQ6EQX Gi4AEhRY+RtdfuLKhUNUXSgGOXpGMZ8GYQsYmpfJWwzukbm/vrXLSNS24FT9m3ZndEJFuS8ynCfg WTJ4PDajDKZYKbfVzGNA2bun/fZ25MhT3VFl5gwV2ANAHs6UejIvLtuQhur1lRYBihEgARdAJPER 1aT4iuNM3I6PNEwysFwmu/Odb2GRxeAD1XnbosDSSCxLLhMdcWAE5q6AtyAo00fqAzpSTTUqZfGt cd/AQvWFpoUchf6CBQWkOXZJ+2BgnWZzu0xcrUjk7MHAMDu20QyVtK+VuceTWa9cdDWEraeiN7Ny 0vaPAMBiTHJ/xeBdWsIcmknkZqJfZWG3WDOgLc6+2fLWigolcnQurR16TquqbB46ZyNC892eh4zv 9t68VzkD0ANOG6yJdsxZk2zuv8hTdI4w9XAxWWiPRlQw6Y7SXjmsCbEn6tQHADM0N/wC2tQonpz5 PoxahDuO1dEmariDVdCFSeY10b2QAiqYgn+trFZ7Ai+DdXN/7AYFLEqpN5ob6o9oCz/v/PtGHMhv beyJXTJIBo8xmY5u5lU9oiWCeIwtHSL98RNzQ3D1eUz6lljYkgOFtdsAby/wu/PfKIhVITIES1fm 7iJwD6dmRFKbeEGUzJzXRZvlWnEQtC6dAN+azx1uyutcQYnqamcIRrKEfp8m5P+Ey/tazxPmnGch 8jYGuMdJrMzty502qccwKAY7Hq32rJFv8dEQ5YtO0d2jSf+eJJMY3kUD26duyxF7vNG5+tIeXaid +3GQlM8pAxVtJYBAP03lTC+8UVjdP/LfdKUFPp0qzXT3Xfcxf+zllalYNk8/lDnecXoU2oU28e8k q7tZOm+on+3Y5PiDKBd/iXt0M9hCRirUqpsmulw8Z8WC1gqH61pRAnOh+IsP1N8f698JD3BzG9Ht LHOzJsM5Y7pFczxnNfD1OKfOMbma3zoSEJ2Ho7IZxTKrnEdYo5VMOlnYzJ70CY9Lbr0/uM34gAqZ S+nVw9TTN0QUVT8uHd1bpYqp5SQ1JW/xQXSDyYoFE1fOzde5PPRI3/MiuNio6IslQuh3ircM5oQs ZjoWjDtmgy86t994gA6R7bR46miYzBVc5JSGzYQQNMrmOOTa+LTfeU7gnbwkI1ULnKXZEGRPtCZ/ 6Yob94jgEsX4T+L+yZn09Jm7euq9t1Nqegf3aTrUaaiNGIkIxcldsj50EKPr3ARnxiDAdRq5UXMO UvzUyz5wiFQRDSc9iMnoaSVYiMiT3ZabU5J87p9gQKGLQ1LGkxjzkhKNk3wKwELTVpBvftUT7byM 2CS2VPqvTOG7G3GMJji4xRwUBR8cum2ispRcbvkN1XrhJgPjGIvPdmYs0I9aoZh6/+eadw8Gs0p1 HC5AmtSf23XMWzo/D1xadJACVNqP35G+NEqVVFn+MgQDLHc62iBTPTBzWE4X0soYUmXP9/1lM0ul OyS7twAEjY6qtTeVDsCS4Onk+7fgVep+jSkpqmfk8yDTGmDMz4jFRe3Uh33Xlfzh1+odkvXZMRRC Ea2Lfa6lwyWVJjIgOVkRUgG9By3trNMpP/VW8K69UU3BfpPF8q9A2G+xFQTEFFAVAGMW8hV0bdge RbaRSLo/Pa9wOeTDeQo12eFwQ37YH2q1SlrccN8yUSIM9c68UM8wCezkLTOiGeElle/5TFOkl37K ZJeSwMAE72I02psSph0ZYBMXCmVOWoV3B5YU8QhkvmEwtPZy0cnjKUkfnw2TLXfO8JfvUftgxYrR X0I3gk0W2sWcoF8F8/NmDLLJG2+3rDgK0Ex89DCuhGLlk3qn5BdQNhHgJG1v161VP9wcuZ6/C/Hn +4UZdU2q5W/RMLQ7mK6UJPa2/CwWIMXgBiqhSq3qguM4mSf2V82hI4UUQiFsJ0ZUXc1fKylv2zZl 9QnTvR4IdvdNKeUhMPOa/NaayhdYirMy7jRrHfWZou2bLWlDDGM33jWmCFpfm+tBzzPZB/7cX8Py ldoY5yhAdwaxUz6S20biO9ZnPSp1pGrmSv7aSHDNrapG5vbi3ecfcxeQ+uQcnFm/I8Qhomg0zrrE 5WUBQ2no2/VozNOKxdnfOENEZrdxHb6sjzzmFXHFzzFNldfmZvDcwG4GcV61HhgIke+WKnADJAFn JVf++OOiNOFDzCqQNb3PySFIa8pp8g9YjHi8n2QXuCVbEEaeYhUgSog7T3XNXv1xIxE1TnM+7Oee UXJqBysjbqqABooSxhzrR0jF/wTDPIElTUSK8KqUSjNkGkA/pmA/KDq9x9XT2XsSxizmTIqblj5i ckH842d7GqFPRZd1RdMgrvvgaO/SInEexyxxXQiozYWVS8gETrsz3qqWemJ67KSn7XcGkDck6TTg dcyDmYUH7OQwHVHBquX5981u/Sp+fIuDYUDmzml4jD0OUVzEoS3sWOgYAdheRrKEK2VS6EJFC4Xj 30YHSCTuYsQ+07PXeX1TCI032ZoHBvJ7xgnA10347ZZKAFMyLqxN19uTzVKFy6W0uFOsmXLwmYVz 4l3KkDqUMWUGc6Qtxh3kAj7mgwC4D03bXXz/+y80jEaw9lDzNBtia+nKfQtPlIneKJ+spHdx/Cy2 HY/QZwfUh0IaRbyLGVaRJCjUXcMpv+IPYZL/Gf2xZhR8i+3vcD0KEjLCTY3u2f/On9PcRvo/qA13 qhAq2Kqbmsy771cE02P+wxVYxaxoREz25ejD0MYBPYk6VxABXwp7rFuSnb9KJoLBUC3MgZocpSHV tnhER7thWA5yLr9JvQAWCsOlbOmBWyY1ECRMZDqgGKkuG7I31wQjnWNLyCozSf0ILnNamms0FS9j O0BphwZxDdhVJg1Fcevi80xsxK/b68R/Ah8vax7HNX1d9z2VStwWCSy+1spl28u7DrCFPcyebiCv t4LCknE6VjQVQqwCCASlcFSBAdtx3l71oIYp30PHB27vaYw8FNPuqiTRLa+uAnZgc9U76b5V6old dIuctvmgnc448WBcNjACFlazM9qIWKlrzgS2EUk4h9+TQfKkdtecZqB6F/ZZSpqtqr/VQITWC/5M o67v4kJKviSnLwhTcqP6or8N4VKMzjeHc4CORChbha1mBE1XIllZzoRNb1rk2Ksm9kH4Jr1XkOAn S0Wk+XqmVux0CwUhvMu0HtizOjcB9kQ4qCheWVAdK8ttHSvM+pd5nty7wZoVozcx2jJ8gZ7Sj+K8 ivR3qFMQblRjj45JdZ7t7tct0iTRyVtVWNPUkbMq0zMW6e/HpPO4h40p4+YYf4UhQAuzrzG0j9ey WZcW51Cgfb/Pad1rOGmRDuNIMKeU5zglveipK+a3xYUWSwk8GMLlo/hjDyKkpeKJoqjoTzAwNdlm pO3/t/JB32rBvJDQlB5dU/EXgLpixMTo7Yx1Afi4pm4akU0a6bbyEcak4s/2D8gslDaIuQrLaM6g xzTJlaJFRbIMUFrz24GmLOKL6C8HRyhzjvSRhVNZC5rR8wBaY4j9GqMR7vsnDECCXUpnwafjs7EI /bWHbzUkkItoCFU8OecqtpPQyblGCp937tm2C4m80OfPEEstjbApP1Q/5zLVQmeb/Bw9DyNqK9cG xrBqa7B9V+u4tY4kzMxqA75Qu8mJlNSIqDOw0xQPtBq//HU1+71unwgRu6VlOxz2zFPlxAyTOfvk WsYyalRdhENoyklRO6qSzo5JNEMuil4fx2L/Z4+xUiBPlnbb9dO5mpDpD63v/LLYWyVBqm2EsVan HykCIUPFIMkU8xbKGQIVU947n0+5eAzks5JFr5b+4Kpl9v3LnxdxzD9sGH6MlJ3arSFspUNJ8un4 /4JPU4HomQZ1lWKdiTfID50AlVlrffF4ZENGID9DPU4mFb7BtPSGs+tkMlDSdbmLHjopwY3kvLev wCLjy2OWwpdJYPEwX0M8h6iOe0GBbXvXikkHRh4uAzYzbH4K8XYOZ1kxYuSXt8sE7NmOUD+LEAFD qu+4vByn6yzV6vvG6IPnltXqahlly8OD7XGiEy2AOXMfcaBEVMgjozWleBUC4fM650m9XAwV1+wK 64Qjx0uTRrNd4cY5PbAxJJ2jGl5o0vw9wd3qJNrg32oBq3urOVhyxZvxCxKHlLxbyUf5jIgg+MUI LuDd8xiiHfOSdytFCeBl2/pbBipewm/H1xJGjnrlrkjTyl9JedBAiMZ4hSejN8dibbrGAggqqw5/ t6k/xnfBBJTqcxRGS547j8h88s1ERWaWOKsd9vyUSCIfGABM/xEfwWUJdxQj8/BqCWueLHRoI3qA FwcnesIH+Appcsc6dD0h6Gyi6aRkXXiZo32BYnLXXfmPgccTSTL9PKj19oOmfPFxa2xO07C6g5Mo hfbsBsBVfd/xoMhRBUEQh6N2whSuFNGGSzULJOG8TgZ5EzKXfkOEoCO3fG/M6tm01Omh5p1mLExK ZwwMycmAGYfGrSL/8F6VHwh4j/xHh+lmnl3ceKibbGy/W8bwRb1kCJUyt1//iGI6yCqKlkobtmay 6dAYKp+dgdFUbddHvjo1KbbbQxCaV35tw9q3JgNj5JOMlAi6dRmPvWgcfxy3qVRGQn0U5HDkKprP v64GYMqmUig2KK/AwyEFUHFOwO3/LPg1ZyuLBB/sqqDgo+7/xLZnE8qCjiHxX4DJzfQuiIDkvhcM UzmMoZiLGjQuSiQb2guvjD+bWvehk7Mli2vQnX6zOi+GMZQ0AEkJVgfw3OBZb/Jbkpe6MXEPXHv4 A6/PPkRAmyqb2MvgAR1Eit2dbKWMEea/IwreSJR38I7q5FjXsN5kA1zB8e11l++36U+M1vAXaugL NXpFV5JSF6L1lEVP/ABXEBLVOy2R7Py77yq10NI535Jn34U7BGMseo9XZDkrChj9HucLrYdQxopG WbcYO7TMRromANvynYh2ccgmHRDpXqpBuJBK4figczuLdcy0r7uhHZrS43v3g/gYC4naGz1khLZn pNkTF/l1e1039MjfqjiN9VuGtu9LI54KrMkrotCNe7gF6qtM1e1U73U7v9hVHd/ytiDsizR2S5Zq sOrfKAjHxIeUyOyB9j7mzS3XYy2oGJSiyvxdEo4/fVpKtgxmYcSHuRL4VlRUpFkTJnAG43ScyfDH qRL7QJgfbZQyPsqMLUQm+2QKjZJP0I3Zj0IM1JrvqJt4asksnIHJXob+0WaIP7eLYCBXYd1prU6c b/r9MGuwmysLC+n3/ERGx2P78Na+RFkI0ZuU3FQ/yVMXq3XiJgBvueyRr6CRcQxBHgCCRsG9kEWO 6ZkX8bBLVu4xXlzOrGrHFnBxvxSsWkwD6aPHM4hR0/sY7bYXTdI1FpKw8RueVOlmx2iLQ1q3xbKI ZFPpqPT6g2vd+gjOTH+WjCrfHclooohHr4os9YQzOEgzfHXhfJo9TSsCrTf76paXSg9t/l5HJFOl YGrnauP+P+lvfgJV6gILiHJErrRiKDwMwzu3BJV5AQSyy2R6D2Zmt+qiPiRxooED4vYss8o6fWkS J81PNzFyNF5DlMXh+CvohtvCvkFviAUcJLdpyh3IpIOWhXk4k44dxytnS+ETYHrysIK4zIyEIq7c RiNzeYZpDtc+kZ5Lttuaz5pO6pa4emJ2nUma36yq3+EfmGyxs5EIK/flcPndltI+Oosoz8gcJVJr P4pYPlG91RAdYnjtRkjY8/lt9/AAE21JppnnHpX2R8xGe1o9bsHmwYFJDRF44Ijq2njAeoqJQa0Y 8s2x2fdzHLMQBf0umkStx1ty+mQaTQYF3E6KpH9bD/bU6KuHv9CyVBY5gl8LqDewjzR4EDCzUjwG X4U8NESMHIYeSNInLJmOCtbrxCjifpjpSw9IFtganAp6qUDOJc2DrABaXyuyjhVZCuN/N0TbE8Mv +cYhKDOHzBB0Ru2wmNRuQ6XWUEANmiXvgwet6IDkXKnJIbaksWVkqjCjYwYJLJ+nLKFaaCGutS3c SSNchObkfy6Yvs9wLNk9aFJ4MvcJEyc04KPooefkQQ+Dh49dMkmCVGhNh8jIwa2zgWSumGIaEqe5 h00y8Jb5lxbMWtoNDsSkU+n2kVesB6RZ7O+aku3h3QFIo4CBnbETjlvdcUuB7TAw0U0RrvKx825W x2tIuPLKNR/Lvihod8XAn3cIUism79S0Rxupv8xBCzgIbX2uCM9DxFb24eg3/OvLz8QusJYEx0qT vdfxIG+d7Dj91bBjR0wGdkqhw666C7pbUoOfBDAhMgM76IsyrV65/NUx1ICuL6YW3EreJfM4FqLY LscAB6nZIBu43+ItRkdeRFV1f+2D3+NcapNvSxbzGeWxL1bwRckBIyEwAuSBEyEeZmckUBsT0aTZ lKjdyFJl6vwVLKBs9HCZTRYv2GZzQ7+icV6PT+mD7jvXxt0cxzAaFJJv/g97gPycNNa9x/AHakxn OKrY0JbiWozE/stoBtWwLTSHzT2neBrKzns8KYNJMw0b3wyH5I8XdhZhuJPd4aUeg0Cj4k01j6d1 BZFuuSRzUrCnV/plx2RQwFCSHGh8cthaWkCU3auBqAmvUOUqBWiMQ1U6TVAeG8xmb6NoabhYpQP4 G02rzr50sbfhlhmijfBm50FU7alO5pFTFh4oV+BL0gDCDNinKuesR1eu7DZjJBN+P8pe/7+AoFh1 WFLJw4a0gOt0vK6x1zYg8Gn20O5AbSP+jGV4QxeoS4R3mZCPw9j+PhEtTIPorObhQN1DoTLXYOM7 Fx4mWizF/HkPYrP3IdefNhdk0NeipaVXupzAvCOtFwPUSpG4si3dZppXNSN5SJtW1IJCVLRDe4zT tJ3f/YgCSMW0PyTvLQp7rYKVwXw0hVbKwK/nam6044gpGOQZKzcy1ek0hKxcB105y5ZNXfz8C/nJ XtEgY3AxE8ZWF0HcSo+x9Xhjfkywk2eN3wFHFiur19F58dve0B+PajEtvi1Xw4pFzwAkbUbQJHC1 2lHT6+YZAEJaWY9wp7taoAB8So3JGqRwRYOP6lqNA5D55xJfByaObr7VuXRERtn9sLqDAcTsky68 AdlJ2YcMtV3d7eF5k7sTNnyv/GL2pBtwPFF5kFLcgvsGNkRr1w+rRpdDygnW8KvXeTo0/0uHiDdc V7o6kYjE6FY5Co98ummN/z0wMHbvR4ytVr/4/RkAGhDH677lzb47VZzNYR+NCf8CMh8Ljp2xlSRo 0i9pfz+K0eiCjSrEuyxMzX68UL/F0SO7iV0iejS0b0a0pIHiz3MvrG7lmQX9Bjm6nB5ZnuU0AgOn WvPNizHB2dvzKgbSNHNdhB128bMp7TX3J5ymJD6zdAunBkLIGt6FIUGWDyIavqJZM49mCdGLKMV7 1bVaOOAY5/rIO2mO+yK3UFjrpn5JiCPfMSI0ypVnGzxShfN1aI5jeGiDURifb513tSWB2YXFZEDV IDK93zIOf6u5h0wNVvxtl0Xf816+SWXmCC6BzUGZjIVUG9orFrMz23RUpcjCZnz+lGLTT65aGUPj 7j74zO/6sjvOuC9b+QNogI55Qk8ugKN8q7Yv7RXidBbGivq8OKa0bNEqqWMMUFS7WJAqlU95pjFq hYn44bg6htW6+DjqX0Baz5rqVEmrpIdoq+SmKwOOXFJRIz33qS+7LHLugZ8N7iincsPb0GN8rnQW 6chLbcbQlXzusR0FGaWN7qr5vpPZvABgLug4L13f9yUXcd7V564XA251NeZJQnPxtGg6FfFlnqVm Kkj2wsMuYAONf080Bpgla3WFMDWIEyl8SD8kAXQHEHX9WUEtiaoHCVzgRgMfbHr5EUH3gIUVMUWk jaM6k4GnYcSzE4daHV2uxBBD1zI4iuwC+IoVooBhj+MJhM+Tl+ZsfdxKHvGl3jJU3qHfGRToVT/Z boymolwZnGADYy53sqxvYDvB5H+V2AVOjRW1NiXj+MVQsw1FbAPT1mLhv9a1epeSvG13/79TYTFl pG9mZ9bulRgECvPI9FEbca+ZjaW0CllGymnYFw0H4gXlYvSJF1KboUFLUa/vABAiJeVs9GmiKTSH 3uSE0OmaEXNVl0tfn9Lp7mbUcp8hXxrEIan0dPGOzhwl8XSunkK2CkozcoGgxatvEDb09AE1FulS 674rQDK0vLH29rc4nI3xFWZSNAfZQ9ywQNJfr63r4L7xg/Xci2dN1IBAVzeW7DlwaeDtmwuqBPsd JZAnB+Zoi5wnY0qRxcqYKL0WfqbKVucy4Xs6wuDon56cuZDYVkvZakc45zaK5iFH8Y4q9IVj9KmL 0Ji7PcwblpQFyVD7Pe8t4FQhmiiklhEUMEGMsN7J+BWLmkMDVjAcfZGQYoDC8LKIzWalHt6dEAn9 IKSZ9AETdCJjxCg97979fmAp/NE0KYQQmOxKTGjObiUsdGUuE6KkNglwz3tKQq5C66DN091zYT7R JRB2dQiieIPyR30rfzfCSSdGYMQ1Z79/ujX8NZBbGRuvPBV/rhdlroIpH7OVVn5Z63t1CIi0ALkb nbL2B4kx4DyzAXbGjPN35HrN6d1pWaT8WsPUt/fnDniDWfkePOLAwXdYoeMGeEbvVvsrjdUfV9rh ET0mqJZ5OYmWoQwvd3VIoHe0+WcCnjIQYPT9k+JjrQRitytfABCWkzhGx1uGMqxlP5J9WP3xXSGP kGU9qOW0ONxqKfHX5o33/iZ2R2NYrG/SJ3TZm+onqSCQuBpYcobrNBBLc605OGePDvnlhEpRTp4S S/q4IY2LqPsqcJTcpV2rCxmzELoMIFoW0iugaGPhCpneYkXh7PRC5sCaAk5F28edm7y/lOb/0fqr EP86ISU9mZ+AHCEBo0ZVPRICSyVgqCIWjWFbMM0zlOO57uIC+9IBJzSCCHIGkQrfPoGS8fy1XgdS RRKVwv+r3lL8rP/zpiyNIk5nQ+ZQShwnLeN/x9RGDdWp51Vk8uBZrqzPLIO6Ak3regyCxEWartlz Q/f3ybZ6IFbIXhJ3XsFr7vrqxC2kzda9K4zTbT+TcU9O4UghnFRXqrRtiiU+6FbFdBo6XpClB3Yr UuVjGIJpoHyy4EUKd4L9uNVYJK4RJ9HdpayyydsQg6JX47XFVVuiHmxaEqu6VcbL0236uZB8zWV6 f2f9IWIjUBiXMjXVXWBA6WVOOc0NQh6tpQuIl5PvRDhQy3FDCSDdOdQANapAWQOX4rk+KYOqRpag 8shRZUMjFSiGDQa+CeCF+yw5rfM+R2HYtobJ+m0n8YTlSZNcL2NXY7rONTMTJ/kwPNqgP4vzSe2F S6eOyw2aQg6wZV27DWdmEb5fNlc4uGqh8xRImDGKr/yWmq9oD8R3yzwVWJVLKDuaqHC7eJ1WelBc CmBM7UvqGUy59TVAnO9QFNiZ+TY7T6bUkFWdkhTDkRMErtRb5VHarW/AqjNucQPYvpkTV0MmaOlY ObVyc2CcYW0SXqBQOB8gWgF76zmfANQhB1Z22A+VLqDc2E7lndduDqwd6WEptemVIaK+SbfhUAPA 0QpU3jrdYDZMz3PUKXGj9LtBrpkamz3kTuIyPTMfiAoLZup7U+sRLMdH9YrFuDzYkQcWaxzZV+82 ZenmtoTBqViQHjAtTFI0SMSG4BeXlRHRLP+oZz/m1SWr/xr9/nw7Xdhd7lvAgIfGxEbunE1SfLgB jaZuwHtay8sduukvYTCA8ZzPLfpems5TSV/GZ33TEIzc26ze/TqPXSnboEhFdVwZn69MFDVg8Ri7 krol/+eOj50BdwAc92nAKffMoc4k3cONx8izXvnuuAED27KRcw7xM/aEdMTbep4S7zbvbakOhQXn NNGXoelVN4nnBxXObtw2rsTBy553Rca+pt4KuqdeykCKil0S5BbCVB6Km/M1w22YiJ2/O04XHS+F T5ddKRWGJLM0uYT1d9rgxsKC12PsvJpnVhY2nvOJt76+H9skuVCFa/fp5wzk4zzgBg3ZKJmiH9Od Px+7zjL3jkY66eQTleuDURbef8K8iwfw9jqsj2qPxvt2p0DFqbN5MZG5ISXTZhSMbbYOcIJuwLR8 ZT4srbh+Mswah1Xc/5iFs7o/EzT++INglothIHNE7Gb3szerekCD3eOWTrsVGn50dYm9q14pNksi Al3r3aOcxx5uCEc5oS3dNTOnvQq016rpA5pKv/2ACUmIp1KJ9Nye8ohpsm/RkQR74/e2msgIg9Mb q/k7eQh6poiFrCnkfXao/2GnR7xj++HQIjUI/8HMdFUSW8yk5zrCf33g5YslwAL4yolhuol5IgpB z4X0jadJzcQMnGWRx+KX/lxSMBVV0BXm5BCL3UGq4OJhYDYZhIjEbk2JSYyCOGi6TzM0DK6BX0H6 J7y3kKK6UI8mOONQaR8dgIlxQ58HS8JkDTJMBWB8my25V+HkQFO9h5K69yJfW6OEpslEHC2kWhiL lVRf82Ze6PkEr3j/6mLQ6+5lqJ3rKxulkTnbB4mQPE0djvnUHAQ9CG4Omm97O0vtOG6hNV+LhhMl Q+tZnMKbECi3BCHJeRKsMjBUo9U4h5zHkIy+3oJBQ0gIoWmuemlkFcVjz9/FzjSy8ESxG4qg2zFf +EAJjbRu/8SdlbDquAo3BKQ0rWx3VxjwPdLCDT4xF3JfGQ0HxivHMApgeAl2EJsYS1mwYwayK+IV veW/x57GCTVID4+TTMpmT/V+bDx3Ui+qw+GVki7dckpbKEcSYo1rTojsPes2I2bG/CZYNAdjmCWw GywweaGIMkESQYaHATvnZP5oAXObj4BsRgTivR+SHsDjArp1DODqYuvtH7mRkG9Mb+u0sVfCkdQk AjKbuoQm/MGozUSKL7PlqwuBLaZAYBiq9mXbaZeeWX1fEc32hxfhQrPlMfSmTNCSUIM1YkGJ7waP p+nyPO9LZJB0tjYILOVcdcPCdaE7lPDHo6bth7gE9yFqpWdHL1FgHCT9bbW3bJdSk5CjwyVAxdeJ NdBCol7/AUJBUaLScixhmuzDrusr0NmbXir6kJMMGtKxMUj1MQ15VQqPZXnN0D2ScutFFVRGnD7J PPE5/JI5nT8E9S4bVwHvn2kPntMrxekfYVbgpyjzBywNatpXF7tsPa492pvN2yy1Lc6em4Mw5F32 527YLQxxkArrQyBkn3LRHm5HTSIO09r43+oMqBefNsGb/pMsXH3JuKKQdv85/P7Uh/qMJK/OC1yh 6t/65EOl1DpHZm0KVHruGyCUl2N7UIa//i8wahcUaC6Cpku4QJSG9KWQ58U/6qJW3QDxUISR04kX Lr0JIsvmfr/QT8om7ZbEP+rEX3ju1r+IaWbsWPjpYIfqAh8qs4vDD7YBWn585WcMYZW6Ynw7OkdI UvR0gPSMU5d/MnC1LjOg4lQ4IJ2IuGPu68FGFhTL7Z1/m1A4YPHKS6LyPy2zgAflHGjn8jY+TgXJ DtxZ7FQP5aRU9ygL7b5Ht/RtyAq3s7eo+aUCS5pDBBsT0nEiOGYrolb3Qv4TsxelrM4Z00HYd3v6 XNAhkIB5LvC6y0XKQWtwifPuqhUN9uxhIoM4pW0AZOQ8B4ww8TYQMGBEgn1mPzIOA++O08TFC0dT WBOdNCbwKo+3Ryzl4L6P1f94ZI++BBU7Kd/7Ax1GNlmXHhLIbD6MoZf2+xacDHuDpzh/w0LzMiQn 5v/wpDv+F5MrI6wewM7CAa3HdWBuKd/r4DOrdzMElcWZ1nsO2DfzBueSzJPFbPdngBof1M+ekCP+ 6xIGeQ3sx8FSyFnizB9tbMZe0A7BLZFe5YK7jcAgo84YOwpCTTjjHkU8qV5E3WOK3+j2PNs7WN+y Nnd8gV8o/KEbR74Z+zs1fbQ9i6PwCkhiipTlCT1X79asAlGnkU/OncBKhR97mOVsSwzZvUyF+NBT bMhbO2UMi82Cy40wb4Ln1c8tS4x0PUjSfI1VHKPmcV+DTVkIukmvhBYWliYv5K0fEVfhppXy34f9 SAbnnyNcnfU28tbYSeINhM3s1C3kQout/Nev0WYojZX9JO/UbUvEZKa+WSEWl0qH9i3iP6KKM4Ik DYK1c0Gf34TDFR6pXYkNz9fqiKk7sag4v7ncXEW+ULrhpzCX1m9BwToHw6W1WjagE/C8XnIfK+dp jfn0jzCtCDoei2VPHi4sfSi+hr6X8Wf9/JmjwVDw9s1tqaAfkNn6cXrurslmtAHfXU5FLVdMYOr4 XGXBzUURzko14r3ny9kDzbcO7jfK4RAWaMwl53iId3ih5zY2zN38jalPlyHs89QNsm6YPPfY36v7 W+Q8Kkixz6uoRL9C1Wx12aJlaicBgRK84P5+K2B3Ir4HjBdDbCVjwgqm7GlZuB30i0DIEhT4ppc/ 0aD8sh6gp5GqqE4obEmxxmWOcnlb++35JscTBMIabdIOuOfIMg5+5MfZUIEueR//5ohKBVLmCIUl V71JoESFC9pvxLrhcNaydQnT7+we+g8twwuxnjXQ3OlDtJp6rM8GMImee6xQXtAl7sN682LkGAlh YHgXEuQC6kCG78/iIwKQ2nXgrpty040fWjo/kxvAuGw05D8sK1iNCpNrUWUSXyp9hluRkpoyjuBJ E3pLQOAGn8Xfyq+bQWgxPuojQybpwSlXCIDZpEFCnzLQohFhJtY4YaoxJvrHsbZO1WpxqjZEg7jv GuRQkzxKWiOzc1KqLt64zNRyIoTaRRiLTZQmzsfB6PEFC4eRVT2cuHVlsGqzHAuF2fymO0eZLR2F 8gSAERTUuvPsdgFsFttBQPf0oMW05nMjcJJk/ieDX3TFiWNCld+DDe0Khtnne3cfsOMM8PSWNOul mvtAfo3YMw2ufwYdkU+y4K/Xh1WhmTmLjqHnxq9VE4XLQUWbpbys511wxcNoxSiiSsvMk65sdb0w R0lHFbmH+7XHGj4qilkAfaOKwOcY9ZyacQXbJpKqJQh+/agp7VaVy8ik1o+8aZn12kSc3/1XTc/1 4PHfqIs4pa+jYr95g8lPbYVGU5xKABe/DlxUPdvzkXaAVy7Ys/J0/COkVQbcfhkp4FYTY5oLiNG0 Ys95bB3q4QfAZJjg3K58lt1PBZ76UgrZzv8g9r0U18iI9JhMkFJRCW0PUfmS3dY22l6Z+YuVIvMq al6KWymKN5pb69JQyW+gWvIQUCNkAwlyQ44NahfDWDvXFnZdJZcMtlBS1czNw5jvWE4pARpym9fd D2llqogXKJxuFdbGJx76OgqDYwAHhYeKH+rUfjhcjIISJ/XOPWXeQ62HAbg2V40hzHkb852bg1k2 fWsB4evP1cKHW+Lj3ZDGJkl8L5hsXqbfpRtLlkWBOVLSb3kdi7sBnIofiCMe+QruaRoeU2JGg1Qc tU56/gsK1fJ3S1/EPmrp9x717lpctAqIz9ToQvvMC3TuTdEE6DvPq5Y6FD//lGZmwvY5pThmcDiO h4zfl6IdRMubiE7Q3m4NAJNXKRtfDkDml4ROoSxNGZVxfjTXpQsKq85hhTJaExqDEAkqO0I/5KDH rfBz+g4zblBgpG9rlIoK+MuHV7sBGvuCN9hfk1tCEGAFm03hxth0vi+O76ZP/WfP3xCeKmeEBGjk 0dK3w9UTuGUH0/MfpqR4C6l5DIO+kKGJyshs6JaoaYZA8q71vZ+hgdkPzoMkDo4uPKd8SUVan5++ QpMqedDHsmx+S1vbozRMkbcXM4XuVPOnj+Xt13OgW5SjdLMEYPTOgyYSeLQm9twB1tOYIkMskDF8 4nbNhohz0fOnjvwrPGuMmpZMp6qlEbEG1q5Kc1gMv9/dYIgTx/3DPFbL+H+BIhXnZyZmLiDj+Qwd CKI8SjH36u8FgQEm3NKoRX4gJWNrNvr0kT3XYFPmd9fUEbLOx3Ksu7E4yehiwu4uhQxEi3GpNOsi bIF5Ns9ivGwnDSxIyBLcPY6fMLL5ZPFpSicjQBMPl7CCOlg/9q+pb33zamuxMsligCUsnq1FI2/w yVkMntQElWeFxRrIXMPVerUZZNCCnosvmlpB6Rxg4cUEPaRnIko47m7VWf1CcHaR/KyLOKCfQnFi UlahMNjbZo+12Xg+3HMG3GqtjlPNNlYdzCsSW+mTTa0uonLbEI2mCFSWn0NFfeKrVqrzx0qWLc9m CRbL25v4AZbWXdR/PfdNw3Dj9NLKV6CzA2xSiYjYzaB09MRXOnUrF/PN9bP/5/IWh4qkqAFA8+no VLglT0bZmFltd1W/cwvOHO7T2oxaWK35CXOPTn4RnIzV0vmsEkOLifksxKPFV2Dk+QCG73dKhgKF mlCVEUoRHGX9aMSZFjOIl/rldwj2j6A+lJV6ldXf/hXsNya2kRFFHmyYILg/jrmIzpfADddWI/V2 s4XA+ABFvJUIE5IiWh0e/Mpk6obEzilAB7LiX7B5X0uZuzV8aRJw+3jIl8p5UiVxPtsqLFlgkUmx 6GRNEOZ97GU/wKnlyGXiwomyGpVkoiUHwa7ey3oHrZEXcXx8Ks875xnWNSNr `protect end_protected

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/blk_mem_gen_v8_2/hdl/blk_mem_gen_ecc_encoder.vhd

11

20893

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block fOPvHkkMeoG2YSxpdCiiaIsa6OukwnK1nUpGs+ws1Kzx3puslJ7iKn9T5myI9VkVUgRFFN1Xfit5 dX6F014IGg== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block HgNCPi3QHpb8dW9RkjxoUGM5YOGOMgLiuLQefgSbCuez4Gs1lAiQxdxBQhTyXNRS4H89tPbEkHbH 4Kggyvl0Af9heeHWsTafUvqQuQWNgivzOk2qQ1liLSXiEJl1Fyiq4YsawJBYE511/GABOu1E9kTU pmHAixKjBq9m5/peLok= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ACyuBPaQ3cHp5s6xGUvo899vJ+G/MHO3F7Xaj7MR44qEHb8iz7UONlim1fw/l+q+pLsNBpoVE2XP zJRxKhGGODnlablcYtB85txWJY2O5wNxUYSePEkcSvh0aNjf+cMEMsQNe2HL2rZ4QpuBDEvwlv9s WW2rOSkOtnkb96LcOQBvhFfaOnMJ1hyH3fZjN7kEzqhyOzx1lZ7F40vGA4At8E6hirc5xMjqdEgS nhipIIHTzkenqLhApVGgUbafRQbG8ESyjA01uFRtZ25J8+Pr4cs+tPGobm0XSO8t3XwLVZapRDY7 SXW1qYkISFEa6NBGxO81MTbzFuTQYdh3r/X0qg== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block JF/XJkMGoJfUihOS9R76tudD+YiVNpy3w5hfoZ0y9FCS+pWh3V2jVVw5cst7125I/hGyQ4cnB2Cm MpdAa/YBtj6yK0ds1YeuSU2Cxzm0w9QZ3nLSon/2jE9kx1d54bisjxRhEcKKKTSHuw6W+FSHffj0 JOZyc8RfIJ5IeOr+rqo= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block T1BVKuyJOlWV6bcI3uYrVButOZWbfA/40bEMumgKuFASXUB5EUZZP2K7kyzSOvm86sj9UL9ICrc7 AvTcJqoQYQhmFnASRJLODgvNhDHbAg2lnzfWs6NJAS/1X+/rmymQ74dE/PCMYJ57I9d++M5vjskf w0OpYjhlBVYSir/Tk9MztjSWYD+sQILHVjHe47WzcVPfaW+EotqO6HFgKqlaDo7HehG2c2e3vqSf vOR+wJbW5Wf5aDiFmC5wYka9JsKtHRwx6zm2OF25VJgE3xTsK+bAIDPdQfmE1j88uDe5XhfBnRre CJ9sWYXEWxeZpiUuR8hxlglo6dezNGJESHO9ow== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 13728) `protect data_block XOWtDNZRv4FbcK5HgglDAnuoXeeEtQzM+5dwtbTltQeOcgiGL0ldThovapKXwlYS6j3SjEpt1ctW l0HJEu5CZQbd72e/yXjziCbCs84D4Hl2Vork8+ulXUTominLbvkE4YkL+H3FyGOZakEzvv3vHoQi bGRSzkjeHwbXiPYH59tq7tQeJMQxgUe+oj3vs74AkG1R9+2YXPdoq+c0ike49CI+BgwG1ugOKpIs VgL02xZMnagJKOXiUgf6pQ6HJDu7a4cb6y+rbPzvCZD3U39xEI3Y25hhH1UhPljfkI5NOn8Vu/l1 pd47R931h0LHGQ9zMdTwFILbWSSgIXW+Ww2X6UYKBg6+XDIGfN9yLUc0j67yNx93C6w7mxcdUnEf d5XBmYrPp9/EcMoTf0aob/1TYF6e3buFL344aO7XizDEZRYc7KG+GUeDaZr1RZaf39ICNvcxuUup fPl6qYVf8bE9LBoHxQs5BKNxGe0s69ylsGwN9ne9Mu/voJBkPMqFF2/pXAkTAXy5CiAyNLz2D4Qj Kj4V0wZXh6DUewkdBgOgMdnG4/SHl1hzGU1DdVr1bgJrunH3p4DNx7ETzJJKPsKmU685dPc30nwz G1ysAPjxF4rsT7ysCwcKpFB5BSTTWnol85/tmFsSpvgHZbfkKPGr9PEQFg0S+Nth2MZL9N1sC+eV I65XtorUCbUU6VD3zsuk5T9ykchUyiijID+xcwuAAaH6QhEosv3sG3+v4M9FbpyXXU2dv+3hmD+Q 3qI1UDa8udQd8CyVOIu/DMs7GWf+DfuY5Neb07hYJcNC12Web7v6KPXVxOxGkE1kdqsK564hww9I 7if5qaA3BuMtfL3+lBhZn5GKYywMy60g2SdSoxO5GNEuBLToM97ulyb91wYTxuvvcJ1nyjBVlC90 mSw7nXfXJjhsbDlqix6aaMoQ5mq6WniCyO3s28BGiKiKbeuQhEmN97BgNY4qvZ3ZxA+oM8ipbDzv OypQL+vvEilICjXzp7hJBlgb4Cd1aCebECNJrqe/AMHC4+pHwAd7aC9eMinjkl0PDhteljDSS4SH SI0sNHQr6d0Jhzp4UrvhRDvfJ9nxbh/F6dtS/msNc+vgGt8T0wmN48DxMu93EAv6wTDclbebzZFe iYRCgpUN+wPNk1rZQ6OWwU4Q2uE51AjSfHdzUotLRFgcfVYCKBHfqqt1xlPe15VS1bRsW2tteYvo a8vf1a62LKECyibR5UbX0qp5OwFpQDxVEu7qWqv9DpXrjTpTPEnCw/er6wej0h9FGgxxiUC48PKt t5PRY2pjB6y6ZEO/wrO3MUfjlx0pLCSBOOfRrNwzJ2g20gkUckYsJhph8I8mBaprd6qd03rmM+H6 sZ1QapOO1+AgxxoWxm/JtLO4v87aI/k7apNcMnb3rtdyX+nQlkDh/zy/F27S7SK+sxIXnYkiVjHU 0c1Tz3ay5xtmN9oMRWyPcehQ+AtIS/aGm5mQxSTRqgGTlNmmXdUm7uwmk0LMAJMx9IEVKD/T4G/e VkFj1wXaHBAjrtCIsk4mpe4/9OLRtRTG8931GbjC7aEGAFl49pXz+gEjSXfgR7jKMASaaHekT0Lf VmubPldiz1uvAREwZStCTrNJ14kjJew2u6c/gzrPyRT7hLC8HmeJ22Cndh+eMAluZ3QjydEftzRl 6/swDB4j2FO6r9VquZv92LAKPVJyjPzR6/grSYjVkPbydBSE2qSkJW15/+UtzZWdDqgFKIUDi3MF WV80epAX0xaeQfJSwpx6bP0Ag8srHZhkfU+taAeA2JjCKfeyErzjt4fwajeMkrb+v6rTZqxZzovX flE/bvBh7zd5Hskf/4gONrf2kiudfSC8AqaVFxEXDwg1zvtUTwiOunUBT78AehfyhdJuv/e5xY4k L6VuYh3esIUF3ovizq2tAX/P3X0pgcgynUvLg1ctVuJKtgPHFs8vbCssvzK672RmPwALLBmR5uxy fNuRI7fWrXHd70jRFTnsQk/HEyuNyTQSDly2+AfxaQBNohUiWtZnKDqfAAy4feRld2qMQyPediJb a3r38TDceZ6AZNVhrpp/JrwZHbLR1zzBbkGL8BvLerH3VpGSRsZDmTOmw2+QRYQ9IlnPbNUAWBHi IxQXruHEObmJWgW7PRh+5qxIocXp9CZqjojH/49FnYhpbKVNQqVb0gnRtdyDz/nCusx/6WsjhECw pteSfnlYktSikI9/pRx0jEc/APbMNAwm1xHQzemGr0L/EC1m3m90wvcT7RBsEZlK6juw8QmMraoW l9ywXqdDXM7Pg8z8eSMiavXwmG7BPjFM5bcsr6ys/8raseJyod+8DRNSbRVLBMC+x1YrqEZBwnGr BuQ5FCnaCcl+NV/i8bIE4GCeSX0TO0z8GE+2vEfD6a3vN50uDN/0pOuyft4JxTshOCiTaDOT9cTK rMfsE9EGPuPUUfmss7tV45kYpD6MoYo6z/+7Ry5lcWcAwffYgxPD4K9BXBurqWafRoWP2l/+FSEQ V/hR3oiEHA7U3nvfM+NZCXR9pkKoH9ELa4D41lo435K9b4GK69JWNX8VDg87AOmjGLHh7SRlddfr En/wyvAS9aWef7b7diP9yLE5TQS2kVI7SlMBnvwJaXkSYLwMn9wnfpo5JhosST1yRkqHbgTB0gP4 mE0prXfcH/Myaf1KJFwdxXeIHCOp+eEyuXUgyemHz5wpwY6xrEJrd194Ew8tdENtoTXi9cfpQURr O5m7wA6I7ZQdifuT4d1NftZYNxu4fTB6P8j39JJpO0aaf4ByNs0KpySlCG9n/Mah8hzV+zq78tTt fdhAnZpTDEqolldjTIGsvJ0AudF35IGFvmA9myx76yXqXo7DZzaX2MghZ0eBnxzdNeojGuvL658w WyEi1jjwZqUnzjhY6j1EhaoDRXID0IL6kjlImg5/YdUvU+KkaqhrwA4mvrbUVsXFuWUBiYymIT8u ZR72/bSZ2qHIj8CCBvJ86gUNhkW32fwivTDIhUbEqVMtsy0sbpE6fHF+AZqieahom+MEXUbCBFYB 8rJfKF78d9GDHzrihX6cerqy5UKsuMDSle++UYgB/1HS+6hm07PjEATky/704K6x1LxyPII2d4Nh HTO0znYLeAJITj6X1zXFBLRxz/7JK7PAgPuH5N6hrfA7ZgH+q8VHdKgdS/c40obQLdFKTuI3AAud 2NltlIMYtdAkPBXf8U6iQkucHZ7orFA6XnpsBUn9oY42x6a1mFZJgxB9igPiKvmqsveCtojdMefY 2SibinbNAXb84FGbpehLb2PHZgD4pUe+Zhtvk2qWyHnsMRbDzaiDhnwPmHdXJ1zinBCvhJn95gre EE1L5i7hlB1a7Z3Lndas2Dff2v1Ylq1f3779VnPSdWh4gm3eRwasiwpx+wQpWIMHefNZ3ZFi3j9S yAJk+gdQT5iBsYHod3H9fc/o7oaXPdU9T9bqAhPpIUwWg9k9Nqwx03nWngl85fwsez5rvKsAMtcY 94oas6UDFJ3qfcEdxSu9ZY5e4XS8K5puZm35BnSWjLL7DNR60HoLRn7Rl3otax7kXiZGyojKx3xX AZ2F/XpnBxK0FBVxDOxXN0JuvSmccBTp0SE4qniOq1hobl7+J/xN6bvWvI8KJLUFXrWgayB8quDp wD5RAYL+hh8wKN6cWMn2Pp2Nyu/qBHFO/yTdNQ3ZieLTyFMdHinetRZGalL2tiXtn7vljDM1HSq2 TD3BZSJs4IdW71hbVUzsO7WwtaXHu1KnPlyV8WuQBQ6W/b3zRy8tJoJg54+SNYGo0nQvzH58D465 ZNHUMpvGUgBhmVr8u2wn6x4vTBOqeao+PGh2zcyNYYuNlQFnrrdjUkFNd2SsManO0dLjZkjFTJ4J 65PTBo9JmOnJj5Z6m6YRVsnnHN0YX9ZkUrHLEtSlRkc+VBKPPPQl9qh4Xw2ETE0QRNwMsmcAY6m3 Q6lPZEOxwJU29Izx8JpmnfMYBgF40jgLHevQNzkBquYTF5jUjwwxPD0nYmett0Sd0Z4TlKyCa2pr 7HCbXu+31aP8EzOufHPPn9n2NVHzCgK0mMDae2a7bjzHjpTjOM7EK1SdZp8U8mflFR1LVczaABvR m6LlwFuGPaqtAgV3qwJpGsditX+6iy1qdsDdTbO6Ncv3Nz39ozjMhuN+45Sz9LIi9SFhS5U4VY7B KB3jG1IFu0VmqTHZA39pxGSwlMMPi3sljSL2gGIc1/A3UWcuVPB7v4PqetKn6j56wA5V/7URLTBW surtCev4U5MKJGKG5Nu9zBf1+afWTuOUzeptlfYO00jidK5FexQ84gt0crgbR6IUWhEawmroqPhM vRNI5CMzDVmS8Jm57mgSXK0H/itUFURaTZrbEXoTMjblseGaZOt+frsgHrbbyZN7kziPaFdm2hZh /VH1a27IrOuSEiQnj8fGgRgIOZXxymHqEGWQtRR0/vg8pBaLKg8VbC+FAato9y5wi/V0ugT6IHQo pb6K5lA+T1nfglPc34nWxTroDt5/3S+b7fi5c8A91AYX15Jd8OI3UVXuvCDZv2yoMWisyhbnqrq6 ArxW4Un7mWWwqCT6z9EK/B3+B2mbIY+IjxVwk3BHTc2kL3DV9oOc3Z/INEzhAUXCTBHssWl+01ZZ oCkU7BQKf4ikm3RfoEr5VTO9WhwrLGhsH3nkr/chCRd9xdQHWTIqLKq6AgxHLA3Ljm6BcxZCSLyr tJFd8UqA71VO1VMpCQ9co7imT14HxQ9UvcDORi9WKuFeAjCAMW2ZTzoSuz4LDfwdcD9LSnRL2YiX VLV72Vx4eY/I1/CyQYu9lIF++jrljWkPyAYwWoJc9cheOagsxtpd2Vbyy9Re9RHw93ovsKMV5+W8 DtOy/MbMkBSvC3BeyZWdwFTM2s/fi6Dr8yfOeaJPlIslxU/WuMGyl85DAD3SW2bcLF+STvPbhAPN ZWAnU1jFPqCIYPcRlTYeTpa7OFz3VjcZ2K5s6qBzMDZhaqaYr/Tz3TL4m4vQDbCg8EQoCCASgjSL DP6OZrdtV/hUUtWk0fMhxXKfJdPavEFpNZunrOh61zReRo8pq/f8Yh3J06c6UhSKr6WR2gTgmczo V5MVXlDvDyQwl8XjZWQNZH6McAPu4x+gAG9JhdljE9kZDmDdeWDKu8K13OCT2hgMUsbIb5OFV5lq SUUpRsu7OX6QzVe5ljg6bCWaE6PCEt2nuC39ilO+DYbe/Pb/YE+/3xqUcNTNSqeWqY/2FU6KHNOI nV4Aa7LL2pEAb9Eg7vzHIO+83JG3CdIg3L8uS0u4C1iYAfj2nUFi9liiuHGNth741sk4N+u3BVLp cN74fqTs0d6Z522ewbQeUR5nRf6IUpusjxJ4BR/8FLYp+oRG7S4LAXqqhX/hdn3gYuVSfy4AUSHr AyVYX+HmvwTR0GjLtJO1I4dAxGxapz4maqia8GQbci7XniTgZvNiS+Kv6lRfopS3nfvl0dAZI+Yq Pb2Eu/4YImPUzzJPqC9bByJwLjoGJSqI5EaKjC7gEkqQlQHqQDeki6pIMF9k4B5XQQl5oLaE9lWl iH1eTpe8xbAC4SIxqceGwVuGF1RVVfwIkO56XhuY4lsClB4WDJRL5FZeWAogtAeatzJOexW1+VNp ESAknDB0K5AwIwCzWO8KaDyfcwvWkBUNrb8PDEhpj7HsVKgDgDwhB1etg4ZVVjM68EOSS/RMrWhW WyZD4pPwSDGDRmz3+lZYYp3NdlYfameAgA3HH6zXhdoxSuOzotOfNUYo5S37Hvo4Y++1J+2nSOxs 2gtu9EozusMtsVLu7jZYMBKmqwjIim0nuGe59PVkW4TcoHl/6iSWbE+yvTTqtRBu/xFlQN1Iju4n JaegefML4jqwM+Ecov6VU/EYqExp/swWPC8qThzaVt/5q1g7skIc6O/061HP1uU9mL7gl9fN0QMN pnwz6YDYJnP36w7D/5f13DAiQ7C2mcjTdiVOhtfgNtTDA5MAKBodIGz5zXZgwYaBwBJJRQ1cvqVi MjwErKt/3/U5/kQ8rzjQQeq7J3ssX1Nky+P6JWEQ/HlNtZDxKFD5KTns7n+ovEUKqyseJO24qbfZ sdJl/oXftTHG3I7Qqw4nlMLszeq2J4KGux9k1jzKDOar+qmEpR77NjgSTx2Ud5QjP6OjAjdS0dK2 Kt4HzKajY2r62FQqwLFnWz5M5dXAYfm2HZVsmV10JL39RsFKFofHH5dFPvbPhMhYAvyBaytYQ/59 2n1+oCG4Xgw74L2Yv+Yy/NFavTYZDsVlxGhnVIPCE+kGLD8m+zL0TaXtK5XOWfeEYiAZw77F3Zb8 d9HYYRKEGxHmNHuko/FYrnmGpwfl7qX7bEpkAJOrQDa5lTjyKDg6W58d6BUfMI7lBOqGblUy2B69 44th80thR5xfYL+qj/qtIjEQRb6oI4A1b4De5BvZSyxOsgCWfmcD+hEbGaQ8c100NkALjzxY3VE4 xX2sCOIZNpes747/xq/FSgNas6YhmaYpCCNvxFOFuZyQAWRRqn/W32hrg+50CE4kHz2N1QZpQDt7 AIdwAnt7nhf9EFUwvzQQbcaGA5i9+OZMWX1fSbM+TfmggFKMLZleugCack5qSQhsvAj9ItOc3joE /CGHE4l/pfTWtLvT27+pwLJaLk7VnxNPGysYS8k2443bvIj44/uJJETgkRcGAZfXBarJux0qJNum PNL/jMyzgmHV4ZrhiTjGDvHuVQoZDFhT+dbl4UOFs2u3OZMMCjzIp8IbNU1FN1RZepfnyz9b/Xo8 65X4wvFBbOIm38EVOeROS8DhqdnSkOQFyHuzLJE6e1Q7i+807FdxaM/QBeUCSZ3+QqO/oO8lp1BI l372/vfrlFyGW6h6EKF9LJaAIpGjU8uJpDl0zqsAJVeJsGiEbmqPoSfDCnDV/ubNdyAW5Y0nPlY6 Ixc9a/x0AfGS+NoyPwEIs3zPArevfTTFxBx/G/dXGpTZ/JoWAZhXrwlF6MaWjkfJXTi3sMR1b6A0 24TgYSofawStrJWTe6PqG7Je1X09BeN0RwltNOeOCjEdiko9cMqxRvdssPNtPHACvE8fsfJhzU5t RzojhSHQsatlFZQ0XpBUPwLxbg6nFgz0nJIjA3Aiv6yjfRFBAbJED3e49FaZoCi/E3xel6nYYWsw AbCkd1j0u4OaG+PxaEQlxOUXWHvnvjxiV9LiCmnFEWfHnQvUEoi1AIVWC8NIyMXXCapzBBb1KIwq vYIDqwU1ljZgGZ0KvG9pr1HdB7BBm8zvcjfi0cKHvdBdL4EIktAQPZyel5fZe9jO67tNmsQMCi6x ZPO61n8dHbRFSbtmFkbNcm+GHjvzhAnYnoqpYCQIIH03389hcOz51bFb2sWSScMm+abt+pKOwgTj NLPWeNPuQQbAbdY66UnMbm01h7oGMv0rqw+VZ3aUf1KkJtH7ec0SCKnGE0HWjLwiKDDV1l1q3RW5 KtaLFIrLIDQUEBr/z84R4cZb/CridLnlq1y4IHRLn+uOLo8kMOFKah0wypCBznwce0PBILrImQl+ i/70t2XsTWsAZYKUtRPfj+qJ/Jz05ly7FOgqGDbmb1zF04QQEKKGLj16RIjZJS7EuUknReM4U1R3 cBYdV4U7V9+jK3JKMOGchnzgU0skNaxY5G0XrdR1x/luHLxJhmDxjazpBbaXFjfVwUtFavdgviJh CMWndo6lU/i6/mTExKCdP5hZ2cYXHJ1/39hY1LpWawYEkpvBlOiCauFMea85wv/Xrfq2dkQyNjac VrvQHyMm1ZFyqp2UZLu6J6aDEkeLNN0tMY2+A9AndDetKMQNzxXJ7QiCsgMXpz4MIiGQB69bYtC9 muiyCPLe4qW0T+hptBlxmCwN6RMvDFyHszppMEDGcTTpDBz486h1mZEwBqRWgeRAT/jdwrA2FDMc bPlEW/oyHg4UVueX0IEKRCMq2ikeX6DaC86bbYICX/Jbq6PMyH5MONkAfiRFkvJJJmGbKu/tzT9V fPF+F33bOZUvdmUZoTFcPxDnJIHybNsSyaJXAtsS6ipzuqmxilssdKe7FvRBUC8m+KPJPFffWBjc WcMcRvyOMPl8nfREfUk4ppg/U4P+4bkvA0DebS54pAA5oebK44vIx7f0rFz/nmc7L+4J3990Toe9 iYTfxihECpab8G0tftQFR5bRkcipoX0nYwhCK+ShV6QiFlTasRTJsiuLYDX00Opw+oJNmIOq31SM clVuJ9WT6zgzLNSnjhg7r1pUO/ROE9M8zec9+GhcTEMbiKTEl1MrvwcHAb2GM5Oof7CMa7bZaTgi Mla/r+wgO4az9k7tisE2nYB9AXKPamKoB3gOS5MX7HhXlFl5q5WLllQYGkRCEUBisBFikG87Akqn oXh2vKamrv1nnxWkLEbtPkeU82KPU5lpYHwkjwSzXa/aaqjAOsaG7m8OFp0DjT1nfMw2xS8oeRqT KuTrEZ9KKMcv92HYRpO+AY2Myhhg3xTXngkvusqQkbXHms2+ZnrqNQZhHCnjiFXp8TaJt05TqXQz m8azVa+EAY0iDdf6qpRX/5dm3Ft7HzCj814+pqlA0MMXET5SD6YGYUIxRJabkbbsopPULhwV597x ouxRY0f74WUHRXhezjDkqMQTEj5qqGT1wmWcSvTkzGe4eaHAf9GLA/m+60WUiixLqRyaJQVJ9PxB eX6iTHsvavp7Ur8LrWv/EOk14PdYh3Lh/62TzqaSjnF8jC8wYUgM5vlM5hl2DBLlzps6AJT327yX 0DutuynuZYYot2DRFzK1ZzAkOS7qFEt6eRCjIZqSed9cbXbGve4LKu2t5bbTKn+HAVwek45FFnug HupFPoZuspncnlsvBtnhEuHWpviUKZNdxjYxCFWGC9ehytQ56O58AE4lGhit7WRFaPtNFKRvY9sW GTMnF7j4zyzgjH7k800ORzaorICJfQqNgUKzcF9zjFDjJ4DybBDOiE0LPJ8fLuL/d0BdD+UPdycJ RwV7HDDC7fFMYUGfC6RiF1sWczVmUEDWm2aQhfJ3RmjDMkCNZWlYKLJsemYeSw2f40WPPuT9Y1dI adsHQOBkM/W/9ZJBFFp0Vw2xFGczHguu6aAE2yX5k78V7nsMW71xOZFZ4Cb8R6nahNRqjrKK/vNL MXmQw64iHNcdowrUjSwpjyEQP2LpInn6NESlj0Ryxb22/pfdM6cdZ0b+bKd1uvYvprHC0u/mIg1B QY468d+PzwWHsSLKpe+t2nMFHo08V2UprhL0XItMtI+XIRnrlZcCOGRfxJcv+MT5pjMe5QTsZEkg tZnb2VdD1h2gNyBpPvKWSzy/nKtGRcNVY/UDwLz+p6S4SVPvsM+pi5RaVkmaWK5iUK8GrnCyu4HZ pXyhVetR1cTLUuyAu4a/GoijB2iF0aDHj0Hs4+4q8ihTeRi7i5pfBecCj76pmHULeKF4DSPGYoqB n5cEXFBoEiPULoAxet8UMalRUyc35As1pFR6m31V3K8IvjuvSqjk3vI6E+sf7OZ26ePWqr/2DH37 28qFQaIAOJg7L2W8GSnScxigbiO4FC0AgwLVZ0dYVRXcPIXiEEscewkwRTwgd2ny+jvyWfbeJ8un AiszR0g4ualmQN3M+GJ6U5IGlIbVzcQ3MoXwtA79Tgkz2GIAYVkSsPVurNgS27fnw7bVIDDtEmeH tz2ijpacJf6eIc7DuIwyRetPZUIjLrXOo2FRTm0IueiXIMB6/qwT7X5kfeDK/eNLe8aCeDu2+RVP 610dQKmznv4WzrmX9Bsx7faur+gUAYtuKtz1GahhWIdR2KBSbk6wv5kYifFUyPzsaHV9/OMUrBu7 XT+8Uj4cDXBfgrXzxAcf7d+Ew5gVbSnXA9UFwOtRm2Zb0TEWaNR0bClPIqvXzBWEWsqdYKQI2o2g sghie6oYQ1X8k+/QdElVgmAxb8/3eAtSvu4b0XltOGz40et8ofuvQJrMKlNPjmwBSziwLmgcby8M 9c2gBK2N3AcsV4C8A1pMSur/m6IS0GFd5QHXiuT61lr5q3BNCa21I6w9GwkZrpX27nkUXdlbghoC pvgKXMbDHQDFeYLORaTRpfrt4+nb8AA03V9HYiXuHJI7BAADWYUUF6ZDDzCls8uddz6upQGA/iR1 DHE+vHnb3amGx/SEngZez/60NokhxCL40RFOWBbOlBai4sUoZO1R9Z14e/3h5m7IdrfxQArF6oYu NwnbEkbOp4BS8B2s4LC45xqxdqklxwTsHJHlEuGkMEP09E1RBSo2dRm36takiq69045JQO2jlD/D ZL4IczKtrXydoMvO/p12KIR34FbGrFWMsU2PKRmQ1xhdYwQO45Ih2SF3YS2Pv6eqpUK/eKtr4o05 Cs6KkCuxqvlsPsxquXsM0uRhOB+aqxZV9InJNAkXnoc49YDtOooVJx2kjq5T47MKA3LfGTPFuVVl HJ0TnhE2xY075qP4sVoT9X18w5Y22BSq0Md4w+z7jXUG2w371uvuNK31tNMa69M2kSg+89acKdlz C2E/OAQ2pa3x26n/yK2zKJxTW9MToHCWsDv386tkn72QUmZ+E3Hu2LpFAzHGsBWCwkNCfU8rxXpR piXukjtkIVzhLHBlGbc4MlRexvFwP1chN7s34Czob+wmYZeCsdlyRZEkN9kNcQoAP4i+yhuyT/yc V/lC4tulnqfnoA7ZjTuotzO2kGUjIL37reUgA+NIXdusy6xNcV0RbZAR3yXmBpxrWshf2JMi0259 +nYjIIbYQEOTnXnZ4J0SMy0+/XWw69NRbTT04wa0U+qZ3pfVO8bx9KMHvgqug7wWEqyHIxeilslJ bmFK7NyDhjX2m/py1dnrzuDCSh9f71flOdcgtemyJXDsPVCTHgRAEPQ7v8VCqIpik5FL7Sm18I8k 2ydYUEbFTwLnHY8sIIXmd4FcQ9R3B+i283c08bEqggHpvpj2aULyzgkgSbxLi99oKLkH8lb1+waA XEiV63Th/rqHB7/nIDpu/lSYwgu861PoTFlexiE5ut++6ZdfN7C6o5AoR3bxNrio1nrQDsE/XoRA E+bvxUcoOonUlL6QfyMdetYFN8zjsEg3IciBGN84QfS6P92wGuQCB+rT07n3dbW5D5VgXgle2K8Q ELZ4RSg8kZCtySXh7GMShwOQOJN8jLjvRE+v/oZz9GVLL6teFijtDtyS/v7jac8dGMg87qDwyieE Os/6Iz92z9ktym3nz5sPR9N8ZsHF9AAJUC7iq0Y2qMUsYm1H5g4TWK/t9+D5q3Xj2GESKfziI84d fGJLSSW/ISzuIOPtyEDb4i2erVhtKO1SRIusRTQJzikuyJGiiLjlhwz3tvcWj9hWi5t//FMT5j9P gey4tkbJohzRWnYXNcc5Uk/ONivVrcsE022M5gZqPMxGgca8W0LXMLY06xk/EylY2lEFahBT9m4S 3B8YQa1wNIQHlSS5qDULnqNHiexOxKCI+kHCl0xvp0uW8eTdo4Iyk1LMO8npQzW9RzD74bYhi4mU 1xSwJ9a5m6gCaUJe4ngNElHBsw6IxJ2jXpXMBizLQEE9YIo0BdhTagO83asIdDh9/fcbh9G91iZV x77q0oBu9BYhrqs9EqvR/zWE2DPAjlLR0HbO+n6RRLOLmB8LB2fvsMOYMJU0l4vCO4uh3cF6uGYp 5oGgkoLro9AH57DiF4+6jjadIUMivBDp+Co7lLNulhmU4nmeCjBti0R0HwMvSzyF4L3wqj3rAGf0 dncmW3iN0OltcyRFMQo+XxORKO+bSDOZAVzAK8ZqVsh+UfgcjAboJ6hUC77/oNP8howK5F/i7G36 Sxgm5dwrok18WxFg1VH8ji0GrXzLpwMA7CCdCr0m7ZyHXwyVZ+kXXz4Ts0U8mQ4nAAu79BiMxVTl cFFAYTEv5tj0rCGck93XP7A2U6xEMJsdAvjtoAXN6jXjOgPF3StOAcXTsDNLI+QDRSwj/NqxbMih ZIVnuCmoOIktmVsfT9qdUHKGNX+E649k/TO/IqsG12kFzCelfNeBk6vq3Aqm6ZSNV6bR786/OxSC p5XkcpFsT5Jorf/UoJi+j3SEpypQFUhUfpFsWkWEQWWmaa1XC6D6+jzn5BmSI+D+lx0WNp7+oLkK bpOA58hLqbR9vpJ3gDqFqut2S99yS94rmfgwbYF92qnOHOQep4h1TEjgSSvnh0ApZLQjXp7uzxYu GjoW9ndJi/ppKmsxLfUItG4ctUWbYKVTej8/mpN/1rnvciFlwVjcWFP6J+l9UqoqzcwIL4iwAukj m5lchbhgF0FBAjq1zTidZ2U2GaLiEQEVmquz3P0XqGgXpiNf4dA8Nk/L7TZrOuJ2nM6mqzx7cEvP KRHLWOJkCZu2xKPSDwHDgaK91Sz9pzDB5ZviO8U+1m5Q/Xj4mKI7YA9Y0fH6eRiri5smiLEkCfD7 28u+uGtHZjAic26PQ0c53PN0IHdeDn7SsrUhWMbjP8u5sPxcBdUmTQvB+wb/Ya0KCoOgK1gKL2cY +TBRFDt9ACl2noFeudVV6EBk2AUj4otaRIPnGbi3cCrVhRF75VV69bpyzKmCC74kyvUXflIX+m85 ouJxK8iayCLSe5eROn+0kDJpmkTzMIl1vrJ6jnyIxcg1iQzul380xSWcC1z8zEOFc5K9vN6/6GMU rcKSIazZe9HmXX9S+YTdZ35AEaAX/RJ7RR3lOhtjIY8jyQhzPdUoghwmqOGyyWEgOMJMnaPt+J2C g9D9i4zwdd/xoOBq08FoXbG+ilCxYpCuHhpTjUw8hFw8eetqZsxy7CIkO3cUnROzWX6jJeckJKNZ IkekzPEUUeLMnNCwKsvY0TBg0g830zSTcFkD7J8zNBNQNgFi2oTH0iq4ZvSFpW/xTVJMQGu3ggZ1 hlGYNUTZiwf8q7m+OtikTnL/RuEn1OsBCoKf74TxHyDFcaWYyNNN9FWhL+QIphWi5gKt7/XtmXQE nOdyTqzNnFvjhnqlu6Xi6GOc4MqqRY6Hl9XBXpn5LkEvOf+cFikgnFvVPlU7sLjG2wbY+IlF41MQ sucGJODsmiRJNf7BX1wo8gJCeTmKbMuj9BFhw4IzcYtYZtUWZChBVW5PF4s6z0IK4qeWZUk6yjRD YcDxcvc2COnsalAVk6wYlVEudxuVusigUYIOTNGybC3o+7HRXY9vEtMD0ZH3wQlA6MoxoNwHDynl RJaiK5cVjj/8ruw8LXPOpqm4rZJ0Jk31zCKr3Ib9VRPGKkW0h0Ms17xFlF3tITEcAE44D2E31urU axXMqEWxT/HH9/Ba+FI1lOQDO8WlTXG/TOkPwKM7AIP6y2T0ZrN+43ckHp60NsfUIGHMOccBjUeO hWXcHl18KB00D313tCTaXwa8zZ//gwFqoN/0EPZWDa/k70q0KUzcsX7lbQPlzC2M9MAbLcL2o6ZV DYS1pV0geiTdicnQFohArY0zC702G839afiK3wlV3D3ydl367Yx+ssGDptp8RP/T+VopwRAs1O/Q LvVF9+T6JIA3zS6e0XPjBri4TlyXarDtr9q6NuiGyK5uXCMb+fHXRwaZ8Fvi7ALKET/XvhCvtiB+ tCEbf/Bogxl83Cih0Lv5nXuBCd9yu/BdsmkI0rvXp4CHUbDbCz0mtL65Vkeo3C2u3CGaORsO2+IS xmPPiTTyyArgns9C2OXPrUQF08EHYflVF2C7L0h5QBQ7zlWABlIE3FNge+0iJvurwcwCyUuurRvt xxaSdrK+rTsT0aWkGrhV9DPwYMv0GfhtE/cWTTtJHkYCz7ntzKqThRPvnHAT8HNxqrrJhdgwgiAc GmPuBoBybVi5TjooZNN1GgqU6gD4yuiUnwsjYkwNcyX0EpZFSS91ttvJ40Q9wHcoCkh5g+W72YuU WdIV1vRoJmzhcJmmD3/0abZbJg0m/GI+U9Ld0MuXQmsxkuZvVZcGm9YvilIkw/tVbBxHQzLFuuHe y83fCBHUrhX+5aVp0oQ/xKzv7SAgYjUUvVK54xCM9+f0I62rLzR0noXTXm8LhXK8g/AdIjo8dVxF LNNUsSzsv7e6C2r+u7LiO5mg8366ZeIQqfY30TZ9Porubd8h+fZBm+SrKf+k3OF5bLvzw2C9Xh1b DN1XgHAZobO5ESsWhdZfGwwFSKwNCb1SEpy1Xu61+4mDMtw9Nor3xMjVRQcFJDKfOfv3HEFrb8GG JtnOxre0swLsZ9a77m62ySn1w2Fc0NHL9BK1nL/g9UUBBfDj34PeEVLBor3RoPiOQtnciAVLAOjz aOC1Ke7Ef/8EC8Nxxje1WeXDIo1J8voygjyTpPm6HRH3sGm9Ua/w1B6ssTwrR2t6c+XIhbZx9D59 ZhX0MpGvxVDdpZGhn/D6qX2rgURptZQ6yPq9smFwarzpc26kG3ZJ1dA5rwzHlYex1Aq+I3/TOCqQ oSbwSffhhTGfWVL4d6alrt6lWnkgSz6SmYf0GoFLf1ArpaYsT1meT3Wlj8xN/qdsChbAoVNH5czw ipj4BVzziC04ELaLJCdbTGfaJ5g05+t+Obod01qF/hJ2Vh4xosD74zEBsom8RK+0rnYI79rqQljm 8jMrB/KiCGOHa6m/XvNEjSMDvYeRSLnKUNMvy4TJ1Heamzs174XWlP1uOyJr6U2srfB5zDaF01hT VU0gQXIRwtamaUPzlcwL50oK9DbaNq65g4vkvwTc0UA08GUGCqNXyqNvLHmg9KE+4dw5USswRN1x EBzJgKhdyoJuiWi39pZFtLIeWiB1vbbG9oA2TQQr99lJL/DwHrTV+aT9/ZzBSVA6yan0o8oVZnPI bDIxzxOp2Al1aKZDj2EBFk0e7qj4S4cb/gNOWSuUJD9p9eRe2P1LsYbuj5OowBsoo3//BV9mvd3p 4BgOuNhgDhkzuv7oFD/UmtZhnwsYPL6OLbG8gAqNR87UbEydaYjd0t1Sp0sX0aB/h5SlX9Ar/Cxc MJUQwJInMJ0rCFkFDRmzIKLtOIWYzEuGcdhIq9e/HNKBM5LpRal53roPGYgOLxMDYDkc+kQzI5FQ D9tLQBAPNFRBrphY5Sj6ChWnhc8aeDMR61NTbrONci65Noc6a2f5mZKkOd99g/IjMeSfeJCCytpG 7+2pPqYlXuej/U4GyeLDZtlFiEXXEMAjynY3lPmLXPmDERoh6Srs140pCLIaCPFdLkgK08CLjXU9 kWpOrKtO15UtWJ3RegGp9xNnitXspY9AqJJU6EGf7L41yVl8u5eIWe2qdUMU4RyMWqM3HIV/8GW/ +ZHrbUyTxmuaZEMYNgJNLfT66CtYXJRsY80BwvJINvyTU1K6cmudreU7xbE6+ywGT3Zq2uYq6KqK ZWAFwT3JRdYihXyb+9EMRy2DIBsWdHwvyaFb25OdB+QGj0XW75/3rNr+7pllg6ujkbTHt57/9SqZ SRJLvJ1QPtGT1F/RGoXfwpgd9rgsxqGOv9oEbM0gMiJA3QvI6IimF6X93Usgz9cqyQKQ4JfGue8L RUkM+HE5iewMYx1RPhkj5LRdP/oXccgatI4POJsnfvTY052IQm6ebgEK76HvyTO0YqFInlHYd/cj 7Wd4XMLkAjjWbfTravvDhJAQe35wvrF/Ltv4/ECS/vkDjCiRfCNRoW8sdU9Kcsk9j8Urgncb6oSn IA5Rei8sL6lCK9J5RlcswwhMs2LP+VcJQgnzimudafrauXRTn7h/4odY5A0Izo7ruO+PEMh/kjzk aDd6P5kINr1WOb0ZxGf8M5o/vmJEmrDPHff1qEWjudqaAsX8xBbLsnj7/Vce0oFM27w8T6W5wda5 Uj8kOOf5+6cMqnsMsOE2FNvmmmMQqV+UbWi0mTfoY47VmssCIWRA2GTOBdXnn08ivBrkMhwrK/bw j/mwxPFwrYZdfahfSeyHSYL0IkVFoL42Gew+lI8hajz20O+JykDtaXGuYEzDBO07HBWJVj4qywty WNKt6OFKBrk+QIeO/iY/iELeOPXvALgvrzK46fEhhFBrRgedPMMo7cX3RUweYvTYYWt8QErVaz1b YHd4SzH96qA+/vcAShkWAGdObyCMT5bdYGeDKIKqbdlZanUCWtJ9m7DuaGMhl/m49yOiyKQCeNnq DRS0UEH3mhpmKJUs5mYw5Ti8/RpPCf8NRGYD4ArFqdNafsJ4st5KW9SrpQDXzVtGi/ukdHATOLyk bGdzPU+aPCwXmELjUxOeiSAIZWRhsoI3Bhht670gtQTiFk+mxuBxfo1+VD/69WxKUpi7NQYzdbpj +SW87PdzXhL278diGJnbPivjaiG72mcKf/8cFgK4Z2ER7WTe/HyGnND/3vMTeP6r0SJ4KhusbArx 4HsQtxS4KKEHMTNr5AqRU57BxbLZyohF97aUfyfSOMcoMh1oo+uMf47DyBZpoZCz3Vyo1sH+AYH+ CqmEXlMT5JjHdyJ1jrkUgmgraZ6tRxY2Cjy1SoDGVwNK3BaSkTsDAzixOrqZ3qjY6F5z/FSCPhRu eRJ1cJ4rSxbXNDE6/9UXbIi8w4ayXbSZ9mSWT+Zkny9g3SbZuG1hhcqsbpHJyMc1g9HRdkbfMtYj Ce0nO4V2R98e60KBiP79DXREuxmCMYrC2Z+NLzWaAFoIvbtpsMa0wgjpgU91z9Ea9u5bUlGzGoom INTHJDMQVbjyYYgl70aWiOIy92yWFdkNVDwcI590eTUxllEtqpGb/kjJ4kRoZu6nHzBDhNeIz3AX 5c1liG0VWl7+vtXStNnAGnhK0w83J5P/iz+7zyF6PXYlvCGMEpMrTkVHFcsZgEiI7RUvL95zyzYb kMfQB4HRDfU1Ki98LfdDX4aHxu3ytB3xkoj4Tfe6EZomsY/vAnMMoEJyIQTYXLxykN753uKeUtMA 6icJzSnsRmSqmSOkY8z3L2YZcSDhOI1UeCd481Dh5Cux/qNcWWW1nRiR7Z7OcAkQBnD5DneWa+2C 5y7RVjWTuF5ICG/iPRgSpVuu2lIyVEGJpOKe+HJmmFoOBV1wxKRItNIUDbcnE3sQL/vrjfYWfZ3a 0o5qffEIhvunKnQ95NGXO40wFuXj1mnNCC2DMi8gV2R/xSn3vSXGxDPYVfM69vDTYbrkIrf8M7fF XqhqOZQRmZ+nFqcR9kIz0Yw1rWPliYfMyvnmxn2r7F7yzKjmaXma1SoYxw4E3WWEJAdByh69Jnph /4xfq+NBO1LUXgGDMo3n4htdcpTaH5Xt+Zsp3+hoHu9LPQAI+eLZgRmmPehuEuuCrpeg2tWDr3B3 Y1mk74Lvq9gIr7HSkIDZwr+UHwTiba8Db6HLV8KBsOR+afRvo4eCjZpC4CSG218nCQ8o8GztAP5l fZyqFSUCgyIyETZWGGQFhZQRZCo3puBXPrUkkxqBCnsAAVi9KD8LEHXuREb6AUX2T+zKacAAavL0 wpvBhyLcM3lsqWZ2g8DyDjbrMiqpO3FkVvJ+X9K7pFF2d4WDlUefP8Dyc5CZv6yz2s2WIyHMkL8w vRr62JX53ynYVYd2z2eiX9T6TxwIkPCyu2iLepF/QIKOpDAmUamh0YOLFKcLLlOYmSNXqGinlsWa 1Bm6nuu3jSHt/Sxmb32WM4YyvCmE30N/wuBZ/OswvWS5a3lCdoNMbC+d3Oky/snkZFms0MWdbTeF RddKs7/tbLYcgbtRyQJFZi4EZj5MmhZ2iVjvThwxdxRIrq7jUp7lFD6tS6krt6DqazvxELiXadZT NC5kOJJ9ErjZTcV6hoyANZb0WBx6LHbR2ZgxxOkcedH7DTzA8f2dCVwZVWlnrAXuKS5BjTe8RBrL G1jPAw/GtIILyY57KdFw24cpK6OG35xI8KfqtNGqFSqmSswxzSQmf84cOCrgIXlm3D9ZoCFKA69S eO998PM/dXqp1sk/ECqsaSN0IgaShVRII2/t/R9aqG/E2eayHrFvESZqWYmCBCu2PNLaZHy0WlGY /LWK7vusAphHgwxLh93S4psgDWyv7A1dhxii0HAbIvSo28RT1yCHxJHvH4jDuuMjEF3NL3Cvc7tq D8Me0fX+99xu1gN/djT4j8vMBIXX0UtmBZuLW7Q8rZYjxWDHEepie8dT2YN2EsUAF7cSFW18lVP+ ubtC04w+9IKN7njywZeEwhACtrZkxtnl8/LyHLdgu9HDv/jq1KFQrkvqbNt19UZOzVP0RYXwi3k3 HkPSxZ7m+6WwUK44sezKtdTuHMPQrfRy8VBA9kdc2z+dI2c3FDc0/B82Mnd5ZV/WOZ9rz6mfECFZ ZMTjWoVCODKQh0QEosKKF+LCyQ0bxpq107lHHO7Pq+F+dTfHdFOu4XGLe5inV21AqyPgYbqmlQFx adXbCnXfOBEokbmafWu7fF6tFCvndt+/kqkHqE9V5xspRjvrZ8pf5nrRoIkPP1b0 `protect end_protected

mit

Nic30/hwtHdlParsers

hwtHdlParsers/tests/vhdlCodesign/vhdl/interfaceArraySample.vhd

1

504

library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; ENTITY InterfaceArraySample IS GENERIC( DATA_WIDTH : INTEGER := 8 ); PORT(a_data : IN STD_LOGIC_VECTOR(DATA_WIDTH * 3 - 1 DOWNTO 0); a_vld : IN STD_LOGIC_VECTOR(2 DOWNTO 0); b_data : OUT STD_LOGIC_VECTOR(DATA_WIDTH * 3 - 1 DOWNTO 0); b_vld : OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ); END InterfaceArraySample; ARCHITECTURE rtl OF InterfaceArraySample IS BEGIN b_data <= a_data; b_vld <= a_vld; END ARCHITECTURE rtl;

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/blk_mem_gen_1/blk_mem_gen_v8_2/hdl/blk_mem_gen_v8_2_pkg.vhd

11

123927

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block Ccre/mo4iYR6ZSgOg1gk/7yavHm/Tab3ZkZcYFm6mHsK2rs8opjY2zm8CLFAxyKzM+XWqIQXr/Fc dQ62SDu8pQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block WyYd7hG/1lw77JWK+H7uaCTBuAtJ0TBNBmyeEHZzKg+QBt3Cr/4H8z2MUPj6pZRjBIIMcBdDyWAg kFxba6x1wM6D0583UJ6utRg76JBTYn3hze0vwLk8TflbT8BIsLMY/07o7U9RQLj+Czrd4nu/GcB9 pJ+rlEp3a0iAZrf+WXM= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block RfuO8rrKLN6nyJNR3MR3coxhKut1qVIAuEdjKuEt9/BtiGJZN+vho3sGPhnXGPXiGhQsomdebq5G ubnDKN4NlrU/K/1OyNtvkXiCQ0yq0PS2JdWUylqpjwB9ynBw5A57ADeaCo/udDuX1y5wHWGkhROQ fsJZ53VGKb1Op1Lb3r9BDB8N5YilEmUvvtSyFbdB+7psIBAUYyMVMn5URNhxA4cyzgpgQhfcULcK sD4UNIk4VWttF0vTTR6gUts3jmAIHyHf3d6WxdEAShshX6o4OKR2UxT4uLzQata959gMnHWV1u8z szCVxPR8xQQ0v799z81NPg3yNd9QbIa33NfW3w== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block vxmmKikWOvh/MtjVuTOdXUEizG5j31xAKxSiM9Xx8aixITyV/shFEvsvoImS9EU54TgPNBdxM8IR npEUXOOcVxO9WfGzwhZNQ/ZK0jBxGyrb28doc6RBBBRFSLq6zp6eRXW4db+xriK9oYHqwZlnFh+p +PrqAo/I9KP6sZv1oHU= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kSh8dathlvrCSfMnDfy+H9hBRQczNUVPEe4uv9JEwCAa3/2S1CyBPGf5gqqXuNXvqHZolzJIX/7w pSnd9F19rFWLAuVfzyaIPlTZrAsax9Nea4XwtEczdmi61CkouLWxlFuVwoM1bzkNI5RFMcI3c+mY VVE9udu6in+oPKf4Zn+ElbHY3V+cc76JILBdVqpMZqtx0VT2JvmWZLAz3e78avyNNr3Xow0ywIGy OdX3dLU09soUoUFPZH3IK98LoelBpKnR1+HxTI22lPYimCTRIAx2buuEryXwBu5wfWWSCn3EPtF5 HiIi9rQ4DoAlkBvN4LqTfIdUNmzaJr1QCruccg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 90000) `protect data_block lvJgp9F4NgHfQyd0s9WfMj2NKmMmK+cVw75XRIANBEFXjAglUPymuokPQnOMfyJFPf8qKWlwo3Qe XrJHuaeX6LKfO/NZ4vjdMRky3qPb7KS1ZDXX1CP1z1s51WQ9aTQO6BiBoNW6ouNJWTZmvWcHc2Ln YVf6M5x28gNptT5WNP+UIgu92VricFgiOBR1gPIL7FV+IOzcJznZbjyvYSvlGJdvulnhubW2D3JW KH6ybsV2LnM8zlsz7L/FyejM4DfPUIqfzrVM08P0bR3I/cxLPH/mVg3BsSIMreRHxSyPg5oJgT7D cAJ41+YIDsrJkB5vf/CYBXpOcT06iQorhXtVQLq4DPxY3lzIXuYlbAqYKxPLcRzPrr0e2IB0CoQJ MDZdgW2WWv7T5W+8mJ8+hwnyhFhP9sv9oMmGA/gM9vaCyFFxsyh0ybR63XJXfPaR35uhG3lSunFE oaxRIYv6LaEaduqlH3ZgH2OHX9IkqqTK3tweKgRuAfXLoGkE/6+tYPmB5LuBmSif1yu6bzDGIATx rauJ16iPQRnnBIMEReZK8gv/30XfdrH9NmTDag9LOnv9SCeZv8slp6k1WjfEgPI4gQU6AiCI2TxT AcwN8eSlKJ6i98Rw2jb8N16ORwBUpupPRejyRA21l6dL14kBHeZODL0LuAcIalmoMdd2bw2YRzMP R+kO91ZduRRzsBM0mnr11LFV/OezvYwU3prAH0gWn95fyGniKpD68fYmccEtwa751Tce455rDm+l kexsscg5DWc4PRhHqYCHk4j61IISlAqaYbn+WU5gaGNFp7O8UcY+n4AUAQbemP8fT7swYLfGxjQ3 z1+SUbUzhrq2vGFr9yRKAIbW2YblXIshzH5T5ezD8kQu8/qP5FKtwRQ9PkYTv1DKVC4amA8/9NB2 gq8180MPsmlVTYaIvCso+6Ohy39QEZhX5f3WXf9pqnMDxipiq0DVnoWHET1wDzF0Rucv9T2wnf8U 2/ubcR/Cv8DE6gw38amZ4XlnaUux5M3T2ljijEPBWN1TFf1ofwQkRafL797wlcpsKVB/6twM1021 Tvi9zxbYU0jnqqeIjZnYCZB2+MpPO+CSkSSW7IzbF0Mx7mXmO8ytmUe36dFEMa3c1ehkk/V0a0OA BCp7bxRJoRiyzLi4z4cSvXPPjxp5aYGl/RG4Tf8XDj8R7BiwBl6TYf3uOHUrKUns2QTV+Tx2aRtn okV0HBSuheoJNBt4aKG7PUfmJ799ESS/o48TBZ7rcxWGj1Ln2oII3pBl0AQ5+zD4lzbM0kktTg/f c6Fhus0fkV0cdE2B+6awb8jenB2oo9At0esjmrCvn9ixhYQOItm2Mb9/t7MsDqThbhUx/E+9yXoz Iy3BuZyzVCITVuN+4k3d8BzMqIbvAp72Hqbbxcq/Oe86UYGbaALGa9UH2pMawdeidGIeeK6csm3y +KAMEhxzwHP2PBNr4aXiTId8+tIljBF/B2AOfDtV80SHz7lpSuj4kdbcSyfDdwZPsvXKoWnlRxLi AkOJfGgUVLnV/bRY2BnJ4uQ0ssX/gd33ANwScw4x+hHdeQjh+OuxYpfzwvLPUpeY1jqCROIGODl+ IaS1GWG73dhWFKgF41chiVZAHh1e8jJx/u8SNs7DjMot/I+CBJPylr620/R61C0c9BNMJv8DEYOo XM3gTNlCf/KXySjYIwqu5eax9GuRKHU4knBwJnqEgW+EA8gZQNRuryAyu8t7aze6YGgXv4fYn86U +/PFVHMO9HEjHWeAKBwwXiezGABUXEaHuwoTbzuIW9n7u7sfobAgnjX8GFqz/aKaoV3MEVI7Zv8+ kLREvGPymwmhxP3VTUcjjbnFhnrZG/pBECqS5eFgWKMR7nEYRNZBnzOqZSyxk9ovt9MVi5w2DTGL XyBTLyDfkljIPB20BerlXHMI6uuB71eWALT+IHAP/uPBZMvQFH1mktW5JQqQrqwNT+flWPDgedNN Mhn/bIyEVZww7yGFdOj1+qBEUC/Hx4vE82P1fjzQb2q18Vqg5+fhn5HVQjoR5na5YSc3NG3rmK8e ZYvGkBiuWXH9HlCUNtSSpru8h4idk7ZGLb73Ff1QzQ9WOqULWs1b326ghEp2pfrNAZbJmhzj5yxS YCWLlQZDYqkGQ9DXZfQnU8sDWp5eIQLieRWHpKVASY0ckHpv2lbWp+X8UvoURRhec8UFL+lXpvfy NV0Ht5J0ge93Y1Aq+h9+zMLaUIlwaGCex3HSyKfUpNOc7sgsBYY5bAGp5cp9hWQtz1IFdSIYPOFy UCyN3tsgQ4LnjgKsVMJasDyCwk7NTlpVRAId8nAdlDEJ5deRVpwm2BKbyURzbAzPtt32gZ8fhaNi 7RHtR1scsrYFDFdg5m0UaJaowk9y8khkPN8tHbbF9ClnVXe3r7Xa7VoJ8qqrfGLfbAWaG8Lp++fR wucf8SrgnSdZmbsCsCoVtN+Bf1z7I/I1NH25bIKlWfkulO0FkAgr24q0RMIgh/L95wrqKkYQ9mEk 9T3mnz59LUEoNBgxFai/PM7IK16By1hAUw1ufscArQjNEk5ndbzHqCQz2jzLOOsIGuIpqtDsJ8P9 S+eByrwbFio4v3GOvNtoG2T2aJpDUR5frWV9Wz48i32Y+dHb3Jl3DIfrGPFnPzKwi3vch7A+U9Dy Jx8RxBl3kAz53wsTI6ZwLRZ7nPPIMObnvo47rCCnnEkMLuy3CXUiZe26c+C/hgYNBG4waSnk2SiF 3lQ3+imjn4bO1njhwI5o6v4wJrsKwTkyCZyjY3AjzjJqxD1BvYbuO4Cak85fXwsdhDSUypcId37D kJYMgvtCMsMC801Uo2kET6q/zFFUjxHdR7XESXnNIp+KvfRA1kBF6CUXjDExyBTO+J5VLf8t/gWh tihxBHNNDD4Cel/IqM707uhZguir5/6/HeGNcOULBKU64JaUO8C74AMbsfHiNat/DVS9CAhXqYUl mxrphLZF480SScZ6o8qWXgAXl5k8Ogv2gDQxnn7/phON01yzwh9eedJSk9RWG+bxdNcO/01whxaL 1Hvp7+tzu+NHHjW1l3haurDqDVMmp/LLLPUE19eJUER8YdY4DqIJGgQvQjxPmqg/+tbbFbeFjTaD Wk9AvRzP+J5a1AoDGhRLpcBHpwfj+51UJUiTM67VwRC/BSYqF5nJGtDGAXRJ8v+bfcXhNbifszi3 yvdW4B8eNFe4H/lfgO8h+qXSEAOob4zre4UBdodfqaUzq1S+qtqZdGmnHio9rN/z/RUMl2YDT+ul nEIILSBI1xSVExKpHRkmLwGdyfNQtxwJJkRvnaoDa6yYejpEtRHJ4bfqL8caAbl7IEJgEtwUBTh8 MVjay/FT5USvbIGfU/KQX4ptft54iaF+5hIJ+eJE2ZT72SWFgy/tqGzKFT0sfSqcAl4uKiH/DSe7 9YoR7Wgga347T4L/swBR+5iguE8Cd257P90h4H7pG9S8wkuQJGzAPucvMaRLuKr7Jm7Cyms7rnxp kxh6G1pA88HHmIcmt4/MWaSkKyMYr0aMS99lg7JcQ7RbqE7LtKh0pKVthiUTzciWiXExcbnNPv5M 7QfSUtQtJSJiTrIu3P4mmnhxgPgcrl9BQZp3iETjJOk7eDfJCInOhMEwETT2P8pvT8RPUUSyRbzP WPssQ0OI1zqmP9jsOpHzyST9bN4xlF8OxmaLFFEddHelzKwXHLRgPqvH1+GDkTYzTZPIZYdELWW1 0d+CEtgda1eVep2JKkZpHjqmD2z5AZpQwKVkZ00T/1p73FoqvfHtbxBgIO7XKMAQWONuRktcTW5I 7lS4rkerJze9mrOnsIqX0mT9dRuY2ZBhALupbTvIg+4FfAXk303/KvnexK5GPJTVFo7ZuIC66LfX i1CxAOmvs9sj7iJaJy4B2MuztvDHL+Rdm+ga44q0QVqkBheTT+wLAcavq4uS4aqk8dcAayabtYkZ wRQf5uizuL2K90zpudVZMj9puR2DSOqW78ttFegLgOvQGhfHA/e2Vw/t/qlQrhRLGd6KuvIo6tVt q6BYNMI+xNyfV3l3n2EC1qMpzlnTUcutOyPkywXhUE1vsYoegO3OR77Icz5CP03FIb9bbKfjouoE bTCstTfet5CjURS5Jf4pBHH6bOvPKKjdeUyAJurr5ZHn0K+WgpQ0oPN+sMINyvTt2W45TxOcEWXh krsYMNYe+epYAAbOMWhRCKGVFfudZpOOD2WcqNvDsVOmDBzLtgaM30ljpOTA5a7+3qsvdzxe3pVC XvH+O5Hfr4le+Zy/+eu2PYwTysrmTKrnq7OcVNGMQPvPmuQdcY6+X8YVshGjkXnNtK5qzwMFeTZc 1j2JdpDoKsONbLJtiGaONZFLQunFo4aWXX1YO28V1TxyFgxGGgnGYzNuISiFE7av92Bmt+X8ex5s r4gTpwBQnVXlp7tK/0Hmqu3wJR7cjsbEVFOqKe8IwYqzL57/KsKb1f6hLaJ+aT+KRgauATiSKbF3 G5Zpbj+LwukERrhoXKrGeMFjFlaTfD5NV7RDQhW3brZu+4drh0hQe8jUhxPysVPH2G2hSrnpTr8i cwLKVay7ZX+IXFR38K+HHOTYAH4hMOrBLxu2Cpb3Yz+DIDxTDEkSyEiOkBt7X0aYSuxj3JD/J82K bjktME5B+v7eSmOucz+9Vtsec/uPCgj+BcUPQ2IqkIryNpZ5wRPUuRjiVGDu4zHncX8D4J4L/oEc LY94rzemfNaV/XMie8Nki/rls77rtdOXSgEsQrs+n5k6O6iEfLEc+SJl2OcvlRIbPjGGLmSv8Qbx Qu/9llVSFow0S0Q8cqOtNrUrRhROPd9tfGIbKlqdpdG9Zb00oPXXHtC5KeCjokIUYjC0VrdEj0nK pSRTdoi9EZ9JFVEcdnYvAo2AOZkSoXytlMFq89T5Qv5qLfybNZ8NDNGf6zb2YLAjuQ6QY7PKOCgQ egzmwLkYZlU4KcODH6HT63tpLfz97OPXiRnX9lwAFso1VSUyUCpGy4xxjs+kVIivqg/Ho9SbHnx2 jRPYOPopVcXQr9QUxnHYiEVeZt4h74VpLGTEFICsOOsLIK9eujhu6kdZyClRpsJHcmv6Gg0ZnmGr CLFBboFURI38IZAbpsc5p9T2fo+TXwcwGAqc8A0SkmPDoAziBBmEmmUg96em1zE9eGNzy/cJyb4S 6S80zn+i43Zr5qiE/ueCHjrusoJfCKGON0JBfQSCTAK75f+OXeauiTKyQX/PxvLnUU/Li5j3PqGN z0zsRW+k3kaw5PCK/QUDXYOTcFGAH7/s+XsGubgaRos7bOP6RyQemjtlKjWhfvWOz3xjvfAdby6V 5/fFxAOMFwjNfUkDHt/wLwVeHs/M0LdiTtIutNLphfIWq/d/lC08FcM1afEgnTuhnjIRQoULorIl tQUhekskQUVM3bHah8prXmR/N4qrhjlQJYcs7yPx3U15pG9U8IM3NDQiwKYjrNjxWiMIH5A2fmuT RGkU5/92rRXzBcC3COQQv5sqjV5QMv4HG0JWei++MuW1hCykWABG3oaJgUkAx7LT8EURA+ycsKh7 4vD4JGo1vLBJx2w1XBX9Ddkg6cYPlAHFAaUfGmP4fppXo674p0VjN/C0Uqn+HiWvcKjNmE6s7mvB MpB8clwkmImH+TpU9doOUKQxkvqjjZ+bE0kbhiYzXj+5N/bH6K1VPQFFvFgb6Izl3AbuM8OJgPAs wNbdBXDHOXo9V3GMu7GxxBA4jn/Y43/6HRPLPOrrgao/2VFs2i6V1KWzfFSsLXbGEF444GshAxuv 8Lbqd7rM09SyMcrYIfli2SBsbETLRUTeg7MdLMfV4SKPipLSZX4paPphh46oiJJtTFfShrM8h8eB 0cqvd1pwpKOwPPqX/nxBAPtZzTnztEhI4oX93whVR9+S7Se4ebLFOYhjVBFANHEr34UaYU7aFj4m /vrCLCp/E0CdMjwQ+kF1EDR5sMVQ4jEQgFzRn2DNFeE56OtoY3TobtA1LExfbvzBYBZwSiiMaZYe mIk6G8PDBLBL/YbXW/5IMPA7xK/hN2zjqDJSPoS9qYQrud+8BzlxFmV2O+fKLJY/PKwxX/MoJ5e4 35qAR+1jODCBlpuzT2Be+mJWJFt2/u60t/yYehLUZy2GNC/BpQ8TAslP1wqgrD0AZ/VftWRWB9wW h9yBQAzPdldRv+EgSTCXZxDXKKmbTHNseJRctPEN0GMWW3jL4FGXyR+MRBKq5kB8CYFPghT/FK4i Vaxv6FSv1roGWhXbh8vGvqr/K0b2/3TtLdIyTx+a1L7JFTC5l4fGVp8nBd/uFy93WIXQGwmhB7Gp zpEDN/hRi/9Loc6VDJc+HzncKQmgARUf3f9vvYjjzQY3u8KU7NYgWJ7cjCKM4DbVhmNvmEscfDOj TfEZu5HhB9q62Q1+qAOcIRwUr3PrniVoXa1klAxS6StyGvNzEDFkIfZNgYJSCLw+QKC4V4jrw7Df JG9DkAzqqYpyBWIoOugs7Bp9qgPY1XlV3ioRKMh/hYHO37W9ZiC4oxkGkAC8CqfCLr3dr1M1H2Ac yYyOFCJHCkhsrizfak3lGyuCrX333tcftcCQKacOqn8msrQka1bN/iCbAB4seqMaQBnuB3206/rW RCQKJMxoK3dqD4niSi7DirPcmkgHVkxoGpwD4a0leUc7VrDVSQ0Lmg+34XW5iCN+prjX75GpgVef l0lPkD/D83mbtJcqFWpzcqiIPzWSFBPtvDFNsFhMQ2gV35HrwR0DKR5Dw32jN/UA3aJfbeAL20Yz ijsLY8wRMUqHBZrKDZyEJkYoO6519tyzQu7aR9lvkWjs2vjusxsUBRmjMmGSZLYddGuvy2Im1mOS PwNbAadcSqpKSHpb3gFSw+hXtr8KX6kikUv3GggEe9vj1B+rXH9CGpZwFP6TOs042GoTvOddGCNl TGHM2ExiqnGsAaCAm4VF3KukzqbpFCaW1lCaV/s6UjO/Mfhk7SdmouttxUZArxC47lxewGB/+eDt eWWJnWNAM9RTdtCe6+2LgA22pcTpi2uZF5LAgW40SeoCJZYBTqE5BpKde4Rrg8BKE5RIu0A6W+j3 YZoXh/8kJ3Ugu/RfovALpbR3HGBvwL3bwZREJKmyYGaTTl1XscwUGyz/tMGn8FCBJsLdAyVA2+lB UxWJdUlSlt7lcLluSuyjLexiQsIxhCZ2vjYW1pEWVZomQggeOYu3W7tmdOXWXbpL3b3QOOsiv6Kr aVfI0g1MkkWF31fr3lklvg4Q02fK/+BWmoaRUysR0YnM7jsUmKOyfFFKhd3eCQ+ohqA4EqMVKRpE t+AIq9mCVv7tASWlEOExgBOkiR3UW9XMBq7M5MX7ddOH43niuKM+/zUxjvnRRpIDol5prLMZ9fBr UqnAAZmczr7CR6XfyPdeQn5vRgXFPkMeY27H0mLB2xBHpRnG4W3Dcu/CfGbbVEMgG9kTNYp38HCO 4t0V8IILAS8yJ5scVmeAsj9I1laZ+nXv6sKmhmHnhqhVrp1bszFbPLv8BYSUalHeWhCClTnSer93 zNYOd8JA9wOiNxIXidgzs2uuwYKPQTqS08pbnVBiyZYrkBUsHebT9pW6+me3hebo80grm1INYaK9 tWzdaA59YbhbRcoYja/K+KCT+YaMlZvrK0JVHdVQxnsR9X8QkWh/CTeGuPRiM0D2divRb3LxDfpV m5hf2Tji3hwH6plPKphfEn0WT57tBCES9uTEyJN1ET94gaCm6YY/w24aGxgffb9awF9+FFrRGLMe d99JbQ19WCI6nJwBMFJlxD/1VKRXF4TDI77LCTcNb8i6+L8LPVEb1uOnu1I18cGDX0lzvrD2kdF+ HLOjeCQphucECQRzTFt+BzscLKFzZE6B1JtGx6EVT8jaoXyz9hLsnfFsAmUnssw+CwdGxe6jUTMI NDcK8P+G+aSweCHlyN64K9oDlkdiIVzM9xLK+Ahfb45WGNkaTPdyskoKWThkAjc2ncupXz4y6/XS s/U/LKA3226yDpTsPjL/3oZ5hu4NWMDVHNxKiu8sercAxdYQd86UM3+it0/q7hEmN6CB5/Qwnc9W xIQfnaryCKvhFLu3Hf3+XvBTmtvImRxqfHj3brlsFacMUXPeUNZu2TCHxLWUp+nmLRm7t57pko8g HWLKbIesFqMp9HEsvGsl/Eo18R3+QQ3ROO5Dzp+/aRXmk+jJka8n9CVCWSVJfToZotS9Uyln3ZbW OAhEVpTVbXzUbo6rOgIMgohCBYOD9d3rzBHjHnI3tEzgnZzZnMh6Q2ZdEJMNr+lduN2SLwAENdBz n2dPsFMPfv+qC3kab/MGtYuah4utJAQfiINioDtuS8aek6akpE2BkpUOqjwhq5GTEL9TvLoun2zq Usw26kPN999H/3LvlKr3CPkN+Ztvs34IkREEONJEUqJCsnukHAMCmJXOCv+JkPhVHhIIXtMAieaN kys9LMf/5LdVLtRMBNXrnjOmHA4iT5bm5l4ylcNj+eOAHPLmq1xO2oCBAa041KsPR0A/X/4f1ogS fYPvxzDEHkeTmMzu6679hmRF0e8AFzs7kkmF1ooBVC1gCG9m+5+5OsRXTRKgEGrpfdYfrMGMhlWo JleGrs2+1VQFNinj5BJA8zc1FJVh2uePXh8+2xiqRJQkxu8eXkt1xOc49t0nP2Hyiw+Ez4F4umsy L8yYEWEsayXgMCvpufM0dtaKMgKgDLs9Njnmeh5KfaZSVsjcpTRYaCBMpKDTQJZ1N+vERWhs4dom dkLsrSacPwfvchMRDK3YzCURHvf40VngRgKjRi6UgVJoWFP385PrjBEtLarbCIHkch3sW/W1e5KD jp3FVXzcghgBYWPZYHSbcY1/SImnhw/bEmwFXTcAlmg9TbcWbLmxjKZDDQ1Mjih7pH1Sg8cOrY98 amGAw1yeRtQt4H+twmdbXuMwhfGCMtTK6Hylb4C1nB4V6MokBYhT9KAmAYdB0RihX7jY54g01v91 S47xpDPygGBt8lC8qODz8h3qMDjJHq6bqkqtQSIJ6HtBuF2aHRJcWD/AEGdtwc34Y1eQ4VuF2ir1 /4AYJZ1AI2ojRVel0AvgMyw7fN3ZXVoyGZ0Kzz2w0qINhPvpG1ibI4ulElnSngzK4S2irsiOGzK4 DscbatywJUfgsP7gj89FkOIEKp+stC742uXDJczZs6njfSCxLsq98evZIjfJadi1lfxf6PcmRz45 07MsvxnpkXNQztliaoaurcsyjhUeLeKmpCEyMCnOyh9mVwJ0Ym6XKOK6jQp7Gwv43GyAIqx+T3f3 x1vyFYtx0Ra29uWaltpeLLkigv4ol5ikuxIdzvcchM6eufLFy3IgdN9FOrCkUvC68rzFc597FzXb ODUwroV5cAEQyuxtdmjqo1GJwqTJ9R0f6yjP/mUAI52GAcnOHFu9TiOyKtKuhNjByuEIwHKnlE2B E/quFr5SSaxPURWtmHEW/3ePkow0cTGiRcpUBvGAqIlVRVdwqWn3HWGjDcL+1U7tb7Ly91WobxNN 8lcQfLBy3Sy2uMPzZ1X9s/bbVFA/ZAFlX9KjUSmxOgUHL5MPNnQ+jMFUecCUDtbcpiGHSuOcyxjq GqKpSyoac7jFV5gx0G7y4YTyGfhxIbZUht/0ooDAxHX0dUP8ba2XrI7YdE7b9u+HPNjP3hV3kY3m cYGkJCMEnqCwv+bzNKd1R1P3T3RTu41fYimwAtuGU/PR2TOkLJpgvXNOaohdDe4nuiprMk85s+8x cnx20fiCdlJz7qp2mLHH2BbvslY+Z+GBtHoZrJI/3lI2kdIsGEnPFd6cziV1EoyIFy5R3Cj65yxu Vb39GulT612eJKlb8Egx2Jcs9GaE46B3CujxeQNna3I10fSSzzF83jY8lVcYsXmfUnwMkwrA72al ZAL8feURABA3E8SnLBmTV6JPhI1lxpwlRzAXJtAMkeDgalkSpQb/utfxJCSTFfP6ZL+J4ZE4Y+SA eIdqlCpoN872rrWj1xpGA0TjR2FiteLRzoJ6iAoqJZU/9CVCqWOUrkXq1Y6oJkOSd/GjXLlb1Vee cKjhOxPNIE1Rv/Tsu0t7VWUOtWFEz3tLWhk71Uw0MnYS2coYADNkFFo6oBFZN02YczAMeP37NkgK EBujWtc25djZ2+6UheOX/dtl4y4/T8bIOYD1WQXTQ4SPBNKrYu00qizF6rkHlKK6TiiVGCUx+JpI tvhHxMqUzr5dp42iP4Nu/plUTJmSqjjzCwrvNU2vkfkA3qSZvHjzh4eC9Ye7ZMdvZBx4Klqybut0 14gukAFh5vdtg2uN9gP0dmiu9oh4PVB5BVI1EyW3JQ2mZrn4y49e3No2R7CDlggeM+UbSQalFpqA ZkcBDocyJvUi54qCUrXt3FrCW1sohJtxujAereE51MjGa2u/aXG5gEuKsZ0ZmqTl3y3yV6kGDNDJ 7yaz9mDiOrKG3er7hcMnGPFV4RPEljVZRJHZmpWvGan8Chx8l7vlFL26l8g91pA4d14B7Ts81fXT fgUS+PkebqqR+IxmDNXWdqniSFNJC/WK4McpBMJeshohk7EB1YfmfSMmnhzqPvz3L8RDgRJzKC7U Uatntfx5xXf83ba/dzZFZOVnvRzEVN42J9oCDVYR1xpUrGoR/PUJgz01Q5H4Cel9AEmT06VzTt4H jNbU+yQ0YZo70n3bNk9WNC7u9FarbFKUV3/EuOHB/1JxeCM8x1FXp/AZK2yHvs8hlQZPuR346Ujd dFX2y1FsH7FkIo1ursbnMeCgGWADXj0heaa1P++0OGSG0QypzR4+sByA23c3attfDeEKdzYWajPl WW/vc5KJei4GTiMFd5wY72ALGBJV9bX8GDQ8BEV2cTyW+vEt817D80Ehbr+GDfWOHpqgBvZGRgj/ Eo7Dn/+gy65Yd0frADJStWi8ZRWTYFMtot6xzwV+QiYcj9e1/X1LeQ1vHBDQTTgbn1CSDIhV2SHi 1k0MXJZWaThdO1tLLJNPQcKgRaSWgHaWo6G8Z5GhtgsJu9NIlGTffzTEL6j9UG5qK6umMcH1m7ir mG409fT/fiHlHDtf45gz1LjXu20SZZ7Jw69xIphzjo5L8bhi9X9HZkmZ4JoQELWayT4oJmgT0zdN HHDDSLJR9o5AF1EdE1RbPKj+FDUOoSa3hs+ljTtqQHdjPD2M+AlzyCmIGy9shKQ+SMCy4ASjIxBN BGvmnP3iWjy2kttgl52IgQs/9149HS8dzPgtyb4r+zXpGzVLOLYJTWzRrmt2F0loshZc/rTSLVpz LWcp+60mAwjDF6rqB64j4Kpf0VQOfSVsvxK23dRFsC2SaBJ8bbr5l0uUhLadw7GAM6Rz1LXgmJtD EVEiYeq2aqgN944SdaZ6kpG2VL8/REnGg7F8biP5BxhfCH47nmsnqPmMIPyrHmtpHNTrJ79J7op+ HFIqo50Igpjj8Oens6b8DSkmv+5zrAdMvbogA/eFXEyloQuMjh7B7pvH+boC6puEtGWtipfPAoeK f4pMK53rmWbln15vxBJJFpH8UbOyTGMpD9DpCGjjKNJm6G4ix7kDfTCCcS2yp/1fi9X7QrmudEFb R2sRAcyrLtGUrnP6nOlBtVGvut8biyZ+8AMZlEQI+TaEh2ZpyJ72Q+LrPuGG3c9SQzIaZT0ZIXSr EHX10/0UpoiQixDoudtUyVxhj5AHYBRuO12vHq6OE0R83KrzkvyZ5TV97CEyhKXljh2fTZ9Bs9ZY 7I8kZu60r85fhzZcKoNZHOcPPw30uv2EurU6ilxEd1FY6cEA3qtQJgjFd9X34vgsXMvXVF6iXNb4 Qywm4NdcSalsWZ0owrIQh+0/gVu5/AhTEM0rk+/rmXop+N+5ZNRFda+XGODFlUx7j3tXl5RKS00M yA3nio128kvLV3rhoVdSKcNs8+DjSuNvttTIwSbDlMkFBLLtgoNJzDWczw/yeD3pAnWR4bDOPhHT BZDdR5BGmavuQm8FYR70OzX0LsTiNbPgVlOSH7ijvKAnRd2O5RRWYDnUw5H97EV+JIqQ70iZA55m H/+k1dg939k7sN8t4ammWXFyo4cX+8DjjaCMC8BkUWttL5ExeDjpSzXAYMfIr32mfMtcrLB2UfJX WFM+3CPKRZxHqfVGV0X+Jmfyydc/T/9GCJuDV56QzDI5hmGlDclLbnjrkeIuoIQGVq0WhNUgerfq d5xFxNA2dJjhLkbA3SEFKo7R3ROg5QuZegpskTiAVYs6RA54unkQhrbJFZ+grsA0DI0eqpF18jL+ DOXQMnwUx8lHMl68T+fePgTMM9+voJjCXKv2BSRHu9lgiDSGa9AnwX7alVrxU62SB9ekpTQGrp1e niK1IaE16fNp7Z1J90PhF/WUR6+ZcSNB8i0gLce+oCBvt1rvaK26a2ZpESJaoO0QZ60kzoLNRvzz 1bNN6kUOFDMnJX8XT0IaEOolXyivopvOE8TdiTMOSI7b6Y64+5dd8Cnl5ecYMgjReBIIWRqvfxjm jGP7iwGYibm4iZ7YsPiKCvhBpusYbVwBrd9VW/mDUyUCwpPUTkM77ImYqRBEflKq1gYKBcgNpWvt UutSP/WyJz9tWIyYkMdvk+8uP91JCg0S8B2DKzPi2KnBtiVOVhMH1ovcl/qQHm0OiL+9jw1K51qc ikcxrRRQSlnAhQPckOZ1YsVPTXT5axylr3PcqDFjzydk1x3et5bNcveVT/eqhf1nVvnLKbjBfW82 LC9xBt/h1w0wkfrcERBUWUGR3CVR7FGZOZeB12jiRsbzsXsSmNcfdxGd3G4DrYiUYLm3y43Ycx1g k9i0l0NwwCR1a+te/xVGqh9soBeK4w6/kDPQf31TqUT9LvJOAnVDOBQ/ESuS09qshelzC8oDSUXm BnthkFpNcmEvAssr0H0kudLy1MgkvlhcloHacrPBXi7hXARlsodpP8LfphN0Kl7eUP00WYLcAyf7 RnNJv2h0EeFtnuUcafxsPyCGwbBzZmDd9CCtzIkRUckr6+i0vlIzNLO2sjxGDOhlQSCCQL0nsTA0 95UxC1M9Vhos8B/4/PJyIQNQDTDvTgOn7vigaSB7LLkjVMNiTFr1rGM6504hdHlMk0FrO5yNtkB4 fuKLQ1aeXnw0lEiCsRHkxKcxCJDFKSOQZtVbGrt3DRWqOr0AIgCpfDKn3PlJcR7UDmgCY8V4t3JM 9aajrLm9opy9qXM7pwXCDxAZnDxHX9NPhpojyU8iRbxUxXSjr5KEwadAUssNiwEt3/Acf7XH0eq3 qUgNVjwu6llQbLarHuUlVXRZrPZAQbL5jmJFPhDAUcvtonSf6frvm1Adeq/v9u3Jql78Qld16tX4 /vgfmPS/1qkdcKbCpWbc5PzrcdjN/L1aLKIynB7CsRvtIvUFbzRQ+wxMxTzjljwxrew5vBzkvXvF v0Bt/jxrsAuz9XEj0KciDaDr70M4S9b2sC5f7HVd/82bQ1HGX15n3dMPdMk2z97Ryjd3EC0ZkI8X 6mqlV3PV1MGt/k17LW/l+sn4pWe1C8+Dj2um57XNjElp4fjCumHKTqDKE+uPsGWR38OiyjqTdLge SzS1/JRQIlWq7S4dSdCDVMT7hTdwLQRSvim3z/y9Qt9Trn3Sh4DG3ZmgyPkZUoQkH4OJbySiTzBW Su9aJveU184sVYPAhmmYofmbNWt2dvmRq/y7tbbtyEDbdVVzeagAfUZMUWszxXrMKED6lY+OFSyc bxTvdOXYrO+EmhApTYd4CNy3UxPpbVcvqtZgnXJOccfjwVUi8H4MMDVUlv2x1SW8pFGohwusZENi Ke4ALQg0m27AhXCLVlh79Ge8VBsMQLAK3u/2a1jOybW6cXMQ/6bv76pCOsFOTfZKB1RMTzhzfv0a vgdxiLRK4MWIBjYqIFoX68ESxavhR8OZ0ETHoIDpPeOQmx9ww5I3or+KRQBVlRs2MSEyNHIEVX8z mqJfcbn6q6Vc1AqYyaBmmLYuOnxaC4fcBuOwLlZ/1iDq7wl7+OtNh49qPani4c7juV11Ojqd4IbG bfY47S8WmYlgtS4xwzXZ1oseIDHiFUahxGxoMDV3+0NMlM8O7WRy3w+wCwtkG+8O0lusXuOOnNII d2cHx7PJeBcRKd8XBi6xNGBvnos4sEQ91zZDVH78vFlFHBmXP54zMgA6yPFvd/K5bywma0BQt3Rx QkKMseQvUHnuI+FNcViAepoLtnDtnhOpcPAaM8X2y9OYZo/1M+FR4C7ohLpdQoHFJHkKKRFTmMeP Tzkw30NHbdpLTz+8XHwB3xOnB2mkPO1aVT86anNGt6csJ+EDaAZZ+dGtVvZeQ2ChTi1qm6izjibb 9m42q0Bn4pAPP6HiBjzVeTkUIjhZpmMhWyBPTzn/XeUr+A7DnVOCJzZY9UhRsuk+i/JKvhFL5FyV Bckrr5cXIPM8i6l+720T0v+ByogmSCkjkJIbVzICx7MCpwt/VsMypOqw+qv4TRUGjRH3D14BYI4f b+XQx+F358cA+a57r28Re9USKSAh8YweBV9zpY6a1RuXAWP6M3+YpjNKoXVMWvu7K7mSqzJ4cV02 J7GqFrX3637GsVv5lfNQ5OUv7TPQJtGVgWP69Qiq4RBoTZh/jUfZIIIFwNFXMIqrMPFtLTpYfymE /2Ok5qpw/NorvgS4bGm21sF1hqQ4wU1Nnw2qjeepgbGssRz9IQb92a53vyjvuRmV/jPvHSA4549+ gezYVVAbncKDOHsR2HoZBZepd9bUhZhIsNDFT/AFJH/GMc3ZlduG4KDXW4JEOk5wYvVB3Lku8WIS Qh7UsGqLKvmTDhDynDQHjANRSXPL43E/NiBtRsPjkG4GvVorsqQq+Wg6UZjWr6EPkPTDiJ5LhyLY 2V1y5aj4WepUbYV3dKRm5lh//wCQNsh3mXSp3nX0unfmWnnoZxmVS2dCLwf90awds1DbeP45JXJc /wF9mFe768H4kNkH1iVY/U6q8Z5y5F+r/C5xPp5+l5clhqI4b9ukfg+CKkuOdyBWNG00j8A5fl6K eyX8VY0e+8dZhCA97p/7BCqxHh43VRu4emn32ifFhkt99gDO4EY2CGc/xMP+IHQEoYB7acCiaiP3 JhHxqDNX3RBqYporY/+FHn1yj7mp+tTf/ROdRAADsnTZUhd4ducQhUnoRQtDM6C5SVN/NxEEa82c iAlgDZy3HhiqbsBTVaWxVFUVn3R0mdlkMYc+jQEJxI2QQUYKKPawYDEmUvrcpYNC7RMUjUVF0g6n HNQmoOO+WVftnZfy8pHPYHLQAerQMOFMRJB9p2+BGWtmPyBgrRVotIAKfTgzty4VFtfR3DoVP9gs 3ACIlLwIA1ae3ntQpEKYjeMpR7uMMwsaT5mMEwQ4IXj9Bj79/8va/l8HjiuoWZoot52gEWY2sQWy ZJEyaR1s1T1mb0zZqKh5PaXu39J5h3+ZZBXYpezjEMJoV07sFmOJgK2SSVVKcmrJal8jw60Bcpoj SaOmHWHo3E7gptzP4zyAdebLx3p0SXlgfnw7gvwUjuMO3SxUHKRvynXcMp9aTfJYKVqZByf6ioX/ n89m6uWIDpiecTME5rZomNHIGeoChTPxnwUYQsgKuzU2rohucmnQMdurjTxtdC/I3iKNsKMVamWG j7buNCvi7LlmxsWo+p/BkQADh1+AK2YpL9W0F8+6/EjS3rQSIi9ml2AkbacIx4HLR/VgRvSefm+0 DRrtcLNu6x1zz32Tyt73uj6XfyuV4zKQYo2SUhncAfqlGZCuj3wUMiySBNsK5BVIttY4FeigIg2y jk04B+cmhg2GMwMePnxHhDsYGXmlroyFWvQs351Qa6QoErf5uMMc+JZ2fMGOWO/lukhw7oIE0sVB TssXfkI7v3WohE0jft0WnxcsBtL/s7VhU0Oc6yE5772e1p2zEF93UHFI+zeoKfTMnIMw4haisPBI tODuBC9cj6Aiaxv0bmp7T/Q39S9eoDnlqPGOHeKEJfCoy2yEpcZ6x0F+jjQYV5/vav9x6M51oXLB Pzm5ppEUsWvVxasLTstqE0Zx7QNsz4vT+j3i+AQdyvEfiS5HOvHgGTmkJv4AsZL6jdrb8kooMFWT 1MOGEO6hAt3lCUHXo3SgreICtUtKdiAgfsuJ6ZisgenD2MC4gpJyTUWFauGIjFGVVoNjT/vPz6l+ ZovGiSMFZ4OMBSVjz7b2WWgR02ndKNPWCUEOWddZMr43o/yyv181qhBFb0K9q4vbi0XVJGNngAZ2 5kL4ais/DdBY4EY86SzeQvhVy70HiHgaUmRIbLEhjBmWrwxhBtrjmIcDYlKZMfngKMzQeymarmeI 8f6EgDbMiBR/1V86cmmXK3tambtMDcllp/ckJUr5lC9bRn9eDKnLpL1KPRZNGDFp/PtzTmvOWax5 lfj+sClOVv384EtFYtnSOEBwg2eGpFgZFOcYC47KqAFH8wsPgIPmX283NeooSHkwj8f+kSf9hXKF jJcE4c0Zh8dAK2ixTf8cwmIyEpA66YcQgmcO5zbn8bxVsi0vn0r+wNS+DQ+nvEGLWWyeP38zyyHu oTXZuYb01ViXtyMMAWV8uHKIApJHdPK5JdEROL9ogfnqv+IVcoywAOxPw79jIRX9rir806R7wocG JHjyeG3OjDe3NagmWBWEAelmtXp+witAAlBTtYUa3kt58LbY2CdEwFTs9V/ZBXl+sr980WyI45Z4 4YIBlaJSVZaART1E6/J9CeUGOKPTMXfHaXvIOADORfJnmLFrKS35p6FrlfNWkPTE7NHu9S3sd696 Viw/f7y38qQp70vQmaYSfKFIqehSLLuJnZACcL9wtzB4BNj2vnEenum5sDtViE9mWTmN/B/c5utn 9EKbkwgnEhYANKBiG7LdvzHOLkcAdvCcEQy6WcZpma1R/T/0gkjHYjjUl0MdzVzOlNGYFH/16S+V +l4cFPC4aznB5HmQAWHay5l5dISw5P6KqvGtvXdRwBuN/0f6f0AwwPBbIjWGF9jKh9nZau6ZrxBx zmW3FEgl8sBAB2HrUWPGizxssba1ugHm3+UaH4rfO22s1gjAW11sPFhyluyIgF17BgHh+fSHmjtb 5JUyPa6N2nZhcAdHuYm3Mz2tDphOQPacuQj/TsLcCBwS1/jpblt+VJaXzPS0497rF7ErwYjJXe70 +Iqf0Z9I/tRg1Ep2/qq7C8nIjwN1lCm8mZI2cwHLbB+WdqILn19utqQHxgOLwj9HnYzf24fpWs+a Ublja8W6z0u3UQ6PCtSexi5X40rSON1p2ukMJ3+6nptqjDmX7ip0SIv3a0vZHx49RFKdw6amlyQ1 WHKDRcPN+h6CJbDYrhRo344fTu4Btc++OzDZFrD8GzULtciQfAK7Phr2PpgILmsWU1JSr4tUsWJN xZoz79J7zv+ommpZoIBfUi/GkRT9rJJ5Y6SslgGS8Zc8rAJUs0J38yNHwiOvHWeSXhf7jAqPz3Nw +5XEKfFKXwgtRGWrgXBpzad2LoqJdhLDXKwqDQSXMF1uwcpkAEe0BRd0GI9XCoyoIBgxN/OoFZGv IYuc2MHLs37CMJjDGsVEgy8HbaV3oT5IH+cZrbqHh9KLosurX2FuwGEjUyZD+5jWYDIrCi/uI8/O SbTMYYWorfmrFnFAd5UUo5dobbvuZT5xRFW7TUnMcO8zKPlRdT0ZDGSut6nPBjpzRgz4prc/e1g7 Qk36acSHaTmnzF72huOAsqYcFLklD6Q5ebofz+1navGAsOpfSOyvDamx1uRWediZ132xs0sD4rnh STzgdXpUZtL1tcNJ7vYwEGr385k2h8snG4RZOh3UrI8jAGxnLe0BrTVZFM6hXONaLGapeFST7aLk lQ0jSJ0VjSW5zIe6HwVRw9wZ2o6ETaStq/gzKhxVFa6/DJFFwN/LmU3aleWqFb8y2kVzZkBaSTyX 4GmoesKOfPRbaMVZm42irJoeKnA/4p5G45Bxo88w2TswgEIGmaJ0J0YWujdzUrKzZd+1QPgjXeUr KGdRMCl2AskNTiNEWNY81Zl8wZiL7Oyc9Q/B8PFI8m0wIxIXcFUzufQUo1ArWxgQTLvgGC2krtA+ 8a6jBTH0jr7XDzQAejuDffhMMuLhCQNkrDN3TrseDpxcovyM7dtKLXtPqjMc1xlGNkSQ/SIRcNmD hgAebhITxmfWfbdEk9JcxIR+BJx6RQHYUTTrNfVqv1FjquULS/+nTSvHwjf3MACVbAwfd+mV6dgF sEDjOwwHlCepOsmeWsG7bcrZHtmPnOY9ddJkpz/ZlQKqNEPlZmrQg0gnpPk2LcB7GITKG4omtFPT 4FTuktjdfP4lCYLdkDcMAX1gdqyrqxbMLnKZRTN9RiWzIMsQiECKRp84wO4UyaFtDp66ItOi1fTq TVypuDQhLMLTQo8iBAJcQJ6iYTFY4+IlVilKWPqlfUfRnU26SjbBohwuXMkzm7nC6MvCrddZ+Vhr I8esKh6skT16vqUvh6L9DOmorHzIiZ3g8eoo151G8aA2X6B8vTu/cp2f54y7s+JDD8mnc+b5JT7G gRQqwA1wHRrjiz8Re2bQLNsOyonMjvc5My8ZLImTrmun1l1i+wq21qJmJsYQstaLZDkBA97mfcm3 nLaeER29u74yzSy1MIlaCb6P00A+9ryFnS+MSuNwd1lHbyVGu70FjCeNbmJvUHfE+qFrauBriduy uHPetJrSy5yyzSxE8yzF3B5NTsn5vvd1JozlcB2zD5tVcmzzZ0xu12jwJDMEKIp108HwuJmA3ZHg IrZTpZOKVF6ON1JA1tLUWu2H+NqYiAKJfOzIvCFCZ8+CY0tVTAJrAtc9WQAg0uLt+C5RxgTTJZ8Y KMwbmhKprOn71xsRvVS9lpB9e+6CZne/J6wfQqNquLKqS4R3NA4c66xT0yQD9Hf8qQVO2mepnmhC UdYpfB+yB7VYikC61kAs7SlhWY27KQSqJEZPtbXrVIXzXAuJl69hnPsJ6bOhbKaF09ETurLhHbQN hf0QsG8rrOOkrTBQZa+2HVSOJ2pfLYYrtjaob++xuM3rFtqK0QUZ8D5/8/2WhueDSbVtmV4c2ZZP PrWNwoaKy8NiVectIHikGMEzeOY6J8gqO/lsIHqpsSRy1b8OkWaJhrWlDAtd6DiatPbqs0KTfwjw ylGjuLQlM6f71AdV8wtFHcJr6Oh4zKBiCkPT+y9fJJfDWOxmEcel9pKkpTE+zRprkeSpuzVhUFyE o0+XdiE/1+SnhwOaFLbU9RFeK6a4TLbTiXQjA6Bs8tydZyc5gEE90FxYm/39dmYZXFm6A2xgJdHv rSg0x0Nu3Dra+YaokKeTnzVTrYJHdEEW0VZnbKaoKSKBBWgrzHGQCqpllpqVsjWwMduln/o7kt4r l6eDAo/t59BgQGtkX2Er3l+tXawVdSFKPKs2C9D9/lQrHPa9qwRGV88LpvPg157YKLJWmAwKch9B Ir/Vi5td/28mACftDIlERjPcXJWzkphBSjw1t9kU2gO8scHaUoJ1FmfnnWxdjXsilfvRzRt/pWaW dAgue+/F7RVFRn115SOgBVF854qeBVqXJwUCx5rh5RvT6qY73AYsL5kDKmWH3idDem97mNT7wKXr RU+bTmT+N0J5UzdqCaen7elFVuLuK0cYgfkjiDrjttG482gweDe9poRVFYhwhzbd/Z8KbigNUXny E70CzG7gZAIjDmEUeHXFcr8tCyLh9FdIUf5mxpu3FbLrGuHPwr55U+tHeMBwBdjgtHLZVA6p5Lg2 wFYJ0n3lmjmVGTjV1lwRXjPO6WvpiESBRuFiKl1k5fIUM6KjsPoeNAL+RRaQNudl1uFDdt5ycgii 7/iafbU7c1gf3lU76gbKO9bribpP2NM8wqKYEne+0TRoTcvKIrGbNBf5dorx9S6BtJSpJklzQD/K WdLZ8NawpTiKTQ4C5rzKKV9HN4XKontaHv8I+McTRBSUG+57dbakTkjgYgjjWEq+Z8ZtL3UIxwCd SVYU7qcWKl1lIG9o/hHo6toWauxJUbUYKG5oCOIlqKVgktl+F89U8c1EMOILPnQte9aNe57GCck9 P9q3wrS6gT0oDZKzxpRxeHO2FrKHsX1RxzbQ1eSkKDZBQxoioEhWBcX9jCRi+B5/SFSC5h64PHs+ rtI4ICrXvuAFkV4rKbJ5Y5pKdCgiIOCEU6IejSKr3Y/R5azsUX7vApfgGBgER8qTKAuJMF6bmL/S 4RXEjmf2bvEq8FHb/4rMau45GCWz+K8mPOPX7wamynGV+GxJIt9JAkeP8b42Pm82IOTsnXXqstw8 iWCkcqtbWi/YRdfC7skPMLsYvvORfwrAuhmzxIA+fwr1menRedpzdI1jCa+mngfvGnHU0qwqLm7M I1GfvwHPjsFoVNV7kSUhSLPwQFmIZ5bk2rNnQ4nxWx5Vaqu5zNyrSIdsLtfgcqfbEXiTiwfJbsmY 63/mqFRW/nzcyRoh8M0FB8wO1oV9uy5VgUz4eKRYdPa32e9puUQJkenPTYPAZLRAOnV4rvQ+c4E3 hAOdGSY3qhRALtvPBNGYp42cwEiA5S0DHRP5pvJ7P2iXnm98FkDtdAWmV725tUybn7GZ4kxslONR he590ErT2jcVvmPrGWYRFAZwiCe/0dHwT5S0Zwd8a5J1KE9e22vKsYqeuM5+Y9BtWv4tZ4TnqMls 0joOV9NBMYzmL7lkZ3YX//g3e8Dv0NCwKwn9TEY1b3sOMj1CoGS2V5+jAJuQwtbAf3AoGK+EnC0Q LaPc2zA2G4G4qCgpE7glH/pCjn47PM/dw/IO80D3siE6K9LQjauc0R5UOV754fwT0o4Sbl9gWwUJ u3NsDkf7CF/nQWhPJNn84sA4Mfq2mmkZVJBRNHdm2rYha1WOUTUI6lnl1d4S/xBCyD64wLMe2Uvc JspAxIItBcykgTVKSPB4uMJbNxixfNHaiU0Q7po3l0Poy5igBNMk7If4Egyi2C7Mr6lG8Zwhol7T wedAJL/uWAJ8+ibN28uv0a4+juXUp9Kl7dX8K3jAn2qSARbZfBYaB/SKylEgjB7B/DpngoJ3JEKw Gjpkw+qDGgluuiH4h5IwKUD3GB2W7lwd3KvQUX6Y0Ep+9b8wJ+17kBD4RFyMRoABCfGRL0EzOrZu ZCpCmFweG4/HP8LaWQd4EXkeSwq/2lJty0T5OTy0JQJa3K0cZ8JthKUDdbmyJn2B345XGg23XoM/ vKjxIEQIDI0Wgs1Nhs2YH6AayHwH1MqsE/DkKkm5yZFoDE+HUQdF++u/4euC+nKa0W4JeiuaN8RO R9rZkkIK430m2OGkHsT5LOm1iQQJTbL8hqogDXnsP+3l0ETAIPH+u/5BKVBQeNU7nX50ZOmKl3se 0vvjXl4iq2/UkZIvt+CPB6F4NupkhaA8XoUdkAB1PuK9gJHT+DYlo1F4QtR/eSjturwvF8W2fVam 7zPv5J3zN0E7+nkgfxF6lp7/syzJBsSYghrrYcab9t/cpdarygz8Z/4+m/nDCW68lsLhUxhLTRY3 QDWjOLbnqtylmWy4ZwdLK6aCrybGpbkF142Qa9YmG6LQeAxX080KiVdiDUoIzedveSfjuNyU3jwu QVUZ+1RBGgjgBljj0zSweZE1sPlnfthscXihbcQkCiIgHQi73EruBdE9oGSNUFW6p+6qwYGgygv+ 55s4HaL+d3vkXOJZGbYLNM/FJcid0qzY2jr6MtnlgXy1zZ11//AD5lR/3XMW9iRBKLKmwP91jiKu ngfqUxks5+14clO6PORDspu1FKay4Op00n3Mba0gr8QUmpG1LXIuMgnPIiWRr3Wp/bnGgfYc1moH 7vYRNHYZfIKOM6UZThjoyVGct19H3JXBzKAoh5iVBFlXgPOsRpXPP+Zh53j+T5H7jKY2Xo6rGQYc dai5svb3GV90EIGT03i0efGgTfHEMvxJFZZMlXeNiIEFhP8zGT8nnissjggaQVSFwf6Um/ehhRiI yeXVLj3L7i2HlWpG3SOWNB4F32SQTfj1aoczJEQxah51FW92/aI0sU3A+6QadwIj4uFuaq///TnK pDy3PLVNuviQvSex9rv3ZO0Xe62v9ce+VUnHgZyCraoIc9EJyT8vV52YrehcSp6Ae83UgeKDukOr Z6WQR97GJ66zvehqigJSuaGQHvvMMiN4L3uM2N0k73wJwdWwBzJfL6AKFoyhqD56lErURMkNCxIw rAh9TzKdzJ7+zlgDF5M0FFJuhhP1dXwDHubFUPchq8/AO4i6R14Lf14SERWwRVTsozAfj0AWNxiT X/ByZbNs2RcIQpq3GIXD6LNowq9Ccllm+S1tR9E23EyUTZXfTwd6nUmsjsp3MHD3eE8I+WZpW868 pwU2WfPwWcAw2wrnBHQPkKN6gkfzZ7MlDJjb0iRJMqdd2aAhi58uSmVvbv0vMxtEcpceqfmofR/Z 5/Ugrs8w39LIILUndOCLB5zLd7qaqi0Teg9UZH1ZF7L2gXl1F8L/N9Llf3rNdwlPtjIcA4oAJ4Tw RANUQU3snwcfjEmEaLpJkIi0Wy/48jvZmV6EgVT0aOTvv616ueR2RHjmSxnrdakzz0pLpKhYcEWr VVWHlliGsA+v/6MAjLpLHtxsF3S+JBztWaGP/1dE1ZrKcvBzy31iIzZLc6aZ+dibygOfyd70VEKB We0q/gXCn/+jegFkU5OGZiAczI9lv1fxGchw8UabHgPHuGlqeEvflq/I/xkth2vqGAPzyxsUfHrP 1txSBPalibisHYfiN/8dJ/uTysFp1UA5wQphxCfEIddDrz3gFM+cyvbGu2rzz9a+DcntZL9uY3Od dH3HSUbbk3mfHxQK176tZs1iL/s7G7rrv3WvLSyX1muqmAT+aAwMgw4to+nnrgc0mJFQVF8nnjff 0Sa8FjZciTaqga6n5VBlzERbG+o4YaqtaIrwZGvd5S42ZPkPVb9QK27Nl4m3UHcDxU6Gh7tzCHI3 V0S/CSQ8ecBgIfyN8gu2JgNd1rjKq5yLiUFf1G1Sc+hDDQj2AyMuQHR8FB2rdnwMreo5576ckgSU fXR+L8+fhqX7WIO2e2BF3BpthIlmSbLOI88ajhTX7dVgJL3upNU6vYk3wm+3qM+CC5A4CuQ55ylY DN1FwK/AiyuwgArpujF57/3YprWws6vAgnAxe1VQu59Unq7nApIj9rqYauN7yVrY325SBDnlUki+ 6E1jcHfy8kBylNI30h1o51Vpa+q3PdEfOPuH9Zn1LY049JXAVXsY/YZcBBh5/Ofi4lFGhDogcaWN kNLHcpXo7puwbLXEnnuJZbJaLlP6znXq2vZ2nB+QUaUSHMRtmSSHboH7udIudkIVX1ZTa4S+zN5l FIWDdwoHDmNXcWJHOljta8lLQIJOQ5lP9LV/+9+D6ET4bz6pHs7u0o7862bJ8CP5U3Te4uZXQfWg S4i+d713rMvVeZ0sg4pLfI1CT6raGKfFlTkhhcoSq5Rc46vx8V0Es4xwokP0lPIWZAc4Nj3cqf0n AArsGjP154WkijhHn/Eo2xGIRE6CrL1v0EYe0t0Laq4o1KvAlswIl0AIsdN2MTOmWHX/Gws/ibO8 NC5O2uewlvVCZmFTcJTiGi9BkLQYeQ+zfnqTxx/A17mfg2iDjQVlyWJcKF3RP3woxlM+v5ny0kxW Usbu35vgr9tL/cpRJGtdn5qlWS4f800szS9EV6HZA7bZ2n+s6lfUqXyJ21D0m8ZWp9AQEuU702UM zBcqcBh8wVOJwi6kFJW92G7Q9DKJAcv2lobApgLV7SISHr/NQJ8iMxHh0g0rm4tY56QbHgP5HBiy DcvSXJS1M34RzIJ8CMLlFLJh/tEbbK5mvBMY2a37GZs90vbmvuq2mfIQTD2O3htj9phqsWLomKD8 D+ZH/QpQ4lmglturKbuU2iiJaVIgn8AdFXK91/PZwjoqV/05lJrgmtnGZZV6cpGVsek73EfeosTF maR8BFzOz2JQ/V26oEOML/DMa+hUt0poA0Jjy2gtzmoX/WY7Tgpin1vO81nX9KXw+HAulRzWVInx +C3hghW/4et05wJFlz0WIzSP45OnRLwsJ0Jg03kgLpte2s3dJkgrfzDfehNhCzBD/ehpOJTe6Iae 3af1/wu5EhZNdks9fEppzZBxbEFA41fSLCp6cAjeNtpspoOzflzJVDehM/QY0zS2dJPNX3ikiN8W wTcryqVl7A2oxFIbmyJLngeyiQ3xEkRc8or8xykgYq4T0BntX68smm113P56FyouR/XQAhTfS5cm 2luDRcWOUO1Hcs0UEvTT6P3WG/mZ8sA6eoYYaAjs4SndJnX2yarjzKbXf46EAqxJL1PK3YJI4Rc+ 7O503HppVgSQBHgZwhDMXJ+4R1l9Z2eWhpkuQCkd2xf0RMH9PP3uScCfenqFCeFKaZtgp+1zPIcb 4vDOFpOlMX2XhsO7Lyj6N7NotM6WQyB547i0pIlAYPHNAhtPsApLOcU7a2KWkLSdjk+SpyoOrUqD /xDI4hOk8Hqd0YsQuA1beqXQk7Yt+WPeSOkuWJCjSM3z9Tv/Q3lVQKi2D/I6aWF7pghl1/o9dRFd XVwtAU2s5Rf/gkwMfyKUN+deYyfsTPtfZWWhgkb8Qus4E5Lr0TPKqh8tSzNbqM2KQfnuYsQNdG7s 7xR/+YykXVVoynwBepRoiFqdjqPeWVjxRwh98mXXmsDycJKhZbMe/obxVcoVwFjKvVVAqDrIXXBi uplJNdLDpYNbwfNg8ZOpa583Mfv86tElrVPVvni1egA+aW1rnXzf3lm9LMB4FtM0Mhp0BfEshndo 8miHUSKyr2qVgWMLPkEQQrOObI5kH1t1qac4YtndBrOgSZah6pqnHDLQhfdI29Q/AqS9q4BBZDhW nPcDfUmnqdyP/rzgkA+HKPIxeGMzsLFuFUJQW3rRWKuXz3SZd4hZMsHgZoWPIV1ZwVZAcEQyjEOt ZdBovJTTuqGnz2zyaW3BpgvDb9HpJ6Q1LqVf8OYCxex3OL+bwEX8RcuyNRA9mpObCez0kOOrYouW 38eDQjLk6cMj9ps4SKJezn29kXr4jK19E/YF5t+LtD/W4P1zyRQygyv/exd9pCGKsFH5fUIGZ35W 8BWWgyMVXOsoAyLPAq68mioDKk5fAMTtUxQjjAmWbbABYc6czQ3u5nbEsX/FRsPKXItQolfODWev BfDxZ92xhFGKWJIhlesAqvy4Jycj0pBUWNgYuBjiw26U3NXbsl4mijbciyjM3GghJp9qUiOcUiXX iZtH10gMECJ9cM1WCLmUCzaiJJfLfSqRFT5k05MGlL8B5dhqybTxpf7ZMh2ybDXu4ohS4Gh39WrT kpjC8e10o3TClOhyKv9qqX5r2VO8634wvKfDjCyFKDNOxckqJG3Bzd3WxKESinhuI+l6kIQ2/ovq vA3e2R5GIDeTu0pE/vNV6xoHuuw8A3zt1rFetxI74JEWFEeDqV4+0csjD/fKkHV7rskUH7UXLAFg 5UKQVZYtrsLpnZ2QSl7QdVCqZQLCieFKtfF/ZXHyDU4GhDJlzaXEHgNCTsYQ6+ZnzT/Fw91YarZC sfpaie9hAgKugyoormbxuluE7IAN9MzFlhu+IqKPHMhE9B50MF5ozxVim6TCdVDKfxmBjVrE61qs 1vIhH15PgeMPi5OlU3ogFHItot1CJFiZEO3lUHx04tLLRoCPbQkC2tjXxWXmexojLe19DzNG16RT rI++UlD2TjcAtiA8j1Fcg/d7nUXjo+N/epvkWPuwmSS3J2tJm6ZqWB8eRj7Hl1NexZGe4JsLXSrA 29zlDsV0NsDEPRDsmcN2PUde3uReKYUMEUUB8Otq+zkyh+p92so2OkSAX1FIWHk/UnuwL+yxzXcE BpVqAEkmVYNG4jFzgEA6EVr0c5BICStrG7Fl/ME7iqE1RM6Qj4IvM5etyXQRBu2ZbAlixpR5EkNM 26keDSiIcgGaHttIhY6wB3SqjGZly+i0RzQyeTRRAPjFW2+JPCdneYH+WutsUKPpxn9PAxcPaIRz mZNUcu8cJ7B5dH4KAdjkV6r5a43hmhoHaOxDpKSH99sdsBBSOwCMcZkGLRlcg5PDNKb5W4o+kHXP jaZvc0w+leX4cfJEUkAIkob6STgVinFGYVDQrcGLlLOrWiacKrkl5qlFffEmNKdaTvrj4CWxC7nv cr9k+4mPc0Vg2adfoVH1Byk0f0CPIjMKgzqVs6zkw0I4mVD7fz6Fgo/z+hd/88iXTmxWvw+u1NrQ KWhu6KtSxMHEC9fdR+qo9e0yeeBW7pUhbbxhllWBL3aRbHOgTs6Ynji+ubCYqavHtti1YKqJGOA5 OiGEJ6+EuZ9btI1102d7hkpr1fXcEwiE57Mco7i3FaeXG3gc3vmSw8TFCNvewfuvqLMmEzMgDt5q R9o+A4OCwYuU3loXziey6V/f7Jc6xwCcfiK4ujXlGjkPtOCxBuouFlm+sWpUfwEPuWhiSpFPXfZk 0yATseOs34kMkui4wJqBhroBpMYglPx/vBRr4sRik7VPCWNqZLMYeju9KGNO2h8hrJGxOjjar0hR SglAJrw8CDCGwaL09n0hvjPkdOTR9qPR6t9F00CcepFzQGPNGULv9q0HE1cYCo9TS+HDo+r7DMW/ sJrgXFAwTayYxpRDsrz09dGGZbA7vgYj7wV1WfQdAO5ZJHcyxduI1EXBWiMYu5lY0ZCuJla8CIh6 d/1SZFfuArlP5dbWkMetQFPzsjBjSBdxC9do415t5R9OR8/kIzf3I/Xxl/MqWba6C8LRqlKpb/Aj eo1pePKuksh9Q+VnASLroRa4Vp4CCuhNWHbtyyEet9HZpPksPjepc/JjIVvPeQQas1SHmts6ZeAK EccZHVHxHy5FZ2C7AqOIc/oEQbWut8dGxpwH6kyTgFdYKKNakekDqYqFFrsKxlsCHWGSFw9HSIzl MFeMdO9/bRI/f/CCH8IdXh6ZFrjyb7OCuH+S+f5uMxSTV6QOwsRf9iBWowmJUj4KJBuLXgMa2rgM HNLkiTsLBvynRcwb1rLvJNWWA/JcvV/wKdEHwwiDORas0Ux8RxO+8+2y3k32XM58+vwJl7e8dB9Y hrCNMI9O0cHeLrJl7zP2RLCZkXO1s3pShur6XRpxl39e7j6cYvikKFK/hXsDSGBf2qkZbW8FEf89 aJfoSPYWtbjGx8EKiPl6mCgp2F4m8Po9rPnsvswMloPNshQUGzlC7Jv0ou0cnpUzgcTp2Gaa8nRM YiPOlMFtnZuLF3zoasodRi8FN+3RI6L1RlSaO11PTPMVxQhVVy4crkfYK7JxdwrfgflB4jzcOQKg jQSNQyaZYaveuNcYwTajiYGAjVPEmXJ+iT+wLIwcAl0mICyM5opiQtYEMV7upjHmS6G0/9pHDo3p OY4ypGZN607EAz5Pi83VveQjbJ+GvHTle6ju2yKs096tn57GyiPnu5BzzmO5ZjE3L9mW83RGBhSK V7KUVChRM5nPyMAhc8jpNagfSpRtbQ/PdnuUTE0q7HxNrTv0MYAiJzt73ppU3dUWjK5SlZCInL8L BskEjonN+s8KTCWbZgH96VGevfb0xDq/thxeBEHaBSfQIqh76x5BQPRblErWVn5kBEPvDuUSKGr7 Vd/oVRsrBl5zLm/yj5OwHD9r2DYKv/MzUQA2gMcRUV5Us5+nGlOVJs/5GtRIkvTr13ReiDDxy9du jSQ5EKQ6pCi96khxc+LU5NpHzRBVwOnSVjX0uPuNjvP/aqM9jWZ3nufifDM/36uj6WNeEEmYFtZm gfPhX2JA/zIpGqU1COSTfgikB/xGffZfBy6Qmyu0xi9ayC2kBsAOe6ZNQKUD1zoUtYGTyIvEdDiQ aNPcgI0wNRPfWGKBOdj4YU7R1DT7uNTVesNYghn5Q32rPKWIaKq7eLRG6Aku9Qtl/Ped2xfzJbHY uY8U5W4+xt7/3NrLFacWbH1+hecthjwvvTR5bRPMZGGPRCMtmLFD4KhF3yxRcpbJLo0ehum0H/Ar Ipnd2YdCjeUFgR19qRCkIQ7DefntxWZb3KtNwum6HKYT8e66heaRqm3zk7TgMl7zBgrRaCXT4AFp eWt/bt3MVlMYXRqLXPSCRzW/wvbRtB9IcW6GnNBKYiHrL/FyNzinULrLvtT6h//R6wShJznPLSLR pVnAxJ002dWD2/Lilb+cIlzot29CQkj/5vHuBrGIzD6w7YM7WeFP73d6Bwbv5wNctPF4CUv4u+7f Q/gLTI/LhBEUqtjL496Vczvm4nnS1awwkWPlI+xG5B+5Szw2zx8LbvZJUvv5AKb+JS3qjwY+kDNT 9kCL1EyXrI72jXQq7fvq1lPz5tnm7ITglpv2TJBjRx9l169f0/N5Ufc2Kccs96SJx251sM60eJ+x l1lqSQc5oOODny9LfrHZgGnSMlVda7/Ww4wURzvV98CzImQOXUJMbPm5gnDsHfTxLHsg726Bz84Y UlojlUMhblB7DBl55vryDG1jW8rN+kYr8Z6cd8MtVnKKKAYRV6VNaUOU61jKMDBQtN5NOA6iXWYC 85O3pGR+wwY8RJGZR9jpFOGzrnqp48S+Enbva06xEN+fgJM/V8tAsYzb/G+nocMhwD74Z13BNN+A 7uZdCUaMug6hKyo985jXpaygOPKlZAo4kFLkjAEC4FDmtq9jv5Nuo7yJQQIsd3+pfNaxsUyZTOQ/ QbNw7v94jqbnd/ObSJuVtIX5x4fdvD/gFWijSL8QA4SZu86bCgkX+p8zGPsVmnkJdwnU0BSn3/m/ AjsHy+8Gouu8ER7qfGZjOcIjt/8INwfKkmjWCKAMn01OoP6W/lau8v1yw3czjLBiFbYpFU/GhJAa W2AJn05b+UljsO8lYuhwSFGr+/zg7WdLW2j1EO4PB535Wqel9jFS/nXuUH2sHPc9UNdRLpTPK69Y yWSH9Tvv3XyQBWPo6NFmaRpNPqqVfhfQs0I/JJP2oD9g0BTmYa+4C+WWl2zo92PVD2ijqpE7gBMq z+au1ZVVkcw3Dbg8hr5U7d3zvhSY8wWW3TE7+Qx56uKr03UP309IcrrCPphTGr9TN35Jq9WLszGn HHD37hO0CRbiBSIAywbDKg80V7cuS6dvN+udrKt3L1LY0Ld1ANHi6sSqRvC6Np/yxMdZ9iKdvFRn uPYvS4tmbKVdJCzr/9DhCPPy7xy4LFYpJuvrC+uj7ggHhQhWECadGSGT59s3kruLrEVOVa4DKbrI b0pzKAazUViunPt5HwhDP5DRyPdILILLHXXWleHib0zRwHWOZTqnRfZwkL4b7IuiP6lBSEKIG3Xa 63B3WJfHdEaeU9+ynYr30vcZja5IggSqlB9oTcPdQPwr4V7wv4M/S5Z+JTvyaSUn7/0K6Ig02Dii lEhXGszyJ+WrTcwgPMAXO8PIodNp1kOiSbY0cUADdbcmHl4u1Th20t4Um7jdKGVEv7mZYqPdfr+p PYVKu0Up+cWTlXfFKOKONlvce9Rc/HfPJQwfhcGCaxKv9qe/J0AMfD2YalsT4eY6YRVbq7UQruwp hRQ1VgJVsxXbZqVoeZHb+DL/BJ7hvMVHqKbNfFH217zTCNsJy3seE6C05WSjgKltWgihhTWqMp1/ PYdfesm4ZzTVDYmI/AoTua+ikrpXTwaM+Wi7VtcpS56lEsbJ5uexZuJgO8HFUSbdq3hPoVrMu+bM AcaSoSDC1WCFI95ugHET5XQYd3llsnUmDwrvMaHVJ7tY0h8bYVO0QKv9D1e8YJz5WUiYoRHJJZq5 5Y8EdQIT+YpX7uEyylCbGfiWNwvxHz01Y8c8YUSuvMeq26XfH18qMHJMD9sSvSNNUrHDx0tbpEDI brMaqxScIDL5RNc+uzvFnnrr6yelTiSPLt3N6V0XkZKDXrGulrjUPmMAIp/IACJlO1fqUZ7dOPSp iEfKF3jRfBCFudXHYl8MJmJxmJa/lPi2+3KirS/GAHyIxm5yrUQidd0F7kjaM2qdbhcyFidf8GwJ 5LD1VsW8caZtyC/uAA/ReARWS6j9AMEMgNVw6GCpB095qDcigTdpxbLAu6Yy21Jpc7oTGgJmz6Bh wlXrCrP1rU3aQxyzZZJvQJEkoIIa9MyosUIUHowyOl6C+LWLWv0ELxNSwLaE+lmlIgnijvLnyR5E LRYW6a0ewSFjQ3IyZuQlMsNn5S9MfclS8d6eYom9995TSNCRnKe8QEA/LS62lduFb2+aWB3RC7xy XUqXBTCa/swpZZ3LVwBL97xASdH81KGdhx4PeC6WjvvnDDIAFnt2ydQ9GpPFw03YWMkqIDrOIaF1 SF2bQXrxYHgoPVY62Xom6R+8AHgBCyXcGDA4ElEhL4irEJH1P+iIv/ZW4IQk9EbglgrqcqIwaemm 0DJM30FAPnNVdG29H+FlWEOEVToNCIa7P6w0vfWWk0Wr8upGRTwwxIjq4b6zWIQYOrIsBkLbtC/+ kaWORDU84fcTAzz94QhOdZSlwfDDImanLKqs0ZsSmYQrD4r6pfFdG8BKTax0yuci9g9tMJ8jxAdW e4eRYoeNb0Ghp7ZdWtFRX46SJeDmpzUA7rMPS4EbCigizNUKJ5Np0ekupFKxCDU6EY3TG4dC+4pj W12XDuNfXeyyUMqFRCxAQpv9+FpeLygZZlRHY5L0PQOh5bDGlpcFlCgnNClQtgznu2vym4HuIm/I j9a2SOV2d5QdsTBReCbF6VOblN9SBiJk+T4nA0iMXiGkCgD9Y0KrOYiJSRH/7FFjtFZRYH3HRwAK 877Zy9Q7OytcKP24KL4ZvyEFRtQbnogkuJdGHPz4sSPW/vU5wM8bfya9yMJpyAYGMmUg5tIvdXX6 gfQyHKRUmoL3R+2D4o+rJcu4qPWJkXMcf56mCEuv6ALp+d+E3U9a2BY/zjcf2zYQkD23qjjBCbs0 nWvdEB4txrjeaV+XYYHI9IgwOvEwY7KCLDNXLeYZB28RacBzLHWP+u33BBfeTksQP5dIbr3sjql+ Pw4X/EBlMrCF4TIhwKokKZfRLCrrNSe9SeOsCHVa20FmNv7rJore0Z9w8J+3cJKa97AZ2xzNSxv7 3qoWQNi9njtjUkeYqYR5BzVT7I6HeHwvqzhYE/6peQodRI9Q1kG+BSPm5Mk4pOAm9BtdjhGxCcOY mlbVTkbcnY58vCi0IU+nhP2i3fANSSMkAnBYdydFqYV/O16GBBy0Uc8eFO/IcZledfRdkEBLEfFY Nf0HFk5G3VgV96Aox1ED4y1d8Z87Kb+R7hU6NkTe4NwE72t3/fFFoUBOxBB7VRXA/8ka3KpL7ALD QsQ9x1wkst7Bbsiwd1G1DKvAIhLDOUyW6zny/+TEarcZT3byIo8uShw4nFz1KJS3czhTMWWWaj9L i/YxiSZRtJz2DWJ7Pj9qq3/jRVoZG7IvqNjWNE0FRcSJaWAngQba24g8jflZLW+sp3hEMpex8oxL zDwi+gDFt9eExcjZ3mN1O0i+TmKwwtaCTojJeq5bPyjO3K9144cbQ76FmcQYGl/BdCr4XBLLhzON nUsHrK3YhHLEnsoDY0fibHVf6IjCh3IT+xJTe8osZD4Lay+/3KjvtJe58DYCLYHxBLFKZ5YVxEku 7mkRJS6ZzyRq1NXBGH35LF5PD7C3zgQVdWsBvorLDWDPKFZw8wwQTc8aUutVCrP5mQjqvdLqGmbl ts5WeCBzmBGSXl8C/MHNHlJuE+T7qIUYt6+xN7WfeMfhpX5R8aBXr2qrmYrDDs2ShtEpsk0y/ZeI xNt1PFNvBiCtSKxvwD10sqLCouunugIF4+80m2yKbJlMmpPxICffXHwmt6Rho1s/bQOBZa0nUs6w FfR88Et67MQqRA0C8jioQ0lOt9+LzzmsnI5AUeDikRWiQv8ohf6PP0p/WK3twms321PAMBlJaWuU UsT2rPjZWfIen2wg6vdL6ZwXKlI+EZxxAm9kI+5HOQ31M0a9Eom1Q8APS/yM5qZfIS9LP3ArVOBY eKa7SIOcJ8sfa1mehIFCsnl/sVBVNcCPHoaj/M8263g++r6KalGh/tPr6YoNhXS4rAJ0lHHbqDnB rAbye0hCB1zqfUzVcFzx6MI9BNPcsmju40k38fO6JoiQn5WlVOzHvpeNb+iKAqAe+teLYAQNQH5W hyCgIV+Yh1kugtfQgxzDSDx6rz0ov53OZ/xR+sMV8PKDko2WSNRn6QeyfYO/UrZ9+k/1N8T3iDJj /FDeWxuwI4zuEQ4DG9xbkM0x2xo0YZoFzXKcoCF+v/g9hSi5f6tvzcUhAM2wL+ydwG8nsBdZgy7a bnTzhy9rzq0AslumRDYwty0Kyps8gjSlcyXwWnqhDyqfi2ngROn4hKdhWijbJhAuV/L4JVK2rue7 N53m6gMJzugjgftr9yZSa+IHwUtImH5C2M6NZWY2YRUlVbP7W7w+avhpLdxDbS/vIveSmPkzuPr+ BmfPIe3z6jNziCxKeU7bd8VPWT4I8UDRpBZa2lFdeFrAPAZsXBihVQ3yZ240vPEWFdzkWytir2E+ fmN0mYF03+S5G7+FKOZSEGMpSClF4EYYJaJE82OHOcz1s0MwjZeCCtBlQwK9YvZxgKcJbXeATp/O OEf3U0VafhNUZsv3b+p8tf4r0srZ/LGhvgOhiO5ynEbeIHxCC/YFQuVgWP0IM76jlEo+Dij1xQDl 8QmpV8TLlbkg+mhxa1GvbbXpPmew7iZJpNGZ3Yzw1x0iRK3n96106yJUwdGNMj1DFo1oneE/qsLI MF3fQvmtbctzNjc5JRobcftPyg/HxK94lC7Vf9L6hYBljmJ41ad/zHktB65JmU1TzR/Z+U2/L83k IPX3H0gi541PZh1lfOFjNGsou4b6PubTXOJUPg7Vht+VBMk8zAetfVPETac+B+CAKqL05AZW5Ik6 i4JvL7nJ7hmD6J/Gg+Z2RJx31FjW8xYK6U31t/7u4hKMRBoKxLDAxrLPvpxlxf1FH2GbR2FaRIJc EYuQ7Ga+El1aQvqd3N9owdomAzgCypvRyCvofZuHW8cbZE/GUr4sG7E0BZR+eXmb8bn7dYgxd6BV GmTPdnTUQdPGbgmN9YBs4O/BAb4uXnXUXtHm/+DdDaoST3aoUkl2Wb8mjlvDBu8IbgaYWk9MibkX hXE5/oq+NpbtL4UQD1bqr0iHFt/mGQ20exerjQ4wpStw++L28wWdhahmLxm6u0l3CR6jDLUOffhM Be1nXvypoH/6FYX2cd9wzOcLejzNVXroj9KVwDxjCZ8oY28gK+zCYzHzTa3jYNT+0b1reipIvFG0 QawzYhrqpAdJr1EsLxbXhHH9HwVjbO8jeNI8rpWsqBRwO+Usunur+rHBeAyYBk1Sup5rfL+hWeDS LRhVB8uHzATQ+BAFwPEOdlyW16XV98hkjoXMSEJN3J+SfMfCQYEIX6uHbE3MSO/lCfF1nJaaK9wh +PmAP5dY2BOALUjsJtiO+0jBL+ss8Ho004O/GE0tXmHEVScdvJ2fjoLRpCuZIMbl7kZoCO6hnNEO WsApZZCm9sFSj9y1UrbPyUX87lPvANnFSxBMAm9pDAiN85934Z/78nxd38cBF5hnsSbtz0KPAa6S +c+5DS2mzHlLxLqNWFlj33br1xD0eqXKg/fU5/NoDTF3WDB6hlUmRcVLLNSCH5Iy+lmLon0cfjTw PQRK1MBRnvxBFYMXX7Cnt8VLEK0mgcqgZZzNJYwo0NcsIyIKb4ZD4mpybf7m7CaFPPUEwKUmMkDH 8VUwR37PdOUtYxxYXDaLkiRTe8tesJhnIYvVNwUzXXNcIs0ruw5xtjEEZdfEaZG7AmcHQ0Jsbvor RGkhObSTev71OcDUSUsuVw48mSykIpd4XXlUGbeQvMrP/BqHDcjbioEXaIOZxf2ar1LDS1zjIGfP MyqENIa54DaE7tdtyZV70b/50PMkfbMRvCOZRDMAmMS3A3B/0VQRhIN7UdeLhIzezHX9Nc7daLpB R80aGyvdBlWXQNIBkGYH3gOp7Jfm7/QxGgQcC/sbUamj6B6Xt9i+gS4DTwAyzY9tjFwSwnBZW89z PFUH7n5QotPDNWMmCdxS6KkiPsOGVfmELJGkKF7nrXfRWHes7WneKhQRtiwj4md2vQVTgSLDc0eD mA5Nh/WDzzehS73WrjbXYLsVZQVWZi7FsenoUOiYTx3qSNoqXbBSQI6DmRpjHVdTztsPuFcisEgo J7HxQVEG1t0kd6oA9W0hrZ0rxliYb8N+0A9b33m7CANUJxuUaSbUdbiyYKcPBcGVmRzL1r+JMaj2 vYeQ/y/eaBDZwILtuGTWNPuuCD1xlD4VwroXECXO4OzJ7lRPegfH4HCuMKlzzqYAkD7gMy0nMAXD 9pUUFQNURg2S+gfQJJ+2WFte/B9xPIbHTPP+ZHU1G5HRP1MmZdDF/spfvxium8wz2HQsV7hPN6XD TH++jgtZl0oHAyfqu94+sBxYYGEggydp5FaOkM3gSOuK2fzYLNf+t2HhKt1f1Um1bi5093fue7fQ GO53yXj3+90Cv44tTWSJ9MED6rtkyJpa0i9nLFOs6i1TkbIdZFDuJb1u0VMyJliMK25c0nPjxupq P03jNcn/c7HIFWDbx+E3pQabpi3X04f3qmpb3f9UHj4+uzM8iZFmPI5PVH9ICRjLebXqYCVO5uSE V0F4d66n0xDB8d59E5LwYrj+sjoqZ4/GMYnXWGXyu4DrNElzR9ibABO3t6+TKAGeu7RsZ1ByyXHc OiQj+4rG0bQn/+FGjmWZjthhz65+GV4jBxe58RbR4lT/1FmuXiNrCHjy1q1yVgJDTzYzHFftS4Gg +E1CJVbAYeSZMbf6eg0zCbznjGzTkZk7Q22hcEimfPwAXrf5hADoSuvGijJPLIEwDais8cX9uS1+ bOQIxef+Eb1tyd88t1jCTvqI2fHetjfqtIC1cAwPWNNamdvRtNtvG20G3bupme4/dFXEdXRTpE7b aShSx5Bv1FNxjYMnzsQ7C2OpdGQG39wifyR80mgi5JD4rpE82m8EVAKhP4l+n/YnCZ4wdLg3I+Qb ipuFwzDofbGOCstKIBeXtZz8EusE4JBLV8gf2781tFXJQNUEzD8eOq5CK+fAHF+l/LkgfEgVLpWw Vfn13ZNblZtD7wEJtja5rrv4/Nx9/Hf2kYSL++dxNfqBB53Yuef6LbBnMb83PFUh+qYEliOy+5tv 66TZYp2I0WAVKlx1CqunW7VxClptFW/S1gZ5jFSCcBDwpmB1a4omlblZa0yUbx951mtPtpTRorMp iSFtB2DjWO+XVUtxqKv7Rv061qIyF3P5+wA/B3BphKe7b8ZI184P96yIuoFLbZR6xDUko4ifJqCw r9UjBWAIC0Id5dRBbTA0HkRnWphfbr8WNyP6HiNUtVztJzPw4vIr25CU4dmghVDoeXx//l0ZCfRv j10jlfJL1gZMhO7ext9bSX7CN+qOpEhyXEpmns4qIwGME1chN5utw1vR03eLiYKSwNFeHehDdIxc WehCG3jUKiAAgmgUHShEIbKJLOPd6NYOfBjU9No9Ma2XSD7yRs9iCwV+7d/OE84nUea7rRe9kNJm bFodJMq9zVsVnAxe2h1DLouTKqhii8HkpQ9uZUpmONR5RsmarTs47FqZm3aXspM3vVyivPX+UlCT ii+cYuxEKwQOduWhu6h/2s63xeJc2sBGyQxKqfS3G/gbrOCjfBXArG07G4BG/W1t5SYY+PDy0WXo EGohr0Z13xFEcgEoL2FCoYQ7EzGPn2siRsWV46KwEVqiwcMHq11RbvjZwcukxi34bxEkP+IJYJzd XpsPIHuORK3dfdN9Pz9JozUGW2hakT5NOa7TvTGu3wwzSuEzUVdp5vNXXjmn+WEigUNdfTlnjVq5 1zHWIANT1BiD810Jzs2sJKbkiXrugnjpOaKTtU+SziHD88H62fCMDmNXcJP0ZUC3KOmyn4uMPz1H p/TmOvxv8XnNLQym0zwBgTDDzi2LIhzK15erh623i4VfPgrKM+I98IX+X0/YGlfFwFuz5UbJK5kS kVH17tIpZ1OAmxY5oN2jVUFB0IYwuRZ2fItxnUb9ktmrU+9cUAkS1DzL+b/ABgveA6ze2prLh818 eZzcP15mvBwKOSfUgimTp3VvKwEXbX1bhoGg31S5JepJUL/2QQpkh78B4SAMPtusGuJTpW89jpF8 xei4tMUM3qfayjNgSOfWb7Qypt9Xp9zAaHa6BYZbXrxclM1G5SROFbCB7ZWeh8roZ5DOXulym+Ra fYkG3g1EHftPtYM09+MnN2dSUeNXDnIbIvRqrDUCFdKQIUkl+35gugCIgnZviuH6yolcO6o+HcL2 M0Xr0FfREPB1gvpyBbqL/UQYfBphzO9ZCennWrrZPlgtSVJvOYAlSfe7lr46EksGWylOFbvnKBOh E7BBqcc6rAAdyoijSESaWkdTcqvxZ2YedZetqzL7AT/z8wZQoJ/TRObtqHohWXLH0x4jn8yYN4zD LkSdgFsSZcDWHSk6FR93TlNCcAY0mjn2XIhplIKZPyo1hgR/V7y898sf+bSysqs0JILBEq0sp8sb azjVRfGyxUBHNwf1j9mzRofVQ4S3TTtP3UO6N5PNjZxgQEpJcR1Iqgfb0x6GIHqIE0Ss9P6wgCvy hr6w9ufM9KYhVc/6H1gyF15Kz04ULGfXjJmxkucrF0OAegdAAaJcukHq1cBeLccY5souVGiTpRV6 vyW1yJjXDJSExVL3P47IYNE3ihmpG6x3YE3XxaTvNi7Ubcirpa5UeiMl8LA+29NWMDNOOZjo/DvZ zUccSskz8XJmkA7z9prCZIWfcLqc8/HXvMifdvGwULMNalcQyqVQBEYKJrMF8uB3N/36TUFK3HHx PS8BH96x7qMDl+eGcEtq6JkXg6luY8fE31h3m2YfoA1pdHhfh9Qai42UVK0Ui8zqTqz8asVRwISW 0LY1ogGFqjKSLpaSYh9Xl1XrNPe1euzFVjHrW3bEdkInrigPZ0RoIej2mN7xuLdomj/EpB/h/T+L +vI69wt3aNvBp+CwF4C/afgTao0EqQXME1+B+iS8zqJTTYLwI/QP10J0cOaLLWIHwMuR5dS4NepU BjxcxEKfx5Q6s8xuj9vlKL8kdHIAklGWM0/c9XPbfTFpDmfENmM17acbPs6sy1sFCFs1RHNzAwOP xBOYqNhI7B+Wc5eSB2GwPFjreKD0fdTJe1e0g9pq/Qa44ENOB2vO8JfhlAcCZ8jbdpCOtYvz4vrO qHQOBx+7rBSHhXrdJfrLXiYMzaIvRax+BYgC0SH0LH4PKBUJt4MTWbE+owg1Q4fsLDFivxxq7ZzZ f4nTKCUsX2x76Otbh9seznheaejr8oXGB8Lybntt9VqIYTF/N20kd30Q4IqrHQ8o80EY6bRShRao t1WY2nCrqO9TomvBecCsAl4SFonYRCf/o19UBiVfYec1k/sNKRGLxoytZUbkNc8z3yZvXH63GS9Y 8yEkIHq6u/kr4HiAs7p4KUwwRVI6pwDxne1zHMNi59CAUzEkQa9sa7G+Fmem1aWLCqAj6lg7K14/ 6z5nF3+KOziTvzYdp8fabg9tso+x6Hj7/qI/U/7kFC//fOEyHEPYmxyRrluDJKsxCtvWoa4y0X1P PUDsPNLRzx2wrVvmNaUXcUUh6/Xtp8BdG6XwVuizNqKrd2B//dThGvXplgPIASxHWgohXkKzfBqw dchrjr6jR9F8mdoXgj881ozsNuauNSsyk7Ba38hEMu8LFUTvktwRsIrJUDD6NmBTa+8CTNubrKiS bxKAwFQYa5woI7VRbbDn3fwQOUBrG/X7+Jioz+HvgE4sDICHHOyOc860lyofKEd/XO16SfJkgiuv dzwROv01FcC1LSEyQma2K6VVBXHcgsLU9h37AwQoFKpXjia/xD3ofTo7/3OUnAVGDf8ppjcqvTrJ i9s8jgEX8wl1vA8gBAGX6EATaa9bafvLPA4AUCwj3L4RzdxnOkK2DQBmd0KbX3keqeUYDO6muwQc PH6AO0ufb/YvhulFd3j5lQ1yxSTx/pS5SKeg0lQ1aCd+Uj8Eb0Pc9Be1fUCvuKxeZbyr3c6o87K5 4CwFj5hrVMMWDvEm68K2kRkl/Igv6MbfvCHtzPdz9LL+ZIlo+ZJn3VKYaX8X0/2xsAIMJVRMvZeI +QvIpXSXitd8Y1EjwVvsL1w0HrX8BdppUJBONDtHGdH8LaXSGo9bseTTJnESjSliDwhTpiF1QLZc pETz6aCqF8fHuwOhVUrU+8vL8tq4UnOfVLDBk47K0uYmZgVbZE7ebdlrwikuk3QZj6M0wakkc+oH tUQg7ROxX9tRbMmk3qIYFqzCpmhlvPeV0NvoVfE8CnXyDxjDHoFZhxpfSk34I0nc0zPrIszgotN4 tB6yKHVejy/B7jlNe0GVIR3Vo9VWG1ubvq/z6uqZcVc0C2N6LBGCmBdBDmjooN2AMn5vIoYxYa5G B0/oBUDAVKAQ8UvLBIFuGT33eq2QZxhkEviOArlnTE+eIqStv2jQrwoXJIu43evKnrd4MS5GDovU MMLdxj1ORxxorT1n+IWXkDo5fCHtiyuY2ZlbxFJJnVuIQw43diDlGWqI0vHHNxDGcizy21YQUlaD dDZKHDz2thGE11FehkUiEoh8kXEIblW20SLSOIMMpXE1yT5ydtzVa1dQClo95/IIrwARwoHjiDks ViawZqh98Q5LR1gLlxorhBC46QdsJf67gkx4dubGHftdTCSmpRB1uM0On4Ihvho/D8jL9UJEuuIG p/AfPCNXM8gUmQJNWmaaLmRWwW4S4prfTrnUcuqCmr6S7kUnaRkzLOhAXG4+0ov+4zvH7Y0gMeUI Z1CpOXfHliXI3ng0CK4gQLwrtNblVan4klRCuYGNrH8sl0NcM6/VH/qzFiCSM9Vd1C5sRrXioKaq M97TjeE9CchXaaLaI2S3yB4R7DjBLSwsnZwmJ915SyG9LatCaaxBn0QUzce6dCBkLlYgf2CXIprH JFtW7rUznMgmZ2tbbnT+jSqCdXdyzjS9uICGhk4gPECDMnwGQ6+a1kxZoN6zV3zkS/hqJNBJChWD MsnxbVMMFLh1g47JIP4AsECBG99fFhr523LzdVhFEI5jwXRcsytF+nGdaeocgZimV5jGeTA+DFtG HjJucWq+P8JXcaPHmHuGY4yuVDkpXARXWJQ54rINEebP3zXvoq/KxKpmR2f81aP9VSvQjR+2MvrU h+Tr8Y+rL0sM2qGWqVoBwlYwjV4SHfBvv+t3ogk6uP5XGrIfnHADjq8vocPowaux1d+e7HLFvtOv pIo88Sv7xAEVLt7Tdf1I8VJSdLQMsYAJ8lxI4V0UUdMd9hFCyxItmXpY65q99kJmR6VjXACJMFjt QfsGLT7Cq8vRyZNXGN0tTmJzqcBGJu82zx3BxKuxjO+8+BUWZnxOY/bVvvL0SW/pu9DulOXgbj45 VTKeTm0nXu/jFmQrnarXeI5KoZyZTBkFh17KA3dU6dgoiIz1FFI5FkRKJMKEZvkO9BwVTe7tnG8G 6UA00t3NvCuRJI5nRDASBeLbAbXjpbAbEw96HAmFYD8kilKUS7dkpMzRyr0de+fUB1jgmKao0I3j MFVXj5KxicJC9dIP9vmbCAHwiMbyt3MmzxMfdd8r3gm/SgV8wipx5kD6VOfstKb1n/g1Mcts0EIp ZiEzhoLFpLDTxbcFwOzIsHkhW3hTCtwWjHJ7xMNda1MenrGSBQe5ChWDmELoH7HZbWjwVE8PcSg0 VVYDCei1gzCvQw/2UGo3Cs2DVpXS3WVcJf1kzKhP55FCSXHLvBUK7/Tje+CXkz1r0rUjsgEEJysl V8O4Qbfp4xySjx/X9U52P/pJX15bmu9AI/gFNFeE56dXMYOJWxEMMUVMrNzKdWVQ5vEHwj4+sT1X 1Kne/OS85w9l587OFPQ3bFexVZswi4qWfqasjeVFbfQCaF77pFVCCGJACNxUFJuAxTPsqEM3JCI3 /uSo0A4wod9Vu+GL1X8gBt8+jlp3hO0nRKp5KkNflQAvTuWJKaZqFkFjmdNzCs5hoeZU3fSYodYt ghc5Wvu9jNxopyhLbwhRjCkTruIpKe4v9rIVDLQM2Lz4ds6FKFR8XC5lvul4X7jNVCyppQuY1CCU WAA3LEkIzhA8fAp3Z4iGX9uHT8+QLw5fRw+yrC6frfmalGP0kpJM7LmMKN/YHz1qLaXYdPEQ6UaK bKcXLVAD5qOJrSbl8R3eQ2MfH1Zf6UU8a4FsAAftU3WmMMLpQeLoDztmd/1ODa/qP/E92t2LMc58 DKQh681w3AR7Z3B53pcl0wV4/je51gOxtA4J8RWTdQaRHvGnNzLMn9Spe1CDQPeQQ6ES0hmrCEmc B5OwPest8gMRYFnXLj1zTmFqqz4w6zclDHEgywyEPReURYLuDlVK40xWCWqQP4y0VJFiT2/gHbP1 WXABv6BE9KbWGtyOq9fFipVccpp2Kb/BliSmTneKTS898cIRLAPn/xUVjABjhakoHMH34rDz1YNE NYjink33xhtuMDaGVq3Gx6QSgbWmP8FnYkwzEA9ih8GvH8Q4YhYG9V02tdT7EgSkzXLPgZlLwrOy i74Od5P54H469m0Q6UvQhwtTin/lmA+X74BomjAQOtlNM8CgtIUY4JmU2Z4yjZ8qS293FUS1RFaR hfe4uQqT9qrTGo7pxMm0rr1hTQGpUuERvL00Sl33YPnR9hqmIrvrmJwBNwnnQfaV6PBUYyLcOjRz /KL5+sEpbI+la0GR0ooXwmfpslF8Hp8cAa3nY+o+rMYouk5N7a33lA3h6anjb75JxvP9TxpzFR3D hDUGun1p4jM0BYWGbYvw8jbvDYIHkrAi2V0lqpA+x2QqolkyhxVi3CnHMOWB8Vau/LtVf5lH4JA9 QvX2pked0itbZeYQ+OlVDNMlvp3tfhWXa8XfOrobdaiLsUHmBipPp1LzcuqtU2zAmG1n59Nr/+XO aue4KlIsDbopte2I4iIi87zCT8oRXKMvhLVr4l64Fd9fX8jnuZ4KCJz01RD1iqJmPcKh7stUy5Ho IlhULiRmB7ONduOd988EtUqvvmwYvjgmG+w8TaeHFT+UqCgyP/Eed4g6zlabvTKhCxvCBK1ymu1g xlPyCKgJuQBKBUx/eS4NBt5BNB9joYTgkRwfGFp0PoLSoV8dOtSpFH1rOzn363Jo5kI8n+DNok3C RXUERNI0wyuHuuEi36jQeryBwQu+WDsmctx7uqAYxelNJSoj4CcIAgKsLZjzqKsGftIGqkSaxQ33 VONetDZyfMBB2MgeNmcE2ffUn0V7tovWCSFh34scxMOzjxpLOvoRuzGgA597t00unzV9yA7wgv6P NJUtWeA7LQtdT9anMVHLTqEhLZMkG+/F9i73/gyxe1lvYDohu/rvLcAgdjhXavD82ml9IM6AXw8r KPosTdyVuUH6YPxszvwbOiecDiFyjouGURPGyiogSrIYXPUZBeIzFiu09Fh6o2q8GCl2kxOHmoSd c6MrkPeOr1rJbg616E0EQsTYNES/XYNeon3Frv9qo7n6B6iGcVn01Y/q4DKKJ1oq9Ufh4y5eTf8U OgTEwIrOZ4WfBuYKfU6I//a82sM0ACXtClLWmhOxEO61QlQnzY2D2hrQ38fJ8N6WHi9g0njY7+Po ReOZgMoPkHgy9+Nk+mHgatIAqS1snPW90kzZyyiV5ARff2uCBUsVMVPA5oWAuaxp19uQLGWxB88f IA4DTeT5z0FAeTnqq2ol3E50i47TgZAURM6T6oyHA7QtCF5CjDuwxAiw5wjDETovgF8W19r0Mtf7 mPk5tECJDjgOCtV27Pnic3TxHSgQzofLgGCDMCqUgdJxSz1JlEQvprmvAfzNXvN6cMHzp4KzjzBG vPLjKtQoPFz+pfr1HsZY7UJQFMIyY0HKovP+NmT4dBwW9uY2Vz7JZPbIFxcydWqVIE3YuniQrRNh L1t6ltiiHkQXLj8UpHLA7FfSWxReIxqC4kP8HlCFIvNA2weUYwCq/Qhlt8yLPTXIMsI/InFcS2gv p5Bvu5MgoT04uz9m9d8aDC4CIgM5Xs1r+/7UC7/tSE/zO5T+grevkr4ISdNL/9Wz5z4KeNUxIIHd /Dgqz4xdZz+xR5U8bdH07jPwRPYFIEK25EMFbuBcnW2kcUWQdfExPiL2UKvIBNWwGlxZdzpsylgo jSRFRLD3AvdN2nrGYxssSJzY0NDMbRyBFLRVkDaDvzku5s8MoIU+ZrHWO+4+ANavk/Agp/nYyh9e AeHPaRhDscpRruPiEEQlsaTho26VZwlvFETU82siArGc5T3RmSDDGIzDWAxwLs1JjRAWNHwVXfv/ 510g+RlF50LDq/MKehgxLu91q1fk4HWe0FTkBi9t7YRzMeKHNp26okY4OeA2TDZwMCOXsJz529h1 hnWH/n6VlzeS7CVjWgddV/ECerEfZS+8FKP6l+LAPQV4urhmh4Cx3/8XjO072qIw5nWuio9jahDT 7YKLNvV3UZdSFUQle/MAX8U84un04+JGlu3WcifBQSg6zLnKaxTAwGeZLP2+lM0PBrSknHhKGpEE D0aTUgVfBn9Cj7PyiVddTF8vv4xuJb+23/Tm4UZQA3npdS3Fh2wrg368MQCea55LW4866QVkBJ44 B61EPD5cAXcPq/ciIyu+thGR/kHXcq2nnGEV7HOZ7f3taUfRYHeYMDOaoWh5mvP8wJK7tN59uBio qvwq3+/1yt5AiC7utCKXHg9wT1FhWK08RD34lrSt/UIHZnP+6OyXU2NSxX8PDBBkoc31Ar2E2s8r j5Y/JoE8RzTdmw0mlRjnOyRsUYGCjs4x36aVwd7sx9A3OBcqNHqFLoj2XMttYOE80Cop/LEL0Yaj /EB0QChzJMkGYVsRxv5Ri1uopEdG/HzdbpXq1D5605fc5EMLXqiXTORzL1IZHJ1KDwPcqBZv+5fO sfQ7YD+lRE/m89GTHH7QfCDnF7E4v2hrfCb93KaBIRSwoQit63ovV8fg1o4/6A7tNBwHsPI1QIXU WSe2wxxgRqzsJmDMfhZXaRGLiHNlaDf4rfTvXXxJijfpFm3q4zcJUqGG4RwkKvPCwu3Q8rXFGDQT qfOAyic+4w0QMLPTNiW3yl+OLn28P58nGUh8iarmzewl61PW7gKtTb9lC2C9s+EeIKx4A3twSt5k uKaVz6f06xfX0qMrrkU9ocF3OCk2YXqJzNyCkUBtLlJEM26RJsT8Q2+Apab4G3x3DT7FrZeWGTUw WFRMWdk80tlEMgoZPmjP7uR2Eq7R5p1q8LJ0rKhNnWs8EtdyxFvb/VnyqofLUPGjLrRNurrWLrnU H1cnh+CvgIJms0ykepfiSwj4GEN6Bpj9kDLN7h/8de8OhUgIbXmGjS3p2PMt97/SSBLqO5CnlAaL 2AfzOlmu03ubdAsqQAwPFCYRXTXdtyLewsvsbJu69E4MZWn8H6w008SxTVdL4PfxYPhW105ZXM0+ mY1XMEAw1mD1nrEIvPcUaqrKGw/j9FuzUju3X3hEUOoTFyQ84GLSTQ6wyY7EaPIRoDNsu68MoDej CHhC9wOkCnxK7eICuV9akH/Yxgvl1PiV3jqOBw2mbGW5E47bW226aJAjCvIajjvILCgTaAXyGAP9 F1zUXjfrM/RMHbLAzoGSq9cwxhNGYpdxlpxkRTpbqEI+H9aGfqP0NxHiL0eX0DZiDNT8rYRV6/e0 5lgerBGRzIylKAvJEiuQvB9hmY+W3e7ABwueRKHhbqD+RbMqUc6Fv1E3C1M9k1gKzkXcqGo9XOCa CAuEh36vVQFQT4N7LNxV8831H8dZsm9/XceHYJorEOo+h0Q1NgjQV9rzoKN4c7UViZghWK2EklBi f14XKsI8NGpCVmQUdXyDkCOJmBtxCabS+/hTmbX0ORVD/HdFovHUm+dQVRv5yiNB00kixMCxZfku JlHY7iVWXgQ3WgqrDJ31xVTsqIrK86uKnYUSvNgc0baTB4HEIVmupFluCbr1K7jM3BgpspBWC2Lj qmSo7fp15qsgk06ECCZByl62pbnVOKAFcRaOHw3LRDU/aGpizXrKlAjn/s5Jfx6yHhMkT3esMr4I 5zGRRHquCpfO/rGkX89Zcyt0ooEi0tFeHsQPLH5fSfN6Bu2nU14399RCXopPqj48uYk5No5J34mf RpphuwM6suYhugnPWNS3edDnLpGeH/BtoHv2A50/jTpc63AfydrT/jHznVA5Svxjf2dPcYMn6phG fFfDQFn012VYC8U8FbvramgJ+TRczuslyFG5WYYEIei15f0dgY+xCURieS/trFcYR10HJxk47rD4 q9QTuks25MnF4jXckx/9cLiSUU0vakam0DX7u6AMX02RJpWt+FS+JDxHaqX/kHAec6GczXmDAyAs Lm5232YKxlQ8ghEkRI1PCaO2YdVuF2mkpz11cp6y+D++lvRgV0mDWYitHRUcJF44QeWJaFqDcCOi 1OT6TWpXhbYS7AfzIY/8RdtbjfZO4G9YMMVXAKAUZnVTue30QjajAo4J7RtA5DBo7WueYv2e60QH 6Gx2BTiSaDQ1t7Ry96Yrc17xWGEE+YKkGf2304PHrKlKw88DhVZXuEz6CfnZoO2iZy2UoOxVYpCj 7+Hfb9MzbBBCm0ID/aYAa0UK8UT7R9dvILiVhah4TdOKSrPHaC949SiHehMmHh2KjaWjRmkcCe6U 5PYI3zCKKzKcEzDssXjkk4JMweu1EQG1kvDdUN8cw7tlPtrVbCXPyB9hnAUdePrK2hBbk4uayeo5 UB1jj/2nB4b5qNJQN8lOKzurpieKJwro79dY19PB06ZV5Xg5ZizL/TphoImWj/b2kHi+QGSsQoJ6 lW8+oSB9OGRP1gufoHHXOfg78zHjtAJ3nUub92tDZucmoYTf/iJR5OGADr94nsqOQirLvE1UlEd1 K2U4kjMQipXFBmC5g2rKMmfNUy5IX6dc+OqaskXUZtdCbstZvC/8vmJBXBtyBT+c+Bwg/tam3sOe wgx38YQgwRCeXh7cs10H6h7MleVBda8ajm+QW5faJAs3fSS6YjGjL8DFG7iCq509Z6kwZeVbIPig UWxm+021EjsO1aIhf0LauC656RmW52Leq8EECA5icLhSh+iC2ecfxu+HbtiRrKub5CPRanWXSM7W SEv0bfuEPTkFi91SxjZIxc7ybx0LOvMNg5SJRCJEDvHotZ+tnd0OkWVs39lJ75PIlgOsQsKMPE7T Ko+heNJrlLd10drkj+X1CzdZ3eZ/ygT/7MrXLRxLZr8466rzNYMAnRLptIrJObbyedjBDjtNd+Yr D04VAsDRtNCB67A+en3ToFjUlxfeo+C0tz9NMJe63b9oWtD91sxYGVDW4FRD7vmLtLYzBvhnoKZt iI0ZHRk+CSGsmugdBUn0jeTP5B5eAeejks0slgScbs602WyzCFdngWFvuH/CfD7ZWrT5VZcWCLKX 8o8OuIq7Rzrd51Jur4/C7C1tcXt/dA19v0Z/4K341YJnTtToBirF9opkQG1N4qgiR2DGMwurRijn NVDzKiMTO2eLOu8VW6FG3iVGB29aXNYR4caZAyiwBYj56pbshpJ4CTMtuXra6UrNESn7GbYwLqay Hzh88TN7eus9eJDiQ+/4Xp1ZZEz33ziwBID2DFCv4Ry5A+KjRDCPlFP/HgjNY2w+bww9JUYBr/ap Z0VoHyPzMom6MlLyi/u2cmfQ8iqFijMHPfS63yV2gdwbTy/Be4rYusxjHLe9oat/UgIaFcCIDpfQ qlhdFFQ8+6fO7KeLOXhmAdpkN84eQMAkBBHSbsdVpxAbk1IYFEfcHnHE1pj9GRH8jlRT5KVQtCjX OLoVD1Iwf7YwP0iMlRHp4URuz5z1XXNQOVN21V7+hcgfqz3c4pc3RGuNiLQZB6SnkJYbcjdiCYHJ bQGzr3kig0yqb5jPo01cVBPpnr4/5Wd4bl8glktxzWiYMpt3LYO+ZD2syeHFjn2PbknVaYqnl3ye yzFhdhTNnpi/pOX2RxC2CUa1fAuj3GKjRLS2tl8DCh2pXVxNZerz8jfII78CtWrqf1d7//sYsMAK p+8NXS1WFvHkV5InGQR5aWVricKSpPZavKUqC2VUyOY1kJqUFY1PQeOWhBYxYMUELVf/QZnUo4D+ 3o23ou2Jm9Zd9uvBq79Zn48du4BNhmEqeAhlC+C0e5ALWhzaHNqtCBGJZ2F+dyHbzRBI+aNKIQv5 SHRYttitRD/XkxlicSkbyoxEhArfBWn080XqPH0D9bHG1CdZeBn7SMcDPdZs7J3Ps8EGkf/hOIZ6 9yLV1DOjUuXdGQ0B1Zshux+LZmfdCh9ouw8xiYjhtx+AU6OMDDtvRL5hKPHYF0dPYoZRjOABMLB2 S7FtkZFegoQU7GJCNOD9eMz0E2xppZq6cWvLjfkLsHm/FT6zpWhqO7hxlEXSEfN0R7JOOYNP7VL8 s2WSquwbK4Ne4Wc4WAwnxh6KjdtQOS9+IV13xC2k/FoQZ/7aEvqNAqwC43s81UUmzXRrPS/AnJPW fuAHkIoSpxXiBy/7PqIou/zBZJgl2lnGNew/hUr6KXiRRlKTuq5+8Pv8GlNaeHzNJYdVQe9c67lL amfzb9LuGFBQVKw8AI24k2Yxtsg6V99kzDbMhSzCOIDcUVBMMZatnqXIwtpJK9ZnpurW9YomtPGO BhHx4S1DLkp1Vd2i8u4ZZoTkyO0yZbB5G3MhuYRhlK9Z+gcxfxNQpLxOc9ECNg/vcepauSV4fxaf i8YaPM72ZxbhiPhJwFNQrVMOFRju005YJpYv9kSCDM0qM6Z5bm68G19bkj7ObYzpojVZ6SWPQNps nJ/tmcfioffCjx2Lo6cu/9T2Pa32sHGXoDFF+S9kk6uTksOuPXcfEbcGL5UVR/Z4EG29PiS3n2hw hpm83GkWATA5+q5ZxYSKfQZV9ykZ460MHviFoQNXFHhYhVnrgxqhwxzFDVsqZx8vtp4A0ecK7Y8T kGi7o3OKT6SkBqxG0tv2qAsoL1HlkGFaRqvTYhGQvJtDuRKwt/1VgtaClhjA/3CuN57T/Lrxpd40 lIcZcmLu0oRolF+dd3M3SYPYQOa9HWAmwS4IA32oFkzsMejjxr575qAucA139aedXlA+PRl3ZiDg XPgkcik/9WbgyABGLt6xnBRUprrjHn+eMOYJwNulz9kBaxLw7UfAPuYGW6pbmnP6wZTzoLd+WaWm Dcg4SIvOrDsBZlrmkRw4rGY6oEQe8PlGPAg6BbmZ9BQIDEVH1DtQYQFx3lcIVAFG4iREw92cJi29 sbVWGRpKQ6yhYsWipJPGYnKegooyKH8a4KagE8LhewZ5yzNHf6g+rIllua6EupAtLns9z47qNhDw NmAWX82Hmg2nS6vXpa01R/U5j3jDQC/goI2TVwB1I0h+6zEfCeQGsmk+9MYV5MGQHEEkEVLKJROu bVqMPpKrfZQ5C8Dbji+PXLp76Uwo4HtKseER01EmpIAwiPBMshUzwyQuTeoaEuQ+4LGJzVqqjsS/ ObRrRjL78pMpAMT6crvFQFd6cpLTTF9iqfivuT1F4wBiHyEVNPnquQff9PEPZFmiWoFVjhAYf/Pu tU41DbJfbPlLrNAzdu2lzkn65pZlh6Kw5OQuyc4E3EpwZp+KjbQouBq410dbAjpaPOj3AFl9ZqWd qjbE3TkzA/0A8QPXdZ/VIxhbD9lyy2tim4SMA1KkjwmW8+ZlEvnlBw5NFV3r7tLoSIZyx63xXovr cbKI9IcUBInuWrrHZgDvOnIUM9q407zpA19EHjOrdCgrNFKFltfJZtb4V5ltiSsDF8AwzBcCVeht 2kGBnqP5Qp8rqv0Pk6b9PNRrTh8whNliPyHoeggiLdCReNqYR/zHX7gnS/ivqS/uqPz1ai9nn/lN aiSXN1TDDTctDCXAIgVXBBTO3iNRx7B1djYpm+z/5xG4b5WrEhwssFzHPC4LbiuTE8YGf85L29+d KVuFV6WT8tDNJtedqJhQ8u1VJZd0PPfSQLgcUUgN3RNcAOHSFqZTgxugvtP4n35NUjQpVQehWB2R tmye4heN4N0KBbrfT9r9850u57o/dpGFKSYcg3pzVIMxtRbem74newKPYcgEk6Xb5O8GCu81KXRw RK94yWaPNApHk/vsgEjypkXH8InfNKp3YcQ3N7WobzirpK3qqtqzh9R6TjKxo/KMp4lLeHiKAU5q IzaJx2nG+fczDmBuFcj1n83WyDmlr75oZKgJuDlTbX8Az7qe16CrAu+QUPwNEWO/1Ehcx3W9Ayts pvVM40BypwLg+6TeW5AB6rg8wizeVvBFuRKMRXpMRXxHMtYYKzKENdl0UJgvoD8JBpA/tUnae38+ ouisimSMe7tFqfM0QG577cIr/8EueNXNWLhBLxAQiUvnLmxVXuRJMwNSI8lxnhBfpC9DrnkC1i8J ZBk9CcjR6ucdOUZUIlqlqmmySJFDmu8kuXWtqZUb6fd7HOmXmr6gRkjvSOtMTmCtXXRDIkO+Uawh v7THskySx8lt6yUAjYUVv0IGH4KxkzMOz0Z1zrHyS/Tc8rjBRtYRfl0fRMg9JKWf8zsTvMpROWjG ZvxRgG6KTiRYZAqBvvspvGntBTcL0xAwhTZiCD2nqUw86GOwjstRCfP3wc0YkRzhBM2FkCedzBgL J0QRn/VtqRvKVtD1rOO9I0d7wgYez4ReWpozgmSNP2FvLNzqHNQ3tfGFSGWxFd+ClHttk9x3Ee3s 0zZxnCJzsAmQv0buHO9zmBBJ9mNLcgzlSjucKaFwzbSxgv/Ej3d/JwAjlINpNRHnvQjHd3NfaG7z 7RQDZEV3CEPOkYoIBqPiWHzOrFF46uMz3uqvKuO/ndMC2f0gWaRJOEQmqRbbDhtYXopk+raPAw3s Lg0dPMowrnyiKhloqzpHmMvQasAzUEQDjyQFKzQjotlULhjiz8fC2Q2sbe7DwgIxfqSm/KgYC9Al SF5/mYDnvcs/SdXf7S9asCtd59A4fvb4ykq5RX6m4pScyX2X6Z8grG7Um6eYrAzX/HlLz1zqRV7r WBLV2lq1VGFh+POTvZU7/32vDC4OwVNGSGIha5O+DeKQCSh+u9Z/bQo2TpLMLv9R+nI7lz6Xou0r 2Xno2aS6ccFviFBkGgFL7znIG1ggO7NIFV8F7w423Q9QHLgEarxQ+FyGIHrlZZtfN9rXrViwsV74 rooF7YjLbIHZO7EyZqOFcIGci1LR+fr66mx0m44LlBJ5KwoGohvE5WVRv3+weMVX4zvdJa7CeuPb 1l7IBd4LDxN7rT7lXJCqPXK8XoCiZlEtXQ8V9p+eKr/OzHO945+7JshuR01fp2eK7/goIaEmTe8B 2oLQnQtzJuP/rSaZtA470bNq7l2Y3KhUZ8oCe1tDPBExtm2eW+wBPuaG8j0IfofrvtHRFXxoyvPn CPbT+Rc9LIFTCxFczvZLaEdJ3kTRVyvepbl7tOSKByvuRt+NreEgmZoEQJMeV+YNJ4CJbd7g4LNs Mq+GK9WD0hUFwr+lEg1ogbQkrlr9MpMj3n9ZkEae9h/BkyNtX4NFD09VY6Wb2eIODMonNkslYFo5 BtcozrRq/EGlwCJsf+DkrsuP9a079zormgTtr0nDI0QnsU2BivHDOAhJoaQBI4IJZD8TpBCZ0iRo 0kqGRjuFTrq56RJMxFFE4W0c47wHlIgOtjeTZiWvipoYNqOi7/enYJHtLsWYPjU27ORbhg5fbYnl PLB3vym2FPkomcnCBdIbx2JJMecm/oXDrf7UG4jf/lMKqRb0wu6xW5vAwfXhCCNtPqM9lVnZEpAZ zf8BCjt8y8F04TWOjxYxIWTl1u1x4NtJYI+vekJ+KAzAW1s4dWd/iUjXXPBjsmbUoioKjnaWBhBu lHjd2vPfNha797Bxcrc7qZf7rCKBKMW5BTIUTO48Gc1Oe8FQvQ5uA4Sx88YBi83QqQkN0HaGlLPm E0ZqPz1EvwvdGS+Bs7ZHCuiIM2fJz2dhA7tjXzEvArznI2U5AFGYUsgoNc9qG4OD+XRB8mn7u3AO luDlyeBtmvNnyaeIaMo6gcGxcfAFZnN3weOyruaLgJbNbKcZ96f8zKz6HTJw8F7Upt2VpF899ULL DJINfp5XF3PJ9dEivYBWioXsR6Iq/DvnzIibNdrCFaekINwVQwCtlKGYzdhV6HDMOl49U/vWPT/u BeLhMODHXmVotdhdW0dGehO2iwmURKhRWiKPVu3QC51bKB4KP9t1NFIsNLYqCaV7wjbMloSm/LOa la9jTx5AnPHevF8seek66ggwc2WBNxrf01Kta7/Rev5P9APEMiAi4GhW6fXpgq7goxIONsUEOCYd SCETRkRm5KNYec1x+DVEcZJ5ZF/h1IlzXjrs23BU6iiV0gqCV3oVFDtJj0c9ZmXGQ3JrsOKLkvNi vLkdVn4hYF1F4PM4ZVsLcxK04GZ8KCx7eJKm57D0YEAFz6Ml2SM4DYWKGXcBixIlMHf2A3oCH5Wl W3UxSbXZnkV8bnpb9NUM5GVfx/RGoBeD7CtorWKX3s5fheBwC1dvVZBJk1lpsOrVtEtByAQLMA1r +muDqwqs31eNvfVROgnMjUkp3Jjo94JkGn6xmqZc6GsVGAGPH/WCynM0kxUl84VxdtxUxEG3JczN 4PikXfDvlaswhP56tB/fMzVARDGRJbiMBhygQCw5E7MkEiDiSJcOkTyNebVr1NfrwZ/1Ac27rgLe ajwLTIXFfGIySNHYAGX7XezE2tRpjSOtFpxRPqQTXJKQP5So3pE1jPSV6B5PRsDkonN2UJwr6cMj woL+9wgCAwUXnsybfkOO3MAkhhppAI6wOpXKKhG7HePgA2TNRq5lrdMFpRLC66jNLC5QU8rshCVO OFQr30Pg29xTn08lJY6rXmlaSmr4lM2btIMqWRyh6vjJqfw3qN/W1L/qltBfEYnaWi20qwjyfTy5 kU8NK6AqatHg7uRZPs0g8ulqQ7xKMa/RKUoStEwOFOj4lz52kiRSzcUFHIaLcP3jYq0QaTT2deOk fXEx7nXRKfSsdnwPXJNw42tt8Du/B372Sby7wmM1Nez/D4vIzcbMk1jlM3VeI9RY80NN+q8iuKeH CHArRrLVpBtHZG5lrRElEd8ZQoRZ00xpGTrWcrdyXG5G7F4LCgN6F875DPI5USZGVnpVg1S5DM/v +s3h8kjDVCOq2Wb+tdarIdohPMcLmOe3h+FGig8SSzc/0kwi8o23H4QYYUzYCFWdICtPz44vA7Di 8DOmYTJ8HK1I5d9GDRzFCeJKIgRd/6xVp329t8Kqql18UnWQKWXHrkidkBeURDzZkCFr6v6bINPr XNroX23msDzd2jRd8qq/TidjIraulkb1cslBCIHmxGC5u0UByzSt5X97li1ayzYnexbGdUYLtgd0 Z13ksC7kllUW2bITLWvfPKunRYCAyCy014LM2LR6MVJO8MTxraKplyJBC7/kjQnevz+3hP4AUgbw XR+GUdm68GvxAYEi6+R90aIiGVa19ijhtIfmzb5C6kg9xOzjE99u5qhkvxvfdwJLGBqea33I0ij9 /8KNRwnqIvTS/ONGFP3Cdd0aBM5ixPnPVkbzPhUazKEJjd2KSgvBmqrbDCEmp4LPQ8EchEGLmyVH Fe6GfqyoiDhpm/xpt7aPKq6kV6QQH76ToUrhw45WqO7I++rNOHoTXtyo7yivWDt39dcJA8U2WvDu D3e+C2COQcGVTLkb+VI4/CgQWO3AuH7uK0myTc8EkpUuDDRHTFtitBkv3CcZp13D5+5spmpRV8bk b6hnNbppSsX5+cd/8n0EOltgJeOdFQ8NEC7B8Q/L6uNXrnrSpd0J+BAG+cIF9aIOTu0S5BYKMWl6 eLfb0KCTFsLVUKaxMspWxn938NE92ynKz6AbQcKbCQOaN0+7wrbIS7Z7ggvbH1aW7oB6j8muHIE4 reYW+kJ1JVX5Dq82BZTKvyqSvGbi3tX1LisQbxdfnKAs1kQhC2N4d99zLl13agrQQ/w4sYG3nAai +6YYccYTmhMO0HR9KNgpZPsS1KrSXNz7JGDrACz3z6fDfEbCozLRmDOgb3M47cX69xT6hSjocf4V Qp5LFRGef7gQddN/0SM0u9N5clxgX/KkVC7wetLQekPy/WiONzJtrE4yn8EIHso8jWKFj4REVcD6 Q58pFHQbmHIwBKxGKbN7O/Y4CKKfIQIuT8PeAq/noFsUAaNN+4NsvoHqGx4wAcdN93XhAN88LmIR 5zwkzsEoXSZmNPRxg83LzLWQzlpP3xOMz67u2QMJKSSaNtpgcnuh2jPfdUzbiu/QTcMYNsIU4Y58 T3pKosQZx8RSpFozelAFSsStRzpNzY5r2YYcaEurkc0cOIXDd2gzJD7391kH1vuBLg+mJCT2bWm9 zKylEU9yIlDJZ9x80RJk5i8+o+Q1YeyisC54xf+b8GKwJOJ/s/PGVAP15nO5A538CadyH1KH9EHO d+Pjqpgh7ThjfjQg3s8C3enIBeNIEn5gEJqcywVVW4JRpCFfk34A1K9IaOIAp7bbNjX0WE96sn7R mC1vXqckofZoGPNkbB15t14u53LfFBdr7l5mpGBtIwztPw+RNi7Y9m0wRpT3hsT45x/LlvvmX16l ive49HDW4OuQ0/gsafBLldDkltzFRUGrYLB/RSYAQN3sCXX+OZPbI1vFcTx+OnNevLTWtxWipBxf 32iQEN8SzoFghyYgtR7+gunLR3tuRoQaNPTsH7cTdxwfyfRIu9Wv0WTsCjnN+Ymjk+eNsbsoLrvG 5JrF8Zacv/bFoN0JYpoAdJhMVlPPHOGk8xh88OKxvJi0SLp0uhfSInX5tcM20UwK1nKiddFKgOg4 q3XqXxiWDyt/WYSoEB5f3norTULjkOi08InyMYXkrjpzeUVGpvb1z6uxMmhvr65uAIyz7jihYjJA mHolv4UvwNlrGNkDrmYk5nuYHKv0CMNRLd67h09JHLtquYr/2sNUnU8suI/yb/htOqnBtAGyPlkm BpzOxaom7Hq65gfFbV3kkubYG8lXTkxvnYr4E62QRc7lEp/owfWd1ZiTFqBQ01+87ROSzPQtdOOp YAREJCKwRyLpXGrthz+oYW2QjYU0K5+CWbV/UMX/Zrb6v2lpgAeEx0OhtJp0E9ryVxUF3fpRL1R4 sMJj607FSRWi9fwM6mg7+kSYKnTIsc5YK+8tYfYdUyAXeSvBuGvkYvAw2OOTqrnt999P7KzPzD+D XqJTbXRwnVJ49vTZxb2d0hwfGevdFGGCLeAJC935PAKkO/5ala7b2I8qDs71xaVAP3EXk4DntMnh gqsVtLkZmelIush0yfRGyx7l7MGUFhQ4UJBgH2vIvNow9U3RYHWgdeBCzY4NXrzDU/8oPTKW5iaE e6tzlXlSzt0P5o9Pv1dzM41W5D4eXDPavbHr7wyYRDPfcllRG1NoL4KGCySaswEvq/AUWj/if+/H pYxJzTMV8PrDdsOwo2NQCw0+9TodOnOxXBDARqyXIekNjs8SeMb0+IibX7zB7y3qoCOQEUpSO9aM OVFpogTV0R5izrmgqQ5XuP43yEjjL4jSEkINT59ZOlBwfaiOsluFuqV70fmoc1SstIzn4xYO/ITd Df5LOvF9/RddqiDbOcLyahW2TrzeF6OfcfxPZIf/xbWM0Y7pxZyMjJ0TRpQDdTjor29HOIGzQu3E 8cL+8guqZWhfrt4w7D355EGB1jVf/SJGFRKIhZGtOSkrUjm8Xt1VvM8qyEu2GABnU6qjy+TV6gQc 4NlhP1HAcE6b5TqwHCnYYPxmxbuyATM2ztAoselh3hz34Jcz7LqQUeanOs+7Sx1G5ahUFHmuIRI3 OZDcPQI8N8LfFqg9JzSBMu50V27pUfIyC659MpTuulfwiw/N5myOYmpvRBHnaJMwhD7AGVquGOAd daR6PPrvLDdgMWakldNHZ+c5f79Tim434iq2ihq52xhnhUeoEoQkJF59/0BfVN6Jpj32xS+qTNxV o9dJn6ckzamKYHQNBDzYKfP7/JY0Jdk1CmZ0JHrJzJiVcP88FxnJm5BXL1I2IohVCcyYMRSQRYZv 2nIZkhmhYfudpZvp4ZKdmyXbReHR++wV0TbeXg8TOfztpp0sPXHRsRFhtFbiXznHi/PbYuKnpNjj vE25NjW8z8c4VuuEk9/tuAlfyQwtYmTweS/99cuaagz7nj6zZRLBGI0uoLjRdw83UeugCk3Q1Fmv 8z0i1v4lfKVVUQdHIv1ocH42/fC0HY4m2FAMYNBqtKJcA7D/HP+qmkGnnOP2Q87KVwPXSnbHYUnL S4isgMcZqm66LIi3hqwV7hrvvk2N7QRe0DJSwxCkF0yHbLgfu9DynUfeQ5SzGcSrwswwXubzbtZQ DRj/X28POsbaVRJ1x7xNSVDPxkSGoLtvJS7ZsNxuHzwgBBh0aUmVMLUJBA6Q6vrh1gpFYfDYNTGM 7vuFByAEXGAsvlAmuKNhjEZIrKDdib564lJ2E8/h5JJXIAfosYHXzisHg2iBTWhG4bBfuFwGpfnS aXdlFXblH2a4NpeVfWdxin5CK8f2Pbt/ZTJwY6qgd2yHfKhkG73KURd9fGmttaFHfFNfKrAGmivS q5m7K1DoiMA/COvqnY/I75F5JqZIao+S8g+PIG8nEFhZ8UIx3l1Qpcpg74VPUu0glUJrI6tmn29L YDzXXP3tC8oQMEfTNTHhiJPSJTppXQ2PU7Sn+bcORS5VPVOsx2GGAtSDqtvxEB0r/f11gZvnX4HA F2uE25KSp9zSzYytzJCJbTFBq6eIeQ/a1vBZt8sB0nBsuaW4ENFHUiCmwU0PClWFVf+VoEj3BD8u VTI3ZfCtjwRq6uDYR3Hr7ptCfNBcCCOa/grncQVyZfykZREHn0ymb0YuGThn8401ZHLRe14TDNIY hngZlFlzZgN5jlUHk3x8KqI0ye1G6Je4wEAyytK1+o1MUz6RQb8Fcpc4+SiCjeF525cXoRlNdecB MOKG5Wa3jMA1i2w48EcoEEuHwHLUuUePpg6A3BOkourp7qYaczxhSEwS8kuM36FeQD1QFDHKcJ95 RUm1AO6I08lt7STJiBotr4Z2sym579PSoKxIlZA6wkz3hef0ejfrQLCrtgoYjnChywc7hPUtRXD8 QFFIpGdmFDf8240WJZ2QjskcwkM/AwDucziGYLiJ/vnRHzE4AItc+9qV/WOKg54LANa2tP9MD9nm x6XYsmUGR27BKwDR23zA5wLpgq0WdpaQ0G/O5TZJwWwshoJq641SXtmirbPmovjYn8NTN7kqaChW OEu2t+Fog8A9gsBqteV03pX7mJPIcWacQFsr4Uir2ioMaf4DjOp9CLtR1xZ7qw9/PI2yd41I+IIW /FXyZnPEGg03JRLyKvFDek+IlN4JEAgkypdycHVUBbQuDDKDHJd5nNVyUw9UCCQ2kJ49X6vxbwWF KcbaotfSJDUL0mz7av9wmWVEppDrVLrrcZtwsqD8MHUHhgDE9Zt5VxoO0suL8jum3zh/1gz1J3pl 673oizi6xHY1ImIEs3I58A0JSr57baRXPJgEkajwD15Kk5Zd2D6+bv+2xev1ETQ+VKfITaq8Bzs/ Qw/5j45AG31rLkzPVh9nP7u9smKFso1IpJTbSmKcm4XY2ouI+34ZjQ/Y7onXQVuO6DzyXvypLDzw c6GoafBnar1lRBKBZZnJBJnz/FnAKUQ0eiwu8JNMnYfC7SVjCPux+KYEeKPxL3XCVUXOAcMMcoMa 6uYv+vG1XPhITWVVXvyRunp6n4sZPXiUUM/Pab2Vz7oXwCxxb1K4xVCTGuLtvxBqMoSpgM0CZq39 ETOsRfq/53Jhbc4dQ+jJaNFxBFxdrJ1qQzjdyRNpn2DpxXpQsGm60d/ivU51DQRo/R1vN7g1yQE5 rGhBg/Je9DaoDlTyJbTESvo4OjqqWwEYjpMrs2MPPPNtJ3z/1+dF7vuZ22f28oEnIYmMdd+Nlx0/ zzjO2BYWqPdOcfkuWnxlHbc2t72B5Co7SSSfr5fIxxW43yzXxNQhQ9Ies9z6F7TPpY0+/Uet1cmk RGIG6bD1/nKhl7V/V2uYM9yrsWAElQIOGrqph0sNCBuxecsRPxfrbepSyEWlv1XaNAc01d5+3xwP FiHfltRzqzVCWfw/u6NRYorP4j8FF0AiOY0iBQVRzCzgiMtYo/5ikAdtkw4Fy/mcTAWg9cvb6WIc TKwKJ23rVTxFyurWqbA5sji7/Yx8+b1Na2Jx0LNGNjn15wiowwBHtw2PYJGGQrq1g7vPCQBtL0/a LHwiUk0vd6H/GgFeDxMhgJQafV2oxip2y/uR44yYfG6V7TCiIRfCDOr3R0mPNLhSRRPnXOiyfwJQ 0qmvhUiehtSCDpiBWq6rUYgRmr6FP+UlyxA+WG3ApD4esYnsIZrs3mi4hqKg7HEIr8pUrIyRfs4x xZ8jxUrrf6prdRGXM5HWJrr23DeAQdriRGX0e7j1qWpR/5+n5/dilg04NqOaGCYYzFotS/Zbatc7 AxyntAOkoweO+yMaPsQLUuAG426bMwG5JHRAkDVBb2tfoEaZbsoeGW21+flszSvCEc91trnYz9DF Cfxb/6u59No+dov4483JzcA/o3VqJo1i1MAeXPpcPr5c6CjhK9RBga1YzKcl0jgieFvpsXrCRQF9 UsZ0MdehMAtiQgYT9OMFNR53dHp7/rhS0NF+00F8crGM7MWAqCdkZuwX5WKu2bbkQtKFzdWS8iS0 kmLYO3UlIrJzQQI9+wKis+vQzngrRYclbBhE6wm61llXfTDC1aVJXP71tEdW4bjQ+8ttGZjOwP0S LrwQwBJBPl0KmYQPkuqLAkiEwOCqjT7rAj1rLKHEr2aaUsOXnlcMwmM/rfXMIXIiTYeESk2vYOJe 5d0jXkyIhzyMvQ4fUSCkl9J5YNADFK1kXXkcpEJTEUWf8r2TEQ2KWIwzDBLxrdMstuR/OBv/gnbW qrIxzvGj+VUoCttuX3txP4v/3bKucUixCbv3wVRC80INJBOIQVgeXDRk4FMbUDjX1vNeBEknuZ5z 6S9eR3CTb8z313ZRfa+jtWdVdE76qbNs3shO8LBbwi5rxCimOFqVn9BUiRhYCL4lSAMaXrEEShS0 my4Rp4QdNn1Aak/ZYCiSyc+U5JNQj/Ou+W8iqAQnma271s6w5W0iY+0mPYP1UEq3WlF/WvsV7FG+ MKaqMqThgIRwt2Y56Vm4ajYFZCBR7X5bVr846i+be4iECdcONXsqP7kaDSFQO9Sfytld9Z8LbqJe DanH/kvCuEEC/4M2vm9WKiv7ReWXz5A0MAhfEDt/yREtUheQZbej8dWdW5Z96FAyrQK0znY+VhPD Txfn9hriYpMF/AQI3YP0HcPWzPmyGq+rR+ANr6up0QcQ9oDXscfGf2DPZmFwUugV9EBx4Bm8Bxk+ p1idC+fc6VjjHrUi8n7VYwt8PutJP323BUA+v8EAhYLfU2RChQ7Vaw1S0Fuazn/nS6VbW6LBro1I ODL7iwIxmR5KhfqL+FdEOnnkNCcEF5KiOneEu+b2a9oexboVCwTYuOQr2qK/qXJ++T3dQSsu8+fm mtGk3gIFME1cUzp4T2Q6gj7cZRzH543MsDGxRKw/Zmgg7rqBnuDucDc+WXtgPS786o+gmA8WFKjv lrxFm3nrOuB5ihM+5+vTT6qwLnfvuxdcrzRP2GGB85jcg3kihzwDNjI9ABwG/Ddef1S8khP5BwaY nTjxfxISIUQ4VYQajMbcygbht1rCrTF1N48cH7j94KZ6/mZrdvg1mosj06LM1K0HynRv509peCfr DMpSqUtlAndyuGHaNVW811OB8FYSKw2iDnhT25YuCzzlpJ+zslJq4RgbK7FX/QFEJUyh+g+MSjnW FpnyzC981DLQdgrcXtn1Sh1Mq4mQDR0+bgUVpYDEep7S44Rcl+E6w+s2WqIUqh3RRU4+QHr6lyHe lq/P9p5SNz/4pE5EuS+Zy/wqwCMIUX53dy5Mnpr/ZM/2QeiJl5vyTrcBwq1eDLNyiY3zGepCwP+d vFxI0eBLTIPCxkAj4pzNJ2QJaEjaFXAtzodLloNFA3FaVrxFZ3Ov2fxgFsEezxl3FFqTsKipmrYb N5kA8gGoBOHx2bpN76Qq2woBEiQgx1dAhiNiWnhAup4/DceMJgmOo76peshL7A0FfrUJKNHsdpg7 x3GQUG5h6HqKHOkQU1axAX3YzQEQoLM1coW6wRwVUfP3uNLfBpXntfVC3S/FgmIbFHawuBJ0mDfF gJjZn6/+bmOfjHusmNieN3X4JAkJLDwR0hdhWweqMwCduwDK7fikwTd3jxDZDMrHd93XXpWrPgcM nNYAXf6BCbGVujLivjOGtwK84lMu25VHbph8o/GCy73UhEtwU7HiBDrf9KlsmQapPjfOXIRQG/bC wm8kZOTRzOlxqyVzzL/3GjMX/8XrtrvGa6DLpcsQWIJ5+hJams8qYrhOhJozO54LdleoCLN1GFE5 9KLUjwzKTzFF3RGr7sFopSn2izMcWrcsnBlnQ6K48ZNwW0Xhj5sBs3IpvrPCqVB0jGhTg14rA36T SGjPJc6RmcKjPhSJh8v1odScp+LbHyw1WiBGXowh8V4m6VYgQg0h/QDTT/SCnEzuVeqM3mpWNSQw iFmNa1qdYqpTR6LUZh0gBUs1kntPk8jt7hwkUFhQZ9AXezeazoZXAXCRxIGdaeFk8a0XGUzOoqLg xUhOlYO1Ogj4h65NeYgCbUK4kMt1iP7HY0JghCtJNltIbY8lKMoADIPVzkgH1psPkvaK6SoJarbw mfKAWtMUpD4nDWA2RiRpBEQjTgTpXzz8pk0siNVDvNFX+qDiudIGPNr10R0FYOrHIPrT0Yfkdzuq 0RwrXRQF0kHYX04PeXekFuMRWA6ENTrqQtCJMkpb7z8Ek2ZnMuC3aOumLEgnw5c9iWJmLID1/3fT SPYhIisAkKznEaPKuoX/gfjr+JBirs2r56T+AoFoaFh24dprRJdyr+EupE+XjGN0HtENPU+KtWPt JXBH1/wEA8PQnUXRDeA/5FsiSurglewRba3zJR7HPDULLVz6ZcKLS/KIuDpsDZQA8GvKJuPE9pEm p1iHvnWPOr86rbPn2Yf/DkAsNR4RKr4Kz0UGNa6Pzl/QzZ6flBH4WmojwczIgocVZ4HENVJrINWy gXhQzKDZNcCcGcoax38DVHguFxfMOfyw7qIqvBq+7yBp/jo+w49r4+x2ULWCLE7Te+EVdtHJBB5m ym9pmfA+dw6qSGG+5zstw5hs9MYzDRHfJFeqkTADIEwk4AJG5Rl7WrVEpSfpfsWirjKAxXzuiOO9 hkZ1iLXBzjdhW1jEGnKI6JvyzU05dXoK+sDrYEcZT7mYRGvxeDmAAEMnJD8gj3Fk4h8iYo7sUvN7 9VndI5TqDjbm+su9WaUWf6eRlmB4Yv0XFjdTC3jffOroobRTgtPx3lLbVpQdoZeAlSMhRBzHqr8R Me+n1OQAIfuWGrSxIa2CgIDRGC6sUEPVMZqkp5o3FLUtaX0MdsVhcZDj5cdDcZIj3KogUxRoGnaL GATUAloF5K+8a/RdR51gw6nKEo+7peRBTgXXba9B9L3kMOBDb+sjbDA/5VgumPY2mrdZEWnoTcub idmjm3M3bV41NlZZ8EbTH2UkXNK1HnXfBQsDE5vfFkmhERGaj/wO5yVliR4AvoamYm5FTjUfNh4x hVkciYaRllFpsQtmXI6vgYCF254M6YtDNY9zNgf1mQI4HYkI0YcOLvnYMQJIw1rzs+0QKUc9Ex91 VUbDLhRc3ClrvofZFdIiY09sAcZLW4LAWgJpslsa/+0A5Mqu56dYYXTvbsITlE//VxvbokWLdwpO r6pFFS62/JEchLk8TiQB3I9W6a3GMgCCtyrl2bsB0XuZvjNU00zngcMm6dU3VxAQiy+dGXEzx+xO YG4tl7WAP3JYwV1s2l55pPXBk5QOOafxNGPlTPO0+89/eZOrpFkenOlpixLJ9D2SNIO2KPtsG+g1 YUGDTZ/FLpYpXCpxwBQhvuVvCVLtjiqhYiHG8SbZD48YBF9G2GF8HUhaYlJHXCGgRa3T/M4FLUZa ZnxMXR19p4G/XArSg3ZvVN3siTK+jdkGqfuo4pthurq40KDkiU1S2mrJ8EtNIuUfSaxxaHnvUxZq +zBGy+kTBO8LJWMnlpwit8mBDskDRKUiuMh1PV2K9Ea9c3KZTHkcS+IK+RHiBK2/gt/NSc9wGHWB JfoptUneYxqWQcPaLbDsK9GgVi6t7EwgMxPd8xQwDMeLtNivTbBCyi88AjaY/vegLZ7iJGpDqNXk yfTht+SMO+/onQ0eOKsGHU0QhaMbLPnj4fWHGHKZCY5cWnDD/GN9bh0ZerXz1YbFUxSk2siMwXXZ uP+xLFKat/q3VL/86vV0bk5fLBoKxU7T4/+ZX6zSbUkW1veCBMV+36czuoBUAIYEQdNnaBLdGmL3 pzbQ7UD0j1EJF6KFmxeAmHCbxSYM1rbWMvvGHCH6e+tUqf+giQmA3coaB3Ho6F0bbRsib84UqJL5 IFoY8JOLr1m/f8aEV6EuCL/2u+TgJE/KbyjRgLIouBpfK8o/0C3hcmooBMrPpCYF4pE6DLxJM5qq N8rjMNPoXE6Da3nPnklfSd7ihyophPqWHaLvgLcaN9PsMo2tT8308uoVZ6weaX8MnHkjY4YswtG1 LeVUAj38zYsNSe2DRsGWiWTcwDn4mbYkb8MudDQ2dTaufGzt60yn6qjsr7AoXJR7rcDtQEP2omLh IDBrQbc/AG7TpVu0B5TSs7MeZ6+Zp+w3G//j9TB7+e1qGWybr152h3L0oirta2HUHNIX4W61SIdE 3jgdStN4zIEXAx1kfXUf03MaIkK5kZbbXuwiWcv8l/bzIwl7EHG/qKRcNWf1vqmj6l9f6UpjMjdj qV9YT8jmla1VaNxdMJewLg3g9TZZHowCqJYz1Z/QPBdwYzi6El4UBhHjCsqGm7OF4H7CgEWKqHB2 TqOjeNCz76H1MsNX+ZyCRxj8xPYD5J4tA4z/Eac9ToFczzdex4iNQo0ET9PlHyLY1Lv6V5Fq0uLh ZhYjNoZ9zrYoqgJs4zmIvXHF+5pUYCDzCKkb0qYastX3ououQ3R4Jbhb1ZZ1MK9a38Ii88Iqr/ra SP9qeo0nCyiOG6iObpJVUEEi+qAFREgPBEnhARHyZpmphaDsC0T54InLmWDLDQUJcS8Zg9NxZPWr qS1Z6dr69GOz1ZKqmgNUXt7FnUVx/MWqjjhyxbdimv+trhPC+QdCRDbp2JzAsJUs+a9PBDpTa5lo xKP0KQOGd5CjXVRWYHXm6L5Cis62/3OqOVrrekMbxvqH54p4q4ba1UoAif4NUy+B4xA6tIjyFTZM 168C1soVdknTgIDQc/M24KDfosP8in+BshXp8Ee/0PUFknvM9TRrVIdFQKJBE2Zg+PT7UHGVFaqt 78g41qOwf/v6H9lebGi8VCqaRj0JV2t6a7FsJJBgDcFctg3CxPETygus5SrpY1hUG4ZiH13WTwOI eTfslOALnhz7cBR9M23hy5br123gZ06vkx544ZH2MJ1DKygDVy/BM1KUQVB8dUzlJoieYXK3Qsxd qvfrJKfnTcwf7myPEGoNaLWUCbRSqRZFKUTnqJ0IJ/rf1DSrJiihzgV1MIF6kYZgi8SXZ5mDkEUq 8BCY0aMXUnDEkSTrGNttuFSOmPoiD2uM/PvArM3ezn4SZ75s30TWXjrVbIj+GmYmulXY3utZwxJZ 911zB020uVtrOnQHmOb1HBfz9Tfja4jckXOS2vbD8+Gb6AF7GPVl6HUp99m1rMzelmZFH7jjga9u SxNWHS3MQ2ZeB4brWH9bvAd1QimFVqW1dTiiDB/bFOT1XuDWTGIzhSkXM1pDd0qpq2I0oABPjZOy Kf2iEdnVM48jf6nVsGCV0JuCrjfTSgGD3FxQ3vGUBRlVjhyC5lKfXR9tvyNQq+FVdG3VzsXKq0JN 138+dxEdB8yFAq2HbJ30dp4DO5XFhEfsZjexd9d6pUbgg3T8gmsikqIOLD+z8ZO4IyKoxbbBnhm5 ScGMoneTxvVUJ07MTeXrjaPeHoE+c++/Fdn0XKlV/oVPXMj3rFJbUxOhQDUjh9DuLxTp7Y88WPCV Ywui6KuKWz2u0r/aLsSVXPUtlADAgqwZSYqnSrfSnXutOOeZCMJo6p8hTIYe+k19K2cmHnnBqlA3 tRa4T1PXQcmHOGdRzlFN4JSeko7VT0I8IltLYro/0tm2ZFSq8HcVVP4GsaQi2nur+sedqFXjNDsB TwEybHgf160u2J8kTkmLWloECeUzFny4938GMMm1pso1GsrNEBI5OlGfqvRJNHwOsYYMwm5tujCw piz63hSaTcxyXLI6uJVyPMHyE06n/q9Yi3BoLV7kIeyDTLBhfz4siY5lD9P+tyiAbsyYkvrx9/Mw kykpSFp0sQv5LOkc57cPN6K6rKz5kTYyjyCEq1ncDMgQ6upkKmIDtp0CCCSSMMNpZV1qI5llTSbW 3882xlYp08/TxMdvZLYBFbUNPcrpSMUWOd00USkEbYkIz7EIgsi7JrDZx+udu6I2r2e0uQX8+ddb jAyVdfEuyqizTaoyPAvYkWGQleKL1mDKvTlQ45JQYRdZi3uslO6s32+bu9kyzhrGT4WVzgIKfSTF DQ+sfcA1mkW9ufBwfZWkxBQmYBZMTbgpa4wm4+i5Zh2AtYSzd7FCsPVy+hoFbLrmkoZK73Hc5O6b hwQh9jA224W3DDne7xQ9ha58DsnHNcEPBaICJVdDXN2UvDpOH26QrwqiKIVj4NVffKIUVTRqi8Ci wsT0dAR46h0MtS1YsMBqWqOWem5aw0xZM6icGSXvHXyLvyTNd1HoUJm2RM+6VMVXnpACn0qjYE0Q QiOyarcnCeXU5wH6ktLGj0bQV8vrZvLetOD6jMgVmnOMXtsziyMiut0KbQ7l5HpxrozYW6INXRif SXEvwg3MtuhQt3GwmDJDBOEZLHsK+bK18TOyzpAvpvupuMAm24DM2LaO/koTWy3W7L7NoPYxV8FZ EVFyy2zf+AUcNJQudnXplP1ezLEebVo8hHa9Gl1xjRgznmqxBe/TtEhDdNuVl0hVTB25i+3g4Ka7 bALkrmKnQGXwOkAqOvUMwEjPMXLzJ2P64mDKXGTogt2sgP1OzGy3pB/xIrBkHRtsxyoX82+rCrtl GrMvXpmBHJ16E46ay/TZA3M2EF/o++W11BNaJDOG/qDzni+QCzRxQypWo7d1kmok2cmax+ER7DNN lcuF+/io5k+7qawlCQQkb8gEk48O2KRsJ5srEMKkJ4dJOsrj8yLMJsVitTciUmdeaIlEAX5Q3Y3h XuTdI518+2oKFC+CYOxviHIONfA6j2ie9aWbCXGMr+dSZXUQldoDXHmLbppjBI2Yp5Gu/hrgvF8A d8+WJ2RtxZQrSCvUAElrFY6CtHQdmNZd5iamg8r+GDDwWEZQ2w9srZ2Dq+zG4I8HG0TUyFC6khjf oDxs5mrMlO6XYC8fydN+hbu7QJI4shNgXZVe36dr5uiU/QuddmtnnTt1VSdEKlBp6GXPtZpHp9es XGPR7S7JXuhfbkwERnNoi0IEWUl7G+bzHDESFqjYK96N9/xXBSh9P+A4HLfoPG0tO2DyUeJY5AMf 58fv8zcqj0ztKDiweKyvrEuFR9cPfuleULwuGNcQyo2sD20ptRYKHIAi4m1CluRlQCaMvq9W0V1j hD43Jq8ZWuewgNpS8nt19FDj7qa/4f1VcHJIX9f32WLIo4OoMEb62G3TtZEXMWlRgxCO8QDZ3jUl I3iPq9+nY9o77DQLuEFSxTVcZPe0aPMmIghg4OoOt8wNIjpSh/mvm0uhj5HCbY0WThqrY9himNE4 2gZV/PHLBF+ut1IIqzquMmNWUSTDpTfQxz5QqElWNVLBt1opvWJJb/YahQN0K4qRudMXs7b0lLxX /au+H3AyUdTpKsofeBGpwSKWn8JWHciGUoNr5rb2wEIlEYwpDHArmq9r1Omz6XA8mB4sd+BYdSHB u02nZ5fU6JQBBLmeSaPTGSEyBTVpKdFagf7uG75/SwiY6ibLnF2UeFHtlJepAX3Tf7N6kddy7ALS 6ttbUFby2nOYr0dg/8l1ZV51hx89qtC4qLk+LJwmV2vqiUyaNi93iorRy3zD2TSf3V1+qTtX+J1o 0RTqa32wUT+LzAasAPUxz/LeF+cK63ZfLepkcpTQydMtv807XX44jQrqJazQFIHnr05kXU85Jdim Ns5e7jpuPf4VWRUHMjDyBxePIhIKHCt3RZtaenRBtfskM8GjbK5nXoWFhgNR4wM5NVYzih8aiMTN +NN3W5qNGiHMcqsnLaNZf9QHQVY8kYEsdx5ne/PSlhAtUUPcGQTJkH8NlzdN97oWzZxY7vB+CKLc 5exlDE+nhjjrkSCakN4Xw4dSfBcFysHjQZg7kHWn2N9hqTs0pMBEC2zmpXTEtY/KTc5qztAF5fGq P7HvupkNC8MaAYNK0+jCrDbzGOpE0geq4xw4E+VO0ggwakMBqkr11GZ15yjwzBeCFG91/nRhAoHh WCyiSlwnSa0JRAoWVb6BnBD4xjBt9j0tgAINRraiNkWjCrSa3C+FkiHNahZDfNWIZN05B/TVArzQ bxfuH5e9EbgZz3yixPtidtcPrEvgubWCMzcXeh3kB0iPNox1kc19H08UyNE6AqW0bJoTg0X6v9v7 ZtlIFsEXdW8RJo0qWMS77O3RhongFxI3psfUxr3iCAz/ZgSQ9pHvhSyXpsfnVjTVFQ0PNYoLxJ0S 5PCWUKT0pLQGYpvEhFNLSBjsu4BtXhQ42QnrghbIl1ue4XPFaMgvrnp137b+d64eHU+0sR3SR9YK SMoDA0oNTguRkbnePgA+2otDMRJqz/0SKUUhJfmVvInuD5x11EIeFHsSurN5hj8Jmg/DY0aMl5J8 uK8E4JkyslcSvFcowY+eAvS2VMpWLEw/9aH2zRmuo7bpAYwgH/XNCJe8Q92dLm/PFBG69JfwC/3e 8TUkEg1bT6xIakF0iIlOrdnvL/HrITkLVNB4bK6PU9tFrJ6D88ugQfq0OcNp3yEpdFTwUwx7Ziq1 4PErhgTVMQfah6Fran7cCSgdasldVeFYzxm66m8c0G3p45Ke80wOgNphBPZ7+60PFNMnxHw7TD6j U0fPS50bkXOG9s3T+nqQe4gGjGqe967rrDasmaQ3tDrt8C1ep5/6/pUaimj/EiFdO9jacVHM3J0r xOzFkbBEOLQ3NHTydWfiauy8i30rbHYQJxTNUX9RC6FYdYv5ejXXOvAyUHyEEkMNArQMv8g3mnji J1oFW2D8oqeqseS9+ODFCOUvU4remVl+UoGFaboR7UKm6CfCcTLsQOWGNb1ezTJAV990INhGmiaF ejzyf2b1CzM5FSK8q2HCbe53eT+5wQ87F7ZFKlB8LzwM5SS8JE4fQgghQ2wfxSf6so/BMENQ9W+y BOulNj7hr1LBuBZDNhElICluu/I/5VjeP9JWmHPDbRZFt6qBrb/xgg4Dxdnxut7bhsGI94VS2nOI nmDyM9TuXM4Az21cymLLtKgVoBVW6wfQ+BX07/Cyo0eb2XweeOeUNkwBpi9T+/ezxzOPTx1ljXIr WtCrb+ExWqCVHTl1toACYy7IV7stCLpLwo8gCUytAm9JX1NwEDMSGipW5ljdtLe6rotHZaX5aq21 RF6IDkXqm0x4qN5jnnayebzCZPHTPUSBopKF77/nKPr8HGnLeJkGIiRQ3rN7va+TXWqh0puZrPj6 RyrHSKit/CX9HprPVZ6+fA3zmnv+vxZyptafPDogYCTzllmKm/zh9dAnv/dzDdPygE22pTmYu4R+ 12JQWFlaSy+NBQtA6MwaAJIC5ZV2/nal2g/qlvs5konSwwHqu5NcXE4vvXhf8ZXwp8ht/zCQ3/iI 7NRp47g/IxVFPXrRCNJEkR5yfsjkWSpXlR22s0ZgRF7h8gF6uYkOyWLo8K4FO4fvTtpTWOdi7jrY cTKiKfR+sRGGUsoh++C0tvOd/VtYv///DrLtrFYXk6J1gKXEe6l6TDHQSt11zgon2IDeCN2haCY/ 5GxD0hEkaQVF5mv4SQWj4D4GOex1GiTI7q2aA1DjSRYlUp7iDyjs03ZuCA+5dkEZ/K1Gdi44qfAI XWRl1U4XoFDZ6rq/lJU53h64WHsOTNFvMvzIFv1/nOKRMy+3UPKisk5pj1LVDICrVPyEsc3zNGUC cswuldipgvFIL4mD0Omt8z7Ro3VDq6baCArh8PZLec5yn3Gkwl0NePOFz1/A2QCxbWCo9xc27Nts BVhkwuaJ/9yezz/BnK2XSXOTqVjnYc7JCrVA4rpY5yFaqnKgKR2PIXmVjdCKY1vYHdFWakeAD2B8 8IVBWIOkv0RD1VbcgTAi40DxghZlrJzKLKmxe+OWiRQJn41HBQ5XNoUASPI2Ibny//U4fG2cWtau jXJ7hYcCbwnCldNhG4xgyC+JTHrHNGkSNNt5hogyOix11lETZKr4s+DQgFpzyqIKtGedIw3pFKIe F39I93TJyTz2xKYwt1xtqfzXtTwb9qyXX+W4wZeKewtbLbG2Wap3nFTQNubmXn7D4wZnkd8TTvj8 0kIXC/2OwAC2MUakB6AZONS7CM068yNCzgW4TclTobMA+sDL8XoObUUDndWW4bVR6G90JSryW6NK FXmxhQwp6Z8GwmQ1M0e6otoDjMtCQNpZsGSoWXkAxjrv7jgi7P53YJO5jFU5dDJTYFUpiyva/dQw jkZRxXn9JU8yt/AP8PDndjAHCfeivNEor47dfDcZBeiIYy57Uk1qnHx3vYCq+qQa3B9wb/f+Ojjl IDtjWbwYuHFUH2FQWcP6Cz1zMnTPO9yH02fr6I/6RL6enIjnH8bc1jSqy+k8G3O8qzazOsFb9P31 KeAZGqU4uLsP+nGas7bMjm+au4qZ2wFI9dhFF3eFDztnbsxH8rG59Q5Tm49dzZEUhk4zH06phk7k /p9pgFdXQ9kTDRbeXgBABgiGm4Par0edFyBwnY29F1+0S7oy9gorja9jhHLuBiWkCu7/s6i2wkIa F9hgQlhSx9m0zPEChwG1WBtQ3Dt7l+5iaVS5R6MzwWj00BaIJ2oTnKrCNozH/SFnIVw67x+hJcv9 qHVn4ls1u6TsR7e/Wkq504sOXB+1L82XkNDWWObxRUpvWEd/618k5dryT5lqtXYEeKZIvyLgoy39 0AXJfR6h/DbLELkSPu5Yo0mfNIPoiy7raYNCkKPNHFkEMASNyF5QPTdjX4mj37PgcsZSzP4dTM0h STW29ovkIXsCu237UHBztIUWS7gC3v8OMVYHkhnL1k7NKfjsrZ90nr/OcKY1U8yuSxG0iBT5OH6S m8wYTaFgah6af2VmF7KzhE8Fh8GbJa5Y1fnGU0jq35R4qGHzVHioM+O4oVFGG8qxP8JJbiR/rTCr C7CG4RMCs4GwNRjfkkEUfVWSBc6G5T+kz8Xrh9gnB6xylwT+Swx5nceRHaBwQYkHI/ZzpOYoNbhn JXoEgoAHa4BEWK3kj0v6e9NBFcJ9pXypfnLhONyj9bw190Fb2IfhWrSRkg0Z5jpt4/CNMFxUhymp 9LOoh29qnCuyk+K6EMx8nhnWrjkdZrNJBzBgSW53lfwRun5cBxsetfPEKd8VnQIPM/r56TtWNjQ3 IbD4TzjTdlxvAJck1IpmL1pVTZaujrhMXqwJazQNJBUWEXUKdBlyLaEeooT2qE4HygHAYZyvV1Jz fCCy5+0L51ynsvfBGy1NkRcvyuqKcliT7s0nwqOM43YSRti5xwjQfcmob2yRCALj4nh7zNHW4ojM OShYSDZB+C0EpzuMxRmhg1JszZXM0HW2G8urX8tyiFtS3i7JUGI2nSVLU9Nd2vMgTcOAE1xKKdzy 6E16hLcHmWzJ3UGVvyMtj7nCwz3VTjVCJKTp93nePJx+EDt0QUj4hgUz2mv0hX2gPf4pDAHintHR aduanv7VHwS1+pTnLg1IVmU0+l6hTUfaXi+KR6r9eI+bGV2Bn0vSNRRk0pii4Nd9aOsc0cqQ8Jz+ X443dQTyS54D4IjTI3Sd21mo1dtqXVhJo1H69Bzrl9rsWsx5zujRSQhWjU/R2T+GSipNCDwe2Im/ bTAeJ/5YDGzKlDPDC8XTVTcIwRHDDFsIBih0HCV8kAiickbMUeO2+5GsyUY1WWvKHhHyFfV6zA9v sO/kXXrH/WrRS/OAc+uQbF7JqEfWe1chC60/bwwomqQ2JhUB43Cw0zlU9Cc6MyaBkpSv3lGrC0fU TcuZsALa9urPZK4ouHxTkrOwNZAl/OchCTdWsv/QfMYUUOty0dAUAA67Zom+7h17iMXb4VXx3meu Y1JihxTTJ6darXK26+memPWcDAL77whnwWav7SQTdrUzcede8VA1TJ7PLrzwjuIHhBI+m+PSJPUG BA1L+9OOEOIONqAE2S6MrAAEMNyGoQJpG7G5kdB5pfjrTFKQroHaBaxHfWcK2AhDcZxE92QV84TR KMHJymSRuT1yyk/ciTSMQDSvAomvU2YRzo21Hge1pQcP5eimoQR4wslYWKm1vPmrQbbLe8Rhm21q IuV/c9zQ4JnjKGz1i68AuxKu3/nixs2z0FQPqMg91H3Hc+hLPzWlVL45jUrAX+LyXUqjfLWNFto1 4zVOfGGCR27XXn/qYeEUNN7kLshu/2t6Z91OILTJkLidNPZe57mXry/AEoORAhjL1/3tdyAtwGmj DbISNO+csOEQoy9piASoj95ul5N+NzOBSSMg4L+LY2KKfKULP6grdNQkjVqHW2bUJ6uvOSS4s9nz ZFesK2TrLVu5JBuGTUNgxey65NNOseFn1Ne+R+eFmkhYmSEjhiDrOtQPeAihoGiNxToWNoJoi0Q9 UzJMwjFRvI1vVcPelWA0CTv72Qx40nQpOH0YYnqLxshHB4ggjgKTn1oNgF92Prq96KE2jqROCH0/ jyGelFFDHTNoGG121plnL9lTz1dN/bpeAY0jPsGeQIvYMe27LQdNyhSUsHogpq/o+LLtCkOBKp4v mn103cHZ4Pyp6T8ryfq5N+JcxHw7NqMiz+8Pkng7SoMCjlyRB2/IOEKHXHNzMGoca3REE1TuaQrM gjaAGPrG3jfZNK9z4wXnJK0Tki68kFQXmzWgpA3bnopx7WEHXEMoezUC0OyWd2IHkarrvdtnZqQT 8Y0Xjf3C5FTajx7ahzl6ZzlBBV0pUBLwNtnsZl79E6b8EFE2DnUdSGaqDAY5pH6Uw2Ktx5jwF+4R jrdSrqiygkOWP1Wcs/Y5NOvwlPhpfAsu/nCFwQE0KOwis8HCucm17h5u41KMKRqdXIYVLPVaZUnW dFQb+qzkrrlKHDfhSlwBPPwRqZQRE6Gk1MZ9rpaBXMXdMy3wt+y7JID34u8+OrKkolLzYRhUt40A AYaPbdn+3xNI/Idj7Nu81CfxQf00LFHFlzkIHhyyrsNP2K5gejTlDF6gq2Vmi2WHrDons/Kq+/i8 VTJp7CJUsk1a9sVfYTjQr5SIvbLJbwNCwpI/sfdRl3+0z3GAm3l5D47WNeQwk8a8mdSA5mBR9+eh c5XWX2Ut2sD3er5btOI1H5O4oVWtOxIUpMl3/zunr1MUAfNG3NBNZPCd6ik90wUXGbljFAlg9NuI AlLTo6fieAeKoCJ6CX4SC1Noa7HBQAsm+z9cb58m5njlYCD5kYIr9mx2STYtEGeo29BXkxvOIMNJ eY1qLq60o/8Tm27gVwBpa+qq7n7h4cbyEMEoxyu+U5KrcCaB+ZG+iTFtAO9Xodhtvi4DrNvzNvee MfRO+b5RyN3ZMFvHm2hmsFeXBDdQribx+SScOTZoYp0gH80P2iZpSkTyhj/lBBhV2afEpaP5eXSu bW/Vpa9sPEbpaVOLICY4xRRXplqnzNJ6Yo/YRYs4xGiCLwb3hOI54/OThubGlnmZPRBER6Osrf+U lE5SIEpCf8gjWq7n+esZTXBlxgECJ0CiuUzhT/l+EmqNDJbQa9wby4HLf6zY5jNKoxycVirICeXD +UGxXyWK7tyJsgX9pWOClqoYLn+08osZ5Uuoifo0agWszzQhxEEo4i/gztZJfi/Q+5T9YcdDhrZQ /Ywd5UJ02W3bFaL3mfjw8nDJzVH0SQmAyYcHIvlL3EKv0vUUx9POOe3kTn4JXxXboRU38HxOkOLe gD6E4Q/0FYZjXBSJpOG8yGx3K6n3OkbhoEEnz1FtJRCfOgBcab1BWDVqzTaLrcItCuBuddRxLkP1 HEiZilYT+Fmo01kn57rto8FyXyzR5Lt4A7Z/RSH97zN5bGqnlTDoG4mFB5yx82nM+7V3QBJF6mGm VXto3l5wj1bydZ2dmjbiA1VCtmBrPUn0MZGxY+ZlmeHMelD75Ol/MCGhNjz8taq71fxTu2YanCMT fgsQlrKJUmNtxMR7jS0R2QYSeTOk1IeCf+JMuEgb2MFmQHr7xAuE9ZQH3hjgsFbbgvgcQcSbeqGg fsHtZU0SGxQdkjaNez+2ZttzmCViSDGexQE7CGFsMs0/2FD9XCcXeOTWjk6vPxe6UWShaoOJ6p7o FoySuGx/nl5pwfUYFZx7cZk028yXeU/7ItaXpYvlP8zpuZ74qB9OrRlpP4Lc3RGu8DQzxbBRwdqg 5fbfmOfhsvMnKpqhbVd1FgwGx3nVzNd0tGPv9dPmeZQG7v5PbLF//ANksoj/6JqKeOgrLkYhs9Mq uUUbgJjwPETljklJSrD7MORVv9+CPD3X5+/how5DOSbm/RdG5gMyNj9SCJxVICDQjRvpeaNvdFAx yLwZTeP8bktiYTs9rweXoqXUyB/e0pe9mZdGZDms9R2sxxXrh7U3vmH42c25x0E/rW04gxfuNba/ 3IEuBZr9YI/1ifv+jZZjbDnyMNQUyjk67607v0KAya4KcpDXPyuRKFFC35PpDC5HGYBAp8X4PvzA y8rp/7vZMod0v0lBUTo4Hf38XoBlOM8xA/E48QX4eOPR2+FFDJnfEGR19sPsA2L38ZiSZNwZciqe Bvsm2ZFtiaHW6s3MER+04B/DFhP+1QejQt2c7jh9grfmEDQxTwQY5+NgxWt6TXodxybas4GhNVdZ f/JA+0W3sDdD9nzcB/1xjkrtx9VQMTjZNN5c3vkl+z6TzZGUCMdeLpDi9SN/51ZhfReOgeXTCa3E hubSRF/hiFHCMYKACiklzVrkhPe9kQYGLBYqgTFe3RvxZ8Zr/tJhs9N5J8S3Zs72eL3H6yKmbETN l3g2V5wMS6FOm4Rqrzu/JcNE7EhRlVHKLFIRxW6HL3FHl3my1pKmEqasGV/Sbnow4uMqkfq1tA1I 2dWmIfUcWatM9c3I+6abLrm5uaOB/3O1eUQ8SUWf8zHayf5FSCdUSeaD0G4J5PiniLQbs7s/ccLa GJi05e54PjBYEKNozCWZPGlBhwR8+oKQHqEClSZUjiYtIRUCJO8PIKpCEC0vZP9+Aanx1rW7gBEr YXYmB8w8uM9Amw8QLMEgRe6xxNfGyVXIgPr57uP88T34ehu2FjeqngSRAnOrmFq3wvLbwjnxTf0F vCXz76J1opGfvMYp1WYO4ccxzSgqdVnSQzNp1i/wO5XDFWVqN+bwRlQC4eKoWJsI/69nzqVJNBpU 9M1lEE0aG0eJUAcqM2GAKzPG6CM/6NAk3/u0jGywuECacFs8jrNTqDcULfyrGkUMxLrogxSPw3WB pJoAybkSFUX5EAg/YwJE0OC4l1ZEIfaj+cU6uOKnrrL3KKcaHcyxfpg3rBW51kde9DLNRnY4MD+p rNjwqY/zj3tQ8zEMnhH719OQYqJut11SPMguptEc2qmw7wMmjHnEatXhXTxhAK12rMr8Yay9tMk5 bmAxSEACUcEIvzLl5srSlZJVMCmv5jvmc+C/LvuAOkkdfpg9y/LF8Z0jYSU5A/FQARJAas+yL0LQ +qm5r0IFCZI/yAppzLW5dbn0y/n0v1rgnBA6ZfauAoFdZfMVtm5NzSOwPMG91EemHnJ53TPjl8Un dmOVkfRj1AhIJUZ/gNrNOk764HsJS0y9LB5b7eKkNDIYoEjC6MAaIbBPkzKOEATe6JvT3iJVfR1y pu11pYWj5Mq8UzZIlF1V1/JLlnM79swBRSPvIo+8tScGR8Z1AOYXh3rC1yTf5RDLNw5+Vta8dEkD BZg5WZlW+mHc6ITv5jBjFR0/0fhnxknzNlhtm+XFXpcygb0qBoaydZRGGtGRyHiOnwa1nZL0E3n3 FelQutibzH+zC3/yRGeRv6Kfx3HpGppkRNzn3Tkbl3X+WaiF45PLbUIVbnYRmDl3wsFtem75rCmP Jatk0d2XUeH+opCj9t3j23W623d6OTYTIRKGrlj0PbfIEJGfAHl9LBSnV6N/DV1YzEYOuxiW+ZhR iAqpFTA1eB8U5rYPr/x2WQR/j3x4iOWpaSxVBWt/FOryWLpmfv/oeXguxX9IZipDAu51Hun1nwud t/wE9eJwu2N06QPuE3BvC1vhbqKu+6rb2hl0F8XIae0bv4a0OTpT1Q6Nv/tB7tVIsZV+5wQ4kiML ScpUFLiJMwFttMp//QefN1QnW/SdllqxRaB6w91WKBX7YkIOkmBJ1gNGxcsaMQ1MTmmeONqHkBnk 71SiCoI+WtxWlCpe4fLGxLe0RualQxFwn+eDXganHpPZkWL4jZJydUjF5gEAiJ1iVlqLDZew57wr /fnk327Kn39Qlznw52csbkqUvE1/yyOdp/Ehit452vWATNhXmv85Fxx0L/c6KK3a8QHmo/BgIvzs mxF1mMHjWzyd2XaiqZSOhbrtPTR2XvG0qAUYCWp7oEvckrbEjU4Rz77ADCX9Bx1J1U7amS56QAzw 71IoE7AYQo+eB6XkYNnMYPmgl2bVlhNxB3W0r9TlWGIa1EztbGoEbRXAUNmWuIBrB3CK3IeORlpE Le/QvYJlcN0dbQoueIYEADbcMq/cRT3i8SZ2lUgmBCJetwM9a7JCB9k4Vkv63MJBkvW/OYb0VqVZ 6hvIZR4qYYfjsRf3WapwXtbrOqDmjF6wJ6jHuRDergovvImkx3on/YH3FGlo5PrlJJABBLVqlhiL tDbKbpPDx6w1cNfYbJ96nXJT84D2CF4XAtnLTUPggwwqJmXGAtGZfS4v2TLodUQOsudwa670hQA1 v61yxieJAbMbYQndF0sr0P3/AJ64ygakk/kGuzJUMXO2Iop99fi7TWYe9Q5HjKlXr/V3xu7/GqJe IdDcVt1/e4LndcnRw8o/iI4auMRaJuzrM/XoNvdyXWDU28okRc3xS830qM9Tty3e6Yuuqp6Hr4z0 PkCAAjPBxz/ELc3nDsLv4YvYyfMj3pfcR6e5/gF5YxeKA4MpLu+cQnY29ZjAN8jy3TifyNIREWVu 0hvdC4tea6vhHOUtu15uCMaoA/DRN7gkMYWet+IrNtOom+qwB7jsxHxWUz8VvrH6Vj1aw4o2lWWa 0mePHEkTublY/f8Pn8kseuTQEEAjRe7Fxlwv1QvNDmVqEUyxG9cweR032jPmNMBuaWYYcd4tL8Nf 0cy5yz4QiiSVvzqfPuLhr8yswKsSKCHZAw34K3kHck4gg1lPA2gwcjQmoA6u3MmtuUyfwlT6gcnW bBX9sh38u1/IIqjBzk31MmJa78ibuatUZfLDW9I43Te9mdmUEd1WESFaLD55f5vMLSj2VxRmunPZ eP2KGuWtoyeJHjSHcLb4+RQOofFI8kKcPe+NwH7Yrf36AfTPyecDCWWrAJaMLAIjYi1T4JibA6Je wKAMiYzm4W3DtCSqaRlKtcgmTC/BchQcA7EJ6TVNXkTSXTsI4rVko+HCOTmtnig9wQrMGwKd+WC7 S/Qzr3voHqRtcAu1Ee9AtziTBSKYlh5pUeXpB+cViEluUPmEXLI9znON37JTu6E3eesCyZdLpB1p ketOGNLePK+X7qrHf2H2lktj4qvcS887Rl1GBXIQW44oH1Uqq7B+9eQy0t3O0UzQ/lLvuAlKSaUI kSdozyKiTt0hj+eq073FTvxl5GzfvXbrRPrNB3kSarBgVmIbxqo+XG/AU44PsGvBpUqQR6WGFIXS XuakzZ2XEQpP9MYR9uKhuvquJj8uMiozW8Xyd1NfKqBT/UtRqtXuqytHln8F5iqIjkoALlezwymD mHmXENteFZZc8efJb2FRfibFO4f8TnXtmH/tLsmcm7ze5UVbejxlaOpVqUOpMsyM0irbxUFmEk9m IN9JS+MNBFtjjgk3nbHzi2AO0YSDxvX7pyYxmbToBj/RMaQ/bVSWVt23ufAlG7EM9z8m/aj1uC5p emgqJOLuOTfEs5A/xEkFeZ87U6Qc+6DLlDKDZXmqAZbgmfKQr3Upo63bSon665Sye/FTYSg1fWvG sZvCK3WCUT8GQK4bSV9WywwV5e2YF6tvX3whMKcV3t+iQG8fljekhRtUKE6oF6Ot574cHbG2WnoB S+XpGLOv4qXLUrXTSm6NR6U9/+/B2Yl5sJz8ZRVmBIyXFJ0+kWFqycfgZca7CCYN3ehZef4rRR1Z x5/vYe2AlDhn9alji8t9Nrgxk+pC+UhehEiwTDDeSs9Gp2VrF7hE9eA9JBUNd/S9iu4wTSXOCib6 13pW/WPMHYTR4VbXe91XRzr4zNUv4uckhRlqTgwX18GSBAHgEFQo0BEMI5hMWjjjlqR6r45keJne iUTc5jaKvm3UiTLoP9P4yJccxMSGL42gs7DWRCRgrpSyH/NxKYzhK9nCmVlBrb3TAq56DAiuE+N8 m3xmcFwMO/rRp95o7Qn3QbVKZiv2MPyqqNCTZmrqJZNC/nQSmeSgsVWHAZXpQHLqA35pGlYbrE8q msk2DYUJckxeHPhZ2kbam2O9xKusfAwh79iB1IrlWbF8+KaZjr4U89UyjKV6uUYytk/cPbj6JHIJ tEMyfBNCzQljph6xlSUklSFw+63dP/f3YdNIwegU5i7fU3x8Y7GV9kWYdal6a14Ix/V1VvxU3i36 34MjK7w/J6QhobYom0D3Xs7+umrDVJ0PQnZdDgqllTmbUR7sGXXNiJTSMSK5pAAf0idApFQ2eZbs Nv6ttHqAAMaP9pQykHIOrZONkwzPAe0EXfw8fo30vqxYe13FiJ2eJHk2W891ydZIzBci9Q2yhCpq DkQit/iVFEsupVj0302qmacdYM/kNVwjV3T6LOvp5ALGuAgXHGRIdL2q/VezIZ/lbfG27Zpo66+n EuLRBCMsL6Fov9C9t0RMFmlIf0/6zD3Zfyc3KXNKxTgm2j2uVa+BMQe20FQZ/XNsSLWbWMgu8wro vqZXP0ylT6Fz95w9Vm+NmspWingXElruk3PEGCIR71Oe9HoKthf5XWq5967tEV+RD1alp8Pns9KB SCQqzMPeOEdmcHq1Wcmu8w4juPN/Dxc/vn8risqbVJPKonVGXY0cRxkBquo+bcdtD48GLKHiTl4N mWZ6gWpwmDaRepgzWritvlQ10wZfcYu6Huw1pmEaTn8m0ZFWrUUITo4DVpWpiDW+SesiOO+kY6rn eRb9fZK7SajyMsjVeyUMqOB1fAtwMWVzoSyRv6MwOXzAyxnhEm9S7d6oFSvg8CutZcIwD9vE+1Pv qNM4W9v83V32rsnjuIiBL4YEsov+++3mixjOUHSQatVNdvlvDdHVbZWqMibKwQHJxGLLArqtt8Yv C8YvxxjLpnhZ/RI4471bSt77LpBDB+16qK/C1RE7Lpschk9kDhdjrFwkqqpH+7D8gMj7rrR6dQWG bioVnP7yRF5fskkLJ3ARoziPupW/2JeF9xWPX8QUDnjaG87xC5M0stkxPzxWb4u9Zwl5sOvcWGzD 0mQh5R3htt0GWu1uIAG3q8MXnw2mSAuPAEd9ub0SNHd0+QFRrC5pDVsfjtfGQqMb9ClaCgDjqpTq z4WnJYC0KVvCuPqwBEufOwFWhjXG+noAcgtZHhEXOI+f1MldiynFVPRSq1VZTGxuByozLs8wEFSt cfnbM7O8dqZzlQt241M5hkKdoDFZO2h7u9DgO4X04emyd1l49r9h5BwtXC5aAYzL5rTc4VsxC/8M nSVH0hFwtI45SZ9OetEtKIMbm1ec2ee9AdJuNZxFgtIkw90NW6lk0bc62kHU9+yrYFeplSApYfSr Vy1dJXQR6c/8LF/YEZer7U/GNOSMfjdbjmg0fHxW3azkkASXGeL3taqDAheAzkta2xN+RrTjS7CR Uu2WKXtg2j2lfKmm0rbwX80uRont69bim60ro/3TwKlu7TClZBcIYBdYRtfs/jCq9V3eKiDAESqm CPa/gqN9h4wOuanTZIH7XqiEB8ddTNJFoNRsB+2x7fbmgSVFtxqBNLAhSlhRLZiD1Afkj42ARTXw mFrw+ed2QmJlCkinwWBtc7ikK9baIm0rmQUivTXWvy6w1BLColMhOfvOKE36QZfUgZH2GxBmwMLj Nz+PvW9CAPIwBTbtEb+cE9ShOrlaAkoelo6o861S4UOmgqwLfnsZohTAUpGaPPOu6cvtIAOi/s1X znATiEJo7DoC5E9Iiz9BzfIlroRMVH+KB1GwXn3ir9XYYTyiYOB4rqk5pxKNB24q/4Ouhs7FbJx2 JUxb7loN8zPnHSZvJ3MbC6xWLLmR1fE9AFNke6lTT/2PQCIbkldo5jSOJAQODBPFsxE5ZosJU+Y2 aFcy8MRJyuqrbpGwPiG8uiItC+1DwxdHDdyUDewOt5fl6M58VrZrzCn7xo5oweWmYlM+vjE/NGUK suLf/E6cDB+5tQ5cDl00bNSvJzKp1k9AMgmUAil/K92EzVAs6eSoIjOztPGRxPxKs2dSgB+09bFG blJjzljRzkkx4nuyhWm5aKzc8/pt4oG0lg7q4WxpHtdquDbeTrUhHytwpvISwMK9R8aABizmkVB/ 8tzQ+xkKDBLBjErlnTug8wkzj4GmSr7LrtQA75AFpjDho3ANxkhZjGyvZNS8qPcrUXDreNqr1pTA MyOJVV4UI1dyAqtqUzoTWXoLaSB8ATrUMUb5PdlWl1xD+g0ZJBLgmdRj6kTbNrIz4VZArWnirKka GTlYn4KneWpAvG5bez4Pvwec49mhrRutgGZu7l/jfDZXr1dcemnDncCKriAC1m8F3Zn6W040X2HM YMVi3F1v/QrUHerMAz0qHyNEUdbJUClD3rQlI4ukWqpxtSS5IEEOmVZaVydkwELcIFRU4kMl4mqp ZJ8WgREMt1/Ryb7eLOKFQ7Lu4UCcIh0x98Ql/l5aWTennlOduxW/UrK/xDFN28MOoeHtt4mxSZh5 akM55AZz6l4R5ZReObSHE04mI45ff1a7aQwHo8mZ1jhpEYESKu1usWE99AbsvJl/7ak3BLFRLiO6 3LC+31xs6BiWfsJtnIaOOqAOMl/QYkUcslKxVsad8pg2X3gnEXdGwb1lxeAd5/eX9JOVhA8WDdyT pcAVR02tyW5UN0ScqRFSusUtB4fj6JT0xB+dl4As4+j3NIdRbxMYw1QNfEHVRZZK3G0RZxzlrry+ 5XpQxAiKOcT1nVxG0TLNCbAq4GxbVgaf1Bha/qpagw92VaJELAKH1xMIXQqRzWC1Tll2GH/yvaOw DT6SKJHR18RKNt/2B47cSIHTRLFR3QGWMYYWv0bpsOShDWRYz1dmAzxZhUG2xB1ht8vM1eyAY4SS e48F0C1L+G6GrzYPcgs+Kg+lU4ihFf1PZEswpdOdlHwXT3+hQ+52QbhQe+hImPKcdbvgY3J/50Sh ANFPuzA+UMPcsYDruWScgUyzjMnA5yH+L2iFkbVm9WDAfGCMqW0HMCA9QxgJ9n/lh23JdbkhCE7p vI2n8S4KgeaBM0Ojg0Co1/DPd+Muk7Ksy9sJ1QRTaqAJpt5K8twNlQMDIGndJ9UOgTLHz2PtQz7B Kjnzef+swbH9vJdVCVPx2oCIyv0rZddL4N8O8sLf2EG3iV7UTGKn+xCCN6WNf2P8KXzvlFkGh+2K uuKMrEmNKLh8AGrI9r7EUjuPRB4quqSsk+j2yEGBySLUWiei7IdfhOZVEBU4T4VKs8hO7of/LLHF KA9QQEUMKg7ag6q8lnYQIUSdS+vBX79zhuppKew2hX1GfZf7fTFulx7wUiU3q7ns4YvOejqDEs3/ SHg7kQVKE6ZPW+3QqdAf0KprWUw5aa3vJ2rflhEHOnZF+5YYRiAOAW2+wllg6Kdn6i+yGQ/dzoMS L6O1AO1baNev4SIpISRvMQQBO0axwaX7SbEq4gpLzg/N2jbUTxDI5FYFfLjcFFuEO+qDu/OnzZ6i U3PvNiGCPn7s4Q++5bATHg7wiAXfcGrOjYZ4BpvV/BvRKYspHQd09bOZO1rYhNGMKhWD+Hir7Cup wZp21kEfhJ7mk7Z7EZmkyqP+FGA6043y1NWCPf8A/cATWE33fWPJN96O7ctcHM3yT2tvsEmLOkKY 4/Xb0G978YXMMLimjLdBUJ8YOBEa5EYSTbjtjhK91NKGhjbHl91Onr2aCYcLE+DW9P3i5h6NvB1J EbwZAf/LA41YT25LYvdN4QhgsRyweIT/71sRlTZBTL7iDcXyYfGe0dRc1GKavgWIzbWTmXx2HqFQ RL9ociLoXWk3pnWLjJmWCZqNaPwRqAcMpToUSEL0VJ03cepIJ1PPrgMFTdFlLjDsgDt55lWEOIjZ nR0U8XreouB3wec/21/BRNg8kwPEjk2HuWS9huWUn+t3YhVZyJB4oqaUdMVnK2VyQCiqQgirl+/S uMbe1Q1FaL/vJXhZTOB6jWCnf45RNTc5qS/s+4Lk5UKYLek4iBpex97FpEXa3p//p3JsL2OkI9hy IfyeKyFB38MkHR5fDPDlIRgWPxp435i1wPaLcKZ/npLM8qe60gRf1vIck43WxKiP4doqLon3NqWE K6YSh7HEbRJFpmXBGW/3J2KT7idAqOTEXjS7+QxtwaO/efUAk202AN9rsO78B8g2BifWAt/vXsJ9 qIa4NMUH2mkbIJWoiqShbcBMowX5ealf3imjSWl32jJxP8g3SGWlMuIou5T5dcI17NRFTp8bx6kK 12sFQKe8e698G0URTT0jdONjjDpyM2iun5e0MK5NkFrmPlq3Z9PcP4YNA1L/Za3KGuc7t9Hpvpxw BbUGf/rJ/s+HYGSSFGYLtTuinHoyWKGT6EDbdLcnDGYGRRseA2THgeNrbY6WWj9oTGkAHfIbLAvs 7OxMGsMD2oiqGVWWjujnUxW7J+E6Pnu4Lg9wWj/y03a/mvaoSexi0lwgxA8ZWjCxS0Xs4mUp0UqR FD5T1v2es+XXhodBnnAW2eOJDQ2upvd384qr+Gba7AzVpfa3nanK1/7wDrjaQcAIy1gC3DuI573S IsAuR4AzdeWfjau81ai3EbRBLBRs3HWEvcctlu/V+T6zwaTbT7w2SATfnIslzEVFXNFxlwCDWE3I UF3c0+5NgiIsmmzkbR8z+eKRyByDE0yE23JMPLA24lrkoa3eEoa2sIr70gFDC4iQ738XYYQqK/R6 AyKSmjo/vIUb5zCLfBEdb5TFJ8owJ516lyLZZgyyriHoQGqeZaUkAfoZ1rSHLsbJTKgUAqByIlWf 7pIWXkzsHs4wl036SvaesqQjwhTfZKEVS25ONrbcnf37T/0FapolR1xwllP6C5dbTDYRBehbqoXl +5AQAz5idZzFc98sUQSfzX3uJvGkmN+7l8l3m1O986NbLiWA9F5oCJCLyLnBsXMi1TFJMva74hnn Bhx2XSqRwikYbZK2iVL6suHxvyy1LL26ESL1Oh3JoQaQCVyI6SF9LcToyhO7eszytrXTY+SuM50Z UyilimUKCEZNqL0H2K8KQBbkH6nQuNf/haGzjIQPmam60gX/EuVEg8G5LopDLI2vQWhW7zITmdAC Ow49+tZUNG8smXsXG9WKHHKu65JoPfPoKazLr5XCky5YwuJmAZ0pJ8JqHAZDXMBwihBWVD8S/DSW +cZpwQKVWQOf+NwrG9jGbePmbA9vUNSIZUyxPCoGdKWiILVb7T6WVrAD8kWHs5cBuYlssJ7Z3d3Y gKDzsxNbGbIYWZg1ZuyjCkeypSUN8LSP6yYt4SLmOpaZVJqTMyj5GolkUfG7WE4H9WAY9kwsx4ha DZmvqQbP1WjmfioTsxbShq6w+Sz/WLOqc/KfTkyDdRcOHfFrmLi/N/zt/0OwQq1Daq4mWJjkzHUd GufbUQnvM0shnxm8rzzwhXWWTAUdI2niRm7MAgjavUVkpFAb24V7sdExgzPaUZbqtfBHyrJRGRds hhXtICI2QN5QmLlnjWwUqZBS0yzHY81CFGvpXlcCeVifO6jEiGHaUvV8S3Kv7xEZ7En7mR1iI5wQ bX/fb4TT98lrOG10alxzxF9AHJslaRjpN153JnP1i7EnkS/NK0Cfl8N0MEg7z0X6kQSjJL97a9bL FFzxOSwEuXe/tllMxLWFFW2x+UTWMpRc28vLb/NQQz8j2WYzc2WsT+aXeX+6tj8cteg4pdsxVFwO Rbu/dfdYYDsQ9SalwrHGPSi/pEwfPQI0LS9GYA4O53QiVzFIdjVQeS99NSLYfOFVZakNzm7qditl HmXZbWIX+xtvh33q07XEmoDt0K4jZEj2PXJHMUqOm2ujOnvTwRAqkyKJR9hiylcfaW6i3XPkK4uk qUn9vJv6vAiXYDgLOJwhHj8KGjuDFUXZ9WaO+Mizijk1q9lQQ0oj7agjzJpzLoMjRKcpUMdkWBN4 Z2BiQdLRGlNP9a8ywPV+8sOFZQvBsORDbRHbnrGeDX7V0Z3LTYj/0Q2HcWvkiODtd86DbBtO2bb8 UcVsk0mKdub35Bu8rQaCQKl2cpobpVgFngvAFfcJir6CHZAup6V8mC1O2o7Iy/SzaMDIGUo7mbMb hPFuoCGmueJkMtmel0IY0pM89Uhts42diZhatR3+HSnRnp9KffpwHcfFMhbSiHv2CbUJ+qoIlk/g Hut4Ys2NMtEIlPQqhIsL7ZSnJDoHv75rrL3Nq429/ha9a/BjHRNmGBvrXlcz0PDc4/w7GYbMVlII WHyvEj2XbCMKN+p1KKsHyr+VwMgpiDAvDlRQj0oWuZwYAK4AjZ+QndraQ/g6E/2XhmNJKcUpb9Ib XabVh1ta37CT5qXwCzKvftSLktnDvfUW5KYSy5KMYCjtzA94ldbB0JAyDE6jytc39OMBEaOOOX1j ZT5GFN5BcKaF3bgK1hS1numkK+hrpKahqlQTB7wKF0pN/Bak8EG5V80U80j4UxIL3c3a7XzOXiTW mBr0WGHN8UgLt0q/eIpZ6OAbJfO2IjuS8vNAL2UyIrSmO5r8PXFXC/pyXWMV9kO3qJrGNLMNh1O6 0XhT+ur6hjkGAlYWSCN/cP/PlOMRMj/KPjaggSdCg3Xynn6DF4/khWGMtzJknISp7QZpT77HYTv8 Q9oFYqWsqLoqicmsZGy3e5qolo9kOsqjT1QFYBq1cSQocYplm4xfPedll6ZELnlnT5czR9ngjZQx epenG4Am3XuUnhiomws947dJZ6Gb/Wfg3XGwUFL1RCWNScjIDIg4ajv8wcy0Xzp42Y4LuzjjwgHu ISdmg3CudARDrwrHxKpIfmneYpkBmniSbri8XL7qTh0uQzESwowKWuzCoE30jBX7prRCoyoFCgCi qAUU17WQWEZcyt7C7ioub/mTc5GvGsYFc6KqhRZbn6q1VfAh7CDf/HCzktWZy7KI2ptCHdICrj0M EN4SaEG7MYJbsNd2cuU+/2F1OvOJ8SBwUt2mTMPEQLfW5Zq6u/d3YTq0n3pJERY1WmeYOibJfXR5 ysDQqIb/cZFcNVJ3wZiiMiYTFmf4kRXNU+5kDGeq7BZBk9UaOgC0O4ukEIePSVLk/UwiAQa4gInV 1Sua/ADwpUWB1xc8tSnXxzeGT9QrKMSoIaoyjKYzDW1Ijcbtg9K4OmUfu8ReTw2I6/LDTXB5f06p lTB12dL8qcJFOee/WsjU/4t9oW5tS02auJirD1/Z7i1lYO6zYY8axP5769c7YiYuitD200KTcP5t fYQg6LxHrPgXW7qkidjFcBD/MBEUynKM1T5oeIZF3GmhMEukSWjLnDo+lXTOWZFvueNHc167yu4j ZtVTaTHSDp3lfb1Tjiu+2RVm5fZlnFcuBULFAawyHDydCUQvXpHmV5sYbYe1+N5pwXv7E8uFE13B g5B2TU0sCq4heZuJmmZvgGuHwIMHcCHuHfhAcU1awkEk3XPGiTZaqaSQqfohrJ05g//AhfcDMkph U+CO8lCNFkE/mA2llowAMSg+Zn5/DAbTVwm0onqepAshZIMe05YG5LXIueRj3thihxPlAu6wieOx 8OLZTtWWF/gmfPQEO8ckaPPgRejDyyUY048YDKiCt+Bt/FybPw4b+m7ixqoplcjYNPQc9rAdQTbV gmPr+S5XHf4HffBids/de31zTfHgl94mFNhlT9exiSSZHDL7U5XbMspe2eyGOdGGQaa+1XNocq9E /sWPakwJyc9DwZGFMaS4XiygVSa9aUotFhyJNuyv1gaO5Gu5zw5Sj5J+7Xdbu58GyoIReeXiutnM yQk+B7XGQ5JfekHwU3pW5ZkxP+YCosLnVePNXcXIAmwGPbNaHTemeF0buMRPBDxwxrFt1ll77OOP BkRRGgzsEorppkBUdn8/E0NQm4gPnZagFPxsqMdnbjiQ/zO18Aqaqgw0P/A++0vRlPhb3N4O5Rmj kn/wufZPWrv7E4vqBwkh9BUIRAPsMNrisRXt6eK0j11o2m9uRcMCN8mwqdg+fTOVmHrvlz7+wfmX gdyh8vtPJpyjk14FSiWGoiYOlY2i8/4AmqGLchhSvMHCyPwyrVgCX23ROqFb4uKwICKf52p3Ll1N eOWD4JKoMLOA7w++rp4y4RJ8YQr84T+T5AtBGZkGyi9jLDJDf34CKc3G1UDernbYOcNqTScwOQs1 l0i5LyQOK58MPdCNijguVyBqm4HArwk/1ts0OKTzPdiZ8c3iDQfHLJRATXmLomj2glMiTTk5AHPu uJ1tTnZsN8NAB8ICUa5fbrEYLAwb/kKyeIks13WnlAIGMdHSHY6Bm7Qbk8ZQBM90B/hPLKEgMucn O1EWlqhWunoDqI6dz+qQXvteHXvCIpg/7T1qpPYpSn0qAOnRMgBZY6neiyXdshqwQZitfViycpiV CEEx7PuLxqj/S4wim2evW3LvCKRGbomIun2Zg9p3GdHjGTtC7dbFOSxbOCzdjydKnxR1Gjn6+yJI I4DGiWl7c4+kLeqHKdIqIzwtZ7Rq0mscrsDvMzHHB2TqGKBSgwp06BvRtYYzREO3aJE9Nu0jzVWZ K6geyekwtvK0jbq9N0b3bneg3kCY4JBuMLsfR7cbZvjr3CcTPclaZWU6kRyFiRuw5JQ3FZyrVmTo QIyeS395+mnpBb9dF+PkJVLPyzLbPKavuQD1GXUhT9Y8QiORKCNtFQxyWUyEBTPb9WrTI2jh4/Z1 rxVxHpuKyaGOH60WaXtH6ZBdEY/7omeJPl2BZ1717sfqCMCsf0qsbW2fyV/OeY0O9ZEpWT1wdYuz VQZZzfcCFE4nUUG4Rp0KBPfEiSp+5ID/8TBnVOXAqww2n7LxAicdoEvPf3RuzgrZaZSHiBKXKDNA I1pki5+KwQLwPVEGxBXLsKGbjkCN5OlZVPwXDbAVoMwrCeNC/nsaLHRYIV/NoFy+lje6Vc4A+Lf0 yp8IqY3jypBOrBn5W2yg65I95KoTFGo6lT08Vda376zizJe15AnYURZMwToV4XoR3WvDzIrkq0Ll WXWyCJw8E/vainK2uoOfgCWqSfsB24pc/odIKqwFiy+AAF/FYBV5z/jFmG5k7Ckod3XW3JGkYYDe SlRL5ZXR55R7i0Z9Ig3EUCyyKuRCeOfiye0b4RmwVmeeyHrnMz/rnC1vER3lHOBkhutxhrzRtgc2 +AwwaCSH822RRrfByFbszI0QZ5CUbiFx1riPZ+OgREL+uiSxtIlcgApevyDvBNQFy7WoTdNhNew9 y3dHnnPJ4igGSSQrpoq0FWra67OiFalrUBd8+CXi8luOCO8LlpHSlp482Ld4NJIoOo+HN9XMVG+d xHlTj1wLXplfuSSfe/nXM8ITLHRQYLhcbQT56jM6wdEV44/sf/wWrfzZcZ5itwIbA/Rni7wRybOh J/5hydXTcObwQC6K+LbhkVfM1TCa7A2CDhx3ZA3t7eLU+P9ITibxHKLpWQsrUY09BCWmfdb/C/ZJ Wmie/2maPsvLLhTrBsx8KhiuR4D7VDLUq1gfkJLS6kQOrMCEddyDYorTWxWnrkr74tD9E3y6RlTb jfJFMpzUQfdBvZ0bfAm6QVbvReptAYLtgQkbFCDbyq1N+38E8sWM0airFjjbpFQFFvA4pIpfxifK c7l8MWnu/3lsGX7dO/fbgoyL1l3OCKnMfuJ6yVSuYP7OYpjlGimILDDk3EvqMNQwOvVS0Onnhh6A 11PQPhv6q+VJ+THkBt1QoBWRK83Wl9OQ2h8ZdeF9QTa/t13fENXCI+ULoDWPSfLZbXrbgANAhmJd kN+8UYpk1AajN5mNUEXI6jnb4d4DXVPKQKHE/LKj3FhZmz8s6mGjhbc4xywiwLWkbMFeoWwEmy46 hL7n0lU1eupPDkAVOdLJokCFmsZkgv+QpQYxFX0xNBoHoXzUbHWJyJZWphzeYvEY6sr4YVeC1eGw /bAsUSJzETYwLRcuIWLpLj+oOpjCbm3/HyfKmAcKDa9hPv75BDpk3cHJ/Gs3ZlSgxxkhjLu/B08L V3jyna2A3H9NtR0xrcw9ZI9HI2gDoCdGIQVU0akrO2CewhJg8/+KLbSGCcrfSbbg0TVT0YbaQoDq nePZutjHAZALIVMVQeLs8xXfK3+D1Tu3a/iwcxcr6Wi5n72grxdFML43tCVDFIECfHcj4R3dKNJo B0qWTIUoa5wwyauZSh7xrx0cSAbFsVLp7OHXF820dr4GIxnXjPcBdK0I1frG5YREcSi9VIRPn07H v98UGlNxS7PEHEaoMxGdpIiRt9u/WqKSuVRvgtVgwcxMX7dht1LcoulpNkuSl8CsdNfEBIaWiemk 4uE0WujPRjFDniqyMJ7WEwUlDfYQUYHsqvTUvpdGM4rI10Qm0QwpvVU6do85jz23wkmuJjRaoJWC hAB+Xi5lx60/3b5H5vF4gXGA8L7jZ1SQ6Xy7j8i93cfkEprFRf34bLiS9NrvXSbOVjaQ4Wvo1kwe BJl6wpg3JfKUHuzcOLtACOmUf0PzUAkPqbJMpk5pva/cnV6+JlwLweG50KFKMyrvxHyyVOiqsh0s XvkP70CBxBVK2fHcE7i53Y93bOOG5kf7sNqTziVFkn6YUeAHr/PVmcBfapyjppdyMIJqDFc9tl5O 8RW4oXd//QIAgQVKvh1jFkQzsTwNjS9uOD8z2FT8Px046GtjR4JPqZQX1v+ONmIqA5UMFNXh0139 sU5l5k5PHpModVpvfoF+nSpVpCqhtPFbMq8zBqykzHH9ttvGB3efkImvlsB7Txn57WdyyK5Ox+Fo wr7fG2693SFKdzpZ6lMhlUQeYD7ABoIiwYYa4DSH354153fxCIb0K552tDUYVpAuvPk3J4SfNxCh WUSlK2AcX29yOevNIJKfUpBeF3rb+EVscYBitCwLeITDkfiXDYlJBSY8Ts4EOrVQ0lduvwfrZ8ut IViPd9Bfv05ZSKtMjNy8X8EobKDmv7bJmwzCf8GtQNlVUQqbkS413i00LqmhgHNLVX5q7MgDDSGr XPPf3eKyBP7lMbSf/q3B+aT3Tv8sqZEWp2gHGhfuIxteO4Yhtcnk0fFm6y8s/M3RpIggHoD22V98 mYTZvGNSl1RXNNPtQ+7uuHgd2UQeLRKsNLSV9l/cKnALBUpCFYMa2KJM98xjxO9kr7KFAa1d0TkD 2VhVp/WZUFke+sdIT9W15rk7qsgHMVZa2UNPi2QcImOBq7K8xAKK+YUy74dlxeKKHN1vhDGzQSAp kr4rqmo7lo7uJ3LJdIK8DTngvBovU6Fl8mC+uQ6/PiPPQzfHylZpUTEqmLf+y7W5etGXbBtoRus2 BCRyyj9TDs8JNV8QPCuRsv4qIwLia2nijsED+97IIZLTVxkbbSn48NaJZm+8tCp+DfoBFfWnqU+A 46Oa4UP9IlFCT5MExKFlQWq0mkKwkBemPFF16rVr9RqrfiBqJshUXCM3XucyOr2T7L0378D7cVfo WeI3IbuQz8rSAw0181kgkQHBawGc9noH+93SHK5awJeu6naX15UZU1BijAOfsrDwqCoXawgm2dCy RRXHIE3dMEvZQRZ6SDoCDprRqfo+W2izFlyvDLSrnrUKkHyFXEHkiSHKkNDm1yqkHCnTf921+9G7 +nXPt1o0K2Egz0HdLZzcwGIWLMccEiO209RIzbAdTMGkUcveNlA1uuOkaAllvJfEXlUpMxB/VXhY AIo+kjwncFHKvB7fsEnvKoJ18QDRkwGL8zjGBjPZjOcJFD8aNHVoyA0FM28PgYIjG3XwJMfFYMfn U+Oui/3ql9T76aMgoAE2S24gyMVWn3ccq6sjv/7m2QPq/CGEmg5Q3gjj/NIeC9Jmb5A1lBC3XfSy t5gz7EIpwkMdKb9XN5u+ChR3ARDih5ugei7dPyurGKb91pNrRTJ2npXh4W0KyMgqrJ7Y19KWf5m0 q33b7HebmXbueFBWjt2uonA8eemU8F8MVEtuwD6UboWzFucWXoQ7opIwRJFkYV/QCJ07M/mEmBGg hQnA9n65+uzD4wJDWKGVOxjE4hlx1aYeCAl/1oIUX2ao8dDkFfp+HEqSDd2Yad/AIo9S6g6055oq 0XB33ApHaaGnNqpGRIc1eovn2a7lDcyHupZBzcUzdBMDITyO5Vr7S2Heqpe19imisdWXXwaYaQLQ mTAf+VpUba84X3DnmvWurif1UIzxSDQiVnk65JZYWNboLbGFfaRi8pwd8oXcmPBA4Nk5ISWLud/7 PI3n97uHLiAXH73p9C60bOqU/cOq3Z3bgdyAkyWa5TzSqSO01pyhxuF84iqsIbR06HcQogNoj+Ef CqO+rq7rn/TwKtTe8Q9k4flhzJ7DvRV2CdK7OK8eJiC2dNwFOda8xjgYkafTqxqbb3gctMVgnEh2 tWqxREWjnS0ZsB4uYbH3wsuJDNyPFsEma8stMXeAveskHjjZ9Olc5JZUPKa7Z1NifOb1dG4k7K1H 9IREgOAhUykbbSL1syV1U+SCYc4Rylafgpif4hqxQ3ey3SDXlyyP4YgMLsGe9TrCbS2u1jsl1WJG XC8yvIW/KYp6VvEZrNsS5wx484ZyI1XjHUIeXzR03/r2FkmHWPFnA0LogwGGXxgj0O3+XAIGPhED Zt40hYi3xpmqEPlf7ACH3kmlD3TjWbRT0ks3Y4aIkCJlm77Su2eaQ5rsrA4V+0r8RCkoDqNeFypq qt/oLcZSG5SFHXt7G9OaAGNZPpBdMZCeMfWamJd1449rKMazbcBqsSBKY+zuygHf/LTE0/3osMeW oJssvgUmbQCGfP6bWP7zKvhdQCsVnM9kMvBN6TPhie9AAnk0J6w9l6qcA4ebMIXc3CGHIbLkPu2o 3eIa84aXucTx1IWppqLSBo3ZXpNMZrIlPw3TgRAOutKNUNoC1lfLUvwEwBuQ7dzsX+GSMva1zwDl uBx243ZMow7wKAKiaoNuM+teSUNB09vP2oV1n11ySq5jkrpu6zTVvpiZLIBAya/DDWF6ZZOE0UPj gY6qtFlj3I/hXS/fFEi6q8l+nfJb0w/TaHNRSH0eYlFsf7Kl4hzCaM7nzHp8T2ZpIyjtI7AzgjGc vGySUlBCGAgV4HA5oJykBMqILt2m0HvyXeO4RCyt6HOpqeqpsuG5sDViD8CWWy4/EIdJYdAiZeek /Bezf/nR24Xh/BpdXATnUQ3tHe+fb0PMk+EF5AAsvzasq/OKzGo/YW/VjE1tav7kQcrRbpL5oVbx uOjqqW9lhvtj7/FtzjUALr7KKuJKtFuAwPaAUN98fYXwMWYVypvPCtVpMPy1kD86L73+jQ4VI12o YC/Zct3Ot+d5o6HiZ1azXDM//wLTKD1ujq8XaCw7f+sx5dP/OnQoDMMgdCrRlm4hwVRsAq3pESqB kDcYETrR3SnMnjz5+qTlNBu5NheP5f0DRNy2V4fGMgXwMLnZ3TZy79Rg2dNrUFpMmTL72YwXnIUK 78Z5OFAl6R6iUYnu5D7jd37zDA05b1OPIibz1sBC9gZMW1k8TOmxOwpD9oW77eEMRRJ2IpGZZu2X TBz1Saga2NBqJcJdDfSurcokXZ0QIt0yWF6q/ycKfZZCEMUzaHIa8RDpzlmpDTY2xnB7jRwOcq70 J2mkHWPjf8tc8/Bll5kRHPF7PtuCnAUTOrHGWHC9iRJFLKSB74MLABTxprxkQnZjLAF3Ji9HX7jQ +l1gVXmBhBZcU34IIrHSL65OdWu/gniSE+kyNRICzvgvb8sILEukkOiKDyw+ZW1xHTssajziYS0c C4D4p52N3X57cSAIveuu/Zu6iZm5eYiuDfWijCLRcm37xvDZBHH0tecIi5qENutBiI4Nm8C2g7vD +wKVU8Wf41rtNf5p5RcXKbOWaKdyy+/xFMhhd5oR6eFdM4f+RkB4RDlYPckNAF/z4DKoRlN0urpD 6bfs2tRBbHRsJ7AJqeDxR1epiR6NlAmQx5q2tMr8k5hzjrLj0EZ6WTYaC/82YObNxydvVJaXVkG4 93s3Hur/7sCTEMTVL9TiaOubiqdWkNTzb6m8w5Unyjml5gi9/egFolxvk2TO83D7Ee8rk8W9Ult3 4c4PSBh5u7g/fZeFzu42zU1Vrl+oIFgY0CqUkaM1QI1AgyjJLC8ts0AiD+T4JM9YGhYBtN1FGNkd 4SK1oI51x2ek99SevzRvtfXskK6yiyh4zN5dNScdEZi+FmiE9wWjwyxqL3Tsl32xzguLbXhuqGiI jF3WPFxhNE2DUSu9hYhwPsrlEAnU1R07A8X0hLXXOUQY5AI734aIlvVokRZP5iyCRttGTIibs2Kc aQFo+0aiu2YSox5mrVMAKK0fQH7zPITKnkYmRoY3xq0JzrnH4Kv8mutw57YtrmvrEuQ7JlPNid7h QcKlFXqYz55dc+5eEr6+gIEV0iS/4bK4RKsrrMKI4pHxq4etC/bLnkYAKC1vhQOEGAceB+HyEE9a wBCnB34DvnGHD2Lhd0wIcc/qdjoew4hnSYO+r2xKPgPqFAbcgmH/4NqsYpD6RB94lv5RUXx/E6ib pfxYXL8VAjFD9P7gFXAu385ufbmFEHIwni6YF7PpXmSfNfVBjoFymda4HIuEptls/h8uHPXFKNrk 9sWOq3poJ7Q44l4esNuFSCCCf4kYAcF1lap8XjpT+dc6VLiOlf/rFGiitvXkx9CzOqinBAJfvK3e ykJKn1CGgyZcm23iTivU3BUOeQ7uhA/+yyBGG3L/IVmNbU0tJ7iJ9pvVypFK+FsYlalsKiHxZNO0 xcsCl9h0NN2LmKqHhndedieskQ5Po3zGLr4JKvywL9+uf3J7r0zt8Hd+NRkB5mkUkDCm/GoBtkSZ sa5jrEU2CMhLNaG0VRyIIkTiEh/dZ3VXwr0+NLhgDbeMy/KBtdrTwHvwLwhAEQNYT1Xa/PBCnmlA ln848IQSkfeiDo99o6qEofLENBaZ/s3F7WyaxaTK3jKR2QA/GDvPtH5j/o8b90WcDGDq0p+QORbM FzlB4wj6lFYJO/Sqhdw3RkBkeD2fd4PGiv68MOFZULi1A7OuUabA9glBJ3zT8PskyXk2aaBb6ikX 16VLqs+RbtQsVc7V+Cfs9fzC7AwuY8a1nX1iU80zb1QheQkBpV/58GnayQrUTtYFOdaRo8/AzLg1 ZS0+XTNcbRIsy5HNeeTi9Hn8J0TDOAdgKrpc4hTFQvvaBsq0bpPWB+f23B59OclbY+5ZqajwN6gR BjcD7LPGXioi1fxHviha6DHtVuI9/K96LJ/84xE8U5ePj51+vlGWFoHqzy6xIFb7MJa7ZhwzZjRM ndrNW2ED7B1oEk42xsApsGMmU3vN8lTiSSHfjBzzfw+MnJyvkOndDDRpFR51Wf1fBOyk2a+SP3S9 QCkBTG6Wg23gG0/zpw9yoH7VgkcUGfkU4ZfIOL35i3YqkU2ZrL4WG1XDQXza9BynAwWqroYpPkPA HWn+g+36PFG+mhOLNyQboyhGYVtGlS+PXSu3MQhDiRVEtMinHADmbz39lWPwYZxG/zGWRs1MWIW7 GCBTeJ1qw60+ED6UqbVm1jSsl46i4Nr1Zzpu1FALW2BLpjoSHZ4QrasmLnE8ltuQEfkRWfV5vZ0o cP+HpCuKujtFTB4NYAU7GCV+KmVfUxGvEN5uSSo/hWSJ9ksDSrTJYonOEy56ve2Ads+lfH5PpfDp wItdQWSbAr8LPqGaOlpDwQ6shiR5XRwl1ri8puevJstHLXy97xNjDBxRS7I7S7I2VAUB+RQHYuhs qsU0wxHa3MzNURKRio7K6LFKF7lel9VF5fVxwTG4LTTwuABr2kv8ghsIUomBV9N9XomWaiodfEOZ BDgxzWTe0/15uwD46IBjuGj+MrpnZhz43+6Wb4sMhOOu5qgLi18XyLyLyIbHVr7gu/5TQIVCBL7b pbBnbUlsfywaEa9jPuedJdVW974Fqb8sXa4/bvvaEjEqXt5MHZSa8Sd7zEiXDPwNbemkwOfRk4V3 boo2RjirS0vL+UHFDegRZ9hysXPLHzWVHbBwM4XvkQGrd8vDZOPs4avelniozltQMhAahZBj7u1N B7dNcTO8fku5Lg76E8+PI0pD6B0BDIAYdCGSviYQrVDjTpXxbgkvyQDFKIHlgniJ6LKWia3wDMg4 fN/PECY1A1v9mhfYMTGMzldjt8AWtvxUnnT9oacS042bmHQbqx8kXs0FUT3IKllxInrbcevJ2t8n nHw71p/56UkIc1iYH2M6Vd0B78pLd+OloN8CyhHg/032eRDy2uLSUhF8tzqxPfnGX6U9QC7cYcyJ 6/4fQrlgzxQ24JHLfDKmSq5EfyZhgklnh6AAuxSDe3pELyBi+UGR1oka6PjcZsdq7a5sxA9v/frt dec4ShQNN6npqGKn3z7ah0LprRfcxg4bk7Lpg5ZMzix/JsHSh8iG2rapjkXD1KkQ75A3QbhU+ZwL fjb3l1ZRPWSamDeF8USP1FTfCsVUi2Pab/Av3W+u8ackOSWv+81f4YBgu91yYcJDQ1xoUf6fF6jH XJC7LtnNTitLgjpmMzAb2elpsz/6nY3utGkARKQz1nQf0GOLfPlwgIcO+HBYE7Llg7u39N1PIpD0 lgNcmCKRLbAbZD0FfrVzp6GJqKNYQMCnYL7grYGuTVJnZi7GytgC1/aqKknkJDo0bwC8lJTrz/YY vn5AIfWRSzvZSAQ45PlltAOmFvuYNPA5tapvzLLKg/9lFTNrGxCa5hSEkxz3672MtZ6FuV1sjoef bpftme7RY68cfGaUecyPbEQjxAdLOEHeiLs0RRtkR9Ym2CF7jZUNfmtxLtw9HAf2KgUxD0DzYs/C v7eyT8PaXFQm7gj7M3hkqRY9IzgUGImZia4oLiqTqjcjOwdLYWdukh0YoKsBoigzW+ldhvx3Tw/M qK7pkGZG+ctPW+C3ldH09CEF7rvspiBBsdd9PB7OWyznkWJhZFVgy04qXj+2kneztNbXgT3MkV5o fTAmkgNY6i078RWgvrERIYl11SGjmA0/CbQZUo/URCmC+ptN3NZ3kQI55uU9f8qm4tYiQCZVUGO8 Dq3X5axa1GiHr8UV2APdXgwFofteegoqybyHZY89YXZ3Xn/p4oBxVXWTTXfMRveooisqkGWB5HpQ q0W/T4jJJ2UVFNvgfp4wQ/WojopLDXpeNqw9d/63jRP2Dk1cVYvZfQMuTjXr0ZiQIF9jIMsnpl8P Cjm9OsdOWFzVrWrGNUnbaTT5h01ngu8z2z7UfD9oO1XxzUIR0ldGA4w6dt2BgyXEfMzGM2oWlxwD eERmL1X0kry9h95eIYaXIngnihFD3DkDrRvVNCjIQHqPVAl3tDLPtyMTPxmdXhKihlFIBH+VhjBk 6SZgo9UQ/d/qCoP7BcF8qvf5Hmd9VRNsF5qkDmwJg5hYhLJT9DmQeEPePMKnvboFe7p3x/peNNyi REWxoLiLkpakZ61mLmy+SGJCgJ4QcklTNgDp2bu49aXegtuGh8dUU+lCeEJjcyjxNCOGltUSjE8P 4eR9XGyUleydCY3ls2E0gXkNgzslHLemDA8y9+pkUzgs0oOPBanDYZlDB8SmLv20Va/ZcjpRPSEL SreBa+tWuZY1fRxI/LbsevPz3nDNe6rFeQLgViiw4MiKkiE0cpXbjJtGGy3+Ck7S0GdlFO2wpYdV YynNbq4BsI1C6KJ4DMFX45ZOIC5Ybu40ty2BOWTCGr2eoLI3r0yv8WZvJCEGFN+Fjdq26QzHZPf3 awBPRnDgOvz9F15DKsHsh9sbab14r8G2vR99f4yfWH7UIvGv7T9ho6qnIJkHfNnNXOh6RUJZQfDo Z0gZ5XAUOeWDVtJp/TMbRxgWWYIk8dmpUPZtV33WT/bqHB7f1n4l7lzra7VwJd+/y3Co1j77pTlW 5PVeTEMmMfqU55wI04618tW1LufaI0pg1KIEV9BpdA9aSzDKHpPGI8zftDhMRvt7B7gTfTBzXp9t fjLYYucTFkJW9vZWtBqSdWC85/ov2rW7FoWX7eFAtfqcjweKGBDdlrTMhkqOnWBnrdseWX/XO16e PVocqkOoE8UQUu34A1OAnZIFxn3Llw/X//qOuzezmHje1zDU3M6pXybXdlZ4ZwuZVi/VoZa6EuIP xvyIg7L8ogKwI2RK3GYAQ/NTQLm4ccpjmHH90FvBnds3IOhUXDLQYRZ92r8fO+jBLB8Ym84g08Db OmujSFDifCkGLygeteeGqGKyVN+VRXZoqKHfCK1gFI/iGA58renhpyo2Bau7noWMKNwAcJCJmQhu 4BSwtAq4L+35FNSbMWhtupUFCXT2xSBbcYLIGDoVlAlCNOM/+9cskv0r/RJ6Kjum45x53FZEBuj2 gf/U1E07tlPyA9QJFnzbqa9dk/WF//qItf/y8ruLgK8xqEBDCKRuBppZmtDx0wOgkHXjS8VjiziE SPIT/7FoC6Mm5yUCfCO6EyytwR0OJiJ2Nw+XTzB/NDyj7+AA27TQ72lJirPYhG3zgxzFzLghm0MD wn0w6A1vDumuz10uCrKzkemyOxi8ofK7PkCQ02XAkEUKUbL9bt2fK4eZLrdp4r/LwL2mRwllMJ5I HR1M0C70c8G3GuUjRHxGNAah/7VkDMYbtDB/hSgqP27vHuYuBm/ki/4igV1QcRKExEvzG7iNr3fb XY2+Gk1N/1ULQSP0TE3khAeFOBJUG2kFu5vplzM/NnWeweRPGYgjWBWPl2e3YxiqmphyvwMrCVym +E3G6GFMCl36+pQgZVwvz1ryJNsre4DQsy0zyxGVNHfgizKDVMUx2dhHz/5ACP9fn/LqXRw1yCI/ bGvvx4zB/7oqt8tmTk7WFRUYVrEktUUkoGLi80lGxt+BGqLJd1eldO5ZGZN0IF54ud+DVAFgeuS3 /HsPww+mz00WjXztH/v13bzjfSpjvFELjjfN2XGBKzjyByOSyL7RvCtHEmQxDY+Vio8nTDU2eja4 GxMJjG4t0pn+V3PzYuRQcQUABBfeLzgnMaqMmdsEMSMIHyfmdJiUIinBNmBChLqEGk8bcB8shO4S U7y5BeNePZP6/mrZoU704jfvYjYpcycUphKHssPYEGtNHA3CLj6i4hKJ3mWQ785gxSLyfCsQiy6j fm/7BYgLKb765BMexVx4AVR3H3/jz4HKcYLV/2PRBmuvCaGcXHY+k0DcVP44SdZm76rZg50B3JB7 9+s5m0yVWs7k+TjAyGKa1AMoKzYkGWh4n9CAiLbCqFLsGgVpVog2+gIEZVC9knO/hJw7Kd8Cu57L 7hrXcZwey3pKOYZEM2o5jEaUOHdCfefzX/JogwWIB2mBTYuE4ATa+AwxUrrHOxKDleCAbLq33I8K 6cGFCJt7a3eMuKfcYDn0wL9VXcvJgg2ImGLKRCD1epULykR79BPEEGX3A98jOe/LpmS42A21V095 ULJwMbUQdvm/oqAWKUX8kVW8l1z1DNdg8ls1t/Hm7nkGej++VpSbhnEjWLbp8jK8uoYsHiCuXJVI Cb16kzOo1vuMin1PqQUkDGY/bfh3if3BqgPE7oA4x0cai0QThucdHGh6cjs7V5fAPQ6dkujDoJqK J479G1+gdOJ+sOob0YGWwCH+2s7iRx7RfdxTGmMzgoDJvZMthWjWP+6ql05s9ylftwFP18zGIg+C 9h5FidmRX26Yx0Iru4eGS/nKhoN4weLPSBsXBKbNbblUZCe/GIvvAu7A3SZAKuYXpvMKYy8zA88J wqa2NGT5pybtR3p+4uCL1R8FoyZ5o5FCehLckxsSFGxlo+Vdo+ky50hU6xXYkDl/gGQdPXDXPmBh ywWumxQtx5ruEdy1MCE6KrgD1sBR+ep9KC6bbrxDWZhtOIuROdBelN7GTKt8YS4/tyEIquc6u5yG S64Em6I44Jnn+Xk1azaHZZMbdiUuyw9ZUIaetf+ekCl5RQ+AxNiOAuj+ADirbO8xs2GaoqOzzuOa ybehbU+g6NV9fH8loDBb5vaQIP2gk9HUjRzfSa2HGkn07sJiBIpHnYVmywOJV81icnh5F9BYW7Pd eytpIqWgkvaqSO3pKI4AsJAKR5/E/4SCOZMNex2pr8kq5Ox4jpcmq1+FEcSTi8lQl9L3BkPVlvbB 63dQQn2UskymlLus/pIo9b5fMh6OTc2qPJqvia5vGqODpetgZIjRpf9pdqh/EitRtC1deYMFj7i/ zh5QlcVQGzv51Z61GYEO3MQdBqLgXS3UjrU5pbcU33CpqD6WthwIsKCUOJV6StZHhoOk1RxQKHOx 9qoNNyz7tWw4pxnqX50liLhB5SK0kGcU51zuHK0VWnzXpiCdZ2H8PKxWW3y+SmS7jqSA9Yv6ZKH+ KOZ5X2oLLoWMtp/EHT5HmdRr4HlXn1sJ0diWE5a7X3IALelqDrn1977saIyeRa59Au7ZBsbdM44G QgRbbxEmD4y6eXezRrNkollOsNC1AYi1S6oWCHc58MQWYQ9iQ//vgISRuHEKwe4uBj/Db/dVzThh AV0LA4YIJ7lzHN8rYSqL4pnHyw7v6Bl1GMGjQkAROT7CXJS+F6K3994QDucfyQIDVBfE9Fix6J/X Z7VX8tY5bVgqoHyItY6op/IqXCCmP0XDfcOu/JXiarA9BCehxxKjxp0HQrifmvVcrW9viMt8hqIs yg2rqggTElNoolLgd5aM1IKaFHQAkleoyAmTI5OVjHmM8Uog/8Ej2AnKWvciszUw771kwJQEnkzG io5Q8fvCD53RBB8PBUJhrKGGBHXkWHwXJV5jhLlP7FCzlrSrITp9SVggePC+gqqWm89+xujsL9iC DOGgNxRjOFkrGleMTsMKkb8+qXaklk+uj+D0wanaC48lJUzCB590L4R/XRsZ6HpofWA9oCSDqOY2 e4yv3kTCbfFvn+HD5tKyWcnMO+d3eSltEk7Gc2d9mtHOHyJb1p9tYWohMEx95o4+l/YiDEuLOt2x GC8HH+sSTYIxQxnYwJD4Tz7BQJL8PbY30N60uzg6U4I5AWjuhAEc5xMuFwohdEHXGOEOvM2l0pe2 dyR/Q/oCPLyMzKI6pWzIQpAIcG5bcXZeMFSlCE/tBS31DhMY+DPTjjWn+6+rLRg7FR9Bsy5eQYWf 3qODGVzgJfc5vhpYIAtR6ubNfftdYkVVGwFeCWEjhF54X6JyXii6S0dXfE5fmJ/BAcpL3fCm2EOX us2YWYkKalc+pSGgFjRWK0S8MrceAGDd5x0CDYZ9EzmuXdNnmQui6h6TnKjBCVDsKax9EC+JXXkF FgpoDtlYQRmH+47jOBCWOaGPByy+woALj5Pq/2niB9FupnelaKUK8383c5kWD98wwJwtoE4zlkGr Q0ip6teTJf+P50Hr2B0DCbpluaRw2E+uWNx9kYr8gCA/mhZdqc53U2QV+V4Sr9Oqsp45SOmE/IzV L5b8L7Go0ztXDGIpw/56/hG62/N2B8YdmPDYdVIorOxVmv1F0nqVGFbFfV5D4FxqzE/i2is4VAXF 3BAp7VBBTjqhLKo6Hbs9Dmvb3JxOhn+HK48QrJna+Ix3xD7HfKDltOb1afcPVo5lEFPo5/5F9GUA CeJQsQa6Lx+1xcGjcObWf+3XFXOFijvq3U6YqGFv5jpx1IVCJ0MVrVBSdWm/EVdQ1QqVqKGMh3WM BE1Ts5cUvOdul3iTyCcHGe41Txh0pYPHeh2Zj4KeUVtCOoFvdWranDmli9f0N3cVZbkGVmOPi8Rl PyeUEkKkgwUZEwdTRi9lCzhEkeC9QzcgC0gGCzHwEMPA5I9So3V4lEgmsPQz0iiBJf2VsaGf0WfW iSBrlrGD2F0bZup4TDsN5rQA85+afmg3OMcw0uKJJMSpMKeyLFFt8DNENi8jmrnoGt8YI/8oxq/Z Gg31ACcK62qRWhF1U7+WfKEwc0bPyDRUwL16QCKN+o10FPGiNhQOVNiWCvKwUTnLlphk1mG8xinw +bv7YJkr04QvZylfmEaNNdMS4pZaWEt59/2arVbzLlBbVR5xbwBJp3gDycrQG9Mo+OqHEktDfvqM jGw+rcNtlehhFLGNrqePf38+gRJcwYbQTZzzrfz/EXwfT9ExF22ULnAUgMkMgMn/Ap9qVCLGq0XT A6j/EXJueEDfiBuYzVAu4voYWoVgb1elBYXTbm76NGAont/P/TtZR/SkM1l1in7UpuzgOtPncqgl JWzrB3vLjzvJseQqGGP5ouEdKkjTIQQ1y1XJLGeX1STNveOJtciVjgDiMOF2WbZArbq2f23eodVk 29udrf4i9klI4fw9p4gQgCUNtSX8nqUJothrwpleM7BtW+cJRWu3C8r0SoI7W6ySkicAso+MLTiL Ig4yaqrfboQUyuEi4imKrTZ8kXqSjfsrahRy9psft2EAmzb9C9HDdCOdJTcedEzj0A6K6YGKVM8R KgU9T0XqLc8D8pmKWPyxvdVhvtfS1o+LNpPnhGtD4sbKMhEs8nR3//9x1h3anwSxpOBux36Ku5sH 81ZX1/jz41iSDwNOswqvKuEw0IShVNBkd103K0V6ZmtMmvKPnHQPSgz2bQCBdYVhTB2xJfuHe2G2 +6kaCBN0aSEneRhYfMcEOAiMJmpwOjslR5OXeqA9FNelMbjIB8OeAfmQ15/HgJ9af40X93O77dKp JLIeV4r2TXdpETHk3554cKwtZed/G9jLdcUVaA08ZWnPYA87m2cwUncI6OREr0WdVyXsmVLd9Xtj JtbbCBGLDkaib9TvHLDcrdGZBI5Z/25DopNE3eFrFCBpyYcdHpppBK7q2MWZSJTONYxSmXEC3uDM NyIuYWunFFg0CPNCV8awN4IPiJQvBfgQPtF+tRXEAoKfkv7Hu4HlyPrmeY2/S/C5XPXXrGp/aZk6 vQZ9w4VsK3G6JjJzH/jQiy7+eICzB76w0CZcXst0v/yDjp8ext60FVwW1DqDm/ghb3ZV7lAd33pI 9YW2TCmNXUwLsOVQ1cGkX5LeBZymthtGi4zWJN1JNdA+2EDQgZTeP2g7/h1Cnr7n3/he2isC42x+ hpNhctygT/Tl244a0TgACMy5bU4dxFT4b/UUJ4u9Tlb75+4H91i120d8AqQWT9Duo4iFrsm85LNI jo2En9FfTMgHqzEgNilCufs+yHk9XJiN/gLemjqdps5oaEB4FKczLBwn9oydcg4pk+lxMpzoqdUT BHzn4/P/3oZUhRrPoKCaXbNCIVInDXXpaF8VWH2ijZ/Fg2Eq2m1EDWuxMaKryQE/4PjigiLTlVr2 xlCgRWdIxM6MFa+3X/ZAuAA9Q9aqa8elZ3RcwqYdsuVTTFRzBXEJ1qHeR/yGKR06m+Ot/y5V3JTZ vKttVAO/IeJbylClEOrC0H6evQCx1wPpyw8gk+MhxkdE2C0SfLva0IxjFSbBN1ayeRUQHIbFyUCy 1Ydgj2taD/SlgL7SvlOohbtKYKu5DrfJIfkDXfiaiza9SgyL+KrfdG8nJL2iZWiZts9rBavIZvdc xFwMy9xvBvZb9cAEkYyBxvendyOrseoFRmj2EwzL4crYcexmnyP2KS+8KpSDVDTq8HhbVzyoqlD5 Hy9GrFfsuIkuTtKwsbAZVj6Y3T5CrAvcRQOw/9tPYHkfAgJMse8Mm4gKkOM2WOqBOlPJlsJUdWlN QXobyjl8l4YUZzlIUULyW5S8tgScfmkolIQ2kzjlW6ZJk33CVWzmU8nWWbPvUK3CBOL8K035QcdM W9wmXq4YdJMDhAqWu8k9Y+4FsLASq7fhUpiKXXMzUdUeKfQMKjI+Pv9OpO0ysGoq+oWbd9/vUL+E iTuDCdi8t68EJFR5yuUhyRjfrMlklc2bcSROfAcE5wSt4pvN9rvxuBaIGCqzCKSDiVZdjZAKB06J TrmF9XKh7G79IpUmA0LIZmX3u+Fxw7y8RF1cu9N1ptxUuSKxHb8BExeID5XzRVL5nKWFDmUiwYVH BY4lfsPdUJ4UZGNARlIsTR4K7MmmlciRNYiuHhO3aMHk44u/aGFHxSYlB0q1FrfTANE7/mtpWMza 3jev9LUGD+Gr/Rso+CBtB6TP2h/+REoG0fXfSoWTj0MkhngexWYYvXMh7lQQ5WlFTzOBl4yJy2p0 zm5kXyCMc1tL/0NkzfGzslAcJ1GaFotS2xJOG3N+2SPIlGxKOkQhXW/UvhzjrOZ4WXGeWgbwvWr8 K9YT4XNYjiYYh99VRPWR81aweDVHISSLZKLwJHfnSDWURybx4HZ8QQbmBNOfntFtWSOvn7AmAYhF OxnfLIHmHFOd03SO+zMzC583Mo96+WF+xRVZLE40DudaOa3QgbMkFUoT4ggXdbZqZVzQnL6kXN21 7yu7QOrAe1BuV08TC8fInPMoTQKWc6bABh/FEMxBH7b/CX4y0k7JcOegu1vlnY+VA8FypOrBdwH6 uf3Z2isZLqbSsucdZ6NNyLobxsTNo0IYll1TVyyNi3cOfDt8tmh0d7krPPAZlJhaXKE3lOnwxAZt gmCjL3Pn82rS0/bvyZMRHCbwfEiAIA6lPKZcO0nGA404PmGGFLgUknYW5vW+ElMypHIGZkIh3W50 oli1eRleAjswYFiIa73Biq/5ZJzEdhD0J5qSmkNWbRtLCaUnjTB6P/nmVr+fT2il2wfKk/1unkp7 y5F/QTi/Cu64ObgoBQ8mNNpLW6FcuOencupQPBeiuh3EerTTljb82jUjeZ7zlk2QY6XfuwAmb66j 1xFjnv3fj0WJHfob83lSIyMbgSv7Kdp1ufX8oV7MLlQj3z06yKQ5eOXxmzus53bI2XSd1Wpnbe8H 5a+Q9X8SucAmGQB6TuCA+ieyoDzk5nfN3s+uCNMDuZ0KEAKayHCxvp0ZvJLEXgm20Y6YnqusHKAx j1o7O7jvcFazyIvzhiMX/jRk4vMB83rI5jCcsr6O9EkYSJ83NM4Mr8q0ZNiyjpc+Ni3QDodoiE/V cEHvDRr6T8ZZOGjsMjcSt5Jb0B8NsEph0ZBeCA8ZlChJEmS4qPogLBExjC6gQk2EIwGaZeYtA+h+ OJTdbyuuvR7vdtxvXpyZaKP1piXB4Dzw2E9aCjCDR8FDhSwHWAgURC5vmv27rGNM/PwHQsVUx76I Eie8xSJd1aY5KnqAzEypRRcfi/ENOCsRehYhHo46hw1d4IVVg921GxsYrNQiANQheLZpij26cDha GhmyXQf8zKPLinvDsdc2Uu4SymeXUVllJXbSGO9RkplSI6HUoRAOurzhj3IM4pNowHBgU8BXYSjM ENXJbUzRPWR0kfYUos15MYKQHDHLPqccsSSU/waDwJnRkY1eu0Ps6dh/7+wN49YwYJYRsJdoVPu+ i8JfeXLm9zSdJtiJogMPCiQQ070x2lXYxeKFnY9YDwD66MFodv1EGGVQc5wAQq6Iu2vD8FmyFXWa /TR+o6M5FskQlcoC4O0lkCY1b9SlznAC5OC55AE7BKPAa2RVQBVkaBjIqmZwxPw+EX0EME2KKAq7 7vBbxPlBLwdey/WFmpjdZAdCry8jEYe//s6sAAT5XVcySrcUB5BPhA8eZHYD6y6fE1m09qwxvhCy OIVF3fVS5bCdHVStQPcdZJyaaNkx1mkhkuI45T0w8tazVqDX7V/R8sLTk0Hom3fo50K5+WTx6Mak XqixAc2sG8y/uDjtQZ5HtnHVnurOq65tqpDTGlI7s4JHNJ+7gthJeq2vjBGS1FhF/fi/SfZApHUF me0k0pmE64bzCGNFMckTsfeo+yANY/1ysfHOTcbRTftVe8n4+DW6tKfVsr0YAal3vEaUaGKhM0nm Sh7p4OUGbFZft+jKFdoxhxXIY3doGWEsrxqjkamYmbwlL30GRX5iKy4vS0mJYBkrE30AkfcJBP2R QkNmLYHSj2bSQquHDXaJZ6oNyTMX1wiTsbdnG5FaGOC74tFZ9dfWwjU7Yz/tKGW2WT1SgG1DvmQo de39CaiO0OnkK0C5TlEVRVhdCVBq/WWe4GBtEj1lYgBi4eHKIRdimaGsXdY2ExpM2E0o4Za2nQzS fX27T+sX2KgVxKgYGIONQm9+SEDvRLbIpckPB4T7HiLb5pgATPLcf514tICLfxcr+ljoWV7ooAFu 2vKMUAosCTJrmtitlnUgPCo3jX7YpzeCB/uVIgIGNLZbw9EvoeqkS4CMfwbyPE4D5+ioh2fq/UBa 65S63YDxcV4sZW0zV9CyE9CIhFPpeMXWLfy60EWnmLqCGAEhSwBThdPaJ4vZpioWp4qWfUzUgjHb htUa1LGt55mCX2gP8TK7jXQRh6izE3GlE/s5iP6dHwT9gmNWc+HVRQC6c2dHL+LKB/N9cj9AJtFF Jts+rDnyVnJyX9ntPJTXd1DDgfeqeT6YXkiQkpaTC6A9mtVjYvKKwz9CZWE8t3MGFJlHisuBP4dZ 3/RoP7g/QBlL2V3PrMLC9yWJhP3WqNNCCNwolHu9Vqdoft1uHv/6AUTb2h28hytGwYdzs4TmpyXg PN3bQvEcRenicVUmLQVIduTBNXjrr9/bCmzepMS15J7mC5REbRLEI9KBl/mDGARUWVUdTNnftppY BkqrXaGQhtSPb8l+9t2hKJoKAL3Od9l4yX7IABqTICPJg9sg+p29hPa9/uquHjwHYtwXJLfAzUrj F27/4NQfI2Msq8NeOvRTNqU3Xsbl1dpYgzCcA11OQAOUEpmGV/iN16LW8dOctD2zd6h6b/h/ACOb U6wXhu3GqmFAmIujwIZ++jM36mAzV3R0tNfP7Us7Zn/tG6gZxXyh1OHpK0JVlKaUpKh3+XBbucl1 Ms8lt2eOaEIcFacn8cHN9u4gTECtTHx7+JKICnN9e2rOyl7EDp+6o6F2k87kZA+CgvN+osMgwUlw QPjL9xzpFNazBfrC+pLhIxQyvQVUExMhWnlHrcAtjJ4hdY+PxRlXQ+un26JNK3IHBgRbew1gg64y EY68elc0Vq+vWeChtunXfBQA6ERkyVTEYf6MvwUnM74A6mWDEHEJ8VvQvRgmP6AGnVaCu8L6po7J U43h6ef3P69rqQI9aIt/KQjBA6v/j6H5T6i2Fx7Rhgz5OlmIO9wyBzsUEQLYwONg1JtQrbQWsj38 JMTxIwIsoD+PdaaCr4QafW7WZ7+3uqK1qM8EBGSS2qfIYg6ig47xtDc/BCEdCFplaaBnrhwcihkv czJeJqcaWECpVKaPPXmKWzwq4b3xJyorfjDLdikw11YonQgfPvx2OEVyQMswPZcLg1Eg7xJBuJz3 p6DGlxMf4qeEy6U0REoELzQZbAVfUB6rvMoOfO8LawztAaeot8skOMrvwoHL6YI6QhJInDy/koPm Nz56uWa/A3o5n7++fPRYC8jk7b07plPWQvz1Xiq7FgX+F6J1p+P81h/WV9L8atss3fy4yVnUhBVV CZW1JzdCC0d1hLA63zYo9g+DZhU+OAEMxjrs7zew36VvGn9buTFp7CfiQLsg/LYXFOKfmGgWRF7I ePKaGD0xoiZKA1+EC8ORGmQC68IZYToPlaQGAavx6Fqh7cBjOHU1w2n3+0+hTd/WWVf6Ig6yT/K3 WdLRqNx72zSHgpRxRqusKB2AiGatCONXFeJt9B1HFhHL28oeO5to7/jt2CtmlxtnwHSC5bjCwD6X VcJMjpZN+Uth6RgnTQr++y8I3Nn2rtdO0xH38UvON27D6ADlT1kVoTUseU+G8v4pqbuJJfN5UoZx efXV0m4euZgk4nhzDGvFFoyiLtN6V8kotGQMRc0JEHgOH/gYevjovb9BNOotEuK8W2+8i5dxSuVL wRC8avUtJPe0xS0oQfPYSvTRoCZNtCEODOlswSkA/yApNtyadS2cTCHW08jjGdB7xvtwwR5JFTC2 +DYS7ozYI3wt2QQ21CgeFzBZ4yGtDNRwssbyXWQkHhwRG07FkicEwueOhNBH5suOoaE15XY9g+Y+ X8Bt+ZXQhC1DM1ec8A9uAruDXw0Mr7KGyrgxu2N/Zx4qUrpBtoz5NSBkJzdNhaAYwWMNH8H+Pf2g w6uydlFW7892OJTUsqcBPeDXaQPlaw0mDRnedSI23cfb21V2Bnm0tj958jXkA1oEWFnfmdTu27RJ p0vbUJIufqMmnqzCKfNWtzeRGY5sIYcP+9litKjzsRRSpAHg5xDHajuHnYa+fjq6/PizNnwe0djz ukYP9AAnD0cL7MUFbtSvaTOVQr7i47hyvlOI8+KAdR9GnzQRwxGazVmVkC5Elf0jHhh3usmPvkPS CaNnV4Px0hnDkfYgJKj524u/Ka9At9zIgw9WB7ldjV1BEe40xDD0gEf/CMgf+OWkhcrfeZZ/FDAv 1z/dKl3V5VPtl2E10JKr/5HB6hB23kRimIwB7nYvNQfNQyvFWuerQIc2CijyHgdN6iLZkdVFDLlM FZ4G6rswtlWM37Qx9IkVNOGy5OptN7OA4sjB8AYnT2DRrdcmZjgojBtwsAAwxWxRGIcrxNndZOu0 pHVJ4v4SsgbDptq1eeXaSkHmlg5xYIPTAz1YQlaaradiFb9vDOKLV054Byt5QKPbOSmeV3bIR+Mz zCHX5LHgq+4Vo3tgwZkDA/zn+GPwScWn7jY/2G639+5ovdX0a/T2nyvRcG3/whljrcjAm/SJJ3ZL UFWgSwwwRrcrKWcBGapnWoeHTNjqUwe+n+8ebw7wxBtbUFysDXrK8OYU5mRbbMpW60Qioap0KVPT RAD6uZIhRxHv3iWGnp9LBYuc2E2ApMk2+1Vh8KZMSixv4la9bqu/FHgbDuYdMLUMbD/wX7+ZEFjC W+F/3H+HZ5tQmDu6CLxJ6a5EWJbsJphOikYCXaPeKhqq5rtMsw0Wwa24xfIG3jjKJmrTYd4OaT+5 FkI/MOSihSClrjv10ShdfZ9rtY8fckibXv1uj+6HizhwCcY6wfgZC+3efrl3vVjvBuxO5BszyXl5 JOAlO79VZHfuXo+iNzYAcpkIZ+tswVHu2+SGF2QwwloeTr3bgeBv5CshDYTxikR97jgHRa0wwC57 tZxsPIdDX8Z40IhFjwk7Nu/8Ut5lKCbr5Qnl+M49wZy/bLvIQFp3mt5LQsHNIH9+YpUTOJ4to9N6 ylCvxUbyJjAy5NOdropoTAsFgTvxZ+sE7aOTHX1pushejA2nVHkqXGbbfo12Pa8XTUkecyIaudru pBmy9OP0pxx0uJcOrgVvsJQUlGlvm2M3UDpzc9FcXFJ4LMVRafJXKX/jurIl6VZN0SUwBptZrw55 5YKTmfowlLYDu+saLy5Nu2j1QljpyxL846zzYsBzI8qCe1GS1plOmuSYXVGVHj/gzs71rEwMJLUa WJWPWKAGM5V85BdTEnVF2xRdhmAYxRoD/dG+5Y1HO3Lm+9Mfc58uQvaxUjKQaGSG+XDiOGq4ixnq F7HbbduGm49moossVXutDtdq+3niz5HNfaega9FGIVZG6VwpLRg+1fyNP6b6R0AMkw3nKkFHVNVi zOcVf8BNyzDSCRxDVhfo6v2j/NJkGl8pWLCB6G/FgQKOfmPphA9qCyt7F2Q5ewv4wobj5zZSRceA HMp6crt0zPkBGdEmXN4doug7wOv0IJ/AwByeMvE9jc6KlvSgBPV2y4sC+wPMz7pw2yxl7+MOQeeY SyOCNspT37GHhsgqgQce3BNA6KV+DEXtAhIuBMp0zDwYHQDaO8P+RljzUFRhrOA4ai8nkiuh0U4+ 2wRyamtZfSbAhPlu+6H7RYVKTQlJUTUrJ4lKUOTC5+BydLTCdJwUqSUYLnZHvxjGAXM5aiWLWTXr MdPTslph9E+4AsV4aaIzgMDvybOVJ7VD78q4hQ+pO2InMZGxN7vqQKkM0plZ+08eQDuUjNqoXCo0 lPTkZnR5qxjzAgHZCjhWDPR+gpW3Ehxv/0oIdgFrCQH4fSNjPRTvbUclB8hus0v5Z9K1Nhwbym5D E+2ntzgAP5aBkrz8lXEH+2sngHnVMjYTwWptp66snNbhKKaw9HcZiqd1LoIorrgmEaFnHwav7ecC 51vweb3l+sheuV1b2EJwd5W+FyYHU5ImecCKBCZlyPPwwFzmibGiBlZUk5X5l9JqMa5CMkDnroi2 qJT457nzrHqf5SXUwf2Ia+7PQO/oKYepxF1Lc0bpG6P/VJhGZIZwwtsQl4SMYjyRA0vfzeBtsrO+ /SsXxbxGBiI/prlCSVLAPv39LyaZdsrkkeOBGRlWIzJiMG2lBIvNJ1EELyEWxLV5SVoBMG1UL3gl Km8u5tjEVkp+EOgsTBbTEi8hjUDg/Ng7fd/lmGWU0sToholw1CHVuHlhQxf3x5ZXrhrrFTpIgOA+ Ia7hk/jCC993v3LJlRWrukFcWjYeWOW4g1xh7GPurNy2gb55rdrM94D+9I7CAcdgl6PmalQF8AIj 4CIt3d71sKX2vN58I2Af4R+Z41qtdj5IcI+fjP2jF7onz8FOeIhC6d9ESQTBrAMIpaGOHPe3XjIh sGtKuOuHabrIKmjSw7N2+jOrrNikQ45h7doIlXOfjP8FfJVRM3P3iILCcpR4bmKhIV/3A6lZPqVD hrLmjkTrNk+aHi0xKTQMd0iCwMBqxBRzYxs2HPfVCOFILeub/r06Ic52jiuBOl8cGMOIcjD1bhkW 6SQXrlRDm/Q7AtFctYm13pS97kR05v+EBeaDPBi5EcyNTZfRAyafnHVn4mfKDixLPHZHO7dvLVKP LIndrnjPR2NbRHRES3hUV8BAri6/UkYTbx2O99FnKe1L/f0o9WfOCdcQRPyrHe7lHjq39jZM5u61 Fq5IXw15aI8sj/lUraaTxEhYGMX9H6QAbCDEWqedidK4WvuXz5Q1nojYSZ3YDBVMLKQuphIpkUZ6 iiCHSHfVpLAf07mtZWD+Q/teSQEn/I7bew1e2+SFDBHDtC9r/HJTJtf3I8EYcg0LNsJJjra1hl0/ 7oVvhZWXhQJiJ89j+JWCPIjyGCDlED7H7HqF/DZKcJkziK7VOv91YuWjT94oD9EwCNx3BSP2yGJ/ n0f0dnqj1qxbWZRu20/LaLvxilsLT+S0bHq6Y6QS4qlHguU+iWRHFsT4xXDCjkFNihhftW2soEHE fzPIKxGsz25EK/c3HkCidM9Oz/rexahllf88BSC+uVclozpjWjDNYJZ5RYpeOuo81ecIKT3CvHNx HYIoz1z3H2YMfVIl46ZpTqxgx8MW4OSLFc6on83/4APxWmtrCW67YxMk39z8K8OrKvbzqR0LSG73 hAGxjzylUuOmRo8GZcZClLo/24/zOqbAN7PFGtfUgvJLGlkURT7iQCzMpsGT1pARV5n2/v/qFuUK 9i7qsfSQRs3x/0vy57TY4Of0JWIrV8bQlXlWsdgJckW/bIeWdl5fwBwzSWYe1+82ug6C07F3w7Wh sWBKgrLI2FJHxjx38OsUjDu9ywZUXZoXULJmMRCmYc79feJHT9EWAO84AnBrBS37Inhpnjt9XOvd I2HqhFkdKhGwUiWN4XT7L0gGq3jFX9FupLdgySlGq59en332oi/KKRCwkIeFUd5EF9wBXIqgTvOJ TWcEseAJHdKwUzmCy8JNgu3ZIK/fNOxQ0wOQXEsSPGQslnPYBNI4yhNyg6N18pDwzjemx8FBo4LX I1ccG7KVKMZtiGl2i3+Pf12ozU3WhQub70h7n1MN77EdjdZoz6kpJAVWvvP/iRV9EKJ2mBLXtVpR OKrt3koS1t2I9B2nqT9O4A1y/l/XqNjOf5jDlQxbiRZune/tTzSFjxhEFXO4zPz1JGrdslx/++f0 3lSLu5emSTfHN+altvTq8Tct9RYcOU976zaB8OIIv+/AMAoTgtTTEZUuXcZY9KRikeZz+cXAQIRK Vz5ibx3IyUlzKvsF3wtVzstbczFrFMIXDILezMY84+q1C3FP9qq+ZW2dmiBybqhcL9Ippt7giA3e 4rsVKmc0e7W7lhbf9/uAkgbR7q9WLD415y1XaXGtsjkXk4pICk+MMFKKjhJ5N2WYywsCT5wiKU5m cuJi5oipVhvh+B093i8GoJoKe1EyVVi3C//8xIKoCSVUQsgUOBhfmIn70+Hh3wtTmOgW6nL/56Vn TPwn8DNRwdWU06kGjBgAJHD4qhKUfIKSVj+MLM7bfL2ZC8ijtc3tIc0h5KJCF8WBLgk2BOTz6ICr 2HmxvJ3+x/XNbPIbs4bg1zrVxtJmfR5zPpCQnQwVOdFOdV0GBloE1VYnzyIe5PRC10wcenqq99FV nUzQbmKS4de4v7q4UNcGa+ctSYiMiIgTt4E16KxRMho8MFoq+YI6djOo+Npjxbs8s+/ST+CTGt7E IxJUnTQDOmsDMM2uu8K+KAF0jIo+2uA/lcFQv3ezdR9dcQA5Abpl6KUx1FhGkqEJOSAgWl2RAYal t52tnHLur+Wj7zgybzU1R/6LVW7GNU/wsvQQr4FAhrpgrHcnOk58EB34VLCyUVsY3SDIkrTyIGh/ S2NnPDQvHEmkFfeBmWk2rWOnVrXLcWfHASFfQdfhv/U/6/MQahdBIUHp6DNKVgYEo56MxYvavXEU PaC5l7KwW8r3aa95UCMGia38H3mMjcqUjYWNdKDbMyFSv57m3IOuwDVILiGjfduZ0BBxNOZGF0gy cwFrc90ndHM0HHvbE0Pgl9gyErsD7eq/nDeVajS+9u1CK0Mc6k9Es+ykRxD36BWpfQfGMuttn9UF 8/rR3NGbAL/Vw/bV8fo62vSC7It2T4qAZ76t+4/TqoEeC+7KktNTFX89x8A6jL6OkPNkaW+QyicJ RMX70byK0O5aBCj0iiLv17wIiVUGoNy2RggtKXM2Z8WMOIhy3fCUhXtmwrT5fl373YgawRX7bJt/ A3blgyhyH+nTcRQ+7+mZt/XYbnnKDaFWQTV6wHane7EJq83Z4huJX0X99SCPADQzHjesUw9ON5Uf YNDOYBv8l5/2hJ/d/KnC9erNxCpMALxu4h5P1BKJymApbucudjssrEsFkYVSIPsGe1R/EsTD1RVa NQA2h5Jyckr19sUlr3j6nJwh1S0X6KyVQT5HEWtx1LHz8FDTfzmimpbMADykRxbcof8PAB/OY8LC 7AYje9ix+IKQ+27VW6vHxRdlpvP4vACHNoJVV/dmQMxPnK1awTuomVZIfU97KWJ2UnmTXYz61oSw sNl9+t0G+dl5qJ+bBmPvndDtHcIldv9cvZsdd6XmYQDRPCQl/H5tM+DJ8WK/mylo8oKZ7dGV3FrS Xf6nYsaxUY74IqnBvH6PS468U2PkO887ROj+6mMSHJigSn4BnqtBgYwqAsfa0iab9jd8bG5qw99c vOLUzZLzWQ0Ckc22vvapGOHlZUHG0tXZmyN3qEQifaXpZM0MHp/VLibFg97sorSiwPRvW/Xr+a3R zEo7krjpAfk/bvJbZRLxS1oBakd/aQxdG8mlI/K7vV/VNOVpwJl2/aAq2v5Zn2B9PuVrLkkRg2xd 2wBhOHxi7PBaBFR/+6jFjTvFwAtxdPS2lWK80Z4OUAc5mRCkPPIuj4PbnfRp6THaqyle4sJKUEXU XBimkBraQzdoA3I5SuZfwywy19nmc+8TTT8DfvodyGoy0DCb/L4GxYd9jZalTxVr1nUSqnwKXZ6P 1cClWVTkPcIN/d9lL0aiQAplkNce4vIKUFh+eVR7+39zaguRuzMcHkhgM2a7ieahfNvNoKH8zyJw Pwu1p369WqAF4DJ0omtwQEmflOvG4UXkT5sruKrKUxY+qJEc6lkQSxm6BCV2Vv2De+wj+/gWZcMt EuhSr6SD2IZ2pwXXDzSPkqSkyF6Xu01JG7+46JiZIbsgMI4muTf89EsOOyNtOb0j/6AcH2Vfid4n asauLY7xWL/1Z+mNvSWZZJ0gQ/OAVqbfSXz695NofY+cVibN74V1SEHPGbbJT/Z4ZhKahhlQZFTW sYHBk1npFbzNZZnQtmZek+P4YpMYVQ7Hip/I7cfOpgzz9uCzcQRcnFo7qFngpGVxMv/shYDYCzKy dXZ1x3Zot5RGf4AwMl2aOPBNhIbpein78hqqkhSeNdeYGapRy58xtdp6N9ZQk0Gj4vpVg0F64eTl viMaygSdbiZPyqE97kRFsqMifTs6guJhq28TB7ptKKKMQuNyuX2bS/uuCr+zglzo5RvNiH8ZcPfM 3hvjLIeEWtOd+s+x2FXRhv+WhzSvcfrbbR3qDHwsW7rKkcEca99NDH/vfTf4oEWKz9O7tuyIm0qx rw438l6xTjTrqVcJNEJk1jmk4zYc/G+t0BonS8D/8ORClBUQY+127YOvgskwc0oqhTUAn0RaW4A/ oW38Ojjz/5Rl5DybuFRGMvzOkdeO+wklkCliDQOet3mqqh0LAZwkljOXXVPWYWBn1+ru3L70VPSv DHUeIgzKyQfW6CD6hB9golwIq7SO2asH6quO3uzAMnSUZy0FQVk+HYD1fWFunH3XRV99aTXCTu/F zfF0bj0bljTqbuXbecj8pxsC96HLo7i31RrKQx745O+TOXycSyu7Xi/2/+Uwa7IoDNOwb6T03NvP O1hO8aXAep6e+UsNu3RHystzneU9c+jhK0UZGdW9g8pI/lHgq0UyKgCiDAcmnor0xDutnNHs5Rlg 4JaPf/Oy7ZB55gfw4o22OBd9yT1qwBulPznjS0dylrKbi1t/5RwjF7CdFaywLp1DVlt4TlEZBNdQ uNVCzqtvFQWy0cU7qu13vA6w5tI9OCvWtmenFE2f2kgxvRaG51wSkZH9d8MlGgo3wjDglPJR1rev HQd43zAAUoNJonPAZ5ciwQEkw889M+ufqY8gDTUedQuTREqPP1T+0tkAV4oyI9gEF7r5gqV5kkQV Rhv3gs1HlohfY50H5jNvRmNV8so8Fb9BtY2joHAnM7vakd7DUqNfIcaOLhCGGx4ZdJ18R92N54Ov PE3OsYxQjN6CAIWhJlGyZJMc/rbPpWLtbhFtpRUTl0uivo+kpISXhbPNXhRoa6oiVHsSupZuRNcv j45Ed3vBvypuUTrMwqpy5KFHGk5T0d1FqAG6DMpZHB2mOJyrVDUwcgjw2PRAo+LL5nbFBL/RDRpq 8aCa2rAtd6nTUPwqrJEVkFeumUOPE7BVSTzuKcL9YcM445MKGlLlpkARMgzHh5hgvjUDnbDetQPP lsAEi3DKk0L/3DAQ0iK8LDxYOvIxAzXtj6J0vTIjCHPGrTDQzSPkvEAEjF4HnEGiZM6WLnnmkM/O 4NpJZDTcG9VgwYsn99eh6Kc8Mlr8s3J444U5dxN+jdpwV3COJfAB6ClmYAIFyyLeHwycVmLC4uNZ H/APncnEVXN/i1zbyTTcoJV6dIgWjrCcYagXLfm9SLAwMJhvjg+HDDFK5FErsEZhKZ3LaBQ4sddd eBKjuf+rSP8gXQmrXV7gFm385nn+uNldsBM6PhgMjZgCtqh3ugrEvmW8hdwptWrU577rvLuSUTCF Hnvdf+vgPQlOI43GQ9sKgoUVlcoq7bn8zi8wKNlFKa0la8fwAP1k7qHHc1ffONjzrI5qXkjoOTf1 DWsjfwEKuQ9a5ols9DqDpuU2X/w7VKd/eb5yPtNDDLV7yz64WhBoPRa+ESAGo+7nvuTISztg3vc0 kF1N897DVCMM9i9LrvDofXFRQquRe4lT2QV2Ck1I/ThkfThmXLwsR8n3/EjH4V79+v5o0pbbk6EO UQfHKuUPsfYvpDIpYhPA7Kq3CGIdIs0PkCIWnghviUsBnvgHfXAtiGztQNC5JKFAs8QEkHRwvgBd liwg+kwEQO1JWbd3xUOUXGTWXr8dY4bo2/W6+43u6RcBT8VlSimrq771G7OvslqwsUdLiuNqSlXV y5FJdHVsQJvYUhlpSoHwb8ZL+IUORHOLwP+Kr3jhg+d2iOLVVyJkhINMip2Afo3jrURZkUaremU+ Im8o3hgBWhkZ2R8oGx5V9VVJlCsGMQDaRY3ylrwsbFiQTgMQw0CY+EgYRrUPjGMtNoReV50XsCvK t98DE2rf8Q07O2u6eti6IwQzX7WT1aY0QYU2AIwziEfKcBgGJ6WeCmebQQnqFOsQJOCmvsrMiLCM pEFWB5J1OWHyxdZx0XnnynA3mWK7kaZxYonwApZ4ZZdniul0boJ8FGawV1PjvTiiszWzK854z+pX 4mJzOxBusaOY55TKRriEEGv54IJgx0jmd1mA3jvgsk2Tqyvvdpy82+bOzLgWCWMHpUeaVr5KUEAP 1RHbA6Fjbej0SOaD/ghFYZJhHEJ0yODgY8yUU64/aXtRxYzoUeddIzuoAyCdi7sEESMu3LEKzsRy yrIlAlxuecPBvIZgB/+WtToxAph+x4cgOZMlKvkjzvLxvr3NxDRrjM+0CYPBpDMrgSDOOCiGkIl1 zArL4Wp5vXcioZjH00AbzMeRKl97bA05dwxafLHEJ6nicDmdodduIfJRmMNgZ7GJpK+tCEIJBd1X u7JQlMwDOEvxrRD9tIx2QClcgwpJnXUcTlZ4DvWJZ/XLTPwaAq/JDP3Z/2Ria46+X9bizkdly7ao fE9YulN6pcr+ZOZg6LsUGIHRqSVvJHBbrT30lE9SZm7HzwAQ/ZvRVLX8Wz2SoP8TzhfQkZg7dwnQ 7xPMG1w+x2gkBVLqSnVmLQa0Mp/IdI1SZ6R5qO8fHMc46FcuVmAqH0Y7xJI3qXKKGTANwVW/miK8 Kj33J/QuLYud6aCNTSL1QRU3JV5TvgKC7B+HIsgkCAUAAQhSiYWGEY2nINWFS1m/3HTeBxMsVrf4 V8B3HZ83WMarEjL15OXE+t2w2MGOQrkVJmRH8RLNMVJjRqDEmR80yXnx/7DV1NZmhzZLXm4CW5AJ 4J8BGDwXuKhuvyNJqNd3uSAIIaU6j2a7FN0+W5RezTeUXdEWhf7Ks6iUqnVGIXO2N7VpyTIAcqMs bMUu4ZxGXv79qrX/rgzoFz7xkMP5VXE5OwXo4V0MYZnnlnbN9oL7AtxWvib3AP4ByHX977yfb4lS a/R+cz3BY0kR4MmPIOPPebj0q+zODJ+1A4OirAhtReLL4DKngVkiWvLSPl4XYLcySH0VA4jvcNrB iiKV4qI5wCvu+O9tM/nhJNqyiRfU8bPBaUlLYI76HeNXCrP4zma7qH7nBn2mqh2lfrBLYtD1xapy LyfJQUJcDrb/61z5gwsdcUVIfi9br3IjNDu7Qn0QAXoYExBgskBnSdCUYDftcXAb9L+O1J0aQBXm dVBWnrfEz5tTVoCWNFB7A+k/k7B7yddpNIB1Eqq10rID8fr87o8kQcoUi+5uezKsAQ5LciWdZ5jh UPwsdmPilnyn9k0ROxV4aTUPq/PLKNBr5Gzqbqg/zadGT6N/1K5oDsANyaH0YPxY5jAKbXrzCmmf xumUwWHTsKEquGW0mMpGkj+i9CQC1JPp2XM45dTqwyw5V9TzOiUJ7e5xr6yTKgifA3CMEDy1jWx+ 3iI/b/wAQipnqkbrUp2H/P3ibA3Vl5K09Tgil3G38FAKLgOvVeSbS7KCAdxaHg94MRzqFgjCiEz/ jv4wMjVUoN8FxEVzsenb0AjUH8ENu4ANSVHgf8swNk3Y8+049Qp2dDuV1QuP4q3P89CrGwSlH6Fr bAnQbe/c1lv54j+hfkGy2SAgu6sZgJ4G+ZJ3aQvdT+XZUdH9RvCVRlWfFzeYvIu6GHqTzce4N7D1 Vs63jf3M0Z5SHFfwxAZOqdWIf9dmQgmc+YPCgll8uczrQSZw6u3W3e3WgbjCu1UUbWYFQuKYlzhy 8F2VadrqdrfZMZGvmuJUkmRc2iHPdMaXg6Xqy587jTp7moI3E9jEg3XmGmuUc81cBf+es3omOB9D EAGWX0AH6TnLBZMihZ3ifKz+IAB9+0jXtyF3i1pUxuWp/kyff7QSWPDm3ALvJgFKvfnToaFwft+t o+MgGb6rdjJUNnhaF6ZkSSoI/z11k11uxBQKhi3ByIgslaz7OI2kshTQZuX+bA2zeoiCOrvJNYQM ZWsB4GeG+7gNfG5V/PYrXgS0EJjbnLxWR+yjCqVoumvSu+WrSHdkRSgXx8+iN/fka/t4LCCxtNl5 jQFbdjZUGMKXZbk6trZdxlRSdv9pq05cBNyPQIwlD9UWKCh3Au0Apyjf1UfKuNoD8LrlW/u0rhQm 44RfdKgb/YopMxdeGZfQslnbM23m2PzOpFRWPgr8JPAfrZebpWunrQduvz9d/WXWneXufOR5y6Gj Mnjy5XYhQFI59o+lE5A5lap/x3LZeTqLJ7ZMD2bThXURXufHhLXZPrpKJbCpAg5DUcb5CUHVvN8/ GYrhmvi9w5mzYAKUNRv19CnUrYVKVo+p6ebEuEl/7U6kvueF5+unAEJdlZYHVGIJYmzqM/Bycmep Wk1T5QMf6sJj8FTXMl2rBeCBbMEes5kEbTEjBPsVjYrSj7ZWOVLqeR8Vp4gIAxSndEeG2BPdnSAq B4tE7SJ27fCbC9ED+Sgklvt2QzhtBWCfFZ1Z2L8KlMmnE5LgM+i6xlIbG7OHQ+a/zsaq95CsoOCV /EBiADMF7F7Qp1HyPAR0Nk/ZhOMcR5jPOa+5ZoUrHyPUqi4ASgYhwj44QBiH4QY8FfAHfVdyHUcQ GJFjwR87EEug2ET7YbwRIjOz8H+D+wCt4+7p0NMVu8DEK+SvoXi5rCqCcVF4chjJN+IcxKO/RLn1 uWIfnU5+ADOcEdlqw2zlkgLi2bjD95BYIV8EtZU8UGlbtPrccmfU59N+jr5Qw6/sxAsC9WatXIRu s+2WhaTmcewEat5dfFxW22W63Ht9CFsNOOYUnTXTpPbJxV401KYBAyg2XLbUobs7f44fK1vX18Lp WeT0MQVcelUpHh8wYUWIC+T3e76a6fcbxU4In0dvEWOlDAftQWEUKbZ4aBlQy0gL0hF5NLH573jS JC/l3l01aZsJ0HjvotzVi+SeKjZMbQB3HRQArkf9k4VcqihYI38AVOfIaUHfA+A2EHTeNe1zKkKZ oYaaZiI3DJScrdkWkAXFKaVzFahIwtNWan0y4a8O+SLIGVELqJ+QIcD4HlLy9dWtdZhh9bCpkX3r EuBlFinFeu63ikoEaneJp5QLJS+E6hTC8+Cm5Y9Wds1YegQL9o9ajRlSL7+YiTvDWZYRkDEPqNUK beksgfboc9bffeaW12I6JcsX0TRr1y4M2umMSdwEq62jBNw2Bl6j/bz2PQz2bSj1+9M+DiwUzq32 lqSyhzFcSAYCkxSShu/Fc3gNh9dkmF2+gRRZ/iXEPxtCbowOBSwMZqB8ZiMK0rELUszkV76rTxd3 Lcgfx0zMJ4qa62v0Jv2oQdP73cAD6+BAtaEAk7M1t5GV9mq6rAoEnb7bbGTWd042khtsP/G7MR5w kgTZs4U1Wf9U3iCl1mGKQZIBH+401UTK91JzlNjB+QcMXZXDevB+hAGmYfyIiceiqJwjxbnAxYMP 8EOGTMmDSYti5gx0xCLi+3YmJpzHLskdBtRzi2p/H0oBxjSBqGOOlCojezyUSPDOGjb+hxPahhDP J0UiiEfX7TiDy9/D/tfw1oyit4Ie6EVesdRnmpspEx39OohY1BpK06LF5VIvLqmIh1VWJLWJyI2q U4zp5x1/hiLKY58wyZ9hsvmLZkmLa4MEpTpaVNKnVyJIMidJNsTt6PFE7f+jbPVcFlpsTsAzjJ+s mUAwK18foGNPU8DcrYNA/3lEzrAYa8uf1+kFzvqz5bJn4uCT/HE7yLww7PNT6FBaoyXcA0AkQerx DiN5etS/P9/ED+G1g8rDoZrkfnYtsCqHAI3mOyGAez70ptanWayKYF+00hWhd1GCNJW5ez0+jJ7x abCr31xO+7aGgdGL/2OAkNCpzpv9sDL+bRsOh23bIN6GOSogvxOKGHpnF1d9ziWH98uboBbHxeLh PnCktnmOsLMe1kY7jS7/HQC2hA5HeQFmVmMDAkh9grgzmDk+lDcLC4X5o84Q4KQBPz0M2T/fuAAv BkM7FNgAyad+nriH+Dk2dKW0Zj2Py9R+beKvsuQweVkE8wlBM6nCgFNqPjqHBdWObtI229lI8Pve mqW8vQIx0pUoPI7dZA6RbUqaNfQKQEJ9w4Bg8QMCGlRxiNTn4dg5e2sbbuglJKjt3+p5okAzUkel MBvYgjmt02YXPoWjvzfTALFe96UR5pyuvjPRJKI/aYQhCUgoKnfVTYAPK/9cxKikrqKCnjjGgH1Z 9wlT+m815bEloxTgLDMA45A7cDsNxaWelrZH28UOz/V4YhH/Skm31hk5lXw1ZpJ5loirjiPKOWyN Rkl5qaWoSIAiYv7kQ/JymUiDp5vGLfbd4W88p0aqia088/oa95qTh7MV5Y4/pYoXJe8ZxNow+hbT aNd7EmQP3p+GhjvMlBgm/EH103syTKGBlSY1WuKf2eQsqx8Bse4Ks9g3IfMbQ1WJgurYktzrB64Z L+zIvPWGLslsanNRwBsOT/FHTgLd9YDKpHw59uccM89OKwbFWTLZQa0g9wQRnk05/pZJsp1gqPSJ rAAuAmXUB5RAeYeIiZHeUPqy4YXQY/5PTIRJVIEFcImVJGvAlhIkKGaVFZu9ulw/obyNoGyrBSHW 0uIfWnCho5OuXeTtnfLXUjD56mBCuj9+6PDCt2OaMlEIWPxEnPsQSbR3vT2hRuTp7EOtcMo4TOh+ pJe5oUGMT87AX8TN9pIj5m0geAuviRYOThvHoTr9SiH+BTg6DFgg7w9l7j8vvvIXW1aCvlsvpcQn 6Z7Bw7R2u8RhplZjVmL824sIhlVR7sQehLeSNubPe39+bkkP/qY+2DbbmfCbuiYAqdt7X7rh4f3x uIf/fFEO8q95WTVF4uvh6IErWWGRdM7Enml4d3hG/Id5BTVuBI9g9kho8oTny6R4GlMBnjh3MSpM itVnMKv2Rs/O3NcdlAVJUvc88GSfIG4Tl7bFM3Hi/DFsQSZM9oT4mtWRijbFJJs8JjYEhZtp0s/D D6YEz1fToU4R7ROTAjYUKXVjjf9VfLNXUIbYrcIIbie4YCVKnw0O+obbPH0UXDMRZr8NgMgMDHKA P6w0Uj8jnVHWUcH22XklfsAR19kjIWvtzptvvrx1QKnncW3zlS0/tVdIwvFOLYJfWz6TQoCKNzOP P77E5uFz6mNHvk+0yx84ySnakDMWvphba9VmxcDfRteS1Bpx9vZ7LHbCPk4rIe9/JUiUCQyt76CY SOdZCHygOSwAdGzone5+l2f18G8kNEqwy0FresC5ARMEwF25dRdSs9DzTuWR3ZKKZJcFkUBkfCSm 9umH8akkvlj1w5sl79SwdTMYzGfSUvDAHIFFUgZzGXJgEeL9T9MbkB2S4ifOuxHl/d5jCD5PI+xC 2ZNTPnQbxN7mZ72cgE9kQqyy4LvGq2LuNlbF6FWVvFw9UCcCyUHRSrCvJAJHt+30j31zTxLvDEf1 3T6dW+aGwBozQRNEubhfwhVfF4wpiR02haYKhJRvEtAPQ+qsFmS2aiKSiO+fyMKF3UIOvf/YoA/i U6tim9CAzNEUfDSU6PBD4boYm1kDSmeOy2rb76TR2FeUXkKZTkmGszJuw9N7po+ssgM4RuOBYAMW uXDnMJMxJylJIixWuIdiP8YkxZd36Oy3p7AzBx86gHL4us5EgDf2iyRykqsYz6uQbE2Jk4IcZ7jy xklIgvowo8ITZMdcK2r6z+fUxQ5Mro8+1R47FyIdBYAHPgcsPaavZdJ4vypQ3Bc/XisPY8br5ERr f5lTPEqE0vh2CTebHepko446GZtNvsjJ1dIRBp5wJk8m6a5ynfZLoYQ42+1QPakwCksLwq1woSb+ bf/Qi2Cbn4WsCVBKc+hKw60KETToVj4vKFlMBBhPgxUMgg4Dzc0VneDRHNacGii7db/EOtkOa7OA Sg1LIRgXzQjHnRNgref9daxwJBfoXJQIuLN27G6jXkrlVH2Yq/QDUfJomSlhRnmvM16LllpgkibL p41+2b4Ro9BKNd9l8EbFTi5qcgTZb7r6K+QSluZQ5kk1LAp4+Qz8WKAeE+AG32+gwl5GPFPHomgm xi1fWhVjY6vo5AZXdxhlbfHPNTcHHnZGPHa5diWvYUdpgz4sMUrl/VsN/F/HhMmV9A9TjrmY9wCd kUj3kP1mvMgywps+Dzp6enApMgd02rKz2tKTvLLkfcofUT9V2cCt59ws9pRZZsmanbW8QZ4/Vge5 Y8DTu3KX2cBEUKbTKpSqffUNK9VFinqYbpsysMlZAFKN4rGuJvVLeySYDxuXFdojDI/J57LVZLcX uIkJVtIst8LoNLcijVsB49138gc9//2Nhi3UUgx0A1HeM5fbX1EceB7NGwLiiZ9JmY59Jou6DPk4 0ykzjImH5GYBGbn8ogjuXXiI6V/V3mpUT3+qI4HO7AtZkRolzZMy1TM0Oe56fYjZL3QRaDlF4zbS t0pIdKxoc2DfLnQKxFMdMp3IbzZ6HxMTbjP60clZ9kueRxvRnI2naEY6tbncr5bXcQixtHGTij3R MhIb4jKNoptisLPRGn2xDjHvjbxQTLLTsP2bv8RZaUOwySXfArjpo/img06qPTdAORPk8iW5GTAv 9G+32ZA8v2C8Ni8x3bYvkQM7F6fLn7DQVRwHF8W3JxQAUGjrYmGfLrv1zhBwXrv/tfixKyvBu57J 633sBNP0cjDnuuTZvAI1OtKVKHPciuUj6EkKxxnFHRAbA7GMj2n4GXLqnqC3Ggc61C6Ugxv8+zbJ DWN6bbncofoiSea7AVan2SlCm32AFeHNWi1GHfTEEFPUgIOp/fiC9NPxpKC56Cczh40DNiqXbL0m VnJxncs5rbSoa13hOjA/9xYxTQEd7vwLjgySH3Suo1GuFKmCCUezEPYf37S7mNIyaPIkPaBigMla veSU5PeZZdpTUVmGNqHBhwhk57hTkbjiJZ/QFsB2LQYArcSjHLdGuJf1dSoQnKjBblxXmoCwFZ+p hzv9vFZ78fiDLrxRbLkt6B/3TgINzWHaEu1xwBj3elAUlzjIfXJSQQeT5zqs5rIfWlyy90aca9Hs CEDl5uB3agLTo1OXTq8aFOONslWbyl5voOcVsJ2jlE0J6g2xljZTCZfGHArB5IxflhzvZGsyCbqk bCDqeud1sYUMPE1Nm/sbN4RrYvPsvPfQj9JTXLJjKMte4n20E8q/lrZOCJ3pPB6vTz06ZN1MVDwa 904yFczexOWituu97t/RcSRFRn792qbu0R+1SETnbWHSmlRgUx0ELVO6hSqAdh34C2+WykTrOBzJ oRCC8Jy47b+CcnujdbBOUyd7SbqzBM+Esmxn6bsIQc30y2/C403MubcN7n9Ed1xPHk2LhF540pZv 4EX/phj7Mr1QA/I6bvhm3bi5UR7hqbkasSxwAxFWuhFJd46mYIey+5/te6p4HlMAaCnWD94VKDAa /QJWQk7u6qLNfsLPSW/bUWt043fM7onhy3U5D0so0d7iQJVAJmC7/gruqKqIflj9z7w6gwULk8ro X0cj1EjlrvP51IrMGG07djJT9XVorvxdM8YWcKTaEZsksj+1rLd1A6+/5m29wb7uJiiVmj2u/ofM UYyKXsxY76o9qyX68MVHA8sNnjNrGRi0YgCf7xCj5eymPhJ0wlx2PfsyqvWcnaaT5eBdZ6Jl910J uwYf9DbI047QQskLxNKRXMlrlpUj1fYAYk6hbZ6f0q5TzoxfsaAPQNkl0zfShQV1oAmKGUMOTz6W WzVgDkj60LT63q61/Jr6sFE8U8nuEF11+jURvVnSnW15PrommwPylJp/1BKv/acWvMJ0IVcNgg2i q8gAmcUXd4UV23C+rHy8weNghXvcn11piX3M7GXZ57tw1pVkGUdcx6AS8MB7s5BO51VsBJJNgoWr 5qUIlkztOmEcV9zRZDP0ZFbw1gdf3J8UxzBQvYJJq1q6LxaW5gcmcaaVlYOHlo+whEnL+Bthr/X3 UIOlCgYK7PothK7e6p1EW4AXOrwY3BE+5wqtxYGtzc5IKOes33mvHFGGMvbaTNG0K/nPk0NkzKpG d1Z44qPhkb6qEb0TbrnDC2itkE14zxrdJKoy7+27OtsdUrFcXZjatFZNEMbDu4wDnxCvK+WI2Ndz dRqVV0QlfbHwc+fzf5bGVgjBsqxm4gD/qCuqaBu9rh0IUUSCzoxv0PxtSN61yugLgFbIFlntHimD JODOnAc+wM+7vpBv+cPuw5Tq+ukkNxC/Zx9cwTGhBBu8jTR1uZNS7ASuHvCCeE0XzNvRoeIgdy2c Ct5noSHUfYusJjZHlpFZI+/Qo6LTihwYLAYja5nAlPBZ2b7YogzCsbv44uxzcKj8yiVVi0Fi8s+2 OusdWQmGB80mZeO1XN7NOHmwEQ0NGQyMcormtEeKCE0gG7AJXaHgmZIWUJOQP1puB98aXoAZ561C lj/Dl136qFypFal6h2858Ew+nnv4L3TSLglfuQWYQJ9SlBx53U0ZhXxWUwb3D1rtNrtcGosdnvdb yaTuMhNRUVNcL4r3pc1i7sb8x/I+9cf7ojNcJSPbG/LXSKA5I5C+B6u0fyIf+RaMg3yVgnWWXOS4 0pdUPDKg/XUV3ih88X3cOJ6j2Xc17D7jUqy/hAQPahBb+DRAm84FUTa1g8kfqFTKwXOnjG8eN+h/ D/H4HeklTGe/oYvUnqFwgXBxQEI2qnW9RDd5wdM3e8e657kHLFXSDYgAWrHuH8vtcnsr1NeTTh+8 jmKlX4Og+dm650RgQDsa3xaK8CHtE8fFOYOAsEfNJgfb3RiSBGRYmQKFgz6PbX2ywpA0FhwYXEt7 OjKIf2T8G15iTDz9jnJnu8qy6klrtDvKMvfn6Yt3tAs3BQVPWoYHJoAy2YAmWJzCmT+4fVG+2t9t vLbYVNbC8ezWaDca77qrZmX8WwKmxmCTtY/H5dhnGhZDpp79C7Digv6/1RLj2xmLt+AnY8E0nS8C gwQlgDOHrVPUM8cAXrsj14zVxV18FlHVRP3QBWv/U6kl4fzKczrkQ+DI6ri2u1N+5FSzGHYsORz2 +T7Ed/al0dbTXkfHrUUv0nKUHy7W3NwE3ExObMvvL/yiIe8FNcTGIpC5fzL+rKJmmZ3i0+JYPik4 yiyK6qKOxZA7CKaEvBPhmmuN7xaJOaQEhy8Yx7LBdB3NG22K0aKK+VNaYEQD8sjwKDoeH+KodAhQ N8jUpEBigEPtnkAtTOSTdaXA5sIvOSMo7uDGowpOz66FiVo5Lapv8JKp/vPU7fiskjd+HQuE8W/i yuqKnSlErzoXcEB1IvYMlkop/QQ17AYJ/Xqs9QMtGEgXRl+LwaTA8pD67Ra/SBU6se1kUN6HbWuw 2327gQtid35mMBG2dOq88LvmYiTmltICswMtYo2qIzJ96OdyAL+deXaE8f2v+7VbcrO3W9+tqzGX 8CD1j4mi3e9r99mDafhY1AXYb52ZDAtOIlBU1df6tD4B8J1VpHMwEcF16Qt8q4afPk9vJ4j+8aFe 3BeJrjrTYBQa/rkzwT6mYZBI/cg0mWEq7uYroiW3iTYi4HAcZKKb5GQzJnvartWuepavHSA7mXGA +pzdogexTIK8nHsvX7Qek9VyJwLkHr4z3xfbMb/E6RhR4vZ4W3O6XpppLz2Jke3dHJwyUzZz0Df1 xvwemhUnTpg5IYcrvWJXb7rBqlEfI2pbjJ6vOarUYRoGgfKHNTM6GivZnAcFlOnwXJI6GPwiJ0D/ sgvhnysDCK9RrczmuwkhMf0qIkJt1rZ7NKbJ62qvpoRZcyZYbOz4npqTWze6wZOi8oTLVx1c `protect end_protected

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_2/fifo_generator_v12_0/hdl/ramfifo/wr_handshaking_flags.vhd

5

12657

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block l9qS3t+34Adw3J7tzEF6mdxJrAFan02fIUr/4xjQbFxJztYO8Ss8efJfcKuFdSM+KgMwDxzut0r7 7wUKes/G3A== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block D0xSMGVp1kA364gfEeBgZ2Tu6iS7kfQ4zOA/16+EvBEEf9d4urc39zBLLeFYyI+kO+GefLswguDl LrFagcSf5vM8HJcQXy6nYClvbBVol6lGSl6JttTC7gD4/KAPOJ9yJjmDse6Pp0VQLeNYVJxO2de1 Qg6YvPIP0TmB27TZpAk= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block pa3K+4uLLYd/JDdKM4dKTIzHVhp55BgjObW0d2aXf8oi+A6zi0d9p/h9InG96DGGV6OGmaF63M5r D/ZvbKf4SK4g2ygA+6wzuS6HnosV8Mhi9DEghG41GRMMmBiZ50GzzC8q6+Zqvd36tXHRGp/XJ5OG 9UuHwOAfHyJYfZW+670RVCanD8JOUK3zfJGORgc738FPH2ObEHJqWarl+/7UazVnUXaAqPgtVZKX AUGFmiTmYaBHnHOBTywp1a2T3SOGrs0lMoktS5ia63W+4QHt5bQNGaWhQyyYf2qW3xwAe3RcZYhz iarzMT5YkN3/AiuDsWYW1nyJQFQ8RsGMhksSMA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block fSCz+VtGXT44NsvPvXV/l048m+nIHbFkEqlytyRY56VQ5UwFwh0Hq7ptMEPECN4YBKpjlQaTv9fX VPkJAqzm6fQ35ymXEJsK91Rt7JTjNeSC54vRUR3yaSVnwF5gCDaisyPpXt2LhaTTxLVX3QW7Tq5X ATruKUzAJXwuE8GFWg0= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block Zg+/is1koS4fIUk7L++MHC6v5WLMmMP8ErlAst+jLhMPnoUEx9yPd8id58awwI/b626nA22mGWMY Kl+7LuXpSSz33I6sf6J668LCCwgloJXoM4d88YCwfHS3jBFOxAnx0N3jjSieb2lxDgO//zri8e0G RJTduyYmXbdelOjUXLV13VxxOTYMxwoHAYlRD0p3dozFYgddWp2OHVngKhVWR/jpijxUT+A/buTi lmKCpTNllXIQAjIBAPMlQYJfCDaSSPZyvRWbfgPgNqAzGuNReZ3Bjjpk2Zx5yZV+xTXQJlwo1q/L JL/5jIhwY21gO5b/QHaYV4ciSjKfcSuU2KDxBA== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 7632) `protect data_block 0/4fBZsdE2xh9wJ13KHLYL1nla34IpfgL55KmCEOb9cRaM8gVmfCmm8qKh9im4zapCjdIoJBUeA9 DwAid7OwQCw+x6NopLmry2GP2Wf82NgpOIFSHF0Qo8mrm/q0ZXr6H/gDHn78Ix755tuLis8xbM5R 9IjVtYqSkk8Bg7/k4lN3h7AUca05+D1VgUQH9mQUt4HttTLkJUAnZ82nmhfkWKqPSbMI0GxWopoO 3h5Yfem/9zWYtMcWAv/SpoAjtFOJKeLvvVMR8KBpHdxr+fGgoQV5c+RxxUaaggS6BhnAL4/b+yRD ELClaYyFMVj1YKAYs2WGi4WjVnGue/XiHhkr+njtzb8nCPOrC1m3n8WTNTld3xpJ95CD7ywTtBzs neLoBBQ3Fh3xxuQ2IOQNPPEmOR3bhkApOYmlxL/TD9VuB6zdbo8CreHf7tOg7YdN0DfemrMEbZ/j PMVMA1RmA+jRnvXOeRhAV4pCg2QoQoElKTBOP4sfN6v4aQMjvEm0wCr267mAl2xCR4+ghpblsXIU WKEERhY9k/UQExwSmoDXUj1ACD5EyhAto3tTG1OUplpgqS0t08Zoq8ypxhuzk+l6tc7+KRxDU464 pNBxcASlDHXYpNX/qzZMb96i05kbnSyaeRljOtUaY+7uAmjC362VRrlIbQahVTAVyLKpxbZ38pHd LMZAu2pBnGAmuXxEzHMfY76uBChwab4S4pQPzgjhw412OYZfl8xJTieYa38xZV43R2Lr3A+ZKvbK KV+San71V3TnREFagiWONdmB4LEjAR+3ql6Bcv3h2YpHfgc3i3hs/D2LnlJdM4EhZVIOi6RVdRvo A1gFSMmjOIQ/4GOzJtOEd4unQvTD42IyydLylohgADyKNFzUP51hHsWKec0BtsAW52LBd3z58Wel WpI8ExcSryyqPQ3GObRuxSa46sYLI6tZrMul1Gjig1JEzpUY/L1vnVGFqulbBRaxLMgR/AL6382r UgC4t+1Tdmfjv3DMoPWQUQl1ebVAGcAZotSi2W9Bn7W2hhz/bNCIKlLlKfh03cl5Gkn19D2ogHgM FZe/Cr5p7DDlsl9RlvoAkXalQKDSRCNNUkGltiPI/4dFHuEqGRM6qs20cRtq+CW8fFGT5C9wKtwL rRFD9TSVBD3JrfRQv3KUBPDbuZr+rCwH/yZQOhGiyrN1DbyOiltxvtfMoRtMeas7UxcPV2eD/jl2 o4QngUu3M/+0yppDeFg4YKd2kcmwCCVa3Y2AoBdifqF0E1C3Dj7OyRb/EwRO8gEcrVDU4dBYc4AL ns8TG5uFg18uxQHuITF72pkJZFApZDfrCV1FSPxn/b/eAf8lbR0yzYWJoMgBMuOd7nRxqHI5Qln7 u+ancQRDvFeVOvOZzYJuZ8qwtCMnfEsOM+6UBVDduOG5gKcLLTb/nPP06+kja01gBZZ/vhY3xFNH FubvmWA3xfzUmD/ppM8M+GcAfiWjvC2XK21fKxqps2gHZCeKTheATKC2afbIB3RbAWtzaH95cEae QR/Neq8uf4OYBmzh7MXSrBWxlsxw4llA3YT/OnbKVoyVkXzM7YaMQ+ZBtiP4sBMby4vJ4S2FTa8g D1Ms8PXZn9+3nIlJQX51WeU68ciV2O+3y4p9u0D6E0da8o1bvfGt0mHkEPVNhaKMDFm67K5uQKBL 6dlgkOmqeI5bzkoHUeHt2wTwWx0EPFtvPM4TWAX3buTRLkmXyACU/zZGwx9RToKQnkHTi8Z03nWb Tdfp3VgmZ7Jj+gpnOiBnqVTkdOoqmGWDICS9+mme+AZgpeh0XV7hy9Vjzr6Cw9tM9lST/JV941Yh CixtC6gbXqfq6KfA0q7tpfogQb5Zeu9PKUFh//odw1jOFS2VspMwHSUbrFn8wsXdlnNUwYvvjU2W LyyUhsc+IFeZnn49Fs8wgtHa5Zo6ZUjbMqg05tl4qaSeTYTeXOeq0IE+22DI+YbK6XFF2UUt+34M rNVSJ8svykfjMBXloUwNWDB8VI5JCaujpYcSzNy4vPYPDOBRiV3EXhnX7sN0vRAK7NwNF3of32zU 7Sgf2GJ/DMvzbZ2TZqMET/2E2+3p3R/HpRbpjR/6HIvt+fnmAVUf9KKSIazFCFTOXKhyLy7E+7zl gcLss3iNx/VeoeySUNVQNpi6rKTQpLAEXNm/r9ZWj1YTXPscX/WY1xsTdlOXpa5Wk6pVSZhrGjt+ MP3zfm983DAC6kMmZExI5nak5ax6UZDrxfM2pU7ncwnzFlVFvPJYZ/0WFQ4G6rjZy6o7D66/SVei B2Jdx/xOaHqcLBYfkipDB5j9IX7V8qbxRx/RJjunIdbduTzejOalqbT9hJUgk+ebvTos6gK6rLhY Hg/e4Dn/gYzWiXbwtpsXlXTsz6dS8qFmGfOnBff8CYlkTG4lyfpguWn0W2+qDf/I38QlDw/OLlRa m1flLIztcuOQfWLuL2dllpqqB0OURG5BgmEXOk3prELxrhAjPsqbQefV+eXhXLyn3m1GB9V8lhqd RBaFbv/DFNDAM7WR2uoCSzJfE5962EFilbeet+JTbz4W/WtcjDTt0d/g124lRtYj9IXhR/fgk0sp 7Z3PNKE4lIi8tnzY6tbzTzWkwVDhaZITSz7I0nyt9elBM6FE7nLRVwFmGPur/xu4XRZnOErkaztk 3EH+p/Jg1A9iHQLz66yjuYISw9aXLM4d8MnvIr9rjfwcIyEukWmIWDlhLFZ7/aGYY4EuK0A6WmxX y2CGboa2V2UeCgYjoNnosAp33Xu2W/y6YWUR71RgNuhtPTofRrhCTVazp9tx55YgmOM0OQ1Z/dJQ 8DgSZLqhArXmItX2gnJqT7EteSPeYxzOUReLg3Gvvwr3c2hsOSaaXbiDPeuXpGCJVgepwm9s6QIQ ZXly9IprSgAP+27IzFR/CMN672Tsy1MlWnoS068Ur3kmvYMQgCfjKN+/8Z15uAaFly72+iJUaub+ 2+b2ntm+oxem4W0wuciEPHIKWNX1iFVHcTv08Sdn6K2mAV8P3/uVSLesiK898UbV2EIY9z6I86xG VqwWJmqE4NCzRO1/NFxDYgWcc38W94PDVg6AgYCrIdAeCPt79UsLv68jZrJTfZ569n12l2gDefTJ QO8/u7lCt8Jj4Ia8QciIC8eyNgljEUmgsGk4GaJVJ8sUkKZbfeshm6/m+e87zQqbWjecTl94rI43 Uil1rSHdJUFOCVGXN6Ip0rdMB4sAiSHf7WxaUFESLN8ftklVsCWXdRolXZ/LTiCvQwjjzcZ3jdHd LcGssCvCIySyTntgkaw+DMlZfafoHWgaDDQwG3+Z7109G4/JoTI3Gv424xKJ6IO0GnL7568il26g OVfsfBMQnPKySJfDO9U72qzHxaFZveg3a0qJZQjpYGCMrhENl9ogGOuFZEGUwMQk9hz5O9Z60GKi WOskm995mnbPubKlv8BrN6xiRg6rTs+eljhCcolpyqTeqLxQ8mP1SsjFU7e+EOcQdgbf4ZPTOxgA g/QWT/EPF9Af0yLnLXiwsnKYq6du+2B0AooyoPFj3l+enDcBAVr4WCOJTTqTu+yhKxv9QqsF2ENn 9GfJ1du9MC0qQeHvD2rfKEQ4rqRYmVCtgxnHxdg2QxrqUPTCSFwpWJNq4h411gnMK6VBNYOUcdFt Pyegg9xzaF+1K0coXtDObOh01I/Jg1DgeZ780u2BwQacQQ/xEUj5zcQsgwxIrUb9fx5XGxzmaj9s N6T/Q2YA1v25A5N4jbR3LkLuTgR5P7cU4cB9s4YwPLyuSQ3CJaaAXaqesZo10u3MWbl7RTCCO2/s F0/xSwL9cUxPWxkp9VTXdfrrV9WaVHX9SBrXjICHzhgRCCxeAeYAJki7fsa+9TBDN12beaKUI+XX GttForFuhecDJwahltq8d057sCS5QVtFIMgdk1qLycgoRW2IbTDlNaSmySYvlCmFr//mifvessZs uI/POjXCI8fW4nc4SfuUeoIhe6zL3+DLFp7CfQC8zV63X2kt6agORy1jz0HH5lInEXJgqtuLnTlk W/5+zDla63ZRhFziAoWFZrVfPi6vsmwmJOXyhCFRJnyEka4YzGc7Y8CjmBJP2Xibm+NQ5IOLyvMe JVn43X+DwCE1NfWNpfLcmO7/ocG4x3CWOAUyb7xs4LWhiXnwWmooxGhrWeya449x82ihXlPDLmKG rm+Hz8M7Jyk9kSzpAoyvFNvhsh0JBVDi2wAalkHwe7bNyYe20CbO8gynr82DxsDbXuOsXIOrwKb7 0OC2kIN75LlHnkwp4keQy1teduP//JCjXXVzDcUvPHVec6Ar3iNPqCcxKxVMqh67gtIqYI4WyURh quUxVOF4J2xcJ70ker78ual2EUTqDsCBM3E3sgYNiFe6YePg33zkqThnweYd60ddyWU6fZxRmwZZ BBk/vDQQTMiJazOhbFjeh4sIEvfuDfwJIGaa//0NYbwnd6DhurlSF/JRv2Vvp8qG8g1hi+1BwDVE zJtt621NoNR5ZWMQq+x3cS6euZl193Uizo1veAoYg3AhY+MJfVirneis2l0XPEqFRKXL2j/My9aC UTvrZVykl+PGrEi8/t7c1831+kv1L9dNUtCR85migT9/hT/y+f+2TMW2RFf2ZTSHnM7t0DzL3vg5 71K8QjIEp2jCgTV4TiEsOeXTX0x9hqvkM0n7Tefg/mI2/ikqrELZSlsCkVVtRu4PERg3GCgsuv26 CjI0kBXg7/IN9JatsTiybRWknpx0dGZIs3eiyDmDp5Mev1NVlqLN8JxcPsSagA4N+GD5TGe29bX9 1dDvsghZIID1n3GKDI7B+aRMvlSei1xiqfPejpKq40r5R+Xj1bdhUcZXGRU6pLl3ZkRtH6yjSQah +o3MM65kcHynYs010/rW0U5pxRoqcFAOBj0xrLQj4RmxbXOAoMyn9kl6dIYTU3pW3t3Amm6PKdtz z4BT17ckoVDuW8RArUn7Gd//dxMVbNFUVrWZ0jSL7+3GhNayPb1dvZD1eHvtdkrsi9k1G2Y7yp89 y1iPYy/BkTotxx3p3aEgLmYtVcuFdN7ZuYNqyhbdYeGJk5qyB4AAdC7pTDl26hgrbRSzQfaruznr fcfOSOFkSIjm3UqCCcrzFwFtaYnpgqPMvVOyME0Kmxczf0V6yXW10SDN2z69PE2lvpAlAJV11oMd MNNTb4bqUH7b6DNv/K2rfy6TtTVahFINhFRG/BwoIoJk1Kxn1ovqCKNyfTPpzgn+dtnbbCwp+U/U 13WOvIjJdnz9qXtYrOlBhzG2TLpSW8Q03iTvvqfQ84oRg3ZS6i38zD0sUXbgrM4gnkKYwz5TyIf0 OfwJgR9vqi92BV92YVGs6w/7RCeHzXNFpVsc/cHVlkTufV+RxpuOgiZvwOV5mlrzQ2UpBn7owsSg w6jNg2CB8pAInwvPaBRc07jZrYEu68ZS4INFSEcZUTBAxNlitJQ/kvpBJPMHjVASbCjhCMnZqa9s nfQ3JDdY5KZtltqDuROmzRgcDMIbTVGJvp5YW+VTaxHSQVjzqaoY/JKNEG+SLvp9WGIKsLaJ6brb 7nDKsm/b3wDE423jEgev2RwZcOi/3+9BO4P8GllUmnAcpi/f2grKKbZQnzfhglbvUzBVsFvDNyoH Jj55Ce1EVpqiv2U/da/D0qeAnU+/8pq3TGzhL2uw1Q6GadsIifMo1h0j+UVJuX/Zhy2NUAcCzq9D ttjM+3LDGnY8C/ieYZc32QBA/cwvlsXcH3Lk5eirYD2y0q7LxcRJePTNTPA+LPTdgGDtWTOL+0Qc pnzMZ31a5K5DQbOhkx+uSxCdiamH5/6HYn14zuaYQPnsNvxEJLFvA0l9eJ3Y5nkIKdTnUx+wlEJo AocnodJiPYxFU2To086NvVi/vN39JtPf6QoGaL/ekQDEQwXawkUzAvxtzKKFV9zFVjl4IOEBtTqv MU2J+gZlw9zJ/Ciw4DYMkoPxcjYAVPO1o6qGi+NAidlse8HJ7k4LGXDb80xIulWA7UQDsj4Uo9WP Byh1OVTBIoBIcVNOLqh4ic3swAQ+LJXNHsMuJMkx44SYpYejYkxW0q8D2/DFobsBYiqgfxNDJLdJ ygadg4urUF7sdEdwPpmTjfBRkkO0jZBt3xB8NaAanfbBuEzE9Av5oAQumt0E2CZJw8QVM79kXAsU QfruUp+41SzymaiBCoq4W//zTImn6ZpRv2a67S9CC2TV2Th8Rtgw3MeN8xsEP0glZaJpy3bN1WbW kpitPqdYwtbetBk/GwkocQCs3K1V+PwGXPNco+PXSRSXByixFVQDUI7asBfQcTBd7rO4ZqMXuN39 BOgUZtMEEu0bkxaSJTd4xfYdauZpn2SZ1PSFV0ighih5xbov6ExbHeOqvz5mVDkTd0eOzAWUfTTg UMeHDtDzmYkUqJIKuw5Pke7OQ0xG6LTcrUYG8FR9ctjKmqUrrjOZK8p/sNtCqjQg3IAjHWtqOxLv FDafuu4g4fwgGeHp6YsMxuANnlx3dRgNaCMzmpzDNaLhKBaEym8FIHi1MSHaRTQEYZq47dmUvz9s po6ySRfBREcdh0PC4t+5Pw3CBSgpvMepZivY3XCye+tURCkxCDazUG8cJm/5GSwF53cgs5ecjeR1 tGGgLWNkAWJvem4Yu5mgsqgXOsSzK/3hPnvVgW5KM+de0k0jvfiwLeMB4/FiZFg1g18FwLXtK1Jy GNiX/sSS1/KZSo3jwnTwU4tkHd8WXZdLx2JBe0eHupOB8T9fiTJGUhxFRAjKgKW/ol7RGS8Cvjc7 plpAncerS234vrEe8FoIKFefTp8AycTKkyfL1QJq2gHR1V5vEFCb5c28Tdwk8kGKBHX6C5DRSzNF bS7283gAchNGFlKRaA0SU0yoDfB+l3Uo3oECoCEIhCnY1g8NM1h5iuYW/G/O7Cbkizr8XHX6NA2W uPZjliHj5ud/DgR+6Ul4LSDiy2kfeUsfhpKxms4+d8T8v2lXgkhZxlVvp2SBXh+NiePAt54MiwB8 fkNnQthsYbnpJo/Nu/81Hz97bD3GDkoyUoEz9Q7Sm2o84cSJA3YG/oSvnb3uJD+8uznTJxcr5pta RMqGsdt4QU6gzewf4Amwhjwuxt37vLy7/sZRkLqLKAhhk5T/uM+Aa9CU1vKwY9ZLH8M2iJAm/oev nNlTHEi1diT2Yfmr3hjmDjQ66+HzXxZEsU56AW18R+xv2a4yun0QWZ3xW0rIM1SVGrQWwpuuGTSx EWgkTrP2Ma7KTStmRfoh8nawLBOv28gCCK6PHXw07OwVHWtpsG59CXbCSTFpF/eiru6i4IWKH1Mj FjIu36xXnD1ixm7wvm1m1l/8i2AIoh0GjcvovTLSjVEEVLvYHfRl8xVHegTbtjOMeIX2QSO+1fRH JbVBpv1JjgLvIDWsE0JhGJBK+aCV/2ZoHB0gmSCDxVo5jrM6pimpJo2h6RcfBfs01769eJeT9+US X1wXdJuo4IT6mw7Ii2oCf8YFRwVzx3UVZdUMP16m+OWe7m07x63z4nA+0xCeHTEddRm1DkBO8tuR 7D2haQva49eZpWayEAZIBzJLQHzZIeKM7G+sbslsiTZihDQdVQ2TQEIqkgqTWrR5BguW/ANmNmlp eBeoIzsXERru3Gq282aheOPXmaKOmxQvPzWYFL7dPUetOf3tUQ8OAQ3U+j7Eg0ZkDOI9bRywY6gw zEbr0grM2xcFVgfjX+vo0pqbjbcKSJltg4NM36Lf/WLosuzqlUmuOgfYkP3RabYXJ4fPxAHLYOiI Ts/GjGbiSWuQs279M844yTMohOzrvzyVbLeyiVMCL5kRFrzILzEyRBL+cpBOBP1FxFCU1f7rRraq NqmKB0hxPuEn8ecN54BoU4Z50EWg32dbHUZEZB0qUJGyfjIqv/+6cwepBT1xg1lrmijD4FffhcPa uD4EZJA2pE1dZ5ENdXp4H6IdwRhLUWRzb0DE7XXjh+yykLeyYFrTfOSpR+upSnQKfvBtWc8eZTaC rOhQCgdqPOn3hXQHVx20zeypJ6b14bRcAt4pT54shQibcAIK9z74CprmkYTzMUfQRNDFaMsegQFD EvfvGOdQE40PFbGM4JL/ZvY9vgHvSPiSUDTHb2XQ9Xb3srEFu+O3I5PHUZxtYSJT+ebd95InQqbd BYrfdwnTWXdD418LFYAw4P8r9Umy0MMZNse7g9lhPy8gRPDJcYCz737rA+xB9N3kfGY4YRcnzzwn Se4cSGGprVMBPZuycvUBawEdsRZO9Ceqh8aellAAHE8DvSClqnPD4Rim+wwDq7J0yu9lklJMNuNO poheM678wvAW0FBemZiapBk8rzGDT5TseMgbb0VIaIwvbQLIYNlDs9lyx3YxIzfopd6FBJ3SaK/P xHTSNqQJA+pcIi9Z6GBVKAEm0svdsU74B6+QnzjtyQNpMCB3yGzDLu6j0Zj8TcH+SkI4hCVCKcV8 MG9D0dIKHpdgbwwcpEMVMJxAyNaz26ltUf9jmQ/ORDSFz4M4itsAy0Lhsue34vG6ITPIzmUen7UB aKVdSVz2MjQ6G4gytOr3vvhcAQNj1IMroPvT0I7APfhqWcRJeNwkzLRX+UWKWXWO1O47ZUbPktIc 1eS8KUMEv1OCsssAeG2et60qSb4GnPMGmgIU55x+DRPMkVCd9sK5+zy77PyQAb9NcQjp96WOolo4 9IHcS6ix/9Acx5cYG9YwVje/Ovc6KxsJGUlbOODg2VIFE45BcjOVDIgQL/BBQbXzrN+AYu4YFrZt gYkwRo8EYIGoZG8bDCPrJmIs4RUAvbtAJmLFNbq+/XajW8lC3sMUSEQ/PhKvoOPt5KhS7b/f4euQ Pj1Rp2JlSzLxw4zFA3JjeNarb+RBKfpFCSLcvwnOr/wrlDjG/pV3lwHWMWB23ETVYDqOsvnwtsMI /eniKO8s0/VYlcrwsYw0gS2xRI4KzyFs/J9ss4scMR17OtQgGwIYR+w3wGCg5vN4Vc8euUTiVl2Q Fmp6BwvSDiF7mgxY7EuplpApMLXr7k9ilTYejm6MMNlI8rQsZ3Rzt+w6pAEDrdlP9C8J+xij2hbL TutPg/DyjVJQbh6OseEMynbIzoMX0PNbfn2G+zzjqFKGk+2rpf1nKTJPfOqXFlERDDK8l/poi1JP HraRciYnlFzMdDkHYah7YW704VUtK5L3A6+liTszgEPElKePGSKhavGY1CP9NUTLkt1/I0TIUEKl Frh36JsjPZZCRpTZUswxc2QgmR1VuoK8V/vdRid6kY1M+40WXWKKZK/QyQXjgqCM34X1kZgQwrEF bb9feQTN0E+ycSuixVDhoNdfNVXoNtabyLoEkPC+JxpE+QiJxDcDxQSLeTRItpoq7c49XxGb+y3D 04r87zBdacfWKemxqL2mctftFU0aJDFOU76t2FjvlfI+NoQ1rHpGUU8MwaEM9qEOb8c/DLe2lHXh XEnjSMEIcCPoCgzBc/l26VzGS71xJHrGyCYn2cJ5vtGpnypBoCUHZADZTHaqE/d9FUMBSz3e6jOl f7wx0qlme2kY3gr9gR1m+Ad7iJMFj0KqyAq9v29KJj2Mm5Bqe4iN+k61gnjvHt9cX4IaS7SJzfJC JCQJbHkuJYvcruJ5mJSJA04yw7ex2NKL4FtQ/yacK2fAjc8saMV+3Fmb+Xl7iJ0IozLf/fdQOqeh JmsKZdtjuyz6RioTkXlqtPtPzxlQC1ykdmI3BdhTmawjgDwuDDPU1dFaC9kVvxyrz81qhgeR2ah5 LpAIps3FllYgvPrc/Mpy6MXAj1KKTaueCylOOGcVYdrsaMcjvVXVogWeG/TeuLLAvtW5Uotq8pP4 6YE44gLISwjzVma3rxWh7riMgnBXGGn256DYjr/ZYtKRn0nSl82onXh33VotmpZfisRwwekiqtuc bWrWOy+olboD3F6J9sWUIJhAzy/85xcS0IxmKyX9xPwcjWmuY/QuckofLEfp7B+WcNIlj8LX7lI7 rAiPVZZUlv0B5AkNOeWf4WgCnibLOqpqQgdwZqHplFx9VK0iHWLtQovB7XqlVR/5tYLesNcBWdNz EzZfWSWm9jxVqhF1Q4bP3eu7WR6dexHptydqPIf0sF2XJEMezWZ8Vpsk2IKYjsBQvMEVa12zLC2N q1T3C0dNBWqz3rzrn1LyJ8CuypW8mEEe12VRWxzizfr3I6XmSB7a1LdloFFen7o3pMne `protect end_protected

mit

camsoupa/cc3000

cc3000fpga/component/Actel/SmartFusionMSS/MSS/2.5.106/mti/user_verilog/MSS_BFM_LIB/@m@s@s_@a@h@b/_primary.vhd

3

10201

library verilog; use verilog.vl_types.all; entity MSS_AHB is generic( ACT_CONFIG : integer := 0; ACT_FCLK : integer := 0; ACT_DIE : string := ""; ACT_PKG : string := ""; VECTFILE : string := "test.vec" ); port( MSSHADDR : out vl_logic_vector(19 downto 0); MSSHWDATA : out vl_logic_vector(31 downto 0); MSSHTRANS : out vl_logic_vector(1 downto 0); MSSHSIZE : out vl_logic_vector(1 downto 0); MSSHLOCK : out vl_logic; MSSHWRITE : out vl_logic; MSSHRDATA : in vl_logic_vector(31 downto 0); MSSHREADY : in vl_logic; MSSHRESP : in vl_logic; FABHADDR : in vl_logic_vector(31 downto 0); FABHWDATA : in vl_logic_vector(31 downto 0); FABHTRANS : in vl_logic_vector(1 downto 0); FABHSIZE : in vl_logic_vector(1 downto 0); FABHMASTLOCK : in vl_logic; FABHWRITE : in vl_logic; FABHSEL : in vl_logic; FABHREADY : in vl_logic; FABHRDATA : out vl_logic_vector(31 downto 0); FABHREADYOUT : out vl_logic; FABHRESP : out vl_logic; SYNCCLKFDBK : in vl_logic; CALIBOUT : out vl_logic; CALIBIN : in vl_logic; FABINT : in vl_logic; MSSINT : out vl_logic_vector(7 downto 0); WDINT : out vl_logic; F2MRESETn : in vl_logic; DMAREADY : in vl_logic_vector(1 downto 0); RXEV : in vl_logic; VRON : in vl_logic; M2FRESETn : out vl_logic; DEEPSLEEP : out vl_logic; SLEEP : out vl_logic; TXEV : out vl_logic; UART0CTSn : in vl_logic; UART0DSRn : in vl_logic; UART0RIn : in vl_logic; UART0DCDn : in vl_logic; UART0RTSn : out vl_logic; UART0DTRn : out vl_logic; UART1CTSn : in vl_logic; UART1DSRn : in vl_logic; UART1RIn : in vl_logic; UART1DCDn : in vl_logic; UART1RTSn : out vl_logic; UART1DTRn : out vl_logic; I2C0SMBUSNI : in vl_logic; I2C0SMBALERTNI : in vl_logic; I2C0BCLK : in vl_logic; I2C0SMBUSNO : out vl_logic; I2C0SMBALERTNO : out vl_logic; I2C1SMBUSNI : in vl_logic; I2C1SMBALERTNI : in vl_logic; I2C1BCLK : in vl_logic; I2C1SMBUSNO : out vl_logic; I2C1SMBALERTNO : out vl_logic; MACM2FTXD : out vl_logic_vector(1 downto 0); MACF2MRXD : in vl_logic_vector(1 downto 0); MACM2FTXEN : out vl_logic; MACF2MCRSDV : in vl_logic; MACF2MRXER : in vl_logic; MACF2MMDI : in vl_logic; MACM2FMDO : out vl_logic; MACM2FMDEN : out vl_logic; MACM2FMDC : out vl_logic; FABSDD0D : in vl_logic; FABSDD1D : in vl_logic; FABSDD2D : in vl_logic; FABSDD0CLK : in vl_logic; FABSDD1CLK : in vl_logic; FABSDD2CLK : in vl_logic; FABACETRIG : in vl_logic; ACEFLAGS : out vl_logic_vector(31 downto 0); CMP0 : out vl_logic; CMP1 : out vl_logic; CMP2 : out vl_logic; CMP3 : out vl_logic; CMP4 : out vl_logic; CMP5 : out vl_logic; CMP6 : out vl_logic; CMP7 : out vl_logic; CMP8 : out vl_logic; CMP9 : out vl_logic; CMP10 : out vl_logic; CMP11 : out vl_logic; LVTTL0EN : in vl_logic; LVTTL1EN : in vl_logic; LVTTL2EN : in vl_logic; LVTTL3EN : in vl_logic; LVTTL4EN : in vl_logic; LVTTL5EN : in vl_logic; LVTTL6EN : in vl_logic; LVTTL7EN : in vl_logic; LVTTL8EN : in vl_logic; LVTTL9EN : in vl_logic; LVTTL10EN : in vl_logic; LVTTL11EN : in vl_logic; LVTTL0 : out vl_logic; LVTTL1 : out vl_logic; LVTTL2 : out vl_logic; LVTTL3 : out vl_logic; LVTTL4 : out vl_logic; LVTTL5 : out vl_logic; LVTTL6 : out vl_logic; LVTTL7 : out vl_logic; LVTTL8 : out vl_logic; LVTTL9 : out vl_logic; LVTTL10 : out vl_logic; LVTTL11 : out vl_logic; PUFABn : out vl_logic; VCC15GOOD : out vl_logic; VCC33GOOD : out vl_logic; FCLK : in vl_logic; MACCLKCCC : in vl_logic; RCOSC : in vl_logic; MACCLK : in vl_logic; PLLLOCK : in vl_logic; MSSRESETn : in vl_logic; GPI : in vl_logic_vector(31 downto 0); GPO : out vl_logic_vector(31 downto 0); GPOE : out vl_logic_vector(31 downto 0); SPI0DO : out vl_logic; SPI0DOE : out vl_logic; SPI0DI : in vl_logic; SPI0CLKI : in vl_logic; SPI0CLKO : out vl_logic; SPI0MODE : out vl_logic; SPI0SSI : in vl_logic; SPI0SSO : out vl_logic_vector(7 downto 0); UART0TXD : out vl_logic; UART0RXD : in vl_logic; I2C0SDAI : in vl_logic; I2C0SDAO : out vl_logic; I2C0SCLI : in vl_logic; I2C0SCLO : out vl_logic; SPI1DO : out vl_logic; SPI1DOE : out vl_logic; SPI1DI : in vl_logic; SPI1CLKI : in vl_logic; SPI1CLKO : out vl_logic; SPI1MODE : out vl_logic; SPI1SSI : in vl_logic; SPI1SSO : out vl_logic_vector(7 downto 0); UART1TXD : out vl_logic; UART1RXD : in vl_logic; I2C1SDAI : in vl_logic; I2C1SDAO : out vl_logic; I2C1SCLI : in vl_logic; I2C1SCLO : out vl_logic; MACTXD : out vl_logic_vector(1 downto 0); MACRXD : in vl_logic_vector(1 downto 0); MACTXEN : out vl_logic; MACCRSDV : in vl_logic; MACRXER : in vl_logic; MACMDI : in vl_logic; MACMDO : out vl_logic; MACMDEN : out vl_logic; MACMDC : out vl_logic; EMCCLK : out vl_logic; EMCCLKRTN : in vl_logic; EMCRDB : in vl_logic_vector(15 downto 0); EMCAB : out vl_logic_vector(25 downto 0); EMCWDB : out vl_logic_vector(15 downto 0); EMCRWn : out vl_logic; EMCCS0n : out vl_logic; EMCCS1n : out vl_logic; EMCOEN0n : out vl_logic; EMCOEN1n : out vl_logic; EMCBYTEN : out vl_logic_vector(1 downto 0); EMCDBOE : out vl_logic; ADC0 : in vl_logic; ADC1 : in vl_logic; ADC2 : in vl_logic; ADC3 : in vl_logic; ADC4 : in vl_logic; ADC5 : in vl_logic; ADC6 : in vl_logic; ADC7 : in vl_logic; ADC8 : in vl_logic; ADC9 : in vl_logic; ADC10 : in vl_logic; ADC11 : in vl_logic; SDD0 : out vl_logic; SDD1 : out vl_logic; SDD2 : out vl_logic; ABPS0 : in vl_logic; ABPS1 : in vl_logic; ABPS2 : in vl_logic; ABPS3 : in vl_logic; ABPS4 : in vl_logic; ABPS5 : in vl_logic; ABPS6 : in vl_logic; ABPS7 : in vl_logic; ABPS8 : in vl_logic; ABPS9 : in vl_logic; ABPS10 : in vl_logic; ABPS11 : in vl_logic; TM0 : in vl_logic; TM1 : in vl_logic; TM2 : in vl_logic; TM3 : in vl_logic; TM4 : in vl_logic; TM5 : in vl_logic; CM0 : in vl_logic; CM1 : in vl_logic; CM2 : in vl_logic; CM3 : in vl_logic; CM4 : in vl_logic; CM5 : in vl_logic; GNDTM0 : in vl_logic; GNDTM1 : in vl_logic; GNDTM2 : in vl_logic; VAREF0 : in vl_logic; VAREF1 : in vl_logic; VAREF2 : in vl_logic; VAREFOUT : out vl_logic; GNDVAREF : in vl_logic; PUn : in vl_logic ); end MSS_AHB;

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_3/blk_mem_gen_v8_2/hdl/blk_mem_output_block.vhd

11

17242

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block W9ikAzfkNAB9r6UjwYkkLbO7xSa6Pa5uk+WdU1HnuyZEhmVth9jtplxOjM44FNqSQvXccO8yxQi/ NOIWOqyRuQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block hEuem1/oUd4/OEXkW2OvYqIxpyUbHGfY7GOC6MYHG11DUK95IJjyjs7VGLCJVTSk7aMQu8m0Up8B V7A2i5Ur1C/MGpffEfJZxWT9TmFVFogk48CVrfRqfUf+EY/RnTok8AxbPM/CybW1sngqZ0CjEdAR WFwF2WmA9kANp7DyS9Y= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block YvMHbfeLoNrrdjK8MzZ3wyAsEds/aUUU1qihbPDmGwW2kx85UhHj3XK9rxLVtguq6gNEFC6HhSRq ElvLoh05rPkMnw6WFsbKYG4H4bGxyS47kd8q3QuXnE6sCz6iwiKIv3dpxTb7XlMwEgrVo5qwxGVL s9GGRvYTehzL7krjc0uS4aFXrE0IozDVS75JoLN8e6buKPj0LqKxI7eJDZG7nEfNSuwPJgV9jjsn hBN7sE/TpmRuBxik41OE9HAXgcn8nnK+V1lhlH0VRFNNoFpqAT/MO7xuOSQjqp+eRafuukS3cAC0 2Sj1JyG5X2zzvgGRtR4WAzC70VggYtvYSDr4fA== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block odYDbVugJa4zsNoidrU3zfx00EVw1f1F4ZM7PMiUD5vBKIyGujE3/2kpootoEODrHYYL5BLfkUxF BOQX5PSqpPgaDdiSWs2KCidYq7PHZN3L6Rfg3lupSDrgIHrKR+n/0uxrr/QGDaV+/KOkCbB4EmF3 NyOLBbCEbB/cyic67Z4= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block eIzvt2wVqO3FcBIgfe/d1GrO8xAJyZ1wgW6um6UoZcItt2tjAa8e4PowdMaz78drHioWBIt7t7sB imWtFcP0XMZDfFZ2wKw3JJinSToIdJDnmZ+SigbxdzjvPvdZmXqc/soqccpjzaBwx0DzDM+jpCRD sdcRaQP44+rEYmGdQzUtkX5LMZ/ySPHZt7L2ejRcX1NR7tjsbb6iftGBFtOOKIolJXES4o+D0lFM w4plD0zfXEeIpYzOx/B+7FZQ8lYPkEeG3Q4nhVL4OPIVDrnnmCTdbedEddsMjHf/oddTYPxyD/Ra iW41N9W4EeySOPEdcOEovPgHrZ+ZDykNGAE4tg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 11024) `protect data_block wCi1EGWEcepbgW5uOEPN0evgYS9XZMSzJsF/EcLsBFhCvSD1oOzqmP8fJeDLmEdNQF/7YfTTGwOG s/wOi78uIdGAW8EknbP1v8GZ5t6AckJ+EAbHX2Fw5Pv9eiMTrctGH8sk1YlZDCuPnfV55Q2O0zud +0ZgXnZlrc7F/yyZf/0sL5RdhKarwiOYPkVaXJQy9vCiCznzitdbynS2yKkF1aLC3vIZhryEd2L6 6bsXkgm7ee4SOk169T8++p+1X37L+DO43l3b6H/OI1+62kC4OMfxcvL1jRl+vSBIkdl3HUEXQrCw BmWHZcuGnpe/iwZc1V6oVxIxWi4cGY3ejnO6+VJ5a4rzjl4OlufiZr9qpgclLk1fxBa6TbGihHi9 RDMs4KeyGEvpcjzh6tGhCG/gvV3VK3M7wp9uT7YEPNHxQO3EM7PlrsX/DYSZ9PzM4RJjzCocSe/3 XiNKaR345NJXRC+Wex8XcPYAGljr9J9w5GUwlC2iu4yMn3fsLiDyiN15qNEGr0Tl4Xth4CG1sfYc glnF3CpxdEWH4FnY86Et46HYGX+ezVvSVjzWPfQII4x4TuqPCdxM4hq53UY9L8QnDPjkJidKkAYJ A9SVIQVaSdUJb/fJsTc5rdQBFybAaNUc3RWW//Q/aegz6j9UZTB4EY+Fq0UzFmtB/D263K+5m5R2 k1jVDCHI37Mw5Q3mIzezR7HEVX5NJGQP30WUpwf5n0QmslBWheGmAaBdXi1VQAj2oDgSvzK4Roj1 oqpd3mMkX30De+pToc2HoY/rZUV73JMlIMw0KCIskkPCTA7ip+VF1+MO5EsiF0xIZ8p/FkZhkGPo Gi5RbLu1rEg2F05pIat444Nyyr3Pej93fE8aJc67F+/NYr9AVk21O3C5g7oFX+l2Nce1AuajhKwK 0zB93kklzSo7mCDRBC8q7PEMADV7fFxZucBy3aK8WU++rS6aGKvHQYo+2p75y3i4EMMBkH1Rcqoz CBDgAyuUqGwrEfY65q2fL/2jRGPjSuml/rXDYuZlu0e8j0ReNOjghdJSehSVOXHCyHM/xw1qBYIo uu0QnGqCpTsM4q4RdHu9HlYeb7yCMqSkjYeM1+X3xYu8J8+p5KKY2mUE4eWgHtP8CE1KaM/Tb0Ow M2P2+liiXliBjWMtM85usfHCJ7fmmm1r3P8jk9iuggYxmEjXFC63ULsDz6owyUT1VfVXpAIp9/ZJ u7uajzC8LEbqWkwqWgryamL21YBZNwlyNfVdbSiclHupKmo3pNGFhYwOmYlqS352zcow2F7u9+xi hUqZH7C4inw9SAFF63DmJqxhVE1mQjcWzRkw85tY1KWM6B7udsNpoKEM1WTqI7qQ+53iDoEu5xYX 4TWSLv2MSWK+djqLm37+GWvOwVSDkIkJhLGlxOienriYDND0QfWDwNcyTjeD15JdJMZTVEYtmU8y IQISw1STkXPechQz3a1Rh5jWVUyLi0HTzdHo52FenD9MVRpYD0qxoBH+H2Sj536fFfKbTI2ikQPG z8jiimt1UA4pRXwRZ2SdUFdLHp++REwX+6F3gnZbDjjJfhP1j1akVyqDtJiJOsDEaC1xx6PwaQWV 1lFxpoiRpTgQGBwDj4H6zqpUJELMM9xoQdNcVawIlV8H4xSQNp0KFquOdMjw7gk43HAvEoV52Ucx T8G0SOKKXyQmn+d6RoF4TZiPzLsGLI9JQ3fDOnU+ONTmPwIa97TF2/1jt5rEC3BoZlZl5J3iLjym +HwPiDdyxWmDVN8eh8YTbIUbx23sWRkXdO2OxFnLn7wNQKPAtPw2rVHbDty/enJJ05RyJrrLrsDT cucwoxxeBYKjwEAfjRZqkCDGUioTv3uC9+7XJvxjI1GNCyFTtLwCCL5ERtiC25hSec/rtw4U1PyC LFRTHU5FERCf0Uha12OzrTndcISwL0Q9nb5McAttt44W9asyyeSQXJmtjxx8vZhBBv3KDFEJVZYd NLNr3+KqXxd5e5EsUXiXu6JDrjgmjVcg4CY0fyKZ6AzWLIO23g+fLrmTjEjkaqg93g2rcxdibiC2 waVnqlSwtmaBJdGxdDlVJpgmHKE62H9wO9fM9/uDkEfQQtfIlXIA+9k8PDVKueAwexRIhgb3mIFN uptop6MXrrb4kSu4iuxMzbCT6fl+/NgFz1AXVItp8SH1h/Trer8XpdiXcvO778r+66DugCLXYS/s OIRR25AD48R1w2GP0649sZpXLfBz7F0HqCLmdgVn8gMNQ5eKsWdXOnpcQIiP6hX/l1FOLdMdceNP gaatnO4SVC+162i9QswQXO7OlN+epuzGKmPSiTLYygv85pACrYF/KnSZm/x2tlWh+wVZkReOksgQ 2N+D0z0RXeDWwtyHcsOM61s5kuGRbNgEf8K1bhCo2G9Gfv31XQMTLNupQOTuFm3oVLClNt5WhDm/ mrV8YpxXM9JhQP8wV2zVAO45sV6/pqZGkqOOB4nSI4nsbD2ISQn2325dzZ25uZMmUGVvlbQ19cAz LLV+EzYlV9c8Br9KeG8BGUrxR8dFCunXrnTGyVRQeszGYBJaBtJm69UpBBxF3Jh5mGvmr0n0sJFo F7Mgz5IglCO4mIUfOPRMsWmb8JPB6yUX9MaCvjILyawpazflhCDi8aAjE07GCW7VaERKnY1hAVIA Re6UzqWdTIOWz8miNNWoJWor/+ScvfzOwPaGhPVALiP4pZVERb7JIDgUDeR/6EBJ6grJjM8Bu3Ll 9m7bsjxFoSJfwkkrkjkgjKlOL3fl1/FLFoL+aPfk9H87k9cQ6Bv9RFUGNLF/taOw+n8UT90Zlh3a /HmP4OyxGohsCGcc9FDhLDhdwKVIg4otoyF8/ZE0B6O8DE4K+o+CKG6MC8GPyEbnCgcQ8P21P/b1 wvydvR1ISUCwoSZmkgDtXFfnaL3UPnWHm/xsOWX+/MJLNsoXslawTgVjT25e8J8Yyflj5vyKiHNI 5lpNEPTvrBzidpYSoQ9+v62kKOyKwT9V00ne8rXZxXK5/Ei9h0wc0DJAzRVX5C9/CL53uulh/Xvu Q8yU76t3lpZGujaqWf3XCHi+TEqjxkrVubny3pUuBw9GoclaqlYCeV8OAdkce7C535FnNXlfZfn6 vqF1Kbti+iAFI2TGU8NDv1O1+2ns05P9++TRXeyKJUYBVnhUswAg5xZ6nkar8fcORx98ziNa6fwZ 1uuPktpyjrXFSq64UbVTERIA6TwHImc3el1+hKsFQRS+nWfZDvKLqngq31yEjkFttrJBfI+hCaDl JnQNOpuFklfg4bYw5L3P46b97uKq9uNmAHy0ezNU9BSoVI4xvVG8thF+tC/UnN353/LZ/u/2nr7T VFX4x9doWaEtMnpADsz6lxQZNSKjh2DEIA4GztQ9ix6GamPsINzITUnvzGBzpScLm5VseBy2PMQi SSDhcsdX2aymtT8K0SOkIIT0ImnjqK6nuq4qx89cCQqIIXMlmESMbhcJjA+iinWl9iy1f8uF2Z7l dVk3fVcJtcPlnVjOCYj2Rc9cspPF9v+Nt7csYxadnwcAkr2LHGzme4309qjdh4Af847tlVAbuid8 CYV4eMBbTaBkI6WpVeU0vBd53e4j2L4e/i2AwhY/o9BdtONqeLM8QjbYOGN8H+Hhuj3Qm+8Qs9EX emAmIvxoh8nFtlOxwCOVtRNuj7sMWjAZdt3x6+MLm6NOas7DYqopXWOrpT2oOtZvHQ5p/GuEgDSe 6Uw6Jju9Zq3Q7WrP+++YfW/Rg4F+M2f8EPRLBPXQ3ofmID2MNsBOrOTPT9lP0P6/LO0/lVfnTRnf UODpU4GJtAqQ0Zb5Ckwa/7idPRN716prGurD8uY8lxZuoKcXPZ4sRnt21SGZvXSZAneSnLHkrFfP Q2XwfJI/ilsUgxf7cwQF3IJq/xpvVUzYguPYt9UHGukSNgxiECvXWdWxVJS/UHX0s+RPz8Cxrrxm 6GUQQZ2VHelxubUgbVemoZVBSr/50f+GDFmYocgabwl3XFQna4WZVtmx0j2Djr0ZMvlghtlFCDbH 26xgqSUWD0lF4rs2yDcfpJMuK7p6NBC8yTqo7PJ+wi4JaypSPQrUv8AsuqYO2mS2BD5wN3gM55MR uJGpM5PoRnNDYCe5okDEzh+vfVBtd1vmewSCfzqbtKrQvw0AN/2b3iSF2wKsd6elS/JBbvDJeXR0 vcaLurJt73FtjHzMvDVWwBjs2XZVAkRy2g/6ax3EJel+aSsxrCLdVwUg//cF+dNP8O57BZ4taE7y LClTQL0stTDosvi8b4DMpWvMEU/y+/EAf7Gooh55Bth3hcWzU+Z++HciBWGJVnZA3w041qkK7F7k nrcpXABgxCSW05l0Am2jQOHdm9gqrsG0jOHBSWvpIeQZ/6cgotjsCH2T6a0cAFG+D0FyJ1h3pY/w QEc4gvHNhj1vUxt4LHVcEXZ7d9PUdjLY80iZNaT6XAq2OvwGoBkGZ0EIA+jaTFbMwc5M++i5MHxw AtbcGVZ/DvSV2A6ZfjMB0BJ910HgMsHkFPk8gpx09xssqKyoickNmqbOTRzKkApmOtpCKkV4XYxL OjvRP7hQIcHhmu9808MLz4C7gYfHiMl79EhttiWyB3PrPvxavHXmfa1dnEJLVOIGncRBk50GIIGg HrO+kb3YjNpx46IT2NY+/VCTXNJ3mBRkkUGyUMD/LxnONccqZ/D0+eVoVT4wL+cmeCsUTMt3HbLI yLAGCdPejK16Jw9Q1FR4JhYK8pgHUvJyHi8zEkKe1g2ajfMWGBgTLk1I6uuSvnXJLLxbddK2gJfK JDMgtlc8E+h4laKrZA2jBiTH2mweBeZNzsaBtO95Vg8jqXNI4BgwovJzk4O3Zcg0UYiuyq9E+iCM 8MVkTxPuWYPh8tuVMSY3TrwQmGJt50A7CjAKalLx44K8UN3L4zZtpzNJRuOuKU5dg1ssAUaCiVjj zhtIhRJh8MphYXXxi35HSuWRlQ12KRrpsXefBadtqgrfoNpmBtFxwZR8vrBc1uaS9NwPWnbBk63M daE2DGX07+agz5imV+o3DM60yc2/40St3Fp0EuGGYBF/RiHJyhRfENOrQf1Zlk5xNCqyhR+RmXOF EDdWJYA5+eLQICqMCN/ZK+ImITU4xnsdpr2lLhCS1q9I4ivLjGy6VY/8CoVwpScON+33WdsOHqU+ HiQl4sAd2n05aFi/kCKfnGBY9Dwo7+MuVH3/A3SwyPcIYHMEdAngKYbdq7+OETPEAvPnukxPeQo8 WvjZsG+kvu1ngllQBwYYjnEAF5HhiZP0MnadKUS6o0C2t13rOEPB0qaBsYB9ELEcy+KRWX0Y4k0Y CKch2/HMoaSNrgolSVp9Uj78ko+cpf2hO/7Ap4CedHfgv/qo9TNjNBbBicnW6pqgvMZgLmEjzBGg J7WOrMNNDvIrA8gBP3FHAbAXOr8Gs699EQPkQCi4+1P+j3tvsZ7z3gBCyUPHXvkD+StxtnA3BZq5 dlA0EKVU5E3QNPqHTqDFiJgnrGKz1uvgOp/MLkPwbAnfv+k+Cb3P+4Blg0qHdKaLX1okmpODaSa8 JvKQoLJbgl8gGklvGrlORf+OAdO6wEs0mA681HnRhFvkzHCB8CtpZnMkj+XtBexkeEUYZHvOh3pL yOfBF1a6qizc/RNu2+FannoWoR96t1fPF8eklFf+cedAWEfaPK3nWGej8ukaMXjIKbg9fVT6KyDf wLQrQL4LdRFWB6Y/9kBiMxDuWdP0gE397ePL+HOLP6bsGjqN9zWsntcqkBRmqO2CMVVGS3Y8148S gU4iPECb6FwXbwc3yjcu4DxPuJ6YETrlybH/nb+kZsFNms0XKO6ND2xTUixnwzyr1N3vv6F0CWe1 1UacUML6Dk2ndWa+E3zqOBVwFSpRIHGZwb9syoT9PMvJXmNM11cc6WEzzhZpbQJB8SW4rNqe4f0L n1fRwmvHyQefdv1eZKvQr0EL2i4CEGAdh+8pKR5QgI04d57PCoJQJjvXiR2JfYNd89BWMtGK6zd2 +UWaNp9uXCurzNVgXb7Q5XctS1Bl7fqnhGkifP9GBi0sOaLzlYrOWUreezuC/Wm/i80zm3HIxrbh CphcYYEUwf+scO/1cCTYZWeOt64nPlNZC/I+ONWyG1/iUfpT4pLH6NLZysqRDlZRDML3VUQNUxDr XOujCaTRinuglfapVDRf7ZVegPTnWssuG+QXNuur50QuDW3K6WkBWx7bDiKH2h9rvNc7ktkERk38 heGQygaO0qeo+uB4twoVBNfyNKfO2Nd5pwVIaLKHxTmNNb3NvaJZ3dctvoC4viNP4WaaK4Q2cmTD aym+cyLi3OUq7Pd3kQQPWaxZXbAIojzcBRS0HAryuzXScnsbL9493fqEe7di3jS+qWizMjlx9aGD 3+8RQEb50X34FqOjMHFadbS0Smz9vqgi88BXX1tA1m0cBYYdZ97ZIBEj06txiK+MTHDQdxhxNWAg 3orony6RMm+lKifnHDZZWReSVW4x4aHjASJMMCSVAmk6sjjmrzAdL/QO7Bx9+UgElmvLlpmMZPpD m0X1c7KJJ7VqDsT5QmKXCnwd5X8BDxE2155esUsxOsx8q+rDw0MzXZwCf1U2Jb6Dw8xEbwOZ40jz ttetB2fjsJIbDrJZe4ZwWhtTPwIFI5A4w21PmugJtsBDNw6M73CEoy4+PgYYxT+VLBuzc0VSG+gN qYJ4lwrkBzxFmgU5kYhvkkLV5o7UXPHq+Dn2BwVK6J3Kbd2pGu8Dzhc4Cpit5kDLuwWfA3gt4TGD rykl0ClqIG0HYJZynx8FUtv5DfHrwLhaJZ33418ifEQqrJuGR27CkXR5v3zsElLqcpM6y5jglrxN JP4k1npi+7jM6E0i8wEU71eOm95QD6BUd4aZij7R7vjD/02R9l/7L3j/HHpgjPFi78CfpwLhfuyB H5OPlCC1tPAbtWVsNtcXN8Ab0HWNuPsPIiDtLwvIe5F0SzXnX1tjbXzJuKUOZwPqTeCJJWOELJdk wdvUfjCTcB1FcGoLeUfdmuIFE+RKyS7zbt2FqcRIUzgzRzB2bDZ/uL8A1diLwS/IRfEo07STqm5v NFdVn/tcWfWws8udUK+rDuF8r60p+oeUEoj7LsrOpT0dIkIISxjGpuPjh4Pr4RfDnFyIsGK6o1YG GGI7bo0D486P0n1B+zNqE/Y0t54PzRLzgNeDYmLPRSoXWQsVMNkuHQRQrlCEYY5y/FwoHy4yc+/o T/mBxinOwAM+S8jDUnG18R9HmgohJk5o+s8+L5v3GxxKkSkpXFZAmUrVEOfoqnKMwxsiwsiyDE4z ogdndONAvMG7y2pWm/kdTpLY+tYkdoatms8zlAZMPX2N8wWD/GhYzIwd27BaEdmeeFDhzY7bB/I5 LTo5U9yM3sYxUOCqSuUf/VG7yiNIvmRVehgNk/s1G1ewwZCEr8gi9gOLTePLF9aQUhNMJS+VU6AW qrh6xlsbGVUYk2oHtGWBlw40/Wqe1okdkZUKvlMxUUMxkHBMCphMyuCjhF3uwRkdH3nD0cKJI6cd MzAADauO/m9767UuQvlgltNUk9HJbpvnt/67xQA5vu67/GTyZGu60uToCuEMImMsBzZaiUo1NGIS vdpfVnGfM0nAe0EM+kGVQSdP1QLgkqCW/5UYzPtibyMA+A0KAr3T8dEHBnkO1JMntrE8arM8VP6P M9klHAIXIb4Pnzt5IunE5leV7dy6WPepP+F9uyv4O2oPDA1PTL6BWj61uKlUg0xPO8KCtWEW2lAT IRLjFdJJvXslKd84Tne5jvwRQAQMg2WocmHiwk7TYyWihN0odqKNtmSdqYcauD2QDzTT3ihBnBjJ 6ltHjrCfFwe5NeWOnqUMypMPtZXxjH17d1nIPpdm+zqa79/nSB95FS4FG9vAprWvmwr5X8RcJojD 5vkOmoQtpYaKgWYJz28RekldLSfNPb4H8mYjUxOmizCSgbfo45l+6b/hTwFCCgPG1W89qgOhlrYf HECCi9tEPk5XYM/WHVBty3A8vxcms7TF4e5f5u0rxRnM8JnwYuosVCmJpfjo7myfsexQkF/BhyLx ewQbT1k0UWHWV3B6a7yO8G+DLz+kOt71BICmvR3AeQFVwyaX4ldNbsaJeUZu4jOkyx7IpDFpSLa7 z90EvaHOShqu4nlPI95Ke8kgKOaQ3GukwILrFwz4w+0NvWcGNFH37ozx3QxCsQlKpdgt+Ib0iBBg h7iL7B5oYOeHm1Lc0fKIspVm0GvHXamYCK1xaqQKpuC1qd/sHrc33ACYzcDxNDeaVS89wgDfh2vc 3R3sO4PsurtD8zXuIUcptEfgUpJnUTRWgKmD0P7H8pg5PPHlvoq0B0xXOZj2lhAvr0pSwputKXLb Wv4M8F/+aWXf7HL7bonuqT2EHCOe+qWEOdGOr6e7YYOkUULd+c54YnAtaPBkI5pWIWSzy5U3b9nJ /p8+zVgoXXBkUo36PMqQjoppaKHP8xGwMY9IjndFt4XtXwpbAHxExUQCyLRRcvPDJnswjxNGD8Cx c3kJa74PjFdAzbejqNdOFviT/EFkwyO1pLxLs5BoK6dRgiqQbc1ZphImlMG5wiB3DU1d2QQSTMn3 fVkF2YXM4/i9WO7bFT+jDzCPPD2INmiF2wjzr2d1cOGoKU/ROPAxk6ZFyhCJ74czt/CIdy9oUWPm ZIALnrzH/+RdOMKIk7NO1XHj2xU855YLuPUBu7GJgfdCNsSdKuCQgWaeUINi2YLbiXtRKZqSkKB9 o7h463WBwWTKeX2hiYlr0c1BnMW6kgqSbEFx75kLUaTUMm2+UI/+lw+1x2BHBP9TB+jvx112YtyW udDOW7g/7aAlDYIyYZQAqYZUWI2n5SKHrZH+aMUz6oz0jy7yTczjEHocXFu9s1uzEu9/awHX4161 qlL97LWPVkGWhLx2cTevjlDrpoukUEBE+RHXXfm+XP9jkd0QA3+1rUoGGoabbWpmhkUl1yeDWm/2 iUa4y9s931hkHMfw7/DeqyX+H0WjGthxkHOvBLEIuv1bd02/1vXlZcKAtgK+yApXUvn/XqqWEZI1 jGzM9Rugp+rMb4Vca042m2SrTg+k0ip+8NbQGbHFK98uEjPBb2NqWw30qxEIvxYlcirlImi8osGq QKigQVTuoiJz1z4MS9C6nZmj+6bWZUuzZm8b44kJMuyF3YFgXjWRE2VjYUGSWDb4Zlr6830oflJb FvmFbe3ZPaJiXqTQETeXuI6fSSkDZpTw+XJbdMLOD62UHG06clgTHF9NZwR4yyHPB0jWQ5TLPDjf I57V8jTs0lYVDnHL34BguNJJXtkU1a48C5BbuOlwheBO6Ir5E1Jo7HEaShY0wA77rMAgWqg9MV1k doND6yGLaoudGXQll9HmIROFWe4NG//FKhdqGOqv20sm5/Gts9vhjdulxNfOw9mepUUamVYl7olU XpwPjoWjBx7zYiOTrirUqH96iTccpCIb7ickww6IbM6QQjOgbX3Rz5sTqTa9xAVx/IPxBAS7FXOq GuSPD4sXIjXpZIQ98cQLdQnnrGGl/lltEa5B6B1wjrf4JHb+07V+K0kX4qf1rzMaxcY3QIuc+V7B XV4GrgBD/97DWOFOV22elPnURolVFxUr7AV1QVdcAwklf9h9Br4gHxQ9Wf0u05AfKT6EQMpkJwwa P47sjB5PWc4/NWzuMxyFv5X3mGnugwrpGt7nbD59Nbv0r2P2FENy8zjXXZ80KMK87YKyn3LXPmb2 q6dOWAgaWrEZrFR50Qev5aS5Pnf36DgKNvU5E+J0/BwjjShVU8XwgAI9G4Ur3/GRez0Pe8izzQG6 xQV5+nn5WgdnvnxJvKyYvUfcqtqXLv/OZ+EK0dmadT0eKPoCPyQUzywwlI7FNjn319Di4YIcdxXq K7q2IdPuXb76sT2MjAEJArApz1hGIYIYkVwPxAFrwzMCDbyl8EIuG3oIeUqyDjPZTK6+kLxt47ba 8G2R0/udH+CHwRW8JZ7ap15J0LCVLVa/n+gamRuaNCO86/BAObtCNuixubfs8vQImjkefo1SMY5Q B6fB0iVbcdbxEc0bQ72a9RKFnMJzkICcdiNv4Qpty8ShgBcTGEkvuMLDARtmOjBRIoMuKwcPYmLn JvsfGm5Re5EAAJYFC3FviXp+6ps4bdWu2t2NyvWXZ1ajaV4uwXLe9lgSgyTY+MKDY3US3b6+8HM0 BVkvIpSkeaDwua4C9nlm7JoOIEoDL2Ll3V+ABi0ki3BPa3Ye+s0iXZVbMgLPhBrDgQwdTeNWY2iZ 9kydxvCQpPagovce5+KpCINv1RaYyWqzep7grGyfVccfitrc3vC6NPpJnPuLwfudK/4+OM6/J+PG rXkhzDxVq9/NmqvRCR3Bh8Tv3BmxiZmLJKlvADm86eI7sYs0QF0Cq+PG7SI221Z8aWx08vo0RYLJ 5Shm1keaQFbDw+1jS+1Bvamj+L4K407vmquZwMfK2dM0zQrkgCWq4Yfed0lurnkb7mej17T46+vO uSI9luoSWTWZCYymqz+hKcEzOrIQS5yvn9HrXXbveQhUxyROqHtxRpJqnbl0wZ3DJgVYmbXCSS7W k7lDnduuW4kyvzKoL+6/UNTRED/rVGJnqwBB+NMCg1wJTdZ2Xi3GIVucxZRx2hzWZXkQ1YF6TxA9 lymDZjAh9psFClQxxpWOmfL0F7e5viWzjSKFim+aRUwdaPWHIdYSbBSkv4faJEbmC2QToilLjNkM +icgBYlr34gshG/BhzLW00QTvhA+UdvLMRC24SPGPVsokbrMVSWSAM60gjljTdBUFbJDm50wkm6s HMg6t4IHvdsXH8TvyInwyZ8JN2aVyOwab5jx7Byf0mjgQx6ZzKlo4XDCffHTWiSfOhYc58C7e6JK QHxD/QAJGit0pCrdy6LA00ZynR6tfTiUpd2x0OcXYIg82ChjvQ2TbtxSFx8EAd+/yPwnn83fJd5W fvZp8MWz098AMUWTUPo4helY+FA9tYpczfEgTIqCs4ptE+WE4gA/rneEEPwqkoOgWzgMYO43F6lf f4TD4M0AK5uWR/lxD89GTjQYnHILNoG9ci4E1kQsxVtXyGZlIr12gSpdDKWXexuJ42YPaqddbyNi ymODEWI6bxyQCAAsF83994oadmIyxeAg2RjqXpN37mhroY6FHN8SkLIS9FOTZl8VTSgv1fp9vjiA Jx/h0b303s7xNZ7hHMwwOgMwGYxYTHJzxnbAMf8GTXtcirnBEHvH+HGawnsC6quCcVpapJBSwH3Q 1SSFJThAkI5R+eLRK0nstV/nzKLcAqFlH3XujpVZ8+jNTBqlK4GxBRFLt4Aw7S4V7F+6ujg+dZ53 SCMMt2KA1AMK0CRiv/G3phXD0atibwKb0wSjaHVnfGa3idHdIxGI1Fog981FdLEcTBer1rs4zymB Z14gb7YkIFI8aYUBz7CtECXwOcBw+jABdqGmQuMPoNJnGkXV431I14MZRJpuqfcD0b5jbHkp14DN wzbom/0YYjAJPzAwXr/58oQWpPCczxq8ZC09sztQw00hmgMErYIEysWFjpNTqCMRLjuY9tmrceWM PJa/qWDr6yCSOduTZ/gEenngtXm2orzroHdOPGKKzHz490U36HVEKNr3Pt/XQU6AUVvQ3GLs88y5 cTDrZ4SgmiNf0UfEQDYFzwG3wHL4p8Tnl2nmuxrAVRQ0nNSst+3ydz19l/QN7x/fZmoC4YLyB6J4 ndKKDCgwb94G1LR6PCLZYh9olBov2fv3h8H2rtQMBZdBVLPMj6E2a2KHr9NahH/amAQNL/ZBgUqI z7K2myNcHxZ8ABBf9yKc0c/Shb+xrhI+ysMFLE/3qOKFc9qrMOylDYZcvaq5z07Fgl+9WpHpNnGB D49l2Un42iL4EeofMpBuYYEZ7/++bYP6o96ldaxcehGkbb1F+NtMXwVQW/XgYVqFY9J2SF5BujnE g6SuA26MsVpksJuD7vbxOzPtjPicuw1Fm+DD6IL+Bq90tgfrTAZMQW1IxCqcGKH4nSyqVHhKpTjs Ron4T9adljJYR7DsFNH6bjXm3ePk/snq7/D4WcWVkmY6Zsb88h5jZOV4Mp/QRnx2zaO0BoXebgAs HBCw/RqcD65HY8+/uGOqtudNS/tYd6hr/8llyel3dTB/xv5T3PXKIP2IuPLs33xKkJHRN7F4aJs4 Qt/dWv3iRG9cqvX8NyZMArBxAnDbD2ywVTGk6ZwRbzb4riv5frsaSnuO2Cbajiw7677Bxup0pd5V 5Io5QoTAkmIOd5uJ5FbziKKo+bghTpBE+4RXrq46GIC7iEVtAqEaursEsfNIWu0XecFEyHurmnwA T2z3iSMqF2WT00US5fdoE7oBAfCaCEJZqF3M2ywIvWHf3Bw1Ce3H8CZVdIKERaP/zWu+VN8a+D5A S/MfehnY3jfnvS+G2WA2jSHVyeWwjTxo7nCfQWPIbJDucHdJySiyiYQh1+15NhEwi5mRVR+bJ6Y4 eX2ndPdswspVL5y0+H0RsXZkoXmLodbG1mI7b/BL3DdEWg45Kp68QF3yuGw6iwvd1Q2fWce8/+IJ p7473UwrOkEvRWzP6aVC76E/hpJobCuXIASIlPfJIOoIt4R6WwCXNB4ZIIN3N5a5go5YfAANWYky tU5jxCxLyR/J0nF1eG47Krp0cTZ8Xnazpr3n/wbq1Y8hNUuGcdsel1RWleITOy0OWtQVctghqftx 0PFzNp/Vidh+/YHwUYA49cPon79VEjLEfQLS7lTt/jBDESAWnwEaLaK2TzQlknPHK/NiGqQRAVrU v13x33eL4ep0ZLtfQPNipieZ8qNnn3xmBt/+t1i4eVPhqKwTkw9rrU5pI1Q5Gsrz4ruaUvZq8A+f QpLBhoMnB3blMpzxQeqakg8X4WV5XQXT+KjqPEvyIovYcBNg1f970NRiJo7+AB/uMUpi0o0qlSOU Gz4cjwe4WEQ1YVgKDFpZlJimkuroij6Tm+avlzoxDqD3m/gpEhGbfyEddFfDBM5iCJ/3fF2i9BHw PX1ZIibfjGwFDbv62/FZjHBJuyQdEObKiWzY83GOOWy0chAqSfLf0NG0dmaHmKU08Fxf+TetX4O4 /AfLBiALQVWsyDm5ME01cmG/F0wGoIMJh3v8p2FyFLcxbuR/2wKD1Ki0fpHV54xw9yXhwDc1pwve T7mmWQ2uoqmVnCtn0WKsMu2dT2D4ShX4wzxEyg5y1mUQ/jbhUQ8tqpTp0YLW4RBu3pmSG82IpK4E lBrX2yZMFLy+5P1DC/hFvzS4qVLgXxVrqebDA/D3/oLt5nZ/Y4+Y0OtS8TlhFeVHlJyPSpAfbR7u wpPu/uMxl4BhF9CxwSlRsz1Zj3R7CfUvrbKqbnvIx6jRf/VUgEj0jHTKl5c7nZAWCmsQNoqU18V0 lE0hmaqSchE6dfhFV3OEDisMmT2UD3byoy76CavG5LbMjQyfpqFA/zcvCH4jogR3UybCKtXGd3zu JWjOAyCZ2EsISs9uVxqi6H9W4iZhnJS94o4+FkwUt9wtP5H4McFninSONxAz/P+H9EKIqt54ddce W3NxZ2g741cfWMXrTxT96NHVzuPqaCx8o0k5ACUiJEktWcaY3zgySVJYl78EC7UYbUAc6ugBCVdy k1+bImun3EC0iSvy7QJMo2iR0fJTdSNwWoCIlPXyChMZjazGrGdNYs+RBRoScNr1si7zsNNiyowh pTjVDUCHnaR+D0EpynL4gGGQVKovn8zRm5JcVMpJl+9/dNph0Cxr1ESdMpmk2FKrZKRdVYGj6fQ2 nG52LBZWAG2owBc16RlTG4naILE5Tbo6omsQ6u6xuT8nEqlvJctkzNiwbWOAiayZIMKWTFHr123Q hzzevdPgq+PLETWVpuqWVwABs2Zry5Cn8/1bY1ycLn979JIAWPZ+CWFYFNlN25pN+EsX/RHG6R5S KJiTZkoSVqcMgA0DpqLox75PBFPyJ7i1cvjK8YtTujok8e4VVhXsI/lNXWMTC/UbijxZwtH267Ce I4fMGbQQIMESXMd6WE9C3YnZ5MH6x2UpDFIkzWsQJQA7KZolxExV1s5ks4RNysoYkXVDzvo/mCmX k4oR9apqKxMCecmDlaBiNOoZiwzn5hqEyIJKPLKsH9nSDyj+JnoZMyQQvyMZlh+vPrf8rCFqY6hi RkbrD+u1Mq9vMeE7pidNai1Srz9yGef2OGgIq/L53Utc6vbDnICqYFW5f1xEB75dcUvzqG4rdo+T 5CggBverDRcHd0mfv6/cuCDA50UKoXchT7um7hrHO8Bpg+5LcmfN/Ih2pHLF3ljBEhcB0vXfOlcK Iy4D241vvk6g27GzhLpE8ygbJd5gdgAf46O7SwseHXBhsP9j8KWZt5BXtsTED+LI3kePgYlW+5RF uE2dDRAmi02Ick7uqMtVEvW0iPsXfaZBD4uIyTkVxJEl4PuvxkRMzxk9UpXqxzBED4LKQu9Xx0mO TDZWT/WXqCembv4/MjB+VKBed6NZzUIVa5hoa/RHKhjwueQLtiOCFeBXMECrtjcv66lhe7vfb9z6 +5/p/1CVftcsyrdAPnK0cRwNJDf1EAaYh7BPwK6H30ueXZtm0tsVo7VdSz/sYtSzIdG72vXqeyCt kntpF3Ak8hJmnt883z/0Lav6YRbzEKfW90EuPMm4AiewTM/zdWNHdUN23cJOcLrF77qEGEYDe8Sb Ridq1vEgTVRnwCYMu4+7sDFYg6jXRfk= `protect end_protected

mit

PhilippMundhenk/AutomotiveEthernetSwitch

aes_zc702/aes_xc702.srcs/sources_1/ip/fifo_generator_1/fifo_generator_v12_0/hdl/common/rd_pe_ss.vhd

5

46465

`protect begin_protected `protect version = 1 `protect encrypt_agent = "XILINX" `protect encrypt_agent_info = "Xilinx Encryption Tool 2014" `protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64) `protect key_block p9mk9oDYGr8pmZkWXbY2TLDcNbG5E8gje77Jb79LHblLzT6z9srp4YogxjZP3AdpB91kWPxyMOW6 yZ8yldjKJQ== `protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block mVXEkppMj6g1IXjCy7VbBKs+xRMg53vy4CptQMu5kxBNHV1PdY2Z6vTMCczc46movp6tA+re7V/F HsTTtWCV8ZPfOv3mcdhM4UeGfFJKyzETnvTW+7FBhhQEC7rVDuHV/zQIpFu2woT92yIODVDJv0OJ d7TknpWbiizNGWwk/hI= `protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block kaEPvPGfpEJgQQGZTZXbF/2CvE4Ypzvh7RT2RT4lopARsSjuV2b5tLmuzYSb85Q5AFDGlfRWDwtx F2YZzMpA5KuWPN8p6nQWyhLNm/SzroKHii7qBz7lYa3mPULaNNzH3dQ4LQE55pFWYPOfv3yGdzz+ x0MEF1ydRO95dewin0KqN+iIoWFhfzxKJvwhtWiiI/X05UUfC8+LXpcJqGLxKw605Jlb+NeKbbhq fYieug+3ebVwrZawhJ1LjKOdIJ8rUBrE5RUDvZKfy1WLh7meweDSbRCQB5rPDK3OcggQilKZ2mNq 8WI66wOyhQxGZBLF65BiKY2T7DqYxJCp5hGwRQ== `protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128) `protect key_block CVvJhNJw6EHSDIQ731Kbkfkwh9Wl9VKmiOV38T/SVAU+kI3c+cxqP00ao5AoKfnBVtld7H9d2J6J kXhNjYdDnAvSRM/7oTsMkgQ3b7EgkwQVLR7bm4uQPlxcIXIdQ0tZoHzgZNTJUL7DL73vJLbed2E/ KzI+61P+AYGjXhbYkqY= `protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256) `protect key_block ga5Bitt3CebGZAmuyISY0yRlSG9x1Tj+suj5BLHTSTSYidEbK8uW4qCTr6BxF0yV4Xp11LL0s44p pTF4j1DpdFDEchCdBhPTnweZZpfsgl1tF2onzxM6huOLdb8WUzx98iaDFlYXkwOae5tqfbg/QqYr LyzTmB6gN+UHIqqd0Nvja/wQ+C8qsyVXUotU7XSAyQnl09HX5VboIooc80WNwl7i2epmVdrXOo1U vnq8TH8TcTYxW0QC7SWveJRCbce/nT+MzP+z7RYjxYN8q+AXvkoPoJzcA3kTVwwvXpW3tNSYC/EL DULswVBWDYJoUSH86zvW8e9kh4GPJv6rviHyhg== `protect data_method = "AES128-CBC" `protect encoding = (enctype = "BASE64", line_length = 76, bytes = 32656) `protect data_block GFUOlaXsp9nvniuf9Yj+35P3XFkM33Rly/Cql6L+SVOFmDHwBnnl311fReTRdQswrOQzkIK9mLV3 Y+dA2qHWprdNKpYEA/FKxgvP9cBaoJrnWYNV9lVLg0aeJ5CMyiLrZ8uLViaNWnQcGAEK1EVOh8UL zIePotyeAlUUm4fx4kAukivMG1+ioQAfnSS7NCTp9WoreSpneaw0J2BtIBwDvzO90Km6jK4nCxmL y6xUpkGHEkXeJVC9VJ4GfBtb3XU5LUPMW6BWuNVnTDodSW85M1IVYLcvA47nJsdjT74DatyIgYUs 9zipUpHjbhfo1guYIveV6AOOwzclevEJzodFZNIs6MDOl7Ue1k63UM6tOBgRCSAVpdTtX43KSdyi W8gSSE/xRO2zd6CEtdTMUECMgz+FM0B8rdhfvw1+PFgul8ga9w47Mlr58ZFW6w3gnvpHAXW1yzwo ZWlth4GrpB65EaNMZGfnnMeFy00Qa+ShgUUX0ogN1bQoXO+NyAmZbFFniUxaCvsyhRILviiQPiUM z9joSRDSoKam7aQ9M99HubxmB/uQcJHmoCEmfkeyXp699SJwCFc5BlI4cLWYSTmfbDOmGPqYAsGf Y11t8WlliSLcAjqgX9O7Az7cJvYB0B6F/fjcIl0Z4Qy8/c+9y9NSpts14y+eecL3o7CsTFGYCxts mcfvGzAD4jaRf3eE7U62zUK1740KMj8i1V+dUZ+H9pdT2BOhyQOWt30MzHy/bt1Hm74dX5t/TkQK OyB6pSWgm/eVnEz+sARa2+v04N2rJC5tA0HXAyR4AohGrMuxgbzhVutpRXQ0+dT7+puOzOnglslc 6GSUcdugLQRCDdC8vaeLrPZdyI6FFtxWl0V5XkM9sAVNDWc7rwo5goLkzYqMwdGfXwnmlDOD/qhg xQ59aZRzFo1TUwUktuFrnMqJpiYjES00iA8Cs4o928AIbanp39AgHKzL5g5CWLiDax+O0A0avJtm GDB1kQnIbMHXOKmoIxZZ/RkehaDc6r3UtRYqREaJId46EcNdYFHXUAnJATvu0utFCOcMPs2Bivo3 fTJrFGJboYO987BWLtP4TOQzrzqLQ3cghfIWGZuAAONScAf/4CqwqrC1PxzEPfNxgWLnoCvO1cAm 4v8mkhe6yEC54/HDXzbJIRAVexllKZnjw5FYIgnyzgkGpZv3pTQ8cP+BNMpwL+pre52bX7ZfHYFz Z/v3axxsmtz2XzyNPpHKB8n+yFlaYXt7yLwQLkdOs6xxFSL5bFf9VIlUullom31Lib5XsWh5bd5m VJuUKcG2wLmgcrlVtA0qACulzxVbgznOq3wKISC3nGZy7q4Y1CqKEVUuXvVdJQM4bdlAqUzKOnvF Z2llXnGXMHdNpJnBPYNzd/vdunDO21Zm4aghBDU1ZotyfIKNtiWvyyctK4cxUcJ6BipqhxtmjZAz +pOV1SBbqnBMr4WdvNmon242BUAMsiBhu/otZNFoydHK38NqIlAbXYS9d10/D2x/Cn9XnXEKLK4N hNtEEPDnCOg10GHtVARfC3toVhbWL3fK7jos7yBSsQxtGVzYZqBXvf8bd93J0eWP8eyHYpYeB24Z JUzjNn5s1C7uBNKYcw3OOGUI6iHLC95nJuaSljThX+O4j+HlwRUdpOCNgX2pws9WVa23bVvFFd/F NUwHsacvXufCrBQnFvn9082Y/2nCLZ/wST1gE7blYRsHouXCsHD+Ca+QksQcOl3XQ7PQRYeSM1do TjMAou110MAB3/b2SyIOb9Ue9/qDK4CCUZ7VCxxlfXKlT/ubgVHNJbG9rV+TyHntRFdZjt5IXYqi XzP7iq936Uc+LXXvZbOj2Tw4SK9gU895jH4b3BOwIyhXqrQpQjrAVTJuTuDZb7Z8mHDIhVtN/p+k 5RvZ9iFnh689QcqtGxMD9EHcAv+jkvE4fs3aChn9D8Qstg5dhXT5++NoKYNpEdiPYNYJXKPo2kU/ 1NkgyB1Alp+6af9pSiQF/cCpOF0YrAWGZoY+GRBdAU8IR31+r6Yv7Fe6gPHA9rTvhhUdOG4WWRiM U9nnPUfh4H37StBYotcgmCPEGaX+t+w8QZCsyi1gHKm5mt/AT3LWqhEamXTl/RAn2YitGOIi0bEK s3RrCofyxJJQ9yDD2mzb+GEmhfq6NpjokNr32lDB9S6aErABkdqPY6KDGvgAaimH3e9lkuXHW7/5 mdTDegHSn2eTA52aCNBl99m0Dj/5CNdH7yntyvZ7vDSvoq8uM3ouzvc1KZWwjAm+oWbpmh5bZ7Jr l9laaq7ij1rnk6BoAQJbRQ5hwwBlwi+GQr+yLtejWMG12aP5b1SdtGCFCqiGP5QxfD1irT5HqJst WMl4UWOeti1okuC8PDkPI9mwHRsIByul8KOhAn9Bn9HiG47sr7b/9A8oY9js/SS37agXjo3Fzjig b/R9i5J4Y38Uku4mwYUqjl/s/hNfUjOPnD4VwVFE4kEPoPTqM16rdESFfy6HCl6YiCNVo2sTQzUm wAX3yrUrLsDU357DXZ3n6q4s7BQX472RIkkuyLHyPlj5JoWt19KCqhuSxY+SKLAJ3gzQ7Gc+3xNY +UtvZxy/l9r35kvBExK2ZmMZTYkQIJDkB91/dRfp+HtjmH45UZo0Gv7Psi5JC5iXq5QHde6rNJvv 9Cl3E3gKlTZI346mD/dyJL44mJZ1WMLFAtCHDLRTHgY82n8vLRYvp9iLSa4XgWpnUCp+sphjdy5T OtjC23CERotVZflihiI8rJvJMfwlEM4z/fUqy+7Ii90jKsJJEr1GjQbbA0/EzLkFQrjRxuE348ma jqvx2vA7zKZYI1cJjrmaHEYjmy+0TdxMldLeaH15WM7sJ2Uz5om8ItqtmzMbWYt03QMPeCvWUmXv rxFzNpTCRtDC1hpMOtkX3EX3UsEXhggiit9pycCRvnQ4HbDSQ/4ugE4GObty5kZrpYAbyo9MEhYy L+mU2G6p92qHx9560fpesWTDTiFwrPksBy2i9KJp35q0Z2m3e4MxnV1L822Sb9o29PlIBESXPtTi 73PqX7GI9pUbJJGT4IDGg5pgkvdzJQwhnYcg4UyARnU1xiYdCaBHeSK+HPnzzor/0FNUVcshRV1Y fmM23qJlOfaNE4XKZTby7CLYkYYEDjBzZY3tscXRr8pSwI6zW4Pk9WMr90F0z40fS9bhzSEE6Om0 hG0Q+FBEJdf0Gl5y6fXOw1F6OGyBfvfGcAm8+cVY6gjCoDXLoCo3i64sHT8jRgNbfXCclqP+Mj/g 2UOnDMOhEPdHlu4VNxtHiu/zQvYBOzJobM7Z5fIjnYB1TQ1vsNMgcFQbRvMqYkIXA3WZ/4mBMf7H lfwRg5WlBgaWZOpDI1gLY8NlJxDtzwCQXAyBXos2x3QryjqD9N4FboB2Qz3MjPO/YlSUhtonp2CF uaa3Sja2XFk0qjZM7MEwzBbqt7cDnJiBQMukWgRxnxOKo4oA0WXNu3nFP2d+uko8bpiuvmJUesLC bjiwqELal6KrawqFPKLLIKipReChhx4cs2tM+4+cqHeIw8CYzqRlM8sj1Tc0n+TjtdHorDlkVZM0 1MVMOUrjO/HP2kOD/XKZ1OJajoLoWens7tG89ojmqQW2KtOIXS7h58vYTP/iU9wltq9Skc2xlq3L Byi1P3j50rjnU6/zUHJwiGNvzzFkg7nYkju55rd+JTKkBu5myRg+T8VOTtu9i3K7+PYmfuQBfqYU 7pGjQ9+rn98G+o3IEsgPv3z/lXf+S8npKA4NXWdAZwAHhSyaHZL4mNlJsxa0qCVvLhRlxlhH3QPu IOvTv8LlcjyGsoKziHALm53faD4Xd0YBcXvn4cHuQ1uw8jq9nvyxc4u5PyhK3+i31+rUb+XbM/Sv ewUi78bhNKcEFbFPt6FHYjp3G2kpcSm6HsfLDcn5mBoC+8p4d7BUMuGgJZZ/gmX/0/eOGmYGYjOx 7NNRik3UfdR/UA7ZN7ehnHi+9ld0iHUDziUhU39iEmpdF4Va0u0JW8F+M0bydAPS5+EEECuGpyjo 2JKNqXXAVkyxUXh52aeN1kAyFYTPV/Kz/ZBY3zkCBZBpTgyfYXjFZYq8iB9+drVZYwQrAaZTe8ty RqGi+5YHC6eqmXJxhyGf/I74xSRm+FQrje20QjAsE8NJq+72xoKs8zi5X05lUJ1nMPjWNqeB9MrE 2yL6BsR2P5DbhvYudxssOVPZINBUXvsxX+KRrH+kbr9gYq5+4yE25fPKqfZ/GzquTCC17UQ7ZaC6 wKy8Go/pUZDy9EtybH67LigexrJHrDrgkgXcc0c3t8/jJ3xCvEhZrgMQra21f0J8VtK9iD8+aKra FU5ImN4Usi+W5y8hlzuO+oq0TS8JOT3QpYZCzTGGlGJ1PR2tjkBEjegrdqH17q6TP6+zCBuhVegB 7QdKLx6m+jeup/gyBD+r570fsEX9MyHyIJulVpdz2Ltfwz6V63t/mUM9IR5OcljACsqkdqs1OLxZ 4hNBHsg/TtSeUtRoyBg0ZckTKTC7urRkGzygJV92J4T86ejueXXmy8SRCQVPm2FtIorgiUZPYNto onmMJGOPOlIXjoqGZz6qpu/M1iGybBxUYASxVBAPbogxGq+qC4ITbkudC2wICFBW77qOYyF7G6d2 dKjvMRJU8v2HuNWKAYrtrFLJPpzCVd6yffSOv3ZzXBDQXj5briW9/vQEAAwoGgvrUb1X56ZFBLFn K5LO099HTTUVbdgC8l8c5eZGVdZpDHUNMGi6EJYRVTqQ1SVvk1eJa8M2LGesV/xMLhliwQU+2Toz Rz7ARCL/sja5+LTLXFA8u5BWPxZelVHE70bIfj88Ng8i6t8sQZsC9Vgjmp/VjX+lWlILYPnTiNjv gxAld512KtZqgUHzExDG+u5cvDFJyUIUFx1CyavAzuX3rm9zU5d+5lUAVeNi7DythVQGGmZMy9Uy RLOXO0Ka58TAoN2WufFs/ZXUkrDTUh86XchCzvLMV7tpum5G3kPclfgYTNqtPt+WriS887hX/9pJ oz4ZErpyeNA59ysZEsszE3Gesn2w9UyxXQeVbFgp7+YV6vVBymfGdjoATMUJlPfF7ydF9HZ00fJV f+u0DcjVh57osxTbpkFH4mpoUSn/WSPHD+XGJxmpzupdVlwfqwFKemc6XyIwczMTF6jln7/giGkz 0YRGftw/OCEfWmvtnZQ8OIhG/XUpKyokAnPa0blQoNgY2ppcoSIE6ie1JmMGAy/QEN7NN3LghGs1 zwIdDKjzJjqL6eDc/+imDlYfSn5aHqLxAVLR6HNzKExTUaK30BqZtJjRUe36hTSmmBfh4CFd5Af6 EmO9Loy+myB7ksmZIg2v4JaWD0xoJNiroFAt9i7N4PPvI3g8q0iYNWHUmmAy2lQ49FOzsTjmXl6w RSGxChASJUr8vaUrWVabkzxdctrmIrRe057N47PLFt6GvPwHbsV5FGo9uWI1XnsFjxKTCkfDuZtp s9RsCGQ7NywBa2/JYvO/4bN4Td/Us0xf7ihaZaCtMbFRjWS7Wt+6IjLk5DoDfed+5HaV2A8ax5jX /WJgon3QWaCJ9aglMObF793Qx2q0pxKQ4Kl492tkrh+Lv1c20Eg72gbNNb5ciPVqcbePSco9+IEw MVCp89rCg1ec/vdhOurSrUH7FsbOdxphOcBPyXIR+D/73D9BtZM5w3ooZlAANdI6P37vbSRQs5c1 B4a3mCA47D4setXN5h7br2XUs0nlaqu9wyDR3ZqAfwHP0kewJxTlhvtgorm7JmCxDbanI/ccDA5o 0XP28j+zURJy0g15L6Nkn1FqrMuvVlS6xqA1HDtuIxR0x2IbueGIhRaYyEZj/F5N2rL31XoesIpr nE49CHIVX+EBwoOVoStdAyUMWxjy+cy1/PsBTAhWfeDfh4OPoRYKzsh8gZIVtiH3yU9QMLd2ujIe PddS1dAKC75RCQYCr5tEKbcDby8afrzrzZcB12qmbhsmMFTKspQb/LHAtE21qigRl2PZF9zBa5bp 427bK9Lgi5dcq0fbwZJVYrpVX2/XNkE0U5VzG7u4xxOOozLPrYXBChOY6xgqhFyrCTB3mxnghqgo cYw91pJ1o8lF5t2eKZl37TYLVxObYnV1sbMlG+ghQYEY+b2/gtsftczvyeI/qVdJwSVox9GpHmsH Go6M9zkod3xPTASLx3giE/yiJls7JqEQH5PFEcDvGB+YcsxrP/VIAe2qoDQSGpqwgfJaodL0Pp52 GuUf7BkUEburuFwWSV5URnWD0DVPMwHGUeuB5YgbUsRrOrYyPVlE2EHyMqIwtUV3gQNCj9xfNIcS fPd/VwAmHZg7i7Y19lWzWI7nqLTNzlW3QrGj6WKT6a7OMFDTb4mjGt0LNeoK0GI5M0pus1aLe5+z Njx21lflLewsuQ+T93vxaHIjXwYD7vWRIkAUHlk6+eYDn0E3IDDIicDs+0Sv3G4OSc/4FT3JJnSu n8JNBgGd/TDg4mClXg8Tz5ZtUWi+ievggz3kN0/JEQkflKY0PTZz1cd9XZOGkgLHyKKW5n7q65Tu aLKSIPpYNtLOAGfrJ6FyHTOI7jy/lYdmZUW4Y54S4WpOVEXSOZXNd7l/dZlfc2VhVRh0fofRmiRK m6j1bN/T0U0QWe1U3ARkYNUKeuHSCw5XecNlhe3KxcsGXgA5ptL40PsGLpHMWGV8xbbCb9ccfqx4 VZ73Dqq5usYtLEUKCSprRgvzfsCWk4HPUijC2BYMOTGX4AgP+DUAFTvSB8hs/qiuAtlRO/BJSNkT 0WxMFB2E8DLk8cZMvx5bXJ5zzuoQBPv9Pdv5bvkX3NqcSyQpLjRkkdYFXdDRg6wg45vRhhmblTTB XYecDVVOOU6HHYQyS83x71ytKTdBKiNgn4ght1t9Vr9N559XnGXxxwhARabbkGoTidKHKrD30Y6l 64xsRV7KArCmff8SaHGo4oxhpFxnluPZy7EnBCaiLJsCpmMvIRjsUtPHDsh8v7iOgKB7AHrxZif0 hRCogLUru9+NaeZigDbxg+yRhfFoB0h0xi9ukc7wMvdHUBFDkf9oU8OGMsd1daPn2HXLCZ1IuQJa SawiJc3XRPCaj0OF0AydmC8pI/eqW0ROPpDURY074TtqYUtF+GPFqofNur92/1K2BMhwzUIQ766Q zM3QKBiyPFlLrtuXArrHlaZJDQ1GCM83Bchy8tVAZE6lsVQHvMa6h/9tUIlU9g4ZMhWsk2EGmmTJ O3GhAUOqWArirRHw71JAj22mckaYZObVuk9L6/wWKwHDtHIhiAd1SXFwTeK4NCq2fxtWnhl1oiVG ty0YeDcnDro4zmK0nhIq8LWGGixtb4thV53+hsZBdBiHEx6iKc8/5djk0tFoQGFLvAq1IBo55QNS VkDYfZHt+h2hWKcvgOFzZmNvIbZF8/pLky1Yho624pak2W6Zg9lbWVyqrfhxqAxQ3kyhuHr/+XbL ONng/eLXF4De5VigdOcLKxiwrREvC5SiQLZe+4pxkFJMItqjUVdi3z6YhyZ3RwFHC3qvPhwk1qw+ w4NMtBUwC774HUuXRfft97peLjV4clkNFEqhZloC0BpBiKLqtG/qd3/nfTvxbwit0rB6R1AC30Jg ewu1+CJXvoTTecvDJw9YBhs5HSxUti/gsTeU6XRS3ZB0AKF8NTYL88Z2ot9O7Uwkzg8sTXU4bYAj iDr3JcmlvTIHgWyxGApizQG7OPX5ZlcwH1yihATZ84ieNXJKvbGFcGuxSc3iH0DuqLJlK+EvJ1r5 9T+Nd3JuVSl89jb0y66+XRUKhsDT8nAuoK9RnbYa6gQeyUYt7MTBlvcrLUOaFsxmMAgtyH8pTDth BfIYwHunDqFrgmWsfqEwfHvNr42qvwVhJFqZVr3BBl7CjTHy2bLFgvNMlJ8vqsVVlqqKJhqPYM0o +qZ4hyMfV7cIhZOPAQzYl3HR46yVqOpYUmJAEXjDU4VdvBrhHNLZ2bhqK/K3jcFkTfl1KkAkwbpR R6qbf2Y8T1smB3BqwS8NocdAUPHGePsHcdzfTLWRfnGzjMD++/hBi5k8ug6Yg7vLqfNeunCTU72c LVsune+VlwI8vQGSBoHeiwqAn+gaKdgAndHGIO8oZJTEaSoXVomTP15rDcfmbJ26llTpWNL8cjVm sEChKwgE5PyZe9fiUhbK0KIX+QWAlS2ChAgiXyo2jGvDAnNcwc9B/uZfuTQjE/wseDNPsuvukbuX TFWqyO8debMRjJpjFQcXwa680nTw73SHfFxLtk716fNUaGSJ4Gkq4wNtoHp6bU3IJC377ws+OCd+ qQ4oji9ekJKmzqs5tN07MMIOtizFj2+NRk4CnYEfCeLW+kmqV5sWPaICKnhJt/5D9Gf2SNCJ/fK3 LjP5urLBkIgkolTsjOYRMSjoLxSInDmKiZ2ZFPD4ejONDIOiQOdhhZr/9PBHBY7IOMEHpRbhZ8ZD +sSEUYKhWaGkXaI93odHHD6jHar5Qe7OVZf/CCYP8ykWGccYgkeJrxtrcMuYL+RqZlLZuuCB6Ljf cjTzL9l7j52yalOB0QaMkYymzd5u+hIXUJXtbfm39lEi7n4CQQclHrd0WuefYmwTep7R7Xs2SkJO Atrt8AEuduP4qDfIMa1O5u/pokQxDyCl92c0+EBBB7Fw1pXrEnad0rdh1SkRxn3miXoEZXWgONyL PpfrJYHaEkNWS1T7w8xA36trCdRTsFSq/rA/iRAWk1vITQAyx9xQiV71ZTbAg8ntw8d7wzfBkPbF rRMdBumHLc2WHAdcPEqePArGnzoGu47DoniekD0/WzZv9/NKM5HkTbsaZYPUc84suhWVVJ3zpSfV JS4rjQIiQGQcSEQbVstNoBHuNfiPPK8cMbX/NXiu+AKJV3bu9R7P9dmG7ir8GVnvmqvfjNg8lGhE HYV2V+UZlapgqWj/CLa01p1AWKZXSAVQuACWjn6xFULdUXJ8F7/ZwjjVKCp5N5UbJnjEZADGH1mZ Fy7KRGJKUtisC2i4PF+fCdZ9hA9mC+IXr/VrDKGqHgB6nr9/D/NlFDuKppdKfrmq35PCfiIkuxIl CgiZhOO8IhxAxur7VEILq+MWXYBnZ58B3dBBaHwPFGLRDjPkY+LQA9Rtm6T2o+hkLoXowt3BLX4G QV05tGmWlWQ8G33ltzwnSkjht+lvHo4bO9hE7Hha/1F8/70O+Mxt2TG8tpjo83S428Zc0pFJwaB9 et6zH7JpmYAFWMA9jy7dkGzCV6BB5QcK3RzEYL9kB8Ec1jWKoqhrwqF8OYfg43YYOxRzRF37dUbC /5kD6DZeHzwZyrW7288awpo7dUdBv1ecYPkfcmq6Z4PIx7M60mFVEoMtrygbA8zasM8qyaA4Kxvs 7CgALcC1/Y0yEvyBTHhnZ0J4lZBJHa88dDEtep2G/eFuaxeM2KBzRJQqBe+k10BrEWihCzMW/prM BAaa13grzc/v3R38zREzZ9q1Ezt1WxxrCpqDpd4B7gPTuLhowCl89wo0basrggcdk7cL67ShQcfp 1dRe/fzisiPr+PVlYq6+wMZpO00RsIuDYHMbpZlNL8i5ugpEKlbcWMrZkFAiMYfIEoSUBLLtb5jj Kg/RL96pyaXyTwDtn0ZUYQ+tn8QW8RVyLm9EVgKVSxEANY4LXTNuFvnR4ppEEEURyvimVq1ynnBn nAJ8FRLi7aQyOVYsUqbbF62ppxp11XQVNnCNi0iNzN0ZM+nBGwupJI40W6klrQOYMPaQu4GRXNXx nI/tdr24UVOCBVTUcL3CK3HYWAJW0IMn8uXnnFeni1cYntZelEHd/tL0PcvOfdd4F8Q1dmtr1NXg d6gYsW4itF3D4bU4CFqVYZTTLER6UhwUH2XuVnG/b/ezEgu5aim+QKjXnWTNTDz8FsPH3rhXLDlq CWQJxea5j7CN7sutc18JeplTvKnjAFXr1N7qEubtpHydsPBSLifBDE1WSX+w+hITwWGm7SbghkW3 YYPvb/VdI49G2BKyz7HpH1jQpwv8ZaQbhR9Etaang+elIjqBdywb9PYzz5ya/UX8J+rogpq35YdR DuQCdBafd/ITzev5gZBhfjAtiMEwSSwPvZAW8xt5Hcw1E3S0Tec1mfm5DSFzTDI5Je4G19yZEHai 16uNjvrN+A0Dvz2xIBOPUFwR8Lhjka4KlGECeYXll8CZVXyFsrSQu2fTwc1EtVzuil5cKeryNDvD DDtzroo215xVpPSxC78Mgdk+u2iYEA/N7wQCiNxRLpQdb0ib7D0hiQKRkfmpOdgOroscm5nbZqWG RjshSMLcbPZbSzU9hoo9WCTr3EaqJ4wXuJhmdjxCDet7F0kYlNeH+di3HYmNEU2TYA74/CtcXBIw sYrF+kAFdV9HcV+O1Mo0/JJJeBoZYlNbOxSoBnBj3wekPeixjCwt5XYH7JouqT5hR2opLW1T3/lU X0duslGOHqo592zKYQG4QLq/13N+4PjH12zrrcAZZmPvQw1Kfp81w2esG4rI5LFxssk7Zh+I8K/H XrKKPy4uBu971xpLmRoa7Fl0VmWappV0yLFdwbsyThhsifc+JYoJDRDfHODOXNqiW6MHTNG96nTe D4wBdJJQztmLxI8w5QejTwApT/Hiz+1+kCcymnqLN+7g0vE0ip1JY4T6OCkYvuTsimYwxwsP7Jxk frPIh8sJr69nrOIx8yjmmkTTpflptT+Huakp8Y9ESI57sCNS3zwqHt3caP8h0/gi8ov90tJAkfaE nZkL/J+CBrG2qegt5ub9gOnh2idXbPBbSRSqQFDY2E62ZsceQzIJWF7wP8DtZVLRAx4yffuZWeT/ lqfUM9EZg+vnxF1hxJUIKtVrvUwrKQ0oOgWPVwST0t6LlA13m+jmyRXFwqbQJNQXhpEzootLGNDG 23loWlsMy2g0Al2imdrQM4Vc2TLPOPwHiaGMA2a4VJlTiA2KuJ63qfh/FR17VOrRLpl1urwlAoWG CoYltSN0ozWhZE6bb/9lI7uliXFrZObBJzlDd5f3FP++kivfn/GjPFW34Z+KLPD515gnQMZTqWBe zem7y/lSgI0imG4c/sJjZoCkcrrMtq+RxwA7tZJLJSITpS67SvL7pN5caPs0x1t/b0FkeDEFq10c EgQC1rBW9Oy0LCLFIurbQ8YOmyUxSdT7iBGS7F4uf52i/BS8AdNJoGOsCWSoYFite1NSl3+ZEjd9 vGNKoLWBLfzPyt3O0c1eBfEJhhT7Db4j4Xmr/hPJlej2mFqy9j5ZcQ/TQHYXmMN+Y3lBDmWgGBNh sCjKRfXjTF6WaU2smy3SbrXsmEeftdOY0fey2kbZ2KTx6JNYXeB5SOQVXlya2BFqhg/gfCxzmBvk enudwKRE+dRjF9GSb31xPymydVh/+93sXe6wNMxPZlcweQWxt2cRWvtFqqGd522T9Qq1M9RWdTgB p8ozV5KjEl/J9DFBYod9zSyCOlAhHVAi+1XW8bzI97EqHSKIgI2DBc9uFKez4NL335fKNKafa5E9 BZ+yzlH9/tBe07UfX78xsmN8YkZ8eFP6eFY54x0pAA51egMW+8Qe0vkjoBSN/L6CvhiT+7xm14pB PjGPqGrMd81PNpJXeAgPZ2U9ukP1Ea2PYg+X/8x32512S7tqBVyHUD9kFmHT0jC7gPi6X2+6uGbk 9vzJLuy7kdqJkmGfHQ70VOzOpeZec7Ytn+JfLJJ3J+e30+julJUpfQunXXYPaQMVxYPq94RCtIcd HjimGr2f+h7Objl07fQ+RY9Dp6wL/A5u8uY9nnASyiNs0Z9xA/4VZU/g3b62hqwq7lxbHmvyyVNM TY8rINJ4MQC2rGG0Aj2zSmn0CAivZguyPwn45L+kkk7FO7uLoDP20mlEcvC7LED0k15+COV4rDzj FGFkM4gvkSWQcBgysEIp+lPL5sIk9eWkC51C97O4N/3cHyzyBgUu+5U5hqQsXJIN5dPpouUAwV+k nSfHnrtqXl/XWYySTCcA1xnqsCKdMrpVyzaEZIumlZjHpWmmkFlg7nj6lY8ShrwiVMLEsHOawODO YlvXUO/xHtKlHia+X0n1ZAw/1CzAS3+gNyCeWyDzgKhr06+nsFxqmOi1ioOdSh5Cj9w2EuyyCTgs 8q0XASW/wTbRVBWtpNtV0w0AgCWM2Czufys+uI5T9Fm88pX156Mplr7EUUPpjDYFRvEBo+uHUjHW lYnk84KcmMQaieMcXr72gzeBIg4HLdrfG6iGZhM2fy8Fj6r2oapsWat1y0yW9mi6NUeBA+Gh/JOp on+ZDmHgdfTW75wYLjyT5IPsyJNbyqoHk3O+x4iIrSwFOFjgr8+Umgw95kAOhsL3Kgmo+1M47lTu Do75wvyTtNPUlKxPqPRDtCtL+HiNipZfdXlbKwsndHV4t67uB+35AV5hSON0Ezc8wP42v1R8f5sW Da+QM70ukqd2GT9pNBLxp3mnpvbtGswuV7uhWJXfL3L6CpIe7cttNMScPRLf3q77PK6HPWYCDEL7 z509NgQr0ojk9kw9A44m6EKPpm42Ecf3KipMbFB4PNHsXCIM4YtClzSE1b4dlJZD+rJvjVnR7ahj k1IrSU6IOBlcUvOtK6JnCqVtcCAQdNcb7kW2C3Xe17dkfgXug2R7CSAdCwqzFrPnfTYIS8uJrobY S9ur/YTsqTdeQGNRLWdfB+vZvPgp/Qzmi2rOcWwxqg378559E4M/lGti446Yttn823g2s4lJDMQa FMPZX8eJ4RPwweUWY8ljA3ZfYVeeOgRc8JkBWjuuZwd9i9QZlJWbQQROkSh8ZyAk9qgwnGFpHB8j VpgViKNIVqIF1PowCE2dNKWDuAR9nhyIVR6mFWSGMZHbt5eEXugCVplwTvcHTIkbe0BOgqUuZjmF fqdVdH3gdOYCqZnqigmkvAY28/+CUPKlhBGzjSNLYOsretXbR5LnQ6o9qVNf95MYBHWLYg9Ko8Sr 44YODC/apcouJOiXqkHA/6gc0DOs1YeNomcvHdE9/v4zVMAwQ8BULQL+2KFaLjkVG8/eTtTyooqc mX67uU+Uu6V8vcGT25AgSAyCdud/rSU6PdEs7QOSaDcSZQaX42nzP9O6a2FHmTFaTv6dCSCoZsVi dxIYiHxWuV3vlyMYrCo/t16yazDd/klWmyDSuDrhhO5oUNEc8VRl0G8PYNyy+eNgkqv2BaZM98Ou Edokq0O+5rzI7DhVT+dxHLgJLwwarVgWP3O4mg8ayyPNbCLBbrto3E1kYExfd2LA+cQ6hh4pjFH3 VuUPbMc3toUAM7jU1t9b/KqyQZ680pI8s9PdHuQJwJFld/RCFSsORLmf8qJ7KL7an/dS7U94WgFr KhCo1pgViOeZMCyuTtclpK+b8HWrLT1VsJXpz+gFCBmkTD9gxVvmpchso1uc7R39IYPXX7inJzx4 Y4N4t7uCQ5kBmCPRGQAhAfcRblxqWlAyJwhUtxB/eqXox0R1/JthofmouAjKR/Vt6WYKzGQWGkf1 DxlFy6Id43Ay3pboD/k5jfsFeVLqV2LNuW2IE7Z8QQIsQN/5MIwbSgAa12sMdilD3wHvqNZJixDZ +6YvqkSUUTw6OVPOVBkQPqtAD5f/leGfX4zFMFg/qnyjMXvBbmYsL1515jyvrGjQWwLQNAF2Voep xNHkvFADx/eJE+DfhJGKjJK4/hd7V2vO28jTmq4z2JIjmcp/lS41dDhoweuJUJuERDIXH3Fh6mSU F3kjAlhR+/yOjTmpGucVzWUVjTXsh3iDaWau+u1cMKUvHaBCagpq+d2cHSCoB4Y292XnP+NSXxZj fxoXbC+lzEqHK5nNN6E3Yu/8XTP6sbZ6qbcvCWCgudXFoFukAH3jLjGkR0n+zkRS2D9o330ba2TS s+OLTd+o9E4rsWeB0rbTLacbHbQd86jDuBDpCCcQe077eymRWO5LIRKWsuaXtY010+TdgF9ENFRj LiUBSVjTjvC3J06RVPcfYTvzuftvo7Fwfc8PaRlyy7iYXlACAirB91tJsroGMc9+rP40IMiOcht2 6WiGRbKSw6NQoCFr3HP8pz7vkK/X5aYtu3orkpxj7rT+OSHGkuYaltfCnZZX+gx68p5kaepEOv+2 /tbP7+hEPQjXCfPhHWgC93w1ppVZTLWVsC9Xaa+cFS+Zn1QLANL5YymjvgtR8PUDzvnIifecM+N4 6O5KT9wIW+S/C/zSEB/3262DsaZaUKlxVr0HrkLLfa9Ytrh4FMbhbRrTUbt3UYCnOeXe3h+AwoeR rwkIbjPRQ4GRZaxFlXHeaRJSaaICEPoCmmamGWYUlVXhKk4Snc/28seJeAHAPWUDcbSNP11tGM6x USg4tWC1yne1Jd29OJkqIMBLUlpa0vClcG1jFjksPal6JgKK8TuDmUfWHA2pnlhunS4VFkPd4643 WOPS82eIasxIQ8g9wPio3Q/kzMSzUqh7BXHpttqX97nzy2c2F2WErxsX/Ip0mRBB/bizwr996qm6 HIk3VS5XcgeF3gi9DqMaKz4TpideGvxdxe0h+iguZMnKnBvVgSoG8hTQ9W5GbflkZ9GkiPx5//Uq 13XPzEj4K8WuY/IsfvAallxUyWiJprMF3vHzIXWaIfV+0WtG1qVFfmeAYzxitmVaWaIWbIiID9im qag8BWGzRJcyrNQHI69mCJJlnhtBnTkKKWDrN1ccTTaKu9rx7xen0pcxHMLR8pAxMprSiW+22NrJ TvWgPGBYr9UwXf1NB8s/DJ435ZooS0SwicjybVPNI0cpQ7OL3Gj6A1Zp3UTGs9eXwvrtPmeXEIeS 9ggjkIu6x693HsP0WShhz7UsMnIo7Buz5q6QcR1RLXGTCYWKXta3pS8cBDXYPKuFEzFObzva93gs j6J1vKnNzWiV8iGG5eyo4UGcYrP7eed6QAHX7Yw+6ttYqRJt+0TLDHRpuC60p3O5ePo/ekGuDVyG hItMSZuaPU9pLiBY6zS3jt4moYHoNb1pKQHk4S3feTaD3v+bi8wMQvVk/ONKscr3z/zS0VtIjsOR d6Dhcf2arPJSXdWBk5O3Se7ulG0l66S/jt8+Nl1g2w5L1ZAxsd0wvKcNO1pexCUM14/xZHF11t/U 4i/KYDyTmD2KWxmXTFhdni/HwC8qYDMw+WssfjpEdXP+cJczMDuHkQoiwJF8R3SdU2hV8wU5jM5c /ixvgOcxqZDMjpn5bhmRACXQpe9GAq8kceIh62n2pjpvSUIxXq0tlH9bORqarNOIGFXOp3uG1c+9 GGkbQWgHZDpqkM16RYR0nH14I7uXc7m175Zi0XLdAy61Gwg/SzugMl6aozcsyNy16QAnNT51wVtj V64QN1sCkpAOer3qSM167kgCULqGrhHCKD4b0U0ckc0h4m4lhYXsOjF2k0jCRfwctE+LlWkxAZpN 7lTPU48/1642DRlnbOh5+c+mAi6K8T7Zd4faltUtPGvCeU5vEgwNi4i2CkTpKiYm3X9vY9V1SsDE JNPEouQNPaACWx3LvV3I+tn0zJMoIDvYRlaNzlXJIkzQmHicMFDtdxe198R38B/mVYpaaCz1gKAy yAl0Hmn23xjyIXbcqZ/BcBo4CuMsGm3XlfTkNoaqowlZFBnzZTVao7dFcgK6Z0V8a8gQTNTGrsPy gotaWzCShbQToI5DZc7CAQpl2moxOv52dgf8LPyO/ivfdfPRCy8AfBORXOBAKTMDNXNMoAPn/LAy LjOEiqj1Kk4gRbond4byJajW0Lh4RoglpDvQ1bBAdXpfOUOqF0U6oNV3E27xMsW2pFESh6N6oyw8 XWpSz3yHHRnWXnHhnLAw798dBZCK+vB1rG1DCuu0X94Sbjv0Nj933c++H8dmEdwFmNTWf10ApEW5 cPEBnM1Rcg2aS/2YLKsOY8R38Omt5T8Ff+OEPmTOhh9F5Xw07Ysx6V6G7amjKhV14JsAD3wwaOiS gnHbv9es35KdH3YirE84/dEajcs46rvt/ZqJUgZWn6veoK8ioD8+Qz3l7yZM3OnJlYPJv3OcsMaz B6QW8sPKvjuxauc8CTEsLoZjrYbfEGFv+OhFDYtmKr75reds3+I8GyMHiG7KM7rjUsT6OOecq71C K6bR2K6AZNoFjuBfBXWVSZWXJbobGQtpomRz4/9iELHPqL0VyuAMfsNr0QMyYBJ1SxrQa8GqLdE+ Eripbq4ZbY1FO4ItwMs6zLwRg41hlXaCe9/7E6Qw7aT1WdzaH5FBwS/Qts4Yvno6igvgISNo5nzm LUGKotCuVwDuqyxS0c7zlN2JPG7lR9Bsg+XB83R2aDEhQym6GABLdOzNYDtwvcyVdMJ1Ko8KzhKF 50oB+PJhUz75BauAD0aahAAoYZd3DdNTIRsBFAp/F8Hn9r2vNAPRNar8lEMGTYhdeuSvAQTLetaA 79REFot1c/ikwoQScl8QANUfR5SK+8H8Qqd+Sp9TxgwQweX78hdL3YBFomG+j8nEAkFE/2XXbGJD BcbNCshiN0yEsE5Ebfax3lbdn6jB4eGfdsSfpW9SP25covyEvaWMb/nKOO3OKABsZyl90hEdgG+Q 0A1blQm6E9n1kpripgX87Ynvf75ND1t3kNrelCgDLj2ihFHw5BxWKaL5pR0uT5uhE1q5FvCN22Fi lD3wcA0Bm8NDBrAPNTncu9xikv1HT3adoRAeJkYf9HjXzUrsV4mwqw/g22eFw10ZBh3gW/oBh9Y1 Avlt6+d74318pvXIMebYnrDIsGDXQ7PBtXqTz9jFBGDuocfQlEgJwCP6CYc8DYSjEW5PwQ3b7KCO CSmKKmw6SsTakTjVHL2CV303/vwMPsiZ99FjIXzYM1zvSuHYMt5pmWftQjP0BvAg87Q6SFVwSGc6 hbUnctnYILcifEt044Zd6lm8v+Y/gg9tdtOzv/fFa/O3Rll7kDQ9BroHCj6Qln21I8+S4Rsx0oGv jhV4HjtQGrDoq0cf/KxWjnh9blXcW7rAUXiJ/MahVq7VGWakfj6oDgAvT4J22sZ6mXXkGCeStk0w isNQQ93P38201NuCZk3ha7Awe4Zu2keBm+K43Io+x9+yject7G0IwMQKO40KDiyjmixpSODYambf L5uGKIOxzLW8MH12M//wnThw5nzFy7vNfIiCzyqbFjML2y28z5ShVC2ZkUqjxtjTW2JFymd6ix+U Va2Dz6F4my/7xjQAr/bE6IUQn44nA++owGd95AH3XYwfGCaRSBi+Mm2v+alhLXTi+o7sF3YxO9vU JQbBFmdekFsgNQAfvinvs/u2tLCTzcy9GHPiySu9ngvb1yzCsCOPS10M8phaKCuAFYE3UsOCrp4w CHGrIxd58cRUgXrkDZ79cDIb6W2J5a25uQsaYmH+IFCbKWgi1szvYNroAZiey17hqsT7s8pd+4yF e57B9oIzu62Xbw673lj0YikDwAsrjhSQwpOyx5S7yC3BZVliJv2l7RtE2dMwqN206gBDAB3Qb+m9 VWmue4jW91LWPBW+hB1IcXM1GvxWUcdLVgTbuBevfyfaj8fe63hM4SG0xbuRTPomQ0WaMDNkdoHA IEvZbth6K8tf9PCgWEB1d+JkvMCdDxXJj2F2rEswkaI7/QLslLQs9EJVhDV33aOiiqeJ2nn64w30 YvLv3n1GDSjOpqmVQLn2btZkxJfVvX5abhwmyHRYjtoaMYNUd0g4AH52ywLS+0sDheK773yIb0Kk Wkj9BknZ4A/eAR2Kon6K55eAilHKFeBDfilrzizG9uKgTM4BV6k0Su/DRj5cCI8NwewtNQB1SgJY 7xIE116oqTA9hgoEHAaJ+UAARLyKY53GS2sk+kiPJqMb1d3AmmU0qQiozXG0hjso4jgkXqgEf29V puVbvz/vbCqqfb/nRUIvSCkhAjxYWMNJcPp1VZujY9tl6EJk2nxGDlwh4TsiFr4ErUT1j/y566ls uKB7g/xsr00+fG8B7+Pt1+MEdnbfzDTOJtohH25ZSsF/XwiWf6O7AbGUUAJmGx2Ltr8mb4o3QUwU WljsBT5d2NFT0dFd3A9BkWRzGPY6XsOv33tM5RRB2s9dviFq+obgEO9qs+Fuv9l4U9cvKcZ/16pX 5XuWANKDD25MHpGpGtObgh5WWAC61AS9RXuXLCAiLKHx3X2iE3JXDHrfL1ACK3Lf/8ZCnqnF0ShL 85Mg3qeuE1iIMWpYjTfqnF40zdFF4N7e22ybIXVZ8RIfif80NwDCFAvPA6xngtSnkDoanP4A/0G8 xn47CzPecoiHSC5HHIb8Dy82vGn2yQfsOQe6xYf/sAxsRPWt8sz7BKIGCv3ysrrQPm4uFDQuyCBH oTi+l4y/IXslruqkRvOcPkCUzpBHH0wy8N0wSxVKRaF6qGohzt4W4hewFdjgsmn0xf8k4VK97/23 e9KQBfVK4UbQGbQBwP2LUzVclV6F/HNG8BWcBp6nlh1iBwMa/5oGVU4CocEVgl9/HKWgQczdgrnz 8KWSHQLq6U4JEpl183tHYg2LGu58jzzzw5fgVVKCj5wi9RkMjdy/o5b/95sHwG4z0Ww6TfrR2LOH HTLDI0IQ/xwDSf+l+7Mb9v8uzDFaRYwzppostwuwRFVWQa7HA7fUGX4maIdXj+rmv2ijX3vCPvPr Uq4sYBuj+s0Tw1CbbV3fLIJ61yw4527eoXX0Syr7EnBvpqRYpbkjtji+04XI+cQ9VFFYAI2nySmE TrmeOe8VffrIXjX6kBB7d9JnLmX0gbaPPFoqpEX9PYdEzJnG8ncfjzioFtXbzerHUucjz78ibwbt ROeosKcJO9hYovz6Z+8xKuXA0onCeVrx7UrJa6SOQFLgp4BqD8O94XDxC0t+u6sQZWmQiVLKc5Fb YEElTOgzGgXgw807v0rslrfblJvQ7CJR6HyLceCca/6s2IEYy0dssJR5kmP19C/GQoCypxFt0wuG QDMM0dPZci9TfMfmtGdFzoGu+A3z/6LGdfIDjE/Af+2UcF3CBCGzukn9OWyL9SZrXWHTlFE0ReX9 RDwWR6tI3iimaiEPdvwm8eY5XeR4E19u4JfVc8rYTj3cZHHA2Sa+Y5y4lnAOYmgcnyjPOGaldEFX u++qfX9NC4k/gu52wXSweS8QxkEapUZUMlelOgxt3fedTjka5PkU56glnBHPq74YCpmVHCKslE9t 9WP9mFgJ3ZN7TkiVNRzVT/hCBH++QO/Kw/JToNvZAhcsyTYcuxBJmkO/Vkw1XVG3NiVMf+v0d5zI CulzFnpfzRwM8xwhGnh43MK/NV2tusY5eYXkr8vAnang6tl/skwwW4wdcjYPWQps39etOnb+GL3l M52Ha/6aFEw50tbX1Op022TnAuKm18SJSHMmDF7MJceoHKPSd4kuqkzUo7ss97FNUyZA383u5bHh kTczjd7RZDDDdaz53q4GGHOe6jpz1HArxaSTxtEqbdYbjvHrT+6LiUi3Czr4h9mckHeOHdgyYkXG j48yqF48ZKchEoISZclVbDZ8YPFUBry5ndhmV+ydRywGXi41sVbtj8V0lerV5XA38I98i0Rf9DFG AB/PtN7GQ+h/iyFW3TA+eNV4X8Vl9L20321mg1vEYVUJCkORpLWfzrX4q3wJYst9w/GLepI4LJxz nH6+TPe9MJGRm/izNpygvauFghAUrCLhmdekq2BJE4cCXB7BySfr5OvSw9M7NrMaBpgXZFZrZycA 1s/rA1WdF/g4C9bihiv3k4tFU3eMaIbPaSgMg58UGeWf23qXcVPWFY98jJcalPyLRh434lnzDSr+ pQfRAKulS5Fdcb5vZwV0Sje4VKuwaTF0aHvPxhX0D/Yxi4AIWJgCU01HparQ2002ahMbQWJ2sGxs /jOJHSWzj25EKK7Oa3WtMRAstGyWsPq51BJoMNMa46JR+8OAsaUCwgCAO/6RqGvwchB/UlSEvw8Q rwrpOMvMI3HiSc5OM3h5vIn/ERNVMgnteuuO/ORoA7/Dlw0JQpECMhEJNyn/nqXrEHXtfEN1CrLw rqpEQE8dU4mKQSU9TBSDx0bSsiZg3+zrGuaiRZCaphsaTWcEUUiw5QyGXVpPrnYZ2mMwp2M/u6Zf 5JByqUg7Vn9M15rvmNQ+H0T5/gSV+Fp0z7jRdBG+jVsHEvzy2s4utee9LMNaKNLSzgfVuJ/eXc7j ADa2u5XeLYrsrxmn0V1Nx/RDHVgwD62r3689PSlcEaOy8zIO5FHpFciP0uED1ZHhoMQ2jHuwS0bR G81n50Q/xJhE9oVWWh1VVqvlaXC4SQ08kMjRHu2gc7PxkTGkf1YExHs2pR+NpMZ5vrSHwNEYY/Ke /ahcMCCa/Atotp0Rty/fCrnrcyiJEZy19gOyRt79NVtP4Cw/m3cRmxiWsUZuaVKsfj1BUUkPgQ6j 56LN9u8ImmOUG8kh0DT8tuOvdLaP3QRtEKZ06AuV/A2zARXpWfP1GmhSkua755cAJX1F2hZn2ZnO DKv8w0Q7unNxWgGHvw/mGXWvujIIE6sDVEnzWDvgCeg3jtW6XCVyBjCkNLrGQgkHqF1Tw3Q4U2I4 R+fvcFYnMnm34qg7RSKkW6WEB6bk/I6/mf1YqIdxoHAUce0BjdcBMAGSbFp0CZAjMlkoX64Wpbzx KXAfYZR53bzj0xfiScwlggnUwiEqkKuIYmqqCC2asr4ySmUu+Auew1tzlDHTImLts+v3HqFBKayg W7NBHR8ypaCkBRfL78vX0RMW2PwTxQOIV5izOFSFpTfWx2NsUQRkRi2MkP4LcxjlcoPQz8YxS8Bb BHFs5ZBw6zO1rTKchQfQ4G3l6CU9fGRy+PeZlQIlYsR9JTnDUgweaYuB8XY5sbc81F9trDxOiiWR G5ip+aK9MBh8Ieh+jmmJKuvjUVpsNDO5+i6aB/4++iPW+yuX+Ws9buucz2zYw1EE9zJJeFhYhIbu aLw0yB4DN4FkyR9lR+MqW/lNsMJFvqzIl1KnNfQhiUX6T+v+lOexNUoH65bQ1BDxdzDtr4IzZg4S m9Ua51cjweFn3U+7alkR3v7RNAXNGoZYjvoxMGVRER0GQ3nitKprcLKZ3hkG3/2UuMIyOsJQwNID 6j+Q0CWApTqFtRA2zueCFmq7dW5gJCmHyCGqitZCcSdH9KyKugJrkzNi5sNja3os6KUCErlX/W3A Pzj/6qxbOEnuTCXY5NJqp4tjxZL++zfQ5PCQWUUP6yLS5JBo77SU6HTVCvVb3+oUY9xLeVv+JKD/ ENIgYUq0bbYbHEiqVWM655i4P8agto5Rd39Wc12q5Kg1qx41EJLzBqGmKn4vwOOu5dNporK3gHoa j2Lcj/e2Yra0Vk5h+dUIyikDfWLUMYcFLROM4zGj02N+fTa+RlGAXcaJAWb+oVanSqnGCo+JTljW 03w+4CA/va5FlBdkfLKkti8lCZD/sIHsWk1vjnJvVIpsxSxl6sNoaPT5e2LldOddgUnIWOCPPQG8 YEcxMxIasK+y6jYVc/burKncR0wq91Tzc0lwiZE7nr4cRZQwEG8But/AEkELayQdVAdlDgpIe4Yz SP1EzMD7q/O2yaLzsw0KJ8PwYcuF8jw4USH8vLTS3lNR3QL/wQS0yW0kb75CbZhWEqhUC/MlRjMF /pOVlDYsxgD8Jj6z/GxvRzS2ov1sWZmhs2s4XRuGe1Dprk4qZ0WlpOdTdO20xcIgFvdcmSUtvyVr urdaV9tt84QYCB28ZVdNwJGDF4mPWAn1NB8hwCqwSFizHucsn7QDScppH+6xF/7LsD6gRmU6DAcH Yri8CbWSEabKBN3mlhZ8uv1xE7SBIsdQzFd/mpU2jUzOYUwB4IhHsglOa6Krh0rJxpyhXjwhWz3I dzu4ehsXN2Vw5g5YqBsRda8eucQZDOCzkc19W+1lc63T0b8m0NxcvB3F0kVWnxjbl+vrleUtDG9/ dbSYrk5vyMBPOywynPlAmIizsr4JzziZ1k1jRZKIJZBWXAg5eq/aH+kdGdDOmG2i47xZMivxPxWB NZCpsqIqy+H6e+FRu1j8Kbu3unpuskd6H1s3IXHF9iZmRyZ3P94sX1m7Cwu7Idkp8czTbWj4NJsF UuSLSGTCfLSDJj+O5mdlRYwgfDirFu74KFoO1xZBxMhynJSg9dSKCatLrfd+NIHmyzNWeSP071uA V3zujN+EEj3mGyOvkerUMPd6JeQzhBS+EudJTVPU8AQWnpxAXQo1x2QEaNwBmvB+K4oIbZ5LYxbX lhkaDayLf7Il+9ay/lAUqaJoYk0dvkQLA+eFf0fP1cYoC5UWnZ1khE5ouEYn5uon1oNWGEqKWf+X eDD1NUOSnksU8taWSxjwbuN1vXU/xxTYAoUhnuP2vbswcCQLYpYC/8lsZy/yEd43r1+cbRbt617m WAmauE1I7gCQyEEe4tbp0py+q1Q1eJQ90N9n7lZxyCn9D7Nj7k6WdOBcgX69Tb9m1fmEWQM2Rcg1 L4BiSMmMF+BWjyZTaSNY5vEgquZQ48z69fnuf7aMHGZjZuONsinSIbzI7D9NvfgNR2VM35O+Rhpr 1C5GkTVABZa+BcPyrYIF237nvoPq0sEQlCukfL0pzEDmnV99EFQ+JOOpLcVmmchjkAc6nnxYic4X LW6PeY1MaNS+3OwA+xKHcOqDe6670XbDPJPha330K3ZjARShUtFJrWhi+7QL5l2JCJcSJAC5BXFG JW95hWYELLJQ6tydScMxAzpALLn1egNAcdvEIf9PMeE0iZRlB9IhuirHbjkdWdSDRcMSagBf+QRd OVZrnl7AYW8VM2/GEch3ND7Ygk9arJGmp2eRyy9hpG0NLc71WDEjF071pp3NdzVysQsuGhYgkJTm eXMHZ1wNlLR7fyb6gSlbBNbGvtOBYeJzS1kfWkNNZKSMGJbbVdE8XZP1dNtdHku6NsitSXFWAUoQ Tj8XzV1EEIESqMnaBXTK+69bn13Sr7XhhNcKeDcWZwjrjRmUsJ0RRfyyrdjscPrA5HcSaqCjpHIy mVvcHSFuDaoUYz6AIhQ0JGlcD9EclO2Q5Gnx+UZ+Ss8qUDdvf9o475V9YDJtVWCK+05hshGWsYaz ZY7r0yu1gDs+KS9HSl0VQJaeCxQwvUW18AhzXTxCMKrmGWe5xhGJw1y/qxPT6xgUx29g9EpGR0T6 5+HpfiC2bWilJSDNA6ZC7MaBXfPSQYs9yGIp1khJYR2Y6AniYqw8gjYCV3WeME5IKcVf14tJbnUr dUYI+9INlz6Cjpc6EeZYyOUF4V8fBGLJsnhTTi+/kMm5bquuzSPagOps664X5ibI8e0hhG9ioO9A /8NKInC72LhHJwJR3uzefSDLOl7Dg9AcB7HYjWFfEMHjRfJ8hXe5L/Ro71gMeXcod73/xDx6XBXQ pVG7p00WQnkKvfuXIDz5fDdfo1lmnSD3OfPDcqJ9Zx7CvBhomRLS0DsqtyA27fHFbjz/nze+JnaF oWNFUNZtZrckOFdyOSIo5c8RGK6lBt0NRfFCgMsweXhObAeAdVDTYnEmyrf5p2Izr/Gxcagm0dOZ IKMa07W5NKIEur9wamaIAEubgZNASLIvo+p5SuMcEAmodkerty9jUZuGhKbiWIYjS80BmS27QS9z jrHqOHIF5aPgjj/luBao86GQRxcBnF7CWwZPKdA0MDjbgHIuWyLS3tnvNkbW663wkm9ie/lBg+X9 l0Pbtp6Zxtg/U8CFcMc8hqI2y6hV3ou9qHaemym5Z9RwLGKU6qETFCq2hEYrQRt7Ftbef0MxQZQt ukwt7+VGn3OhTBDBTxmdcc+XvaF84OUdWee40ZwreOW0Ld/05RDeql6blwq9P4RNFnBjn8lT/ihv 9uHU07wJA+h2rC5IgTmrlr7n5/Ow5p8kt0iYdzEJvNZ7oS7JLpTwXzbjK2kdNzPMRL3+kWtLiOqT t/YtvJw36523wR8KgHj1zSsAzxMl4VIxt01drDtxjy1ScZ0c6VfpTGopo9dx+sRWzLPToXjFeHkI /lw6qLgud+FKeTJfH17IcQVtEzgVDGeqmYdUtVfpVwgPOZRriP2/cKCQgXNutWehzQg+XS6p9Spf WDD/vBZDgurQ1UDsfQ/2EKRCfELM4sZpjD6ilMShWamJDDLUScnWI/IDeYFHWPwH0bpHoaubO3hJ ckB6YRIP3OkmkF0jTjppfYTUrFKr+s6GL0NPSwmgdj9jemVGUfvEZaAdi0W1eCmRPV8F1sFpnbU4 FSxpMxp3asf34T1GbGMhitEWvjNN6MaWE6FQfB3+FaRkP/k+ywgVGbeOLSR8ba5xyYdTXixkGWED 5GZFzPIl4J5QTaDV9EMtU+3SUbF63zYQG5l4Fpf5MSIG6K4iHXfsJCSAIOIVSZgNxZAyBmfCgzGO 2acchpmqdt+9FsNvF/gRjVOtRQI6mhAI8k9wCUtIAXP2MP499EpMPI2+QXiOA5CEqfCGYbM71ldW UxXEHC2SI6A9dYtvQHLDjStg2JdLtmRzSknGl+v6nV3sOdkkRAnlgHdUmAUXfeSkI0c4Qjlo0LhY +KU83nt/TRFXkTaUCIqEgfgbRFD8MANqTnBW9yl244J9V0C1on2BRGpvQ3kg9D8GtoufR7bhECBY jEi/HuwJsLWKgnRMGjAixRJR/DgKCE1NwDRm17XCUQqT98JP33qzXIhjrNZBh+fcUEOIiZ48Cww6 YS+Kp34xBcHNtD6YEKV0hJG7qlCknixO/dACI9yjFSnuIqAin1MFYkHKchSvFjBLet6pYtj2f87C agYl0BBjoVomGKgKtjmDTzEQ4phwa+htxr+kKQT0SZe7fgmaT9RVU1ZPoZjpXdclzO71DtznnX3u cWopsJ6afm5xaagsXpKfmVc2MStMsh4rrqZG5j2rsfW6cuYya4ChkEShHy1dNi4VDXH8PAyoidmk cZVqgMri3mr4aL1X5M9ZkjuBfJr3GCZnfFRN8W8f0EftUieoz/VR+V5F6iRRseE8dHqqL1v8Lek1 ckPkabbXORP5H09uLiTBSn/Ac6RyUfIO3dFUiyK1VeHpM/OXC04VkqbCIUR1MVa3U8TrKYJ5tDe4 4mF3Olr30WBu0nAIUDPOZrGGo610ZgpiOmSe3GShE7X4acBUGeU3eS7sThxkA3f1hPMlGON5tZMp vG8wABxQzcGw6PdMjunGAryAIE1tkTuGUtkz8NvUtl+PAsj9YPBIGLv9XU48ARQOcQo2cNEOrAMv dVcPlH0zpUfo4mEt7avjgNA79sDftqkAkK7N1OWAVBC+a39XE5XglMjENczYAcl+O/QZwm80UaJV SPCtVl8c3ZITIZNryGMuL0Lpn1RjQFrPzpi2e/bxJj33+mbuISwC7cmFAFeTolG7NuNADL87WZDw s6dMC5pX6z4Tlo160tAPIfNO0o+ls0Hzjx1JiKIr43ScveY2lENC2+NirR4QgEcJ35XgGNGjLpYb pdrpoXKQ7TONLu/Zinaz5UF4cKynrqc36Zzo+BwNLc6adUoHeOoARkfzafeBQtCE+/ncSaVpKbQh 3VZrekcupyS1FldF/7Jb0SB+VX6Tg6jYNo4XscHIq2qrWpJHUkj2jqYrpe9wJQLquW/+Fz0hCM37 vILmJaDwLyqOYrICoheox+/GKBMNykuUgGusK00JRZ7tdDzGdRvDNSJKk5Mi9vpzJugwABQby3Xz BtvrWLUpJsfwukKIIRUxVxeVkJG7FRQEr8Vt03lLb9CjhxpFRk+ps5cid6URx2avtxRcd3/ky7E6 oUfIgC0NiISniNVNsxdQhBliDDSbAGKc+GR9ck4CJgDj59JyBpIY94hpKPWzXGgIChYWC/hjuFz8 eG4DVomHZ9P6Tz4cpwEt82HG8MvMEOFVj/uPG6bZPu1lfS9WMIMXhnb9OiZvvhyio3VRQaqHnN2U 9zedV1WQ7rwSceXs4441UB8liIqEmYwFTWs3IFwaPXRhMVZh7e7TouElacq0rv6PnbE90j+jMaLF rvsVwbjp0TJ4sL3X1JokZvn637AEfj++ybOBnHQFo37ig4tzel+psE+aRSf8FmB+nPrVXxbVqTpr 9w+YSfsvrdOGX0egG6556bdBFEspMXjlO/RUQL8UjAJpcWZ2cVWjtr04INiBLrgQORSZbMSjsQ8w nU/s4xu5deXzVQ8OAQANT5mL6Gmuq2Wm11BUeLRmCzMguBnLl0Ok6VIgvROuYIjrcyk838GCSl3b mr0+D19LskstHRgcdzfbBn4PcdVFQvnQ3CM3gbOByzpDZdSC8wtn6XTL38jafVFheF7ghahxEkZT uE0kJD/312YYpaYpGcqUxUjwazU5pN5kK8vj/HzUcgLs1i8fhiRD156Bq1BPVlYAUkSM8ANosc7S TglZ9fXuh2l0KeXNPrdFeifM5BJMLgPZ+1MdvPe9LHYdt8ryH5DMw5nieKwQdsyKSClD6VoXwDet uCFceCNhbD/YtpelyXCRh5e7I+WVSJM0YnIRd5FJTaWi5U2SMHTcd1Rad2PiOaBRzUj93MdH/Bt0 183CT6rg+SNdx3rFLsRUYBrFnjkLj7gxIxV9uoRQe0ptM84WAg8HK6ar9eZ5tkXdIZYzKno6ndlk 4zzs7HcXsZt0m0DCXFMyhehk1zA9MUTKFTlmK+fzf0JCHnmjjNQkcMDBWebUcuGhhtpmpUxdvID/ a0mzznaZQDpdx1fPpfMOGxlNOs0YC1rXqp7GvRnmBVtCoO7GaHH1ZoO1PfgHlBGj8UgXFGavVQGY BE1rVnFSUa7lABa2EBeEhyDU/wgk+B6m2AUxhN9O9gl39E+qeaDCKSTx6SpbNGCx81I7M6E3IniT /Re8SWc+GTAjKxmugRnZsNIh5GgKy1OiFJ6YYyib7FldhOfaqUPIa2kds0WwnnzuoPm66NOAWDbN wXtl3J9sALO2FrfrDmQhCs4P9u/DTdGcu3NX1bQkRryglppX5cs59Nm5mGmdR88ihpGo3v1F4sAO Ap41lXSe3CWSkKydGqLBUFsF//egpZ/dLIcknq3Q1rQJiNgUiptd999CAC+YK72pMqqQ12xVz1Gg C3OmsDOSW3VdCPsSnXg2lgrfsJb8wKMccPioMptiqUkUyZFQcK+gsww69M1W2FcI7LQUs2/6A8f9 hJBaTFOW5Yxo7IddJ28QJaJ6k4oF5diUXjRgONJWBiC6j9Bm/6oD+7Qq+3G5FDcL55fDdPj8Wzu4 un60Jmb15baFUxy0Z9rhlQ6mnwIp2IWy5O9LAFdW82sMVhrJ54I+9MRa/l4Vw5br8GsRxI60hGLX sFxeCq4Ko4q9ZZPB4tDE9vnJWe9jr4BDg1SWshsjJULNzANMlwKI0EfUhS8J4W195jcWVuJNgHV7 d6D0q20jRmxp2FwXhsu6CgLfxZNQco6+YuXgowQFVcUOkGM9SHb/8f3eKEQkV5F7KbM0ehiN3BN4 T/PuDSdqYpXWErlNf7wQSdJrC2k8X4gXmwSVqjmw2ggx/PF3NVJUl3H3xTXYghOabSQREgph5Jy5 LFvmCfBdkOd7U6/Um9Z8UfspPNIkW7Sh2lnF2Jhw3okoQ0LVBjxeUVHApAlQSm48QyN1Yrhs0xw7 RDYWUN5ZA07uYxBrJuPibNxfCBa+czfQeBDG1DGtPHm7wxXmY9M/5SVeSprVl3dqsQrr2gCphI1n +LHhJexN1PIm53Gd4ULcGAxubGL/S+mfDnyj1bV5LP5/FweaghKpvJYaeco/Du/ToRbDn7EsQf0S 2hlvV+Iv2RnBEDtCsfBLczQRxQLPTxP3yeqrHHUIfTCLr4IkEvE5mkALVjw0P737dM6iFKCHQMvc 1a8JLOyP7oFzWHYXmyDDGpqs1R17FOTMYyrMwQu/EcIGDy01/zH1ewF3vGFBFsErorcjOzPHMyPA 4bz3B/3bS2oFj4B4XPHdJFgJ8Vh3yiWuv3bZQq/Fm6e44vlr8YWALVzSu4tXj1Qhx26elmqoE+Kj ZFr/8DL6iDVUXxIn0ujJJdRE3Yh1VXlBRiWq08cuYxm4OpbLevE3qcTFfU5bTadh0VNSDqcF4VQj NcpMu2y3wKdM6wDvtQ8YEnkQVtHeb0pxYZz61a3xPg1mZB/ux9XmT7LPaqA4EVfYYOSZxt93/Uo+ 5NX1N64yiyEmNk0tp9KAdCJs7QeqQ8WwzgSglqT2skZdlxwkB3w6Vtq4NtmvZen3ulSHLJ3aUEZs 9UEQjukIv/vzBKNhtwpjw1f1eMZdpD/0WgJNwESEBjOcIQ30bNrWZ2qcDqIuPTGjf3grZ/mA4VHl T0buC+P4PKEB3lxzh96dXPFPfRtpCgKDn0aO4l66hZINDqZg0aPLtJ9JW1KJmJiqIJla72rrOtAr UfI95nKMNrU4GUlIpbJT4Ru5dNushZ8wQFfHNnOWzX6ptPD0kwwhzq5Ho7k7h9idLMCPPibb3KDY 7X1sZYqUuctuSiy5a2ByBXJ68GdPqqA9EO+coGF6GTMQ6VOgsfWHTWYOs2BQy8Bf8xR6f/6CWGGj OesMGNDuUoUlRIwZjjWSVVSX803yPauWAYWuYNPPFXUKxu7+uSm+GJlOAbyVp9RNwlkm9NRr0YTD MrkTZRgajj0hnYgyEIVSgjbBAGbx6/EklJRXxJ8Iz7m5Zgfc3rQvmF8xJgmFu0I3/nx4IDtgtq9d iJWYbD0CpTYaSEy/YNMwa2gQC9NJsOLmHlXnunR/QSnQOfw7nn2JpcUF5vRa2Sjo9m+nYnZxepO+ zmn3WpNKjVA54x4duOaVvG2xKWIQMh7wEPMpOtbGEhlcIcTBeFz7Az8UzSPuY+hL35Vw7CXCx0bW VA6xFJ40KGMvgMFOmaPXmztXHbkIUfkdzTwBmeHq70J5BQpU7rjWiqKFitAzUXX1pB+Z91j1yvEk YkgjsP/4kjPknl3W+eczONV6dtJE4pGxifOV2ZqrAr2r9Zn+PVVs1NogynOZBF46sjXs2CmqDs6+ QtuZ2c6JDZPNq8ZGtss4TTdK/L4n8VckGehee9bgBD6oqOyFZ1+wNthiA924cA2WJ5JBTrBqr+1O BFUXq0EIKEATAYPhMw5W+QJaLlxT3ZchOHFygqHp+yTH6EbralrHfQCcknda0p3mugku3TiRFbPC 3LTioRaQaEZY3i9CuxRVJ8ppcPt5zr3ek79BaMfg87VnBSsPEcK/uWifDyuZImt0xTob23swyxkf Yx22/p0dot+TqGV91dPdFhreSao9aGRDYn6F8AJKRHUrSNLC5cX5Fyqn8fcqB2aIj+F9iCsv2Jo0 u1xwek+0GaNcxV/ZppMJhHGCWlh8w856VaQzqUfRkN9bqicnfSo1zCwbNEPXQnPN6deaNL+dJLFk mwqOemNfVYeQLRgL13PcXfUjf8GMzEGVaRtgJcLHRDPjftDxflmZ4JTcUdGG/RRllz6n+7APyNAt c/LluWO4CnNKv194pv3twb6QXuTnsLoD1lG7q0gGXfOP6mHYF+W994JiSblhfvQ8MRbIWTVwcKVn kO0yKQfObTs7OSPjKNGgMBwUYaTwiszTkPxkpOYOtMHXTIOIDp3XtfGHX1mgide8OciGBnsNWshG fvYqw0GD/sH7gKO1IMeYoPD+xzkREDUMG3caOSrVe+Wf7NUb57QQ+yPxO2vinFEmbI+snnNX70su UYG5wy49DgaDjPmHwKZ7l9PKVwYUFpUWeFVG1GDXOx0brNFiWlxJMgqpn/wIoEUQZqls2j0NgOcH u388Oz+JBlQbEuuvOUmdS0wGVbqVpNetMCOvSIcIh4S0QJ+d/M0OnjWTUCBHLBKV8i1AYjAVz+GZ pV7rY3sFyW13lpEKat9K2HIcLz5pkuiE6VOsqQyy4LVgP6CiNRgdXi+FHRz0D1gs1mPbsBt4n8yP yelt3oal2+gfTV+kshaf9Nf953ErX0z0HFVGY7Vr62odvMDUBaG1rFPDYnrSjHDX1kxgFa37m1Vz cgL05AiOwt332bBY/FC+Ym8NKs/QwTXBqAlRP+lpTwA8qYmfSkeYXHA/4FeZTb+LGlG46NXcv+8X VXg8EMerb92hTWYfI69dHPonmzEYLXPile2dN43VKMiyH5B4wCnTrdZNsJ8OOv9D4qrJkIT8ulS8 GtpB/1LYrS6aZta0oZg4PDI/9C9gtCnafLBYs8tpDU6j2YMMfyW19PfEV1GPs6RX9UTjRuzuOs22 wVwfK80SJLRDqHGSfuHlrv7+yPHA4KTqNMapytLjPsaTWWsrh6m33KmnL6MXtSFejOc/kudIz8IQ SfN7LJSM5W2sGTZrR9mxc4dDFPd7QJg0VEqzzZgpvBYQZ3B/GIhROsTTsyp3mINJbJIAnPA1nUST Zs3upQKkFSLKk959ccdoLxDaKXIpIORm0RbzrRAb2Pgs+022uQaSgQQqrPgf6rZ6vinzjqeEcS3h +43y3mciwPf4W9CBTG/30MFzwMMVP65mSk/GtWPJV/Tv+xc83VoV/A0Qvy4OUVG0SaDPFifk3ksO LnFSM6UbxobQJK+V2E8Dz0qGmMHueS+fkCmvuFZFhy159n2mgo69eo9odM3pFr3MlMAxJGELvsLN 6oyuBQYBEMTtTe8yQ7Q/Gv2rVS0FBcUlVqwaiq4VUlWJCc3N7U+9/C1iwgml93JpbtQc20Vgg7Dy cmw29fP5fRqhHNvPtF+e6SPAEugQ8fUYumFJn5zjMWjY8DEU+YoKWsFhKEj8TghFm2GeMztynpke /cUY/HxoX/T6FoXmZvb3Af0ZlP6m3p4oagFHREOYdyElGfOEukBxkHhDRuXhGtp0ssjtJ69a2zYP gA8NpF8AtJVdZuu57o1Xt5P3331mVTP4gMILgitlL+/mLiQo6LolaoqK/oUcbpcXMOxK2Diif+lF YpH/z6vvLMtf5QV7VRFcz6tEt3LwZ+bXQ6AiH1mT+3O4zFo+1Zu0hWGkos4EM8uU0Gf0XlMBLoou Iac0bsWVBYopmfbpLYcBNdkSoCsCZ7ToMCZ1sWYP3spgSJPCg24whYgu3rLfWT8RKE8I+62H1hvZ BmY18HKGxrOcqycQTxX1x2O7FP3ZYy5XuZXLZLxUzkIbxqmRSf56NsA6pwB15ss8xBn7avNK4omp s7cRqyT7Ik7mM8Q7taFJs7gys3STCqMhvTx8CJB0eMbS1cmbmdvM+kEv/y0yhvwcyK/iIoZ0dqBO sKYHNTyOUHf6xlbDMsClUShhJ9tqZhEZHTu8eI7uHgcLp+NEdrPxr34W+ERn13MFpRWTPWue5Tif /Os0Jsv09u/K666JAmSj+83WDgfIt1SkgXpUKIZ7G0VxM9Y8W9OFfI4cayj14MJWmrY6EQbKb0Gu p6TPaypchGSuJu/D8Dfsg60WrmlAnNBkcUdlIp0yvzJksofFS+Y39fdfLXckh4GHENfqbn8LCcHy 8XnwuaHUtGXBxdgutXXLn0X8vvacxvXiY40QgONU+W2R/HPbVhGijN3OVC+9bb/Om+AQYNb0Ybsi gYHRkmu607e+JQFjN972t7a7IXqYVGkbR4m4HENdKy6YMV7Gr6bjYEGnn4lk5c2eSRmH8Caf/7AH TKZrrny5MQwqn9Bk8CtOk7iGDh8/Q2qXpPK9+wZJMVh/9QMhc8O2Z8l/AfJGwDyA2LfBf4QPhvw6 e6UqAqyJNnIGX/0t1PT1fdw2laYrSxgUsFElOpvZRqjmx2vXvHC0R7DO/BfJnUQ4I1fWHoAT3uG9 h2f9hsKyegovRteavYDZTVdqOQoFAGUKJ5JIdAneduFf4uEbR6pJaraMo5Z1Ws59YlUVaZbVMRqI KvF+TXkTXJ7El/DeLcBE/o7Ai67lR3+YK2KoNSDRZZmwf0X/3UzO7FIPExuQop5Hxmk3mQCM2oHb 6dFgiQjGxCvkeSN1V2fB4R/bz8BkezfNKBgL0lEM/PnkhdHefAfs8cgZs1ZNUDk0R2laLUqX2EdY ZJjstGWCg461biBhT/mBxXxa4iPJIX+qkhEIAEM9Uj3g6/BNbYdYZjUN2zxX6CwyaRqV6K2/wqiF 8DA+ZdH526WdsbPwhAY5bessQoFtZUJ3AcsBkGqdgVi5aJB8EBTTuHc5sZ50fAH+uXE77VHrx2Gc 5dnsNfTLwd6SL3XYdeSyh936Qhxxwty79/tNCX/o80CrkXM3B3vHMZ/UUXT1OXxk+o2uJd9Xo+JA GOWoVJyOXRhlexl3UZUmG5tvj5BoKxz7bcrdZ50Vws4llU1OGDVpF3u6c6viGhqlmQg2SMGmJsOE jV2D70s7wf4NzuUEIXCfCTkRTBI51I419ckc+mNVB9udf8co2sXzZnWHUYXk4Dsuj/fKGpO8m9SW o8TetB1vGzX0QhZcE4PZPFcgSwZ7Cp4dhBOs4NR1E58v8awbBQEWo6rYeU1lDAXiXn63lfhjPv1x KakrqnDTB30O0tVwR8tnTFrRrbpnoNGZGzGQcHd3IQfL4vsJ9uJAULaUBraA6DDRNK6JvPdKvAzs Aspvk1uMqpKiZKQNrKfA3mJ/v260StH3qu6c3RH6fTpSBBK7lPYnL0HMDa4krD+YORbLbfVoL2Ni qzmLaV+chAJz5UY7xcPqaUsl0iC2pRIT8esBH7IKlB3E3AOBubaBILQYHJfD2oVnlqPQHiTuQCzR Dt2kxqR0AEjuIf3cBCubEG2oE9bdilaPieizBUeoOhpWgdRYShugnn92YJdaJYTZNKT4PuhYNoUC BqWzMzf3tsHoTMVYOg5gEz+ijh99CSjkDFkVuAVjxPqmbUVsQJ6VBx21M5sfbUG5tqGS+nr2VKjp wF0dv9ONvCGHWhyDE3gqM5cHn1SeclhVe2dIBjDoL1OHDzV8xZJSKzDDNfRt2uiZIjRyc6myp8Wb GRkJoGFsqGMNSC+fhHBXAD/xtzUdYl+Tw12doHVyju3VwufBlk9eNnkUgpZpMslcLV83cQC1vU3n ngw1npoi9ZHCFSeopN+7CLmcvLVvAyb9xg/DcO3DS9P7FABsDHDrgflwZDGeIlVfsjACfiEKExwW RZb2FcG4mlQ0xOjj8A3Yj9tvqbkHV3vNhy4V8W79Uqd4Kf1xrD8CtPk//jxvLY2bQGVbh/EdlTV/ 1bd9PvhVGxQ6T2q/Dwva8i2sfW9dJyoJOEioI3OZQWAc9Axr9LZbyMO0Zraeai/1l5p8/BT8ffrG zU1cWpfCUR9Ka1O5DqB5L6IDwt+kfWe9FqyalD3v+jMeK4V3uXPKY34I+QFhQ0XgzVJaFmilLGfn RN3JXgfgGMeRWbgeqFFKF0duBLdeI+QhJaOUY0mIbRG2A/C+roT56vG0oWAvEjWp1tpmpzeowAbf MX9UOkA3ppgyTSHExaMRqtSPW9boY5mhEtL6J2rlZZ6g6uqJG/vi0bWBudJWqgEMSw/s+gl6TwSm zw2eafu2W0dCeQPAGjIo6ugs4UJHZ+1HUE0uq2Frw8T+NJul4zBFdhxiTcuUzKgysHHnMsVth5HR 3ieQKVZL4rA0obtY28Ivp+ndgDRHEah4PXDf1S3Wy3vi7xqMFCJrLJzGy2VKXyoMd2U900s5jr6m YEWwz4C6877610Y0ZhPFw35UC61JUI1gg9SasUGJC8KCnV5pnHMrBPaaY4VCjTrs2ZkQ9gortswI xopyqG/NQ2kSDPvmnniGcvi3p5W67O+HsHB9B0a630Xwt/0NMNifJAdITDJ/3NctS3FcyB8WJVds PvldVBqgUq6oayKvGtcbeDOFwoRQYBlKB4iVIQDawquENIcJXetL9k0iw96IovXVsVeUTz9Rzldz D267XNKZm2fq4nNnBwropr2FDvnYFUPssgOYXJ4uxjgV9IWvP8d/ILYhaoIjMCMxKnRMYXGx23Jc /5JOd4WKnDSuwaU60o5OJhdsjN15YiCqPwM5ARHCddFPzcuyed0a3qH8UJ93765+SoYAGnNuO9LQ H42ZLImeTZbWgwamXcYa3ELeOWJdyP57wmhlfuFSei5nds1vktleXQM85InB3eH/gHwJpnHA16y1 eMsx+NANuFrCRZ9JzmlapiTUr4l+XfycC83K3UQKSZr1YvGngSgpSsBu6tMwl8s+ZhMqrrlfGJ/N c3FiG9ANlrJIuU4pisHZs2UgjdORiwVL4IPWkfOQSk+09tN1WHToc6BSwUEdP7+cDCI/kXvv6oCm 4vuPPKScEFv0cFvwg/C62PxvGipEnC6nkPpaW6lsMWoXjar9OHXeIgGGVOtyvuOLLjPlbWIDK8n+ pqZnWTRwUig10EC3CPSYtRk+6srwGhhHe4P2hgBLdb91KVweayoCF/rYT7ra0KiXQIqsz8LGlWzx O5xuI5/aaO6cNy0NURJDayX2Agd0aVB8NMMjqrGI3594Rhj+LoQZ5F4lb5ugQDgqDsK4pT6f36b4 cxeKCe2exvQ04F80ivNHuO5ywPIn+n26mRbOrIs6blx7Bcr1XsnYfSJnzeWaBpmm3spDuorEF4jk Uj9bUKMZGm/2pWDLZNwQTcqo2CcqgP4ZJDvYkZuEQl0ubefintDn7YTUwra3/6lFHv9CJ0ZLJdvK VXMQ9PnsbqcbQMKQQsANXpR1hmn2/rcX+OK5mG1v7oeg2JXgSGOTi+WNPz8Iw7Zl/sq4yJoyKgMe FEvPsQwLeCDoEbTLK7LmUUZjbw+ycISUNU/0Er9rEFA9Ax3635xgddBu4gKR3aeaaOLJpIVa7X+J zyJtJLWlW54XMpeMnuKrg0IaEKMeR8N0nCeC+DVOO1QeZjycyevjg/SLNP0bauqwacULCc5ccGUD fLQYcL3fKeppkijfeo5nR3jkU1ab+1exr07Oljs4QnO8kaE6Fk+/5HKDi39yGXY7xyi4IqKkB/FR fT9Vv+ZPi4HvqdaqQI+AsorFskkff60DGFWxAULsuiVX+rIHqQQZggwT21jus8gCbHYpZpw+Pg/y Az95NYjgjOlf4N/TfoMw3j3Gvsa6HflUPYDPjek7Pyaf/cRWKEd5Pr5hZIKlMzl5NHUx3sR0ga5x MyvSnVZGkZfEgC0A8IamHgc3UNup6N6XRk1g2BLYndonKg6oTrALIZ/2fAw1NND8JVYWx6h+HxFN uD8DlZJEwfKAm2tmWVb3iGj2fNg6OSRHWOjKzCN6Dlk/l7v+n3gEGpkxWWUcHY9PX8HyulNpwJbU M7+9DK+n4iOM4atss6sdh76ehEkJaM1/4VszkvIRLFWiFefkwUaeHzqBLSP+pewNKm5baAd5Rigv I37H/tIKvv0BwtnCK5+/GrcP/NGk02r7msbtINSsP16Ig/Ey4dH8Ydhtpab9cQ0YNt1QAiEOQIhq B7y8ZCc6TUwWYsqRHKa3QgcO79Mz5qcsmMaO5Mco8NBnkNQ4j+pBnrHHsUStaQNC65OncP8rsTFX +lNuUfSi0nIk54ONAXse3sq3j4xS2dOK7/1w0fBLglNlVDGzU+AIAiAQxPP2ftwr5won6Nn2HeZN ZLnA6eKVWZGz3GYpRd/wyI5SSZ/+PJh9NK1nBr4O6oua951K0ruaa4ufOkzEbKiEY7vUXwbGLAvk abRXlIxt4S90miymWfORxegVYSqFqSiXGbGKzNLvYvNdQO0k4o4LgD2T6H5+figPwidihXHFJRCk UPAUOD3xrMgNTHR/y/eugZG8/lLzKhWNpUkHA+O0O8x0MTLak4kAesYvnZVqA955KoilOROgcGIn I2tUEQ3xmoF92r2sLyYlSlMwWVHLBj33Ps/Np7ngI2ebgI4+JbAnlPHRm5LB0WH53XyDNgLaNjUf qBd2FKO856qKqz7uZbmSocWthsJyePdP9tcb2Ps2vDwJgIC2qZ7eGyD4kUCZOIi4QCmPyiXMEcxm Eqav2r4+pdb6e2J4ZaoQ2Xzeh9akIxxl906YoLwPum+Sblx5vsMqktGPnLeNDnVm7BP2ZB44IYd5 SxWtWXHTuspwrdX2JlITZ9QKIazykfLVh3HjnwmYROh0rxv0qXnNZuX4fEK/wdnEz/uyd8a0WmGO OZeEmZ/nYGWMIFlpBVAQWANuOyQkktBO1DkKZEZTVFaFaPZXqipdaG2lDCsTauvWBAiU4jMaD03+ VFgUvwgtvCNYuxRyJcShO4MA8kTkNQi/J8Xnuj+eQlAQ/VeUTAJ+5m0gC+xU6k2aAoZ8J/OlBwiK wT/FkuLADHLRQTYip0flCVrlB/urySFdaArRAGKFZPNFQCWmuMLWu2oP3ERAcxFnl+cQNFjzNza3 lwv7F7v11D1qgdSPwl91A8VnB9piVWZm93UCGdqvx9R9IYOXJ6y94NUZq+byTQOD0dZNCj+ir/Ps vfNE2y83Y4IN59HSY54aC8Lj5K/MRXJYwvUgmWdbpu0FY9RSPhvD9TF1zkfn99+3E5rm34qhP4Xc tYzg6VRAPyxaWKOavHj92IuhLxFC7axapIjS2oRfMqp4TG8YIuAJffRH9A38Yrmc5B5C1gRBXMP3 KQMwvTIiviF53mi+UwQPf7jSvzxtsFXxEgEWDoVdVZUUjq2CRMNpjf7uN5qyS86eaSxEErBwPphb M3jh59q9t4hBIg92EC0GO/NLQbdAPQhrpXxrwMXLPPCd6x+kkAN/a6WxUgLc3Vi4E6jjvoVoFa1H 3UZxy75d87JDQlq1eJrZjpxao2H6FpuHrc0HjkG2cbqtIRHGNRAeBNIqKU8UfGOgGnmp0QKle1Gp +wQuHBYDDMecuC7O+u8OjnBTWPqouq8cC4TkfpklpEzxYFGGRf2k9aEU6LUEEbu+lZNKx1TnSeDP UtEeoMkupnZsImkdKDFNDvZdGSPCqjyVOfQjWcNu4W5G+Lhk9Dy0taI/bNCSl6MBAt9aGMizR5Jg nLV5r1f6yK45uNgHuIJxHJ6EdCkHlxJHbndgMycBaWcBeQMyLvkPqqSsjYWyn03qd2u7dtI36JUO Dw3jZpHW4XXoYL+HmxQsYMROFk8M2eM9wTo7cwVE2AFZZReC4QDLiuS5daEdspE4Ofh+NNw8ulMq mi8ZVptmQ7Sk2TcE0qlRLI3miqeR5V3VaHXkwa39uErBQxo6LZuPbS9DJCF3tSaWgOCLOkznSRmM TjDsLsmEb81+YcTaAp33leQ4RKQuYOlThNdabG4sq4YsutJil24QhQft24zKBwciyE6Smk0kAS8i akCcRHbSagVg2fixaeRgaXUtjd5yBafnbuwwo94zW9AarMPTFnw6pLNEfhlWXibriMeKPgwuoaCC JQryXsIhi1pG/ohrDOI+uCDEeZGcF5sBfE0ogPYmc+PZeJHZs2Mmeq6FFzGCWUluyW3DYedY/IgH 0SRGDj3vncD0UcrD6hdJ3UPqHt4edeu/n/JczYUfKYWqN/dKMkLtiupbWsAMfVqEGhkGdxb3EFfw RoisfhlcPB0a+nYoYPdNl3EThL0QRpzaWm1Sk+iv0aPMGgX7CAoKtB7PWK88SF8KD6emrh3m4PTt y5pCDjdvr0ceq6LcRPQqS93qLV78JwU/IP3R57rPHz3l0q7s+KrPial4XAabtj0jJsMx/iJAPD3G EzFw5sLt85Wfz6Iij/wWmCD4W21QvLPv/UKumpe3yOjH7cF6AWNbXnXsDxLsQWPb+CYLR1m0diEn K7lQRloL2wBxne0DdGYTY2jrRskXUWGvTkkTnq0OmIDamr2fXWqQ4fgs0trZBWEgIIxwe+sJHs/6 31aIwQTf/1Gcb0hzVfbkADWNDVQisn9BzAgk5l9A5W4mXoL5kMWOqwrk3FgPFai3xKmWA8wqi9xD EWaUhmAvzuH+iB17inrxW4tmdMiSEC7j/MkiqN0tklwpd2wcmD6QzjUZhZB5f/W1oQdxbL1YswyJ rjsxtdYKQhQ6XQAsMtAcF/vRqlyBnVgT9nZnNjf+mlZnEz5X23k5df4oTq8vwI9Vn3Fn9JjZxOU5 U/R/bRSN/9KMp8A+qGbwkGkBADU4lK0FmEb3pPTLlc2YzCncGJUY5N+RJbgpXzI4SSrPilWehQA0 +vO6Xu/no3tH9pVwn0ms7/vmQB3FizmlcpbyDyRkUP+aCuq8qFTc1EHGN5y6e0c7nMC3uMU/tkV3 KeUBJvCKSBqGH74i0SruFhvGtNObYK0bNqZsjrdfP2JnUUMVgVbWWbviml1ESTw1vR2RXOq11zY2 8aFBut2cI/MjG1eBKuI/joEbNdd+v6yBWJ5EbVJszArzRfaG7aQatnvCRuhws8zVICochza7trcc upF1GnbDDBSZGHiMIeak7uKkVNdWXFLqRsRZc0BKBYyLn7SuW1GcTJaYXm6WyOpIRbDaqIOPibhO zN82IebEK1FeGTrnKODf+o1Rpyx19Jdre+q5SRZiimyFJW6BhlpmxJKKUtPYCija7CWWJp8UeZDZ mbfwDVUm5W8OvRCUjYMTyTRaCXKSZtg3iyEClbBBLbuT7abgaN2ZqXiTx1G26vO42l3qdHmXPE0I mOKOIHm0sSAUQuEaF4ilwwbQumHOUlbxXxbQrdZBVyo/QhiwEB9/WlCrpDU1XeT2oenh53+8pfx+ XE1XCrwJS9uc6hs7Svx+SR7lcveY3luVqun0VEEHc96K5MNUpWtqb1SJ2bdSuz/VK4c8szgTBBvv e1rbW/vJYRv1eX/JAgp0DmUdF0HlpFAHBvDcmRbWG/EH7nw2EbKmYrtwcRABHKKJfu5Adxc1SoVu RHDDeX2BXUFvwhQavw87XPmxnbonN4JS9uu36tPUX3HMDmS9FiF4+/vPifNpOMrF83M4aceuSiD9 2MeVpqO0rPr/TRaQEhugICfJpI5K4uFfhhheiE0HxqVdZoTsDnZAz2USwRaX/zxRS2n+BHmywe7W Biu6OtNV71MniyRrzeM5xyLJDOODQRf7xSX40okDfuTVgXCeP8kiDSZuYG2xuv+Ok0t3N5+293NC +gWEoFvO9pIN2R2oP+uvxBZRGA1MUlRy2jLXKNkjRnsfewW+DwUN/Mgcnfua13ylDO8mYUUxFrgE rukjmMaYKNzgGdC2KgTMeBUWCwNkRS5qQzeG96anMp/vpb5PgYnvBEmJp0xcdzwT7T0aJZE9JK4f cTzB/wb/2f1Hyvt5RaQpPutcerC+yrbtcOKhPvaXkhr2uqt/L9vs+8NDSqvM+zTpT5E16x5m1U6p U2l/HTCP3/r57oyJ0CKPUWwdN8WuAFWAQaOLdveqjFAQL67nfn5OWfxgAB7u000EdsX6VSSErglH Bx3uE9PbeKnDqBtkAgdhDRVnKbXLGtELyRjqY1wBcAjQU4vSrItPOVySabH5W2k67z5nckGLsh+V onik+UjuDf/AaY1TwiaiRxqCZVhk+HQDlvKJNYhzsooeM4kMEyWy8QcHid8YERYAb+ds5GgTjJfE ZldmerEgQN9dKYCMFhKvAN3q2EpqHHFqoGkoHT0+k075jF2G8yCKy5nDKFvhwnCbcgDG01Rkne0d tHfH4iE3DWj0ec2d+0n6P5RE54YKi1b2TpqXvlA3sLm+sq7yimjajzHH3NwsCnJk1nE4PM8v7JhU rumVlxs7gT/7ueiCgExITcJUFOl0vfsybo0rikjS18kEMzcvKJyfr3Dmrztz9xHNjVsXNP0Q151M NAJ52mRQl/lLBJHz4GcFdub7bM7AlCgfs3/V+keRqR7X+NcZYBSrYRQQkzMOcKMYpUK9yVP1iaZK /DdyVVnhIEraI3gm89qTXjMMyzirxZTUL41nAZh1mjOKIcJm17gYSdDnKMeY8e7SFvFbi82sSoUd tejbVSGgJY5Xi/m/rfW3OORThdtqnk500DzIpAXGpHL76/2VoUDQJZd+lRT9uNvJ0q3IRgbvsydK HnbbR0hoeya2HBThdJvmmS7Izl88I0Jfe/BvA9ho+n7ekzx0dC6tBPB3aPF7o9h60ONeJR7s6jPE yjUcZyrpkqbcRPOqXl3/6JuFFA2QY6Jr4Rm3aT8zcJHnnW4Kc2O1tA4ph8QQ2V2b2NiPobF/y7L9 yPcN9c53Awou1LASbU9bybG7/vieNSRUzLain1BO12jgknDjGfz/iRChHzE0+b1Y9Tqjk8AeYDTL hn+3z4ozvfS28UW1oh8iPENmNuJ3auPVwyd7iVuk+Lst5jPYEDTRBOcEye7kBEUybjYguX0+PEMt e3sbDcaM8JNQBJTuvebM8zr8oXlPNuH4qOY4F4cN9poj9RTt7NYsN5FBbo2d+R6IwfPkBG4NPY8z Ksoc0ThhERynlR03PdXmW/Z5eEcnHdfeSSAFC1OXtqRm+DHcZcDFVfudVPnX08iH6kIld5L/Kt0l 34gLMgh23ch8XGkEwuWs6m4IMe+fvhYHk03CUuhVZDy/UibHjjI8Xgb38by4qK3YiV1dUIF86I55 yhdKdYeO4pFsEsv+ZOr3IBcr35/D80E3SGghZheBxy1PUyLonnI91CrNOuMHwcnGVeOFwr56FxRE 6fnYB9+7IrH0byfFs/g6Jh0/XObamX3oXnGy1EStagl+dLw0nkcFPPQ+wqOfuUzZ7y0u+ryi7/Mv GpvFu23AcXpTm4CboDDNC0CJ/cx1s98ico2YK1YFKO1vX8yNGHR9fhdCCZrh9Pn6zgnbdMgRHUoj qVzg+DAZD+jSWUsSOSPrMYWFoZ5WJu0WIQCrDaO+dEkw+W4EQBTYGm44szr7drSfXUyXbDuv/W1i 47qJ8TwH9YWOs8Nk7UPtljwO97Oae95mjBWGzLn4SVwSrBEnxxwWuZLDLxLbCmbWVEPy174KNZHp R8S/mHSyc7PvWDjOjYetXi4b8GjdI0FJdP0Su8KepkPtMfR3K8NAGyDVBMWZZDqWJJ9IAqq8mof3 cK9NW60p28ljapPGHcTWDiWjjLFAKa+baUBlBjqMFi6CjrXLbmNdkFT3vi/2gzfKdspSNGMOuG/k Uawu732u9g/kZMH4SKsAyyqUTvEDdXnOZ0mEDM9Tanov/5pr6y/nS1dErkSg3P4mcGNveFjAiI8D wDjuNI3chGR8TXEJSL8Ei84HWRUw2TdZslB+bypmZUOhBhGRwr6BoWlmOgBuvYK1fzB+3fa9S6cK 4BA/RrL8dKOjbyJpj+8hnbq3fCPasv76mdEX5T4lvg7qTEC7LeJtklMF4Qenb8VrITIKNgMKpEJd RdaB3YPqaapOC2yoCi5c2H7BPmwie4Spkdd8Hm6u2kkbvEgxkAQd0WjjwCizTUNCxl39a9KN0AP/ KSIj2RRZrAQiflHCzeDtcn8CZSfSetr+CoCE+viheBImLOMhfYKEaxtQ5vMHfhtWQsb1r0ma7Lal pVfqkn4NCfEqjxWPfcPWXr0k3tKpMu4MjVyNARdzsbyDslfwqLrbUvcjoK7pFV8RES9+gZvbKUb3 UGzAMalwNH+QoHyTjZ1y0IPNH3/JonvSr+vC1OiTsa0TYZvxi5sEGGyANKOiLUCwP5tVByrQtLMg PJBYaAlCmegS5ncUxaNwEFTeZO9YtB4kdPZyAcHyivMGS7j5JpiNiH0BwlNhPg+dN66T8UjiggBE vEAnfpEhHiNmVjLe18lre7I3Ru1qMEhJjjeHN6BNP4fpHUJhn+F0EEyEb9zM2BiEltzTJdajIVko xLkFSQeBa4gF6OzquOCQfbhiFxo4fFvvIpBHXk0yg5aRw+cbZb6Qk7crr5YgNJ5D5D1VLtprnFtL Qr0ZJ6KtbQlZWbYXOFtDUeu46WdTSCASMvnkJyyNMbUlJxePqtzAZOU+QZ9kDe1JhT3LtpZsPB0r AZA6gvYlvf92JZARYVat0TfvnewSnk60zpr7kMQco18Y2yGrhmUFmvPsFtI7ZwDiQ2boTKYB34T+ SqVupvX5EO5MTDvJHJ0tneSLB1yYTbjNDfKTSaBpqGkRGrZfBywKGjn9H7m+BJlHqBqDRrBGs+2P 5ltocpVG6JSCjbLxORw0q4/j3xZaAS70gq7HUzgAqdzHLx/LtWn93xaZyOWChQO3+GUXiObWC7kB q1Qws7842QIbOrAl5w6NE9iHhNf1pQl6iSHSonsxAA5i780Zpeo8G8SUZtDNsbfmV5H8QaeYd4bD eyVlixmdN1cZ2e7XNdgw9m0OLmJgg/lyPN5PWVVc41ASGb/57DZNHdBh4iqOPmupx6PDtd9z5lii 6SDTLXUY47QCHsebnsuE8UixphBK6M9jmF2IE9lqI9LBxBccQPXWXuGNEv5hYGxUmmMpNZP4ikmt 3U+a4eWiagMCrwwpJtbvw6ueWhT6X3prkQQMyhf/F4+Ug9az5WkiuavEDEMxHWHCQjnol/puuRsB e+ghlOfVgmoMedcLqB0diPA+Y9XyqbeVfwDBb2Ewpd8kv+vTXzXqwEu+jngpiRvvXfaFfDR59PyB PXKlsqLJ1yo1CuEqHsSA/XSLKhH+sksPYp/Q+typpKfmHSKksZXvHkX2elAr5VhtSLPOzF1us/f0 e/kJhSnhK3ijgU4byuGgsRaO0GahHq1iqj4VeAuwE4W+9I3ICRC1Fr68dRcwBX3WWyfG/VoQ4reB +53JuWDrN22m5GOh9z3iQ21jc/oIJ/rLBxT8EnMXrEVa78/W3kGQrq8Z3riEdZtLFqHOLlW34964 ruGwj8qzWxSvmT9G87wfOnDM8vsSSYo/R6UHg9Y8o6GpkWisxxcXexi6dSq7DY1pD2v9slVbqCWl FC+BuKaoHcFjA8gEdpYIudnQUIYFyJrsfkPh+rACguBzvnL/ORQ7UXP3ryAAWpVNzH+kaXdazCDz ry7xFyBHMYwPB5XShZAzvJzt4+K9wgb8rrpv3B5un5zVHi833E0zH696zNsAzaCabMDQCVq7LdWD Zksl85thw9drK1j0yT6eIfCCiEeeN6+mdvsYPcr41uPPTOQkmpnDgeKFKmlkQNQ1c6pnxVMhOxdE dJDGqNL5J7aHSrHsqUCQfJdG6/sz15m4AaOSNSWgf3HxbY81FG4ymPFrhFtnXnu70z49pWa3vG7c +Y9JM4pfz/Va+cYxA+OYpinLh2jpGzNcsgJmMtfegfJJRmH634Z7Bh7WU8ACTxAIWkzjp7BK5w96 hWNdTZ+uhie5Z8E7l8ukFI2YyBjpv43Rbe2vxVZrl8wI/bpfW6szMSztwspxewzoSmkEBbursz4O 2qknI5SiONYDfUdMQdHKPlslq8lA8mySsshmb9H0jh/NQZVGr+pfdEqnbup6IFZ2O+XiouifrXOi jkRgq2zhdm5IfyhgXu+4vEXfW5o8OFZjzJ8Os6B7XFYFzrvBb+ozYvp9nv//dKQykHEv2XHbciXh +EzIs6YzqJ3KQXD2tfrxfKDTEfixz6cX7qQ1I/4thokmKZZQDib41iEiDmOW3vKNKovmVRsyLOW+ ktfJbFxsiyig8Cymqbnq4miUmxjzosso33+cr6cDP1ELmhDDiZOJPV4WUcxgpCCCZaGInHUcoYlm bvFU1Sk1jBOeFl/u4KaXh8DiivWAH/bHQNJaVuumBrom0k31Nc7kv/hxOq5mXwnbY+QqDq6KkCo8 bLdjb6rBbT1oK144x2r9NFRvl58OB3QBT0GWj1AIYMgn8o7WqxeH1ADEWvVIGxsu2RiNCU4Q1Hys Z6fnuwo7pGX/J2gv0azltitQWT6+BfeAwanmWQcYE/jSdtB8Ju1S3ZEGKiC4wFvZNEgPDHUqBCSp Yrgygi3OahV2z6NeRMsZChb4H0rp3a/LKybIqn4a/7/cSuHeH7pgx90wCEY163PNWof8oyofaE2v q0MZNUvDWs8rmtTkp8e6OaRGp3UVQXzWW+fS8Ni55LgX4xaSw8XU0LHYcL/U5TP6p+AEsw== `protect end_protected

mit